esp32tool 1.3.6 → 1.3.7
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/apple-touch-icon.png +0 -0
- package/dist/const.d.ts +14 -0
- package/dist/const.js +15 -0
- package/dist/esp_loader.d.ts +3 -8
- package/dist/esp_loader.js +174 -83
- package/dist/flash_jedec.d.ts +2 -0
- package/dist/flash_jedec.js +113 -0
- package/dist/web/index.js +1 -1
- package/icons/icon-128.png +0 -0
- package/icons/icon-144.png +0 -0
- package/icons/icon-152.png +0 -0
- package/icons/icon-192.png +0 -0
- package/icons/icon-384.png +0 -0
- package/icons/icon-512.png +0 -0
- package/icons/icon-72.png +0 -0
- package/icons/icon-96.png +0 -0
- package/js/modules/esptool.js +1 -1
- package/js/script.js +4 -4
- package/package.json +5 -5
- package/screenshots/desktop.png +0 -0
- package/screenshots/mobile.png +0 -0
- package/src/const.ts +15 -0
- package/src/esp_loader.ts +203 -90
- package/src/flash_jedec.ts +114 -0
- package/sw.js +1 -1
package/apple-touch-icon.png
CHANGED
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Binary file
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package/dist/const.d.ts
CHANGED
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@@ -56,8 +56,10 @@ export declare const ESP32_SPI_MISO_DLEN_OFFS = 44;
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export declare const ESP32_SPI_W0_OFFS = 128;
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export declare const ESP32_UART_DATE_REG_ADDR = 1610612856;
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export declare const ESP32_BOOTLOADER_FLASH_OFFSET = 4096;
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export declare const ESP32_APB_CTL_DATE_ADDR: number;
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export declare const ESP32S2_SPI_REG_BASE = 1061167104;
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export declare const ESP32S2_BASEFUSEADDR = 1061265408;
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export declare const ESP32S2_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32S2_MACFUSEADDR = 1061265476;
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export declare const ESP32S2_SPI_USR_OFFS = 24;
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export declare const ESP32S2_SPI_USR1_OFFS = 28;
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@@ -81,6 +83,7 @@ export declare const ESP32S2_UARTDEV_BUF_NO = 1073741076;
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export declare const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2;
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export declare const ESP32S3_SPI_REG_BASE = 1610620928;
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export declare const ESP32S3_BASEFUSEADDR = 1610641408;
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export declare const ESP32S3_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32S3_MACFUSEADDR: number;
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export declare const ESP32S3_SPI_USR_OFFS = 24;
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export declare const ESP32S3_SPI_USR1_OFFS = 28;
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@@ -105,6 +108,7 @@ export declare const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3;
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export declare const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4;
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export declare const ESP32C2_SPI_REG_BASE = 1610620928;
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export declare const ESP32C2_BASEFUSEADDR = 1610647552;
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export declare const ESP32C2_EFUSE_BLOCK2_ADDR: number;
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export declare const ESP32C2_MACFUSEADDR: number;
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export declare const ESP32C2_SPI_USR_OFFS = 24;
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export declare const ESP32C2_SPI_USR1_OFFS = 28;
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@@ -146,6 +150,7 @@ export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 1610647632;
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export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 1610647640;
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export declare const ESP32C5_SPI_REG_BASE = 1610625024;
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export declare const ESP32C5_BASEFUSEADDR = 1611352064;
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export declare const ESP32C5_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32C5_MACFUSEADDR: number;
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export declare const ESP32C5_SPI_USR_OFFS = 24;
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export declare const ESP32C5_SPI_USR1_OFFS = 28;
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@@ -154,11 +159,16 @@ export declare const ESP32C5_SPI_MOSI_DLEN_OFFS = 36;
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export declare const ESP32C5_SPI_MISO_DLEN_OFFS = 40;
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export declare const ESP32C5_SPI_W0_OFFS = 88;
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export declare const ESP32C5_UART_DATE_REG_ADDR = 1610612860;
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export declare const ESP32C5_UART_CLKDIV_REG = 1610612756;
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export declare const ESP32C5_BOOTLOADER_FLASH_OFFSET = 8192;
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export declare const ESP32C5_PCR_SYSCLK_CONF_REG = 1611227408;
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export declare const ESP32C5_PCR_SYSCLK_XTAL_FREQ_V: number;
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export declare const ESP32C5_PCR_SYSCLK_XTAL_FREQ_S = 24;
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export declare const ESP32C5_UARTDEV_BUF_NO = 1082520852;
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export declare const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
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export declare const ESP32C6_SPI_REG_BASE = 1610625024;
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export declare const ESP32C6_BASEFUSEADDR = 1611335680;
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export declare const ESP32C6_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32C6_MACFUSEADDR: number;
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export declare const ESP32C6_SPI_USR_OFFS = 24;
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export declare const ESP32C6_SPI_USR1_OFFS = 28;
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@@ -186,6 +196,7 @@ export declare const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN: number;
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export declare const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG: number;
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export declare const ESP32C61_SPI_REG_BASE = 1610625024;
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export declare const ESP32C61_BASEFUSEADDR = 1611352064;
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export declare const ESP32C61_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32C61_MACFUSEADDR: number;
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export declare const ESP32C61_SPI_USR_OFFS = 24;
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export declare const ESP32C61_SPI_USR1_OFFS = 28;
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@@ -197,6 +208,7 @@ export declare const ESP32C61_UART_DATE_REG_ADDR = 1610612860;
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export declare const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0;
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export declare const ESP32H2_SPI_REG_BASE = 1610625024;
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export declare const ESP32H2_BASEFUSEADDR = 1611335680;
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export declare const ESP32H2_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32H2_MACFUSEADDR: number;
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export declare const ESP32H2_SPI_USR_OFFS = 24;
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export declare const ESP32H2_SPI_USR1_OFFS = 28;
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@@ -216,6 +228,7 @@ export declare const ESP32H2_UARTDEV_BUF_NO = 1082457852;
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export declare const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
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export declare const ESP32H4_SPI_REG_BASE = 1611239424;
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export declare const ESP32H4_BASEFUSEADDR = 1611339776;
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export declare const ESP32H4_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32H4_MACFUSEADDR: number;
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export declare const ESP32H4_SPI_USR_OFFS = 24;
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export declare const ESP32H4_SPI_USR1_OFFS = 28;
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@@ -233,6 +246,7 @@ export declare const ESP32H4_RTC_CNTL_WDT_WKEY = 1356348065;
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export declare const ESP32H4_RTC_CNTL_SWD_WKEY = 1356348065;
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export declare const ESP32H21_SPI_REG_BASE = 1610625024;
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export declare const ESP32H21_BASEFUSEADDR = 1611350016;
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export declare const ESP32H21_EFUSE_BLOCK1_ADDR: number;
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export declare const ESP32H21_MACFUSEADDR: number;
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export declare const ESP32H21_SPI_USR_OFFS = 24;
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export declare const ESP32H21_SPI_USR1_OFFS = 28;
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package/dist/const.js
CHANGED
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@@ -75,8 +75,10 @@ export const ESP32_SPI_MISO_DLEN_OFFS = 0x2c;
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export const ESP32_SPI_W0_OFFS = 0x80;
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export const ESP32_UART_DATE_REG_ADDR = 0x60000078;
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export const ESP32_BOOTLOADER_FLASH_OFFSET = 0x1000;
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export const ESP32_APB_CTL_DATE_ADDR = 0x3ff66000 + 0x7c;
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export const ESP32S2_SPI_REG_BASE = 0x3f402000;
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export const ESP32S2_BASEFUSEADDR = 0x3f41a000;
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export const ESP32S2_EFUSE_BLOCK1_ADDR = ESP32S2_BASEFUSEADDR + 0x044;
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export const ESP32S2_MACFUSEADDR = 0x3f41a044;
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export const ESP32S2_SPI_USR_OFFS = 0x18;
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export const ESP32S2_SPI_USR1_OFFS = 0x1c;
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@@ -102,6 +104,7 @@ export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which
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export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use
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export const ESP32S3_SPI_REG_BASE = 0x60002000;
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export const ESP32S3_BASEFUSEADDR = 0x60007000;
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export const ESP32S3_EFUSE_BLOCK1_ADDR = ESP32S3_BASEFUSEADDR + 0x044;
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export const ESP32S3_MACFUSEADDR = 0x60007000 + 0x044;
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export const ESP32S3_SPI_USR_OFFS = 0x18;
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export const ESP32S3_SPI_USR1_OFFS = 0x1c;
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@@ -128,6 +131,7 @@ export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG i
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export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used
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export const ESP32C2_SPI_REG_BASE = 0x60002000;
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export const ESP32C2_BASEFUSEADDR = 0x60008800;
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export const ESP32C2_EFUSE_BLOCK2_ADDR = ESP32C2_BASEFUSEADDR + 0x040;
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export const ESP32C2_MACFUSEADDR = ESP32C2_BASEFUSEADDR + 0x040;
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export const ESP32C2_SPI_USR_OFFS = 0x18;
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export const ESP32C2_SPI_USR1_OFFS = 0x1c;
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@@ -174,6 +178,7 @@ export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
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export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;
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export const ESP32C5_SPI_REG_BASE = 0x60003000;
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export const ESP32C5_BASEFUSEADDR = 0x600b4800;
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export const ESP32C5_EFUSE_BLOCK1_ADDR = ESP32C5_BASEFUSEADDR + 0x044;
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export const ESP32C5_MACFUSEADDR = 0x600b4800 + 0x044;
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export const ESP32C5_SPI_USR_OFFS = 0x18;
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export const ESP32C5_SPI_USR1_OFFS = 0x1c;
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export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
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export const ESP32C5_SPI_W0_OFFS = 0x58;
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export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
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export const ESP32C5_UART_CLKDIV_REG = 0x60000014;
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export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
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// ESP32-C5 Crystal frequency detection registers
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export const ESP32C5_PCR_SYSCLK_CONF_REG = 0x60096110;
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export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_V = 0x7f << 24;
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export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_S = 24;
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// ESP32-C5 USB-JTAG/Serial detection
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export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
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export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
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export const ESP32C6_SPI_REG_BASE = 0x60003000;
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export const ESP32C6_BASEFUSEADDR = 0x600b0800;
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export const ESP32C6_EFUSE_BLOCK1_ADDR = ESP32C6_BASEFUSEADDR + 0x044;
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export const ESP32C6_MACFUSEADDR = 0x600b0800 + 0x044;
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export const ESP32C6_SPI_USR_OFFS = 0x18;
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export const ESP32C6_SPI_USR1_OFFS = 0x1c;
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export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG
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export const ESP32C61_SPI_REG_BASE = 0x60003000;
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export const ESP32C61_BASEFUSEADDR = 0x600b4800;
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export const ESP32C61_EFUSE_BLOCK1_ADDR = ESP32C61_BASEFUSEADDR + 0x044;
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export const ESP32C61_MACFUSEADDR = 0x600b4800 + 0x044;
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export const ESP32C61_SPI_USR_OFFS = 0x18;
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export const ESP32C61_SPI_USR1_OFFS = 0x1c;
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export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
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export const ESP32H2_SPI_REG_BASE = 0x60003000;
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export const ESP32H2_BASEFUSEADDR = 0x600b0800;
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export const ESP32H2_EFUSE_BLOCK1_ADDR = ESP32H2_BASEFUSEADDR + 0x044;
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export const ESP32H2_MACFUSEADDR = 0x600b0800 + 0x044;
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export const ESP32H2_SPI_USR_OFFS = 0x18;
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export const ESP32H2_SPI_USR1_OFFS = 0x1c;
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@@ -250,6 +263,7 @@ export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which
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export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
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export const ESP32H4_SPI_REG_BASE = 0x60099000;
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export const ESP32H4_BASEFUSEADDR = 0x600b1800;
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export const ESP32H4_EFUSE_BLOCK1_ADDR = ESP32H4_BASEFUSEADDR + 0x044;
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export const ESP32H4_MACFUSEADDR = 0x600b1800 + 0x044;
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export const ESP32H4_SPI_USR_OFFS = 0x18;
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export const ESP32H4_SPI_USR1_OFFS = 0x1c;
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@@ -268,6 +282,7 @@ export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as
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export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
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export const ESP32H21_SPI_REG_BASE = 0x60003000;
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export const ESP32H21_BASEFUSEADDR = 0x600b4000;
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export const ESP32H21_EFUSE_BLOCK1_ADDR = ESP32H21_BASEFUSEADDR + 0x044;
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export const ESP32H21_MACFUSEADDR = 0x600b4000 + 0x044;
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export const ESP32H21_SPI_USR_OFFS = 0x18;
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export const ESP32H21_SPI_USR1_OFFS = 0x1c;
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package/dist/esp_loader.d.ts
CHANGED
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@@ -84,9 +84,6 @@ export declare class ESPLoader extends EventTarget {
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* Detect chip type using GET_SECURITY_INFO (for newer chips) or magic value (for older chips)
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*/
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detectChip(): Promise<void>;
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/**
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* Get chip revision for ESP32-P4
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*/
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getChipRevision(): Promise<number>;
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/**
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* Power on the flash chip for ESP32-P4 Rev 301 (ECO6)
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* This is an alias for rtcWdtResetChipSpecific() for backwards compatibility
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*/
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watchdogReset(): Promise<void>;
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/**
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* Get chip revision for ESP32-C3
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* Reads from EFUSE registers and calculates revision
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*/
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getChipRevisionC3(): Promise<number>;
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/**
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* RTC watchdog timer reset for ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, and ESP32-P4
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* Uses specific registers for each chip family
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@@ -271,7 +263,10 @@ export declare class ESPLoader extends EventTarget {
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* Calculate checksum of a blob, as it is defined by the ROM
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*/
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checksum(data: number[], state?: number): number;
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getC5CrystalFreqRomExpect(): Promise<number>;
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getC5CrystalFreqDetected(): Promise<number>;
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setBaudrate(baud: number): Promise<void>;
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private setBaudrateC5Rom;
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reconfigurePort(baud: number): Promise<void>;
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/**
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* @name syncWithTimeout
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package/dist/esp_loader.js
CHANGED
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/// <reference types="@types/w3c-web-serial" />
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-
import { CHIP_FAMILY_ESP32, CHIP_FAMILY_ESP32S2, CHIP_FAMILY_ESP32S3, CHIP_FAMILY_ESP32C2, CHIP_FAMILY_ESP32C3, CHIP_FAMILY_ESP32C5, CHIP_FAMILY_ESP32C6, CHIP_FAMILY_ESP32C61, CHIP_FAMILY_ESP32H2, CHIP_FAMILY_ESP32H4, CHIP_FAMILY_ESP32H21, CHIP_FAMILY_ESP32P4, CHIP_FAMILY_ESP32S31, CHIP_FAMILY_ESP8266, MAX_TIMEOUT, DEFAULT_TIMEOUT, ERASE_REGION_TIMEOUT_PER_MB, ESP_CHANGE_BAUDRATE, ESP_CHECKSUM_MAGIC, ESP_FLASH_BEGIN, ESP_FLASH_DATA, ESP_FLASH_END, ESP_MEM_BEGIN, ESP_MEM_DATA, ESP_MEM_END, ESP_READ_REG, ESP_WRITE_REG, ESP_SPI_ATTACH, ESP_SYNC, ESP_GET_SECURITY_INFO, FLASH_SECTOR_SIZE, FLASH_WRITE_SIZE, STUB_FLASH_WRITE_SIZE, MEM_END_ROM_TIMEOUT, ROM_INVALID_RECV_MSG, SYNC_PACKET, SYNC_TIMEOUT, USB_RAM_BLOCK, ESP_ERASE_FLASH, ESP_ERASE_REGION, ESP_READ_FLASH, CHIP_ERASE_TIMEOUT, FLASH_READ_TIMEOUT, timeoutPerMb, ESP_ROM_BAUD, USB_JTAG_SERIAL_PID, ESP_FLASH_DEFL_BEGIN, ESP_FLASH_DEFL_DATA, ESP_FLASH_DEFL_END, getSpiFlashAddresses, DETECTED_FLASH_SIZES, CHIP_DETECT_MAGIC_REG_ADDR, CHIP_DETECT_MAGIC_VALUES, CHIP_ID_TO_INFO, ESP32P4_EFUSE_BLOCK1_ADDR, SlipReadError, ESP32S2_RTC_CNTL_WDTWPROTECT_REG, ESP32S2_RTC_CNTL_WDTCONFIG0_REG, ESP32S2_RTC_CNTL_WDTCONFIG1_REG, ESP32S2_RTC_CNTL_WDT_WKEY, ESP32S2_RTC_CNTL_OPTION1_REG, ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK, ESP32S3_RTC_CNTL_WDTWPROTECT_REG, ESP32S3_RTC_CNTL_WDTCONFIG0_REG, ESP32S3_RTC_CNTL_WDTCONFIG1_REG, ESP32S3_RTC_CNTL_WDT_WKEY, ESP32S3_RTC_CNTL_OPTION1_REG, ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK, ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG, ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG, ESP32C3_RTC_CNTL_WDTWPROTECT_REG, ESP32C3_RTC_CNTL_WDTCONFIG0_REG, ESP32C3_RTC_CNTL_WDTCONFIG1_REG, ESP32C3_RTC_CNTL_WDT_WKEY, ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG, ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG, ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG, ESP32C5_C6_RTC_CNTL_WDT_WKEY, ESP32P4_RTC_CNTL_WDTWPROTECT_REG, ESP32P4_RTC_CNTL_WDTCONFIG0_REG, ESP32P4_RTC_CNTL_WDTCONFIG1_REG, ESP32P4_RTC_CNTL_WDT_WKEY, ESP32P4_RTC_CNTL_OPTION1_REG, ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK, ESP32P4_LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG, ESP32P4_PMU_EXT_LDO_P0_0P1A_ANA_REG, ESP32P4_PMU_ANA_0P1A_EN_CUR_LIM_0, ESP32P4_PMU_EXT_LDO_P0_0P1A_REG, ESP32P4_PMU_0P1A_TARGET0_0, ESP32P4_PMU_0P1A_FORCE_TIEH_SEL_0, ESP32P4_PMU_DATE_REG, } from "./const";
|
|
2
|
+
import { CHIP_FAMILY_ESP32, CHIP_FAMILY_ESP32S2, CHIP_FAMILY_ESP32S3, CHIP_FAMILY_ESP32C2, CHIP_FAMILY_ESP32C3, CHIP_FAMILY_ESP32C5, CHIP_FAMILY_ESP32C6, CHIP_FAMILY_ESP32C61, CHIP_FAMILY_ESP32H2, CHIP_FAMILY_ESP32H4, CHIP_FAMILY_ESP32H21, CHIP_FAMILY_ESP32P4, CHIP_FAMILY_ESP32S31, CHIP_FAMILY_ESP8266, MAX_TIMEOUT, DEFAULT_TIMEOUT, ERASE_REGION_TIMEOUT_PER_MB, ESP_CHANGE_BAUDRATE, ESP_CHECKSUM_MAGIC, ESP_FLASH_BEGIN, ESP_FLASH_DATA, ESP_FLASH_END, ESP_MEM_BEGIN, ESP_MEM_DATA, ESP_MEM_END, ESP_READ_REG, ESP_WRITE_REG, ESP_SPI_ATTACH, ESP_SYNC, ESP_GET_SECURITY_INFO, FLASH_SECTOR_SIZE, FLASH_WRITE_SIZE, STUB_FLASH_WRITE_SIZE, MEM_END_ROM_TIMEOUT, ROM_INVALID_RECV_MSG, SYNC_PACKET, SYNC_TIMEOUT, USB_RAM_BLOCK, ESP_ERASE_FLASH, ESP_ERASE_REGION, ESP_READ_FLASH, CHIP_ERASE_TIMEOUT, FLASH_READ_TIMEOUT, timeoutPerMb, ESP_ROM_BAUD, USB_JTAG_SERIAL_PID, ESP_FLASH_DEFL_BEGIN, ESP_FLASH_DEFL_DATA, ESP_FLASH_DEFL_END, getSpiFlashAddresses, DETECTED_FLASH_SIZES, CHIP_DETECT_MAGIC_REG_ADDR, CHIP_DETECT_MAGIC_VALUES, CHIP_ID_TO_INFO, ESP32_BASEFUSEADDR, ESP32_APB_CTL_DATE_ADDR, ESP32S2_EFUSE_BLOCK1_ADDR, ESP32S3_EFUSE_BLOCK1_ADDR, ESP32C2_EFUSE_BLOCK2_ADDR, ESP32C5_EFUSE_BLOCK1_ADDR, ESP32C6_EFUSE_BLOCK1_ADDR, ESP32C61_EFUSE_BLOCK1_ADDR, ESP32H2_EFUSE_BLOCK1_ADDR, ESP32P4_EFUSE_BLOCK1_ADDR, ESP32S31_EFUSE_BLOCK1_ADDR, SlipReadError, ESP32S2_RTC_CNTL_WDTWPROTECT_REG, ESP32S2_RTC_CNTL_WDTCONFIG0_REG, ESP32S2_RTC_CNTL_WDTCONFIG1_REG, ESP32S2_RTC_CNTL_WDT_WKEY, ESP32S2_RTC_CNTL_OPTION1_REG, ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK, ESP32S3_RTC_CNTL_WDTWPROTECT_REG, ESP32S3_RTC_CNTL_WDTCONFIG0_REG, ESP32S3_RTC_CNTL_WDTCONFIG1_REG, ESP32S3_RTC_CNTL_WDT_WKEY, ESP32S3_RTC_CNTL_OPTION1_REG, ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK, ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG, ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG, ESP32C3_RTC_CNTL_WDTWPROTECT_REG, ESP32C3_RTC_CNTL_WDTCONFIG0_REG, ESP32C3_RTC_CNTL_WDTCONFIG1_REG, ESP32C3_RTC_CNTL_WDT_WKEY, ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG, ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG, ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG, ESP32C5_C6_RTC_CNTL_WDT_WKEY, ESP32C5_UART_CLKDIV_REG, ESP32C5_PCR_SYSCLK_CONF_REG, ESP32C5_PCR_SYSCLK_XTAL_FREQ_V, ESP32C5_PCR_SYSCLK_XTAL_FREQ_S, ESP32P4_RTC_CNTL_WDTWPROTECT_REG, ESP32P4_RTC_CNTL_WDTCONFIG0_REG, ESP32P4_RTC_CNTL_WDTCONFIG1_REG, ESP32P4_RTC_CNTL_WDT_WKEY, ESP32P4_RTC_CNTL_OPTION1_REG, ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK, ESP32P4_LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG, ESP32P4_PMU_EXT_LDO_P0_0P1A_ANA_REG, ESP32P4_PMU_ANA_0P1A_EN_CUR_LIM_0, ESP32P4_PMU_EXT_LDO_P0_0P1A_REG, ESP32P4_PMU_0P1A_TARGET0_0, ESP32P4_PMU_0P1A_FORCE_TIEH_SEL_0, ESP32P4_PMU_DATE_REG, } from "./const";
|
|
3
3
|
import { getStubCode } from "./stubs";
|
|
4
4
|
import { hexFormatter, sleep, slipEncode, toHex } from "./util";
|
|
5
|
+
import { FLASH_MANUFACTURERS, FLASH_DEVICES } from "./flash_jedec";
|
|
5
6
|
import { deflate } from "pako";
|
|
6
7
|
import { pack, unpack } from "./struct";
|
|
7
8
|
export class ESPLoader extends EventTarget {
|
|
@@ -365,7 +366,10 @@ export class ESPLoader extends EventTarget {
|
|
|
365
366
|
for (let i = 0; i < 4; i++) {
|
|
366
367
|
this._efuses[i] = await this.readRegister(AddrMAC + 4 * i);
|
|
367
368
|
}
|
|
368
|
-
this.
|
|
369
|
+
const revisionInfo = this.chipRevision !== null && this.chipRevision !== undefined
|
|
370
|
+
? ` (revision ${this.chipRevision})`
|
|
371
|
+
: "";
|
|
372
|
+
this.logger.log(`Connected to ${this.chipName}${revisionInfo}`);
|
|
369
373
|
this.logger.debug(`Bootloader flash offset: 0x${FlAddr.flashOffs.toString(16)}`);
|
|
370
374
|
// Mark initialization as successful
|
|
371
375
|
this._initializationSucceeded = true;
|
|
@@ -382,22 +386,14 @@ export class ESPLoader extends EventTarget {
|
|
|
382
386
|
if (chipInfo) {
|
|
383
387
|
this.chipName = chipInfo.name;
|
|
384
388
|
this.chipFamily = chipInfo.family;
|
|
385
|
-
|
|
386
|
-
|
|
387
|
-
|
|
388
|
-
this.
|
|
389
|
-
|
|
390
|
-
if (this.chipRevision >= 300) {
|
|
391
|
-
this.chipVariant = "rev300";
|
|
392
|
-
}
|
|
393
|
-
else {
|
|
394
|
-
this.chipVariant = "rev0";
|
|
395
|
-
}
|
|
396
|
-
this.logger.debug(`ESP32-P4 variant: ${this.chipVariant}`);
|
|
389
|
+
this.chipRevision = await this.getChipRevision();
|
|
390
|
+
this.logger.debug(`${this.chipName} revision: ${this.chipRevision}`);
|
|
391
|
+
if (this.chipFamily === CHIP_FAMILY_ESP32P4 &&
|
|
392
|
+
this.chipRevision >= 300) {
|
|
393
|
+
this.chipVariant = "rev300";
|
|
397
394
|
}
|
|
398
|
-
else if (this.chipFamily ===
|
|
399
|
-
this.
|
|
400
|
-
this.logger.debug(`ESP32-C3 revision: ${this.chipRevision}`);
|
|
395
|
+
else if (this.chipFamily === CHIP_FAMILY_ESP32P4) {
|
|
396
|
+
this.chipVariant = "rev0";
|
|
401
397
|
}
|
|
402
398
|
this.logger.debug(`Detected chip via IMAGE_CHIP_ID: ${chipId} (${this.chipName})`);
|
|
403
399
|
return;
|
|
@@ -429,40 +425,109 @@ export class ESPLoader extends EventTarget {
|
|
|
429
425
|
}
|
|
430
426
|
this.chipName = chip.name;
|
|
431
427
|
this.chipFamily = chip.family;
|
|
428
|
+
this.chipRevision = await this.getChipRevision();
|
|
429
|
+
this.logger.debug(`${this.chipName} revision: ${this.chipRevision}`);
|
|
432
430
|
if (this.chipFamily === CHIP_FAMILY_ESP32P4) {
|
|
433
|
-
this.
|
|
434
|
-
if (this.chipRevision >= 300) {
|
|
435
|
-
this.chipVariant = "rev300";
|
|
436
|
-
}
|
|
437
|
-
else {
|
|
438
|
-
this.chipVariant = "rev0";
|
|
439
|
-
}
|
|
431
|
+
this.chipVariant = this.chipRevision >= 300 ? "rev300" : "rev0";
|
|
440
432
|
this.logger.debug(`ESP32-P4 variant: ${this.chipVariant}`);
|
|
441
433
|
}
|
|
442
|
-
else if (this.chipFamily === CHIP_FAMILY_ESP32C3) {
|
|
443
|
-
this.chipRevision = await this.getChipRevision();
|
|
444
|
-
}
|
|
445
434
|
this.logger.debug(`Detected chip via magic value: ${toHex(chipMagicValue >>> 0, 8)} (${this.chipName})`);
|
|
446
435
|
}
|
|
447
|
-
/**
|
|
448
|
-
* Get chip revision for ESP32-P4
|
|
449
|
-
*/
|
|
450
436
|
async getChipRevision() {
|
|
451
|
-
|
|
452
|
-
|
|
453
|
-
|
|
454
|
-
|
|
455
|
-
|
|
456
|
-
|
|
457
|
-
|
|
458
|
-
|
|
459
|
-
|
|
460
|
-
|
|
461
|
-
|
|
462
|
-
|
|
463
|
-
|
|
464
|
-
|
|
465
|
-
|
|
437
|
+
var _a;
|
|
438
|
+
let minor = 0;
|
|
439
|
+
let major = 0;
|
|
440
|
+
switch (this.chipFamily) {
|
|
441
|
+
case CHIP_FAMILY_ESP32: {
|
|
442
|
+
const efuse3 = await this.readRegister(ESP32_BASEFUSEADDR + 4 * 3);
|
|
443
|
+
const efuse5 = await this.readRegister(ESP32_BASEFUSEADDR + 4 * 5);
|
|
444
|
+
minor = (efuse5 >> 24) & 0x3;
|
|
445
|
+
const revBit0 = (efuse3 >> 15) & 0x1;
|
|
446
|
+
const revBit1 = (efuse5 >> 20) & 0x1;
|
|
447
|
+
const apb = await this.readRegister(ESP32_APB_CTL_DATE_ADDR);
|
|
448
|
+
const revBit2 = (apb >> 31) & 0x1;
|
|
449
|
+
const combined = (revBit2 << 2) | (revBit1 << 1) | revBit0;
|
|
450
|
+
major =
|
|
451
|
+
(_a = { 0: 0, 1: 1, 3: 2, 7: 3 }[combined]) !== null && _a !== void 0 ? _a : 0;
|
|
452
|
+
break;
|
|
453
|
+
}
|
|
454
|
+
case CHIP_FAMILY_ESP32S2: {
|
|
455
|
+
const w3 = await this.readRegister(ESP32S2_EFUSE_BLOCK1_ADDR + 4 * 3);
|
|
456
|
+
const w4 = await this.readRegister(ESP32S2_EFUSE_BLOCK1_ADDR + 4 * 4);
|
|
457
|
+
const hi = (w3 >> 20) & 0x01;
|
|
458
|
+
const lo = (w4 >> 4) & 0x07;
|
|
459
|
+
minor = (hi << 3) + lo;
|
|
460
|
+
major = (w3 >> 18) & 0x03;
|
|
461
|
+
break;
|
|
462
|
+
}
|
|
463
|
+
case CHIP_FAMILY_ESP32S3: {
|
|
464
|
+
const w3 = await this.readRegister(ESP32S3_EFUSE_BLOCK1_ADDR + 4 * 3);
|
|
465
|
+
const w5 = await this.readRegister(ESP32S3_EFUSE_BLOCK1_ADDR + 4 * 5);
|
|
466
|
+
const hi = (w5 >> 23) & 0x01;
|
|
467
|
+
const lo = (w3 >> 18) & 0x07;
|
|
468
|
+
minor = (hi << 3) + lo;
|
|
469
|
+
major = (w5 >> 24) & 0x03;
|
|
470
|
+
break;
|
|
471
|
+
}
|
|
472
|
+
case CHIP_FAMILY_ESP32C2: {
|
|
473
|
+
const w1 = await this.readRegister(ESP32C2_EFUSE_BLOCK2_ADDR + 4 * 1);
|
|
474
|
+
minor = (w1 >> 16) & 0x0f;
|
|
475
|
+
major = (w1 >> 20) & 0x03;
|
|
476
|
+
break;
|
|
477
|
+
}
|
|
478
|
+
case CHIP_FAMILY_ESP32C3: {
|
|
479
|
+
const w3 = await this.readRegister(ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG);
|
|
480
|
+
const w5 = await this.readRegister(ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG);
|
|
481
|
+
const hi = (w5 >> 23) & 0x01;
|
|
482
|
+
const lo = (w3 >> 18) & 0x07;
|
|
483
|
+
minor = (hi << 3) + lo;
|
|
484
|
+
major = (w5 >> 24) & 0x03;
|
|
485
|
+
break;
|
|
486
|
+
}
|
|
487
|
+
case CHIP_FAMILY_ESP32C5: {
|
|
488
|
+
const w2 = await this.readRegister(ESP32C5_EFUSE_BLOCK1_ADDR + 4 * 2);
|
|
489
|
+
minor = w2 & 0x0f;
|
|
490
|
+
major = (w2 >> 4) & 0x03;
|
|
491
|
+
break;
|
|
492
|
+
}
|
|
493
|
+
case CHIP_FAMILY_ESP32C6: {
|
|
494
|
+
const w3 = await this.readRegister(ESP32C6_EFUSE_BLOCK1_ADDR + 4 * 3);
|
|
495
|
+
minor = (w3 >> 18) & 0x0f;
|
|
496
|
+
major = (w3 >> 22) & 0x03;
|
|
497
|
+
break;
|
|
498
|
+
}
|
|
499
|
+
case CHIP_FAMILY_ESP32C61: {
|
|
500
|
+
const w2 = await this.readRegister(ESP32C61_EFUSE_BLOCK1_ADDR + 4 * 2);
|
|
501
|
+
minor = w2 & 0x0f;
|
|
502
|
+
major = (w2 >> 4) & 0x03;
|
|
503
|
+
break;
|
|
504
|
+
}
|
|
505
|
+
case CHIP_FAMILY_ESP32H2: {
|
|
506
|
+
const w3 = await this.readRegister(ESP32H2_EFUSE_BLOCK1_ADDR + 4 * 3);
|
|
507
|
+
minor = (w3 >> 18) & 0x07;
|
|
508
|
+
major = (w3 >> 21) & 0x03;
|
|
509
|
+
break;
|
|
510
|
+
}
|
|
511
|
+
case CHIP_FAMILY_ESP32H4: {
|
|
512
|
+
break;
|
|
513
|
+
}
|
|
514
|
+
case CHIP_FAMILY_ESP32H21: {
|
|
515
|
+
break;
|
|
516
|
+
}
|
|
517
|
+
case CHIP_FAMILY_ESP32P4: {
|
|
518
|
+
const w2 = await this.readRegister(ESP32P4_EFUSE_BLOCK1_ADDR + 4 * 2);
|
|
519
|
+
minor = w2 & 0x0f;
|
|
520
|
+
major = (((w2 >> 23) & 1) << 2) | ((w2 >> 4) & 0x03);
|
|
521
|
+
break;
|
|
522
|
+
}
|
|
523
|
+
case CHIP_FAMILY_ESP32S31: {
|
|
524
|
+
const w2 = await this.readRegister(ESP32S31_EFUSE_BLOCK1_ADDR + 4 * 2);
|
|
525
|
+
minor = w2 & 0x0f;
|
|
526
|
+
major = (w2 >> 4) & 0x03;
|
|
527
|
+
break;
|
|
528
|
+
}
|
|
529
|
+
}
|
|
530
|
+
return major * 100 + minor;
|
|
466
531
|
}
|
|
467
532
|
/**
|
|
468
533
|
* Power on the flash chip for ESP32-P4 Rev 301 (ECO6)
|
|
@@ -1171,7 +1236,7 @@ export class ESPLoader extends EventTarget {
|
|
|
1171
1236
|
try {
|
|
1172
1237
|
await Promise.race([syncPromise, timeoutPromise]);
|
|
1173
1238
|
// Sync succeeded
|
|
1174
|
-
this.logger.
|
|
1239
|
+
this.logger.debug(`Connected CDC/JTAG successfully with ${strategy.name} reset.`);
|
|
1175
1240
|
return;
|
|
1176
1241
|
}
|
|
1177
1242
|
catch (error) {
|
|
@@ -1212,24 +1277,6 @@ export class ESPLoader extends EventTarget {
|
|
|
1212
1277
|
async watchdogReset() {
|
|
1213
1278
|
await this.rtcWdtResetChipSpecific();
|
|
1214
1279
|
}
|
|
1215
|
-
/**
|
|
1216
|
-
* Get chip revision for ESP32-C3
|
|
1217
|
-
* Reads from EFUSE registers and calculates revision
|
|
1218
|
-
*/
|
|
1219
|
-
async getChipRevisionC3() {
|
|
1220
|
-
if (this.chipFamily !== CHIP_FAMILY_ESP32C3) {
|
|
1221
|
-
return 0;
|
|
1222
|
-
}
|
|
1223
|
-
// Read EFUSE_RD_MAC_SPI_SYS_3_REG (bits [20:18] = lower 3 bits of revision)
|
|
1224
|
-
const word3 = await this.readRegister(ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG);
|
|
1225
|
-
const low = (word3 >> 18) & 0x07;
|
|
1226
|
-
// Read EFUSE_RD_MAC_SPI_SYS_5_REG (bits [25:23] = upper 3 bits of revision)
|
|
1227
|
-
const word5 = await this.readRegister(ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG);
|
|
1228
|
-
const hi = (word5 >> 23) & 0x07;
|
|
1229
|
-
// Combine: upper 3 bits from word5, lower 3 bits from word3
|
|
1230
|
-
const revision = (hi << 3) | low;
|
|
1231
|
-
return revision;
|
|
1232
|
-
}
|
|
1233
1280
|
/**
|
|
1234
1281
|
* RTC watchdog timer reset for ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, and ESP32-P4
|
|
1235
1282
|
* Uses specific registers for each chip family
|
|
@@ -1780,15 +1827,34 @@ export class ESPLoader extends EventTarget {
|
|
|
1780
1827
|
}
|
|
1781
1828
|
return state;
|
|
1782
1829
|
}
|
|
1830
|
+
async getC5CrystalFreqRomExpect() {
|
|
1831
|
+
const reg = await this.readRegister(ESP32C5_PCR_SYSCLK_CONF_REG);
|
|
1832
|
+
return ((reg & ESP32C5_PCR_SYSCLK_XTAL_FREQ_V) >>> ESP32C5_PCR_SYSCLK_XTAL_FREQ_S);
|
|
1833
|
+
}
|
|
1834
|
+
async getC5CrystalFreqDetected() {
|
|
1835
|
+
const UART_CLKDIV_MASK = 0xfffff;
|
|
1836
|
+
const uartDiv = (await this.readRegister(ESP32C5_UART_CLKDIV_REG)) & UART_CLKDIV_MASK;
|
|
1837
|
+
const estXtal = (ESP_ROM_BAUD * uartDiv) / 1e6;
|
|
1838
|
+
if (estXtal > 45)
|
|
1839
|
+
return 48;
|
|
1840
|
+
if (estXtal > 33)
|
|
1841
|
+
return 40;
|
|
1842
|
+
return 26;
|
|
1843
|
+
}
|
|
1783
1844
|
async setBaudrate(baud) {
|
|
1784
|
-
|
|
1785
|
-
|
|
1786
|
-
|
|
1787
|
-
await this.checkCommand(ESP_CHANGE_BAUDRATE, buffer);
|
|
1845
|
+
const chipFamily = this._parent ? this._parent.chipFamily : this.chipFamily;
|
|
1846
|
+
if (!this.IS_STUB && chipFamily === CHIP_FAMILY_ESP32C5) {
|
|
1847
|
+
await this.setBaudrateC5Rom(baud);
|
|
1788
1848
|
}
|
|
1789
|
-
|
|
1790
|
-
|
|
1791
|
-
|
|
1849
|
+
else {
|
|
1850
|
+
try {
|
|
1851
|
+
const buffer = pack("<II", baud, this.IS_STUB ? ESP_ROM_BAUD : 0);
|
|
1852
|
+
await this.checkCommand(ESP_CHANGE_BAUDRATE, buffer);
|
|
1853
|
+
}
|
|
1854
|
+
catch (e) {
|
|
1855
|
+
this.logger.error(`Baudrate change error: ${e}`);
|
|
1856
|
+
throw new Error(`Unable to change the baud rate to ${baud}: No response from set baud rate command.`);
|
|
1857
|
+
}
|
|
1792
1858
|
}
|
|
1793
1859
|
if (this._parent) {
|
|
1794
1860
|
await this._parent.reconfigurePort(baud);
|
|
@@ -1813,7 +1879,29 @@ export class ESPLoader extends EventTarget {
|
|
|
1813
1879
|
this.logger.log(`⚠️ WARNING: Baudrate ${baud} exceeds USB-Serial chip limit (${maxBaud})!`);
|
|
1814
1880
|
this.logger.log(`⚠️ This may cause data corruption or connection failures!`);
|
|
1815
1881
|
}
|
|
1816
|
-
this.logger.
|
|
1882
|
+
this.logger.debug(`Changed baud rate to ${baud}`);
|
|
1883
|
+
}
|
|
1884
|
+
async setBaudrateC5Rom(baud) {
|
|
1885
|
+
const crystalFreqRomExpect = await this.getC5CrystalFreqRomExpect();
|
|
1886
|
+
const crystalFreqDetect = await this.getC5CrystalFreqDetected();
|
|
1887
|
+
this.logger.log(`ROM expects crystal freq: ${crystalFreqRomExpect} MHz, detected ${crystalFreqDetect} MHz.`);
|
|
1888
|
+
let baudRate = baud;
|
|
1889
|
+
if (crystalFreqDetect === 48 && crystalFreqRomExpect === 40) {
|
|
1890
|
+
baudRate = Math.trunc((baud * 40) / 48);
|
|
1891
|
+
}
|
|
1892
|
+
else if (crystalFreqDetect === 40 && crystalFreqRomExpect === 48) {
|
|
1893
|
+
baudRate = Math.trunc((baud * 48) / 40);
|
|
1894
|
+
}
|
|
1895
|
+
this.logger.log(`Changing baud rate to ${baudRate}...`);
|
|
1896
|
+
try {
|
|
1897
|
+
const buffer = pack("<II", baudRate, 0);
|
|
1898
|
+
await this.checkCommand(ESP_CHANGE_BAUDRATE, buffer);
|
|
1899
|
+
}
|
|
1900
|
+
catch (e) {
|
|
1901
|
+
this.logger.error(`Baudrate change error: ${e}`);
|
|
1902
|
+
throw new Error(`Unable to change the baud rate to ${baudRate}: No response from set baud rate command.`);
|
|
1903
|
+
}
|
|
1904
|
+
this.logger.log("Changed.");
|
|
1817
1905
|
}
|
|
1818
1906
|
async reconfigurePort(baud) {
|
|
1819
1907
|
var _a;
|
|
@@ -2279,13 +2367,17 @@ export class ESPLoader extends EventTarget {
|
|
|
2279
2367
|
return status;
|
|
2280
2368
|
}
|
|
2281
2369
|
async detectFlashSize() {
|
|
2282
|
-
this.logger.
|
|
2370
|
+
this.logger.debug("Detecting Flash Size");
|
|
2283
2371
|
const flashId = await this.flashId();
|
|
2284
2372
|
const manufacturer = flashId & 0xff;
|
|
2285
2373
|
const flashIdLowbyte = (flashId >> 16) & 0xff;
|
|
2286
|
-
|
|
2287
|
-
|
|
2288
|
-
|
|
2374
|
+
const deviceTypeByte = (flashId >> 8) & 0xff;
|
|
2375
|
+
const deviceId = (deviceTypeByte << 8) | flashIdLowbyte;
|
|
2376
|
+
const jedecId = (manufacturer << 16) | deviceId;
|
|
2377
|
+
const mfrName = FLASH_MANUFACTURERS[manufacturer];
|
|
2378
|
+
const deviceName = FLASH_DEVICES[jedecId];
|
|
2379
|
+
this.logger.log(`Flash Manufacturer: ${mfrName || "Unknown"} (0x${manufacturer.toString(16)})`);
|
|
2380
|
+
this.logger.log(`Flash Device: ${deviceName || `Unknown (0x${deviceId.toString(16)})`}`);
|
|
2289
2381
|
this.flashSize = DETECTED_FLASH_SIZES[flashIdLowbyte];
|
|
2290
2382
|
this.logger.log(`Auto-detected Flash size: ${this.flashSize}`);
|
|
2291
2383
|
}
|
|
@@ -2347,7 +2439,7 @@ export class ESPLoader extends EventTarget {
|
|
|
2347
2439
|
// We're transferring over USB, right?
|
|
2348
2440
|
const ramBlock = USB_RAM_BLOCK;
|
|
2349
2441
|
// Upload
|
|
2350
|
-
this.logger.
|
|
2442
|
+
this.logger.debug("Uploading stub...");
|
|
2351
2443
|
for (const field of ["text", "data"]) {
|
|
2352
2444
|
const fieldData = stub[field];
|
|
2353
2445
|
const offset = stub[`${field}_start`];
|
|
@@ -2369,7 +2461,7 @@ export class ESPLoader extends EventTarget {
|
|
|
2369
2461
|
if (pChar != "OHAI") {
|
|
2370
2462
|
throw new Error("Failed to start stub. Unexpected response: " + pChar);
|
|
2371
2463
|
}
|
|
2372
|
-
this.logger.
|
|
2464
|
+
this.logger.debug("Stub is now running...");
|
|
2373
2465
|
const espStubLoader = new EspStubLoader(this.port, this.logger, this);
|
|
2374
2466
|
// Try to autodetect the flash size.
|
|
2375
2467
|
if (!skipFlashDetection) {
|
|
@@ -2827,8 +2919,7 @@ export class ESPLoader extends EventTarget {
|
|
|
2827
2919
|
if (portWillChange) {
|
|
2828
2920
|
// Port will change - release reader/writer and let the port become invalid
|
|
2829
2921
|
await this.releaseReaderWriter();
|
|
2830
|
-
this.logger.
|
|
2831
|
-
this.logger.log("Please select the new port for console mode");
|
|
2922
|
+
this.logger.debug(`${this.chipName} USB-OTG: Port will change after WDT reset`);
|
|
2832
2923
|
// Dispatch event to signal port change
|
|
2833
2924
|
this.dispatchEvent(new CustomEvent("usb-otg-port-change", {
|
|
2834
2925
|
detail: {
|
|
@@ -3065,7 +3156,7 @@ export class ESPLoader extends EventTarget {
|
|
|
3065
3156
|
await this.connectWithResetStrategies();
|
|
3066
3157
|
// Detect chip type
|
|
3067
3158
|
await this.detectChip();
|
|
3068
|
-
this.logger.
|
|
3159
|
+
this.logger.debug(`Reconnected to bootloader: ${this.chipName}`);
|
|
3069
3160
|
}
|
|
3070
3161
|
catch (err) {
|
|
3071
3162
|
// Ensure flag is reset on error
|
|
@@ -3102,7 +3193,7 @@ export class ESPLoader extends EventTarget {
|
|
|
3102
3193
|
}
|
|
3103
3194
|
if (isUsbOtgChip && isUsbJtagOrOtg) {
|
|
3104
3195
|
// USB-OTG devices: Need to reset to bootloader, which will cause port change
|
|
3105
|
-
this.logger.
|
|
3196
|
+
this.logger.debug(`${this.chipName} USB: Resetting to bootloader mode`);
|
|
3106
3197
|
// Perform hardware reset to bootloader (GPIO0=LOW)
|
|
3107
3198
|
// This will cause the port to change from CDC (firmware) to JTAG (bootloader)
|
|
3108
3199
|
try {
|
|
@@ -3119,7 +3210,7 @@ export class ESPLoader extends EventTarget {
|
|
|
3119
3210
|
}
|
|
3120
3211
|
// Wait for reset to complete and port to change
|
|
3121
3212
|
await sleep(500);
|
|
3122
|
-
this.logger.
|
|
3213
|
+
this.logger.debug(`${this.chipName}: Port changed. Please select the bootloader port.`);
|
|
3123
3214
|
// Dispatch event to signal port change
|
|
3124
3215
|
this.dispatchEvent(new CustomEvent("usb-otg-port-change", {
|
|
3125
3216
|
detail: {
|