esp32tool 1.3.5 → 1.3.7

package/dist/const.d.ts

@@ -56,8 +56,10 @@ export declare const ESP32_SPI_MISO_DLEN_OFFS = 44;
 export declare const ESP32_SPI_W0_OFFS = 128;
 export declare const ESP32_UART_DATE_REG_ADDR = 1610612856;
 export declare const ESP32_BOOTLOADER_FLASH_OFFSET = 4096;
+export declare const ESP32_APB_CTL_DATE_ADDR: number;
 export declare const ESP32S2_SPI_REG_BASE = 1061167104;
 export declare const ESP32S2_BASEFUSEADDR = 1061265408;
+export declare const ESP32S2_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32S2_MACFUSEADDR = 1061265476;
 export declare const ESP32S2_SPI_USR_OFFS = 24;
 export declare const ESP32S2_SPI_USR1_OFFS = 28;
@@ -81,6 +83,7 @@ export declare const ESP32S2_UARTDEV_BUF_NO = 1073741076;
 export declare const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2;
 export declare const ESP32S3_SPI_REG_BASE = 1610620928;
 export declare const ESP32S3_BASEFUSEADDR = 1610641408;
+export declare const ESP32S3_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32S3_MACFUSEADDR: number;
 export declare const ESP32S3_SPI_USR_OFFS = 24;
 export declare const ESP32S3_SPI_USR1_OFFS = 28;
@@ -105,6 +108,7 @@ export declare const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3;
 export declare const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4;
 export declare const ESP32C2_SPI_REG_BASE = 1610620928;
 export declare const ESP32C2_BASEFUSEADDR = 1610647552;
+export declare const ESP32C2_EFUSE_BLOCK2_ADDR: number;
 export declare const ESP32C2_MACFUSEADDR: number;
 export declare const ESP32C2_SPI_USR_OFFS = 24;
 export declare const ESP32C2_SPI_USR1_OFFS = 28;
@@ -146,6 +150,7 @@ export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 1610647632;
 export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 1610647640;
 export declare const ESP32C5_SPI_REG_BASE = 1610625024;
 export declare const ESP32C5_BASEFUSEADDR = 1611352064;
+export declare const ESP32C5_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32C5_MACFUSEADDR: number;
 export declare const ESP32C5_SPI_USR_OFFS = 24;
 export declare const ESP32C5_SPI_USR1_OFFS = 28;
@@ -154,11 +159,16 @@ export declare const ESP32C5_SPI_MOSI_DLEN_OFFS = 36;
 export declare const ESP32C5_SPI_MISO_DLEN_OFFS = 40;
 export declare const ESP32C5_SPI_W0_OFFS = 88;
 export declare const ESP32C5_UART_DATE_REG_ADDR = 1610612860;
+export declare const ESP32C5_UART_CLKDIV_REG = 1610612756;
 export declare const ESP32C5_BOOTLOADER_FLASH_OFFSET = 8192;
+export declare const ESP32C5_PCR_SYSCLK_CONF_REG = 1611227408;
+export declare const ESP32C5_PCR_SYSCLK_XTAL_FREQ_V: number;
+export declare const ESP32C5_PCR_SYSCLK_XTAL_FREQ_S = 24;
 export declare const ESP32C5_UARTDEV_BUF_NO = 1082520852;
 export declare const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
 export declare const ESP32C6_SPI_REG_BASE = 1610625024;
 export declare const ESP32C6_BASEFUSEADDR = 1611335680;
+export declare const ESP32C6_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32C6_MACFUSEADDR: number;
 export declare const ESP32C6_SPI_USR_OFFS = 24;
 export declare const ESP32C6_SPI_USR1_OFFS = 28;
@@ -186,6 +196,7 @@ export declare const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN: number;
 export declare const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG: number;
 export declare const ESP32C61_SPI_REG_BASE = 1610625024;
 export declare const ESP32C61_BASEFUSEADDR = 1611352064;
+export declare const ESP32C61_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32C61_MACFUSEADDR: number;
 export declare const ESP32C61_SPI_USR_OFFS = 24;
 export declare const ESP32C61_SPI_USR1_OFFS = 28;
@@ -197,6 +208,7 @@ export declare const ESP32C61_UART_DATE_REG_ADDR = 1610612860;
 export declare const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0;
 export declare const ESP32H2_SPI_REG_BASE = 1610625024;
 export declare const ESP32H2_BASEFUSEADDR = 1611335680;
+export declare const ESP32H2_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32H2_MACFUSEADDR: number;
 export declare const ESP32H2_SPI_USR_OFFS = 24;
 export declare const ESP32H2_SPI_USR1_OFFS = 28;
@@ -216,6 +228,7 @@ export declare const ESP32H2_UARTDEV_BUF_NO = 1082457852;
 export declare const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
 export declare const ESP32H4_SPI_REG_BASE = 1611239424;
 export declare const ESP32H4_BASEFUSEADDR = 1611339776;
+export declare const ESP32H4_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32H4_MACFUSEADDR: number;
 export declare const ESP32H4_SPI_USR_OFFS = 24;
 export declare const ESP32H4_SPI_USR1_OFFS = 28;
@@ -233,6 +246,7 @@ export declare const ESP32H4_RTC_CNTL_WDT_WKEY = 1356348065;
 export declare const ESP32H4_RTC_CNTL_SWD_WKEY = 1356348065;
 export declare const ESP32H21_SPI_REG_BASE = 1610625024;
 export declare const ESP32H21_BASEFUSEADDR = 1611350016;
+export declare const ESP32H21_EFUSE_BLOCK1_ADDR: number;
 export declare const ESP32H21_MACFUSEADDR: number;
 export declare const ESP32H21_SPI_USR_OFFS = 24;
 export declare const ESP32H21_SPI_USR1_OFFS = 28;
@@ -277,6 +291,16 @@ export declare const ESP32P4_GPIO_STRAP_REG = 1343094840;
 export declare const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 8;
 export declare const ESP32P4_RTC_CNTL_OPTION1_REG = 1343291400;
 export declare const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 4;
+export declare const ESP32P4_DR_REG_LPAON_BASE = 1343291392;
+export declare const ESP32P4_DR_REG_PMU_BASE: number;
+export declare const ESP32P4_DR_REG_LP_SYS_BASE: number;
+export declare const ESP32P4_LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG: number;
+export declare const ESP32P4_PMU_EXT_LDO_P0_0P1A_ANA_REG: number;
+export declare const ESP32P4_PMU_ANA_0P1A_EN_CUR_LIM_0: number;
+export declare const ESP32P4_PMU_EXT_LDO_P0_0P1A_REG: number;
+export declare const ESP32P4_PMU_0P1A_TARGET0_0: number;
+export declare const ESP32P4_PMU_0P1A_FORCE_TIEH_SEL_0: number;
+export declare const ESP32P4_PMU_DATE_REG: number;
 export declare const ESP32S31_SPI_REG_BASE = 542113792;
 export declare const ESP32S31_BASEFUSEADDR = 544296960;
 export declare const ESP32S31_EFUSE_BLOCK1_ADDR: number;

package/dist/const.js

@@ -75,8 +75,10 @@ export const ESP32_SPI_MISO_DLEN_OFFS = 0x2c;
 export const ESP32_SPI_W0_OFFS = 0x80;
 export const ESP32_UART_DATE_REG_ADDR = 0x60000078;
 export const ESP32_BOOTLOADER_FLASH_OFFSET = 0x1000;
+export const ESP32_APB_CTL_DATE_ADDR = 0x3ff66000 + 0x7c;
 export const ESP32S2_SPI_REG_BASE = 0x3f402000;
 export const ESP32S2_BASEFUSEADDR = 0x3f41a000;
+export const ESP32S2_EFUSE_BLOCK1_ADDR = ESP32S2_BASEFUSEADDR + 0x044;
 export const ESP32S2_MACFUSEADDR = 0x3f41a044;
 export const ESP32S2_SPI_USR_OFFS = 0x18;
 export const ESP32S2_SPI_USR1_OFFS = 0x1c;
@@ -102,6 +104,7 @@ export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which
 export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use
 export const ESP32S3_SPI_REG_BASE = 0x60002000;
 export const ESP32S3_BASEFUSEADDR = 0x60007000;
+export const ESP32S3_EFUSE_BLOCK1_ADDR = ESP32S3_BASEFUSEADDR + 0x044;
 export const ESP32S3_MACFUSEADDR = 0x60007000 + 0x044;
 export const ESP32S3_SPI_USR_OFFS = 0x18;
 export const ESP32S3_SPI_USR1_OFFS = 0x1c;
@@ -128,6 +131,7 @@ export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG i
 export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used
 export const ESP32C2_SPI_REG_BASE = 0x60002000;
 export const ESP32C2_BASEFUSEADDR = 0x60008800;
+export const ESP32C2_EFUSE_BLOCK2_ADDR = ESP32C2_BASEFUSEADDR + 0x040;
 export const ESP32C2_MACFUSEADDR = ESP32C2_BASEFUSEADDR + 0x040;
 export const ESP32C2_SPI_USR_OFFS = 0x18;
 export const ESP32C2_SPI_USR1_OFFS = 0x1c;
@@ -174,6 +178,7 @@ export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
 export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;
 export const ESP32C5_SPI_REG_BASE = 0x60003000;
 export const ESP32C5_BASEFUSEADDR = 0x600b4800;
+export const ESP32C5_EFUSE_BLOCK1_ADDR = ESP32C5_BASEFUSEADDR + 0x044;
 export const ESP32C5_MACFUSEADDR = 0x600b4800 + 0x044;
 export const ESP32C5_SPI_USR_OFFS = 0x18;
 export const ESP32C5_SPI_USR1_OFFS = 0x1c;
@@ -182,12 +187,18 @@ export const ESP32C5_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C5_SPI_W0_OFFS = 0x58;
 export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
+export const ESP32C5_UART_CLKDIV_REG = 0x60000014;
 export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-C5 Crystal frequency detection registers
+export const ESP32C5_PCR_SYSCLK_CONF_REG = 0x60096110;
+export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_V = 0x7f << 24;
+export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_S = 24;
 // ESP32-C5 USB-JTAG/Serial detection
 export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
 export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 export const ESP32C6_SPI_REG_BASE = 0x60003000;
 export const ESP32C6_BASEFUSEADDR = 0x600b0800;
+export const ESP32C6_EFUSE_BLOCK1_ADDR = ESP32C6_BASEFUSEADDR + 0x044;
 export const ESP32C6_MACFUSEADDR = 0x600b0800 + 0x044;
 export const ESP32C6_SPI_USR_OFFS = 0x18;
 export const ESP32C6_SPI_USR1_OFFS = 0x1c;
@@ -218,6 +229,7 @@ export const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
 export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG
 export const ESP32C61_SPI_REG_BASE = 0x60003000;
 export const ESP32C61_BASEFUSEADDR = 0x600b4800;
+export const ESP32C61_EFUSE_BLOCK1_ADDR = ESP32C61_BASEFUSEADDR + 0x044;
 export const ESP32C61_MACFUSEADDR = 0x600b4800 + 0x044;
 export const ESP32C61_SPI_USR_OFFS = 0x18;
 export const ESP32C61_SPI_USR1_OFFS = 0x1c;
@@ -229,6 +241,7 @@ export const ESP32C61_UART_DATE_REG_ADDR = 0x6000007c;
 export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
 export const ESP32H2_SPI_REG_BASE = 0x60003000;
 export const ESP32H2_BASEFUSEADDR = 0x600b0800;
+export const ESP32H2_EFUSE_BLOCK1_ADDR = ESP32H2_BASEFUSEADDR + 0x044;
 export const ESP32H2_MACFUSEADDR = 0x600b0800 + 0x044;
 export const ESP32H2_SPI_USR_OFFS = 0x18;
 export const ESP32H2_SPI_USR1_OFFS = 0x1c;
@@ -250,6 +263,7 @@ export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which
 export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 export const ESP32H4_SPI_REG_BASE = 0x60099000;
 export const ESP32H4_BASEFUSEADDR = 0x600b1800;
+export const ESP32H4_EFUSE_BLOCK1_ADDR = ESP32H4_BASEFUSEADDR + 0x044;
 export const ESP32H4_MACFUSEADDR = 0x600b1800 + 0x044;
 export const ESP32H4_SPI_USR_OFFS = 0x18;
 export const ESP32H4_SPI_USR1_OFFS = 0x1c;
@@ -268,6 +282,7 @@ export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as
 export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
 export const ESP32H21_SPI_REG_BASE = 0x60003000;
 export const ESP32H21_BASEFUSEADDR = 0x600b4000;
+export const ESP32H21_EFUSE_BLOCK1_ADDR = ESP32H21_BASEFUSEADDR + 0x044;
 export const ESP32H21_MACFUSEADDR = 0x600b4000 + 0x044;
 export const ESP32H21_SPI_USR_OFFS = 0x18;
 export const ESP32H21_SPI_USR1_OFFS = 0x1c;
@@ -318,6 +333,17 @@ export const ESP32P4_GPIO_STRAP_REG = 0x500e0038;
 export const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 0x8; // Not download mode
 export const ESP32P4_RTC_CNTL_OPTION1_REG = 0x50110008;
 export const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x4; // Is download mode forced over USB?
+// Flash power-on related registers and bits needed for ECO6 (Rev 301)
+export const ESP32P4_DR_REG_LPAON_BASE = 0x50110000;
+export const ESP32P4_DR_REG_PMU_BASE = ESP32P4_DR_REG_LPAON_BASE + 0x5000;
+export const ESP32P4_DR_REG_LP_SYS_BASE = ESP32P4_DR_REG_LPAON_BASE + 0x0;
+export const ESP32P4_LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG = ESP32P4_DR_REG_LP_SYS_BASE + 0x10c;
+export const ESP32P4_PMU_EXT_LDO_P0_0P1A_ANA_REG = ESP32P4_DR_REG_PMU_BASE + 0x1bc;
+export const ESP32P4_PMU_ANA_0P1A_EN_CUR_LIM_0 = 1 << 27;
+export const ESP32P4_PMU_EXT_LDO_P0_0P1A_REG = ESP32P4_DR_REG_PMU_BASE + 0x1b8;
+export const ESP32P4_PMU_0P1A_TARGET0_0 = 0xff << 23;
+export const ESP32P4_PMU_0P1A_FORCE_TIEH_SEL_0 = 1 << 7;
+export const ESP32P4_PMU_DATE_REG = ESP32P4_DR_REG_PMU_BASE + 0x3fc;
 export const ESP32S31_SPI_REG_BASE = 0x20500000;
 export const ESP32S31_BASEFUSEADDR = 0x20715000;
 export const ESP32S31_EFUSE_BLOCK1_ADDR = ESP32S31_BASEFUSEADDR + 0x044;

package/dist/esp_loader.d.ts

@@ -84,10 +84,13 @@ export declare class ESPLoader extends EventTarget {
      * Detect chip type using GET_SECURITY_INFO (for newer chips) or magic value (for older chips)
      */
     detectChip(): Promise<void>;
+    getChipRevision(): Promise<number>;
     /**
-     * Get chip revision for ESP32-P4
+     * Power on the flash chip for ESP32-P4 Rev 301 (ECO6)
+     * The flash chip is powered off by default on ECO6, when the default flash
+     * voltage changed from 1.8V to 3.3V. This is to prevent damage to 1.8V flash chips.
      */
-    getChipRevision(): Promise<number>;
+    powerOnFlash(): Promise<void>;
     /**
      * Get security info including chip ID (ESP32-C3 and later)
      */
@@ -204,11 +207,6 @@ export declare class ESPLoader extends EventTarget {
      * This is an alias for rtcWdtResetChipSpecific() for backwards compatibility
      */
     watchdogReset(): Promise<void>;
-    /**
-     * Get chip revision for ESP32-C3
-     * Reads from EFUSE registers and calculates revision
-     */
-    getChipRevisionC3(): Promise<number>;
     /**
      * RTC watchdog timer reset for ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, and ESP32-P4
      * Uses specific registers for each chip family
@@ -265,7 +263,10 @@ export declare class ESPLoader extends EventTarget {
      * Calculate checksum of a blob, as it is defined by the ROM
      */
     checksum(data: number[], state?: number): number;
+    getC5CrystalFreqRomExpect(): Promise<number>;
+    getC5CrystalFreqDetected(): Promise<number>;
     setBaudrate(baud: number): Promise<void>;
+    private setBaudrateC5Rom;
     reconfigurePort(baud: number): Promise<void>;
     /**
      * @name syncWithTimeout