esp32tool 1.1.9 → 1.3.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/.nojekyll +0 -0
- package/README.md +100 -6
- package/apple-touch-icon.png +0 -0
- package/build-electron-cli.cjs +177 -0
- package/build-single-binary.cjs +295 -0
- package/css/light.css +11 -0
- package/css/style.css +261 -41
- package/dist/cli.d.ts +17 -0
- package/dist/cli.js +458 -0
- package/dist/console.d.ts +15 -0
- package/dist/console.js +237 -0
- package/dist/const.d.ts +99 -0
- package/dist/const.js +129 -8
- package/dist/esp_loader.d.ts +244 -22
- package/dist/esp_loader.js +1960 -251
- package/dist/index.d.ts +2 -1
- package/dist/index.js +37 -4
- package/dist/node-usb-adapter.d.ts +47 -0
- package/dist/node-usb-adapter.js +725 -0
- package/dist/stubs/index.d.ts +1 -2
- package/dist/stubs/index.js +4 -0
- package/dist/util/console-color.d.ts +19 -0
- package/dist/util/console-color.js +272 -0
- package/dist/util/line-break-transformer.d.ts +5 -0
- package/dist/util/line-break-transformer.js +17 -0
- package/dist/web/index.js +1 -1
- package/electron/cli-main.cjs +74 -0
- package/electron/main.cjs +338 -0
- package/electron/main.js +7 -2
- package/favicon.ico +0 -0
- package/fix-cli-imports.cjs +127 -0
- package/generate-icons.sh +89 -0
- package/icons/icon-128.png +0 -0
- package/icons/icon-144.png +0 -0
- package/icons/icon-152.png +0 -0
- package/icons/icon-192.png +0 -0
- package/icons/icon-384.png +0 -0
- package/icons/icon-512.png +0 -0
- package/icons/icon-72.png +0 -0
- package/icons/icon-96.png +0 -0
- package/index.html +143 -73
- package/install-android.html +411 -0
- package/js/console.js +269 -0
- package/js/modules/esptool.js +1 -1
- package/js/script.js +750 -175
- package/js/util/console-color.js +282 -0
- package/js/util/line-break-transformer.js +19 -0
- package/js/webusb-serial.js +1017 -0
- package/license.md +1 -1
- package/manifest.json +89 -0
- package/package.cli.json +29 -0
- package/package.json +35 -24
- package/screenshots/desktop.png +0 -0
- package/screenshots/mobile.png +0 -0
- package/src/cli.ts +618 -0
- package/src/console.ts +278 -0
- package/src/const.ts +165 -8
- package/src/esp_loader.ts +2354 -302
- package/src/index.ts +69 -3
- package/src/node-usb-adapter.ts +924 -0
- package/src/stubs/index.ts +4 -1
- package/src/util/console-color.ts +290 -0
- package/src/util/line-break-transformer.ts +20 -0
- package/sw.js +155 -0
package/dist/console.js
ADDED
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@@ -0,0 +1,237 @@
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import { ColoredConsole, coloredConsoleStyles } from "./util/console-color.js";
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import { LineBreakTransformer } from "./util/line-break-transformer.js";
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export class ESP32ToolConsole {
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constructor(port, containerElement, allowInput = true) {
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this.port = port;
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this.containerElement = containerElement;
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this.allowInput = allowInput;
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}
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logs() {
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var _a;
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return ((_a = this.console) === null || _a === void 0 ? void 0 : _a.logs()) || "";
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}
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async init() {
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// Create console HTML
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this.containerElement.innerHTML = `
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<style>
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.esp32tool-console-wrapper {
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background-color: #1c1c1c;
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color: #ddd;
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font-family: "SFMono-Regular", Consolas, "Liberation Mono", Menlo, Courier,
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monospace;
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line-height: 1.45;
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display: flex;
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flex-direction: column;
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height: 100%;
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border: 1px solid #333;
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border-radius: 4px;
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}
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.esp32tool-console-header {
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display: flex;
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justify-content: space-between;
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align-items: center;
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padding: 8px 12px;
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background-color: #2a2a2a;
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border-bottom: 1px solid #333;
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}
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.esp32tool-console-header h3 {
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margin: 0;
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font-size: 14px;
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font-weight: 600;
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}
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.esp32tool-console-controls {
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display: flex;
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gap: 8px;
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}
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.esp32tool-console-controls button {
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padding: 4px 12px;
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font-size: 12px;
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background-color: #444;
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color: #ddd;
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border: 1px solid #555;
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border-radius: 3px;
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cursor: pointer;
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}
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.esp32tool-console-controls button:hover {
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background-color: #555;
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}
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.esp32tool-console-form {
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display: flex;
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align-items: center;
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padding: 0 8px 0 16px;
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background-color: #1c1c1c;
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border-top: 1px solid #333;
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}
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.esp32tool-console-input {
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flex: 1;
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padding: 8px;
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margin: 4px 8px;
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border: 0;
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outline: none;
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background-color: #1c1c1c;
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color: #ddd;
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font-family: "SFMono-Regular", Consolas, "Liberation Mono", Menlo, Courier,
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monospace;
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font-size: 12px;
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}
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${coloredConsoleStyles}
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.esp32tool-console-wrapper .log {
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flex: 1;
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margin: 0;
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border-radius: 0;
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}
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</style>
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<div class="esp32tool-console-wrapper">
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<div class="esp32tool-console-header">
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<h3>ESP Console</h3>
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<div class="esp32tool-console-controls">
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<button id="console-clear-btn">Clear</button>
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<button id="console-reset-btn">Reset Device</button>
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<button id="console-close-btn">Close Console</button>
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</div>
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</div>
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<div class="log"></div>
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${this.allowInput
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? `<form class="esp32tool-console-form">
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<input class="esp32tool-console-input" autofocus placeholder="Type command and press Enter...">
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</form>`
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: ""}
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</div>
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`;
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this.console = new ColoredConsole(this.containerElement.querySelector(".log"));
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// Setup event listeners
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const clearBtn = this.containerElement.querySelector("#console-clear-btn");
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if (clearBtn) {
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clearBtn.addEventListener("click", () => this.clear());
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}
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const resetBtn = this.containerElement.querySelector("#console-reset-btn");
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if (resetBtn) {
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resetBtn.addEventListener("click", () => this.reset());
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}
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const closeBtn = this.containerElement.querySelector("#console-close-btn");
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if (closeBtn) {
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closeBtn.addEventListener("click", () => {
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this.containerElement.dispatchEvent(new CustomEvent("console-close", { bubbles: true }));
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});
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}
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if (this.allowInput) {
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const input = this.containerElement.querySelector(".esp32tool-console-input");
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this.containerElement.addEventListener("click", () => {
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var _a;
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// Only focus input if user didn't select some text
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if (((_a = getSelection()) === null || _a === void 0 ? void 0 : _a.toString()) === "") {
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input.focus();
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}
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});
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const form = this.containerElement.querySelector("form");
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if (form) {
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form.addEventListener("submit", (ev) => {
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ev.preventDefault();
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ev.stopPropagation();
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this._sendCommand();
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});
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}
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input.addEventListener("keydown", (ev) => {
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if (ev.key === "Enter") {
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ev.preventDefault();
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ev.stopPropagation();
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this._sendCommand();
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}
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});
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}
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// Start connection
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const abortController = new AbortController();
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const connection = this._connect(abortController.signal);
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this.cancelConnection = () => {
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abortController.abort();
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return connection;
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};
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}
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async _connect(abortSignal) {
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console.log("Starting console read loop");
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// Check if port.readable is available
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if (!this.port.readable) {
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this.console.addLine("");
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this.console.addLine("");
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this.console.addLine(`Terminal disconnected: Port readable stream not available`);
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console.error("Port readable stream not available - port may need to be reopened at correct baudrate");
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return;
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}
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try {
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await this.port
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.readable.pipeThrough(new TextDecoderStream(), {
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signal: abortSignal,
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})
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.pipeThrough(new TransformStream(new LineBreakTransformer()))
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.pipeTo(new WritableStream({
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write: (chunk) => {
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const cleaned = chunk.replace(/\r\n$/, "\n");
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this.console.addLine(cleaned);
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},
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}));
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if (!abortSignal.aborted) {
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this.console.addLine("");
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this.console.addLine("");
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this.console.addLine("Terminal disconnected");
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}
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}
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catch (e) {
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this.console.addLine("");
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this.console.addLine("");
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this.console.addLine(`Terminal disconnected: ${e}`);
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}
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finally {
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await new Promise((resolve) => setTimeout(resolve, 100));
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console.log("Finished console read loop");
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}
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}
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async _sendCommand() {
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const input = this.containerElement.querySelector(".esp32tool-console-input");
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const command = input.value;
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if (!this.port.writable) {
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this.console.addLine("Terminal disconnected: port not writable");
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return;
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}
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const encoder = new TextEncoder();
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let writer;
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try {
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writer = this.port.writable.getWriter();
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await writer.write(encoder.encode(command + "\r\n"));
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this.console.addLine(`> ${command}`);
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}
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catch (err) {
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this.console.addLine(`Write failed: ${err}`);
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}
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finally {
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if (writer) {
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try {
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writer.releaseLock();
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}
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catch (err) {
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console.error("Ignoring release lock error", err);
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}
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}
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}
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input.value = "";
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input.focus();
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}
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clear() {
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const logElement = this.containerElement.querySelector(".log");
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if (logElement) {
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logElement.innerHTML = "";
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}
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}
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async reset() {
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console.log("Reset device requested from console");
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// Don't use addLine here as stream might already be closed
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// This will be called from script.js with proper reset logic
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const event = new CustomEvent("console-reset");
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this.containerElement.dispatchEvent(event);
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}
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async disconnect() {
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if (this.cancelConnection) {
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await this.cancelConnection();
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this.cancelConnection = undefined;
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}
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}
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}
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package/dist/const.d.ts
CHANGED
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@@ -67,6 +67,18 @@ export declare const ESP32S2_SPI_MISO_DLEN_OFFS = 40;
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export declare const ESP32S2_SPI_W0_OFFS = 88;
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export declare const ESP32S2_UART_DATE_REG_ADDR = 1610612856;
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export declare const ESP32S2_BOOTLOADER_FLASH_OFFSET = 4096;
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export declare const ESP32S2_RTCCNTL_BASE_REG = 1061191680;
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export declare const ESP32S2_RTC_CNTL_WDTWPROTECT_REG: number;
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export declare const ESP32S2_RTC_CNTL_WDTCONFIG0_REG: number;
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export declare const ESP32S2_RTC_CNTL_WDTCONFIG1_REG: number;
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export declare const ESP32S2_RTC_CNTL_WDT_WKEY = 1356348065;
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export declare const ESP32S2_GPIO_STRAP_REG = 1061175352;
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export declare const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK: number;
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export declare const ESP32S2_GPIO_STRAP_VDDSPI_MASK: number;
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export declare const ESP32S2_RTC_CNTL_OPTION1_REG = 1061191976;
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export declare const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 1;
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export declare const ESP32S2_UARTDEV_BUF_NO = 1073741076;
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export declare const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2;
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export declare const ESP32S3_SPI_REG_BASE = 1610620928;
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export declare const ESP32S3_BASEFUSEADDR = 1610641408;
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export declare const ESP32S3_MACFUSEADDR: number;
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@@ -78,6 +90,19 @@ export declare const ESP32S3_SPI_MISO_DLEN_OFFS = 40;
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export declare const ESP32S3_SPI_W0_OFFS = 88;
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export declare const ESP32S3_UART_DATE_REG_ADDR = 1610612864;
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export declare const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0;
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export declare const ESP32S3_RTCCNTL_BASE_REG = 1610645504;
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export declare const ESP32S3_RTC_CNTL_WDTWPROTECT_REG: number;
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export declare const ESP32S3_RTC_CNTL_WDTCONFIG0_REG: number;
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export declare const ESP32S3_RTC_CNTL_WDTCONFIG1_REG: number;
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export declare const ESP32S3_RTC_CNTL_WDT_WKEY = 1356348065;
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export declare const ESP32S3_GPIO_STRAP_REG = 1610629176;
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export declare const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK: number;
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export declare const ESP32S3_GPIO_STRAP_VDDSPI_MASK: number;
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export declare const ESP32S3_RTC_CNTL_OPTION1_REG = 1610645804;
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export declare const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 1;
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+
export declare const ESP32S3_UARTDEV_BUF_NO = 1070526796;
|
|
104
|
+
export declare const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3;
|
|
105
|
+
export declare const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4;
|
|
81
106
|
export declare const ESP32C2_SPI_REG_BASE = 1610620928;
|
|
82
107
|
export declare const ESP32C2_BASEFUSEADDR = 1610647552;
|
|
83
108
|
export declare const ESP32C2_MACFUSEADDR: number;
|
|
@@ -89,8 +114,14 @@ export declare const ESP32C2_SPI_MISO_DLEN_OFFS = 40;
|
|
|
89
114
|
export declare const ESP32C2_SPI_W0_OFFS = 88;
|
|
90
115
|
export declare const ESP32C2_UART_DATE_REG_ADDR = 1610612860;
|
|
91
116
|
export declare const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0;
|
|
117
|
+
export declare const ESP32C2_RTCCNTL_BASE_REG = 1610645504;
|
|
118
|
+
export declare const ESP32C2_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
119
|
+
export declare const ESP32C2_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
120
|
+
export declare const ESP32C2_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
121
|
+
export declare const ESP32C2_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
92
122
|
export declare const ESP32C3_SPI_REG_BASE = 1610620928;
|
|
93
123
|
export declare const ESP32C3_BASEFUSEADDR = 1610647552;
|
|
124
|
+
export declare const ESP32C3_EFUSE_BLOCK1_ADDR: number;
|
|
94
125
|
export declare const ESP32C3_MACFUSEADDR: number;
|
|
95
126
|
export declare const ESP32C3_SPI_USR_OFFS = 24;
|
|
96
127
|
export declare const ESP32C3_SPI_USR1_OFFS = 28;
|
|
@@ -100,6 +131,19 @@ export declare const ESP32C3_SPI_MISO_DLEN_OFFS = 40;
|
|
|
100
131
|
export declare const ESP32C3_SPI_W0_OFFS = 88;
|
|
101
132
|
export declare const ESP32C3_UART_DATE_REG_ADDR = 1610612860;
|
|
102
133
|
export declare const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0;
|
|
134
|
+
export declare const ESP32C3_RTC_CNTL_BASE_REG = 1610645504;
|
|
135
|
+
export declare const ESP32C3_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
136
|
+
export declare const ESP32C3_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
137
|
+
export declare const ESP32C3_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
138
|
+
export declare const ESP32C3_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
139
|
+
export declare const ESP32C3_RTC_CNTL_SWD_WKEY = 2401055018;
|
|
140
|
+
export declare const ESP32C3_RTC_CNTL_SWD_CONF_REG: number;
|
|
141
|
+
export declare const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN: number;
|
|
142
|
+
export declare const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG: number;
|
|
143
|
+
export declare const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
|
|
144
|
+
export declare const ESP32C3_BUF_UART_NO_OFFSET = 24;
|
|
145
|
+
export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 1610647632;
|
|
146
|
+
export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 1610647640;
|
|
103
147
|
export declare const ESP32C5_SPI_REG_BASE = 1610625024;
|
|
104
148
|
export declare const ESP32C5_BASEFUSEADDR = 1611352064;
|
|
105
149
|
export declare const ESP32C5_MACFUSEADDR: number;
|
|
@@ -111,6 +155,8 @@ export declare const ESP32C5_SPI_MISO_DLEN_OFFS = 40;
|
|
|
111
155
|
export declare const ESP32C5_SPI_W0_OFFS = 88;
|
|
112
156
|
export declare const ESP32C5_UART_DATE_REG_ADDR = 1610612860;
|
|
113
157
|
export declare const ESP32C5_BOOTLOADER_FLASH_OFFSET = 8192;
|
|
158
|
+
export declare const ESP32C5_UARTDEV_BUF_NO = 1082520852;
|
|
159
|
+
export declare const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
|
|
114
160
|
export declare const ESP32C6_SPI_REG_BASE = 1610625024;
|
|
115
161
|
export declare const ESP32C6_BASEFUSEADDR = 1611335680;
|
|
116
162
|
export declare const ESP32C6_MACFUSEADDR: number;
|
|
@@ -122,6 +168,22 @@ export declare const ESP32C6_SPI_MISO_DLEN_OFFS = 40;
|
|
|
122
168
|
export declare const ESP32C6_SPI_W0_OFFS = 88;
|
|
123
169
|
export declare const ESP32C6_UART_DATE_REG_ADDR = 1610612860;
|
|
124
170
|
export declare const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0;
|
|
171
|
+
export declare const ESP32C6_DR_REG_LP_WDT_BASE = 1611340800;
|
|
172
|
+
export declare const ESP32C6_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
173
|
+
export declare const ESP32C6_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
174
|
+
export declare const ESP32C6_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
175
|
+
export declare const ESP32C6_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
176
|
+
export declare const ESP32C6_RTC_CNTL_SWD_WKEY = 1356348065;
|
|
177
|
+
export declare const ESP32C6_UARTDEV_BUF_NO = 1082652032;
|
|
178
|
+
export declare const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
|
|
179
|
+
export declare const ESP32C5_C6_DR_REG_LP_WDT_BASE = 1611340800;
|
|
180
|
+
export declare const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
181
|
+
export declare const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
182
|
+
export declare const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
183
|
+
export declare const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
184
|
+
export declare const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG: number;
|
|
185
|
+
export declare const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN: number;
|
|
186
|
+
export declare const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG: number;
|
|
125
187
|
export declare const ESP32C61_SPI_REG_BASE = 1610625024;
|
|
126
188
|
export declare const ESP32C61_BASEFUSEADDR = 1611352064;
|
|
127
189
|
export declare const ESP32C61_MACFUSEADDR: number;
|
|
@@ -144,6 +206,14 @@ export declare const ESP32H2_SPI_MISO_DLEN_OFFS = 40;
|
|
|
144
206
|
export declare const ESP32H2_SPI_W0_OFFS = 88;
|
|
145
207
|
export declare const ESP32H2_UART_DATE_REG_ADDR = 1610612860;
|
|
146
208
|
export declare const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0;
|
|
209
|
+
export declare const ESP32H2_DR_REG_LP_WDT_BASE = 1611340800;
|
|
210
|
+
export declare const ESP32H2_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
211
|
+
export declare const ESP32H2_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
212
|
+
export declare const ESP32H2_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
213
|
+
export declare const ESP32H2_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
214
|
+
export declare const ESP32H2_RTC_CNTL_SWD_WKEY = 1356348065;
|
|
215
|
+
export declare const ESP32H2_UARTDEV_BUF_NO = 1082457852;
|
|
216
|
+
export declare const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
|
|
147
217
|
export declare const ESP32H4_SPI_REG_BASE = 1611239424;
|
|
148
218
|
export declare const ESP32H4_BASEFUSEADDR = 1611339776;
|
|
149
219
|
export declare const ESP32H4_MACFUSEADDR: number;
|
|
@@ -155,6 +225,12 @@ export declare const ESP32H4_SPI_MISO_DLEN_OFFS = 40;
|
|
|
155
225
|
export declare const ESP32H4_SPI_W0_OFFS = 88;
|
|
156
226
|
export declare const ESP32H4_UART_DATE_REG_ADDR: number;
|
|
157
227
|
export declare const ESP32H4_BOOTLOADER_FLASH_OFFSET = 8192;
|
|
228
|
+
export declare const ESP32H4_DR_REG_LP_WDT_BASE = 1611355136;
|
|
229
|
+
export declare const ESP32H4_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
230
|
+
export declare const ESP32H4_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
231
|
+
export declare const ESP32H4_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
232
|
+
export declare const ESP32H4_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
233
|
+
export declare const ESP32H4_RTC_CNTL_SWD_WKEY = 1356348065;
|
|
158
234
|
export declare const ESP32H21_SPI_REG_BASE = 1610625024;
|
|
159
235
|
export declare const ESP32H21_BASEFUSEADDR = 1611350016;
|
|
160
236
|
export declare const ESP32H21_MACFUSEADDR: number;
|
|
@@ -166,6 +242,12 @@ export declare const ESP32H21_SPI_MISO_DLEN_OFFS = 40;
|
|
|
166
242
|
export declare const ESP32H21_SPI_W0_OFFS = 88;
|
|
167
243
|
export declare const ESP32H21_UART_DATE_REG_ADDR = 1610612860;
|
|
168
244
|
export declare const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0;
|
|
245
|
+
export declare const ESP32H21_DR_REG_LP_WDT_BASE = 1611340800;
|
|
246
|
+
export declare const ESP32H21_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
247
|
+
export declare const ESP32H21_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
248
|
+
export declare const ESP32H21_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
249
|
+
export declare const ESP32H21_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
250
|
+
export declare const ESP32H21_RTC_CNTL_SWD_WKEY = 1356348065;
|
|
169
251
|
export declare const ESP32P4_SPI_REG_BASE = 1342754816;
|
|
170
252
|
export declare const ESP32P4_BASEFUSEADDR = 1343410176;
|
|
171
253
|
export declare const ESP32P4_EFUSE_BLOCK1_ADDR: number;
|
|
@@ -178,6 +260,23 @@ export declare const ESP32P4_SPI_MISO_DLEN_OFFS = 40;
|
|
|
178
260
|
export declare const ESP32P4_SPI_W0_OFFS = 88;
|
|
179
261
|
export declare const ESP32P4_UART_DATE_REG_ADDR: number;
|
|
180
262
|
export declare const ESP32P4_BOOTLOADER_FLASH_OFFSET = 8192;
|
|
263
|
+
export declare const ESP32P4_DR_REG_LP_WDT_BASE = 1343315968;
|
|
264
|
+
export declare const ESP32P4_RTC_CNTL_WDTWPROTECT_REG: number;
|
|
265
|
+
export declare const ESP32P4_RTC_CNTL_WDTCONFIG0_REG: number;
|
|
266
|
+
export declare const ESP32P4_RTC_CNTL_WDTCONFIG1_REG: number;
|
|
267
|
+
export declare const ESP32P4_RTC_CNTL_WDT_WKEY = 1356348065;
|
|
268
|
+
export declare const ESP32P4_RTC_CNTL_SWD_CONF_REG: number;
|
|
269
|
+
export declare const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN: number;
|
|
270
|
+
export declare const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG: number;
|
|
271
|
+
export declare const ESP32P4_RTC_CNTL_SWD_WKEY = 1356348065;
|
|
272
|
+
export declare const ESP32P4_UARTDEV_BUF_NO_REV0 = 1341390536;
|
|
273
|
+
export declare const ESP32P4_UARTDEV_BUF_NO_REV300 = 1341914824;
|
|
274
|
+
export declare const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5;
|
|
275
|
+
export declare const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6;
|
|
276
|
+
export declare const ESP32P4_GPIO_STRAP_REG = 1343094840;
|
|
277
|
+
export declare const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 8;
|
|
278
|
+
export declare const ESP32P4_RTC_CNTL_OPTION1_REG = 1343291400;
|
|
279
|
+
export declare const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 4;
|
|
181
280
|
export declare const ESP32S31_SPI_REG_BASE = 542113792;
|
|
182
281
|
export declare const ESP32S31_BASEFUSEADDR = 544296960;
|
|
183
282
|
export declare const ESP32S31_EFUSE_BLOCK1_ADDR: number;
|
package/dist/const.js
CHANGED
|
@@ -63,7 +63,7 @@ export const ESP8266_SPI_MOSI_DLEN_OFFS = -1;
|
|
|
63
63
|
export const ESP8266_SPI_MISO_DLEN_OFFS = -1;
|
|
64
64
|
export const ESP8266_SPI_W0_OFFS = 0x40;
|
|
65
65
|
export const ESP8266_UART_DATE_REG_ADDR = 0x60000078;
|
|
66
|
-
export const ESP8266_BOOTLOADER_FLASH_OFFSET =
|
|
66
|
+
export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0000;
|
|
67
67
|
export const ESP32_SPI_REG_BASE = 0x3ff42000;
|
|
68
68
|
export const ESP32_BASEFUSEADDR = 0x3ff5a000;
|
|
69
69
|
export const ESP32_MACFUSEADDR = 0x3ff5a000;
|
|
@@ -86,6 +86,20 @@ export const ESP32S2_SPI_MISO_DLEN_OFFS = 0x28;
|
|
|
86
86
|
export const ESP32S2_SPI_W0_OFFS = 0x58;
|
|
87
87
|
export const ESP32S2_UART_DATE_REG_ADDR = 0x60000078;
|
|
88
88
|
export const ESP32S2_BOOTLOADER_FLASH_OFFSET = 0x1000;
|
|
89
|
+
// ESP32-S2 RTC Watchdog Timer registers for USB-OTG reset
|
|
90
|
+
export const ESP32S2_RTCCNTL_BASE_REG = 0x3f408000;
|
|
91
|
+
export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = ESP32S2_RTCCNTL_BASE_REG + 0x00ac;
|
|
92
|
+
export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = ESP32S2_RTCCNTL_BASE_REG + 0x0094;
|
|
93
|
+
export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = ESP32S2_RTCCNTL_BASE_REG + 0x0098;
|
|
94
|
+
export const ESP32S2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
|
|
95
|
+
// ESP32-S2 GPIO strap register and boot mode control
|
|
96
|
+
export const ESP32S2_GPIO_STRAP_REG = 0x3f404038;
|
|
97
|
+
export const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
|
|
98
|
+
export const ESP32S2_GPIO_STRAP_VDDSPI_MASK = 1 << 4; // SPI voltage (1.8V vs 3.3V)
|
|
99
|
+
export const ESP32S2_RTC_CNTL_OPTION1_REG = 0x3f408128;
|
|
100
|
+
export const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
|
|
101
|
+
export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which indicates the port in use
|
|
102
|
+
export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use
|
|
89
103
|
export const ESP32S3_SPI_REG_BASE = 0x60002000;
|
|
90
104
|
export const ESP32S3_BASEFUSEADDR = 0x60007000;
|
|
91
105
|
export const ESP32S3_MACFUSEADDR = 0x60007000 + 0x044;
|
|
@@ -96,7 +110,22 @@ export const ESP32S3_SPI_MOSI_DLEN_OFFS = 0x24;
|
|
|
96
110
|
export const ESP32S3_SPI_MISO_DLEN_OFFS = 0x28;
|
|
97
111
|
export const ESP32S3_SPI_W0_OFFS = 0x58;
|
|
98
112
|
export const ESP32S3_UART_DATE_REG_ADDR = 0x60000080;
|
|
99
|
-
export const ESP32S3_BOOTLOADER_FLASH_OFFSET =
|
|
113
|
+
export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0000;
|
|
114
|
+
// ESP32-S3 RTC Watchdog Timer registers for USB-OTG reset
|
|
115
|
+
export const ESP32S3_RTCCNTL_BASE_REG = 0x60008000;
|
|
116
|
+
export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = ESP32S3_RTCCNTL_BASE_REG + 0x00b0;
|
|
117
|
+
export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = ESP32S3_RTCCNTL_BASE_REG + 0x0098;
|
|
118
|
+
export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = ESP32S3_RTCCNTL_BASE_REG + 0x009c;
|
|
119
|
+
export const ESP32S3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
|
|
120
|
+
// ESP32-S3 GPIO strap register and boot mode control
|
|
121
|
+
export const ESP32S3_GPIO_STRAP_REG = 0x60004038;
|
|
122
|
+
export const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
|
|
123
|
+
export const ESP32S3_GPIO_STRAP_VDDSPI_MASK = 1 << 4;
|
|
124
|
+
export const ESP32S3_RTC_CNTL_OPTION1_REG = 0x6000812c;
|
|
125
|
+
export const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
|
|
126
|
+
export const ESP32S3_UARTDEV_BUF_NO = 0x3fcef14c; // Variable in ROM .bss which indicates the port in use
|
|
127
|
+
export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG is used
|
|
128
|
+
export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used
|
|
100
129
|
export const ESP32C2_SPI_REG_BASE = 0x60002000;
|
|
101
130
|
export const ESP32C2_BASEFUSEADDR = 0x60008800;
|
|
102
131
|
export const ESP32C2_MACFUSEADDR = 0x60008800 + 0x044;
|
|
@@ -107,9 +136,16 @@ export const ESP32C2_SPI_MOSI_DLEN_OFFS = 0x24;
|
|
|
107
136
|
export const ESP32C2_SPI_MISO_DLEN_OFFS = 0x28;
|
|
108
137
|
export const ESP32C2_SPI_W0_OFFS = 0x58;
|
|
109
138
|
export const ESP32C2_UART_DATE_REG_ADDR = 0x6000007c;
|
|
110
|
-
export const ESP32C2_BOOTLOADER_FLASH_OFFSET =
|
|
139
|
+
export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0000;
|
|
140
|
+
// ESP32-C2 RTC Watchdog Timer registers
|
|
141
|
+
export const ESP32C2_RTCCNTL_BASE_REG = 0x60008000;
|
|
142
|
+
export const ESP32C2_RTC_CNTL_WDTWPROTECT_REG = ESP32C2_RTCCNTL_BASE_REG + 0x009c;
|
|
143
|
+
export const ESP32C2_RTC_CNTL_WDTCONFIG0_REG = ESP32C2_RTCCNTL_BASE_REG + 0x0084;
|
|
144
|
+
export const ESP32C2_RTC_CNTL_WDTCONFIG1_REG = ESP32C2_RTCCNTL_BASE_REG + 0x0088;
|
|
145
|
+
export const ESP32C2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
|
|
111
146
|
export const ESP32C3_SPI_REG_BASE = 0x60002000;
|
|
112
147
|
export const ESP32C3_BASEFUSEADDR = 0x60008800;
|
|
148
|
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export const ESP32C3_EFUSE_BLOCK1_ADDR = ESP32C3_BASEFUSEADDR + 0x044;
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export const ESP32C3_MACFUSEADDR = 0x60008800 + 0x044;
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export const ESP32C3_SPI_USR_OFFS = 0x18;
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export const ESP32C3_SPI_USR1_OFFS = 0x1c;
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export const ESP32C3_SPI_MISO_DLEN_OFFS = 0x28;
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export const ESP32C3_SPI_W0_OFFS = 0x58;
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export const ESP32C3_UART_DATE_REG_ADDR = 0x6000007c;
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export const ESP32C3_BOOTLOADER_FLASH_OFFSET =
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export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0000;
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// ESP32-C3 RTC Watchdog Timer registers
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export const ESP32C3_RTC_CNTL_BASE_REG = 0x60008000;
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export const ESP32C3_RTC_CNTL_WDTWPROTECT_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00a8;
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export const ESP32C3_RTC_CNTL_WDTCONFIG0_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x0090;
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export const ESP32C3_RTC_CNTL_WDTCONFIG1_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x0094;
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export const ESP32C3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
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export const ESP32C3_RTC_CNTL_SWD_WKEY = 0x8f1d312a;
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export const ESP32C3_RTC_CNTL_SWD_CONF_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00ac;
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export const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 31;
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export const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00b0;
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export const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
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export const ESP32C3_BUF_UART_NO_OFFSET = 24;
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// Note: ESP32C3_BSS_UART_DEV_ADDR is calculated dynamically based on chip revision in esp_loader.ts
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// Revision < 101: 0x3FCDF064, Revision >= 101: 0x3FCDF060
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// ESP32-C3 EFUSE registers for chip revision detection
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export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
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export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;
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export const ESP32C5_SPI_REG_BASE = 0x60003000;
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export const ESP32C5_BASEFUSEADDR = 0x600b4800;
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export const ESP32C5_MACFUSEADDR = 0x600b4800 + 0x044;
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@@ -130,6 +183,9 @@ export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
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export const ESP32C5_SPI_W0_OFFS = 0x58;
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export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
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export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
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// ESP32-C5 USB-JTAG/Serial detection
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export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
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export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
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export const ESP32C6_SPI_REG_BASE = 0x60003000;
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export const ESP32C6_BASEFUSEADDR = 0x600b0800;
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export const ESP32C6_MACFUSEADDR = 0x600b0800 + 0x044;
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@@ -140,7 +196,26 @@ export const ESP32C6_SPI_MOSI_DLEN_OFFS = 0x24;
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export const ESP32C6_SPI_MISO_DLEN_OFFS = 0x28;
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export const ESP32C6_SPI_W0_OFFS = 0x58;
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export const ESP32C6_UART_DATE_REG_ADDR = 0x6000007c;
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export const ESP32C6_BOOTLOADER_FLASH_OFFSET =
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199
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+
export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0000;
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+
// ESP32-C6 RTC Watchdog Timer registers (LP_WDT)
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+
export const ESP32C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
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export const ESP32C6_RTC_CNTL_WDTWPROTECT_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
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+
export const ESP32C6_RTC_CNTL_WDTCONFIG0_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
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export const ESP32C6_RTC_CNTL_WDTCONFIG1_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
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+
export const ESP32C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
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+
export const ESP32C6_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
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207
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+
// ESP32-C6 USB-JTAG/Serial detection
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+
export const ESP32C6_UARTDEV_BUF_NO = 0x4087f580; // Variable in ROM .bss which indicates the port in use
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+
export const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
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|
+
// ESP32-C5/C6 LP Watchdog Timer registers (Low Power WDT)
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+
export const ESP32C5_C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
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export const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
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export const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
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export const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
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215
|
+
export const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY
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+
export const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_SWD_CONFIG_REG
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217
|
+
export const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
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+
export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG
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export const ESP32C61_SPI_REG_BASE = 0x60003000;
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export const ESP32C61_BASEFUSEADDR = 0x600b4800;
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export const ESP32C61_MACFUSEADDR = 0x600b4800 + 0x044;
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@@ -151,7 +226,7 @@ export const ESP32C61_SPI_MOSI_DLEN_OFFS = 0x24;
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export const ESP32C61_SPI_MISO_DLEN_OFFS = 0x28;
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export const ESP32C61_SPI_W0_OFFS = 0x58;
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export const ESP32C61_UART_DATE_REG_ADDR = 0x6000007c;
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|
154
|
-
export const ESP32C61_BOOTLOADER_FLASH_OFFSET =
|
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229
|
+
export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
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|
export const ESP32H2_SPI_REG_BASE = 0x60003000;
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156
231
|
export const ESP32H2_BASEFUSEADDR = 0x600b0800;
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export const ESP32H2_MACFUSEADDR = 0x600b0800 + 0x044;
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|
@@ -162,7 +237,17 @@ export const ESP32H2_SPI_MOSI_DLEN_OFFS = 0x24;
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|
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|
export const ESP32H2_SPI_MISO_DLEN_OFFS = 0x28;
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|
export const ESP32H2_SPI_W0_OFFS = 0x58;
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164
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|
export const ESP32H2_UART_DATE_REG_ADDR = 0x6000007c;
|
|
165
|
-
export const ESP32H2_BOOTLOADER_FLASH_OFFSET =
|
|
240
|
+
export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0000;
|
|
241
|
+
// ESP32-H2 RTC Watchdog Timer registers (LP_WDT)
|
|
242
|
+
export const ESP32H2_DR_REG_LP_WDT_BASE = 0x600b1c00;
|
|
243
|
+
export const ESP32H2_RTC_CNTL_WDTWPROTECT_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_RWDT_WPROTECT_REG
|
|
244
|
+
export const ESP32H2_RTC_CNTL_WDTCONFIG0_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
|
|
245
|
+
export const ESP32H2_RTC_CNTL_WDTCONFIG1_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
|
|
246
|
+
export const ESP32H2_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
|
|
247
|
+
export const ESP32H2_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
|
|
248
|
+
// ESP32-H2 USB-JTAG/Serial detection
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|
249
|
+
export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which indicates the port in use
|
|
250
|
+
export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
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251
|
export const ESP32H4_SPI_REG_BASE = 0x60099000;
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|
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252
|
export const ESP32H4_BASEFUSEADDR = 0x600b1800;
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|
168
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export const ESP32H4_MACFUSEADDR = 0x600b1800 + 0x044;
|
|
@@ -174,6 +259,13 @@ export const ESP32H4_SPI_MISO_DLEN_OFFS = 0x28;
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|
|
174
259
|
export const ESP32H4_SPI_W0_OFFS = 0x58;
|
|
175
260
|
export const ESP32H4_UART_DATE_REG_ADDR = 0x60012000 + 0x7c;
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|
176
261
|
export const ESP32H4_BOOTLOADER_FLASH_OFFSET = 0x2000;
|
|
262
|
+
// ESP32-H4 RTC Watchdog Timer registers
|
|
263
|
+
export const ESP32H4_DR_REG_LP_WDT_BASE = 0x600b5400;
|
|
264
|
+
export const ESP32H4_RTC_CNTL_WDTWPROTECT_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
|
|
265
|
+
export const ESP32H4_RTC_CNTL_WDTCONFIG0_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
|
|
266
|
+
export const ESP32H4_RTC_CNTL_WDTCONFIG1_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
|
|
267
|
+
export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
|
|
268
|
+
export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
|
|
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269
|
export const ESP32H21_SPI_REG_BASE = 0x60003000;
|
|
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270
|
export const ESP32H21_BASEFUSEADDR = 0x600b4000;
|
|
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271
|
export const ESP32H21_MACFUSEADDR = 0x600b4000 + 0x044;
|
|
@@ -184,7 +276,14 @@ export const ESP32H21_SPI_MOSI_DLEN_OFFS = 0x24;
|
|
|
184
276
|
export const ESP32H21_SPI_MISO_DLEN_OFFS = 0x28;
|
|
185
277
|
export const ESP32H21_SPI_W0_OFFS = 0x58;
|
|
186
278
|
export const ESP32H21_UART_DATE_REG_ADDR = 0x6000007c;
|
|
187
|
-
export const ESP32H21_BOOTLOADER_FLASH_OFFSET =
|
|
279
|
+
export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0000;
|
|
280
|
+
// ESP32-H21 RTC Watchdog Timer registers (LP_WDT)
|
|
281
|
+
export const ESP32H21_DR_REG_LP_WDT_BASE = 0x600b1c00;
|
|
282
|
+
export const ESP32H21_RTC_CNTL_WDTWPROTECT_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x001c;
|
|
283
|
+
export const ESP32H21_RTC_CNTL_WDTCONFIG0_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x0000;
|
|
284
|
+
export const ESP32H21_RTC_CNTL_WDTCONFIG1_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
|
|
285
|
+
export const ESP32H21_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
|
|
286
|
+
export const ESP32H21_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
|
|
188
287
|
export const ESP32P4_SPI_REG_BASE = 0x5008d000;
|
|
189
288
|
export const ESP32P4_BASEFUSEADDR = 0x5012d000;
|
|
190
289
|
export const ESP32P4_EFUSE_BLOCK1_ADDR = ESP32P4_BASEFUSEADDR + 0x044;
|
|
@@ -197,6 +296,28 @@ export const ESP32P4_SPI_MISO_DLEN_OFFS = 0x28;
|
|
|
197
296
|
export const ESP32P4_SPI_W0_OFFS = 0x58;
|
|
198
297
|
export const ESP32P4_UART_DATE_REG_ADDR = 0x500ca000 + 0x8c;
|
|
199
298
|
export const ESP32P4_BOOTLOADER_FLASH_OFFSET = 0x2000;
|
|
299
|
+
// ESP32-P4 RTC Watchdog Timer registers
|
|
300
|
+
export const ESP32P4_DR_REG_LP_WDT_BASE = 0x50116000;
|
|
301
|
+
export const ESP32P4_RTC_CNTL_WDTWPROTECT_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_WPROTECT_REG
|
|
302
|
+
export const ESP32P4_RTC_CNTL_WDTCONFIG0_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_CONFIG0_REG
|
|
303
|
+
export const ESP32P4_RTC_CNTL_WDTCONFIG1_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_CONFIG1_REG
|
|
304
|
+
export const ESP32P4_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
|
|
305
|
+
export const ESP32P4_RTC_CNTL_SWD_CONF_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x001c; // RTC_WDT_SWD_CONFIG_REG
|
|
306
|
+
export const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
|
|
307
|
+
export const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0020; // RTC_WDT_SWD_WPROTECT_REG
|
|
308
|
+
export const ESP32P4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // RTC_WDT_SWD_WKEY, same as WDT key in this case
|
|
309
|
+
// ESP32-P4 USB-JTAG/Serial and USB-OTG detection
|
|
310
|
+
// Note: UARTDEV_BUF_NO is dynamic based on chip revision
|
|
311
|
+
// Revision < 300: 0x4FF3FEB0 + 24 = 0x4FF3FEC8
|
|
312
|
+
// Revision >= 300: 0x4FFBFEB0 + 24 = 0x4FFBFEC8
|
|
313
|
+
export const ESP32P4_UARTDEV_BUF_NO_REV0 = 0x4ff3fec8; // Variable in ROM .bss (revision < 300)
|
|
314
|
+
export const ESP32P4_UARTDEV_BUF_NO_REV300 = 0x4ffbfec8; // Variable in ROM .bss (revision >= 300)
|
|
315
|
+
export const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5; // The above var when USB-OTG is used
|
|
316
|
+
export const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6; // The above var when USB-JTAG/Serial is used
|
|
317
|
+
export const ESP32P4_GPIO_STRAP_REG = 0x500e0038;
|
|
318
|
+
export const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 0x8; // Not download mode
|
|
319
|
+
export const ESP32P4_RTC_CNTL_OPTION1_REG = 0x50110008;
|
|
320
|
+
export const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x4; // Is download mode forced over USB?
|
|
200
321
|
export const ESP32S31_SPI_REG_BASE = 0x20500000;
|
|
201
322
|
export const ESP32S31_BASEFUSEADDR = 0x20715000;
|
|
202
323
|
export const ESP32S31_EFUSE_BLOCK1_ADDR = ESP32S31_BASEFUSEADDR + 0x044;
|