easyeda-mcp-pro 0.4.0 → 0.5.2

package/dist/pcb-constraints/errors.js

@@ -0,0 +1,133 @@
+/**
+ * PCB constraints — error codes, issues, and factory helpers.
+ *
+ * Follows the same pattern as `CircuitError` and `NetValidationIssue`:
+ * const-object enums + structured issue interfaces + factory functions.
+ *
+ * @module
+ */
+// ── Error code map ──────────────────────────────────────────────────────────
+/**
+ * Map of friendly names to PCB constraint code entries.
+ * Each entry contains the actual code string, default message, severity, and remediation hint.
+ */
+export const PcbConstraintCodeMap = {
+    MISSING_BOARD_OUTLINE: {
+        code: 'PCB_MISSING_OUTLINE',
+        message: 'Board outline is not defined',
+        severity: 'error',
+        remediationHint: 'Define a board outline with at least 3 polygon points in the PCB intent or board dimensions',
+    },
+    OUTLINE_TOO_SMALL: {
+        code: 'PCB_OUTLINE_TOO_SMALL',
+        message: 'Board outline dimensions are below recommended minimum',
+        severity: 'warning',
+        remediationHint: 'Verify the board dimensions are correct. Very small boards may be difficult to manufacture.',
+    },
+    LAYER_COUNT_MISMATCH: {
+        code: 'PCB_LAYER_COUNT_MISMATCH',
+        message: 'Layer count mismatch between intent and board',
+        severity: 'error',
+        remediationHint: 'For boards with more than 2 layers, a complete layer stackup is required for fabrication',
+    },
+    NO_LAYER_STACK: {
+        code: 'PCB_MISSING_STACKUP',
+        message: 'Detailed layer stackup is not defined',
+        severity: 'warning',
+        remediationHint: 'Define a layer stackup with thickness, material, and copper weight for each layer to ensure manufacturability',
+    },
+    NO_MOUNTING_HOLES: {
+        code: 'PCB_MISSING_MOUNTING_HOLES',
+        message: 'No mounting holes defined on the board',
+        severity: 'warning',
+        remediationHint: 'Add at least 4 mounting holes (one near each corner) for mechanical stability and assembly',
+    },
+    NO_NET_CLASSES: {
+        code: 'PCB_MISSING_NET_CLASSES',
+        message: 'No net classes with routing rules are defined',
+        severity: 'warning',
+        remediationHint: 'Define net classes for power, signal, and high-speed nets to enforce trace width and clearance rules',
+    },
+    INVALID_CLEARANCE: {
+        code: 'PCB_INVALID_CLEARANCE',
+        message: 'Net classes are defined but no clearance rules between them',
+        severity: 'warning',
+        remediationHint: 'Add clearance rules between each pair of net classes (e.g., power-to-signal, high-voltage-to-signal)',
+    },
+    NO_CLEARANCE_RULES: {
+        code: 'PCB_INVALID_CLEARANCE',
+        message: 'No clearance rules defined between net classes',
+        severity: 'warning',
+        remediationHint: 'Add clearance rules between each pair of net classes',
+    },
+    KEEPOUT_VIOLATION: {
+        code: 'PCB_KEEPOUT_VIOLATION',
+        message: 'Placement zones are defined but no keepout/restricted areas',
+        severity: 'warning',
+        remediationHint: 'Consider adding keepout areas to prevent component or track placement in restricted zones',
+    },
+    NO_KEEPOUT_AREAS: {
+        code: 'PCB_KEEPOUT_VIOLATION',
+        message: 'No keepout or restricted areas defined',
+        severity: 'warning',
+        remediationHint: 'Consider adding keepout areas to prevent component or track placement in restricted zones',
+    },
+    NO_PLACEMENT_ZONES: {
+        code: 'PCB_MISSING_PLACEMENT_ZONES',
+        message: 'No placement zones defined for component grouping',
+        severity: 'warning',
+        remediationHint: 'Define placement zones (power, analog, digital, etc.) to guide component placement and improve signal integrity',
+    },
+    MANUFACTURING_OPTIONS_WARNING: {
+        code: 'PCB_MISSING_MANUFACTURING_CONSTRAINTS',
+        message: 'Manufacturing process or production quantity is not specified',
+        severity: 'warning',
+        remediationHint: 'Specify the manufacturing process and target production quantity to select appropriate fabrication requirements',
+    },
+    NO_FIDUCIALS: {
+        code: 'PCB_FIDUCIAL_REQUIRED',
+        message: 'No fiducial marks defined for SMT assembly',
+        severity: 'warning',
+        remediationHint: 'Add at least 3 fiducial marks (global, near board corners) for pick-and-place machine alignment',
+    },
+    NO_TEST_PADS: {
+        code: 'PCB_CONSTRAINT_INTERNAL',
+        message: 'No test pads defined for board testing',
+        severity: 'warning',
+        remediationHint: 'Consider adding test pads for key nets to enable board-level testing and debugging',
+    },
+    HIGH_VOLTAGE_CLEARANCE: {
+        code: 'PCB_HIGH_VOLTAGE_CLEARANCE',
+        message: 'High-voltage domain detected but no clearance rules defined',
+        severity: 'error',
+        remediationHint: 'Define explicit creepage and clearance distances for high-voltage nets. Minimum 4mm clearance for 250V AC is recommended.',
+    },
+};
+// ── Factory helpers ────────────────────────────────────────────────────────
+/**
+ * Create a single PCB constraint issue.
+ */
+export function pcbConstraintIssue(code, message, opts) {
+    return {
+        code,
+        message,
+        severity: opts?.severity ?? 'error',
+        path: opts?.path,
+        constraintType: opts?.constraintType,
+        remediationHint: opts?.remediationHint ?? '',
+        details: opts?.details,
+    };
+}
+/**
+ * Convenience: create an error-severity PCB constraint issue.
+ */
+export function pcbError(code, message, opts) {
+    return pcbConstraintIssue(code, message, { ...opts, severity: 'error' });
+}
+/**
+ * Convenience: create a warning-severity PCB constraint issue.
+ */
+export function pcbWarning(code, message, opts) {
+    return pcbConstraintIssue(code, message, { ...opts, severity: 'warning' });
+}
+//# sourceMappingURL=errors.js.map

package/dist/pcb-constraints/errors.js.map

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package/dist/pcb-constraints/index.d.ts

@@ -0,0 +1,9 @@
+/**
+ * PCB constraints — public API barrel.
+ *
+ * @module
+ */
+export { PcbConstraintCodeMap } from './errors.js';
+export { pcbConstraintIssue, pcbError, pcbWarning } from './errors.js';
+export type { PcbConstraintCode, PcbConstraintIssue, PcbConstraintResult, PcbConstraintInput, ConstraintReport, } from './types.js';
+export { validatePcbConstraints, buildConstraintReport, fromPcbIntent } from './validation.js';

package/dist/pcb-constraints/index.js

@@ -0,0 +1,9 @@
+/**
+ * PCB constraints — public API barrel.
+ *
+ * @module
+ */
+export { PcbConstraintCodeMap } from './errors.js';
+export { pcbConstraintIssue, pcbError, pcbWarning } from './errors.js';
+export { validatePcbConstraints, buildConstraintReport, fromPcbIntent } from './validation.js';
+//# sourceMappingURL=index.js.map

package/dist/pcb-constraints/index.js.map

@@ -0,0 +1 @@
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package/dist/pcb-constraints/types.d.ts

@@ -0,0 +1,102 @@
+/**
+ * PCB constraints — types for constraint validation output.
+ *
+ * @module
+ */
+import type { ConstraintSeverity } from '../circuit/types.js';
+/** Machine-readable code identifying a PCB constraint check. */
+export type PcbConstraintCode = 'PCB_MISSING_OUTLINE' | 'PCB_OUTLINE_TOO_SMALL' | 'PCB_MISSING_STACKUP' | 'PCB_LAYER_COUNT_MISMATCH' | 'PCB_MISSING_MOUNTING_HOLES' | 'PCB_MISSING_NET_CLASSES' | 'PCB_INVALID_CLEARANCE' | 'PCB_KEEPOUT_VIOLATION' | 'PCB_MISSING_PLACEMENT_ZONES' | 'PCB_MISSING_MANUFACTURING_CONSTRAINTS' | 'PCB_FIDUCIAL_REQUIRED' | 'PCB_HIGH_VOLTAGE_CLEARANCE' | 'PCB_CONSTRAINT_INTERNAL';
+/**
+ * A single PCB constraint issue (error or warning).
+ *
+ * Mirrors the pattern from net-validation/errors.ts.
+ */
+export interface PcbConstraintIssue {
+    /** Machine-readable code. */
+    code: PcbConstraintCode;
+    /** Human-readable description. */
+    message: string;
+    /** Dot-notation path to the offending field. */
+    path?: string;
+    /** Whether this blocks validation or is advisory. */
+    severity: 'error' | 'warning';
+    /** The constraint type from CircuitIR (electrical, mechanical, pcb-layout, etc.). */
+    constraintType?: string;
+    /** The severity level from CircuitIR (required, recommended, informational). */
+    constraintSeverity?: ConstraintSeverity;
+    /** Actionable hint for the user. */
+    remediationHint: string;
+    /** Additional context. */
+    details?: Record<string, unknown>;
+}
+export interface PcbConstraintResult {
+    /** True when there are zero errors (warnings are allowed). */
+    valid: boolean;
+    /** Issues that block validation. */
+    errors: PcbConstraintIssue[];
+    /** Advisory issues. */
+    warnings: PcbConstraintIssue[];
+    /** Summary of how many constraints were checked. */
+    summary: {
+        totalChecks: number;
+        passed: number;
+        failed: number;
+        notApplicable: number;
+    };
+}
+/**
+ * Input contract for PCB constraint validation.
+ *
+ * Designed to be created from a CircuitIR or directly from board inspection
+ * data (easyeda_board_layers, easyeda_board_dimensions, etc.).
+ */
+export interface PcbConstraintInput {
+    /** Board dimensions in mm. */
+    widthMm?: number;
+    heightMm?: number;
+    /** Number of copper layers. */
+    layerCount?: number;
+    /** Whether the board outline is defined. */
+    hasOutline?: boolean;
+    /** Whether mounting holes are present. */
+    mountingHoleCount?: number;
+    /** Whether a detailed layer stackup is defined. */
+    hasLayerStack?: boolean;
+    /** Whether net classes with routing rules are defined. */
+    hasNetClasses?: boolean;
+    /** Whether clearance rules are defined. */
+    hasClearanceRules?: boolean;
+    /** Whether keepout areas are defined. */
+    hasKeepoutAreas?: boolean;
+    /** Whether placement zones are defined. */
+    hasPlacementZones?: boolean;
+    /** Whether fiducials are defined. */
+    hasFiducials?: boolean;
+    /** Whether test pads are defined. */
+    hasTestPads?: boolean;
+    /** Whether the design contains high-voltage domains. */
+    hasHighVoltage?: boolean;
+    /** Manufacturing process (lead-free, lead-based, mixed). */
+    manufacturingProcess?: string;
+    /** Whether a quantity is specified. */
+    hasQuantity?: boolean;
+}
+/**
+ * A human-readable explanation of which constraints were applied and
+ * which remain manual/unchecked.
+ */
+export interface ConstraintReport {
+    /** Constraint areas that were checked. */
+    checked: Array<{
+        area: string;
+        status: 'passed' | 'failed' | 'not-applicable';
+        details: string;
+    }>;
+    /** Constraints that cannot be verified automatically (require human review). */
+    manualReviewRequired: Array<{
+        area: string;
+        reason: string;
+    }>;
+    /** Overall verdict. */
+    verdict: 'approved' | 'needs-review' | 'rejected';
+}

package/dist/pcb-constraints/types.js

@@ -0,0 +1,7 @@
+/**
+ * PCB constraints — types for constraint validation output.
+ *
+ * @module
+ */
+export {};
+//# sourceMappingURL=types.js.map

package/dist/pcb-constraints/types.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"types.js","sourceRoot":"","sources":["../../src/pcb-constraints/types.ts"],"names":[],"mappings":"AAAA;;;;GAIG"}

package/dist/pcb-constraints/validation.d.ts

@@ -0,0 +1,70 @@
+/**
+ * PCB constraint validation rules.
+ *
+ * Implements constraint checks that operate on {@link PcbConstraintInput}
+ * and produce structured {@link PcbConstraintIssue}s.
+ *
+ * Rules:
+ *  1. Missing board outline (error)
+ *  2. Board outline too small (warning)
+ *  3. Missing layer stackup (warning)
+ *  4. Layer count mismatch between intent and board (error)
+ *  5. Missing mounting holes (warning)
+ *  6. Missing net classes (warning)
+ *  7. Invalid clearance / creepage (error)
+ *  8. Keepout area violations (error)
+ *  9. Missing placement zones (warning)
+ * 10. Missing manufacturing constraints (warning)
+ * 11. Fiducials recommended for SMT (warning)
+ * 12. High-voltage creepage/clearance (error)
+ *
+ * @module
+ */
+import type { PcbConstraintInput, PcbConstraintResult } from './types.js';
+/**
+ * Run all PCB constraint validation rules against board data.
+ *
+ * Orchestrates 12 rules:
+ *   1. Missing outline         — error  if board outline is not defined
+ *   2. Outline too small       — warning if dimensions are below 5mm
+ *   3. Missing stackup         — warning if no detailed layer stack
+ *   4. Layer count mismatch    — error  if >2 layers without stackup
+ *   5. Missing mounting holes  — warning if zero mounting holes
+ *   6. Missing net classes     — warning if no routing rules
+ *   7. Invalid clearance       — warning if net classes but no clearance rules
+ *   8. Keepout violations      — warning if zones but no keepouts
+ *   9. Missing placement zones — warning if multi-layer without zones
+ *  10. Missing mfg constraints — warning if process/quantity unspecified
+ *  11. Fiducials recommended   — warning if SMT board without fiducials
+ *  12. High-voltage clearance  — error  if HV domain without proper clearance
+ */
+export declare function validatePcbConstraints(input: PcbConstraintInput): PcbConstraintResult;
+/**
+ * Build a human-readable constraint report explaining which constraints
+ * were applied and which require manual review.
+ */
+export declare function buildConstraintReport(input: PcbConstraintInput, result: PcbConstraintResult): import('./types.js').ConstraintReport;
+/**
+ * Create PcbConstraintInput from a CircuitIR PCB intent object.
+ */
+export declare function fromPcbIntent(pcb: {
+    boardOutline?: unknown;
+    layerCount?: number;
+    widthMm?: number;
+    heightMm?: number;
+    layerStack?: unknown[];
+    netClasses?: unknown[];
+    clearanceRules?: unknown[];
+    keepoutAreas?: unknown[];
+    placementZones?: unknown[];
+    mountingHoles?: unknown[];
+    fiducials?: unknown[];
+    testPads?: unknown[];
+    manufacturingProcess?: string;
+    manufacturing?: {
+        process?: string;
+        quantity?: number;
+    };
+    quantity?: number;
+    highVoltage?: boolean;
+}): PcbConstraintInput;

package/dist/pcb-constraints/validation.js

@@ -0,0 +1,309 @@
+/**
+ * PCB constraint validation rules.
+ *
+ * Implements constraint checks that operate on {@link PcbConstraintInput}
+ * and produce structured {@link PcbConstraintIssue}s.
+ *
+ * Rules:
+ *  1. Missing board outline (error)
+ *  2. Board outline too small (warning)
+ *  3. Missing layer stackup (warning)
+ *  4. Layer count mismatch between intent and board (error)
+ *  5. Missing mounting holes (warning)
+ *  6. Missing net classes (warning)
+ *  7. Invalid clearance / creepage (error)
+ *  8. Keepout area violations (error)
+ *  9. Missing placement zones (warning)
+ * 10. Missing manufacturing constraints (warning)
+ * 11. Fiducials recommended for SMT (warning)
+ * 12. High-voltage creepage/clearance (error)
+ *
+ * @module
+ */
+import { pcbError, pcbWarning } from './errors.js';
+// ── Rule: missing board outline ────────────────────────────────────────────
+function checkMissingOutline(input) {
+    const issues = [];
+    if (!input.hasOutline) {
+        issues.push(pcbError('PCB_MISSING_OUTLINE', 'Board outline is not defined', {
+            remediationHint: 'Define a board outline with at least 3 polygon points in the PCB intent or board dimensions',
+        }));
+    }
+    return issues;
+}
+// ── Rule: board outline too small ──────────────────────────────────────────
+const MIN_BOARD_DIMENSION_MM = 5;
+function checkOutlineTooSmall(input) {
+    const issues = [];
+    if (input.widthMm && input.widthMm < MIN_BOARD_DIMENSION_MM) {
+        issues.push(pcbWarning('PCB_OUTLINE_TOO_SMALL', `Board width (${input.widthMm}mm) is below recommended minimum of ${MIN_BOARD_DIMENSION_MM}mm`, {
+            remediationHint: 'Verify the board dimensions are correct. Very small boards may be difficult to manufacture.',
+        }));
+    }
+    if (input.heightMm && input.heightMm < MIN_BOARD_DIMENSION_MM) {
+        issues.push(pcbWarning('PCB_OUTLINE_TOO_SMALL', `Board height (${input.heightMm}mm) is below recommended minimum of ${MIN_BOARD_DIMENSION_MM}mm`, {
+            remediationHint: 'Verify the board dimensions are correct. Very small boards may be difficult to manufacture.',
+        }));
+    }
+    return issues;
+}
+// ── Rule: missing layer stackup ────────────────────────────────────────────
+function checkMissingStackup(input) {
+    const issues = [];
+    if (!input.hasLayerStack) {
+        issues.push(pcbWarning('PCB_MISSING_STACKUP', 'Detailed layer stackup is not defined', {
+            remediationHint: 'Define a layer stackup with thickness, material, and copper weight for each layer to ensure manufacturability',
+            details: { layerCount: input.layerCount },
+        }));
+    }
+    return issues;
+}
+// ── Rule: layer count mismatch ─────────────────────────────────────────────
+const MAX_LAYERS_WITHOUT_STACKUP = 2;
+function checkLayerCountMismatch(input) {
+    const issues = [];
+    if (input.layerCount && input.layerCount > MAX_LAYERS_WITHOUT_STACKUP && !input.hasLayerStack) {
+        issues.push(pcbError('PCB_LAYER_COUNT_MISMATCH', `Board has ${input.layerCount} layers but no detailed stackup is defined`, {
+            remediationHint: 'For boards with more than 2 layers, a complete layer stackup is required for fabrication',
+            details: { layerCount: input.layerCount },
+        }));
+    }
+    return issues;
+}
+// ── Rule: missing mounting holes ───────────────────────────────────────────
+function checkMissingMountingHoles(input) {
+    const issues = [];
+    if (input.mountingHoleCount !== undefined && input.mountingHoleCount === 0) {
+        issues.push(pcbWarning('PCB_MISSING_MOUNTING_HOLES', 'No mounting holes defined on the board', {
+            remediationHint: 'Add at least 4 mounting holes (one near each corner) for mechanical stability and assembly',
+        }));
+    }
+    return issues;
+}
+// ── Rule: missing net classes ──────────────────────────────────────────────
+function checkMissingNetClasses(input) {
+    const issues = [];
+    if (!input.hasNetClasses) {
+        issues.push(pcbWarning('PCB_MISSING_NET_CLASSES', 'No net classes with routing rules are defined', {
+            remediationHint: 'Define net classes for power, signal, and high-speed nets to enforce trace width and clearance rules',
+        }));
+    }
+    return issues;
+}
+// ── Rule: invalid clearance ────────────────────────────────────────────────
+function checkInvalidClearance(input) {
+    const issues = [];
+    if (input.hasNetClasses && !input.hasClearanceRules) {
+        issues.push(pcbWarning('PCB_INVALID_CLEARANCE', 'Net classes are defined but no clearance rules between them', {
+            remediationHint: 'Add clearance rules between each pair of net classes (e.g., power-to-signal, high-voltage-to-signal)',
+        }));
+    }
+    return issues;
+}
+// ── Rule: keepout violations ───────────────────────────────────────────────
+function checkKeepoutAreas(input) {
+    const issues = [];
+    if (!input.hasKeepoutAreas && input.hasPlacementZones) {
+        issues.push(pcbWarning('PCB_KEEPOUT_VIOLATION', 'Placement zones are defined but no keepout/restricted areas', {
+            remediationHint: 'Consider adding keepout areas to prevent component or track placement in restricted zones',
+        }));
+    }
+    return issues;
+}
+// ── Rule: missing placement zones ──────────────────────────────────────────
+function checkMissingPlacementZones(input) {
+    const issues = [];
+    if (!input.hasPlacementZones && input.layerCount && input.layerCount > 1) {
+        issues.push(pcbWarning('PCB_MISSING_PLACEMENT_ZONES', 'No placement zones defined for component grouping', {
+            remediationHint: 'Define placement zones (power, analog, digital, etc.) to guide component placement and improve signal integrity',
+        }));
+    }
+    return issues;
+}
+// ── Rule: missing manufacturing constraints ────────────────────────────────
+function checkMissingManufacturingConstraints(input) {
+    const issues = [];
+    if (!input.manufacturingProcess) {
+        issues.push(pcbWarning('PCB_MISSING_MANUFACTURING_CONSTRAINTS', 'Manufacturing process (lead-free/lead-based) is not specified', {
+            remediationHint: 'Specify the manufacturing process to ensure correct solder mask, pad finish, and assembly requirements',
+        }));
+    }
+    if (!input.hasQuantity) {
+        issues.push(pcbWarning('PCB_MISSING_MANUFACTURING_CONSTRAINTS', 'Production quantity is not specified', {
+            remediationHint: 'Specify the target production quantity to select the appropriate manufacturing process',
+        }));
+    }
+    return issues;
+}
+// ── Rule: fiducials recommended ────────────────────────────────────────────
+function checkFiducials(input) {
+    const issues = [];
+    if (!input.hasFiducials && input.mountingHoleCount && input.mountingHoleCount > 0) {
+        issues.push(pcbWarning('PCB_FIDUCIAL_REQUIRED', 'No fiducial marks defined for SMT assembly', {
+            remediationHint: 'Add at least 3 fiducial marks (global, near board corners) for pick-and-place machine alignment',
+        }));
+    }
+    return issues;
+}
+// ── Rule: high-voltage creepage/clearance ──────────────────────────────────
+function checkHighVoltageClearance(input) {
+    const issues = [];
+    if (input.hasHighVoltage && (!input.hasClearanceRules || !input.hasNetClasses)) {
+        issues.push(pcbError('PCB_HIGH_VOLTAGE_CLEARANCE', 'High-voltage domain detected but no clearance rules defined', {
+            remediationHint: 'Define explicit creepage and clearance distances for high-voltage nets. Minimum 4mm clearance for 250V AC is recommended.',
+        }));
+    }
+    return issues;
+}
+const RULES = [
+    checkMissingOutline,
+    checkOutlineTooSmall,
+    checkMissingStackup,
+    checkLayerCountMismatch,
+    checkMissingMountingHoles,
+    checkMissingNetClasses,
+    checkInvalidClearance,
+    checkKeepoutAreas,
+    checkMissingPlacementZones,
+    checkMissingManufacturingConstraints,
+    checkFiducials,
+    checkHighVoltageClearance,
+];
+// ── Main entry point ───────────────────────────────────────────────────────
+/**
+ * Run all PCB constraint validation rules against board data.
+ *
+ * Orchestrates 12 rules:
+ *   1. Missing outline         — error  if board outline is not defined
+ *   2. Outline too small       — warning if dimensions are below 5mm
+ *   3. Missing stackup         — warning if no detailed layer stack
+ *   4. Layer count mismatch    — error  if >2 layers without stackup
+ *   5. Missing mounting holes  — warning if zero mounting holes
+ *   6. Missing net classes     — warning if no routing rules
+ *   7. Invalid clearance       — warning if net classes but no clearance rules
+ *   8. Keepout violations      — warning if zones but no keepouts
+ *   9. Missing placement zones — warning if multi-layer without zones
+ *  10. Missing mfg constraints — warning if process/quantity unspecified
+ *  11. Fiducials recommended   — warning if SMT board without fiducials
+ *  12. High-voltage clearance  — error  if HV domain without proper clearance
+ */
+export function validatePcbConstraints(input) {
+    const errors = [];
+    const warnings = [];
+    let passed = 0;
+    for (const rule of RULES) {
+        const issues = rule(input);
+        if (issues.length === 0) {
+            passed++;
+        }
+        else {
+            for (const issue of issues) {
+                if (issue.severity === 'error') {
+                    errors.push(issue);
+                }
+                else {
+                    warnings.push(issue);
+                }
+            }
+        }
+    }
+    const totalChecks = RULES.length;
+    const failed = errors.length + warnings.length;
+    const notApplicable = Math.max(0, totalChecks - passed - failed);
+    return {
+        valid: errors.length === 0,
+        errors,
+        warnings,
+        summary: {
+            totalChecks,
+            passed,
+            failed,
+            notApplicable,
+        },
+    };
+}
+/**
+ * Build a human-readable constraint report explaining which constraints
+ * were applied and which require manual review.
+ */
+export function buildConstraintReport(input, result) {
+    const checked = [];
+    const manualReviewRequired = [];
+    // Build checked list from validation results
+    const areaMap = {
+        'Board outline': 'Board outline defines the physical board shape for fabrication',
+        'Board dimensions': 'Minimum dimension check ensures manufacturability',
+        'Layer stackup': 'Layer stackup defines material, thickness, and copper weight per layer',
+        'Layer count': 'Layer count must match between intent and stackup',
+        'Mounting holes': 'Mounting holes provide mechanical mounting and assembly alignment',
+        'Net classes': 'Net classes enforce trace width and clearance for signal integrity',
+        'Clearance rules': 'Clearance rules prevent shorts between different net classes',
+        'Keepout areas': 'Keepout areas prevent component/track placement in restricted zones',
+        'Placement zones': 'Placement zones guide component grouping for optimal layout',
+        'Manufacturing constraints': 'Manufacturing constraints ensure correct fabrication process',
+        Fiducials: 'Fiducial marks enable pick-and-place machine alignment',
+        'High-voltage clearance': 'High-voltage clearance ensures safety against arcing',
+    };
+    // Determine which rules actually produced output
+    const hasErrorsOrWarnings = result.errors.length > 0 || result.warnings.length > 0;
+    if (!input.hasOutline && !hasErrorsOrWarnings) {
+        checked.push({
+            area: 'Board outline',
+            status: 'failed',
+            details: areaMap['Board outline'] ?? '',
+        });
+    }
+    // Add manual review items for things that can't be auto-checked
+    manualReviewRequired.push({
+        area: 'Component placement',
+        reason: 'AI-guided component placement requires human review before applying to PCB layout',
+    });
+    manualReviewRequired.push({
+        area: 'Trace routing',
+        reason: 'Automated trace routing may require manual optimization for signal integrity',
+    });
+    manualReviewRequired.push({
+        area: 'Thermal management',
+        reason: 'Thermal vias and copper pour areas should be verified against thermal simulation',
+    });
+    // Overall verdict
+    let verdict;
+    if (result.errors.length > 0) {
+        verdict = 'rejected';
+    }
+    else if (result.warnings.length > 0 || manualReviewRequired.length > 0) {
+        verdict = 'needs-review';
+    }
+    else {
+        verdict = 'approved';
+    }
+    return {
+        checked,
+        manualReviewRequired,
+        verdict,
+    };
+}
+/**
+ * Create PcbConstraintInput from a CircuitIR PCB intent object.
+ */
+export function fromPcbIntent(pcb) {
+    return {
+        widthMm: pcb.widthMm,
+        heightMm: pcb.heightMm,
+        layerCount: pcb.layerCount,
+        hasOutline: !!(pcb.boardOutline && (Array.isArray(pcb.boardOutline) ? pcb.boardOutline.length > 0 : true)),
+        mountingHoleCount: pcb.mountingHoles?.length ?? 0,
+        hasLayerStack: !!(pcb.layerStack && pcb.layerStack.length > 0),
+        hasNetClasses: !!(pcb.netClasses && pcb.netClasses.length > 0),
+        hasClearanceRules: !!(pcb.clearanceRules && pcb.clearanceRules.length > 0),
+        hasKeepoutAreas: !!(pcb.keepoutAreas && pcb.keepoutAreas.length > 0),
+        hasPlacementZones: !!(pcb.placementZones && pcb.placementZones.length > 0),
+        hasFiducials: !!(pcb.fiducials && pcb.fiducials.length > 0),
+        hasTestPads: !!(pcb.testPads && pcb.testPads.length > 0),
+        hasHighVoltage: pcb.highVoltage ?? false,
+        manufacturingProcess: pcb.manufacturingProcess ?? pcb.manufacturing?.process,
+        hasQuantity: !!(pcb.quantity && pcb.quantity > 0) ||
+            !!(pcb.manufacturing?.quantity && pcb.manufacturing.quantity > 0),
+    };
+}
+//# sourceMappingURL=validation.js.map