devskill 2.0.7 → 2.0.8

package/skills/legacy-circuit-mockups/references/6502.md

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+# MOS Technology 6502 Microprocessor Specification
+
+## 1. Overview
+
+The **MOS Technology 6502** is an 8-bit microprocessor introduced in 1975. It is notable for its low cost, efficient instruction set, and widespread use in early personal computers and game consoles, including the Apple II, Commodore 64, Atari 2600, NES (Ricoh 2A03 variant), and BBC Micro.
+
+---
+
+## 2. General Characteristics
+
+| Feature       | Description              |
+| ------------- | ------------------------ |
+| Data width    | 8-bit                    |
+| Address width | 16-bit                   |
+| Address space | 64 KB (0x0000–0xFFFF)    |
+| Registers     | A, X, Y, SP, PC, P       |
+| Endianness    | Little-endian            |
+| Clock speed   | ~1–3 MHz (original NMOS) |
+| Technology    | NMOS                     |
+
+---
+
+## 3. Programmer-Visible Registers
+
+### 3.1 Accumulator (A)
+
+* 8-bit register
+* Used for arithmetic, logic, and data transfer operations
+
+### 3.2 Index Registers (X, Y)
+
+* 8-bit registers
+* Used for indexing memory, counters, and offsets
+
+### 3.3 Stack Pointer (SP)
+
+* 8-bit register
+* Points to the current stack location
+* Stack resides in page `$0100–$01FF`
+
+### 3.4 Program Counter (PC)
+
+* 16-bit register
+* Holds address of next instruction
+
+### 3.5 Processor Status Register (P)
+
+| Bit | Name | Description                   |
+| --: | ---- | ----------------------------- |
+|   7 | N    | Negative                      |
+|   6 | V    | Overflow                      |
+|   5 | –    | Unused (always set in pushes) |
+|   4 | B    | Break                         |
+|   3 | D    | Decimal Mode                  |
+|   2 | I    | Interrupt Disable             |
+|   1 | Z    | Zero                          |
+|   0 | C    | Carry                         |
+
+---
+
+## 4. Memory Map Conventions
+
+| Address Range | Usage                |
+| ------------- | -------------------- |
+| `$0000–$00FF` | Zero Page            |
+| `$0100–$01FF` | Hardware Stack       |
+| `$0200–$FFFF` | Program / Data / I/O |
+
+### 4.1 Interrupt Vectors
+
+| Vector  | Address       | Description            |
+| ------- | ------------- | ---------------------- |
+| NMI     | `$FFFA–$FFFB` | Non-maskable interrupt |
+| RESET   | `$FFFC–$FFFD` | Reset vector           |
+| IRQ/BRK | `$FFFE–$FFFF` | Interrupt request      |
+
+---
+
+## 5. Addressing Modes
+
+| Mode             | Syntax        | Description             |
+| ---------------- | ------------- | ----------------------- |
+| Implied          | `CLC`         | Operand implied         |
+| Accumulator      | `ASL A`       | Operates on accumulator |
+| Immediate        | `LDA #$10`    | Constant value          |
+| Zero Page        | `LDA $20`     | Zero-page address       |
+| Zero Page,X      | `LDA $20,X`   | Zero-page indexed       |
+| Zero Page,Y      | `LDX $20,Y`   | Zero-page indexed       |
+| Absolute         | `LDA $1234`   | Full 16-bit address     |
+| Absolute,X       | `LDA $1234,X` | Indexed absolute        |
+| Absolute,Y       | `LDA $1234,Y` | Indexed absolute        |
+| Indirect         | `JMP ($1234)` | Pointer-based jump      |
+| Indexed Indirect | `LDA ($20,X)` | X-indexed pointer       |
+| Indirect Indexed | `LDA ($20),Y` | Y-indexed pointer       |
+| Relative         | `BEQ label`   | Branch offset           |
+
+---
+
+## 6. Instruction Set Summary
+
+### 6.1 Load / Store
+
+* `LDA`, `LDX`, `LDY`
+* `STA`, `STX`, `STY`
+
+### 6.2 Register Transfers
+
+* `TAX`, `TAY`, `TXA`, `TYA`, `TSX`, `TXS`
+
+### 6.3 Stack Operations
+
+* `PHA`, `PLA`, `PHP`, `PLP`
+
+### 6.4 Arithmetic
+
+* `ADC` – Add with Carry
+* `SBC` – Subtract with Carry
+
+### 6.5 Logical
+
+* `AND`, `ORA`, `EOR`
+
+### 6.6 Shifts and Rotates
+
+* `ASL`, `LSR`, `ROL`, `ROR`
+
+### 6.7 Increment / Decrement
+
+* `INC`, `INX`, `INY`
+* `DEC`, `DEX`, `DEY`
+
+### 6.8 Comparisons
+
+* `CMP`, `CPX`, `CPY`
+
+### 6.9 Branching
+
+* `BEQ`, `BNE`, `BMI`, `BPL`, `BCS`, `BCC`, `BVS`, `BVC`
+
+### 6.10 Jumps & Subroutines
+
+* `JMP`, `JSR`, `RTS`, `RTI`
+
+### 6.11 Status Flag Control
+
+* `CLC`, `SEC`, `CLI`, `SEI`, `CLV`, `CLD`, `SED`
+
+### 6.12 System Control
+
+* `BRK`, `NOP`
+
+---
+
+## 7. Cycle Timing (General)
+
+* Most instructions execute in **2–7 cycles**
+* Additional cycles may be added for:
+
+  * Page boundary crossings
+  * Taken branches
+
+---
+
+## 8. Decimal Mode
+
+When the **D flag** is set:
+
+* `ADC` and `SBC` operate using **BCD arithmetic**
+* Only valid on NMOS 6502 (behavior varies on CMOS derivatives)
+
+---
+
+## 9. Known Hardware Quirks
+
+* `JMP (addr)` indirect bug: page boundary wraparound
+
+  * Example: `JMP ($10FF)` reads from `$10FF` and `$1000`
+* No dedicated multiply or divide instructions
+* Stack is fixed to page `$01xx`
+
+---
+
+## 10. Variants and Derivatives
+
+| Variant | Notes                               |
+| ------- | ----------------------------------- |
+| 6502    | Original NMOS                       |
+| 65C02   | CMOS, fixes bugs, adds instructions |
+| 2A03    | NES variant, decimal mode disabled  |
+| 6510    | Adds I/O port (Commodore 64)        |
+
+---
+
+## 11. Example Code
+
+```asm
+        LDX #$00
+loop:   INX
+        TXA
+        STA $0200,X
+        CPX #$10
+        BNE loop
+        BRK
+```
+
+---
+
+## 12. References
+
+* <https://syncopate.us/books/Synertek6502ProgrammingManual.html>
+* <https://en.wikipedia.org/wiki/MOS_Technology_6502>
+* <https://web.archive.org/web/20061114024257/http://www.westerndesigncenter.com/wdc/documentation/Programmanual.pdf>
+* Tutorial excerpts from <https://wilsonminesco.com/6502primer/>
+  * <https://wilsonminesco.com/6502primer/LogicFamilies.html>
+  * <https://wilsonminesco.com/6502primer/ClkGen.html>
+  * <https://wilsonminesco.com/6502primer/RSTreqs.html>
+  * <https://wilsonminesco.com/6502primer/displays.html>
+  * <https://wilsonminesco.com/6502primer/debug.html>
+  * <https://wilsonminesco.com/6502primer/potpourri.html>
+
+---

package/skills/legacy-circuit-mockups/references/6522.md

@@ -0,0 +1,211 @@
+# MOS Technology 6522 Versatile Interface Adapter (VIA)
+
+## 1. Overview
+
+The **MOS Technology 6522 VIA** is a general-purpose I/O controller designed to interface the 6502 family of microprocessors with external peripherals. Introduced in the mid-1970s, it provides parallel I/O ports, timers, shift register support, and interrupt handling. The 6522 is widely used in systems such as the Commodore PET, VIC-20, Apple II, BBC Micro, and many 6502-based embedded designs.
+
+---
+
+## 2. General Characteristics
+
+| Feature        | Description                      |
+| -------------- | -------------------------------- |
+| Data width     | 8-bit                            |
+| Addressing     | Memory-mapped I/O                |
+| Registers      | 16 (4-bit register select)       |
+| I/O ports      | Two 8-bit ports (Port A, Port B) |
+| Timers         | Two 16-bit timers                |
+| Shift register | 8-bit serial I/O                 |
+| Interrupts     | Maskable, multiple sources       |
+| Clock          | System clock (φ2)                |
+
+---
+
+## 3. Pin Functions (Logical)
+
+### 3.1 Port A (PA0-PA7)
+
+* 8-bit bidirectional parallel I/O
+* Handshake support via CA1 / CA2
+
+### 3.2 Port B (PB0-PB7)
+
+* 8-bit bidirectional parallel I/O
+* Handshake support via CB1 / CB2
+* PB6 and PB7 may be controlled by Timer 1
+
+### 3.3 Control Pins
+
+| Pin       | Description                           |
+| --------- | ------------------------------------- |
+| CA1 / CB1 | Interrupt-capable control inputs      |
+| CA2 / CB2 | Handshake / pulse / interrupt pins    |
+| IRQ       | Interrupt request output (active low) |
+| RESET     | Reset input                           |
+
+---
+
+## 4. Register Map
+
+Registers are selected using 4 address lines (RS0-RS3). The base address is system-defined.
+
+| Offset | Register  | Description                          |
+| -----: | --------- | ------------------------------------ |
+|     $0 | ORB       | Output Register B                    |
+|     $1 | ORA / IRB | Output Register A / Input Register B |
+|     $2 | DDRB      | Data Direction Register B            |
+|     $3 | DDRA      | Data Direction Register A            |
+|     $4 | T1C-L     | Timer 1 Counter Low                  |
+|     $5 | T1C-H     | Timer 1 Counter High                 |
+|     $6 | T1L-L     | Timer 1 Latch Low                    |
+|     $7 | T1L-H     | Timer 1 Latch High                   |
+|     $8 | T2C-L     | Timer 2 Counter Low                  |
+|     $9 | T2C-H     | Timer 2 Counter High                 |
+|     $A | SR        | Shift Register                       |
+|     $B | ACR       | Auxiliary Control Register           |
+|     $C | PCR       | Peripheral Control Register          |
+|     $D | IFR       | Interrupt Flag Register              |
+|     $E | IER       | Interrupt Enable Register            |
+|     $F | ORA / IRA | Output Register A / Input Register A |
+
+---
+
+## 5. Data Direction Registers (DDRA / DDRB)
+
+Each bit controls the direction of its corresponding port pin:
+
+* `0` = Input
+* `1` = Output
+
+```text
+DDRB bit = 1  PBx is output
+DDRB bit = 0  PBx is input
+```
+
+---
+
+## 6. Timers
+
+### 6.1 Timer 1 (T1)
+
+* 16-bit down counter
+* Can operate in one-shot or free-running mode
+* Can toggle PB7 on timeout
+* Generates interrupts
+
+### 6.2 Timer 2 (T2)
+
+* 16-bit down counter
+* Supports pulse counting on PB6
+* One-shot operation only
+
+---
+
+## 7. Shift Register (SR)
+
+* 8-bit shift register
+* Can shift data in or out
+* Clock source selectable via ACR
+* Often used for serial communication or keyboard scanning
+
+---
+
+## 8. Control Registers
+
+### 8.1 Auxiliary Control Register (ACR)
+
+| Bit | Function                           |
+| --: | ---------------------------------- |
+|   7 | Timer 1 control (PB7 output)       |
+|   6 | Timer 1 mode (free-run / one-shot) |
+|   5 | Timer 2 control                    |
+|   4 | Shift register mode                |
+|   3 | Shift register clock source        |
+|   2 | Port B latching                    |
+|   1 | Port A latching                    |
+|   0 | Unused                             |
+
+### 8.2 Peripheral Control Register (PCR)
+
+Controls CA1, CA2, CB1, CB2 behavior:
+
+* Input/output mode
+* Active edge selection
+* Pulse or handshake modes
+
+---
+
+## 9. Interrupt System
+
+### 9.1 Interrupt Flag Register (IFR)
+
+| Bit | Source                             |
+| --: | ---------------------------------- |
+|   7 | IRQ status (any enabled interrupt) |
+|   6 | Timer 1                            |
+|   5 | Timer 2                            |
+|   4 | CB1                                |
+|   3 | CB2                                |
+|   2 | Shift Register                     |
+|   1 | CA1                                |
+|   0 | CA2                                |
+
+### 9.2 Interrupt Enable Register (IER)
+
+* Bit 7 determines set/clear mode:
+
+  * `1` = set bits
+  * `0` = clear bits
+
+```text
+Write $80 | mask  enable interrupts
+Write $00 | mask  disable interrupts
+```
+
+---
+
+## 10. Reset Behavior
+
+On RESET:
+
+* All DDR bits cleared (ports default to input)
+* Timers stopped
+* Shift register disabled
+* Interrupts disabled
+
+---
+
+## 11. Timing Notes
+
+* VIA registers are accessed synchronously with φ2
+* Timer counters decrement once per φ2 cycle
+* Some operations have side effects when reading/writing registers
+
+---
+
+## 12. Common Use Cases
+
+* Keyboard and joystick interfaces
+* Parallel printer interfaces
+* Timers and event counting
+* Simple serial communications
+* General-purpose GPIO expansion
+
+---
+
+## 13. Variants and Related Chips
+
+| Chip  | Notes                         |
+| ----- | ----------------------------- |
+| 6522  | Original NMOS VIA             |
+| 65C22 | CMOS VIA, faster, lower power |
+| 6520  | Earlier PIA (simpler)         |
+
+---
+
+## 14. References
+
+* <https://en.wikipedia.org/wiki/MOS_Technology_6522>
+* <https://grokipedia.com/page/MOS_Technology_6522>
+
+---

package/skills/legacy-circuit-mockups/references/6C62256.md

@@ -0,0 +1,177 @@
+# AS6C62256 32K x 8 Low-Power CMOS SRAM Specification
+
+## 1. Overview
+
+The **AS6C62256** is a **256 Kbit (32K x 8)** low-power CMOS static random-access memory (SRAM) manufactured by Alliance Memory (and second-sourced by others). It is fully compatible with common 28-pin SRAM pinouts and is widely used in **6502**, **Z80**, and other 8-bit microprocessor systems for read/write memory.
+
+The device offers fast access times, simple control logic, and very low standby power consumption.
+
+---
+
+## 2. General Characteristics
+
+| Feature           | Description                       |
+| ----------------- | --------------------------------- |
+| Memory size       | 256 Kbits (32 KB)                 |
+| Organization      | 32,768 x 8 bits                   |
+| Data bus          | 8-bit                             |
+| Address bus       | 15-bit (A0-A14)                   |
+| Technology        | CMOS SRAM                         |
+| Access time       | 55 ns / 70 ns (variant dependent) |
+| Operating voltage | 5 V ± 10%                          |
+| Standby current   | < 1 µA (typical)                  |
+| Package types     | DIP-28, SOJ-28, TSOP-28           |
+
+---
+
+## 3. Pin Configuration (Logical)
+
+### 3.1 Address Pins (A0-A14)
+
+* Select one of 32,768 memory locations
+* Address must be stable during read or write cycle
+
+### 3.2 Data Pins (I/O0-I/O7)
+
+* Bidirectional tri-state data bus
+* High-impedance when not enabled
+
+### 3.3 Control Pins
+
+| Pin | Description                |
+| --- | -------------------------- |
+| CE# | Chip Enable (active low)   |
+| OE# | Output Enable (active low) |
+| WE# | Write Enable (active low)  |
+| VCC | +5 V power supply          |
+| GND | Ground                     |
+
+---
+
+## 4. Memory Organization
+
+* Linear address space from `$0000` to `$7FFF`
+* Each address corresponds to one byte (8 bits)
+
+```text
+Address range: 0000h - 7FFFh
+Data width:    8 bits
+```
+
+---
+
+## 5. Read Operation
+
+### 5.1 Read Cycle Conditions
+
+| Signal | State |
+| ------ | ----- |
+| CE?    | LOW   |
+| OE?    | LOW   |
+| WE?    | HIGH  |
+
+* Data becomes valid after access time (tAA)
+* Outputs remain valid while CE? and OE? are LOW
+* Outputs are high-impedance when CE? or OE? is HIGH
+
+---
+
+## 6. Write Operation
+
+### 6.1 Write Cycle Conditions
+
+| Signal | State       |
+| ------ | ----------- |
+| CE?    | LOW         |
+| OE?    | HIGH or LOW |
+| WE?    | LOW pulse   |
+
+* Data is written on the rising edge of WE? or CE?
+* Address and data must be stable during write window
+* No internal write delay (true SRAM behavior)
+
+---
+
+## 7. Timing Notes (Summary)
+
+| Parameter            | Typical  |
+| -------------------- | -------- |
+| Address access (tAA) | 55-70 ns |
+| CE? access (tACE)    | 55-70 ns |
+| OE? access (tOE)     | 25-35 ns |
+| Write cycle time     | ≥ 55 ns  |
+
+---
+
+## 8. Power Modes
+
+### 8.1 Active Mode
+
+* CE? = LOW
+* Normal read/write operation
+
+### 8.2 Standby Mode
+
+* CE? = HIGH
+* Data retained
+* Very low power consumption
+
+---
+
+## 9. Reset and Power-Up Behavior
+
+* No reset pin required
+* Data is undefined at power-up
+* Memory contents preserved only while VCC is present
+
+---
+
+## 10. Typical System Integration (6502 Example)
+
+```text
+Mapped at:     $0000 - $7FFF
+CE?   decoded address
+OE?   R/W?
+WE?   inverted R/W?
+```
+
+---
+
+## 11. Absolute Maximum Ratings (Summary)
+
+| Parameter     | Rating                |
+| ------------- | --------------------- |
+| VCC           | -0.5 V to +6.5 V      |
+| Input voltage | -0.5 V to VCC + 0.5 V |
+| Storage temp  | -65 °C to +150 °C     |
+
+---
+
+## 12. Compatible and Equivalent Devices
+
+| Device    | Notes           |
+| --------- | --------------- |
+| AS6C62256 | Alliance Memory |
+| CY62256   | Cypress         |
+| HM62256   | Hitachi         |
+| KM62256   | Samsung         |
+| IS62C256  | ISSI            |
+
+---
+
+## 13. Common Use Cases
+
+* Main RAM for 6502 / Z80 systems
+* Video buffers and frame memory
+* Embedded systems requiring fast R/W memory
+* Retrocomputer SBC designs
+
+---
+
+## 14. References
+
+* <https://www.alliancememory.com/wp-content/uploads/AS6C62256-23-March-2016-rev1.2.pdf>
+* <https://www.futurlec.com/Datasheet/Memory/62256.pdf>
+* <https://www.malinov.com/sergeys-blog/homebrew-notes.html>
+
+---