cyberchef 10.22.1 → 10.24.0

package/tests/operations/tests/A1Z26CipherDecode.mjs

@@ -0,0 +1,33 @@
+/**
+ * A1Z26 Cipher Decode tests
+ *
+ * @author brick-pixel
+ * @copyright Crown Copyright 2026
+ * @license Apache-2.0
+ */
+import TestRegister from "../../lib/TestRegister.mjs";
+
+TestRegister.addTests([
+    {
+        "name": "A1Z26 Cipher Decode: basic decode",
+        "input": "8 5 12 12 15",
+        "expectedOutput": "hello",
+        "recipeConfig": [
+            {
+                "op": "A1Z26 Cipher Decode",
+                "args": ["Space"]
+            }
+        ]
+    },
+    {
+        "name": "A1Z26 Cipher Decode: empty input returns empty string",
+        "input": "",
+        "expectedOutput": "",
+        "recipeConfig": [
+            {
+                "op": "A1Z26 Cipher Decode",
+                "args": ["Space"]
+            }
+        ]
+    }
+]);

package/tests/operations/tests/AnalyseUUID.mjs

@@ -0,0 +1,66 @@
+/**
+ * Analyse UUID tests
+ *
+ * @author ko80240 [csk.dev@proton.me]
+ * @copyright Crown Copyright 2023
+ * @license Apache-2.0
+ */
+import TestRegister from "../../lib/TestRegister.mjs";
+
+TestRegister.addTests([
+    {
+        "name": "Analyse UUID: v1 UUID extracts timestamp, clock, and node",
+        "input": "cefa1760-28ee-11f1-9f95-1fb76af3e239",
+        "expectedOutput": "Version:\n1\n\nTimestamp:\n1774514156502\n\nTimestamp (ISO):\n2026-03-26T08:35:56.502Z\n\nNode:\n1F:B7:6A:F3:E2:39\n\nClock:\n8085\n\nUUID Integer:\n275119515460318071558429785403790975545",
+        "recipeConfig": [
+            {
+                "op": "Analyse UUID",
+                "args": [true]
+            }
+        ]
+    },
+    {
+        "name": "Analyse UUID: v7 UUID extracts timestamp, randA, and randB",
+        "input": "019d294a-af64-7728-9524-26da08f50708",
+        "expectedOutput": "Version:\n7\n\nTimestamp:\n1774514253668\n\nTimestamp (ISO):\n2026-03-26T08:37:33.668Z\n\nRand A:\n1832\n\nRand B:\n952426DA08F50708\n\nUUID Integer:\n2145256098533991595556290452700595976",
+        "recipeConfig": [
+            {
+                "op": "Analyse UUID",
+                "args": [true]
+            }
+        ]
+    },
+    {
+        "name": "Analyse UUID: v4 UUID should show no metadata - not possible",
+        "input": "f47ac10b-58cc-4372-a567-0e02b2c3d479",
+        "expectedOutput": "Version:\n4\n\nNo metadata available. Only versions 1, 6, 7 are supported.\n\nUUID Integer:\n324969006592305634633390616021200786553",
+        "recipeConfig": [
+            {
+                "op": "Analyse UUID",
+                "args": [true]
+            }
+        ]
+    },
+    {
+        "name": "Analyse UUID: if the 'Include Metadata' option is false it should return not metadata",
+        "input": "cefa1760-28ee-11f1-9f95-1fb76af3e239",
+        "expectedOutput": "Version:\n1\n\nUUID Integer:\n275119515460318071558429785403790975545",
+        "recipeConfig": [
+            {
+                "op": "Analyse UUID",
+                "args": [false]
+            }
+        ]
+    },
+    {
+        "name": "Analyse UUID: invalid UUID should return error message",
+        "input": "not-a-uuid",
+        "expectedOutput": "Invalid UUID",
+        "recipeConfig": [
+            {
+                "op": "Analyse UUID",
+                "args": [true]
+            }
+        ]
+    }
+]);

package/tests/operations/tests/DisassembleARM.mjs

@@ -0,0 +1,377 @@
+/**
+ * Disassemble ARM tests.
+ *
+ * @author MedjedThomasXM
+ *
+ * @copyright Crown Copyright 2024
+ * @license Apache-2.0
+ */
+import TestRegister from "../../lib/TestRegister.mjs";
+
+TestRegister.addTests([
+    // ==================== ARM32 TESTS ====================
+    {
+        name: "Disassemble ARM: ARM32 NOP (mov r0, r0)",
+        input: "00 00 a0 e1",
+        expectedMatch: /mov\s+r0,\s*r0/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 bx lr",
+        input: "1e ff 2f e1",
+        expectedMatch: /bx\s+lr/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 push {fp, lr}",
+        input: "00 48 2d e9",
+        expectedMatch: /push\s+\{fp,\s*lr\}/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 add fp, sp, #4",
+        input: "04 b0 8d e2",
+        expectedMatch: /add\s+fp,\s*sp/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 ldr r0, [r1]",
+        input: "00 00 91 e5",
+        expectedMatch: /ldr\s+r0,\s*\[r1\]/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 str r0, [r1]",
+        input: "00 00 81 e5",
+        expectedMatch: /str\s+r0,\s*\[r1\]/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 bl (branch link)",
+        input: "00 00 00 eb",
+        expectedMatch: /bl\s+/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 mul r0, r1, r2",
+        input: "91 02 00 e0",
+        expectedMatch: /mul\s+r0,\s*r1,\s*r2/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+
+    // ==================== ARM32 THUMB TESTS ====================
+    {
+        name: "Disassemble ARM: Thumb mov r0, r0",
+        input: "00 46",
+        expectedMatch: /mov\s+r0,\s*r0/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "Thumb", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: Thumb bx lr",
+        input: "70 47",
+        expectedMatch: /bx\s+lr/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "Thumb", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: Thumb push {r4, lr}",
+        input: "10 b5",
+        expectedMatch: /push\s+\{r4,\s*lr\}/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "Thumb", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: Thumb pop {r4, pc}",
+        input: "10 bd",
+        expectedMatch: /pop\s+\{r4,\s*pc\}/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "Thumb", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+
+    // ==================== ARM64 TESTS ====================
+    {
+        name: "Disassemble ARM: ARM64 ret",
+        input: "c0 03 5f d6",
+        expectedMatch: /ret/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 mov x0, #0",
+        input: "00 00 80 d2",
+        expectedMatch: /mov[z]?\s+x0,\s*#0/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 stp x29, x30, [sp, #-16]!",
+        input: "fd 7b bf a9",
+        expectedMatch: /stp\s+x29,\s*x30,\s*\[sp/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 ldp x29, x30, [sp], #16",
+        input: "fd 7b c1 a8",
+        expectedMatch: /ldp\s+x29,\s*x30,\s*\[sp\]/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 add x0, x1, x2",
+        input: "20 00 02 8b",
+        expectedMatch: /add\s+x0,\s*x1,\s*x2/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 sub x0, x1, x2",
+        input: "20 00 02 cb",
+        expectedMatch: /sub\s+x0,\s*x1,\s*x2/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 mul x0, x1, x2",
+        input: "20 7c 02 9b",
+        expectedMatch: /mul\s+x0,\s*x1,\s*x2/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 ldr x0, [x1]",
+        input: "20 00 40 f9",
+        expectedMatch: /ldr\s+x0,\s*\[x1\]/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 str x0, [x1]",
+        input: "20 00 00 f9",
+        expectedMatch: /str\s+x0,\s*\[x1\]/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 bl (branch link)",
+        input: "00 00 00 94",
+        expectedMatch: /bl\s+/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 cbz x0",
+        input: "00 00 00 b4",
+        expectedMatch: /cbz\s+x0/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 cbnz x0",
+        input: "00 00 00 b5",
+        expectedMatch: /cbnz\s+x0/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 sub sp, sp, #0x20",
+        input: "ff 83 00 d1",
+        expectedMatch: /sub\s+sp,\s*sp/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 add sp, sp, #0x20",
+        input: "ff 83 00 91",
+        expectedMatch: /add\s+sp,\s*sp/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+
+    // ==================== MULTI-INSTRUCTION TESTS ====================
+    {
+        name: "Disassemble ARM: ARM32 multiple instructions",
+        input: "00 48 2d e9 04 b0 8d e2 00 00 a0 e1 00 88 bd e8",
+        expectedMatch: /push.*\n.*add.*\n.*mov.*\n.*pop/s,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM64 function prologue/epilogue",
+        input: "fd 7b bf a9 fd 03 00 91 00 00 80 52 fd 7b c1 a8 c0 03 5f d6",
+        expectedMatch: /stp.*\n.*mov.*\n.*mov.*\n.*ldp.*\n.*ret/s,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+
+    // ==================== ADDRESS TESTS ====================
+    {
+        name: "Disassemble ARM: ARM64 with start address 0x1000",
+        input: "c0 03 5f d6",
+        expectedMatch: /0x00001000/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 4096, true, true],
+            },
+        ],
+    },
+    {
+        name: "Disassemble ARM: ARM32 with start address 0x8000",
+        input: "00 00 a0 e1",
+        expectedMatch: /0x00008000/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Little Endian", 32768, true, true],
+            },
+        ],
+    },
+
+    // ==================== ENDIANNESS TESTS ====================
+    {
+        name: "Disassemble ARM: ARM32 Big Endian",
+        input: "e1 a0 00 00",
+        expectedMatch: /mov\s+r0,\s*r0/,
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM (32-bit)", "ARM", "Big Endian", 0, true, true],
+            },
+        ],
+    },
+
+    // ==================== EDGE CASES ====================
+    {
+        name: "Disassemble ARM: Empty input",
+        input: "",
+        expectedOutput: "",
+        recipeConfig: [
+            {
+                op: "Disassemble ARM",
+                args: ["ARM64 (AArch64)", "ARM", "Little Endian", 0, true, true],
+            },
+        ],
+    },
+]);