code-languages 1.22.0 → 1.24.0

package/dist/languages/vala.js

@@ -13,6 +13,7 @@ var vala = {
   },
   version: "0.56.18",
   logo: "https://cdn.simpleicons.org/gnome/4A86CF",
+  color: "#4A86CF",
   i18n: {
     en: {
       name: "Vala",
@@ -23,6 +24,16 @@ var vala = {
       name: "Vala",
       description: "Un lenguaje orientado a GNOME que compila sintaxis de alto nivel a C.",
       longDescription: "Vala ofrece clases, interfaces, propiedades, generics, signals y sintaxis async sobre las convenciones de GLib y GObject, compilando fuente hacia C. Los archivos VAPI describen bindings a bibliotecas C existentes.\n\nSe usa en aplicaciones GTK, bibliotecas GNOME, herramientas nativas, bindings y proyectos que buscan fuente de alto nivel integrada con APIs C."
+    },
+    it: {
+      name: "Vala",
+      description: "Un linguaggio orientato a GNOME che compila la sintassi di alto livello in C.",
+      longDescription: "Vala fornisce classi, interfacce, proprieta, generics, segnali e sintassi asincrona basate sulle convenzioni di GLib e GObject, compilando il codice sorgente in C. I file VAPI descrivono i binding alle librerie C esistenti.\n\nViene utilizzato per applicazioni GTK, librerie GNOME, strumenti nativi, binding e progetti che desiderano una sintassi di alto livello pur integrandosi con le API C."
+    },
+    fr: {
+      name: "Vala",
+      description: "Un langage oriente GNOME qui compile une syntaxe de haut niveau en C.",
+      longDescription: "Vala fournit des classes, des interfaces, des proprietes, des generiques, des signaux et une syntaxe asynchrone sur les conventions GLib et GObject, compilant la source en C. Les fichiers VAPI decrivent les liaisons aux bibliotheques C existantes.\n\nIl est utilise pour les applications GTK, les bibliotheques GNOME, les outils natifs, les liaisons et les projets qui souhaitent une source de haut niveau tout en s'integrant aux API C."
     }
   }
 };

package/dist/languages/vala.js.map

@@ -1 +1 @@
-{"version":3,"sources":["../../src/languages/vala.ts"],"names":[],"mappings":";AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,OAAA,EAAS,OAAO,CAAA;AAAA,EAC7B,MAAA,EAAQ,oCAAA;AAAA,EACR,OAAA,EAAS,kBAAA;AAAA,EACT,SAAA,EAAW,CAAC,iBAAA,EAAmB,kBAAA,EAAoB,SAAS,YAAY,CAAA;AAAA,EACxE,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,MAAA,EAAQ,SAAS,CAAA;AAAA,IAC5B,eAAA,EAAiB,CAAC,OAAA,EAAS,YAAY,CAAA;AAAA,IACvC,UAAA,EAAY,CAAC,OAAA,EAAS,KAAA,EAAO,QAAQ;AAAA,GACvC;AAAA,EACA,OAAA,EAAS,SAAA;AAAA,EACT,IAAA,EAAM,0CAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,iEAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,uEAAA;AAAA,MACb,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vala.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vala = {\n  slug: \"vala\",\n  publishedDate: \"2006-07-15\",\n  extensions: [\".vala\", \".vapi\"],\n  author: \"Jurg Billeter / GNOME contributors\",\n  website: \"https://vala.dev\",\n  paradigms: [\"object-oriented\", \"statically typed\", \"gnome\", \"c-targeted\"],\n  tooling: {\n    runtimes: [\"GLib\", \"GObject\"],\n    packageManagers: [\"Meson\", \"pkg-config\"],\n    ecosystems: [\"GNOME\", \"GTK\", \"Native\"],\n  },\n  version: \"0.56.18\",\n  logo: \"https://cdn.simpleicons.org/gnome/4A86CF\",\n  i18n: {\n    en: {\n      name: \"Vala\",\n      description: \"A GNOME-oriented language that compiles high-level syntax to C.\",\n      longDescription:\n        \"Vala provides classes, interfaces, properties, generics, signals, and async syntax over GLib and GObject conventions, compiling source into C. VAPI files describe bindings to existing C libraries.\\n\\nIt is used for GTK applications, GNOME libraries, native tools, bindings, and projects that want high-level source while integrating with C APIs.\",\n    },\n    es: {\n      name: \"Vala\",\n      description: \"Un lenguaje orientado a GNOME que compila sintaxis de alto nivel a C.\",\n      longDescription:\n        \"Vala ofrece clases, interfaces, propiedades, generics, signals y sintaxis async sobre las convenciones de GLib y GObject, compilando fuente hacia C. Los archivos VAPI describen bindings a bibliotecas C existentes.\\n\\nSe usa en aplicaciones GTK, bibliotecas GNOME, herramientas nativas, bindings y proyectos que buscan fuente de alto nivel integrada con APIs C.\",\n    },\n  },\n} satisfies Language;\n"]}
+{"version":3,"sources":["../../src/languages/vala.ts"],"names":[],"mappings":";AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,OAAA,EAAS,OAAO,CAAA;AAAA,EAC7B,MAAA,EAAQ,oCAAA;AAAA,EACR,OAAA,EAAS,kBAAA;AAAA,EACT,SAAA,EAAW,CAAC,iBAAA,EAAmB,kBAAA,EAAoB,SAAS,YAAY,CAAA;AAAA,EACxE,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,MAAA,EAAQ,SAAS,CAAA;AAAA,IAC5B,eAAA,EAAiB,CAAC,OAAA,EAAS,YAAY,CAAA;AAAA,IACvC,UAAA,EAAY,CAAC,OAAA,EAAS,KAAA,EAAO,QAAQ;AAAA,GACvC;AAAA,EACA,OAAA,EAAS,SAAA;AAAA,EACT,IAAA,EAAM,0CAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,iEAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,uEAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,+EAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,uEAAA;AAAA,MACb,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vala.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vala = {\n  slug: \"vala\",\n  publishedDate: \"2006-07-15\",\n  extensions: [\".vala\", \".vapi\"],\n  author: \"Jurg Billeter / GNOME contributors\",\n  website: \"https://vala.dev\",\n  paradigms: [\"object-oriented\", \"statically typed\", \"gnome\", \"c-targeted\"],\n  tooling: {\n    runtimes: [\"GLib\", \"GObject\"],\n    packageManagers: [\"Meson\", \"pkg-config\"],\n    ecosystems: [\"GNOME\", \"GTK\", \"Native\"],\n  },\n  version: \"0.56.18\",\n  logo: \"https://cdn.simpleicons.org/gnome/4A86CF\",\n  color: \"#4A86CF\",\n  i18n: {\n    en: {\n      name: \"Vala\",\n      description: \"A GNOME-oriented language that compiles high-level syntax to C.\",\n      longDescription:\n        \"Vala provides classes, interfaces, properties, generics, signals, and async syntax over GLib and GObject conventions, compiling source into C. VAPI files describe bindings to existing C libraries.\\n\\nIt is used for GTK applications, GNOME libraries, native tools, bindings, and projects that want high-level source while integrating with C APIs.\",\n    },\n    es: {\n      name: \"Vala\",\n      description: \"Un lenguaje orientado a GNOME que compila sintaxis de alto nivel a C.\",\n      longDescription:\n        \"Vala ofrece clases, interfaces, propiedades, generics, signals y sintaxis async sobre las convenciones de GLib y GObject, compilando fuente hacia C. Los archivos VAPI describen bindings a bibliotecas C existentes.\\n\\nSe usa en aplicaciones GTK, bibliotecas GNOME, herramientas nativas, bindings y proyectos que buscan fuente de alto nivel integrada con APIs C.\",\n    },\n    it: {\n      name: \"Vala\",\n      description: \"Un linguaggio orientato a GNOME che compila la sintassi di alto livello in C.\",\n      longDescription:\n        \"Vala fornisce classi, interfacce, proprieta, generics, segnali e sintassi asincrona basate sulle convenzioni di GLib e GObject, compilando il codice sorgente in C. I file VAPI descrivono i binding alle librerie C esistenti.\\n\\nViene utilizzato per applicazioni GTK, librerie GNOME, strumenti nativi, binding e progetti che desiderano una sintassi di alto livello pur integrandosi con le API C.\",\n    },\n    fr: {\n      name: \"Vala\",\n      description: \"Un langage oriente GNOME qui compile une syntaxe de haut niveau en C.\",\n      longDescription:\n        \"Vala fournit des classes, des interfaces, des proprietes, des generiques, des signaux et une syntaxe asynchrone sur les conventions GLib et GObject, compilant la source en C. Les fichiers VAPI decrivent les liaisons aux bibliotheques C existantes.\\n\\nIl est utilise pour les applications GTK, les bibliotheques GNOME, les outils natifs, les liaisons et les projets qui souhaitent une source de haut niveau tout en s'integrant aux API C.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/verilog.cjs

@@ -15,6 +15,7 @@ var verilog = {
   },
   version: "IEEE 1800-2023",
   logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg",
+  color: "#1488C6",
   i18n: {
     en: {
       name: "Verilog/SystemVerilog",
@@ -25,6 +26,16 @@ var verilog = {
       name: "Verilog/SystemVerilog",
       description: "Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.",
       longDescription: "Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\n\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico."
+    },
+    it: {
+      name: "Verilog/SystemVerilog",
+      description: "Linguaggio di descrizione e verifica hardware per circuiti e sistemi digitali.",
+      longDescription: "Verilog e SystemVerilog descrivono l'hardware digitale a livello comportamentale, di trasferimento di registri e di porte. Il linguaggio supporta moduli, segnali, assegnazioni continue, blocchi procedurali, temporizzazione, testbench, asserzioni, interfacce, classi e verifica casuale vincolata.\n\nViene utilizzato per progetti FPGA, sviluppo di ASIC, simulazione hardware, sintesi, ambienti di verifica, blocchi IP riutilizzabili e flussi di lavoro di automazione del design elettronico."
+    },
+    fr: {
+      name: "Verilog/SystemVerilog",
+      description: "Langage de description et de verification du materiel pour les circuits et systemes numeriques.",
+      longDescription: "Verilog et SystemVerilog decrivent le materiel numerique au niveau comportemental, registre-transfert et porte. Le langage prend en charge les modules, les signaux, les affectations continues, les blocs proceduraux, le temps, les bancs de test, les assertions, les interfaces, les classes et la verification par aleatoire contrainte.\n\nIl est utilise pour la conception de FPGA, le developpement d'ASIC, la simulation materielle, la synthese, les environnements de verification, les blocs IP reutilisables et les flux de travail d'automatisation de la conception electronique."
     }
   }
 };

package/dist/languages/verilog.cjs.map

@@ -1 +1 @@
-{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";;;AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}
+{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";;;AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EAAa,gFAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,iGAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  color: \"#1488C6\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n    it: {\n      name: \"Verilog/SystemVerilog\",\n      description: \"Linguaggio di descrizione e verifica hardware per circuiti e sistemi digitali.\",\n      longDescription:\n        \"Verilog e SystemVerilog descrivono l'hardware digitale a livello comportamentale, di trasferimento di registri e di porte. Il linguaggio supporta moduli, segnali, assegnazioni continue, blocchi procedurali, temporizzazione, testbench, asserzioni, interfacce, classi e verifica casuale vincolata.\\n\\nViene utilizzato per progetti FPGA, sviluppo di ASIC, simulazione hardware, sintesi, ambienti di verifica, blocchi IP riutilizzabili e flussi di lavoro di automazione del design elettronico.\",\n    },\n    fr: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Langage de description et de verification du materiel pour les circuits et systemes numeriques.\",\n      longDescription:\n        \"Verilog et SystemVerilog decrivent le materiel numerique au niveau comportemental, registre-transfert et porte. Le langage prend en charge les modules, les signaux, les affectations continues, les blocs proceduraux, le temps, les bancs de test, les assertions, les interfaces, les classes et la verification par aleatoire contrainte.\\n\\nIl est utilise pour la conception de FPGA, le developpement d'ASIC, la simulation materielle, la synthese, les environnements de verification, les blocs IP reutilisables et les flux de travail d'automatisation de la conception electronique.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/verilog.d.cts

@@ -12,6 +12,7 @@ declare const verilog: {
     };
     version: string;
     logo: string;
+    color: "#1488C6";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const verilog: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/verilog.d.ts

@@ -12,6 +12,7 @@ declare const verilog: {
     };
     version: string;
     logo: string;
+    color: "#1488C6";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const verilog: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/verilog.js

@@ -13,6 +13,7 @@ var verilog = {
   },
   version: "IEEE 1800-2023",
   logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg",
+  color: "#1488C6",
   i18n: {
     en: {
       name: "Verilog/SystemVerilog",
@@ -23,6 +24,16 @@ var verilog = {
       name: "Verilog/SystemVerilog",
       description: "Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.",
       longDescription: "Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\n\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico."
+    },
+    it: {
+      name: "Verilog/SystemVerilog",
+      description: "Linguaggio di descrizione e verifica hardware per circuiti e sistemi digitali.",
+      longDescription: "Verilog e SystemVerilog descrivono l'hardware digitale a livello comportamentale, di trasferimento di registri e di porte. Il linguaggio supporta moduli, segnali, assegnazioni continue, blocchi procedurali, temporizzazione, testbench, asserzioni, interfacce, classi e verifica casuale vincolata.\n\nViene utilizzato per progetti FPGA, sviluppo di ASIC, simulazione hardware, sintesi, ambienti di verifica, blocchi IP riutilizzabili e flussi di lavoro di automazione del design elettronico."
+    },
+    fr: {
+      name: "Verilog/SystemVerilog",
+      description: "Langage de description et de verification du materiel pour les circuits et systemes numeriques.",
+      longDescription: "Verilog et SystemVerilog decrivent le materiel numerique au niveau comportemental, registre-transfert et porte. Le langage prend en charge les modules, les signaux, les affectations continues, les blocs proceduraux, le temps, les bancs de test, les assertions, les interfaces, les classes et la verification par aleatoire contrainte.\n\nIl est utilise pour la conception de FPGA, le developpement d'ASIC, la simulation materielle, la synthese, les environnements de verification, les blocs IP reutilisables et les flux de travail d'automatisation de la conception electronique."
     }
   }
 };

package/dist/languages/verilog.js.map

@@ -1 +1 @@
-{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}
+{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EAAa,gFAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,iGAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  color: \"#1488C6\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n    it: {\n      name: \"Verilog/SystemVerilog\",\n      description: \"Linguaggio di descrizione e verifica hardware per circuiti e sistemi digitali.\",\n      longDescription:\n        \"Verilog e SystemVerilog descrivono l'hardware digitale a livello comportamentale, di trasferimento di registri e di porte. Il linguaggio supporta moduli, segnali, assegnazioni continue, blocchi procedurali, temporizzazione, testbench, asserzioni, interfacce, classi e verifica casuale vincolata.\\n\\nViene utilizzato per progetti FPGA, sviluppo di ASIC, simulazione hardware, sintesi, ambienti di verifica, blocchi IP riutilizzabili e flussi di lavoro di automazione del design elettronico.\",\n    },\n    fr: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Langage de description et de verification du materiel pour les circuits et systemes numeriques.\",\n      longDescription:\n        \"Verilog et SystemVerilog decrivent le materiel numerique au niveau comportemental, registre-transfert et porte. Le langage prend en charge les modules, les signaux, les affectations continues, les blocs proceduraux, le temps, les bancs de test, les assertions, les interfaces, les classes et la verification par aleatoire contrainte.\\n\\nIl est utilise pour la conception de FPGA, le developpement d'ASIC, la simulation materielle, la synthese, les environnements de verification, les blocs IP reutilisables et les flux de travail d'automatisation de la conception electronique.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/vhdl.cjs

@@ -15,6 +15,7 @@ var vhdl = {
   },
   version: "IEEE 1076-2019",
   logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg",
+  color: "#543978",
   i18n: {
     en: {
       name: "VHDL",
@@ -25,6 +26,16 @@ var vhdl = {
       name: "VHDL",
       description: "Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.",
       longDescription: "VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\n\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico."
+    },
+    it: {
+      name: "VHDL",
+      description: "Un linguaggio di descrizione e verifica hardware per sistemi elettronici digitali.",
+      longDescription: "VHDL descrive i sistemi digitali utilizzando entita, architetture, segnali, processi, istruzioni concorrenti, pacchetti, generici, configurazioni, testbench e unita di progettazione fortemente tipizzate. Supporta la simulazione, la sintesi e la verifica a diversi livelli di astrazione.\n\nE utilizzato per lo sviluppo di FPGA, la progettazione di ASIC, la verifica hardware, blocchi IP riutilizzabili, l'elaborazione del segnale digitale, hardware critico per la sicurezza e i flussi di lavoro di automazione del design elettronico."
+    },
+    fr: {
+      name: "VHDL",
+      description: "Un langage de description et de verification du materiel pour les systemes electroniques numeriques.",
+      longDescription: "VHDL decrit les systemes numeriques en utilisant des entites, des architectures, des signaux, des processus, des instructions concurrentes, des packages, des generiques, des configurations, des bancs de test et des unites de conception fortement typees. Il prend en charge la simulation, la synthese et la verification a plusieurs niveaux d'abstraction.\n\nIl est utilise pour le developpement de FPGA, la conception de circuits integres, la verification materielle, les blocs IP reutilisables, le traitement du signal numerique, le materiel critique pour la securite et les flux de travail d'automatisation de la conception electronique."
     }
   }
 };

package/dist/languages/vhdl.cjs.map

@@ -1 +1 @@
-{"version":3,"sources":["../../src/languages/vhdl.ts"],"names":[],"mappings":";;;AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAA,EAAQ,OAAO,CAAA;AAAA,EAC5B,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,YAAY,cAAc,CAAA;AAAA,EAC5E,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,OAAA,EAAS,SAAS,CAAA;AAAA,IACpC,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,uFAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,kFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,6FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vhdl.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vhdl = {\n  slug: \"vhdl\",\n  publishedDate: \"1987-01-01\",\n  extensions: [\".vhd\", \".vhdl\"],\n  author: \"U.S. Department of Defense / IEEE\",\n  website: \"https://standards.ieee.org/standard/1076-2019.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"dataflow\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"VUnit\", \"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1076-2019\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg\",\n  i18n: {\n    en: {\n      name: \"VHDL\",\n      description:\n        \"A hardware description and verification language for digital electronic systems.\",\n      longDescription:\n        \"VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\\n\\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"VHDL\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.\",\n      longDescription:\n        \"VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\\n\\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}
+{"version":3,"sources":["../../src/languages/vhdl.ts"],"names":[],"mappings":";;;AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAA,EAAQ,OAAO,CAAA;AAAA,EAC5B,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,YAAY,cAAc,CAAA;AAAA,EAC5E,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,OAAA,EAAS,SAAS,CAAA;AAAA,IACpC,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,uFAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,kFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,6FAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,sGAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vhdl.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vhdl = {\n  slug: \"vhdl\",\n  publishedDate: \"1987-01-01\",\n  extensions: [\".vhd\", \".vhdl\"],\n  author: \"U.S. Department of Defense / IEEE\",\n  website: \"https://standards.ieee.org/standard/1076-2019.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"dataflow\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"VUnit\", \"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1076-2019\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg\",\n  color: \"#543978\",\n  i18n: {\n    en: {\n      name: \"VHDL\",\n      description:\n        \"A hardware description and verification language for digital electronic systems.\",\n      longDescription:\n        \"VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\\n\\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"VHDL\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.\",\n      longDescription:\n        \"VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\\n\\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico.\",\n    },\n    it: {\n      name: \"VHDL\",\n      description:\n        \"Un linguaggio di descrizione e verifica hardware per sistemi elettronici digitali.\",\n      longDescription:\n        \"VHDL descrive i sistemi digitali utilizzando entita, architetture, segnali, processi, istruzioni concorrenti, pacchetti, generici, configurazioni, testbench e unita di progettazione fortemente tipizzate. Supporta la simulazione, la sintesi e la verifica a diversi livelli di astrazione.\\n\\nE utilizzato per lo sviluppo di FPGA, la progettazione di ASIC, la verifica hardware, blocchi IP riutilizzabili, l'elaborazione del segnale digitale, hardware critico per la sicurezza e i flussi di lavoro di automazione del design elettronico.\",\n    },\n    fr: {\n      name: \"VHDL\",\n      description:\n        \"Un langage de description et de verification du materiel pour les systemes electroniques numeriques.\",\n      longDescription:\n        \"VHDL decrit les systemes numeriques en utilisant des entites, des architectures, des signaux, des processus, des instructions concurrentes, des packages, des generiques, des configurations, des bancs de test et des unites de conception fortement typees. Il prend en charge la simulation, la synthese et la verification a plusieurs niveaux d'abstraction.\\n\\nIl est utilise pour le developpement de FPGA, la conception de circuits integres, la verification materielle, les blocs IP reutilisables, le traitement du signal numerique, le materiel critique pour la securite et les flux de travail d'automatisation de la conception electronique.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/vhdl.d.cts

@@ -12,6 +12,7 @@ declare const vhdl: {
     };
     version: string;
     logo: string;
+    color: "#543978";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const vhdl: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/vhdl.d.ts

@@ -12,6 +12,7 @@ declare const vhdl: {
     };
     version: string;
     logo: string;
+    color: "#543978";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const vhdl: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/vhdl.js

@@ -13,6 +13,7 @@ var vhdl = {
   },
   version: "IEEE 1076-2019",
   logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg",
+  color: "#543978",
   i18n: {
     en: {
       name: "VHDL",
@@ -23,6 +24,16 @@ var vhdl = {
       name: "VHDL",
       description: "Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.",
       longDescription: "VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\n\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico."
+    },
+    it: {
+      name: "VHDL",
+      description: "Un linguaggio di descrizione e verifica hardware per sistemi elettronici digitali.",
+      longDescription: "VHDL descrive i sistemi digitali utilizzando entita, architetture, segnali, processi, istruzioni concorrenti, pacchetti, generici, configurazioni, testbench e unita di progettazione fortemente tipizzate. Supporta la simulazione, la sintesi e la verifica a diversi livelli di astrazione.\n\nE utilizzato per lo sviluppo di FPGA, la progettazione di ASIC, la verifica hardware, blocchi IP riutilizzabili, l'elaborazione del segnale digitale, hardware critico per la sicurezza e i flussi di lavoro di automazione del design elettronico."
+    },
+    fr: {
+      name: "VHDL",
+      description: "Un langage de description et de verification du materiel pour les systemes electroniques numeriques.",
+      longDescription: "VHDL decrit les systemes numeriques en utilisant des entites, des architectures, des signaux, des processus, des instructions concurrentes, des packages, des generiques, des configurations, des bancs de test et des unites de conception fortement typees. Il prend en charge la simulation, la synthese et la verification a plusieurs niveaux d'abstraction.\n\nIl est utilise pour le developpement de FPGA, la conception de circuits integres, la verification materielle, les blocs IP reutilisables, le traitement du signal numerique, le materiel critique pour la securite et les flux de travail d'automatisation de la conception electronique."
     }
   }
 };

package/dist/languages/vhdl.js.map

@@ -1 +1 @@
-{"version":3,"sources":["../../src/languages/vhdl.ts"],"names":[],"mappings":";AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAA,EAAQ,OAAO,CAAA;AAAA,EAC5B,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,YAAY,cAAc,CAAA;AAAA,EAC5E,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,OAAA,EAAS,SAAS,CAAA;AAAA,IACpC,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,uFAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,kFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,6FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vhdl.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vhdl = {\n  slug: \"vhdl\",\n  publishedDate: \"1987-01-01\",\n  extensions: [\".vhd\", \".vhdl\"],\n  author: \"U.S. Department of Defense / IEEE\",\n  website: \"https://standards.ieee.org/standard/1076-2019.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"dataflow\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"VUnit\", \"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1076-2019\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg\",\n  i18n: {\n    en: {\n      name: \"VHDL\",\n      description:\n        \"A hardware description and verification language for digital electronic systems.\",\n      longDescription:\n        \"VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\\n\\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"VHDL\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.\",\n      longDescription:\n        \"VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\\n\\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}
+{"version":3,"sources":["../../src/languages/vhdl.ts"],"names":[],"mappings":";AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAA,EAAQ,OAAO,CAAA;AAAA,EAC5B,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,YAAY,cAAc,CAAA;AAAA,EAC5E,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,OAAA,EAAS,SAAS,CAAA;AAAA,IACpC,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,uFAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,kFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,6FAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,sGAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vhdl.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vhdl = {\n  slug: \"vhdl\",\n  publishedDate: \"1987-01-01\",\n  extensions: [\".vhd\", \".vhdl\"],\n  author: \"U.S. Department of Defense / IEEE\",\n  website: \"https://standards.ieee.org/standard/1076-2019.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"dataflow\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"VUnit\", \"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1076-2019\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg\",\n  color: \"#543978\",\n  i18n: {\n    en: {\n      name: \"VHDL\",\n      description:\n        \"A hardware description and verification language for digital electronic systems.\",\n      longDescription:\n        \"VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\\n\\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"VHDL\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.\",\n      longDescription:\n        \"VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\\n\\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico.\",\n    },\n    it: {\n      name: \"VHDL\",\n      description:\n        \"Un linguaggio di descrizione e verifica hardware per sistemi elettronici digitali.\",\n      longDescription:\n        \"VHDL descrive i sistemi digitali utilizzando entita, architetture, segnali, processi, istruzioni concorrenti, pacchetti, generici, configurazioni, testbench e unita di progettazione fortemente tipizzate. Supporta la simulazione, la sintesi e la verifica a diversi livelli di astrazione.\\n\\nE utilizzato per lo sviluppo di FPGA, la progettazione di ASIC, la verifica hardware, blocchi IP riutilizzabili, l'elaborazione del segnale digitale, hardware critico per la sicurezza e i flussi di lavoro di automazione del design elettronico.\",\n    },\n    fr: {\n      name: \"VHDL\",\n      description:\n        \"Un langage de description et de verification du materiel pour les systemes electroniques numeriques.\",\n      longDescription:\n        \"VHDL decrit les systemes numeriques en utilisant des entites, des architectures, des signaux, des processus, des instructions concurrentes, des packages, des generiques, des configurations, des bancs de test et des unites de conception fortement typees. Il prend en charge la simulation, la synthese et la verification a plusieurs niveaux d'abstraction.\\n\\nIl est utilise pour le developpement de FPGA, la conception de circuits integres, la verification materielle, les blocs IP reutilisables, le traitement du signal numerique, le materiel critique pour la securite et les flux de travail d'automatisation de la conception electronique.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/visual-basic.cjs

@@ -15,6 +15,7 @@ var visualBasic = {
   },
   version: "17.13",
   logo: "https://upload.wikimedia.org/wikipedia/commons/4/40/VB.NET_Logo.svg",
+  color: "#512BD4",
   i18n: {
     en: {
       name: "Visual Basic",
@@ -25,6 +26,16 @@ var visualBasic = {
       name: "Visual Basic",
       description: "Un lenguaje .NET accesible para aplicaciones orientadas a objetos y type-safe.",
       longDescription: "Visual Basic es un lenguaje de programacion .NET de Microsoft con sintaxis legible, tipado estatico, caracteristicas orientadas a objetos, soporte para programacion basada en eventos, genericos, LINQ, flujos async y acceso al ecosistema .NET.\n\nSe usa en aplicaciones de escritorio para Windows, software empresarial, automatizacion, sistemas .NET heredados, aplicaciones ASP.NET, bibliotecas y equipos que valoran una sintaxis explicita y accesible sobre el runtime .NET."
+    },
+    it: {
+      name: "Visual Basic",
+      description: "Un linguaggio .NET accessibile per applicazioni sicure dal punto di vista dei tipi e orientate agli oggetti.",
+      longDescription: "Visual Basic e un linguaggio di programmazione .NET di Microsoft con una sintassi leggibile, tipizzazione statica, funzionalita orientate agli oggetti, supporto per la programmazione guidata dagli eventi, generics, LINQ, workflow asincroni e accesso all'ecosistema .NET.\n\nViene utilizzato per applicazioni desktop per Windows, software aziendale, automazione, sistemi .NET legacy, applicazioni ASP.NET, librerie e team che apprezzano una sintassi verbosa e accessibile sopra il runtime .NET."
+    },
+    fr: {
+      name: "Visual Basic",
+      description: "Un langage .NET accessible pour les applications orientees objet et securisees par type.",
+      longDescription: "Visual Basic est un langage de programmation .NET de Microsoft dote d'une syntaxe lisible, de typage statique, de fonctionnalites orientees objet, de prise en charge de la programmation evenementielle, de generiques, de LINQ, de workflows asynchrones et d'acces a l'ecosysteme .NET.\n\nIl est utilise pour les applications de bureau Windows, les logiciels d'entreprise, l'automatisation, les systemes .NET herites, les applications ASP.NET, les bibliotheques et les equipes qui privilegient une syntaxe verbose et accessible au-dessus de l'environnement d'execution .NET."
     }
   }
 };

package/dist/languages/visual-basic.cjs.map

@@ -1 +1 @@
-{"version":3,"sources":["../../src/languages/visual-basic.ts"],"names":[],"mappings":";;;AAEO,IAAM,WAAA,GAAc;AAAA,EACzB,IAAA,EAAM,cAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,KAAK,CAAA;AAAA,EAClB,MAAA,EAAQ,WAAA;AAAA,EACR,OAAA,EAAS,kDAAA;AAAA,EACT,SAAA,EAAW,CAAC,cAAA,EAAgB,SAAA,EAAW,mBAAmB,YAAY,CAAA;AAAA,EACtE,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,MAAA,EAAQ,gBAAA,EAAkB,MAAM,CAAA;AAAA,IAC3C,eAAA,EAAiB,CAAC,OAAO,CAAA;AAAA,IACzB,UAAA,EAAY,CAAC,MAAA,EAAQ,eAAA,EAAiB,iBAAiB,SAAS;AAAA,GAClE;AAAA,EACA,OAAA,EAAS,OAAA;AAAA,EACT,IAAA,EAAM,qEAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EAAa,4EAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EAAa,gFAAA;AAAA,MACb,eAAA,EACE;AAAA;AACJ;AAEJ","file":"visual-basic.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const visualBasic = {\n  slug: \"visual-basic\",\n  publishedDate: \"2001-02-13\",\n  extensions: [\".vb\"],\n  author: \"Microsoft\",\n  website: \"https://learn.microsoft.com/dotnet/visual-basic/\",\n  paradigms: [\"event-driven\", \"generic\", \"object-oriented\", \"structured\"],\n  tooling: {\n    runtimes: [\".NET\", \".NET Framework\", \"Mono\"],\n    packageManagers: [\"NuGet\"],\n    ecosystems: [\".NET\", \"Visual Studio\", \"Windows Forms\", \"ASP.NET\"],\n  },\n  version: \"17.13\",\n  logo: \"https://upload.wikimedia.org/wikipedia/commons/4/40/VB.NET_Logo.svg\",\n  i18n: {\n    en: {\n      name: \"Visual Basic\",\n      description: \"An approachable .NET language for type-safe, object-oriented applications.\",\n      longDescription:\n        \"Visual Basic is a .NET programming language from Microsoft with a readable syntax, static typing, object-oriented features, event-driven programming support, generics, LINQ, async workflows, and access to the .NET ecosystem.\\n\\nIt is used for Windows desktop applications, business software, automation, legacy .NET systems, ASP.NET applications, libraries, and teams that value a verbose, approachable syntax on top of the .NET runtime.\",\n    },\n    es: {\n      name: \"Visual Basic\",\n      description: \"Un lenguaje .NET accesible para aplicaciones orientadas a objetos y type-safe.\",\n      longDescription:\n        \"Visual Basic es un lenguaje de programacion .NET de Microsoft con sintaxis legible, tipado estatico, caracteristicas orientadas a objetos, soporte para programacion basada en eventos, genericos, LINQ, flujos async y acceso al ecosistema .NET.\\n\\nSe usa en aplicaciones de escritorio para Windows, software empresarial, automatizacion, sistemas .NET heredados, aplicaciones ASP.NET, bibliotecas y equipos que valoran una sintaxis explicita y accesible sobre el runtime .NET.\",\n    },\n  },\n} satisfies Language;\n"]}
+{"version":3,"sources":["../../src/languages/visual-basic.ts"],"names":[],"mappings":";;;AAEO,IAAM,WAAA,GAAc;AAAA,EACzB,IAAA,EAAM,cAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,KAAK,CAAA;AAAA,EAClB,MAAA,EAAQ,WAAA;AAAA,EACR,OAAA,EAAS,kDAAA;AAAA,EACT,SAAA,EAAW,CAAC,cAAA,EAAgB,SAAA,EAAW,mBAAmB,YAAY,CAAA;AAAA,EACtE,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,MAAA,EAAQ,gBAAA,EAAkB,MAAM,CAAA;AAAA,IAC3C,eAAA,EAAiB,CAAC,OAAO,CAAA;AAAA,IACzB,UAAA,EAAY,CAAC,MAAA,EAAQ,eAAA,EAAiB,iBAAiB,SAAS;AAAA,GAClE;AAAA,EACA,OAAA,EAAS,OAAA;AAAA,EACT,IAAA,EAAM,qEAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EAAa,4EAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EAAa,gFAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EACE,8GAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EACE,0FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"visual-basic.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const visualBasic = {\n  slug: \"visual-basic\",\n  publishedDate: \"2001-02-13\",\n  extensions: [\".vb\"],\n  author: \"Microsoft\",\n  website: \"https://learn.microsoft.com/dotnet/visual-basic/\",\n  paradigms: [\"event-driven\", \"generic\", \"object-oriented\", \"structured\"],\n  tooling: {\n    runtimes: [\".NET\", \".NET Framework\", \"Mono\"],\n    packageManagers: [\"NuGet\"],\n    ecosystems: [\".NET\", \"Visual Studio\", \"Windows Forms\", \"ASP.NET\"],\n  },\n  version: \"17.13\",\n  logo: \"https://upload.wikimedia.org/wikipedia/commons/4/40/VB.NET_Logo.svg\",\n  color: \"#512BD4\",\n  i18n: {\n    en: {\n      name: \"Visual Basic\",\n      description: \"An approachable .NET language for type-safe, object-oriented applications.\",\n      longDescription:\n        \"Visual Basic is a .NET programming language from Microsoft with a readable syntax, static typing, object-oriented features, event-driven programming support, generics, LINQ, async workflows, and access to the .NET ecosystem.\\n\\nIt is used for Windows desktop applications, business software, automation, legacy .NET systems, ASP.NET applications, libraries, and teams that value a verbose, approachable syntax on top of the .NET runtime.\",\n    },\n    es: {\n      name: \"Visual Basic\",\n      description: \"Un lenguaje .NET accesible para aplicaciones orientadas a objetos y type-safe.\",\n      longDescription:\n        \"Visual Basic es un lenguaje de programacion .NET de Microsoft con sintaxis legible, tipado estatico, caracteristicas orientadas a objetos, soporte para programacion basada en eventos, genericos, LINQ, flujos async y acceso al ecosistema .NET.\\n\\nSe usa en aplicaciones de escritorio para Windows, software empresarial, automatizacion, sistemas .NET heredados, aplicaciones ASP.NET, bibliotecas y equipos que valoran una sintaxis explicita y accesible sobre el runtime .NET.\",\n    },\n    it: {\n      name: \"Visual Basic\",\n      description:\n        \"Un linguaggio .NET accessibile per applicazioni sicure dal punto di vista dei tipi e orientate agli oggetti.\",\n      longDescription:\n        \"Visual Basic e un linguaggio di programmazione .NET di Microsoft con una sintassi leggibile, tipizzazione statica, funzionalita orientate agli oggetti, supporto per la programmazione guidata dagli eventi, generics, LINQ, workflow asincroni e accesso all'ecosistema .NET.\\n\\nViene utilizzato per applicazioni desktop per Windows, software aziendale, automazione, sistemi .NET legacy, applicazioni ASP.NET, librerie e team che apprezzano una sintassi verbosa e accessibile sopra il runtime .NET.\",\n    },\n    fr: {\n      name: \"Visual Basic\",\n      description:\n        \"Un langage .NET accessible pour les applications orientees objet et securisees par type.\",\n      longDescription:\n        \"Visual Basic est un langage de programmation .NET de Microsoft dote d'une syntaxe lisible, de typage statique, de fonctionnalites orientees objet, de prise en charge de la programmation evenementielle, de generiques, de LINQ, de workflows asynchrones et d'acces a l'ecosysteme .NET.\\n\\nIl est utilise pour les applications de bureau Windows, les logiciels d'entreprise, l'automatisation, les systemes .NET herites, les applications ASP.NET, les bibliotheques et les equipes qui privilegient une syntaxe verbose et accessible au-dessus de l'environnement d'execution .NET.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/visual-basic.d.cts

@@ -12,6 +12,7 @@ declare const visualBasic: {
     };
     version: string;
     logo: string;
+    color: "#512BD4";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const visualBasic: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/visual-basic.d.ts

@@ -12,6 +12,7 @@ declare const visualBasic: {
     };
     version: string;
     logo: string;
+    color: "#512BD4";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const visualBasic: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/visual-basic.js

@@ -13,6 +13,7 @@ var visualBasic = {
   },
   version: "17.13",
   logo: "https://upload.wikimedia.org/wikipedia/commons/4/40/VB.NET_Logo.svg",
+  color: "#512BD4",
   i18n: {
     en: {
       name: "Visual Basic",
@@ -23,6 +24,16 @@ var visualBasic = {
       name: "Visual Basic",
       description: "Un lenguaje .NET accesible para aplicaciones orientadas a objetos y type-safe.",
       longDescription: "Visual Basic es un lenguaje de programacion .NET de Microsoft con sintaxis legible, tipado estatico, caracteristicas orientadas a objetos, soporte para programacion basada en eventos, genericos, LINQ, flujos async y acceso al ecosistema .NET.\n\nSe usa en aplicaciones de escritorio para Windows, software empresarial, automatizacion, sistemas .NET heredados, aplicaciones ASP.NET, bibliotecas y equipos que valoran una sintaxis explicita y accesible sobre el runtime .NET."
+    },
+    it: {
+      name: "Visual Basic",
+      description: "Un linguaggio .NET accessibile per applicazioni sicure dal punto di vista dei tipi e orientate agli oggetti.",
+      longDescription: "Visual Basic e un linguaggio di programmazione .NET di Microsoft con una sintassi leggibile, tipizzazione statica, funzionalita orientate agli oggetti, supporto per la programmazione guidata dagli eventi, generics, LINQ, workflow asincroni e accesso all'ecosistema .NET.\n\nViene utilizzato per applicazioni desktop per Windows, software aziendale, automazione, sistemi .NET legacy, applicazioni ASP.NET, librerie e team che apprezzano una sintassi verbosa e accessibile sopra il runtime .NET."
+    },
+    fr: {
+      name: "Visual Basic",
+      description: "Un langage .NET accessible pour les applications orientees objet et securisees par type.",
+      longDescription: "Visual Basic est un langage de programmation .NET de Microsoft dote d'une syntaxe lisible, de typage statique, de fonctionnalites orientees objet, de prise en charge de la programmation evenementielle, de generiques, de LINQ, de workflows asynchrones et d'acces a l'ecosysteme .NET.\n\nIl est utilise pour les applications de bureau Windows, les logiciels d'entreprise, l'automatisation, les systemes .NET herites, les applications ASP.NET, les bibliotheques et les equipes qui privilegient une syntaxe verbose et accessible au-dessus de l'environnement d'execution .NET."
     }
   }
 };

package/dist/languages/visual-basic.js.map

@@ -1 +1 @@
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+{"version":3,"sources":["../../src/languages/visual-basic.ts"],"names":[],"mappings":";AAEO,IAAM,WAAA,GAAc;AAAA,EACzB,IAAA,EAAM,cAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,KAAK,CAAA;AAAA,EAClB,MAAA,EAAQ,WAAA;AAAA,EACR,OAAA,EAAS,kDAAA;AAAA,EACT,SAAA,EAAW,CAAC,cAAA,EAAgB,SAAA,EAAW,mBAAmB,YAAY,CAAA;AAAA,EACtE,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,MAAA,EAAQ,gBAAA,EAAkB,MAAM,CAAA;AAAA,IAC3C,eAAA,EAAiB,CAAC,OAAO,CAAA;AAAA,IACzB,UAAA,EAAY,CAAC,MAAA,EAAQ,eAAA,EAAiB,iBAAiB,SAAS;AAAA,GAClE;AAAA,EACA,OAAA,EAAS,OAAA;AAAA,EACT,IAAA,EAAM,qEAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EAAa,4EAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EAAa,gFAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EACE,8GAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,cAAA;AAAA,MACN,WAAA,EACE,0FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"visual-basic.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const visualBasic = {\n  slug: \"visual-basic\",\n  publishedDate: \"2001-02-13\",\n  extensions: [\".vb\"],\n  author: \"Microsoft\",\n  website: \"https://learn.microsoft.com/dotnet/visual-basic/\",\n  paradigms: [\"event-driven\", \"generic\", \"object-oriented\", \"structured\"],\n  tooling: {\n    runtimes: [\".NET\", \".NET Framework\", \"Mono\"],\n    packageManagers: [\"NuGet\"],\n    ecosystems: [\".NET\", \"Visual Studio\", \"Windows Forms\", \"ASP.NET\"],\n  },\n  version: \"17.13\",\n  logo: \"https://upload.wikimedia.org/wikipedia/commons/4/40/VB.NET_Logo.svg\",\n  color: \"#512BD4\",\n  i18n: {\n    en: {\n      name: \"Visual Basic\",\n      description: \"An approachable .NET language for type-safe, object-oriented applications.\",\n      longDescription:\n        \"Visual Basic is a .NET programming language from Microsoft with a readable syntax, static typing, object-oriented features, event-driven programming support, generics, LINQ, async workflows, and access to the .NET ecosystem.\\n\\nIt is used for Windows desktop applications, business software, automation, legacy .NET systems, ASP.NET applications, libraries, and teams that value a verbose, approachable syntax on top of the .NET runtime.\",\n    },\n    es: {\n      name: \"Visual Basic\",\n      description: \"Un lenguaje .NET accesible para aplicaciones orientadas a objetos y type-safe.\",\n      longDescription:\n        \"Visual Basic es un lenguaje de programacion .NET de Microsoft con sintaxis legible, tipado estatico, caracteristicas orientadas a objetos, soporte para programacion basada en eventos, genericos, LINQ, flujos async y acceso al ecosistema .NET.\\n\\nSe usa en aplicaciones de escritorio para Windows, software empresarial, automatizacion, sistemas .NET heredados, aplicaciones ASP.NET, bibliotecas y equipos que valoran una sintaxis explicita y accesible sobre el runtime .NET.\",\n    },\n    it: {\n      name: \"Visual Basic\",\n      description:\n        \"Un linguaggio .NET accessibile per applicazioni sicure dal punto di vista dei tipi e orientate agli oggetti.\",\n      longDescription:\n        \"Visual Basic e un linguaggio di programmazione .NET di Microsoft con una sintassi leggibile, tipizzazione statica, funzionalita orientate agli oggetti, supporto per la programmazione guidata dagli eventi, generics, LINQ, workflow asincroni e accesso all'ecosistema .NET.\\n\\nViene utilizzato per applicazioni desktop per Windows, software aziendale, automazione, sistemi .NET legacy, applicazioni ASP.NET, librerie e team che apprezzano una sintassi verbosa e accessibile sopra il runtime .NET.\",\n    },\n    fr: {\n      name: \"Visual Basic\",\n      description:\n        \"Un langage .NET accessible pour les applications orientees objet et securisees par type.\",\n      longDescription:\n        \"Visual Basic est un langage de programmation .NET de Microsoft dote d'une syntaxe lisible, de typage statique, de fonctionnalites orientees objet, de prise en charge de la programmation evenementielle, de generiques, de LINQ, de workflows asynchrones et d'acces a l'ecosysteme .NET.\\n\\nIl est utilise pour les applications de bureau Windows, les logiciels d'entreprise, l'automatisation, les systemes .NET herites, les applications ASP.NET, les bibliotheques et les equipes qui privilegient une syntaxe verbose et accessible au-dessus de l'environnement d'execution .NET.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/vue.cjs

@@ -15,6 +15,7 @@ var vue = {
   },
   version: "3.5.34",
   logo: "https://upload.wikimedia.org/wikipedia/commons/9/95/Vue.js_Logo_2.svg",
+  color: "#4FC08D",
   i18n: {
     en: {
       name: "Vue",
@@ -25,6 +26,16 @@ var vue = {
       name: "Vue",
       description: "Un framework progresivo de JavaScript para crear interfaces con componentes reactivos.",
       longDescription: "Vue es un framework progresivo para crear interfaces de usuario con componentes de archivo unico, plantillas declarativas, reactividad, APIs de composicion, enrutamiento, gestion de estado y herramientas del ecosistema Vue.\n\nSe usa ampliamente en aplicaciones de una sola pagina, interfaces interactivas, sistemas de diseno, dashboards, widgets embebidos y aplicaciones web full-stack con frameworks como Nuxt."
+    },
+    it: {
+      name: "Vue",
+      description: "Un framework JavaScript progressivo per la creazione di interfacce utente con componenti reattivi.",
+      longDescription: "Vue e un framework progressivo per la creazione di interfacce utente con componenti a singolo file, modelli dichiarativi, reattivita, API di composizione, routing, gestione dello stato e strumenti attraverso l'ecosistema piu ampio di Vue.\n\nE ampiamente utilizzato per applicazioni a pagina singola, interfacce interattive, sistemi di design, dashboard, widget incorporati e applicazioni web full-stack con framework come Nuxt."
+    },
+    fr: {
+      name: "Vue",
+      description: "Un framework JavaScript progressif pour la creation d'interfaces utilisateur avec des composants reactifs.",
+      longDescription: "Vue est un framework progressif pour la creation d'interfaces utilisateur avec des composants a fichier unique, des modeles declaratifs, la reactivite, les API de composition, le routage, la gestion de l'etat et des outils grace a l'ecosysteme Vue plus large.\n\nIl est largement utilise pour les applications monopages, les interfaces interactives, les systemes de conception, les tableaux de bord, les widgets embarques et les applications web completes avec des frameworks tels que Nuxt."
     }
   }
 };

package/dist/languages/vue.cjs.map

@@ -1 +1 @@
-{"version":3,"sources":["../../src/languages/vue.ts"],"names":[],"mappings":";;;AAEO,IAAM,GAAA,GAAM;AAAA,EACjB,IAAA,EAAM,KAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAM,CAAA;AAAA,EACnB,MAAA,EAAQ,0BAAA;AAAA,EACR,OAAA,EAAS,mBAAA;AAAA,EACT,SAAA,EAAW,CAAC,iBAAA,EAAmB,aAAA,EAAe,UAAU,CAAA;AAAA,EACxD,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,SAAA,EAAW,SAAS,CAAA;AAAA,IAC/B,eAAA,EAAiB,CAAC,KAAA,EAAO,MAAA,EAAQ,QAAQ,KAAK,CAAA;AAAA,IAC9C,UAAA,EAAY,CAAC,KAAA,EAAO,KAAA,EAAO,QAAQ,MAAM;AAAA,GAC3C;AAAA,EACA,OAAA,EAAS,QAAA;AAAA,EACT,IAAA,EAAM,uEAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,KAAA;AAAA,MACN,WAAA,EACE,2FAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,KAAA;AAAA,MACN,WAAA,EACE,wFAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vue.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vue = {\n  slug: \"vue\",\n  publishedDate: \"2014-02-01\",\n  extensions: [\".vue\"],\n  author: \"Evan You / Vue Core Team\",\n  website: \"https://vuejs.org\",\n  paradigms: [\"component-based\", \"declarative\", \"reactive\"],\n  tooling: {\n    runtimes: [\"Browser\", \"Node.js\"],\n    packageManagers: [\"npm\", \"pnpm\", \"Yarn\", \"Bun\"],\n    ecosystems: [\"Web\", \"Vue\", \"Vite\", \"Nuxt\"],\n  },\n  version: \"3.5.34\",\n  logo: \"https://upload.wikimedia.org/wikipedia/commons/9/95/Vue.js_Logo_2.svg\",\n  i18n: {\n    en: {\n      name: \"Vue\",\n      description:\n        \"A progressive JavaScript framework for building user interfaces with reactive components.\",\n      longDescription:\n        \"Vue is a progressive framework for building user interfaces with single-file components, declarative templates, reactivity, composition APIs, routing, state management, and tooling through the broader Vue ecosystem.\\n\\nIt is widely used for single-page applications, interactive interfaces, design systems, dashboards, embedded widgets, and full-stack web applications with frameworks such as Nuxt.\",\n    },\n    es: {\n      name: \"Vue\",\n      description:\n        \"Un framework progresivo de JavaScript para crear interfaces con componentes reactivos.\",\n      longDescription:\n        \"Vue es un framework progresivo para crear interfaces de usuario con componentes de archivo unico, plantillas declarativas, reactividad, APIs de composicion, enrutamiento, gestion de estado y herramientas del ecosistema Vue.\\n\\nSe usa ampliamente en aplicaciones de una sola pagina, interfaces interactivas, sistemas de diseno, dashboards, widgets embebidos y aplicaciones web full-stack con frameworks como Nuxt.\",\n    },\n  },\n} satisfies Language;\n"]}
+{"version":3,"sources":["../../src/languages/vue.ts"],"names":[],"mappings":";;;AAEO,IAAM,GAAA,GAAM;AAAA,EACjB,IAAA,EAAM,KAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAM,CAAA;AAAA,EACnB,MAAA,EAAQ,0BAAA;AAAA,EACR,OAAA,EAAS,mBAAA;AAAA,EACT,SAAA,EAAW,CAAC,iBAAA,EAAmB,aAAA,EAAe,UAAU,CAAA;AAAA,EACxD,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,SAAA,EAAW,SAAS,CAAA;AAAA,IAC/B,eAAA,EAAiB,CAAC,KAAA,EAAO,MAAA,EAAQ,QAAQ,KAAK,CAAA;AAAA,IAC9C,UAAA,EAAY,CAAC,KAAA,EAAO,KAAA,EAAO,QAAQ,MAAM;AAAA,GAC3C;AAAA,EACA,OAAA,EAAS,QAAA;AAAA,EACT,IAAA,EAAM,uEAAA;AAAA,EACN,KAAA,EAAO,SAAA;AAAA,EACP,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,KAAA;AAAA,MACN,WAAA,EACE,2FAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,KAAA;AAAA,MACN,WAAA,EACE,wFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,KAAA;AAAA,MACN,WAAA,EACE,oGAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,KAAA;AAAA,MACN,WAAA,EACE,4GAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vue.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vue = {\n  slug: \"vue\",\n  publishedDate: \"2014-02-01\",\n  extensions: [\".vue\"],\n  author: \"Evan You / Vue Core Team\",\n  website: \"https://vuejs.org\",\n  paradigms: [\"component-based\", \"declarative\", \"reactive\"],\n  tooling: {\n    runtimes: [\"Browser\", \"Node.js\"],\n    packageManagers: [\"npm\", \"pnpm\", \"Yarn\", \"Bun\"],\n    ecosystems: [\"Web\", \"Vue\", \"Vite\", \"Nuxt\"],\n  },\n  version: \"3.5.34\",\n  logo: \"https://upload.wikimedia.org/wikipedia/commons/9/95/Vue.js_Logo_2.svg\",\n  color: \"#4FC08D\",\n  i18n: {\n    en: {\n      name: \"Vue\",\n      description:\n        \"A progressive JavaScript framework for building user interfaces with reactive components.\",\n      longDescription:\n        \"Vue is a progressive framework for building user interfaces with single-file components, declarative templates, reactivity, composition APIs, routing, state management, and tooling through the broader Vue ecosystem.\\n\\nIt is widely used for single-page applications, interactive interfaces, design systems, dashboards, embedded widgets, and full-stack web applications with frameworks such as Nuxt.\",\n    },\n    es: {\n      name: \"Vue\",\n      description:\n        \"Un framework progresivo de JavaScript para crear interfaces con componentes reactivos.\",\n      longDescription:\n        \"Vue es un framework progresivo para crear interfaces de usuario con componentes de archivo unico, plantillas declarativas, reactividad, APIs de composicion, enrutamiento, gestion de estado y herramientas del ecosistema Vue.\\n\\nSe usa ampliamente en aplicaciones de una sola pagina, interfaces interactivas, sistemas de diseno, dashboards, widgets embebidos y aplicaciones web full-stack con frameworks como Nuxt.\",\n    },\n    it: {\n      name: \"Vue\",\n      description:\n        \"Un framework JavaScript progressivo per la creazione di interfacce utente con componenti reattivi.\",\n      longDescription:\n        \"Vue e un framework progressivo per la creazione di interfacce utente con componenti a singolo file, modelli dichiarativi, reattivita, API di composizione, routing, gestione dello stato e strumenti attraverso l'ecosistema piu ampio di Vue.\\n\\nE ampiamente utilizzato per applicazioni a pagina singola, interfacce interattive, sistemi di design, dashboard, widget incorporati e applicazioni web full-stack con framework come Nuxt.\",\n    },\n    fr: {\n      name: \"Vue\",\n      description:\n        \"Un framework JavaScript progressif pour la creation d'interfaces utilisateur avec des composants reactifs.\",\n      longDescription:\n        \"Vue est un framework progressif pour la creation d'interfaces utilisateur avec des composants a fichier unique, des modeles declaratifs, la reactivite, les API de composition, le routage, la gestion de l'etat et des outils grace a l'ecosysteme Vue plus large.\\n\\nIl est largement utilise pour les applications monopages, les interfaces interactives, les systemes de conception, les tableaux de bord, les widgets embarques et les applications web completes avec des frameworks tels que Nuxt.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/vue.d.cts

@@ -12,6 +12,7 @@ declare const vue: {
     };
     version: string;
     logo: string;
+    color: "#4FC08D";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const vue: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/vue.d.ts

@@ -12,6 +12,7 @@ declare const vue: {
     };
     version: string;
     logo: string;
+    color: "#4FC08D";
     i18n: {
         en: {
             name: string;
@@ -23,6 +24,16 @@ declare const vue: {
             description: string;
             longDescription: string;
         };
+        it: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        fr: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
     };
 };
 

package/dist/languages/vue.js

@@ -13,6 +13,7 @@ var vue = {
   },
   version: "3.5.34",
   logo: "https://upload.wikimedia.org/wikipedia/commons/9/95/Vue.js_Logo_2.svg",
+  color: "#4FC08D",
   i18n: {
     en: {
       name: "Vue",
@@ -23,6 +24,16 @@ var vue = {
       name: "Vue",
       description: "Un framework progresivo de JavaScript para crear interfaces con componentes reactivos.",
       longDescription: "Vue es un framework progresivo para crear interfaces de usuario con componentes de archivo unico, plantillas declarativas, reactividad, APIs de composicion, enrutamiento, gestion de estado y herramientas del ecosistema Vue.\n\nSe usa ampliamente en aplicaciones de una sola pagina, interfaces interactivas, sistemas de diseno, dashboards, widgets embebidos y aplicaciones web full-stack con frameworks como Nuxt."
+    },
+    it: {
+      name: "Vue",
+      description: "Un framework JavaScript progressivo per la creazione di interfacce utente con componenti reattivi.",
+      longDescription: "Vue e un framework progressivo per la creazione di interfacce utente con componenti a singolo file, modelli dichiarativi, reattivita, API di composizione, routing, gestione dello stato e strumenti attraverso l'ecosistema piu ampio di Vue.\n\nE ampiamente utilizzato per applicazioni a pagina singola, interfacce interattive, sistemi di design, dashboard, widget incorporati e applicazioni web full-stack con framework come Nuxt."
+    },
+    fr: {
+      name: "Vue",
+      description: "Un framework JavaScript progressif pour la creation d'interfaces utilisateur avec des composants reactifs.",
+      longDescription: "Vue est un framework progressif pour la creation d'interfaces utilisateur avec des composants a fichier unique, des modeles declaratifs, la reactivite, les API de composition, le routage, la gestion de l'etat et des outils grace a l'ecosysteme Vue plus large.\n\nIl est largement utilise pour les applications monopages, les interfaces interactives, les systemes de conception, les tableaux de bord, les widgets embarques et les applications web completes avec des frameworks tels que Nuxt."
     }
   }
 };