code-languages 1.17.0 → 1.18.0

package/dist/languages/plantuml.js

@@ -0,0 +1,32 @@
+// src/languages/plantuml.ts
+var plantuml = {
+  slug: "plantuml",
+  publishedDate: "2009-04-17",
+  extensions: [".puml", ".plantuml", ".iuml"],
+  author: "Arnaud Roques / PlantUML contributors",
+  website: "https://plantuml.com",
+  paradigms: ["declarative", "diagramming", "modeling"],
+  tooling: {
+    runtimes: ["Java", "PlantUML Server"],
+    packageManagers: ["Maven", "Gradle", "npm"],
+    ecosystems: ["UML", "Architecture", "Documentation", "Diagrams"]
+  },
+  version: "1.2026.3",
+  logo: "https://plantuml.com/logo3.png",
+  i18n: {
+    en: {
+      name: "PlantUML",
+      description: "A text-based diagram language for UML, architecture, and documentation diagrams.",
+      longDescription: "PlantUML is a diagram language and renderer for sequence, class, activity, component, state, object, deployment, timing, mind map, and architecture diagrams. It lets teams keep diagrams in source control and generate images from compact text.\n\nIt is used in software architecture documentation, design reviews, technical specs, wikis, CI-generated diagrams, and projects that prefer versionable diagrams over manually edited drawing files."
+    },
+    es: {
+      name: "PlantUML",
+      description: "Un lenguaje textual de diagramas para UML, arquitectura y documentacion.",
+      longDescription: "PlantUML es un lenguaje y renderer de diagramas para secuencia, clases, actividad, componentes, estados, objetos, despliegue, timing, mapas mentales y arquitectura. Permite mantener diagramas en control de versiones y generar imagenes desde texto compacto.\n\nSe usa en documentacion de arquitectura de software, revisiones de diseno, especificaciones tecnicas, wikis, diagramas generados en CI y proyectos que prefieren diagramas versionables a archivos de dibujo editados manualmente."
+    }
+  }
+};
+
+export { plantuml };
+//# sourceMappingURL=plantuml.js.map
+//# sourceMappingURL=plantuml.js.map

package/dist/languages/plantuml.js.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/plantuml.ts"],"names":[],"mappings":";AAEO,IAAM,QAAA,GAAW;AAAA,EACtB,IAAA,EAAM,UAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,OAAA,EAAS,WAAA,EAAa,OAAO,CAAA;AAAA,EAC1C,MAAA,EAAQ,uCAAA;AAAA,EACR,OAAA,EAAS,sBAAA;AAAA,EACT,SAAA,EAAW,CAAC,aAAA,EAAe,aAAA,EAAe,UAAU,CAAA;AAAA,EACpD,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,MAAA,EAAQ,iBAAiB,CAAA;AAAA,IACpC,eAAA,EAAiB,CAAC,OAAA,EAAS,QAAA,EAAU,KAAK,CAAA;AAAA,IAC1C,UAAA,EAAY,CAAC,KAAA,EAAO,cAAA,EAAgB,iBAAiB,UAAU;AAAA,GACjE;AAAA,EACA,OAAA,EAAS,UAAA;AAAA,EACT,IAAA,EAAM,gCAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,UAAA;AAAA,MACN,WAAA,EACE,kFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,UAAA;AAAA,MACN,WAAA,EAAa,0EAAA;AAAA,MACb,eAAA,EACE;AAAA;AACJ;AAEJ","file":"plantuml.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const plantuml = {\n  slug: \"plantuml\",\n  publishedDate: \"2009-04-17\",\n  extensions: [\".puml\", \".plantuml\", \".iuml\"],\n  author: \"Arnaud Roques / PlantUML contributors\",\n  website: \"https://plantuml.com\",\n  paradigms: [\"declarative\", \"diagramming\", \"modeling\"],\n  tooling: {\n    runtimes: [\"Java\", \"PlantUML Server\"],\n    packageManagers: [\"Maven\", \"Gradle\", \"npm\"],\n    ecosystems: [\"UML\", \"Architecture\", \"Documentation\", \"Diagrams\"],\n  },\n  version: \"1.2026.3\",\n  logo: \"https://plantuml.com/logo3.png\",\n  i18n: {\n    en: {\n      name: \"PlantUML\",\n      description:\n        \"A text-based diagram language for UML, architecture, and documentation diagrams.\",\n      longDescription:\n        \"PlantUML is a diagram language and renderer for sequence, class, activity, component, state, object, deployment, timing, mind map, and architecture diagrams. It lets teams keep diagrams in source control and generate images from compact text.\\n\\nIt is used in software architecture documentation, design reviews, technical specs, wikis, CI-generated diagrams, and projects that prefer versionable diagrams over manually edited drawing files.\",\n    },\n    es: {\n      name: \"PlantUML\",\n      description: \"Un lenguaje textual de diagramas para UML, arquitectura y documentacion.\",\n      longDescription:\n        \"PlantUML es un lenguaje y renderer de diagramas para secuencia, clases, actividad, componentes, estados, objetos, despliegue, timing, mapas mentales y arquitectura. Permite mantener diagramas en control de versiones y generar imagenes desde texto compacto.\\n\\nSe usa en documentacion de arquitectura de software, revisiones de diseno, especificaciones tecnicas, wikis, diagramas generados en CI y proyectos que prefieren diagramas versionables a archivos de dibujo editados manualmente.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/verilog.cjs

@@ -0,0 +1,34 @@
+'use strict';
+
+// src/languages/verilog.ts
+var verilog = {
+  slug: "verilog",
+  publishedDate: "1984-01-01",
+  extensions: [".v", ".vh", ".sv", ".svh"],
+  author: "Phil Moorby / Gateway Design Automation",
+  website: "https://standards.ieee.org/standard/1800-2023.html",
+  paradigms: ["hardware-description", "concurrent", "event-driven", "verification"],
+  tooling: {
+    runtimes: ["FPGA Toolchains", "ASIC EDA Tools", "Simulators"],
+    packageManagers: ["FuseSoC"],
+    ecosystems: ["Hardware Design", "FPGA", "ASIC", "Verification"]
+  },
+  version: "IEEE 1800-2023",
+  logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg",
+  i18n: {
+    en: {
+      name: "Verilog/SystemVerilog",
+      description: "A hardware description and verification language for digital circuits and systems.",
+      longDescription: "Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\n\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows."
+    },
+    es: {
+      name: "Verilog/SystemVerilog",
+      description: "Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.",
+      longDescription: "Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\n\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico."
+    }
+  }
+};
+
+exports.verilog = verilog;
+//# sourceMappingURL=verilog.cjs.map
+//# sourceMappingURL=verilog.cjs.map

package/dist/languages/verilog.cjs.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";;;AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/verilog.d.cts

@@ -0,0 +1,29 @@
+declare const verilog: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { verilog };

package/dist/languages/verilog.d.ts

@@ -0,0 +1,29 @@
+declare const verilog: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { verilog };

package/dist/languages/verilog.js

@@ -0,0 +1,32 @@
+// src/languages/verilog.ts
+var verilog = {
+  slug: "verilog",
+  publishedDate: "1984-01-01",
+  extensions: [".v", ".vh", ".sv", ".svh"],
+  author: "Phil Moorby / Gateway Design Automation",
+  website: "https://standards.ieee.org/standard/1800-2023.html",
+  paradigms: ["hardware-description", "concurrent", "event-driven", "verification"],
+  tooling: {
+    runtimes: ["FPGA Toolchains", "ASIC EDA Tools", "Simulators"],
+    packageManagers: ["FuseSoC"],
+    ecosystems: ["Hardware Design", "FPGA", "ASIC", "Verification"]
+  },
+  version: "IEEE 1800-2023",
+  logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg",
+  i18n: {
+    en: {
+      name: "Verilog/SystemVerilog",
+      description: "A hardware description and verification language for digital circuits and systems.",
+      longDescription: "Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\n\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows."
+    },
+    es: {
+      name: "Verilog/SystemVerilog",
+      description: "Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.",
+      longDescription: "Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\n\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico."
+    }
+  }
+};
+
+export { verilog };
+//# sourceMappingURL=verilog.js.map
+//# sourceMappingURL=verilog.js.map

package/dist/languages/verilog.js.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "code-languages",
-  "version": "1.17.0",
+  "version": "1.18.0",
   "description": "Structured metadata for programming languages.",
   "homepage": "https://github.com/ElJijuna/code-languages#readme",
   "bugs": {
@@ -86,6 +86,11 @@
       "import": "./dist/languages/batch.js",
       "require": "./dist/languages/batch.cjs"
     },
+    "./bicep": {
+      "types": "./dist/languages/bicep.d.ts",
+      "import": "./dist/languages/bicep.js",
+      "require": "./dist/languages/bicep.cjs"
+    },
     "./c": {
       "types": "./dist/languages/c.d.ts",
       "import": "./dist/languages/c.js",
@@ -111,6 +116,11 @@
       "import": "./dist/languages/crystal.js",
       "require": "./dist/languages/crystal.cjs"
     },
+    "./cue": {
+      "types": "./dist/languages/cue.d.ts",
+      "import": "./dist/languages/cue.js",
+      "require": "./dist/languages/cue.cjs"
+    },
     "./cuda": {
       "types": "./dist/languages/cuda.d.ts",
       "import": "./dist/languages/cuda.js",
@@ -151,6 +161,11 @@
       "import": "./dist/languages/typescript.js",
       "require": "./dist/languages/typescript.cjs"
     },
+    "./verilog": {
+      "types": "./dist/languages/verilog.d.ts",
+      "import": "./dist/languages/verilog.js",
+      "require": "./dist/languages/verilog.cjs"
+    },
     "./visual-basic": {
       "types": "./dist/languages/visual-basic.d.ts",
       "import": "./dist/languages/visual-basic.js",
@@ -256,11 +271,36 @@
       "import": "./dist/languages/java.js",
       "require": "./dist/languages/java.cjs"
     },
+    "./jinja": {
+      "types": "./dist/languages/jinja.d.ts",
+      "import": "./dist/languages/jinja.js",
+      "require": "./dist/languages/jinja.cjs"
+    },
+    "./liquid": {
+      "types": "./dist/languages/liquid.d.ts",
+      "import": "./dist/languages/liquid.js",
+      "require": "./dist/languages/liquid.cjs"
+    },
+    "./mdx": {
+      "types": "./dist/languages/mdx.d.ts",
+      "import": "./dist/languages/mdx.js",
+      "require": "./dist/languages/mdx.cjs"
+    },
+    "./mermaid": {
+      "types": "./dist/languages/mermaid.d.ts",
+      "import": "./dist/languages/mermaid.js",
+      "require": "./dist/languages/mermaid.cjs"
+    },
     "./php": {
       "types": "./dist/languages/php.d.ts",
       "import": "./dist/languages/php.js",
       "require": "./dist/languages/php.cjs"
     },
+    "./plantuml": {
+      "types": "./dist/languages/plantuml.d.ts",
+      "import": "./dist/languages/plantuml.js",
+      "require": "./dist/languages/plantuml.cjs"
+    },
     "./powershell": {
       "types": "./dist/languages/powershell.d.ts",
       "import": "./dist/languages/powershell.js",
@@ -391,6 +431,16 @@
       "import": "./dist/languages/fsharp.js",
       "require": "./dist/languages/fsharp.cjs"
     },
+    "./gdscript": {
+      "types": "./dist/languages/gdscript.d.ts",
+      "import": "./dist/languages/gdscript.js",
+      "require": "./dist/languages/gdscript.cjs"
+    },
+    "./handlebars": {
+      "types": "./dist/languages/handlebars.d.ts",
+      "import": "./dist/languages/handlebars.js",
+      "require": "./dist/languages/handlebars.cjs"
+    },
     "./html": {
       "types": "./dist/languages/html.d.ts",
       "import": "./dist/languages/html.js",