circuit-json 0.0.492 → 0.0.493

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (5) hide show
  1. package/README.md +2 -0
  2. package/dist/index.d.mts +18 -0
  3. package/dist/index.mjs +2 -0
  4. package/dist/index.mjs.map +1 -1
  5. package/package.json +1 -1
package/README.md CHANGED
@@ -3061,6 +3061,8 @@ interface PcbVia {
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  /** @deprecated */
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  to_layer?: LayerRef
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  layers: LayerRef[]
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+ /** PCB ports belonging to this via, including layer ports and aliases. */
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+ pcb_port_ids?: string[]
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  pcb_trace_id?: string
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  net_is_assignable?: boolean
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  net_assigned?: boolean
package/dist/index.d.mts CHANGED
@@ -8505,6 +8505,8 @@ declare const pcb_via: z.ZodEffects<z.ZodObject<{
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  }>]>, "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8", "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | {
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  name: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8";
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  }>, "many">;
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+ /** PCB ports belonging to this via, including layer ports and aliases. */
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+ pcb_port_ids: z.ZodOptional<z.ZodArray<z.ZodString, "many">>;
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  pcb_trace_id: z.ZodOptional<z.ZodString>;
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  source_trace_id: z.ZodOptional<z.ZodString>;
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  source_net_id: z.ZodOptional<z.ZodString>;
@@ -8530,6 +8532,7 @@ declare const pcb_via: z.ZodEffects<z.ZodObject<{
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  from_layer?: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
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  net_is_assignable?: boolean | undefined;
@@ -8556,6 +8559,7 @@ declare const pcb_via: z.ZodEffects<z.ZodObject<{
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  } | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  pcb_via_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
@@ -8578,6 +8582,7 @@ declare const pcb_via: z.ZodEffects<z.ZodObject<{
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  from_layer?: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
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  net_is_assignable?: boolean | undefined;
@@ -8603,6 +8608,7 @@ declare const pcb_via: z.ZodEffects<z.ZodObject<{
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  } | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  pcb_via_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
@@ -8629,6 +8635,8 @@ interface PcbVia {
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  /** @deprecated */
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  to_layer?: LayerRef;
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  layers: LayerRef[];
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+ /** PCB ports belonging to this via, including layer ports and aliases. */
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+ pcb_port_ids?: string[];
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  pcb_trace_id?: string;
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  source_trace_id?: string;
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  source_net_id?: string;
@@ -43748,6 +43756,7 @@ declare const any_circuit_element: z.ZodUnion<[z.ZodObject<{
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  }>]>, "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8", "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | {
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  name: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8";
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  }>, "many">;
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+ pcb_port_ids: z.ZodOptional<z.ZodArray<z.ZodString, "many">>;
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  pcb_trace_id: z.ZodOptional<z.ZodString>;
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  source_trace_id: z.ZodOptional<z.ZodString>;
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  source_net_id: z.ZodOptional<z.ZodString>;
@@ -43772,6 +43781,7 @@ declare const any_circuit_element: z.ZodUnion<[z.ZodObject<{
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  from_layer?: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
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  net_is_assignable?: boolean | undefined;
@@ -43798,6 +43808,7 @@ declare const any_circuit_element: z.ZodUnion<[z.ZodObject<{
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  } | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  pcb_via_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
@@ -43820,6 +43831,7 @@ declare const any_circuit_element: z.ZodUnion<[z.ZodObject<{
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  from_layer?: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
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  net_is_assignable?: boolean | undefined;
@@ -43845,6 +43857,7 @@ declare const any_circuit_element: z.ZodUnion<[z.ZodObject<{
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  } | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  pcb_via_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
@@ -64464,6 +64477,7 @@ declare const any_soup_element: z.ZodUnion<[z.ZodObject<{
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  }>]>, "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8", "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | {
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  name: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8";
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  }>, "many">;
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+ pcb_port_ids: z.ZodOptional<z.ZodArray<z.ZodString, "many">>;
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  pcb_trace_id: z.ZodOptional<z.ZodString>;
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  source_trace_id: z.ZodOptional<z.ZodString>;
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  source_net_id: z.ZodOptional<z.ZodString>;
@@ -64488,6 +64502,7 @@ declare const any_soup_element: z.ZodUnion<[z.ZodObject<{
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  from_layer?: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
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  net_is_assignable?: boolean | undefined;
@@ -64514,6 +64529,7 @@ declare const any_soup_element: z.ZodUnion<[z.ZodObject<{
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  } | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  pcb_via_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
@@ -64536,6 +64552,7 @@ declare const any_soup_element: z.ZodUnion<[z.ZodObject<{
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  from_layer?: "top" | "bottom" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
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  net_is_assignable?: boolean | undefined;
@@ -64561,6 +64578,7 @@ declare const any_soup_element: z.ZodUnion<[z.ZodObject<{
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  } | undefined;
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  source_trace_id?: string | undefined;
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  pcb_trace_id?: string | undefined;
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+ pcb_port_ids?: string[] | undefined;
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  source_net_id?: string | undefined;
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  pcb_via_id?: string | undefined;
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  subcircuit_connectivity_map_key?: string | undefined;
package/dist/index.mjs CHANGED
@@ -2749,6 +2749,8 @@ var pcb_via = z127.object({
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  /** @deprecated */
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  to_layer: layer_ref.optional(),
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  layers: z127.array(layer_ref),
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+ /** PCB ports belonging to this via, including layer ports and aliases. */
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+ pcb_port_ids: z127.array(z127.string()).optional(),
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  pcb_trace_id: z127.string().optional(),
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  source_trace_id: z127.string().optional(),
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  source_net_id: z127.string().min(1).optional(),