circuit-json-to-spice 0.0.40 → 0.0.41
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
package/package.json
CHANGED
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@@ -0,0 +1,472 @@
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[
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{
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"type": "source_project_metadata",
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4
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"source_project_metadata_id": "source_project_metadata_0",
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5
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"software_used_string": "@tscircuit/core@0.0.874"
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},
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{
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"type": "source_group",
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9
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"source_group_id": "source_group_0",
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10
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"is_subcircuit": true,
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"was_automatically_named": true,
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"subcircuit_id": "subcircuit_source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_0",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "terminal1", "1"],
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"source_component_id": "source_component_0",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_1",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "terminal2", "2"],
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"source_component_id": "source_component_0",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net2"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_0",
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"ftype": "simple_voltage_source",
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"name": "VS1",
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"voltage": 5,
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"frequency": 60,
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"wave_shape": "sinewave",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_2",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "anode", "pos", "left", "1"],
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"source_component_id": "source_component_1",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_3",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "cathode", "neg", "right", "2"],
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"source_component_id": "source_component_1",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net1"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_1",
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"ftype": "simple_resistor",
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"name": "R1",
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"resistance": 10000,
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"display_resistance": "10kΩ",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_4",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "anode", "pos", "left", "1"],
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"source_component_id": "source_component_2",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net1"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_5",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "cathode", "neg", "right", "2"],
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"source_component_id": "source_component_2",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net2"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_2",
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"ftype": "simple_resistor",
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"name": "R2",
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"resistance": 10000,
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"display_resistance": "10kΩ",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_board",
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"source_board_id": "source_board_0",
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_0",
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"connected_source_port_ids": ["source_port_0", "source_port_2"],
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"connected_source_net_ids": [],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".VS1 > .pin1 to .R1 > .pin1",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net0"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_1",
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"connected_source_port_ids": ["source_port_3", "source_port_4"],
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"connected_source_net_ids": [],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".R1 > .pin2 to .R2 > .pin1",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net1"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_2",
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"connected_source_port_ids": ["source_port_1", "source_port_5"],
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"connected_source_net_ids": [],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".VS1 > .pin2 to .R2 > .pin2",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net2"
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},
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{
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"type": "simulation_voltage_source",
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"simulation_voltage_source_id": "simulation_voltage_source_0",
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"is_dc_source": true,
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"terminal1_source_port_id": "source_port_0",
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"terminal2_source_port_id": "source_port_1",
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"voltage": 5
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},
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{
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"type": "schematic_component",
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"schematic_component_id": "schematic_component_0",
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"center": {
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"x": 0,
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"y": 0
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},
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"size": {
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"width": 1.08,
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"height": 0.818910699999999
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},
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"source_component_id": "source_component_0",
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"is_box_with_pins": true,
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"symbol_name": "ac_voltmeter_right",
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"schematic_group_id": "schematic_group_0"
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},
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{
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"type": "schematic_component",
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"schematic_component_id": "schematic_component_1",
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"center": {
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"x": 0,
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"y": -2
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},
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"size": {
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"width": 1.1,
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"height": 0.388910699999999
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},
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"source_component_id": "source_component_1",
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"is_box_with_pins": true,
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"symbol_name": "boxresistor_right",
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"symbol_display_value": "10kΩ",
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"schematic_group_id": "schematic_group_0"
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},
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{
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"type": "schematic_component",
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"schematic_component_id": "schematic_component_2",
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"center": {
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"x": 0,
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"y": 2
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},
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"size": {
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"width": 1.1,
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"height": 0.388910699999999
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},
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"source_component_id": "source_component_2",
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"is_box_with_pins": true,
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"symbol_name": "boxresistor_right",
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"symbol_display_value": "10kΩ",
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"schematic_group_id": "schematic_group_0"
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},
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{
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"type": "schematic_group",
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"schematic_group_id": "schematic_group_0",
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"is_subcircuit": true,
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"subcircuit_id": "subcircuit_source_group_0",
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"name": "unnamed_board1",
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"center": {
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"x": 0,
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"y": 0
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},
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"width": 0,
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"height": 0,
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"schematic_component_ids": [],
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"source_group_id": "source_group_0"
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_0",
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"schematic_component_id": "schematic_component_0",
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"center": {
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"x": -0.54,
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"y": -0.0050000000000000044
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},
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"source_port_id": "source_port_0",
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"facing_direction": "left",
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"distance_from_component_edge": 0.4,
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"pin_number": 1,
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"display_pin_label": "terminal1",
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"is_connected": true
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_1",
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"schematic_component_id": "schematic_component_0",
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"center": {
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"x": 0.54,
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"y": 0.0049999999999999975
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},
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"source_port_id": "source_port_1",
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"facing_direction": "right",
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"distance_from_component_edge": 0.4,
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"pin_number": 2,
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"display_pin_label": "terminal2",
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"is_connected": true
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_2",
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"schematic_component_id": "schematic_component_1",
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"center": {
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"x": -0.55,
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"y": -1.9999999999999998
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},
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"source_port_id": "source_port_2",
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"facing_direction": "left",
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"distance_from_component_edge": 0.4,
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"pin_number": 1,
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"display_pin_label": "anode",
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"is_connected": true
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_3",
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"schematic_component_id": "schematic_component_1",
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"center": {
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"x": 0.55,
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"y": -1.9999999999999998
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},
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"source_port_id": "source_port_3",
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"facing_direction": "right",
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"distance_from_component_edge": 0.4,
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"pin_number": 2,
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"display_pin_label": "cathode",
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"is_connected": false
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_4",
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"schematic_component_id": "schematic_component_2",
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"center": {
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"x": -0.55,
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"y": 2
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},
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"source_port_id": "source_port_4",
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"facing_direction": "left",
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"distance_from_component_edge": 0.4,
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"pin_number": 1,
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"display_pin_label": "anode",
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"is_connected": false
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_5",
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"schematic_component_id": "schematic_component_2",
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"center": {
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"x": 0.55,
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"y": 2
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},
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"source_port_id": "source_port_5",
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"facing_direction": "right",
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"distance_from_component_edge": 0.4,
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"pin_number": 2,
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"display_pin_label": "cathode",
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"is_connected": true
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},
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{
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"type": "schematic_trace",
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"schematic_trace_id": "schematic_trace_0",
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"source_trace_id": "solver_VS1.1-R1.1",
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"edges": [
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{
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"from": {
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"x": -0.54,
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"y": -0.0050000000000000044
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},
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"to": {
|
|
311
|
+
"x": -0.75,
|
|
312
|
+
"y": -0.0050000000000000044
|
|
313
|
+
}
|
|
314
|
+
},
|
|
315
|
+
{
|
|
316
|
+
"from": {
|
|
317
|
+
"x": -0.75,
|
|
318
|
+
"y": -0.0050000000000000044
|
|
319
|
+
},
|
|
320
|
+
"to": {
|
|
321
|
+
"x": -0.75,
|
|
322
|
+
"y": -1.9999999999999998
|
|
323
|
+
}
|
|
324
|
+
},
|
|
325
|
+
{
|
|
326
|
+
"from": {
|
|
327
|
+
"x": -0.75,
|
|
328
|
+
"y": -1.9999999999999998
|
|
329
|
+
},
|
|
330
|
+
"to": {
|
|
331
|
+
"x": -0.55,
|
|
332
|
+
"y": -1.9999999999999998
|
|
333
|
+
}
|
|
334
|
+
}
|
|
335
|
+
],
|
|
336
|
+
"junctions": [],
|
|
337
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net0"
|
|
338
|
+
},
|
|
339
|
+
{
|
|
340
|
+
"type": "schematic_trace",
|
|
341
|
+
"schematic_trace_id": "schematic_trace_1",
|
|
342
|
+
"source_trace_id": "solver_VS1.2-R2.2",
|
|
343
|
+
"edges": [
|
|
344
|
+
{
|
|
345
|
+
"from": {
|
|
346
|
+
"x": 0.54,
|
|
347
|
+
"y": 0.0049999999999999975
|
|
348
|
+
},
|
|
349
|
+
"to": {
|
|
350
|
+
"x": 0.75,
|
|
351
|
+
"y": 0.0049999999999999975
|
|
352
|
+
}
|
|
353
|
+
},
|
|
354
|
+
{
|
|
355
|
+
"from": {
|
|
356
|
+
"x": 0.75,
|
|
357
|
+
"y": 0.0049999999999999975
|
|
358
|
+
},
|
|
359
|
+
"to": {
|
|
360
|
+
"x": 0.75,
|
|
361
|
+
"y": 2
|
|
362
|
+
}
|
|
363
|
+
},
|
|
364
|
+
{
|
|
365
|
+
"from": {
|
|
366
|
+
"x": 0.75,
|
|
367
|
+
"y": 2
|
|
368
|
+
},
|
|
369
|
+
"to": {
|
|
370
|
+
"x": 0.55,
|
|
371
|
+
"y": 2
|
|
372
|
+
}
|
|
373
|
+
}
|
|
374
|
+
],
|
|
375
|
+
"junctions": [],
|
|
376
|
+
"subcircuit_connectivity_map_key": "unnamedsubcircuit303_connectivity_net2"
|
|
377
|
+
},
|
|
378
|
+
{
|
|
379
|
+
"type": "schematic_net_label",
|
|
380
|
+
"schematic_net_label_id": "schematic_net_label_0",
|
|
381
|
+
"text": "R1_pin2/R2_pin1",
|
|
382
|
+
"anchor_position": {
|
|
383
|
+
"x": 0.55,
|
|
384
|
+
"y": -1.9999999999999998
|
|
385
|
+
},
|
|
386
|
+
"center": {
|
|
387
|
+
"x": 1.3,
|
|
388
|
+
"y": -1.9999999999999998
|
|
389
|
+
},
|
|
390
|
+
"anchor_side": "left"
|
|
391
|
+
},
|
|
392
|
+
{
|
|
393
|
+
"type": "schematic_net_label",
|
|
394
|
+
"schematic_net_label_id": "schematic_net_label_1",
|
|
395
|
+
"text": "R1_pin2/R2_pin1",
|
|
396
|
+
"anchor_position": {
|
|
397
|
+
"x": -0.55,
|
|
398
|
+
"y": 2
|
|
399
|
+
},
|
|
400
|
+
"center": {
|
|
401
|
+
"x": -1.3,
|
|
402
|
+
"y": 2
|
|
403
|
+
},
|
|
404
|
+
"anchor_side": "right"
|
|
405
|
+
},
|
|
406
|
+
{
|
|
407
|
+
"type": "pcb_component",
|
|
408
|
+
"pcb_component_id": "pcb_component_0",
|
|
409
|
+
"center": {
|
|
410
|
+
"x": 0,
|
|
411
|
+
"y": -2
|
|
412
|
+
},
|
|
413
|
+
"width": 0,
|
|
414
|
+
"height": 0,
|
|
415
|
+
"layer": "top",
|
|
416
|
+
"rotation": 0,
|
|
417
|
+
"source_component_id": "source_component_1",
|
|
418
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
419
|
+
"do_not_place": false,
|
|
420
|
+
"obstructs_within_bounds": true
|
|
421
|
+
},
|
|
422
|
+
{
|
|
423
|
+
"type": "pcb_missing_footprint_error",
|
|
424
|
+
"pcb_missing_footprint_error_id": "pcb_missing_footprint_error_0",
|
|
425
|
+
"message": "No footprint found for component: <resistor#294 name=\".R1\" />",
|
|
426
|
+
"source_component_id": "source_component_1",
|
|
427
|
+
"error_type": "pcb_missing_footprint_error"
|
|
428
|
+
},
|
|
429
|
+
{
|
|
430
|
+
"type": "pcb_component",
|
|
431
|
+
"pcb_component_id": "pcb_component_1",
|
|
432
|
+
"center": {
|
|
433
|
+
"x": 0,
|
|
434
|
+
"y": 2
|
|
435
|
+
},
|
|
436
|
+
"width": 0,
|
|
437
|
+
"height": 0,
|
|
438
|
+
"layer": "top",
|
|
439
|
+
"rotation": 0,
|
|
440
|
+
"source_component_id": "source_component_2",
|
|
441
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
442
|
+
"do_not_place": false,
|
|
443
|
+
"obstructs_within_bounds": true
|
|
444
|
+
},
|
|
445
|
+
{
|
|
446
|
+
"type": "pcb_missing_footprint_error",
|
|
447
|
+
"pcb_missing_footprint_error_id": "pcb_missing_footprint_error_1",
|
|
448
|
+
"message": "No footprint found for component: <resistor#297 name=\".R2\" />",
|
|
449
|
+
"source_component_id": "source_component_2",
|
|
450
|
+
"error_type": "pcb_missing_footprint_error"
|
|
451
|
+
},
|
|
452
|
+
{
|
|
453
|
+
"type": "pcb_board",
|
|
454
|
+
"pcb_board_id": "pcb_board_0",
|
|
455
|
+
"center": {
|
|
456
|
+
"x": 0,
|
|
457
|
+
"y": 0
|
|
458
|
+
},
|
|
459
|
+
"thickness": 1.4,
|
|
460
|
+
"num_layers": 2,
|
|
461
|
+
"width": 10,
|
|
462
|
+
"height": 10,
|
|
463
|
+
"material": "fr4"
|
|
464
|
+
},
|
|
465
|
+
{
|
|
466
|
+
"type": "pcb_autorouting_error",
|
|
467
|
+
"pcb_autorouting_error_id": "pcb_autorouting_error_0",
|
|
468
|
+
"pcb_error_id": "pcb_autorouter_error_subcircuit_subcircuit_source_group_0",
|
|
469
|
+
"error_type": "pcb_autorouting_error",
|
|
470
|
+
"message": "En ran out of iterations (capacity-autorouter@0.0.140)"
|
|
471
|
+
}
|
|
472
|
+
]
|
|
@@ -0,0 +1,17 @@
|
|
|
1
|
+
import { expect, test } from "bun:test"
|
|
2
|
+
import { circuitJsonToSpice } from "lib/circuitJsonToSpice"
|
|
3
|
+
import dcVoltageSource from "./assets/dc-voltage-source-terminals.json"
|
|
4
|
+
|
|
5
|
+
// A DC voltage source that uses terminal1_source_port_id/terminal2_source_port_id
|
|
6
|
+
// (instead of positive/negative) is silently dropped, so no V line is emitted.
|
|
7
|
+
test.failing("DC voltage source using terminal1/terminal2", () => {
|
|
8
|
+
const spiceString = circuitJsonToSpice(dcVoltageSource as any).toSpiceString()
|
|
9
|
+
|
|
10
|
+
expect(spiceString).toMatchInlineSnapshot(`
|
|
11
|
+
"* Circuit JSON to SPICE Netlist
|
|
12
|
+
RR1 N1 N2 10K
|
|
13
|
+
RR2 N2 0 10K
|
|
14
|
+
Vsimulation_voltage_source_0 N1 0 DC 5
|
|
15
|
+
.END"
|
|
16
|
+
`)
|
|
17
|
+
})
|