ac6502 1.2.0 → 1.4.0

package/README.md

@@ -183,18 +183,18 @@ src/
 │   ├── Cart.ts             # Cartridge support
 │   ├── IO.ts               # I/O interface
 │   └── IO/                 # I/O peripheral implementations
-│       ├── GPIOCard.ts
-│       ├── RAMCard.ts
-│       ├── RTCCard.ts
-│       ├── SerialCard.ts
-│       ├── SoundCard.ts
-│       ├── StorageCard.ts
-│       ├── VideoCard.ts
-│       └── GPIOAttachments/
-│           ├── GPIOAttachment.ts
-│           ├── GPIOJoystickAttachment.ts
-│           ├── GPIOKeyboardEncoderAttachment.ts
-│           └── GPIOKeyboardMatrixAttachment.ts
+│       ├── VIA.ts
+│       ├── RAMBank.ts
+│       ├── RTC.ts
+│       ├── ACIA.ts
+│       ├── Sound.ts
+│       ├── Storage.ts
+│       ├── Video.ts
+│       └── Attachments/
+│           ├── Attachment.ts
+│           ├── JoystickAttachment.ts
+│           ├── KeyboardEncoderAttachment.ts
+│           └── KeyboardMatrixAttachment.ts
 └── tests/                  # Comprehensive test suite
 ```
 

package/dist/components/CPU.d.ts

@@ -0,0 +1,162 @@
+export interface CPUInstruction {
+    name: string;
+    cycles: number;
+    opcode: () => number;
+    addrMode: () => number;
+}
+export declare class CPU {
+    static C: number;
+    static Z: number;
+    static I: number;
+    static D: number;
+    static B: number;
+    static U: number;
+    static V: number;
+    static N: number;
+    private fetched;
+    private temp;
+    private addrAbs;
+    private addrRel;
+    private opcode;
+    cyclesRem: number;
+    cycles: number;
+    a: number;
+    x: number;
+    y: number;
+    pc: number;
+    sp: number;
+    st: number;
+    read: (address: number) => number;
+    write: (address: number, data: number) => void;
+    constructor(read: (address: number) => number, write: (address: number, data: number) => void);
+    reset(): void;
+    irq(): void;
+    nmi(): void;
+    tick(): void;
+    step(): number;
+    private fetch;
+    private getFlag;
+    private setFlag;
+    private incPC;
+    private decPC;
+    private incSP;
+    private decSP;
+    private IMP;
+    private IMM;
+    private ZP0;
+    private ZPX;
+    private ZPY;
+    private REL;
+    private ABS;
+    private ABX;
+    private ABY;
+    private IND;
+    private IZX;
+    private IZY;
+    private IAX;
+    private ZPR;
+    private ADC;
+    private AND;
+    private ASL;
+    private BCC;
+    private BCS;
+    private BEQ;
+    private BIT;
+    private BMI;
+    private BNE;
+    private BPL;
+    private BRK;
+    private BVC;
+    private BVS;
+    private CLC;
+    private CLD;
+    private CLI;
+    private CLV;
+    private CMP;
+    private CPX;
+    private CPY;
+    private DEC;
+    private DEX;
+    private DEY;
+    private EOR;
+    private INC;
+    private INX;
+    private INY;
+    private JMP;
+    private JSR;
+    private LDA;
+    private LDX;
+    private LDY;
+    private LSR;
+    private NOP;
+    private ORA;
+    private PHA;
+    private PHP;
+    private PLA;
+    private PLP;
+    private ROL;
+    private ROR;
+    private RTI;
+    private RTS;
+    private SBC;
+    private SEC;
+    private SED;
+    private SEI;
+    private STA;
+    private STX;
+    private STY;
+    private TAX;
+    private TAY;
+    private TSX;
+    private TXA;
+    private TXS;
+    private TYA;
+    private BRA;
+    private PHX;
+    private PHY;
+    private PLX;
+    private PLY;
+    private STZ;
+    private TRB;
+    private TSB;
+    private STP;
+    private WAI;
+    private BBR;
+    private BBR0;
+    private BBR1;
+    private BBR2;
+    private BBR3;
+    private BBR4;
+    private BBR5;
+    private BBR6;
+    private BBR7;
+    private BBS;
+    private BBS0;
+    private BBS1;
+    private BBS2;
+    private BBS3;
+    private BBS4;
+    private BBS5;
+    private BBS6;
+    private BBS7;
+    private RMB;
+    private RMB0;
+    private RMB1;
+    private RMB2;
+    private RMB3;
+    private RMB4;
+    private RMB5;
+    private RMB6;
+    private RMB7;
+    private SMB;
+    private SMB0;
+    private SMB1;
+    private SMB2;
+    private SMB3;
+    private SMB4;
+    private SMB5;
+    private SMB6;
+    private SMB7;
+    private XXX;
+    instructionTable: CPUInstruction[];
+}

package/dist/components/Cart.d.ts

@@ -0,0 +1,9 @@
+export declare class Cart {
+    static START: number;
+    static END: number;
+    static CODE: number;
+    static SIZE: number;
+    data: number[];
+    read(address: number): number;
+    load(data: number[]): void;
+}

package/dist/components/IO/ACIA.d.ts

@@ -0,0 +1,76 @@
+import { IO } from '../IO';
+/**
+ * ACIA - Emulates a 6551 ACIA (Asynchronous Communications Interface Adapter)
+ *
+ * Register Map:
+ * $00: Data Register (read/write)
+ * $01: Status Register (read) / Programmed Reset (write)
+ * $02: Command Register (write)
+ * $03: Control Register (write)
+ */
+export declare class ACIA implements IO {
+    raiseIRQ: () => void;
+    raiseNMI: () => void;
+    transmit?: (data: number) => void;
+    private dataRegister;
+    private statusRegister;
+    private commandRegister;
+    private controlRegister;
+    private transmitBuffer;
+    private receiveBuffer;
+    private parityError;
+    private framingError;
+    private overrun;
+    private irqFlag;
+    private echoMode;
+    private cycleCounter;
+    private baudRate;
+    /**
+     * Read from ACIA register
+     */
+    read(address: number): number;
+    /**
+     * Write to ACIA register
+     */
+    write(address: number, data: number): void;
+    /**
+     * Read data from receive buffer
+     */
+    private readData;
+    /**
+     * Write data to transmit buffer
+     */
+    private writeData;
+    /**
+     * Read status register
+     */
+    private readStatus;
+    /**
+     * Write to command register
+     */
+    private writeCommand;
+    /**
+     * Write to control register
+     */
+    private writeControl;
+    /**
+     * Get baud rate from control register code
+     */
+    private getBaudRate;
+    /**
+     * Programmed reset
+     */
+    private programmedReset;
+    /**
+     * Tick - emulate ACIA timing
+     */
+    tick(frequency: number): void;
+    /**
+     * Reset the ACIA
+     */
+    reset(coldStart: boolean): void;
+    /**
+     * Receive data from external source
+     */
+    onData(data: number): void;
+}

package/dist/components/IO/ACIA.js

@@ -0,0 +1,282 @@
+"use strict";
+Object.defineProperty(exports, "__esModule", { value: true });
+exports.ACIA = void 0;
+/**
+ * ACIA - Emulates a 6551 ACIA (Asynchronous Communications Interface Adapter)
+ *
+ * Register Map:
+ * $00: Data Register (read/write)
+ * $01: Status Register (read) / Programmed Reset (write)
+ * $02: Command Register (write)
+ * $03: Control Register (write)
+ */
+class ACIA {
+    constructor() {
+        this.raiseIRQ = () => { };
+        this.raiseNMI = () => { };
+        // Registers
+        this.dataRegister = 0;
+        this.statusRegister = 0x10; // Transmit Data Register Empty
+        this.commandRegister = 0;
+        this.controlRegister = 0;
+        // Buffers
+        this.transmitBuffer = [];
+        this.receiveBuffer = [];
+        // Status flags
+        this.parityError = false;
+        this.framingError = false;
+        this.overrun = false;
+        this.irqFlag = false;
+        this.echoMode = false;
+        // Timing
+        this.cycleCounter = 0;
+        this.baudRate = 115200;
+    }
+    /**
+     * Read from ACIA register
+     */
+    read(address) {
+        const register = address & 0x03;
+        switch (register) {
+            case 0x00: // Data Register
+                return this.readData();
+            case 0x01: // Status Register
+                return this.readStatus();
+            case 0x02: // Command Register
+                return this.commandRegister;
+            case 0x03: // Control Register
+                return this.controlRegister;
+            default:
+                return 0;
+        }
+    }
+    /**
+     * Write to ACIA register
+     */
+    write(address, data) {
+        const register = address & 0x03;
+        switch (register) {
+            case 0x00: // Data Register
+                this.writeData(data);
+                break;
+            case 0x01: // Programmed Reset
+                this.programmedReset();
+                break;
+            case 0x02: // Command Register
+                this.writeCommand(data);
+                break;
+            case 0x03: // Control Register
+                this.writeControl(data);
+                break;
+        }
+    }
+    /**
+     * Read data from receive buffer
+     */
+    readData() {
+        if (this.receiveBuffer.length > 0) {
+            const data = this.receiveBuffer.shift();
+            this.dataRegister = data;
+            // Update status: clear Receive Data Register Full
+            this.statusRegister &= ~0x08;
+            // Check for overrun if more data arrives
+            if (this.receiveBuffer.length === 0) {
+                this.overrun = false;
+                this.statusRegister &= ~0x04;
+            }
+            // Clear IRQ if receive IRQ was enabled
+            if ((this.commandRegister & 0x04) && this.receiveBuffer.length === 0) {
+                this.irqFlag = false;
+                this.statusRegister &= ~0x80;
+            }
+            return data;
+        }
+        return this.dataRegister;
+    }
+    /**
+     * Write data to transmit buffer
+     */
+    writeData(data) {
+        this.transmitBuffer.push(data & 0xFF);
+        // Clear Transmit Data Register Empty flag
+        this.statusRegister &= ~0x10;
+    }
+    /**
+     * Read status register
+     */
+    readStatus() {
+        let status = 0;
+        // Bit 0: Parity Error
+        if (this.parityError)
+            status |= 0x01;
+        // Bit 1: Framing Error
+        if (this.framingError)
+            status |= 0x02;
+        // Bit 2: Overrun
+        if (this.overrun)
+            status |= 0x04;
+        // Bit 3: Receive Data Register Full
+        if (this.receiveBuffer.length > 0)
+            status |= 0x08;
+        // Bit 4: Transmit Data Register Empty
+        if (this.transmitBuffer.length === 0)
+            status |= 0x10;
+        // Bit 5: Data Carrier Detect (DCD) - always clear (connected)
+        status &= ~0x20;
+        // Bit 6: Data Set Ready (DSR) - always set (ready)
+        status |= 0x40;
+        // Bit 7: Interrupt (IRQ)
+        if (this.irqFlag)
+            status |= 0x80;
+        this.statusRegister = status;
+        return status;
+    }
+    /**
+     * Write to command register
+     */
+    writeCommand(data) {
+        this.commandRegister = data & 0xFF;
+        // Bits 0-1: DTR control
+        // const dtrControl = data & 0x03
+        // Bit 2: Receive IRQ Enable
+        const receiveIRQEnabled = (data & 0x04) !== 0;
+        // Bits 3-4: Transmit control and IRQ enable
+        // const transmitControl = (data >> 3) & 0x03
+        // Bit 5: Echo mode
+        this.echoMode = (data & 0x20) !== 0;
+        // Bits 6-7: Parity control
+        // const parityControl = (data >> 6) & 0x03
+        // Handle receive IRQ
+        if (receiveIRQEnabled && this.receiveBuffer.length > 0) {
+            this.irqFlag = true;
+            this.statusRegister |= 0x80;
+            this.raiseIRQ();
+        }
+        else if (!receiveIRQEnabled) {
+            this.irqFlag = false;
+            this.statusRegister &= ~0x80;
+        }
+    }
+    /**
+     * Write to control register
+     */
+    writeControl(data) {
+        this.controlRegister = data & 0xFF;
+        // Bits 0-3: Baud rate
+        const baudRateCode = data & 0x0F;
+        this.baudRate = this.getBaudRate(baudRateCode);
+        // Bit 4: Receiver clock source (internal/external)
+        const receiverClockSource = (data & 0x10) !== 0;
+        // Bits 5-6: Word length (5, 6, 7, or 8 bits)
+        const wordLength = ((data >> 5) & 0x03) + 5;
+        // Bit 7: Stop bits (1 or 2)
+        const stopBits = (data & 0x80) ? 2 : 1;
+    }
+    /**
+     * Get baud rate from control register code
+     */
+    getBaudRate(code) {
+        const baudRates = [
+            115200, // 0000 (actually 16x external clock, using 115200 as default)
+            50, // 0001
+            75, // 0010
+            110, // 0011
+            135, // 0100
+            150, // 0101
+            300, // 0110
+            600, // 0111
+            1200, // 1000
+            1800, // 1001
+            2400, // 1010
+            3600, // 1011
+            4800, // 1100
+            7200, // 1101
+            9600, // 1110
+            19200 // 1111
+        ];
+        return baudRates[code] || 115200;
+    }
+    /**
+     * Programmed reset
+     */
+    programmedReset() {
+        this.statusRegister = 0x10; // Transmit Data Register Empty
+        this.parityError = false;
+        this.framingError = false;
+        this.overrun = false;
+        this.irqFlag = false;
+    }
+    /**
+     * Tick - emulate ACIA timing
+     */
+    tick(frequency) {
+        this.cycleCounter++;
+        // Calculate cycles per byte: (CPU_CLOCK / baud_rate) * bits_per_frame
+        // Assuming 10 bits per frame (1 start + 8 data + 1 stop)
+        const cyclesPerByte = Math.floor((frequency / this.baudRate) * 10);
+        // Simulate transmission based on actual baud rate
+        if (this.cycleCounter >= cyclesPerByte && this.transmitBuffer.length > 0) {
+            this.cycleCounter = 0;
+            // Transmit one byte
+            const byte = this.transmitBuffer.shift();
+            if (byte !== undefined && this.transmit) {
+                this.transmit(byte);
+            }
+            // Set Transmit Data Register Empty if buffer is empty
+            if (this.transmitBuffer.length === 0) {
+                this.statusRegister |= 0x10;
+                // Trigger transmit complete IRQ if enabled
+                if ((this.commandRegister & 0x18) === 0x08) {
+                    this.irqFlag = true;
+                    this.statusRegister |= 0x80;
+                    this.raiseIRQ();
+                }
+            }
+        }
+    }
+    /**
+     * Reset the ACIA
+     */
+    reset(coldStart) {
+        this.dataRegister = 0;
+        this.statusRegister = 0x10; // Transmit Data Register Empty
+        this.commandRegister = 0;
+        this.controlRegister = 0;
+        this.transmitBuffer = [];
+        this.receiveBuffer = [];
+        this.parityError = false;
+        this.framingError = false;
+        this.overrun = false;
+        this.irqFlag = false;
+        this.echoMode = false;
+        this.cycleCounter = 0;
+        this.baudRate = 115200;
+    }
+    /**
+     * Receive data from external source
+     */
+    onData(data) {
+        if (this.receiveBuffer.length > 0 && (this.statusRegister & 0x08)) {
+            // Overrun condition: data arrives before previous data was read
+            this.overrun = true;
+            this.statusRegister |= 0x04;
+        }
+        this.receiveBuffer.push(data & 0xFF);
+        // Set Receive Data Register Full flag
+        this.statusRegister |= 0x08;
+        // Trigger receive IRQ if enabled
+        if (this.commandRegister & 0x04) {
+            this.irqFlag = true;
+            this.statusRegister |= 0x80;
+            this.raiseIRQ();
+        }
+        // Echo mode: automatically transmit received data
+        if (this.echoMode) {
+            this.transmitBuffer.push(data & 0xFF);
+            // Clear Transmit Data Register Empty flag
+            this.statusRegister &= ~0x10;
+        }
+    }
+}
+exports.ACIA = ACIA;
+//# sourceMappingURL=ACIA.js.map

package/dist/components/IO/ACIA.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"ACIA.js","sourceRoot":"","sources":["../../../src/components/IO/ACIA.ts"],"names":[],"mappings":";;;AAEA;;;;;;;;GAQG;AACH,MAAa,IAAI;IAAjB;QAEE,aAAQ,GAAG,GAAG,EAAE,GAAE,CAAC,CAAA;QACnB,aAAQ,GAAG,GAAG,EAAE,GAAE,CAAC,CAAA;QAGnB,YAAY;QACJ,iBAAY,GAAW,CAAC,CAAA;QACxB,mBAAc,GAAW,IAAI,CAAA,CAAE,+BAA+B;QAC9D,oBAAe,GAAW,CAAC,CAAA;QAC3B,oBAAe,GAAW,CAAC,CAAA;QAEnC,UAAU;QACF,mBAAc,GAAa,EAAE,CAAA;QAC7B,kBAAa,GAAa,EAAE,CAAA;QAEpC,eAAe;QACP,gBAAW,GAAY,KAAK,CAAA;QAC5B,iBAAY,GAAY,KAAK,CAAA;QAC7B,YAAO,GAAY,KAAK,CAAA;QACxB,YAAO,GAAY,KAAK,CAAA;QACxB,aAAQ,GAAY,KAAK,CAAA;QAEjC,SAAS;QACD,iBAAY,GAAW,CAAC,CAAA;QACxB,aAAQ,GAAW,MAAM,CAAA;IA0SnC,CAAC;IAxSC;;OAEG;IACH,IAAI,CAAC,OAAe;QAClB,MAAM,QAAQ,GAAG,OAAO,GAAG,IAAI,CAAA;QAE/B,QAAQ,QAAQ,EAAE,CAAC;YACjB,KAAK,IAAI,EAAE,gBAAgB;gBACzB,OAAO,IAAI,CAAC,QAAQ,EAAE,CAAA;YAExB,KAAK,IAAI,EAAE,kBAAkB;gBAC3B,OAAO,IAAI,CAAC,UAAU,EAAE,CAAA;YAE1B,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,OAAO,IAAI,CAAC,eAAe,CAAA;YAE7B,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,OAAO,IAAI,CAAC,eAAe,CAAA;YAE7B;gBACE,OAAO,CAAC,CAAA;QACZ,CAAC;IACH,CAAC;IAED;;OAEG;IACH,KAAK,CAAC,OAAe,EAAE,IAAY;QACjC,MAAM,QAAQ,GAAG,OAAO,GAAG,IAAI,CAAA;QAE/B,QAAQ,QAAQ,EAAE,CAAC;YACjB,KAAK,IAAI,EAAE,gBAAgB;gBACzB,IAAI,CAAC,SAAS,CAAC,IAAI,CAAC,CAAA;gBACpB,MAAK;YAEP,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,IAAI,CAAC,eAAe,EAAE,CAAA;gBACtB,MAAK;YAEP,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,IAAI,CAAC,YAAY,CAAC,IAAI,CAAC,CAAA;gBACvB,MAAK;YAEP,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,IAAI,CAAC,YAAY,CAAC,IAAI,CAAC,CAAA;gBACvB,MAAK;QACT,CAAC;IACH,CAAC;IAED;;OAEG;IACK,QAAQ;QACd,IAAI,IAAI,CAAC,aAAa,CAAC,MAAM,GAAG,CAAC,EAAE,CAAC;YAClC,MAAM,IAAI,GAAG,IAAI,CAAC,aAAa,CAAC,KAAK,EAAG,CAAA;YACxC,IAAI,CAAC,YAAY,GAAG,IAAI,CAAA;YAExB,kDAAkD;YAClD,IAAI,CAAC,cAAc,IAAI,CAAC,IAAI,CAAA;YAE5B,yCAAyC;YACzC,IAAI,IAAI,CAAC,aAAa,CAAC,MAAM,KAAK,CAAC,EAAE,CAAC;gBACpC,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;gBACpB,IAAI,CAAC,cAAc,IAAI,CAAC,IAAI,CAAA;YAC9B,CAAC;YAED,uCAAuC;YACvC,IAAI,CAAC,IAAI,CAAC,eAAe,GAAG,IAAI,CAAC,IAAI,IAAI,CAAC,aAAa,CAAC,MAAM,KAAK,CAAC,EAAE,CAAC;gBACrE,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;gBACpB,IAAI,CAAC,cAAc,IAAI,CAAC,IAAI,CAAA;YAC9B,CAAC;YAED,OAAO,IAAI,CAAA;QACb,CAAC;QAED,OAAO,IAAI,CAAC,YAAY,CAAA;IAC1B,CAAC;IAED;;OAEG;IACK,SAAS,CAAC,IAAY;QAC5B,IAAI,CAAC,cAAc,CAAC,IAAI,CAAC,IAAI,GAAG,IAAI,CAAC,CAAA;QAErC,0CAA0C;QAC1C,IAAI,CAAC,cAAc,IAAI,CAAC,IAAI,CAAA;IAC9B,CAAC;IAED;;OAEG;IACK,UAAU;QAChB,IAAI,MAAM,GAAG,CAAC,CAAA;QAEd,sBAAsB;QACtB,IAAI,IAAI,CAAC,WAAW;YAAE,MAAM,IAAI,IAAI,CAAA;QAEpC,uBAAuB;QACvB,IAAI,IAAI,CAAC,YAAY;YAAE,MAAM,IAAI,IAAI,CAAA;QAErC,iBAAiB;QACjB,IAAI,IAAI,CAAC,OAAO;YAAE,MAAM,IAAI,IAAI,CAAA;QAEhC,oCAAoC;QACpC,IAAI,IAAI,CAAC,aAAa,CAAC,MAAM,GAAG,CAAC;YAAE,MAAM,IAAI,IAAI,CAAA;QAEjD,sCAAsC;QACtC,IAAI,IAAI,CAAC,cAAc,CAAC,MAAM,KAAK,CAAC;YAAE,MAAM,IAAI,IAAI,CAAA;QAEpD,8DAA8D;QAC9D,MAAM,IAAI,CAAC,IAAI,CAAA;QAEf,mDAAmD;QACnD,MAAM,IAAI,IAAI,CAAA;QAEd,yBAAyB;QACzB,IAAI,IAAI,CAAC,OAAO;YAAE,MAAM,IAAI,IAAI,CAAA;QAEhC,IAAI,CAAC,cAAc,GAAG,MAAM,CAAA;QAC5B,OAAO,MAAM,CAAA;IACf,CAAC;IAED;;OAEG;IACK,YAAY,CAAC,IAAY;QAC/B,IAAI,CAAC,eAAe,GAAG,IAAI,GAAG,IAAI,CAAA;QAElC,wBAAwB;QACxB,iCAAiC;QAEjC,4BAA4B;QAC5B,MAAM,iBAAiB,GAAG,CAAC,IAAI,GAAG,IAAI,CAAC,KAAK,CAAC,CAAA;QAE7C,4CAA4C;QAC5C,6CAA6C;QAE7C,mBAAmB;QACnB,IAAI,CAAC,QAAQ,GAAG,CAAC,IAAI,GAAG,IAAI,CAAC,KAAK,CAAC,CAAA;QAEnC,2BAA2B;QAC3B,2CAA2C;QAE3C,qBAAqB;QACrB,IAAI,iBAAiB,IAAI,IAAI,CAAC,aAAa,CAAC,MAAM,GAAG,CAAC,EAAE,CAAC;YACvD,IAAI,CAAC,OAAO,GAAG,IAAI,CAAA;YACnB,IAAI,CAAC,cAAc,IAAI,IAAI,CAAA;YAC3B,IAAI,CAAC,QAAQ,EAAE,CAAA;QACjB,CAAC;aAAM,IAAI,CAAC,iBAAiB,EAAE,CAAC;YAC9B,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;YACpB,IAAI,CAAC,cAAc,IAAI,CAAC,IAAI,CAAA;QAC9B,CAAC;IACH,CAAC;IAED;;OAEG;IACK,YAAY,CAAC,IAAY;QAC/B,IAAI,CAAC,eAAe,GAAG,IAAI,GAAG,IAAI,CAAA;QAElC,sBAAsB;QACtB,MAAM,YAAY,GAAG,IAAI,GAAG,IAAI,CAAA;QAChC,IAAI,CAAC,QAAQ,GAAG,IAAI,CAAC,WAAW,CAAC,YAAY,CAAC,CAAA;QAE9C,mDAAmD;QACnD,MAAM,mBAAmB,GAAG,CAAC,IAAI,GAAG,IAAI,CAAC,KAAK,CAAC,CAAA;QAE/C,6CAA6C;QAC7C,MAAM,UAAU,GAAG,CAAC,CAAC,IAAI,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,GAAG,CAAC,CAAA;QAE3C,4BAA4B;QAC5B,MAAM,QAAQ,GAAG,CAAC,IAAI,GAAG,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAA;IACxC,CAAC;IAED;;OAEG;IACK,WAAW,CAAC,IAAY;QAC9B,MAAM,SAAS,GAAG;YAChB,MAAM,EAAK,8DAA8D;YACzE,EAAE,EAAO,OAAO;YAChB,EAAE,EAAO,OAAO;YAChB,GAAG,EAAM,OAAO;YAChB,GAAG,EAAM,OAAO;YAChB,GAAG,EAAM,OAAO;YAChB,GAAG,EAAM,OAAO;YAChB,GAAG,EAAM,OAAO;YAChB,IAAI,EAAK,OAAO;YAChB,IAAI,EAAK,OAAO;YAChB,IAAI,EAAK,OAAO;YAChB,IAAI,EAAK,OAAO;YAChB,IAAI,EAAK,OAAO;YAChB,IAAI,EAAK,OAAO;YAChB,IAAI,EAAK,OAAO;YAChB,KAAK,CAAI,OAAO;SACjB,CAAA;QACD,OAAO,SAAS,CAAC,IAAI,CAAC,IAAI,MAAM,CAAA;IAClC,CAAC;IAED;;OAEG;IACK,eAAe;QACrB,IAAI,CAAC,cAAc,GAAG,IAAI,CAAA,CAAE,+BAA+B;QAC3D,IAAI,CAAC,WAAW,GAAG,KAAK,CAAA;QACxB,IAAI,CAAC,YAAY,GAAG,KAAK,CAAA;QACzB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QACpB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;IACtB,CAAC;IAED;;OAEG;IACH,IAAI,CAAC,SAAiB;QACpB,IAAI,CAAC,YAAY,EAAE,CAAA;QAEnB,sEAAsE;QACtE,yDAAyD;QACzD,MAAM,aAAa,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC,SAAS,GAAG,IAAI,CAAC,QAAQ,CAAC,GAAG,EAAE,CAAC,CAAA;QAElE,kDAAkD;QAClD,IAAI,IAAI,CAAC,YAAY,IAAI,aAAa,IAAI,IAAI,CAAC,cAAc,CAAC,MAAM,GAAG,CAAC,EAAE,CAAC;YA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package/dist/components/IO/Attachments/Attachment.d.ts

@@ -0,0 +1,112 @@
+/**
+ * Interface for devices that can be attached to GPIO ports
+ */
+export interface Attachment {
+    /**
+     * Reset the attachment to its initial state
+     */
+    reset(): void;
+    /**
+     * Update the attachment state based on CPU clock ticks
+     * @param cpuFrequency - The CPU frequency in Hz
+     */
+    tick(cpuFrequency: number): void;
+    /**
+     * Read data from Port A
+     * @param ddr - Data Direction Register value
+     * @param or - Output Register value
+     * @returns The data to be read from the port
+     */
+    readPortA(ddr: number, or: number): number;
+    /**
+     * Read data from Port B
+     * @param ddr - Data Direction Register value
+     * @param or - Output Register value
+     * @returns The data to be read from the port
+     */
+    readPortB(ddr: number, or: number): number;
+    /**
+     * Write data to Port A
+     * @param value - The value being written
+     * @param ddr - Data Direction Register value
+     */
+    writePortA(value: number, ddr: number): void;
+    /**
+     * Write data to Port B
+     * @param value - The value being written
+     * @param ddr - Data Direction Register value
+     */
+    writePortB(value: number, ddr: number): void;
+    /**
+     * Check if the attachment is enabled
+     * @returns true if enabled, false otherwise
+     */
+    isEnabled(): boolean;
+    /**
+     * Get the priority of this attachment (lower values = higher priority)
+     * @returns The priority value
+     */
+    getPriority(): number;
+    /**
+     * Clear interrupt flags
+     * @param ca1 - Clear CA1 interrupt
+     * @param ca2 - Clear CA2 interrupt
+     * @param cb1 - Clear CB1 interrupt
+     * @param cb2 - Clear CB2 interrupt
+     */
+    clearInterrupts(ca1: boolean, ca2: boolean, cb1: boolean, cb2: boolean): void;
+    /**
+     * Update control line states
+     * @param ca1 - CA1 control line state
+     * @param ca2 - CA2 control line state
+     * @param cb1 - CB1 control line state
+     * @param cb2 - CB2 control line state
+     */
+    updateControlLines(ca1: boolean, ca2: boolean, cb1: boolean, cb2: boolean): void;
+    /**
+     * Check if CA1 interrupt is pending
+     * @returns true if interrupt is pending
+     */
+    hasCA1Interrupt(): boolean;
+    /**
+     * Check if CA2 interrupt is pending
+     * @returns true if interrupt is pending
+     */
+    hasCA2Interrupt(): boolean;
+    /**
+     * Check if CB1 interrupt is pending
+     * @returns true if interrupt is pending
+     */
+    hasCB1Interrupt(): boolean;
+    /**
+     * Check if CB2 interrupt is pending
+     * @returns true if interrupt is pending
+     */
+    hasCB2Interrupt(): boolean;
+}
+/**
+ * Base abstract class for GPIO attachments with common functionality
+ */
+export declare abstract class AttachmentBase implements Attachment {
+    protected priority: number;
+    protected enabled: boolean;
+    protected ca1Interrupt: boolean;
+    protected ca2Interrupt: boolean;
+    protected cb1Interrupt: boolean;
+    protected cb2Interrupt: boolean;
+    constructor(priority: number, ca1Interrupt?: boolean, ca2Interrupt?: boolean, cb1Interrupt?: boolean, cb2Interrupt?: boolean);
+    reset(): void;
+    tick(cpuFrequency: number): void;
+    readPortA(ddr: number, or: number): number;
+    readPortB(ddr: number, or: number): number;
+    writePortA(value: number, ddr: number): void;
+    writePortB(value: number, ddr: number): void;
+    isEnabled(): boolean;
+    getPriority(): number;
+    clearInterrupts(ca1: boolean, ca2: boolean, cb1: boolean, cb2: boolean): void;
+    updateControlLines(ca1: boolean, ca2: boolean, cb1: boolean, cb2: boolean): void;
+    hasCA1Interrupt(): boolean;
+    hasCA2Interrupt(): boolean;
+    hasCB1Interrupt(): boolean;
+    hasCB2Interrupt(): boolean;
+}