@zigc/lib 0.17.0-dev.356 → 0.17.0-dev.389

package/std/start.zig

@@ -169,6 +169,7 @@ fn _start() callconv(.naked) noreturn {
             .kvx => ".cfi_undefined r14",
             .loongarch32, .loongarch64 => ".cfi_undefined 1",
             .m68k => ".cfi_undefined %%pc",
+            .m88k => ".cfi_undefined %%r1",
             .microblaze, .microblazeel => ".cfi_undefined r15",
             .mips, .mipsel, .mips64, .mips64el => ".cfi_undefined $ra",
             .or1k => ".cfi_undefined r9",
@@ -331,6 +332,16 @@ fn _start() callconv(.naked) noreturn {
             \\ lea %[posixCallMainAndExit] - . - 8, %%a0
             \\ jsr (%%pc, %%a0)
             ,
+            .m88k =>
+            // r1 = LR, r30 = FP, r31 = SP
+            \\ or %%r0, %%r0, %%r0
+            \\ or %%r0, %%r0, %%r0
+            \\ or %%30, %%r0, %%r0
+            \\ or %%r1, %%r0, %%r0
+            \\ or %%r2, %%r31, %%r0
+            \\ clr %%r31, %%r31, 4<0>
+            \\ br.n %[posixCallMainAndExit]
+            ,
             .microblaze, .microblazeel =>
             // r1 = SP, r15 = LR, r19 = FP, r20 = GP
             \\ ori r15, r0, r0

package/std/zig/LibCDirs.zig

@@ -288,6 +288,7 @@ fn libCGenericName(target: *const std.Target) [:0]const u8 {
         .msvc,
         .itanium,
         .simulator,
+        .call0,
         => unreachable,
     }
 }

package/std/zig/system/linux.zig

@@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct {
     model: ?*const Target.Cpu.Model = null,
 
     const cpu_names = .{
+        .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
+        .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
+        .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
         .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
+        .{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 },
     };
 
     fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {

package/std/zig/system/loongarch.zig

@@ -31,21 +31,37 @@ pub fn detectNativeCpuAndFeatures(
 
     cpu.features.addFeatureSet(cpu.model.features);
 
-    const cfg1 = cpucfg(1);
     const cfg2 = cpucfg(2);
     const cfg3 = cpucfg(3);
 
-    setFeature(&cpu, .ual, bit(cfg1, 20));
+    if (builtin.os.tag == .linux) {
+        const HWCAP = std.os.linux.HWCAP;
+        const hwcap_bits: usize = if (builtin.link_libc)
+            std.c.getauxval(std.elf.AT_HWCAP)
+        else
+            std.os.linux.getauxval(std.elf.AT_HWCAP);
 
-    const has_fpu = bit(cfg2, 0);
-    setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
-    setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
+        setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0);
 
-    setFeature(&cpu, .lsx, bit(cfg2, 6));
-    setFeature(&cpu, .lasx, bit(cfg2, 7));
-    setFeature(&cpu, .lvz, bit(cfg2, 10));
+        const has_fpu = (hwcap_bits & HWCAP.FPU) != 0;
+        setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
+        setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
+        setFeature(&cpu, .lsx, (hwcap_bits & HWCAP.LSX) != 0);
+        setFeature(&cpu, .lasx, (hwcap_bits & HWCAP.LASX) != 0);
 
-    setFeature(&cpu, .lbt, bit(cfg2, 18) and bit(cfg2, 19) and bit(cfg2, 20));
+        setFeature(&cpu, .lvz, (hwcap_bits & HWCAP.LVZ) != 0);
+        setFeature(&cpu, .lbt, (hwcap_bits & HWCAP.LBT_X86) != 0 and (hwcap_bits & HWCAP.LBT_ARM) != 0 and (hwcap_bits & HWCAP.LBT_MIPS) != 0);
+    } else {
+        setFeature(&cpu, .ual, false);
+
+        setFeature(&cpu, .f, false);
+        setFeature(&cpu, .d, false);
+        setFeature(&cpu, .lsx, false);
+        setFeature(&cpu, .lasx, false);
+
+        setFeature(&cpu, .lvz, false);
+        setFeature(&cpu, .lbt, false);
+    }
 
     setFeature(&cpu, .frecipe, bit(cfg2, 25));
     setFeature(&cpu, .div32, bit(cfg2, 26));

package/std/zig/system.zig

@@ -460,6 +460,10 @@ pub fn resolveTargetQuery(io: Io, query: Target.Query) DetectError!Target {
         if (result.cpu.arch.isArm() and result.abi.float() == .soft) {
             result.cpu.features.removeFeature(@intFromEnum(Target.arm.Feature.vfp2));
         }
+
+        if (result.cpu.arch.isXtensa() and result.abi == .call0) {
+            result.cpu.features.removeFeature(@intFromEnum(Target.xtensa.Feature.windowed));
+        }
     }
 
     // It's possible that we detect the native ABI, but fail to detect the OS version or were told

package/zig.h

@@ -21,6 +21,8 @@
 
 #if defined(__aarch64__) || (defined(zig_msvc) && defined(_M_ARM64))
 #define zig_aarch64
+#elif defined(__alpha__)
+#define zig_alpha
 #elif defined(__thumb__) || (defined(zig_msvc) && defined(_M_ARM))
 #define zig_thumb
 #define zig_arm
@@ -36,6 +38,10 @@
 #elif defined(__loongarch64)
 #define zig_loongarch64
 #define zig_loongarch
+#elif defined(__m68k__)
+#define zig_m68k
+#elif defined(__m88k__)
+#define zig_m88k
 #elif defined(__mips64)
 #define zig_mips64
 #define zig_mips
@@ -79,6 +85,8 @@
 #elif defined(__I86__)
 #define zig_x86_16
 #define zig_x86
+#elif defined(__xtensa__)
+#define zig_xtensa
 #elif defined (__ez80)
 #define zig_ez80
 #define zig_z80
@@ -390,7 +398,9 @@
 
 #elif defined(zig_gnuc_asm)
 
-#if defined(zig_thumb)
+#if defined(zig_alpha)
+#define zig_trap() __asm__ volatile("call_pal 0x000000")
+#elif defined(zig_thumb)
 #define zig_trap() __asm__ volatile("udf #0xfe")
 #elif defined(zig_arm) || defined(zig_aarch64)
 #define zig_trap() __asm__ volatile("udf #0xfdee")
@@ -398,6 +408,10 @@
 #define zig_trap() __asm__ volatile("r27:26 = memd(#0xbadc0fee)")
 #elif defined(zig_kvx) || defined(zig_loongarch) || defined(zig_powerpc)
 #define zig_trap() __asm__ volatile(".word 0x0")
+#elif defined(zig_m68k)
+#define zig_trap() __asm__ volatile("illegal")
+#elif defined(zig_m88k)
+#define zig_trap() __asm__ volatile("tb0 0, %%r0, 511")
 #elif defined(zig_mips)
 #define zig_trap() __asm__ volatile(".word 0x3d")
 #elif defined(zig_or1k)
@@ -412,6 +426,8 @@
 #define zig_trap() __asm__ volatile("int $0x3")
 #elif defined(zig_x86)
 #define zig_trap() __asm__ volatile("ud2")
+#elif defined(zig_xtensa)
+#define zig_trap() __asm__ volatile("ill")
 #elif defined(zig_z80)
 #define zig_trap() __asm__ volatile("rst 00h")
 #else
@@ -428,7 +444,9 @@
 #define zig_breakpoint() __debugbreak()
 #elif defined(zig_gnuc_asm)
 
-#if defined(zig_arm)
+#if defined(zig_alpha)
+#define zig_breakpoint() __asm__ volatile("call_pal 0x000080")
+#elif defined(zig_arm)
 #define zig_breakpoint() __asm__ volatile("bkpt #0x0")
 #elif defined(zig_aarch64)
 #define zig_breakpoint() __asm__ volatile("brk #0xf000")
@@ -436,6 +454,8 @@
 #define zig_breakpoint() __asm__ volatile("brkpt")
 #elif defined(zig_kvx) || defined(zig_loongarch)
 #define zig_breakpoint() __asm__ volatile("break 0x0")
+#elif defined(zig_m88k)
+#define zig_breakpoint() __asm__ volatile("illop1")
 #elif defined(zig_mips)
 #define zig_breakpoint() __asm__ volatile("break")
 #elif defined(zig_or1k)
@@ -450,6 +470,8 @@
 #define zig_breakpoint() __asm__ volatile("ta 0x1")
 #elif defined(zig_x86)
 #define zig_breakpoint() __asm__ volatile("int $0x3")
+#elif defined(zig_xtensa)
+#define zig_breakpoint() __asm__ volatile("break 1, 1")
 #else
 #define zig_breakpoint() zig_breakpoint_unavailable
 #endif