@zigc/lib 0.17.0-dev.356 → 0.17.0-dev.387

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@zigc/lib",
-  "version": "0.17.0-dev.356",
+  "version": "0.17.0-dev.387",
   "description": "Zig standard library and libc headers (shared across all platforms)",
   "repository": {
     "type": "git",

package/std/Target/riscv.zig

@@ -3370,6 +3370,103 @@ pub const cpu = struct {
             .zvl1024b,
         }),
     };
+    pub const spacemit_a100: CpuModel = .{
+        .name = "spacemit_a100",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .a,
+            .b,
+            .c,
+            .dlen_factor_2,
+            .i,
+            .m,
+            .optimized_nf2_segment_load_store,
+            .optimized_nf3_segment_load_store,
+            .optimized_nf4_segment_load_store,
+            .smepmp,
+            .smnpm,
+            .smstateen,
+            .ssccptr,
+            .sscofpmf,
+            .sscounterenw,
+            .ssnpm,
+            .sspm,
+            .sstc,
+            .sstvala,
+            .sstvecd,
+            .ssu64xl,
+            .supm,
+            .svade,
+            .svbare,
+            .svinval,
+            .svnapot,
+            .svpbmt,
+            .unaligned_scalar_mem,
+            .v,
+            .vxrm_pipeline_flush,
+            .za64rs,
+            .zawrs,
+            .zbc,
+            .zbkc,
+            .zcb,
+            .zcmop,
+            .zfa,
+            .zfh,
+            .zic64b,
+            .zicbom,
+            .zicbop,
+            .zicboz,
+            .ziccamoa,
+            .ziccif,
+            .zicclsm,
+            .ziccrse,
+            .zicntr,
+            .zicond,
+            .zifencei,
+            .zihintntl,
+            .zihintpause,
+            .zihpm,
+            .zimop,
+            .zkt,
+            .zvbb,
+            .zvfbfwma,
+            .zvfh,
+            .zvkng,
+            .zvknha,
+            .zvksc,
+            .zvksg,
+            .zvl1024b,
+        }),
+    };
+    pub const spacemit_x100: CpuModel = .{
+        .name = "spacemit_x100",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .dlen_factor_2,
+            .optimized_nf2_segment_load_store,
+            .optimized_nf3_segment_load_store,
+            .optimized_nf4_segment_load_store,
+            .rva23s64,
+            .smepmp,
+            .smnpm,
+            .smstateen,
+            .sspm,
+            .unaligned_scalar_mem,
+            .vxrm_pipeline_flush,
+            .xsmtvdot,
+            .zbc,
+            .zbkc,
+            .zfh,
+            .zvfbfwma,
+            .zvfh,
+            .zvkng,
+            .zvknha,
+            .zvksc,
+            .zvksg,
+            .zvl256b,
+        }),
+    };
     pub const spacemit_x60: CpuModel = .{
         .name = "spacemit_x60",
         .llvm_name = "spacemit-x60",

package/std/Target.zig

@@ -250,10 +250,12 @@ pub const Os = struct {
         win11_ga = 0x0A00000F, //aka win11_22h2
         win11_ge = 0x0A000010, //aka win11_23h2
         win11_dt = 0x0A000011, //aka win11_24h2
+        win11_br = 0x0A000012, //aka win11_25h2
+        win11_kr = 0x0A000013, //aka win11_26h1
         _,
 
         /// Latest Windows version that the Zig Standard Library is aware of
-        pub const latest = WindowsVersion.win11_dt;
+        pub const latest = WindowsVersion.win11_kr;
 
         /// Compared against build numbers reported by the runtime to distinguish win10 versions,
         /// where 0x0A000000 + index corresponds to the WindowsVersion u32 value.
@@ -276,6 +278,8 @@ pub const Os = struct {
             22621, //win11_ga aka win11_22h2
             22631, //win11_ge aka win11_23h2
             26100, //win11_dt aka win11_24h2
+            26200, //win11_br aka win11_25h2
+            28000, //win11_kr aka win11_26h1
         };
 
         /// Returns whether the first version `ver` is newer (greater) than or equal to the second version `ver`.
@@ -751,6 +755,7 @@ pub const kvx = @import("Target/kvx.zig");
 pub const lanai = @import("Target/lanai.zig");
 pub const loongarch = @import("Target/loongarch.zig");
 pub const m68k = @import("Target/m68k.zig");
+pub const m88k = @import("Target/generic.zig");
 pub const microblaze = @import("Target/generic.zig");
 pub const mips = @import("Target/mips.zig");
 pub const msp430 = @import("Target/msp430.zig");
@@ -798,6 +803,7 @@ pub const Abi = enum {
     simulator,
     ohos,
     ohoseabi,
+    call0,
 
     // LLVM tags deliberately omitted:
     // - amplification
@@ -1091,6 +1097,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
         .kvx => .KVX,
         .lanai => .LANAI,
         .loongarch32, .loongarch64 => .LOONGARCH,
+        .m88k => .@"88K",
         .m68k => .@"68K",
         .microblaze, .microblazeel => .MICROBLAZE,
         .mips, .mips64, .mipsel, .mips64el => .MIPS,
@@ -1154,6 +1161,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
         .kalimba,
         .kvx,
         .lanai,
+        .m88k,
         .m68k,
         .microblaze,
         .microblazeel,
@@ -1364,6 +1372,7 @@ pub const Cpu = struct {
         loongarch32,
         loongarch64,
         m68k,
+        m88k,
         microblaze,
         microblazeel,
         mips,
@@ -1439,6 +1448,7 @@ pub const Cpu = struct {
             lanai,
             loongarch,
             m68k,
+            m88k,
             microblaze,
             mips,
             msp430,
@@ -1477,6 +1487,7 @@ pub const Cpu = struct {
                 .lanai => .lanai,
                 .loongarch32, .loongarch64 => .loongarch,
                 .m68k => .m68k,
+                .m88k => .m88k,
                 .microblaze, .microblazeel => .microblaze,
                 .mips, .mipsel, .mips64, .mips64el => .mips,
                 .msp430 => .msp430,
@@ -1710,6 +1721,7 @@ pub const Cpu = struct {
                 .hppa64,
                 .lanai,
                 .m68k,
+                .m88k,
                 .microblaze,
                 .mips,
                 .mips64,
@@ -1922,6 +1934,9 @@ pub const Cpu = struct {
                 .m68k_interrupt,
                 => &.{.m68k},
 
+                .m88k_sysv,
+                => &.{.m88k},
+
                 .microblaze_std,
                 .microblaze_interrupt,
                 => &.{ .microblaze, .microblazeel },
@@ -2554,6 +2569,7 @@ pub const DynamicLinker = struct {
                     .m68k,
                     .microblaze,
                     .microblazeel,
+                    .or1k,
                     .powerpc64,
                     .powerpc64le,
                     .s390x,
@@ -2631,8 +2647,6 @@ pub const DynamicLinker = struct {
 
                     .arm,
                     .armeb,
-                    .thumb,
-                    .thumbeb,
                     => initFmt("/lib/ld-linux{s}.so.3", .{switch (abi) {
                         .gnueabi => "",
                         .gnueabihf => "-armhf",
@@ -2641,6 +2655,7 @@ pub const DynamicLinker = struct {
 
                     .aarch64,
                     .aarch64_be,
+                    .or1k,
                     => |arch| if (abi == .gnu) initFmt("/lib/ld-linux-{s}.so.1", .{@tagName(arch)}) else none,
 
                     // TODO: `-be` architecture support.
@@ -2803,6 +2818,7 @@ pub const DynamicLinker = struct {
                 .arm,
                 .aarch64,
                 .hppa,
+                .m88k,
                 .mips64,
                 .mips64el,
                 .powerpc,
@@ -2910,6 +2926,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
         .lanai,
         .loongarch32,
         .m68k,
+        .m88k,
         .microblaze,
         .microblazeel,
         .mips,
@@ -3495,6 +3512,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
             .hppa,
             .lanai,
             .m68k,
+            .m88k,
             .mips,
             .mipsel,
             .nvptx,
@@ -3604,6 +3622,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
             .hppa,
             .lanai,
             .m68k,
+            .m88k,
             .mips,
             .mipsel,
             .nvptx,
@@ -3675,6 +3694,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
         .lanai,
         .loongarch32,
         .m68k,
+        .m88k,
         .mips,
         .mipsel,
         .powerpc,
@@ -3723,7 +3743,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .x86_64 => switch (target.os.tag) {
             .windows, .uefi => .{ .x86_64_win = .{} },
             else => switch (target.abi) {
-                .gnuabin32, .muslabin32 => .{ .x86_64_x32 = .{} },
+                .gnux32, .muslx32 => .{ .x86_64_x32 = .{} },
                 else => .{ .x86_64_sysv = .{} },
             },
         },
@@ -3752,7 +3772,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .riscv32, .riscv32be => .{ .riscv32_ilp32 = .{} },
         .sparc64 => .{ .sparc64_sysv = .{} },
         .sparc => .{ .sparc_sysv = .{} },
-        .powerpc64 => if (target.abi.isGnu())
+        .powerpc64 => if (target.os.tag == .ps3 or target.abi.isGnu())
             .{ .powerpc64_elf = .{} }
         else
             .{ .powerpc64_elf_v2 = .{} },
@@ -3774,10 +3794,8 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .lanai => .{ .lanai_sysv = .{} },
         .loongarch64 => .{ .loongarch64_lp64 = .{} },
         .loongarch32 => .{ .loongarch32_ilp32 = .{} },
-        .m68k => if (target.abi.isGnu() or target.abi.isMusl())
-            .{ .m68k_gnu = .{} }
-        else
-            .{ .m68k_sysv = .{} },
+        .m68k => .{ .m68k_gnu = .{} },
+        .m88k => .{ .m88k_sysv = .{} },
         .microblaze, .microblazeel => .{ .microblaze_std = .{} },
         .msp430 => .{ .msp430_eabi = .{} },
         .or1k => .{ .or1k_sysv = .{} },

package/std/Thread.zig

@@ -1217,8 +1217,8 @@ const LinuxThreadImpl = struct {
                     \\ ldi $16, 0
                     \\ callsys
                     :
-                    : [ptr] "{r16}" (@intFromPtr(self.mapped.ptr)),
-                      [len] "{r17}" (self.mapped.len),
+                    : [ptr] "{$16}" (@intFromPtr(self.mapped.ptr)),
+                      [len] "{$17}" (self.mapped.len),
                 ),
                 .hexagon => asm volatile (
                     \\  r6 = #215 // SYS_munmap

package/std/array_list.zig

@@ -1152,14 +1152,14 @@ pub fn Aligned(comptime T: type, comptime alignment: ?mem.Alignment) type {
 
         /// Shrinks capacity to match length.
         /// May invalidate element pointers.
-        /// If succeds it is safe to call toOwnedSliceAssert().
+        /// If succeds it is safe to call `toOwnedSliceAssert`.
         pub fn shrinkToLen(self: *Self, gpa: Allocator) Allocator.Error!void {
             try self.shrinkAndFreePrecise(gpa, self.items.len);
         }
 
         /// Shrinks or expands capacity to match length + 1.
         /// May invalidate element pointers.
-        /// If succeds it is safe to call toOwnedSliceSentinelAssert().
+        /// If succeds it is safe to call `toOwnedSliceSentinelAssert`.
         pub fn shrinkToLenSentinel(self: *Self, gpa: Allocator) Allocator.Error!void {
             std.debug.assert(self.items.len <= self.capacity);
             const required_len = self.items.len + 1;

package/std/atomic.zig

@@ -442,10 +442,12 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
         // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
         // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/microblaze/include/asm/cache.h#L15
         // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sh/include/cpu-sh4/cpu/cache.h#L10
+        // - https://github.com/openbsd/src/blob/1957873d2063db11dab780eca75b5e629d1e838d/sys/arch/m88k/m88k/atomic.S#L22
         .arm,
         .armeb,
         .thumb,
         .thumbeb,
+        .m88k,
         .microblaze,
         .microblazeel,
         .mips,

package/std/debug/Dwarf.zig

@@ -1436,6 +1436,7 @@ pub fn compactUnwindToDwarfRegNumber(unwind_reg_number: u3) !u16 {
 pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
     return switch (arch) {
         .aarch64, .aarch64_be => 32,
+        .alpha => 64,
         .arc, .arceb => 160,
         .arm, .armeb, .thumb, .thumbeb => 15,
         .csky => 64,
@@ -1444,6 +1445,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
         .lanai => 2,
         .loongarch32, .loongarch64 => 64,
         .m68k => 26,
+        .m88k => 64,
         .mips, .mipsel, .mips64, .mips64el => 66,
         .or1k => 35,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
@@ -1460,6 +1462,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
 pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
     return switch (arch) {
         .aarch64, .aarch64_be => 29,
+        .alpha => 15,
         .arc, .arceb => 27,
         .arm, .armeb, .thumb, .thumbeb => 11,
         .csky => 14,
@@ -1468,6 +1471,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
         .lanai => 5,
         .loongarch32, .loongarch64 => 22,
         .m68k => 14,
+        .m88k => 30,
         .mips, .mipsel, .mips64, .mips64el => 30,
         .or1k => 2,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
@@ -1484,6 +1488,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
 pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
     return switch (arch) {
         .aarch64, .aarch64_be => 31,
+        .alpha => 30,
         .arc, .arceb => 28,
         .arm, .armeb, .thumb, .thumbeb => 13,
         .csky => 14,
@@ -1492,6 +1497,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
         .lanai => 4,
         .loongarch32, .loongarch64 => 3,
         .m68k => 15,
+        .m88k => 31,
         .mips, .mipsel, .mips64, .mips64el => 29,
         .or1k => 1,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,

package/std/debug/SelfInfo/Elf.zig

@@ -161,6 +161,7 @@ pub const can_unwind: bool = s: {
         // Not supported yet: arm
         .openbsd => &.{
             .aarch64,
+            .m88k,
             .mips64,
             .mips64el,
             .riscv64,

package/std/debug/cpu_context.zig

@@ -5,6 +5,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont
     root.debug.CpuContext
 else switch (native_arch) {
     .aarch64, .aarch64_be => Aarch64,
+    .alpha => Alpha,
     .arc, .arceb => Arc,
     .arm, .armeb, .thumb, .thumbeb => Arm,
     .csky => Csky,
@@ -13,6 +14,7 @@ else switch (native_arch) {
     .lanai => Lanai,
     .loongarch32, .loongarch64 => LoongArch,
     .m68k => M68k,
+    .m88k => M88k,
     .mips, .mipsel, .mips64, .mips64el => Mips,
     .or1k => Or1k,
     .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
@@ -61,6 +63,13 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
             },
             .pc = @truncate(uc.mcontext.pc),
         };
+    } else if (native_arch == .m88k and native_os == .openbsd) {
+        // OpenBSD makes no effort to clear the V and E bits of the SXIP register when presenting it
+        // to user space, so we need to do that here.
+        return .{
+            .r = uc.mcontext.r,
+            .xip = uc.mcontext.xip & ~@as(u32, 0b11),
+        };
     } else if (native_arch.isMIPS32() and native_os == .linux) {
         // The O32 kABI uses 64-bit fields for some reason.
         return .{
@@ -103,6 +112,10 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
             .sp = uc.mcontext.sp,
             .pc = uc.mcontext.pc,
         },
+        .alpha => .{
+            .r = uc.mcontext.r,
+            .pc = uc.mcontext.pc,
+        },
         .csky => .{
             .r = uc.mcontext.r0_13 ++
                 [_]u32{ uc.mcontext.r14, uc.mcontext.r15 } ++
@@ -293,6 +306,75 @@ const Aarch64 = extern struct {
     }
 };
 
+const Alpha = extern struct {
+    /// The numbered general-purpose registers R0 - R31.
+    r: [32]u64,
+    pc: u64,
+
+    pub inline fn current() Alpha {
+        var ctx: Alpha = undefined;
+        asm volatile (
+            \\ stq $0 , 0x000($0)
+            \\ stq $1 , 0x008($0)
+            \\ stq $2 , 0x010($0)
+            \\ stq $3 , 0x018($0)
+            \\ stq $4 , 0x020($0)
+            \\ stq $5 , 0x028($0)
+            \\ stq $6 , 0x030($0)
+            \\ stq $7 , 0x038($0)
+            \\ stq $8 , 0x040($0)
+            \\ stq $9 , 0x048($0)
+            \\ stq $10, 0x050($0)
+            \\ stq $11, 0x058($0)
+            \\ stq $12, 0x060($0)
+            \\ stq $13, 0x068($0)
+            \\ stq $14, 0x070($0)
+            \\ stq $15, 0x078($0)
+            \\ stq $16, 0x080($0)
+            \\ stq $17, 0x088($0)
+            \\ stq $18, 0x090($0)
+            \\ stq $19, 0x098($0)
+            \\ stq $20, 0x0a0($0)
+            \\ stq $21, 0x0a8($0)
+            \\ stq $22, 0x0b0($0)
+            \\ stq $23, 0x0b8($0)
+            \\ stq $24, 0x0c0($0)
+            \\ stq $25, 0x0c8($0)
+            \\ stq $26, 0x0d0($0)
+            \\ stq $27, 0x0d8($0)
+            \\ stq $28, 0x0e0($0)
+            \\ stq $29, 0x0e8($0)
+            \\ stq $30, 0x0f0($0)
+            \\
+            \\ br $1, 1f
+            \\1:
+            \\ stq $1, 0x100($0)
+            :
+            : [ctx] "{r0}" (&ctx),
+            : .{ .r1 = true, .memory = true });
+        return ctx;
+    }
+
+    pub fn getFp(ctx: *const Alpha) u64 {
+        return ctx.r[15];
+    }
+    pub fn getPc(ctx: *const Alpha) u64 {
+        return ctx.pc;
+    }
+
+    pub fn dwarfRegisterBytes(ctx: *Aarch64, register_num: u16) DwarfRegisterError![]u8 {
+        switch (register_num) {
+            0...31 => return @ptrCast(&ctx.r[register_num]),
+            64 => return @ptrCast(&ctx.pc),
+
+            32...63 => return error.UnsupportedRegister, // f0 - f31
+            66 => return error.UnsupportedRegister, // uniq
+
+            else => return error.InvalidRegister,
+        }
+    }
+};
+
 /// This is an `extern struct` so that inline assembly in `current` can use field offsets.
 const Arc = extern struct {
     /// The numbered general-purpose registers r0 - r31.
@@ -820,6 +902,75 @@ const M68k = extern struct {
     }
 };
 
+/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
+const M88k = extern struct {
+    /// The numbered general-purpose registers r0 - r31.
+    r: [32]u32,
+    xip: u32,
+
+    pub inline fn current() M88k {
+        var ctx: M88k = undefined;
+        asm volatile (
+            \\ st %%r0, %%r2, 0
+            \\ st %%r1, %%r2, 4
+            \\ st %%r2, %%r2, 8
+            \\ st %%r3, %%r2, 12
+            \\ st %%r4, %%r2, 16
+            \\ st %%r5, %%r2, 20
+            \\ st %%r6, %%r2, 24
+            \\ st %%r7, %%r2, 28
+            \\ st %%r8, %%r2, 32
+            \\ st %%r9, %%r2, 36
+            \\ st %%r10, %%r2, 40
+            \\ st %%r11, %%r2, 44
+            \\ st %%r12, %%r2, 48
+            \\ st %%r13, %%r2, 52
+            \\ st %%r14, %%r2, 56
+            \\ st %%r15, %%r2, 60
+            \\ st %%r16, %%r2, 64
+            \\ st %%r17, %%r2, 68
+            \\ st %%r18, %%r2, 72
+            \\ st %%r19, %%r2, 76
+            \\ st %%r20, %%r2, 80
+            \\ st %%r21, %%r2, 84
+            \\ st %%r22, %%r2, 88
+            \\ st %%r23, %%r2, 92
+            \\ st %%r24, %%r2, 96
+            \\ st %%r25, %%r2, 100
+            \\ st %%r26, %%r2, 104
+            \\ st %%r27, %%r2, 108
+            \\ st %%r28, %%r2, 112
+            \\ st %%r29, %%r2, 116
+            \\ st %%r30, %%r2, 120
+            \\ st %%r31, %%r2, 124
+            \\ bsr.n 1f
+            \\1:
+            \\ st %%r1, %%r2, 128
+            :
+            : [ctx] "{r2}" (&ctx),
+            : .{ .r1 = true, .memory = true });
+        return ctx;
+    }
+
+    pub fn getFp(ctx: *const M88k) u32 {
+        return ctx.r[30];
+    }
+    pub fn getPc(ctx: *const M88k) u32 {
+        return ctx.xip;
+    }
+
+    pub fn dwarfRegisterBytes(ctx: *M88k, register_num: u16) DwarfRegisterError![]u8 {
+        switch (register_num) {
+            0...31 => return @ptrCast(&ctx.r[register_num]),
+            64 => return @ptrCast(&ctx.xip),
+
+            32...63 => return error.UnsupportedRegister, // x0 - x31
+
+            else => return error.InvalidRegister,
+        }
+    }
+};
+
 /// This is an `extern struct` so that inline assembly in `current` can use field offsets.
 const Mips = extern struct {
     /// The numbered general-purpose registers r0 - r31. r0 must be zero.
@@ -2256,9 +2407,11 @@ const signal_ucontext_t = switch (native_os) {
         .alpha => extern struct {
             _cookie: i64,
             _mask: i64,
-            pc: u64,
-            _ps: i64,
-            r: [32]u64,
+            mcontext: extern struct {
+                pc: u64,
+                _ps: i64,
+                r: [32]u64,
+            },
         },
         // https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/arm/include/signal.h
         .arm => extern struct {
@@ -2287,6 +2440,18 @@ const signal_ucontext_t = switch (native_os) {
             r23_29: [7]u32,
             r31: u32,
         },
+        // https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/m88k/include/signal.h
+        .m88k => extern struct {
+            _cookie: i32,
+            _mask: i32,
+            mcontext: extern struct {
+                r: [32]u32,
+                _epsr: u32,
+                _fpsr: u32,
+                _fpcr: u32,
+                xip: u32,
+            },
+        },
         // https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/mips64/include/signal.h
         .mips64, .mips64el => extern struct {
             _cookie: i64,

package/std/debug.zig

@@ -495,7 +495,7 @@ pub fn defaultPanic(msg: []const u8, first_trace_addr: ?usize) noreturn {
     if (use_trap_panic) @trap();
 
     switch (builtin.os.tag) {
-        .freestanding, .other, .@"3ds", .vita => {
+        .freestanding, .other, .@"3ds", .psp, .vita => {
             @trap();
         },
         .uefi => {

package/std/heap.zig

@@ -608,6 +608,7 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
         .hppa => 4 << 10,
         .x86, .x86_64 => 4 << 10,
         .thumb, .thumbeb, .arm, .armeb, .aarch64, .aarch64_be => 4 << 10,
+        .m88k => 4 << 10,
         .mips64, .mips64el => 4 << 10,
         .powerpc, .powerpc64, .powerpc64le, .powerpcle => 4 << 10,
         .riscv64 => 4 << 10,
@@ -771,6 +772,7 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
         .hppa => 4 << 10,
         .x86, .x86_64 => 4 << 10,
         .thumb, .thumbeb, .arm, .armeb, .aarch64, .aarch64_be => 4 << 10,
+        .m88k => 4 << 10,
         .mips64, .mips64el => 16 << 10,
         .powerpc, .powerpc64, .powerpc64le, .powerpcle => 4 << 10,
         .riscv64 => 4 << 10,