@zigc/lib 0.17.0-dev.135 → 0.17.0-dev.224

package/std/Target.zig

@@ -845,6 +845,12 @@ pub const Abi = enum {
                 => .eabi,
                 else => .none,
             },
+            .fuchsia => switch (arch) {
+                .arm,
+                .thumb,
+                => .eabihf,
+                else => .none,
+            },
             .haiku => switch (arch) {
                 .arm,
                 .powerpc,
@@ -928,7 +934,6 @@ pub const Abi = enum {
             .wasi, .emscripten => .musl,
 
             .contiki,
-            .fuchsia,
             .hermit,
             .illumos,
             .managarm,
@@ -1014,6 +1019,7 @@ pub const Abi = enum {
             .gnueabi,
             .musleabi,
             .gnusf,
+            .muslsf,
             .ohoseabi,
             => .soft,
             else => .hard,
@@ -1219,7 +1225,7 @@ pub const Cpu = struct {
         pub const Set = struct {
             ints: [usize_count]usize,
 
-            pub const needed_bit_count = 317;
+            pub const needed_bit_count = 347;
             pub const byte_count = (needed_bit_count + 7) / 8;
             pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);
             pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));
@@ -2055,6 +2061,7 @@ pub const Cpu = struct {
                 .hppa => &hppa.cpu.pa_7300lc,
                 .kvx => &kvx.cpu.coolidge_v2,
                 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
+                .loongarch32 => &loongarch.cpu.la32v1_0,
                 .loongarch64 => &loongarch.cpu.la64v1_0,
                 .m68k => &m68k.cpu.M68000,
                 .mips => &mips.cpu.mips32r2,
@@ -2442,8 +2449,10 @@ pub const DynamicLinker = struct {
     pub fn standard(cpu: Cpu, os: Os, abi: Abi) DynamicLinker {
         return switch (os.tag) {
             .fuchsia => switch (cpu.arch) {
+                .arm,
                 .aarch64,
                 .riscv64,
+                .thumb,
                 .x86_64,
                 => init("ld.so.1"), // Fuchsia is unusual in that `DT_INTERP` is just a basename.
                 else => none,
@@ -2673,9 +2682,8 @@ pub const DynamicLinker = struct {
                         else => none,
                     },
 
-                    .powerpc64,
-                    .powerpc64le,
-                    => if (abi == .gnu) init("/lib64/ld64.so.2") else none,
+                    .powerpc64 => if (abi == .gnu) init("/lib64/ld64.so.1") else none,
+                    .powerpc64le => if (abi == .gnu) init("/lib64/ld64.so.2") else none,
 
                     .riscv32,
                     .riscv64,
@@ -3732,10 +3740,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .riscv32, .riscv32be => .{ .riscv32_ilp32 = .{} },
         .sparc64 => .{ .sparc64_sysv = .{} },
         .sparc => .{ .sparc_sysv = .{} },
-        .powerpc64 => if (target.abi.isMusl())
-            .{ .powerpc64_elf_v2 = .{} }
+        .powerpc64 => if (target.abi.isGnu())
+            .{ .powerpc64_elf = .{} }
         else
-            .{ .powerpc64_elf = .{} },
+            .{ .powerpc64_elf_v2 = .{} },
         .powerpc64le => .{ .powerpc64_elf_v2 = .{} },
         .powerpc, .powerpcle => .{ .powerpc_sysv = .{} },
         .wasm32, .wasm64 => .{ .wasm_mvp = .{} },

package/std/c.zig

@@ -11166,6 +11166,13 @@ pub extern "c" fn atoi(str: [*:0]const c_char) c_int;
 pub extern "c" fn atol(str: [*:0]const c_char) c_long;
 pub extern "c" fn atoll(str: [*:0]const c_char) c_longlong;
 
+pub extern "c" fn strtol(noalias str: [*:0]const c_char, noalias str_end: ?*[*:0]c_char, base: c_int) callconv(.c) c_long;
+pub extern "c" fn strtoll(noalias str: [*:0]const c_char, noalias str_end: ?*[*:0]c_char, base: c_int) callconv(.c) c_longlong;
+pub extern "c" fn strtoul(noalias str: [*:0]const c_char, noalias str_end: ?*[*:0]c_char, base: c_int) callconv(.c) c_ulong;
+pub extern "c" fn strtoull(noalias str: [*:0]const c_char, noalias str_end: ?*[*:0]c_char, base: c_int) callconv(.c) c_ulonglong;
+pub extern "c" fn strtoimax(noalias str: [*:0]const c_char, noalias str_end: ?*[*:0]c_char, base: c_int) callconv(.c) intmax_t;
+pub extern "c" fn strtoumax(noalias str: [*:0]const c_char, noalias str_end: ?*[*:0]c_char, base: c_int) callconv(.c) uintmax_t;
+
 pub extern "c" fn bsearch(
     key: *const anyopaque,
     base: *const anyopaque,

package/std/crypto/ml_kem.zig

@@ -1456,8 +1456,6 @@ fn randPolyNormalized(rnd: anytype) Poly {
 }
 
 test "MulHat" {
-    if (comptime builtin.cpu.has(.s390x, .vector)) return error.SkipZigTest;
-
     var rnd = RndGen.init(0);
 
     for (0..100) |_| {
@@ -1612,8 +1610,6 @@ test "Polynomial packing" {
 }
 
 test "Test inner PKE" {
-    if (comptime builtin.cpu.has(.s390x, .vector)) return error.SkipZigTest;
-
     var seed: [32]u8 = undefined;
     var pt: [32]u8 = undefined;
     for (&seed, &pt, 0..) |*s, *p, i| {
@@ -1635,8 +1631,6 @@ test "Test inner PKE" {
 }
 
 test "Test happy flow" {
-    if (comptime builtin.cpu.has(.s390x, .vector)) return error.SkipZigTest;
-
     var seed: [64]u8 = undefined;
     for (&seed, 0..) |*s, i| {
         s.* = @as(u8, @intCast(i));
@@ -1661,23 +1655,14 @@ test "Test happy flow" {
 // Code to test NIST Known Answer Tests (KAT), see PQCgenKAT.c.
 
 test "NIST KAT test d00.Kyber512" {
-    if (comptime builtin.cpu.has(.loongarch, .lsx)) return error.SkipZigTest;
-    if (comptime builtin.cpu.has(.s390x, .vector)) return error.SkipZigTest;
-
     try testNistKat(d00.Kyber512, "e9c2bd37133fcb40772f81559f14b1f58dccd1c816701be9ba6214d43baf4547");
 }
 
 test "NIST KAT test d00.Kyber1024" {
-    if (comptime builtin.cpu.has(.loongarch, .lsx)) return error.SkipZigTest;
-    if (comptime builtin.cpu.has(.s390x, .vector)) return error.SkipZigTest;
-
     try testNistKat(d00.Kyber1024, "89248f2f33f7f4f7051729111f3049c409a933ec904aedadf035f30fa5646cd5");
 }
 
 test "NIST KAT test d00.Kyber768" {
-    if (comptime builtin.cpu.has(.loongarch, .lsx)) return error.SkipZigTest;
-    if (comptime builtin.cpu.has(.s390x, .vector)) return error.SkipZigTest;
-
     try testNistKat(d00.Kyber768, "a1e122cad3c24bc51622e4c242d8b8acbcd3f618fee4220400605ca8f9ea02c2");
 }
 

package/std/debug/Dwarf.zig

@@ -879,16 +879,16 @@ fn parseAbbrevTable(di: *Dwarf, gpa: Allocator, offset: u64) !Abbrev.Table {
     var fr: Reader = .fixed(di.section(.debug_abbrev).?);
     fr.seek = cast(usize, offset) orelse return bad();
 
-    var abbrevs = std.array_list.Managed(Abbrev).init(gpa);
+    var abbrevs: std.ArrayList(Abbrev) = .empty;
     defer {
         for (abbrevs.items) |*abbrev| {
             abbrev.deinit(gpa);
         }
-        abbrevs.deinit();
+        abbrevs.deinit(gpa);
     }
 
-    var attrs = std.array_list.Managed(Abbrev.Attr).init(gpa);
-    defer attrs.deinit();
+    var attrs: std.ArrayList(Abbrev.Attr) = .empty;
+    defer attrs.deinit(gpa);
 
     while (true) {
         const code = try fr.takeLeb128(u64);
@@ -900,7 +900,7 @@ fn parseAbbrevTable(di: *Dwarf, gpa: Allocator, offset: u64) !Abbrev.Table {
             const attr_id = try fr.takeLeb128(u64);
             const form_id = try fr.takeLeb128(u64);
             if (attr_id == 0 and form_id == 0) break;
-            try attrs.append(.{
+            try attrs.append(gpa, .{
                 .id = attr_id,
                 .form_id = form_id,
                 .payload = switch (form_id) {
@@ -909,18 +909,18 @@ fn parseAbbrevTable(di: *Dwarf, gpa: Allocator, offset: u64) !Abbrev.Table {
                 },
             });
         }
-
-        try abbrevs.append(.{
+        try abbrevs.ensureUnusedCapacity(gpa, 1);
+        abbrevs.appendAssumeCapacity(.{
             .code = code,
             .tag_id = tag_id,
             .has_children = has_children,
-            .attrs = try attrs.toOwnedSlice(),
+            .attrs = try attrs.toOwnedSlice(gpa),
         });
     }
 
     return .{
         .offset = offset,
-        .abbrevs = try abbrevs.toOwnedSlice(),
+        .abbrevs = try abbrevs.toOwnedSlice(gpa),
     };
 }
 
@@ -1204,10 +1204,13 @@ fn runLineNumberProgram(d: *Dwarf, gpa: Allocator, endian: Endian, compile_unit:
         }
     }{ .keys = line_table.keys() });
 
+    try directories.shrinkToLen(gpa);
+    try file_entries.shrinkToLen(gpa);
+
     return .{
         .line_table = line_table,
-        .directories = try directories.toOwnedSlice(gpa),
-        .files = try file_entries.toOwnedSlice(gpa),
+        .directories = directories.toOwnedSliceAssert(),
+        .files = file_entries.toOwnedSliceAssert(),
         .version = version,
     };
 }

package/std/debug/Pdb.zig

@@ -83,8 +83,8 @@ pub fn parseDbiStream(self: *Pdb) !void {
     const mod_info_size = header.mod_info_size;
     const section_contrib_size = header.section_contribution_size;
 
-    var modules = std.array_list.Managed(Module).init(gpa);
-    errdefer modules.deinit();
+    var modules: std.ArrayList(Module) = .empty;
+    defer modules.deinit(gpa);
 
     // Module Info Substream
     var mod_info_offset: usize = 0;
@@ -113,11 +113,16 @@ pub fn parseDbiStream(self: *Pdb) !void {
             this_record_len += march_forward_bytes;
         }
 
-        try modules.append(.{
-            .mod_info = mod_info,
-            .module_name = try module_name.toOwnedSlice(),
-            .obj_file_name = try obj_file_name.toOwnedSlice(),
+        try modules.ensureUnusedCapacity(gpa, 1);
+        const module_name_slice = try module_name.toOwnedSlice();
+        errdefer gpa.free(module_name_slice);
+        const obj_file_name_slice = try obj_file_name.toOwnedSlice();
+        errdefer gpa.free(obj_file_name_slice);
 
+        modules.appendAssumeCapacity(.{
+            .mod_info = mod_info,
+            .module_name = module_name_slice,
+            .obj_file_name = obj_file_name_slice,
             .populated = false,
             .symbols = undefined,
             .subsect_info = undefined,
@@ -131,8 +136,8 @@ pub fn parseDbiStream(self: *Pdb) !void {
     }
 
     // Section Contribution Substream
-    var sect_contribs = std.array_list.Managed(pdb.SectionContribEntry).init(gpa);
-    errdefer sect_contribs.deinit();
+    var sect_contribs: std.ArrayList(pdb.SectionContribEntry) = .empty;
+    defer sect_contribs.deinit(gpa);
 
     var sect_cont_offset: usize = 0;
     if (section_contrib_size != 0) {
@@ -144,7 +149,7 @@ pub fn parseDbiStream(self: *Pdb) !void {
         sect_cont_offset += @sizeOf(u32);
     }
     while (sect_cont_offset != section_contrib_size) {
-        const entry = try sect_contribs.addOne();
+        const entry = try sect_contribs.addOne(gpa);
         entry.* = try reader.takeStruct(pdb.SectionContribEntry, .little);
         sect_cont_offset += @sizeOf(pdb.SectionContribEntry);
 
@@ -152,8 +157,11 @@ pub fn parseDbiStream(self: *Pdb) !void {
             return error.InvalidDebugInfo;
     }
 
-    self.modules = try modules.toOwnedSlice();
-    self.sect_contribs = try sect_contribs.toOwnedSlice();
+    try sect_contribs.shrinkToLen(gpa);
+    try modules.shrinkToLen(gpa);
+
+    self.sect_contribs = sect_contribs.toOwnedSliceAssert();
+    self.modules = modules.toOwnedSliceAssert();
 }
 
 pub fn parseIpiStream(self: *Pdb) !void {
@@ -1098,22 +1106,22 @@ const MsfStream = struct {
     }
 };
 
-fn readSparseBitVector(reader: *Io.Reader, allocator: Allocator) ![]u32 {
+fn readSparseBitVector(reader: *Io.Reader, gpa: Allocator) ![]u32 {
     const num_words = try reader.takeInt(u32, .little);
-    var list = std.array_list.Managed(u32).init(allocator);
-    errdefer list.deinit();
+    var list: std.ArrayList(u32) = .empty;
+    defer list.deinit(gpa);
     var word_i: u32 = 0;
     while (word_i != num_words) : (word_i += 1) {
         const word = try reader.takeInt(u32, .little);
         var bit_i: u5 = 0;
         while (true) : (bit_i += 1) {
             if (word & (@as(u32, 1) << bit_i) != 0) {
-                try list.append(word_i * 32 + bit_i);
+                try list.append(gpa, word_i * 32 + bit_i);
             }
             if (bit_i == std.math.maxInt(u5)) break;
         }
     }
-    return try list.toOwnedSlice();
+    return try list.toOwnedSlice(gpa);
 }
 
 fn blockCountFromSize(size: u32, block_size: u32) u32 {

package/std/hash/xxhash.zig

@@ -780,8 +780,6 @@ fn testExpect(comptime H: type, seed: anytype, input: []const u8, expected: u64)
 }
 
 test "xxhash3" {
-    if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/23807
-
     const H = XxHash3;
     // Non-Seeded Tests
     try testExpect(H, 0, "", 0x2d06800538d394c2);
@@ -813,8 +811,6 @@ test "xxhash3" {
 }
 
 test "xxhash3 smhasher" {
-    if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/23807
-
     const Test = struct {
         fn do() !void {
             try expectEqual(verify.smhasher(XxHash3.hash), 0x9a636405);
@@ -826,8 +822,6 @@ test "xxhash3 smhasher" {
 }
 
 test "xxhash3 iterative api" {
-    if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/23807
-
     const Test = struct {
         fn do() !void {
             try verify.iterativeApi(XxHash3);

package/std/math/log10.zig

@@ -139,8 +139,6 @@ test log10_int {
     if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
-    if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.cpu.arch.isWasm()) return error.SkipZigTest; // TODO
-    if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.cpu.arch == .hexagon) return error.SkipZigTest;
 
     inline for (
         .{ u8, u16, u32, u64, u128, u256, u512 },

package/std/math/modf.zig

@@ -86,8 +86,7 @@ fn ModfTests(comptime T: type) type {
         }
         test "vector" {
             if (builtin.os.tag.isDarwin() and builtin.cpu.arch == .aarch64) return error.SkipZigTest;
-            if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
-            if (comptime builtin.cpu.has(.loongarch, .lsx)) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/159529
+            if (builtin.cpu.arch == .s390x) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/194256
 
             const widths = [_]comptime_int{ 1, 2, 3, 4, 8, 16 };
 

package/std/mem.zig

@@ -4809,8 +4809,7 @@ pub fn doNotOptimizeAway(val: anytype) void {
             } else doNotOptimizeAway(&val);
         },
         .float => {
-            // https://github.com/llvm/llvm-project/issues/159200
-            if ((t.float.bits == 32 or t.float.bits == 64) and builtin.zig_backend != .stage2_c and !builtin.cpu.arch.isLoongArch()) {
+            if ((t.float.bits == 32 or t.float.bits == 64) and builtin.zig_backend != .stage2_c) {
                 asm volatile (""
                     :
                     : [_] "rm" (val),

package/std/os/linux/x86.zig

@@ -109,8 +109,8 @@ pub fn syscall6(
         \\ push %%ebp
         \\ mov 4(%%esp), %%ebp
         \\ mov %%edi, 4(%%esp)
-        \\ // The saved %edi and %ebp are on the stack, and %ebp points to `args56`.
-        \\ // Prepare the last two args, syscall, then pop the saved %ebp and %edi.
+        \\ // The saved %%edi and %%ebp are on the stack, and %%ebp points to `args56`.
+        \\ // Prepare the last two args, syscall, then pop the saved %%ebp and %%edi.
         \\ mov (%%ebp), %%edi
         \\ mov 4(%%ebp), %%ebp
         \\ int  $0x80

package/std/os/windows.zig

@@ -5665,7 +5665,136 @@ pub const PF = enum(DWORD) {
     ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE = 44,
 
     /// This Arm processor implements the Arm v8.3 LRCPC instructions (for example, LDAPR). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.
-    ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE,
+    ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE = 45,
+
+    /// This Arm processor implements the SVE (Scalable Vector Extension) instructions (FEAT_SVE).
+    ARM_SVE_INSTRUCTIONS_AVAILABLE = 46,
+
+    /// This Arm processor implements the SVE2 instructions (FEAT_SVE2).
+    ARM_SVE2_INSTRUCTIONS_AVAILABLE = 47,
+
+    /// This Arm processor implements the SVE2.1 instructions (FEAT_SVE2p1).
+    ARM_SVE2_1_INSTRUCTIONS_AVAILABLE = 48,
+
+    /// This Arm processor implements the SVE AES instructions (FEAT_SVE_AES).
+    ARM_SVE_AES_INSTRUCTIONS_AVAILABLE = 49,
+
+    /// This Arm processor implements the SVE 128-bit polynomial multiply long instructions (FEAT_SVE_PMULL128).
+    ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE = 50,
+
+    /// This Arm processor implements the SVE bit permute instructions (FEAT_SVE_BitPerm).
+    ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE = 51,
+
+    /// This Arm processor implements the SVE BF16 (BFloat16) instructions (FEAT_BF16).
+    ARM_SVE_BF16_INSTRUCTIONS_AVAILABLE = 52,
+
+    /// This Arm processor implements the SVE EBF16 (Extended BFloat16) instructions (FEAT_EBF16).
+    ARM_SVE_EBF16_INSTRUCTIONS_AVAILABLE = 53,
+
+    /// This Arm processor implements the SVE B16B16 instructions (FEAT_SVE_B16B16).
+    ARM_SVE_B16B16_INSTRUCTIONS_AVAILABLE = 54,
+
+    /// This Arm processor implements the SVE SHA-3 cryptographic instructions (FEAT_SVE_SHA3).
+    ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE = 55,
+
+    /// This Arm processor implements the SVE SM4 cryptographic instructions (FEAT_SVE_SM4).
+    ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE = 56,
+
+    /// This Arm processor implements the SVE I8MM (Int8 matrix multiply) instructions (FEAT_I8MM).
+    ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE = 57,
+
+    /// This Arm processor implements the SVE F32MM (FP32 matrix multiply) instructions (FEAT_F32MM).
+    ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE = 58,
+
+    /// This Arm processor implements the SVE F64MM (FP64 matrix multiply) instructions (FEAT_F64MM).
+    ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE = 59,
+
+    /// This x64 processor implements the BMI2 instruction set.
+    BMI2_INSTRUCTIONS_AVAILABLE = 60,
+
+    /// This x64 processor implements the MOVDIR64B instruction.
+    MOVDIR64B_INSTRUCTION_AVAILABLE = 61,
+
+    /// This Arm processor implements the LSE2 atomic instructions (FEAT_LSE2).
+    ARM_LSE2_AVAILABLE = 62,
+
+    /// This Arm processor implements the SHA-3 cryptographic instructions (FEAT_SHA3).
+    ARM_SHA3_INSTRUCTIONS_AVAILABLE = 64,
+
+    /// This Arm processor implements the SHA-512 cryptographic instructions (FEAT_SHA512).
+    ARM_SHA512_INSTRUCTIONS_AVAILABLE = 65,
+
+    /// This Arm processor implements the I8MM (Int8 matrix multiply) NEON instructions (FEAT_I8MM).
+    ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE = 66,
+
+    /// This Arm processor implements the FP16 (half-precision floating point) NEON instructions (FEAT_FP16).
+    ARM_V82_FP16_INSTRUCTIONS_AVAILABLE = 67,
+
+    /// This Arm processor implements the BF16 (BFloat16) NEON instructions (FEAT_BF16).
+    ARM_V86_BF16_INSTRUCTIONS_AVAILABLE = 68,
+
+    /// This Arm processor implements the EBF16 (Extended BFloat16) NEON instructions (FEAT_EBF16).
+    ARM_V86_EBF16_INSTRUCTIONS_AVAILABLE = 69,
+
+    /// This Arm processor implements the SME (Scalable Matrix Extension) instructions (FEAT_SME).
+    ARM_SME_INSTRUCTIONS_AVAILABLE = 70,
+
+    /// This Arm processor implements the SME2 instructions (FEAT_SME2).
+    ARM_SME2_INSTRUCTIONS_AVAILABLE = 71,
+
+    /// This Arm processor implements the SME2.1 instructions (FEAT_SME2p1).
+    ARM_SME2_1_INSTRUCTIONS_AVAILABLE = 72,
+
+    /// This Arm processor implements the SME2.2 instructions (FEAT_SME2p2).
+    ARM_SME2_2_INSTRUCTIONS_AVAILABLE = 73,
+
+    /// This Arm processor implements the SVE AES instructions when in Streaming SVE mode (FEAT_SSVE_AES).
+    ARM_SME_AES_INSTRUCTIONS_AVAILABLE = 74,
+
+    /// This Arm processor implements the SVE bit permute instructions when in Streaming SVE mode (FEAT_SSVE_BitPerm).
+    ARM_SME_SBITPERM_INSTRUCTIONS_AVAILABLE = 75,
+
+    /// This Arm processor implements the SVE FMMLA (widening, 4-way, FP8 to FP16) instruction when in Streaming SVE mode (FEAT_SSVE_F8F16MM).
+    ARM_SME_SF8MM4_INSTRUCTIONS_AVAILABLE = 76,
+
+    /// This Arm processor implements the SVE FMMLA (widening, 8-way, FP8 to FP32) instruction when in Streaming SVE mode (FEAT_SSVE_F8F32MM).
+    ARM_SME_SF8MM8_INSTRUCTIONS_AVAILABLE = 77,
+
+    /// This Arm processor implements the SVE2 FP8DOT2 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT2).
+    ARM_SME_SF8DP2_INSTRUCTIONS_AVAILABLE = 78,
+
+    /// This Arm processor implements the SVE2 FP8DOT4 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT4).
+    ARM_SME_SF8DP4_INSTRUCTIONS_AVAILABLE = 79,
+
+    /// This Arm processor implements the SVE2 FP8FMA instructions when in Streaming SVE mode (FEAT_SSVE_FP8FMA).
+    ARM_SME_SF8FMA_INSTRUCTIONS_AVAILABLE = 80,
+
+    /// This Arm processor implements the SME F8F32 instructions (FEAT_SME_F8F32).
+    ARM_SME_F8F32_INSTRUCTIONS_AVAILABLE = 81,
+
+    /// This Arm processor implements the SME F8F16 instructions (FEAT_SME_F8F16).
+    ARM_SME_F8F16_INSTRUCTIONS_AVAILABLE = 82,
+
+    /// This Arm processor implements the SME F16F16 instructions (FEAT_SME_F16F16).
+    ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE = 83,
+
+    /// This Arm processor implements the SME B16B16 instructions (FEAT_SME_B16B16).
+    ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE = 84,
+
+    /// This Arm processor implements the SME F64F64 instructions (FEAT_SME_F64F64).
+    ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE = 85,
+
+    /// This Arm processor implements the SME I16I64 instructions (FEAT_SME_I16I64).
+    ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE = 86,
+
+    /// This Arm processor implements the SME LUTv2 instructions (FEAT_SME_LUTv2).
+    ARM_SME_LUTv2_INSTRUCTIONS_AVAILABLE = 87,
+
+    /// This Arm processor implements SME FA64 (Full AArch64 instruction set when in Streaming SVE mode) (FEAT_SME_FA64).
+    ARM_SME_FA64_INSTRUCTIONS_AVAILABLE = 88,
+
+    /// This x64 processor implements the UMONITOR instruction.
+    UMONITOR_INSTRUCTION_AVAILABLE = 89,
 };
 
 pub const MAX_WOW64_SHARED_ENTRIES = 16;

package/std/simd.zig

@@ -157,13 +157,6 @@ pub fn join(a: anytype, b: anytype) @Vector(vectorLength(@TypeOf(a)) + vectorLen
 /// Returns a vector whose elements alternates between those of each input vector.
 /// For example, `interlace(.{[4]u32{11, 12, 13, 14}, [4]u32{21, 22, 23, 24}})` returns a vector containing `.{11, 21, 12, 22, 13, 23, 14, 24}`.
 pub fn interlace(vecs: anytype) @Vector(vectorLength(@TypeOf(vecs[0])) * vecs.len, std.meta.Child(@TypeOf(vecs[0]))) {
-    // interlace doesn't work on MIPS, for some reason.
-    // Notes from earlier debug attempt:
-    //  The indices are correct. The problem seems to be with the @shuffle builtin.
-    //  On MIPS, the test that interlaces small_base gives { 0, 2, 0, 0, 64, 255, 248, 200, 0, 0 }.
-    //  Calling this with two inputs seems to work fine, but I'll let the compile error trigger for all inputs, just to be safe.
-    if (builtin.cpu.arch.isMIPS()) @compileError("TODO: Find out why interlace() doesn't work on MIPS");
-
     const VecType = @TypeOf(vecs[0]);
     const vecs_arr = @as([vecs.len]VecType, vecs);
     const Child = std.meta.Child(@TypeOf(vecs_arr[0]));
@@ -247,13 +240,11 @@ test "vector patterns" {
     try std.testing.expectEqual([8]u32{ 10, 20, 30, 40, 55, 66, 77, 88 }, join(base, other_base));
     try std.testing.expectEqual([2]u32{ 20, 30 }, extract(base, 1, 2));
 
-    if (!builtin.cpu.arch.isMIPS()) {
-        try std.testing.expectEqual([8]u32{ 10, 55, 20, 66, 30, 77, 40, 88 }, interlace(.{ base, other_base }));
+    try std.testing.expectEqual([8]u32{ 10, 55, 20, 66, 30, 77, 40, 88 }, interlace(.{ base, other_base }));
 
-        const small_braid = interlace(small_bases);
-        try std.testing.expectEqual([10]u8{ 0, 2, 4, 6, 8, 1, 3, 5, 7, 9 }, small_braid);
-        try std.testing.expectEqual(small_bases, deinterlace(small_bases.len, small_braid));
-    }
+    const small_braid = interlace(small_bases);
+    try std.testing.expectEqual([10]u8{ 0, 2, 4, 6, 8, 1, 3, 5, 7, 9 }, small_braid);
+    try std.testing.expectEqual(small_bases, deinterlace(small_bases.len, small_braid));
 }
 
 /// Joins two vectors, shifts them leftwards (towards lower indices) and extracts the leftmost elements into a vector the length of a and b.
@@ -384,9 +375,6 @@ pub fn prefixScanWithFunc(
     /// For example, this should be 0 for addition or 1 for multiplication.
     comptime identity: std.meta.Child(@TypeOf(vec)),
 ) if (ErrorType == void) @TypeOf(vec) else ErrorType!@TypeOf(vec) {
-    // I haven't debugged this, but it might be a cousin of sorts to what's going on with interlace.
-    if (builtin.cpu.arch.isMIPS()) @compileError("TODO: Find out why prefixScan doesn't work on MIPS");
-
     const len = vectorLength(@TypeOf(vec));
 
     if (hop == 0) @compileError("hop can not be 0; you'd be going nowhere forever!");
@@ -456,11 +444,6 @@ pub fn prefixScan(comptime op: std.builtin.ReduceOp, comptime hop: isize, vec: a
 }
 
 test "vector prefix scan" {
-    if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893
-    if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
-
-    if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-
     const int_base = @Vector(4, i32){ 11, 23, 9, -21 };
     const float_base = @Vector(4, f32){ 2, 0.5, -10, 6.54321 };
     const bool_base = @Vector(4, bool){ true, false, true, false };

package/std/start.zig

@@ -20,8 +20,9 @@ comptime {
     _ = root;
 
     if (builtin.output_mode == .Lib and builtin.link_mode == .dynamic) {
-        if (native_os == .windows and !@hasDecl(root, "_DllMainCRTStartup")) {
-            @export(&_DllMainCRTStartup, .{ .name = "_DllMainCRTStartup" });
+        const dll_main_crt_startup = if (builtin.abi.isGnu()) "DllMainCRTStartup" else "_DllMainCRTStartup";
+        if (native_os == .windows and !builtin.link_libc and !@hasDecl(root, dll_main_crt_startup)) {
+            @export(&DllMainCRTStartup, .{ .name = dll_main_crt_startup });
         }
     } else if (builtin.output_mode == .Exe or @hasDecl(root, "main")) {
         if (builtin.link_libc and @hasDecl(root, "main")) {
@@ -71,7 +72,7 @@ comptime {
     }
 }
 
-fn _DllMainCRTStartup(
+fn DllMainCRTStartup(
     hinstDLL: std.os.windows.HINSTANCE,
     fdwReason: std.os.windows.DWORD,
     lpReserved: std.os.windows.LPVOID,

package/std/zig/Ast.zig

@@ -196,19 +196,17 @@ pub fn parseTokens(
         .zon => try parser.parseZon(),
     }
 
-    const extra_data = try parser.extra_data.toOwnedSlice(gpa);
-    errdefer gpa.free(extra_data);
-    const errors = try parser.errors.toOwnedSlice(gpa);
-    errdefer gpa.free(errors);
+    try parser.extra_data.shrinkToLen(gpa);
+    try parser.errors.shrinkToLen(gpa);
 
     // TODO experiment with compacting the MultiArrayList slices here
-    return Ast{
+    return .{
         .source = source,
         .mode = mode,
         .tokens = tokens,
         .nodes = parser.nodes.toOwnedSlice(),
-        .extra_data = extra_data,
-        .errors = errors,
+        .extra_data = parser.extra_data.toOwnedSliceAssert(),
+        .errors = parser.errors.toOwnedSliceAssert(),
     };
 }