@yowasp/yosys 0.59.35-dev.1011 → 0.59.84-dev.1025

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (13) hide show
  1. package/gen/bundle.js +305 -105
  2. package/gen/yosys-resources.tar +0 -0
  3. package/gen/yosys.core.wasm +0 -0
  4. package/lib/api.d.ts +4 -0
  5. package/package.json +6 -7
  6. package/gen/resources-yosys.js +0 -425
  7. package/gen/share/ice40/cells_sim.v +0 -3502
  8. package/gen/share/lattice/cells_bb_nexus.v +0 -10389
  9. package/gen/share/nexus/cells_xtra.v +0 -10389
  10. package/gen/share/quicklogic/qlf_k6n10f/bram_types_sim.v +0 -74035
  11. package/gen/share/quicklogic/qlf_k6n10f/brams_sim.v +0 -10949
  12. package/gen/share/xilinx/cells_sim.v +0 -4397
  13. package/gen/share/xilinx/cells_xtra.v +0 -34120
package/gen/share/ice40/cells_sim.v DELETED
@@ -1,3502 +0,0 @@
1
- `timescale 1ps / 1ps
2
- `define SB_DFF_INIT initial Q = 0;
3
- // `define SB_DFF_INIT
4
-
5
- `ifndef NO_ICE40_DEFAULT_ASSIGNMENTS
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- `define ICE40_DEFAULT_ASSIGNMENT_V(v) = v
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- `define ICE40_DEFAULT_ASSIGNMENT_0 = 1'b0
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- `define ICE40_DEFAULT_ASSIGNMENT_1 = 1'b1
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- `else
10
- `define ICE40_DEFAULT_ASSIGNMENT_V(v)
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- `define ICE40_DEFAULT_ASSIGNMENT_0
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- `define ICE40_DEFAULT_ASSIGNMENT_1
13
- `endif
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-
15
- // SiliconBlue IO Cells
16
-
17
- module SB_IO (
18
- inout PACKAGE_PIN,
19
- input LATCH_INPUT_VALUE,
20
- input CLOCK_ENABLE `ICE40_DEFAULT_ASSIGNMENT_1,
21
- input INPUT_CLK,
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- input OUTPUT_CLK,
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- input OUTPUT_ENABLE,
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- input D_OUT_0,
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- input D_OUT_1,
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- output D_IN_0,
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- output D_IN_1
28
- );
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- parameter [5:0] PIN_TYPE = 6'b000000;
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- parameter [0:0] PULLUP = 1'b0;
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- parameter [0:0] NEG_TRIGGER = 1'b0;
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- parameter IO_STANDARD = "SB_LVCMOS";
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-
34
- `ifndef BLACKBOX
35
- reg dout, din_0, din_1;
36
- reg din_q_0, din_q_1;
37
- reg dout_q_0, dout_q_1;
38
- reg outena_q;
39
-
40
- // IO tile generates a constant 1'b1 internally if global_cen is not connected
41
- wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
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- reg clken_pulled_ri;
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- reg clken_pulled_ro;
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-
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- generate if (!NEG_TRIGGER) begin
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- always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
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- always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
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- always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
49
- always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
50
- always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
51
- always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
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- always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
53
- end else begin
54
- always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
55
- always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
56
- always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
57
- always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
58
- always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
59
- always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
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- always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
61
- end endgenerate
62
-
63
- always @* begin
64
- if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
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- din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
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- din_1 = din_q_1;
67
- end
68
-
69
- // work around simulation glitches on dout in DDR mode
70
- reg outclk_delayed_1;
71
- reg outclk_delayed_2;
72
- always @* outclk_delayed_1 <= OUTPUT_CLK;
73
- always @* outclk_delayed_2 <= outclk_delayed_1;
74
-
75
- always @* begin
76
- if (PIN_TYPE[3])
77
- dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
78
- else
79
- dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
80
- end
81
-
82
- assign D_IN_0 = din_0, D_IN_1 = din_1;
83
-
84
- generate
85
- if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
86
- if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
87
- if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
88
- endgenerate
89
- `endif
90
- `ifdef TIMING
91
- specify
92
- (INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0);
93
- (INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0);
94
- (PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0);
95
- (OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0);
96
- (D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0);
97
- (OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0);
98
-
99
- $setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
100
- $setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
101
- $setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
102
- $setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
103
- $setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
104
- $setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
105
- $setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
106
- $setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
107
- $setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
108
- $setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
109
- $setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
110
- $setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
111
- $setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
112
- $setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
113
- $setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
114
- $setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
115
- $setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
116
- $setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
117
- $setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
118
- $setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
119
- endspecify
120
- `endif
121
- endmodule
122
-
123
- module SB_GB_IO (
124
- inout PACKAGE_PIN,
125
- output GLOBAL_BUFFER_OUTPUT,
126
- input LATCH_INPUT_VALUE,
127
- input CLOCK_ENABLE `ICE40_DEFAULT_ASSIGNMENT_1,
128
- input INPUT_CLK,
129
- input OUTPUT_CLK,
130
- input OUTPUT_ENABLE,
131
- input D_OUT_0,
132
- input D_OUT_1,
133
- output D_IN_0,
134
- output D_IN_1
135
- );
136
- parameter [5:0] PIN_TYPE = 6'b000000;
137
- parameter [0:0] PULLUP = 1'b0;
138
- parameter [0:0] NEG_TRIGGER = 1'b0;
139
- parameter IO_STANDARD = "SB_LVCMOS";
140
-
141
- assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
142
-
143
- SB_IO #(
144
- .PIN_TYPE(PIN_TYPE),
145
- .PULLUP(PULLUP),
146
- .NEG_TRIGGER(NEG_TRIGGER),
147
- .IO_STANDARD(IO_STANDARD)
148
- ) IO (
149
- .PACKAGE_PIN(PACKAGE_PIN),
150
- .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
151
- .CLOCK_ENABLE(CLOCK_ENABLE),
152
- .INPUT_CLK(INPUT_CLK),
153
- .OUTPUT_CLK(OUTPUT_CLK),
154
- .OUTPUT_ENABLE(OUTPUT_ENABLE),
155
- .D_OUT_0(D_OUT_0),
156
- .D_OUT_1(D_OUT_1),
157
- .D_IN_0(D_IN_0),
158
- .D_IN_1(D_IN_1)
159
- );
160
- endmodule
161
-
162
- module SB_GB (
163
- input USER_SIGNAL_TO_GLOBAL_BUFFER,
164
- output GLOBAL_BUFFER_OUTPUT
165
- );
166
- assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
167
- `ifdef TIMING
168
- specify
169
- (USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0);
170
- endspecify
171
- `endif
172
- endmodule
173
-
174
- // SiliconBlue Logic Cells
175
-
176
- (* abc9_lut=1, lib_whitebox *)
177
- module SB_LUT4 (
178
- output O,
179
- input I0 `ICE40_DEFAULT_ASSIGNMENT_0,
180
- input I1 `ICE40_DEFAULT_ASSIGNMENT_0,
181
- input I2 `ICE40_DEFAULT_ASSIGNMENT_0,
182
- input I3 `ICE40_DEFAULT_ASSIGNMENT_0
183
- );
184
- parameter [15:0] LUT_INIT = 0;
185
- wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
186
- wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
187
- wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
188
- assign O = I0 ? s1[1] : s1[0];
189
- `ifdef ICE40_HX
190
- specify
191
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
192
- (I0 => O) = (449, 386);
193
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
194
- (I1 => O) = (400, 379);
195
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
196
- (I2 => O) = (379, 351);
197
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
198
- (I3 => O) = (316, 288);
199
- endspecify
200
- `endif
201
- `ifdef ICE40_LP
202
- specify
203
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
204
- (I0 => O) = (662, 569);
205
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
206
- (I1 => O) = (589, 558);
207
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
208
- (I2 => O) = (558, 517);
209
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
210
- (I3 => O) = (465, 423);
211
- endspecify
212
- `endif
213
- `ifdef ICE40_U
214
- specify
215
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
216
- (I0 => O) = (1245, 1285);
217
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
218
- (I1 => O) = (1179, 1232);
219
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
220
- (I2 => O) = (1179, 1205);
221
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
222
- (I3 => O) = (861, 874);
223
- endspecify
224
- `endif
225
- endmodule
226
-
227
- (* lib_whitebox *)
228
- module SB_CARRY (output CO, input I0, I1, CI);
229
- assign CO = (I0 && I1) || ((I0 || I1) && CI);
230
- `ifdef ICE40_HX
231
- specify
232
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
233
- (CI => CO) = (126, 105);
234
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
235
- (I0 => CO) = (259, 245);
236
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
237
- (I1 => CO) = (231, 133);
238
- endspecify
239
- `endif
240
- `ifdef ICE40_LP
241
- specify
242
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
243
- (CI => CO) = (186, 155);
244
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
245
- (I0 => CO) = (382, 362);
246
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
247
- (I1 => CO) = (341, 196);
248
- endspecify
249
- `endif
250
- `ifdef ICE40_U
251
- specify
252
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
253
- (CI => CO) = (278, 278);
254
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
255
- (I0 => CO) = (675, 662);
256
- // https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
257
- (I1 => CO) = (609, 358);
258
- endspecify
259
- `endif
260
- endmodule
261
-
262
- // Positive Edge SiliconBlue FF Cells
263
-
264
- (* abc9_flop, lib_whitebox *)
265
- module SB_DFF (
266
- output reg Q,
267
- input C, D
268
- );
269
- `SB_DFF_INIT
270
-
271
- always @(posedge C)
272
- Q <= D;
273
- `ifdef ICE40_HX
274
- specify
275
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
276
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
277
- $setup(D, posedge C, 470 - 449);
278
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
279
- (posedge C => (Q : D)) = 540;
280
- endspecify
281
- `endif
282
- `ifdef ICE40_LP
283
- specify
284
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
285
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
286
- $setup(D, posedge C, 693 - 662);
287
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
288
- (posedge C => (Q : D)) = 796;
289
- endspecify
290
- `endif
291
- `ifdef ICE40_U
292
- specify
293
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
294
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
295
- $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
296
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
297
- (posedge C => (Q : D)) = 1391;
298
- endspecify
299
- `endif
300
- endmodule
301
-
302
- (* abc9_flop, lib_whitebox *)
303
- module SB_DFFE (
304
- output reg Q,
305
- input C,
306
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
307
- input D
308
- );
309
- `SB_DFF_INIT
310
-
311
- always @(posedge C)
312
- if (E)
313
- Q <= D;
314
- `ifdef ICE40_HX
315
- specify
316
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
317
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
318
- $setup(D, posedge C &&& E, 470 - 449);
319
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
320
- $setup(E, posedge C, 0);
321
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
322
- if (E) (posedge C => (Q : D)) = 540;
323
- endspecify
324
- `endif
325
- `ifdef ICE40_LP
326
- specify
327
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
328
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
329
- $setup(D, posedge C &&& E, 693 - 662);
330
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
331
- $setup(E, posedge C, 0);
332
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
333
- if (E) (posedge C => (Q : D)) = 796;
334
- endspecify
335
- `endif
336
- `ifdef ICE40_U
337
- specify
338
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
339
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
340
- $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
341
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
342
- $setup(E, posedge C, 0);
343
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
344
- if (E) (posedge C => (Q : D)) = 1391;
345
- endspecify
346
- `endif
347
- endmodule
348
-
349
- (* abc9_flop, lib_whitebox *)
350
- module SB_DFFSR (
351
- output reg Q,
352
- input C, R, D
353
- );
354
- `SB_DFF_INIT
355
-
356
- always @(posedge C)
357
- if (R)
358
- Q <= 0;
359
- else
360
- Q <= D;
361
- `ifdef ICE40_HX
362
- specify
363
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
364
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
365
- $setup(D, posedge C, 470 - 449);
366
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
367
- $setup(R, posedge C, 203);
368
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
369
- if ( R) (posedge C => (Q : 1'b0)) = 540;
370
- if (!R) (posedge C => (Q : D)) = 540;
371
- endspecify
372
- `endif
373
- `ifdef ICE40_LP
374
- specify
375
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
376
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
377
- $setup(D, posedge C, 693 - 662);
378
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
379
- $setup(R, posedge C, 299);
380
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
381
- if ( R) (posedge C => (Q : 1'b0)) = 796;
382
- if (!R) (posedge C => (Q : D)) = 796;
383
- endspecify
384
- `endif
385
- `ifdef ICE40_U
386
- specify
387
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
388
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
389
- $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
390
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
391
- $setup(R, posedge C, 530);
392
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
393
- if ( R) (posedge C => (Q : 1'b0)) = 1391;
394
- if (!R) (posedge C => (Q : D)) = 1391;
395
- endspecify
396
- `endif
397
- endmodule
398
-
399
- (* abc9_box, lib_whitebox *)
400
- module SB_DFFR (
401
- output reg Q,
402
- input C, R, D
403
- );
404
- `SB_DFF_INIT
405
-
406
- always @(posedge C, posedge R)
407
- if (R)
408
- Q <= 0;
409
- else
410
- Q <= D;
411
- `ifdef ICE40_HX
412
- specify
413
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
414
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
415
- $setup(D, posedge C, 470 - 449);
416
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
417
- $setup(negedge R, posedge C, 160);
418
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
419
- `ifndef YOSYS
420
- (posedge R => (Q : 1'b0)) = 599;
421
- `else
422
- if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
423
- // but for facilitating a bypass box, let's pretend it's
424
- // a simple path
425
- `endif
426
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
427
- if (!R) (posedge C => (Q : D)) = 540;
428
- endspecify
429
- `endif
430
- `ifdef ICE40_LP
431
- specify
432
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
433
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
434
- $setup(D, posedge C, 693 - 662);
435
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
436
- $setup(negedge R, posedge C, 235);
437
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
438
- `ifndef YOSYS
439
- (posedge R => (Q : 1'b0)) = 883;
440
- `else
441
- if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
442
- // but for facilitating a bypass box, let's pretend it's
443
- // a simple path
444
- `endif
445
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
446
- if (!R) (posedge C => (Q : D)) = 796;
447
- endspecify
448
- `endif
449
- `ifdef ICE40_U
450
- specify
451
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
452
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
453
- $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
454
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
455
- $setup(negedge R, posedge C, 424);
456
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
457
- `ifndef YOSYS
458
- (posedge R => (Q : 1'b0)) = 1589;
459
- `else
460
- if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
461
- // but for facilitating a bypass box, let's pretend it's
462
- // a simple path
463
- `endif
464
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
465
- if (!R) (posedge C => (Q : D)) = 1391;
466
- endspecify
467
- `endif
468
- endmodule
469
-
470
- (* abc9_flop, lib_whitebox *)
471
- module SB_DFFSS (
472
- output reg Q,
473
- input C, S, D
474
- );
475
- `SB_DFF_INIT
476
-
477
- always @(posedge C)
478
- if (S)
479
- Q <= 1;
480
- else
481
- Q <= D;
482
- `ifdef ICE40_HX
483
- specify
484
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
485
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
486
- $setup(D, posedge C, 470 - 449);
487
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
488
- $setup(S, posedge C, 203);
489
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
490
- if ( S) (posedge C => (Q : 1'b1)) = 540;
491
- if (!S) (posedge C => (Q : D)) = 540;
492
- endspecify
493
- `endif
494
- `ifdef ICE40_LP
495
- specify
496
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
497
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
498
- $setup(D, posedge C, 693 - 662);
499
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
500
- $setup(S, posedge C, 299);
501
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
502
- if ( S) (posedge C => (Q : 1'b1)) = 796;
503
- if (!S) (posedge C => (Q : D)) = 796;
504
- endspecify
505
- `endif
506
- `ifdef ICE40_U
507
- specify
508
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
509
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
510
- $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
511
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
512
- $setup(S, posedge C, 530);
513
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
514
- if ( S) (posedge C => (Q : 1'b1)) = 1391;
515
- if (!S) (posedge C => (Q : D)) = 1391;
516
- endspecify
517
- `endif
518
- endmodule
519
-
520
- (* abc9_box, lib_whitebox *)
521
- module SB_DFFS (
522
- output reg Q,
523
- input C, S, D
524
- );
525
- `SB_DFF_INIT
526
-
527
- always @(posedge C, posedge S)
528
- if (S)
529
- Q <= 1;
530
- else
531
- Q <= D;
532
- `ifdef ICE40_HX
533
- specify
534
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
535
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
536
- $setup(D, posedge C, 470 - 449);
537
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
538
- $setup(negedge S, posedge C, 160);
539
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
540
- `ifndef YOSYS
541
- (posedge S => (Q : 1'b1)) = 599;
542
- `else
543
- if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
544
- // but for facilitating a bypass box, let's pretend it's
545
- // a simple path
546
- `endif
547
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
548
- if (!S) (posedge C => (Q : D)) = 540;
549
- endspecify
550
- `endif
551
- `ifdef ICE40_LP
552
- specify
553
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
554
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
555
- $setup(D, posedge C, 693 - 662);
556
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
557
- $setup(negedge S, posedge C, 235);
558
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
559
- `ifndef YOSYS
560
- (posedge S => (Q : 1'b1)) = 883;
561
- `else
562
- if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
563
- // but for facilitating a bypass box, let's pretend it's
564
- // a simple path
565
- `endif
566
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
567
- if (!S) (posedge C => (Q : D)) = 796;
568
- endspecify
569
- `endif
570
- `ifdef ICE40_U
571
- specify
572
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
573
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
574
- $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
575
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
576
- $setup(negedge S, posedge C, 424);
577
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
578
- `ifndef YOSYS
579
- (posedge S => (Q : 1'b1)) = 1589;
580
- `else
581
- if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
582
- // but for facilitating a bypass box, let's pretend it's
583
- // a simple path
584
- `endif
585
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
586
- if (!S) (posedge C => (Q : D)) = 1391;
587
- endspecify
588
- `endif
589
- endmodule
590
-
591
- (* abc9_flop, lib_whitebox *)
592
- module SB_DFFESR (
593
- output reg Q,
594
- input C,
595
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
596
- input R,
597
- input D
598
- );
599
- `SB_DFF_INIT
600
-
601
- always @(posedge C)
602
- if (E) begin
603
- if (R)
604
- Q <= 0;
605
- else
606
- Q <= D;
607
- end
608
- `ifdef ICE40_HX
609
- specify
610
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
611
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
612
- $setup(D, posedge C &&& E && !R, 470 - 449);
613
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
614
- $setup(E, posedge C, 0);
615
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
616
- $setup(R, posedge C &&& E, 203);
617
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
618
- if (E && R) (posedge C => (Q : 1'b0)) = 540;
619
- if (E && !R) (posedge C => (Q : D)) = 540;
620
- endspecify
621
- `endif
622
- `ifdef ICE40_LP
623
- specify
624
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
625
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
626
- $setup(D, posedge C &&& E && !R, 693 - 662);
627
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
628
- $setup(E, posedge C, 0);
629
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
630
- $setup(R, posedge C &&& E, 299);
631
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
632
- if (E && R) (posedge C => (Q : 1'b0)) = 796;
633
- if (E && !R) (posedge C => (Q : D)) = 796;
634
- endspecify
635
- `endif
636
- `ifdef ICE40_U
637
- specify
638
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
639
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
640
- $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
641
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
642
- $setup(E, posedge C, 0);
643
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
644
- $setup(R, posedge C &&& E, 530);
645
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
646
- if (E && R) (posedge C => (Q : 1'b0)) = 1391;
647
- if (E && !R) (posedge C => (Q : D)) = 1391;
648
- endspecify
649
- `endif
650
- endmodule
651
-
652
- (* abc9_box, lib_whitebox *)
653
- module SB_DFFER (
654
- output reg Q,
655
- input C,
656
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
657
- input R,
658
- input D
659
- );
660
- `SB_DFF_INIT
661
-
662
- always @(posedge C, posedge R)
663
- if (R)
664
- Q <= 0;
665
- else if (E)
666
- Q <= D;
667
- `ifdef ICE40_HX
668
- specify
669
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
670
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
671
- $setup(D, posedge C &&& E, 470 - 449);
672
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
673
- $setup(E, posedge C, 0);
674
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
675
- $setup(negedge R, posedge C, 160);
676
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
677
- `ifndef YOSYS
678
- (posedge R => (Q : 1'b0)) = 599;
679
- `else
680
- if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
681
- // but for facilitating a bypass box, let's pretend it's
682
- // a simple path
683
- `endif
684
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
685
- if (E && !R) (posedge C => (Q : D)) = 540;
686
- endspecify
687
- `endif
688
- `ifdef ICE40_LP
689
- specify
690
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
691
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
692
- $setup(D, posedge C &&& E, 693 - 662);
693
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
694
- $setup(E, posedge C, 0);
695
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
696
- $setup(negedge R, posedge C, 235);
697
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
698
- `ifndef YOSYS
699
- (posedge R => (Q : 1'b0)) = 883;
700
- `else
701
- if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
702
- // but for facilitating a bypass box, let's pretend it's
703
- // a simple path
704
- `endif
705
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
706
- if (E && !R) (posedge C => (Q : D)) = 796;
707
- endspecify
708
- `endif
709
- `ifdef ICE40_U
710
- specify
711
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
712
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
713
- $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
714
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
715
- $setup(E, posedge C, 0);
716
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
717
- $setup(negedge R, posedge C, 424);
718
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
719
- `ifndef YOSYS
720
- (posedge R => (Q : 1'b0)) = 1589;
721
- `else
722
- if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
723
- // but for facilitating a bypass box, let's pretend it's
724
- // a simple path
725
- `endif
726
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
727
- if (E && !R) (posedge C => (Q : D)) = 1391;
728
- endspecify
729
- `endif
730
- endmodule
731
-
732
- (* abc9_flop, lib_whitebox *)
733
- module SB_DFFESS (
734
- output reg Q,
735
- input C,
736
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
737
- input S,
738
- input D
739
- );
740
- `SB_DFF_INIT
741
-
742
- always @(posedge C)
743
- if (E) begin
744
- if (S)
745
- Q <= 1;
746
- else
747
- Q <= D;
748
- end
749
- `ifdef ICE40_HX
750
- specify
751
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
752
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
753
- $setup(D, posedge C &&& E && !S, 470 - 449);
754
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
755
- $setup(E, posedge C, 0);
756
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
757
- $setup(S, posedge C &&& E, 203);
758
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
759
- if (E && S) (posedge C => (Q : 1'b1)) = 540;
760
- if (E && !S) (posedge C => (Q : D)) = 540;
761
- endspecify
762
- `endif
763
- `ifdef ICE40_LP
764
- specify
765
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
766
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
767
- $setup(D, posedge C &&& E && !S, 693 - 662);
768
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
769
- $setup(E, posedge C, 0);
770
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
771
- $setup(S, posedge C &&& E, 299);
772
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
773
- if (E && S) (posedge C => (Q : 1'b1)) = 796;
774
- if (E && !S) (posedge C => (Q : D)) = 796;
775
- endspecify
776
- `endif
777
- `ifdef ICE40_U
778
- specify
779
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
780
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
781
- $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
782
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
783
- $setup(E, posedge C, 0);
784
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
785
- $setup(S, posedge C &&& E, 530);
786
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
787
- if (E && S) (posedge C => (Q : 1'b1)) = 1391;
788
- if (E && !S) (posedge C => (Q : D)) = 1391;
789
- endspecify
790
- `endif
791
- endmodule
792
-
793
- (* abc9_box, lib_whitebox *)
794
- module SB_DFFES (
795
- output reg Q,
796
- input C,
797
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
798
- input S,
799
- input D
800
- );
801
- `SB_DFF_INIT
802
-
803
- always @(posedge C, posedge S)
804
- if (S)
805
- Q <= 1;
806
- else if (E)
807
- Q <= D;
808
- `ifdef ICE40_HX
809
- specify
810
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
811
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
812
- $setup(D, posedge C &&& E, 470 - 449);
813
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
814
- $setup(E, posedge C, 0);
815
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
816
- $setup(posedge S, posedge C, 160);
817
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
818
- `ifndef YOSYS
819
- (posedge S => (Q : 1'b1)) = 599;
820
- `else
821
- if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
822
- // but for facilitating a bypass box, let's pretend it's
823
- // a simple path
824
- `endif
825
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
826
- if (E && !S) (posedge C => (Q : D)) = 540;
827
- endspecify
828
- `endif
829
- `ifdef ICE40_LP
830
- specify
831
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
832
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
833
- $setup(D, posedge C &&& E, 693 - 662);
834
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
835
- $setup(E, posedge C, 0);
836
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
837
- $setup(posedge S, posedge C, 235);
838
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
839
- `ifndef YOSYS
840
- (posedge S => (Q : 1'b1)) = 883;
841
- `else
842
- if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
843
- // but for facilitating a bypass box, let's pretend it's
844
- // a simple path
845
- `endif
846
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
847
- if (E && !S) (posedge C => (Q : D)) = 796;
848
- endspecify
849
- `endif
850
- `ifdef ICE40_U
851
- specify
852
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
853
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
854
- $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
855
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
856
- $setup(E, posedge C, 0);
857
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
858
- $setup(posedge S, posedge C, 424);
859
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
860
- `ifndef YOSYS
861
- (posedge S => (Q : 1'b1)) = 1589;
862
- `else
863
- if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
864
- // but for facilitating a bypass box, let's pretend it's
865
- // a simple path
866
- `endif
867
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
868
- if (E && !S) (posedge C => (Q : D)) = 1391;
869
- endspecify
870
- `endif
871
- endmodule
872
-
873
- // Negative Edge SiliconBlue FF Cells
874
-
875
- (* abc9_flop, lib_whitebox *)
876
- module SB_DFFN (
877
- output reg Q,
878
- input C, D
879
- );
880
- `SB_DFF_INIT
881
-
882
- always @(negedge C)
883
- Q <= D;
884
- `ifdef ICE40_HX
885
- specify
886
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
887
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
888
- $setup(D, negedge C, 470 - 449);
889
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
890
- (negedge C => (Q : D)) = 540;
891
- endspecify
892
- `endif
893
- `ifdef ICE40_LP
894
- specify
895
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
896
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
897
- $setup(D, negedge C, 693 - 662);
898
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
899
- (negedge C => (Q : D)) = 796;
900
- endspecify
901
- `endif
902
- `ifdef ICE40_U
903
- specify
904
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
905
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
906
- $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
907
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
908
- (negedge C => (Q : D)) = 1391;
909
- endspecify
910
- `endif
911
- endmodule
912
-
913
- (* abc9_flop, lib_whitebox *)
914
- module SB_DFFNE (
915
- output reg Q,
916
- input C,
917
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
918
- input D
919
- );
920
- `SB_DFF_INIT
921
-
922
- always @(negedge C)
923
- if (E)
924
- Q <= D;
925
- `ifdef ICE40_HX
926
- specify
927
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
928
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
929
- $setup(D, negedge C &&& E, 470 - 449);
930
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
931
- $setup(E, negedge C, 0);
932
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
933
- if (E) (negedge C => (Q : D)) = 540;
934
- endspecify
935
- `endif
936
- `ifdef ICE40_LP
937
- specify
938
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
939
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
940
- $setup(D, negedge C &&& E, 693 - 662);
941
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
942
- $setup(E, negedge C, 0);
943
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
944
- if (E) (negedge C => (Q : D)) = 796;
945
- endspecify
946
- `endif
947
- `ifdef ICE40_U
948
- specify
949
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
950
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
951
- $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
952
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
953
- $setup(E, negedge C, 0);
954
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
955
- if (E) (negedge C => (Q : D)) = 1391;
956
- endspecify
957
- `endif
958
- endmodule
959
-
960
- (* abc9_flop, lib_whitebox *)
961
- module SB_DFFNSR (
962
- output reg Q,
963
- input C, R, D
964
- );
965
- `SB_DFF_INIT
966
-
967
- always @(negedge C)
968
- if (R)
969
- Q <= 0;
970
- else
971
- Q <= D;
972
- `ifdef ICE40_HX
973
- specify
974
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
975
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
976
- $setup(D, negedge C, 470 - 449);
977
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
978
- $setup(R, negedge C, 203);
979
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
980
- if ( R) (negedge C => (Q : 1'b0)) = 540;
981
- if (!R) (negedge C => (Q : D)) = 540;
982
- endspecify
983
- `endif
984
- `ifdef ICE40_LP
985
- specify
986
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
987
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
988
- $setup(D, negedge C, 693 - 662);
989
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
990
- $setup(R, negedge C, 299);
991
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
992
- if ( R) (negedge C => (Q : 1'b0)) = 796;
993
- if (!R) (negedge C => (Q : D)) = 796;
994
- endspecify
995
- `endif
996
- `ifdef ICE40_U
997
- specify
998
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
999
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1000
- $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
1001
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
1002
- $setup(R, negedge C, 530);
1003
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1004
- if ( R) (negedge C => (Q : 1'b0)) = 1391;
1005
- if (!R) (negedge C => (Q : D)) = 1391;
1006
- endspecify
1007
- `endif
1008
- endmodule
1009
-
1010
- (* abc9_flop, lib_whitebox *)
1011
- module SB_DFFNR (
1012
- output reg Q,
1013
- input C, R, D
1014
- );
1015
- `SB_DFF_INIT
1016
-
1017
- always @(negedge C, posedge R)
1018
- if (R)
1019
- Q <= 0;
1020
- else
1021
- Q <= D;
1022
- `ifdef ICE40_HX
1023
- specify
1024
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1025
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1026
- $setup(D, negedge C, 470 - 449);
1027
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
1028
- $setup(negedge R, negedge C, 160);
1029
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
1030
- `ifndef YOSYS
1031
- (posedge R => (Q : 1'b0)) = 599;
1032
- `else
1033
- if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
1034
- // but for facilitating a bypass box, let's pretend it's
1035
- // a simple path
1036
- `endif
1037
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1038
- if (!R) (negedge C => (Q : D)) = 540;
1039
- endspecify
1040
- `endif
1041
- `ifdef ICE40_LP
1042
- specify
1043
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1044
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1045
- $setup(D, negedge C, 693 - 662);
1046
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
1047
- $setup(negedge R, negedge C, 235);
1048
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
1049
- `ifndef YOSYS
1050
- (posedge R => (Q : 1'b0)) = 883;
1051
- `else
1052
- if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
1053
- // but for facilitating a bypass box, let's pretend it's
1054
- // a simple path
1055
- `endif
1056
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1057
- if (!R) (negedge C => (Q : D)) = 796;
1058
- endspecify
1059
- `endif
1060
- `ifdef ICE40_U
1061
- specify
1062
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1063
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1064
- $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
1065
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
1066
- $setup(negedge R, negedge C, 424);
1067
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
1068
- `ifndef YOSYS
1069
- (posedge R => (Q : 1'b0)) = 1589;
1070
- `else
1071
- if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
1072
- // but for facilitating a bypass box, let's pretend it's
1073
- // a simple path
1074
- `endif
1075
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1076
- if (!R) (negedge C => (Q : D)) = 1391;
1077
- endspecify
1078
- `endif
1079
- endmodule
1080
-
1081
- (* abc9_flop, lib_whitebox *)
1082
- module SB_DFFNSS (
1083
- output reg Q,
1084
- input C, S, D
1085
- );
1086
- `SB_DFF_INIT
1087
-
1088
- always @(negedge C)
1089
- if (S)
1090
- Q <= 1;
1091
- else
1092
- Q <= D;
1093
- `ifdef ICE40_HX
1094
- specify
1095
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1096
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1097
- $setup(D, negedge C, 470 - 449);
1098
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1099
- $setup(S, negedge C, 203);
1100
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1101
- if ( S) (negedge C => (Q : 1'b1)) = 540;
1102
- if (!S) (negedge C => (Q : D)) = 540;
1103
- endspecify
1104
- `endif
1105
- `ifdef ICE40_LP
1106
- specify
1107
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1108
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1109
- $setup(D, negedge C, 693 - 662);
1110
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
1111
- $setup(S, negedge C, 299);
1112
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1113
- if ( S) (negedge C => (Q : 1'b1)) = 796;
1114
- if (!S) (negedge C => (Q : D)) = 796;
1115
- endspecify
1116
- `endif
1117
- `ifdef ICE40_U
1118
- specify
1119
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1120
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1121
- $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
1122
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
1123
- $setup(S, negedge C, 530);
1124
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1125
- if ( S) (negedge C => (Q : 1'b1)) = 1391;
1126
- if (!S) (negedge C => (Q : D)) = 1391;
1127
- endspecify
1128
- `endif
1129
- endmodule
1130
-
1131
- (* abc9_box, lib_whitebox *)
1132
- module SB_DFFNS (
1133
- output reg Q,
1134
- input C, S, D
1135
- );
1136
- `SB_DFF_INIT
1137
-
1138
- always @(negedge C, posedge S)
1139
- if (S)
1140
- Q <= 1;
1141
- else
1142
- Q <= D;
1143
- `ifdef ICE40_HX
1144
- specify
1145
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1146
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1147
- $setup(D, negedge C, 470 - 449);
1148
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
1149
- $setup(negedge S, negedge C, 160);
1150
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
1151
- `ifndef YOSYS
1152
- (posedge S => (Q : 1'b1)) = 599;
1153
- `else
1154
- if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
1155
- // but for facilitating a bypass box, let's pretend it's
1156
- // a simple path
1157
- `endif
1158
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1159
- if (!S) (negedge C => (Q : D)) = 540;
1160
- endspecify
1161
- `endif
1162
- `ifdef ICE40_LP
1163
- specify
1164
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1165
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1166
- $setup(D, negedge C, 693 - 662);
1167
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
1168
- $setup(negedge S, negedge C, 235);
1169
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
1170
- `ifndef YOSYS
1171
- (posedge S => (Q : 1'b1)) = 883;
1172
- `else
1173
- if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
1174
- // but for facilitating a bypass box, let's pretend it's
1175
- // a simple path
1176
- `endif
1177
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1178
- if (!S) (negedge C => (Q : D)) = 796;
1179
- endspecify
1180
- `endif
1181
- `ifdef ICE40_U
1182
- specify
1183
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1184
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1185
- $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
1186
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
1187
- $setup(negedge S, negedge C, 424);
1188
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
1189
- `ifndef YOSYS
1190
- (posedge S => (Q : 1'b1)) = 1589;
1191
- `else
1192
- if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
1193
- // but for facilitating a bypass box, let's pretend it's
1194
- // a simple path
1195
- `endif
1196
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1197
- if (!S) (negedge C => (Q : D)) = 1391;
1198
- endspecify
1199
- `endif
1200
- endmodule
1201
-
1202
- (* abc9_flop, lib_whitebox *)
1203
- module SB_DFFNESR (
1204
- output reg Q,
1205
- input C,
1206
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
1207
- input R,
1208
- input D
1209
- );
1210
- `SB_DFF_INIT
1211
-
1212
- always @(negedge C)
1213
- if (E) begin
1214
- if (R)
1215
- Q <= 0;
1216
- else
1217
- Q <= D;
1218
- end
1219
- `ifdef ICE40_HX
1220
- specify
1221
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1222
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1223
- $setup(D, negedge C &&& E && !R, 470 - 449);
1224
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1225
- $setup(E, negedge C, 0);
1226
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
1227
- $setup(R, negedge C &&& E, 203);
1228
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1229
- if (E && R) (negedge C => (Q : 1'b0)) = 540;
1230
- if (E && !R) (negedge C => (Q : D)) = 540;
1231
- endspecify
1232
- `endif
1233
- `ifdef ICE40_LP
1234
- specify
1235
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1236
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1237
- $setup(D, negedge C &&& E && !R, 693 - 662);
1238
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1239
- $setup(E, negedge C, 0);
1240
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
1241
- $setup(R, negedge C &&& E, 299);
1242
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1243
- if (E && R) (negedge C => (Q : 1'b0)) = 796;
1244
- if (E && !R) (negedge C => (Q : D)) = 796;
1245
- endspecify
1246
- `endif
1247
- `ifdef ICE40_U
1248
- specify
1249
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1250
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1251
- $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1252
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1253
- $setup(E, negedge C, 0);
1254
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
1255
- $setup(R, negedge C &&& E, 530);
1256
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1257
- if (E && R) (negedge C => (Q : 1'b0)) = 1391;
1258
- if (E && !R) (negedge C => (Q : D)) = 1391;
1259
- endspecify
1260
- `endif
1261
- endmodule
1262
-
1263
- (* abc9_box, lib_whitebox *)
1264
- module SB_DFFNER (
1265
- output reg Q,
1266
- input C,
1267
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
1268
- input R,
1269
- input D
1270
- );
1271
- `SB_DFF_INIT
1272
-
1273
- always @(negedge C, posedge R)
1274
- if (R)
1275
- Q <= 0;
1276
- else if (E)
1277
- Q <= D;
1278
- `ifdef ICE40_HX
1279
- specify
1280
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1281
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1282
- $setup(D, negedge C &&& E, 470 - 449);
1283
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1284
- $setup(E, negedge C, 0);
1285
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
1286
- $setup(R, negedge C, 2160);
1287
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
1288
- `ifndef YOSYS
1289
- (posedge R => (Q : 1'b0)) = 599;
1290
- `else
1291
- if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
1292
- // but for facilitating a bypass box, let's pretend it's
1293
- // a simple path
1294
- `endif
1295
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1296
- if (E && !R) (negedge C => (Q : D)) = 540;
1297
- endspecify
1298
- `endif
1299
- `ifdef ICE40_LP
1300
- specify
1301
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1302
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1303
- $setup(D, negedge C &&& E, 693 - 662);
1304
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1305
- $setup(E, negedge C, 0);
1306
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
1307
- $setup(R, negedge C, 235);
1308
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
1309
- `ifndef YOSYS
1310
- (posedge R => (Q : 1'b0)) = 883;
1311
- `else
1312
- if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
1313
- // but for facilitating a bypass box, let's pretend it's
1314
- // a simple path
1315
- `endif
1316
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1317
- if (E && !R) (negedge C => (Q : D)) = 796;
1318
- endspecify
1319
- `endif
1320
- `ifdef ICE40_U
1321
- specify
1322
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1323
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1324
- $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1325
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1326
- $setup(E, negedge C, 0);
1327
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
1328
- $setup(negedge R, negedge C, 424);
1329
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
1330
- `ifndef YOSYS
1331
- (posedge R => (Q : 1'b0)) = 1589;
1332
- `else
1333
- if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
1334
- // but for facilitating a bypass box, let's pretend it's
1335
- // a simple path
1336
- `endif
1337
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1338
- if (E && !R) (negedge C => (Q : D)) = 1391;
1339
- endspecify
1340
- `endif
1341
- endmodule
1342
-
1343
- (* abc9_flop, lib_whitebox *)
1344
- module SB_DFFNESS (
1345
- output reg Q,
1346
- input C,
1347
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
1348
- input S,
1349
- input D
1350
- );
1351
- `SB_DFF_INIT
1352
-
1353
- always @(negedge C)
1354
- if (E) begin
1355
- if (S)
1356
- Q <= 1;
1357
- else
1358
- Q <= D;
1359
- end
1360
- `ifdef ICE40_HX
1361
- specify
1362
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1363
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1364
- $setup(D, negedge C &&& E && !S, 470 - 449);
1365
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1366
- $setup(E, negedge C, 0);
1367
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
1368
- $setup(S, negedge C &&& E, 203);
1369
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1370
- if (E && S) (negedge C => (Q : 1'b1)) = 540;
1371
- if (E && !S) (negedge C => (Q : D)) = 540;
1372
- endspecify
1373
- `endif
1374
- `ifdef ICE40_LP
1375
- specify
1376
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1377
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1378
- $setup(D, negedge C &&& E && !S, 693 - 662);
1379
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1380
- $setup(E, negedge C, 0);
1381
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
1382
- $setup(S, negedge C &&& E, 299);
1383
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1384
- if (E && S) (negedge C => (Q : 1'b1)) = 796;
1385
- if (E && !S) (negedge C => (Q : D)) = 796;
1386
- endspecify
1387
- `endif
1388
- `ifdef ICE40_U
1389
- specify
1390
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1391
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1392
- $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1393
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1394
- $setup(E, negedge C, 0);
1395
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
1396
- $setup(S, negedge C &&& E, 530);
1397
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1398
- if (E && S) (negedge C => (Q : 1'b1)) = 1391;
1399
- if (E && !S) (negedge C => (Q : D)) = 1391;
1400
- endspecify
1401
- `endif
1402
- endmodule
1403
-
1404
- (* abc9_box, lib_whitebox *)
1405
- module SB_DFFNES (
1406
- output reg Q,
1407
- input C,
1408
- input E `ICE40_DEFAULT_ASSIGNMENT_1,
1409
- input S,
1410
- input D
1411
- );
1412
- `SB_DFF_INIT
1413
-
1414
- always @(negedge C, posedge S)
1415
- if (S)
1416
- Q <= 1;
1417
- else if (E)
1418
- Q <= D;
1419
- `ifdef ICE40_HX
1420
- specify
1421
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1422
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1423
- $setup(D, negedge C &&& E, 470 - 449);
1424
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1425
- $setup(E, negedge C, 0);
1426
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
1427
- $setup(negedge S, negedge C, 160);
1428
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
1429
- `ifndef YOSYS
1430
- (posedge S => (Q : 1'b1)) = 599;
1431
- `else
1432
- if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
1433
- // but for facilitating a bypass box, let's pretend it's
1434
- // a simple path
1435
- `endif
1436
-
1437
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1438
- if (E && !S) (negedge C => (Q : D)) = 540;
1439
- endspecify
1440
- `endif
1441
- `ifdef ICE40_LP
1442
- specify
1443
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1444
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1445
- $setup(D, negedge C &&& E, 693 - 662);
1446
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1447
- $setup(E, negedge C, 0);
1448
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
1449
- $setup(negedge S, negedge C, 235);
1450
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
1451
- `ifndef YOSYS
1452
- (posedge S => (Q : 1'b1)) = 883;
1453
- `else
1454
- if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
1455
- // but for facilitating a bypass box, let's pretend it's
1456
- // a simple path
1457
- `endif
1458
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1459
- if (E && !S) (negedge C => (Q : D)) = 796;
1460
- endspecify
1461
- `endif
1462
- `ifdef ICE40_U
1463
- specify
1464
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1465
- // minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1466
- $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1467
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1468
- $setup(E, negedge C, 0);
1469
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
1470
- $setup(negedge S, negedge C, 424);
1471
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
1472
- `ifndef YOSYS
1473
- (posedge S => (Q : 1'b1)) = 1589;
1474
- `else
1475
- if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
1476
- // but for facilitating a bypass box, let's pretend it's
1477
- // a simple path
1478
- `endif
1479
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1480
- if (E && !S) (negedge C => (Q : D)) = 1391;
1481
- endspecify
1482
- `endif
1483
- endmodule
1484
-
1485
- // SiliconBlue RAM Cells
1486
-
1487
- module SB_RAM40_4K (
1488
- output [15:0] RDATA,
1489
- input RCLK,
1490
- input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
1491
- input RE `ICE40_DEFAULT_ASSIGNMENT_0,
1492
- input [10:0] RADDR,
1493
- input WCLK,
1494
- input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
1495
- input WE `ICE40_DEFAULT_ASSIGNMENT_0,
1496
- input [10:0] WADDR,
1497
- input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
1498
- input [15:0] WDATA
1499
- );
1500
- // MODE 0: 256 x 16
1501
- // MODE 1: 512 x 8
1502
- // MODE 2: 1024 x 4
1503
- // MODE 3: 2048 x 2
1504
- parameter WRITE_MODE = 0;
1505
- parameter READ_MODE = 0;
1506
-
1507
- parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1508
- parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1509
- parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1510
- parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1511
- parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1512
- parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1513
- parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1514
- parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1515
- parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1516
- parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1517
- parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1518
- parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1519
- parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1520
- parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1521
- parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1522
- parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1523
-
1524
- parameter INIT_FILE = "";
1525
-
1526
- `ifndef BLACKBOX
1527
- wire [15:0] WMASK_I;
1528
- wire [15:0] RMASK_I;
1529
-
1530
- reg [15:0] RDATA_I;
1531
- wire [15:0] WDATA_I;
1532
-
1533
- generate
1534
- case (WRITE_MODE)
1535
- 0: assign WMASK_I = MASK;
1536
-
1537
- 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
1538
- WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
1539
-
1540
- 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
1541
- WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
1542
- WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
1543
- WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
1544
-
1545
- 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
1546
- WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
1547
- WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
1548
- WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
1549
- WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
1550
- WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
1551
- WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
1552
- WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
1553
- endcase
1554
-
1555
- case (READ_MODE)
1556
- 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
1557
-
1558
- 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
1559
- RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
1560
-
1561
- 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
1562
- RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
1563
- RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
1564
- RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
1565
-
1566
- 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
1567
- RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
1568
- RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
1569
- RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
1570
- RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
1571
- RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
1572
- RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
1573
- RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
1574
- endcase
1575
-
1576
- case (WRITE_MODE)
1577
- 0: assign WDATA_I = WDATA;
1578
-
1579
- 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
1580
- WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
1581
- WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
1582
- WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
1583
-
1584
- 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
1585
- WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
1586
- WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
1587
- WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
1588
-
1589
- 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
1590
- WDATA[11], WDATA[11], WDATA[11], WDATA[11],
1591
- WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
1592
- WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
1593
- endcase
1594
-
1595
- case (READ_MODE)
1596
- 0: assign RDATA = RDATA_I;
1597
- 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
1598
- 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
1599
- 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
1600
- 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
1601
- endcase
1602
- endgenerate
1603
-
1604
- integer i;
1605
- reg [15:0] memory [0:255];
1606
-
1607
- initial begin
1608
- if (INIT_FILE != "")
1609
- $readmemh(INIT_FILE, memory);
1610
- else
1611
- for (i=0; i<16; i=i+1) begin
1612
- memory[ 0*16 + i] = INIT_0[16*i +: 16];
1613
- memory[ 1*16 + i] = INIT_1[16*i +: 16];
1614
- memory[ 2*16 + i] = INIT_2[16*i +: 16];
1615
- memory[ 3*16 + i] = INIT_3[16*i +: 16];
1616
- memory[ 4*16 + i] = INIT_4[16*i +: 16];
1617
- memory[ 5*16 + i] = INIT_5[16*i +: 16];
1618
- memory[ 6*16 + i] = INIT_6[16*i +: 16];
1619
- memory[ 7*16 + i] = INIT_7[16*i +: 16];
1620
- memory[ 8*16 + i] = INIT_8[16*i +: 16];
1621
- memory[ 9*16 + i] = INIT_9[16*i +: 16];
1622
- memory[10*16 + i] = INIT_A[16*i +: 16];
1623
- memory[11*16 + i] = INIT_B[16*i +: 16];
1624
- memory[12*16 + i] = INIT_C[16*i +: 16];
1625
- memory[13*16 + i] = INIT_D[16*i +: 16];
1626
- memory[14*16 + i] = INIT_E[16*i +: 16];
1627
- memory[15*16 + i] = INIT_F[16*i +: 16];
1628
- end
1629
- end
1630
-
1631
- always @(posedge WCLK) begin
1632
- if (WE && WCLKE) begin
1633
- if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
1634
- if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
1635
- if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
1636
- if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
1637
- if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
1638
- if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
1639
- if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
1640
- if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
1641
- if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
1642
- if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
1643
- if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
1644
- if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
1645
- if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
1646
- if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
1647
- if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
1648
- if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
1649
- end
1650
- end
1651
-
1652
- always @(posedge RCLK) begin
1653
- if (RE && RCLKE) begin
1654
- RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
1655
- end
1656
- end
1657
- `endif
1658
- `ifdef ICE40_HX
1659
- specify
1660
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
1661
- $setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
1662
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
1663
- $setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
1664
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
1665
- $setup(RCLKE, posedge RCLK, 267);
1666
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
1667
- $setup(RE, posedge RCLK, 98);
1668
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
1669
- $setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
1670
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
1671
- $setup(WCLKE, posedge WCLK, 267);
1672
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
1673
- $setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
1674
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
1675
- $setup(WE, posedge WCLK, 133);
1676
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
1677
- (posedge RCLK *> (RDATA : 16'bx)) = 2146;
1678
- endspecify
1679
- `endif
1680
- `ifdef ICE40_LP
1681
- specify
1682
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
1683
- $setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
1684
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
1685
- $setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
1686
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
1687
- $setup(RCLKE, posedge RCLK, 393);
1688
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
1689
- $setup(RE, posedge RCLK, 145);
1690
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
1691
- $setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
1692
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
1693
- $setup(WCLKE, posedge WCLK, 393);
1694
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
1695
- $setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
1696
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
1697
- $setup(WE, posedge WCLK, 196);
1698
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
1699
- (posedge RCLK *> (RDATA : 16'bx)) = 3163;
1700
- endspecify
1701
- `endif
1702
- `ifdef ICE40_U
1703
- specify
1704
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
1705
- $setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
1706
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
1707
- $setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
1708
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
1709
- $setup(RCLKE, posedge RCLK, 503);
1710
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
1711
- $setup(RE, posedge RCLK, 185);
1712
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
1713
- $setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
1714
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
1715
- $setup(WCLKE, posedge WCLK, 503);
1716
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
1717
- $setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
1718
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
1719
- $setup(WE, posedge WCLK, 252);
1720
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
1721
- (posedge RCLK *> (RDATA : 16'bx)) = 1179;
1722
- endspecify
1723
- `endif
1724
- endmodule
1725
-
1726
- module SB_RAM40_4KNR (
1727
- output [15:0] RDATA,
1728
- input RCLKN,
1729
- input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
1730
- input RE `ICE40_DEFAULT_ASSIGNMENT_0,
1731
- input [10:0] RADDR,
1732
- input WCLK,
1733
- input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
1734
- input WE `ICE40_DEFAULT_ASSIGNMENT_0,
1735
- input [10:0] WADDR,
1736
- input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
1737
- input [15:0] WDATA
1738
- );
1739
- parameter WRITE_MODE = 0;
1740
- parameter READ_MODE = 0;
1741
-
1742
- parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1743
- parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1744
- parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1745
- parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1746
- parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1747
- parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1748
- parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1749
- parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1750
- parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1751
- parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1752
- parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1753
- parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1754
- parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1755
- parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1756
- parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1757
- parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1758
-
1759
- parameter INIT_FILE = "";
1760
-
1761
- SB_RAM40_4K #(
1762
- .WRITE_MODE(WRITE_MODE),
1763
- .READ_MODE (READ_MODE ),
1764
- .INIT_0 (INIT_0 ),
1765
- .INIT_1 (INIT_1 ),
1766
- .INIT_2 (INIT_2 ),
1767
- .INIT_3 (INIT_3 ),
1768
- .INIT_4 (INIT_4 ),
1769
- .INIT_5 (INIT_5 ),
1770
- .INIT_6 (INIT_6 ),
1771
- .INIT_7 (INIT_7 ),
1772
- .INIT_8 (INIT_8 ),
1773
- .INIT_9 (INIT_9 ),
1774
- .INIT_A (INIT_A ),
1775
- .INIT_B (INIT_B ),
1776
- .INIT_C (INIT_C ),
1777
- .INIT_D (INIT_D ),
1778
- .INIT_E (INIT_E ),
1779
- .INIT_F (INIT_F ),
1780
- .INIT_FILE (INIT_FILE )
1781
- ) RAM (
1782
- .RDATA(RDATA),
1783
- .RCLK (~RCLKN),
1784
- .RCLKE(RCLKE),
1785
- .RE (RE ),
1786
- .RADDR(RADDR),
1787
- .WCLK (WCLK ),
1788
- .WCLKE(WCLKE),
1789
- .WE (WE ),
1790
- .WADDR(WADDR),
1791
- .MASK (MASK ),
1792
- .WDATA(WDATA)
1793
- );
1794
- `ifdef ICE40_HX
1795
- specify
1796
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
1797
- $setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
1798
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
1799
- $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
1800
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
1801
- $setup(RCLKE, posedge RCLKN, 267);
1802
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
1803
- $setup(RE, posedge RCLKN, 98);
1804
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
1805
- $setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
1806
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
1807
- $setup(WCLKE, posedge WCLK, 267);
1808
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
1809
- $setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
1810
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
1811
- $setup(WE, posedge WCLK, 133);
1812
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
1813
- (posedge RCLKN *> (RDATA : 16'bx)) = 2146;
1814
- endspecify
1815
- `endif
1816
- `ifdef ICE40_LP
1817
- specify
1818
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
1819
- $setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
1820
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
1821
- $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
1822
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
1823
- $setup(RCLKE, posedge RCLKN, 393);
1824
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
1825
- $setup(RE, posedge RCLKN, 145);
1826
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
1827
- $setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
1828
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
1829
- $setup(WCLKE, posedge WCLK, 393);
1830
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
1831
- $setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
1832
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
1833
- $setup(WE, posedge WCLK, 196);
1834
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
1835
- (posedge RCLKN *> (RDATA : 16'bx)) = 3163;
1836
- endspecify
1837
- `endif
1838
- `ifdef ICE40_U
1839
- specify
1840
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
1841
- $setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
1842
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
1843
- $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
1844
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
1845
- $setup(RCLKE, posedge RCLKN, 503);
1846
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
1847
- $setup(RE, posedge RCLKN, 185);
1848
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
1849
- $setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
1850
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
1851
- $setup(WCLKE, posedge WCLK, 503);
1852
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
1853
- $setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
1854
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
1855
- $setup(WE, posedge WCLK, 252);
1856
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
1857
- (posedge RCLKN *> (RDATA : 16'bx)) = 1179;
1858
- endspecify
1859
- `endif
1860
- endmodule
1861
-
1862
- module SB_RAM40_4KNW (
1863
- output [15:0] RDATA,
1864
- input RCLK,
1865
- input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
1866
- input RE `ICE40_DEFAULT_ASSIGNMENT_0,
1867
- input [10:0] RADDR,
1868
- input WCLKN,
1869
- input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
1870
- input WE `ICE40_DEFAULT_ASSIGNMENT_0,
1871
- input [10:0] WADDR,
1872
- input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
1873
- input [15:0] WDATA
1874
- );
1875
- parameter WRITE_MODE = 0;
1876
- parameter READ_MODE = 0;
1877
-
1878
- parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1879
- parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1880
- parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1881
- parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1882
- parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1883
- parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1884
- parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1885
- parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1886
- parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1887
- parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1888
- parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1889
- parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1890
- parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1891
- parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1892
- parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1893
- parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1894
-
1895
- parameter INIT_FILE = "";
1896
-
1897
- SB_RAM40_4K #(
1898
- .WRITE_MODE(WRITE_MODE),
1899
- .READ_MODE (READ_MODE ),
1900
- .INIT_0 (INIT_0 ),
1901
- .INIT_1 (INIT_1 ),
1902
- .INIT_2 (INIT_2 ),
1903
- .INIT_3 (INIT_3 ),
1904
- .INIT_4 (INIT_4 ),
1905
- .INIT_5 (INIT_5 ),
1906
- .INIT_6 (INIT_6 ),
1907
- .INIT_7 (INIT_7 ),
1908
- .INIT_8 (INIT_8 ),
1909
- .INIT_9 (INIT_9 ),
1910
- .INIT_A (INIT_A ),
1911
- .INIT_B (INIT_B ),
1912
- .INIT_C (INIT_C ),
1913
- .INIT_D (INIT_D ),
1914
- .INIT_E (INIT_E ),
1915
- .INIT_F (INIT_F ),
1916
- .INIT_FILE (INIT_FILE )
1917
- ) RAM (
1918
- .RDATA(RDATA),
1919
- .RCLK (RCLK ),
1920
- .RCLKE(RCLKE),
1921
- .RE (RE ),
1922
- .RADDR(RADDR),
1923
- .WCLK (~WCLKN),
1924
- .WCLKE(WCLKE),
1925
- .WE (WE ),
1926
- .WADDR(WADDR),
1927
- .MASK (MASK ),
1928
- .WDATA(WDATA)
1929
- );
1930
- `ifdef ICE40_HX
1931
- specify
1932
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
1933
- $setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
1934
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
1935
- $setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
1936
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
1937
- $setup(RCLKE, posedge RCLK, 267);
1938
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
1939
- $setup(RE, posedge RCLK, 98);
1940
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
1941
- $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
1942
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
1943
- $setup(WCLKE, posedge WCLKN, 267);
1944
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
1945
- $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
1946
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
1947
- $setup(WE, posedge WCLKN, 133);
1948
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
1949
- (posedge RCLK *> (RDATA : 16'bx)) = 2146;
1950
- endspecify
1951
- `endif
1952
- `ifdef ICE40_LP
1953
- specify
1954
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
1955
- $setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
1956
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
1957
- $setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
1958
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
1959
- $setup(RCLKE, posedge RCLK, 393);
1960
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
1961
- $setup(RE, posedge RCLK, 145);
1962
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
1963
- $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
1964
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
1965
- $setup(WCLKE, posedge WCLKN, 393);
1966
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
1967
- $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
1968
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
1969
- $setup(WE, posedge WCLKN, 196);
1970
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
1971
- (posedge RCLK *> (RDATA : 16'bx)) = 3163;
1972
- endspecify
1973
- `endif
1974
- `ifdef ICE40_U
1975
- specify
1976
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
1977
- $setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
1978
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
1979
- $setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
1980
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
1981
- $setup(RCLKE, posedge RCLK, 503);
1982
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
1983
- $setup(RE, posedge RCLK, 185);
1984
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
1985
- $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
1986
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
1987
- $setup(WCLKE, posedge WCLKN, 503);
1988
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
1989
- $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
1990
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
1991
- $setup(WE, posedge WCLKN, 252);
1992
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
1993
- (posedge RCLK *> (RDATA : 16'bx)) = 1179;
1994
- endspecify
1995
- `endif
1996
- endmodule
1997
-
1998
- module SB_RAM40_4KNRNW (
1999
- output [15:0] RDATA,
2000
- input RCLKN,
2001
- input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
2002
- input RE `ICE40_DEFAULT_ASSIGNMENT_0,
2003
- input [10:0] RADDR,
2004
- input WCLKN,
2005
- input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
2006
- input WE `ICE40_DEFAULT_ASSIGNMENT_0,
2007
- input [10:0] WADDR,
2008
- input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
2009
- input [15:0] WDATA
2010
- );
2011
- parameter WRITE_MODE = 0;
2012
- parameter READ_MODE = 0;
2013
-
2014
- parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2015
- parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2016
- parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2017
- parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2018
- parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2019
- parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2020
- parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2021
- parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2022
- parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2023
- parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2024
- parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2025
- parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2026
- parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2027
- parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2028
- parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2029
- parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2030
-
2031
- parameter INIT_FILE = "";
2032
-
2033
- SB_RAM40_4K #(
2034
- .WRITE_MODE(WRITE_MODE),
2035
- .READ_MODE (READ_MODE ),
2036
- .INIT_0 (INIT_0 ),
2037
- .INIT_1 (INIT_1 ),
2038
- .INIT_2 (INIT_2 ),
2039
- .INIT_3 (INIT_3 ),
2040
- .INIT_4 (INIT_4 ),
2041
- .INIT_5 (INIT_5 ),
2042
- .INIT_6 (INIT_6 ),
2043
- .INIT_7 (INIT_7 ),
2044
- .INIT_8 (INIT_8 ),
2045
- .INIT_9 (INIT_9 ),
2046
- .INIT_A (INIT_A ),
2047
- .INIT_B (INIT_B ),
2048
- .INIT_C (INIT_C ),
2049
- .INIT_D (INIT_D ),
2050
- .INIT_E (INIT_E ),
2051
- .INIT_F (INIT_F ),
2052
- .INIT_FILE (INIT_FILE )
2053
- ) RAM (
2054
- .RDATA(RDATA),
2055
- .RCLK (~RCLKN),
2056
- .RCLKE(RCLKE),
2057
- .RE (RE ),
2058
- .RADDR(RADDR),
2059
- .WCLK (~WCLKN),
2060
- .WCLKE(WCLKE),
2061
- .WE (WE ),
2062
- .WADDR(WADDR),
2063
- .MASK (MASK ),
2064
- .WDATA(WDATA)
2065
- );
2066
- `ifdef ICE40_HX
2067
- specify
2068
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
2069
- $setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
2070
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
2071
- $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
2072
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
2073
- $setup(RCLKE, posedge RCLKN, 267);
2074
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
2075
- $setup(RE, posedge RCLKN, 98);
2076
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
2077
- $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
2078
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
2079
- $setup(WCLKE, posedge WCLKN, 267);
2080
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
2081
- $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
2082
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
2083
- $setup(WE, posedge WCLKN, 133);
2084
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
2085
- (posedge RCLKN *> (RDATA : 16'bx)) = 2146;
2086
- endspecify
2087
- `endif
2088
- `ifdef ICE40_LP
2089
- specify
2090
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
2091
- $setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
2092
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
2093
- $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
2094
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
2095
- $setup(RCLKE, posedge RCLKN, 393);
2096
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
2097
- $setup(RE, posedge RCLKN, 145);
2098
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
2099
- $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
2100
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
2101
- $setup(WCLKE, posedge WCLKN, 393);
2102
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
2103
- $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
2104
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
2105
- $setup(WE, posedge WCLKN, 196);
2106
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
2107
- (posedge RCLKN *> (RDATA : 16'bx)) = 3163;
2108
- endspecify
2109
- `endif
2110
- `ifdef ICE40_U
2111
- specify
2112
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
2113
- $setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
2114
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
2115
- $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
2116
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
2117
- $setup(RCLKE, posedge RCLKN, 503);
2118
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
2119
- $setup(RE, posedge RCLKN, 185);
2120
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
2121
- $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
2122
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
2123
- $setup(WCLKE, posedge WCLKN, 503);
2124
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
2125
- $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
2126
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
2127
- $setup(WE, posedge WCLKN, 252);
2128
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
2129
- (posedge RCLKN *> (RDATA : 16'bx)) = 1179;
2130
- endspecify
2131
- `endif
2132
- endmodule
2133
-
2134
- // Packed IceStorm Logic Cells
2135
-
2136
- module ICESTORM_LC (
2137
- input I0, I1, I2, I3, CIN, CLK, CEN, SR,
2138
- output LO,
2139
- output O,
2140
- output COUT
2141
- );
2142
- parameter [15:0] LUT_INIT = 0;
2143
-
2144
- parameter [0:0] NEG_CLK = 0;
2145
- parameter [0:0] CARRY_ENABLE = 0;
2146
- parameter [0:0] DFF_ENABLE = 0;
2147
- parameter [0:0] SET_NORESET = 0;
2148
- parameter [0:0] ASYNC_SR = 0;
2149
-
2150
- parameter [0:0] CIN_CONST = 0;
2151
- parameter [0:0] CIN_SET = 0;
2152
-
2153
- wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0;
2154
- wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1;
2155
- wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2;
2156
- wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3;
2157
- wire SR_pd = (SR === 1'bz) ? 1'b0 : SR;
2158
- wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN;
2159
-
2160
- wire mux_cin = CIN_CONST ? CIN_SET : CIN;
2161
-
2162
- assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx;
2163
-
2164
- wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0];
2165
- wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0];
2166
- wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0];
2167
- wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0];
2168
-
2169
- assign LO = lut_o;
2170
-
2171
- wire polarized_clk;
2172
- assign polarized_clk = CLK ^ NEG_CLK;
2173
-
2174
- reg o_reg = 1'b0;
2175
- always @(posedge polarized_clk)
2176
- if (CEN_pu)
2177
- o_reg <= SR_pd ? SET_NORESET : lut_o;
2178
-
2179
- reg o_reg_async = 1'b0;
2180
- always @(posedge polarized_clk, posedge SR_pd)
2181
- if (SR_pd)
2182
- o_reg_async <= SET_NORESET;
2183
- else if (CEN_pu)
2184
- o_reg_async <= lut_o;
2185
-
2186
- assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
2187
- `ifdef TIMING
2188
- specify
2189
- (I0 => O) = (0:0:0, 0:0:0);
2190
- (I1 => O) = (0:0:0, 0:0:0);
2191
- (I2 => O) = (0:0:0, 0:0:0);
2192
- (I3 => O) = (0:0:0, 0:0:0);
2193
- (I0 => LO) = (0:0:0, 0:0:0);
2194
- (I1 => LO) = (0:0:0, 0:0:0);
2195
- (I2 => LO) = (0:0:0, 0:0:0);
2196
- (I3 => LO) = (0:0:0, 0:0:0);
2197
- (I1 => COUT) = (0:0:0, 0:0:0);
2198
- (I2 => COUT) = (0:0:0, 0:0:0);
2199
- (CIN => COUT) = (0:0:0, 0:0:0);
2200
- (CLK => O) = (0:0:0, 0:0:0);
2201
- (SR => O) = (0:0:0, 0:0:0);
2202
- $setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0);
2203
- $setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0);
2204
- $setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0);
2205
- $setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0);
2206
- $setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0);
2207
- $setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0);
2208
- $setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0);
2209
- $setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0);
2210
- $setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0);
2211
- $setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0);
2212
- $setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0);
2213
- $setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0);
2214
- $setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0);
2215
- $setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0);
2216
- $setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0);
2217
- $setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0);
2218
- $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
2219
- $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
2220
- $setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0);
2221
- $setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0);
2222
- $setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0);
2223
- $setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0);
2224
- $setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0);
2225
- $setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0);
2226
- endspecify
2227
- `endif
2228
- `ifdef ICE40_HX
2229
- specify
2230
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L79
2231
- (CIN => COUT) = (101:112:126, 85:94:105);
2232
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
2233
- (I0 => O) = (361:399:449, 310:343:386);
2234
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L81
2235
- (I0 => LO) = (293:324:365, 310:343:386);
2236
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L82
2237
- (I1 => COUT) = (209:231:259, 197:218:245);
2238
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L83
2239
- (I1 => O) = (321:355:400, 304:337:379);
2240
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L84
2241
- (I1 => LO) = (259:287:323, 304:337:379);
2242
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L85
2243
- (I2 => COUT) = (186:206:231, 107:118:133);
2244
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L86
2245
- (I2 => O) = (304:337:379, 282:312:351);
2246
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L87
2247
- (I2 => LO) = (254:281:316, 231:256:288);
2248
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L88
2249
- (I3 => O) = (254:281:316, 231:256:288);
2250
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L89
2251
- (I3 => LO) = (214:237:267, 220:243:274);
2252
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
2253
- (posedge CLK => (O : 1'bx)) = (434:480:540, 434:480:540);
2254
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91-L92
2255
- (SR => O) = (482:535:599, 482:533:599);
2256
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
2257
- $setuphold(posedge CLK, posedge I0, 378:418:470, 0:0:0);
2258
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L68
2259
- $setuphold(posedge CLK, negedge I0, 321:355:400, 0:0:0);
2260
- $setuphold(negedge CLK, posedge I0, 378:418:470, 0:0:0);
2261
- $setuphold(negedge CLK, negedge I0, 321:355:400, 0:0:0);
2262
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L75
2263
- $setuphold(posedge CLK, posedge I1, 321:355:400, 0:0:0);
2264
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L69
2265
- $setuphold(posedge CLK, negedge I1, 304:337:379, 0:0:0);
2266
- $setuphold(negedge CLK, posedge I1, 321:355:400, 0:0:0);
2267
- $setuphold(negedge CLK, negedge I1, 304:337:379, 0:0:0);
2268
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L76
2269
- $setuphold(posedge CLK, posedge I2, 299:330:372, 0:0:0);
2270
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L70
2271
- $setuphold(posedge CLK, negedge I2, 259:287:323, 0:0:0);
2272
- $setuphold(negedge CLK, posedge I2, 299:330:372, 0:0:0);
2273
- $setuphold(negedge CLK, negedge I2, 259:287:323, 0:0:0);
2274
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L77
2275
- $setuphold(posedge CLK, posedge I3, 220:243:274, 0:0:0);
2276
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L71
2277
- $setuphold(posedge CLK, negedge I3, 175:183:217, 0:0:0);
2278
- $setuphold(negedge CLK, posedge I3, 220:243:274, 0:0:0);
2279
- $setuphold(negedge CLK, negedge I3, 175:183:217, 0:0:0);
2280
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
2281
- $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
2282
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L67
2283
- $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
2284
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
2285
- $setuphold(posedge CLK, posedge SR, 163:181:203, 0:0:0);
2286
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L72
2287
- $setuphold(posedge CLK, negedge SR, 113:125:140, 0:0:0);
2288
- $setuphold(negedge CLK, posedge SR, 163:181:203, 0:0:0);
2289
- $setuphold(negedge CLK, negedge SR, 113:125:140, 0:0:0);
2290
- endspecify
2291
- `endif
2292
- `ifdef ICE40_LP
2293
- specify
2294
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L79
2295
- (CIN => COUT) = (118:153:186, 98:128:155);
2296
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
2297
- (I0 => O) = (419:545:662, 360:468:569);
2298
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L81
2299
- (I0 => LO) = (340:442:538, 360:468:569);
2300
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L82
2301
- (I1 => COUT) = (242:315:382, 229:298:362);
2302
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L83
2303
- (I1 => O) = (372:485:589, 353:459:558);
2304
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L84
2305
- (I1 => LO) = (301:391:475, 353:459:558);
2306
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L85
2307
- (I2 => COUT) = (216:281:341, 124:162:196);
2308
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
2309
- (I2 => O) = (353:459:558, 327:425:517);
2310
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L87
2311
- (I2 => LO) = (288:374:455, 321:417:507);
2312
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L88
2313
- (I3 => O) = (294:383:465, 268:349:424);
2314
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L89
2315
- (I3 => LO) = (249:323:393, 255:332:403);
2316
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
2317
- (posedge CLK => (O : 1'bx)) = (504:655:796, 504:655:796);
2318
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91-L92
2319
- (SR => O) = (559:726:883, 559:726:883);
2320
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
2321
- $setuphold(posedge CLK, posedge I0, 438:570:693, 0:0:0);
2322
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L68
2323
- $setuphold(posedge CLK, negedge I0, 373:485:589, 0:0:0);
2324
- $setuphold(negedge CLK, posedge I0, 438:570:693, 0:0:0);
2325
- $setuphold(negedge CLK, negedge I0, 373:485:589, 0:0:0);
2326
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L75
2327
- $setuphold(posedge CLK, posedge I1, 373:485:589, 0:0:0);
2328
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L69
2329
- $setuphold(posedge CLK, negedge I1, 353:459:558, 0:0:0);
2330
- $setuphold(negedge CLK, posedge I1, 373:485:589, 0:0:0);
2331
- $setuphold(negedge CLK, negedge I1, 353:459:558, 0:0:0);
2332
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L76
2333
- $setuphold(posedge CLK, posedge I2, 347:451:548, 0:0:0);
2334
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L70
2335
- $setuphold(posedge CLK, negedge I2, 301:391:475, 0:0:0);
2336
- $setuphold(negedge CLK, posedge I2, 347:451:548, 0:0:0);
2337
- $setuphold(negedge CLK, negedge I2, 301:391:475, 0:0:0);
2338
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L77
2339
- $setuphold(posedge CLK, posedge I3, 255:332:403, 0:0:0);
2340
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L71
2341
- $setuphold(posedge CLK, negedge I3, 203:264:320, 0:0:0);
2342
- $setuphold(negedge CLK, posedge I3, 255:332:403, 0:0:0);
2343
- $setuphold(negedge CLK, negedge I3, 203:264:320, 0:0:0);
2344
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
2345
- $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
2346
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L67
2347
- $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
2348
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
2349
- $setuphold(posedge CLK, posedge SR, 190:247:300, 0:0:0);
2350
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L72
2351
- $setuphold(posedge CLK, negedge SR, 131:170:207, 0:0:0);
2352
- $setuphold(negedge CLK, posedge SR, 190:247:300, 0:0:0);
2353
- $setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
2354
- endspecify
2355
- `endif
2356
- `ifdef ICE40_U
2357
- specify
2358
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L91
2359
- (CIN => COUT) = (103:181:278, 103:181:278);
2360
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L92
2361
- (I0 => O) = (462:808:1255, 477:834:1285);
2362
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L93
2363
- (I0 => LO) = (315:550:848, 334:585:901);
2364
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L94
2365
- (I1 => COUT) = (251:438:675, 246:430:662);
2366
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L95
2367
- (I1 => O) = (438:765:1179, 457:799:1232);
2368
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L96
2369
- (I1 => LO) = (275:481:742, 329:576:887);
2370
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L97
2371
- (I2 => COUT) = (226:395:609, 133:232:358);
2372
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L98
2373
- (I2 => O) = (438:765:1179, 447:782:1205);
2374
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L99
2375
- (I2 => LO) = (261:456:702, 290:507:781);
2376
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L100
2377
- (I3 => O) = (320:559:861, 226:370:874);
2378
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L101
2379
- (I3 => LO) = (216:378:583, 226:395:609);
2380
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
2381
- (posedge CLK => (O : 1'bx)) = (516:903:1391, 516:903:1391);
2382
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103-104
2383
- (SR => O) = (420:734:1131, 590:1032:1589);
2384
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
2385
- $setuphold(posedge CLK, posedge I0, 457:799:1232, 0:0:0);
2386
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L80
2387
- $setuphold(posedge CLK, negedge I0, 393:688:1060, 0:0:0);
2388
- $setuphold(negedge CLK, posedge I0, 457:799:1232, 0:0:0);
2389
- $setuphold(negedge CLK, negedge I0, 393:688:1060, 0:0:0);
2390
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L87
2391
- $setuphold(posedge CLK, posedge I1, 393:688:1060, 0:0:0);
2392
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L81
2393
- $setuphold(posedge CLK, negedge I1, 373:653:1007, 0:0:0);
2394
- $setuphold(negedge CLK, posedge I1, 393:688:1060, 0:0:0);
2395
- $setuphold(negedge CLK, negedge I1, 373:653:1007, 0:0:0);
2396
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L88
2397
- $setuphold(posedge CLK, posedge I2, 364:636:980, 0:0:0);
2398
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L82
2399
- $setuphold(posedge CLK, negedge I2, 320:559:861, 0:0:0);
2400
- $setuphold(negedge CLK, posedge I2, 364:636:980, 0:0:0);
2401
- $setuphold(negedge CLK, negedge I2, 320:559:861, 0:0:0);
2402
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L89
2403
- $setuphold(posedge CLK, posedge I3, 279:473:728, 0:0:0);
2404
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L83
2405
- $setuphold(posedge CLK, negedge I3, 216:378:583, 0:0:0);
2406
- $setuphold(negedge CLK, posedge I3, 279:473:728, 0:0:0);
2407
- $setuphold(negedge CLK, negedge I3, 216:378:583, 0:0:0);
2408
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L85
2409
- $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
2410
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L79
2411
- $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
2412
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
2413
- $setuphold(posedge CLK, posedge SR, 197:344:530, 0:0:0);
2414
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L84
2415
- $setuphold(posedge CLK, negedge SR, 143:249:384, 0:0:0);
2416
- $setuphold(negedge CLK, posedge SR, 197:344:530, 0:0:0);
2417
- $setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
2418
- endspecify
2419
- `endif
2420
- endmodule
2421
-
2422
- // SiliconBlue PLL Cells
2423
-
2424
- (* blackbox *)
2425
- module SB_PLL40_CORE (
2426
- input REFERENCECLK,
2427
- output PLLOUTCORE,
2428
- output PLLOUTGLOBAL,
2429
- input EXTFEEDBACK,
2430
- input [7:0] DYNAMICDELAY,
2431
- output LOCK,
2432
- input BYPASS,
2433
- input RESETB,
2434
- input LATCHINPUTVALUE,
2435
- output SDO,
2436
- input SDI,
2437
- input SCLK
2438
- );
2439
- parameter FEEDBACK_PATH = "SIMPLE";
2440
- parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2441
- parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2442
- parameter SHIFTREG_DIV_MODE = 1'b0;
2443
- parameter FDA_FEEDBACK = 4'b0000;
2444
- parameter FDA_RELATIVE = 4'b0000;
2445
- parameter PLLOUT_SELECT = "GENCLK";
2446
- parameter DIVR = 4'b0000;
2447
- parameter DIVF = 7'b0000000;
2448
- parameter DIVQ = 3'b000;
2449
- parameter FILTER_RANGE = 3'b000;
2450
- parameter ENABLE_ICEGATE = 1'b0;
2451
- parameter TEST_MODE = 1'b0;
2452
- parameter EXTERNAL_DIVIDE_FACTOR = 1;
2453
- endmodule
2454
-
2455
- (* blackbox *)
2456
- module SB_PLL40_PAD (
2457
- input PACKAGEPIN,
2458
- output PLLOUTCORE,
2459
- output PLLOUTGLOBAL,
2460
- input EXTFEEDBACK,
2461
- input [7:0] DYNAMICDELAY,
2462
- output LOCK,
2463
- input BYPASS,
2464
- input RESETB,
2465
- input LATCHINPUTVALUE,
2466
- output SDO,
2467
- input SDI,
2468
- input SCLK
2469
- );
2470
- parameter FEEDBACK_PATH = "SIMPLE";
2471
- parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2472
- parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2473
- parameter SHIFTREG_DIV_MODE = 1'b0;
2474
- parameter FDA_FEEDBACK = 4'b0000;
2475
- parameter FDA_RELATIVE = 4'b0000;
2476
- parameter PLLOUT_SELECT = "GENCLK";
2477
- parameter DIVR = 4'b0000;
2478
- parameter DIVF = 7'b0000000;
2479
- parameter DIVQ = 3'b000;
2480
- parameter FILTER_RANGE = 3'b000;
2481
- parameter ENABLE_ICEGATE = 1'b0;
2482
- parameter TEST_MODE = 1'b0;
2483
- parameter EXTERNAL_DIVIDE_FACTOR = 1;
2484
- endmodule
2485
-
2486
- (* blackbox *)
2487
- module SB_PLL40_2_PAD (
2488
- input PACKAGEPIN,
2489
- output PLLOUTCOREA,
2490
- output PLLOUTGLOBALA,
2491
- output PLLOUTCOREB,
2492
- output PLLOUTGLOBALB,
2493
- input EXTFEEDBACK,
2494
- input [7:0] DYNAMICDELAY,
2495
- output LOCK,
2496
- input BYPASS,
2497
- input RESETB,
2498
- input LATCHINPUTVALUE,
2499
- output SDO,
2500
- input SDI,
2501
- input SCLK
2502
- );
2503
- parameter FEEDBACK_PATH = "SIMPLE";
2504
- parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2505
- parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2506
- parameter SHIFTREG_DIV_MODE = 1'b0;
2507
- parameter FDA_FEEDBACK = 4'b0000;
2508
- parameter FDA_RELATIVE = 4'b0000;
2509
- parameter PLLOUT_SELECT_PORTB = "GENCLK";
2510
- parameter DIVR = 4'b0000;
2511
- parameter DIVF = 7'b0000000;
2512
- parameter DIVQ = 3'b000;
2513
- parameter FILTER_RANGE = 3'b000;
2514
- parameter ENABLE_ICEGATE_PORTA = 1'b0;
2515
- parameter ENABLE_ICEGATE_PORTB = 1'b0;
2516
- parameter TEST_MODE = 1'b0;
2517
- parameter EXTERNAL_DIVIDE_FACTOR = 1;
2518
- endmodule
2519
-
2520
- (* blackbox *)
2521
- module SB_PLL40_2F_CORE (
2522
- input REFERENCECLK,
2523
- output PLLOUTCOREA,
2524
- output PLLOUTGLOBALA,
2525
- output PLLOUTCOREB,
2526
- output PLLOUTGLOBALB,
2527
- input EXTFEEDBACK,
2528
- input [7:0] DYNAMICDELAY,
2529
- output LOCK,
2530
- input BYPASS,
2531
- input RESETB,
2532
- input LATCHINPUTVALUE,
2533
- output SDO,
2534
- input SDI,
2535
- input SCLK
2536
- );
2537
- parameter FEEDBACK_PATH = "SIMPLE";
2538
- parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2539
- parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2540
- parameter SHIFTREG_DIV_MODE = 1'b0;
2541
- parameter FDA_FEEDBACK = 4'b0000;
2542
- parameter FDA_RELATIVE = 4'b0000;
2543
- parameter PLLOUT_SELECT_PORTA = "GENCLK";
2544
- parameter PLLOUT_SELECT_PORTB = "GENCLK";
2545
- parameter DIVR = 4'b0000;
2546
- parameter DIVF = 7'b0000000;
2547
- parameter DIVQ = 3'b000;
2548
- parameter FILTER_RANGE = 3'b000;
2549
- parameter ENABLE_ICEGATE_PORTA = 1'b0;
2550
- parameter ENABLE_ICEGATE_PORTB = 1'b0;
2551
- parameter TEST_MODE = 1'b0;
2552
- parameter EXTERNAL_DIVIDE_FACTOR = 1;
2553
- endmodule
2554
-
2555
- (* blackbox *)
2556
- module SB_PLL40_2F_PAD (
2557
- input PACKAGEPIN,
2558
- output PLLOUTCOREA,
2559
- output PLLOUTGLOBALA,
2560
- output PLLOUTCOREB,
2561
- output PLLOUTGLOBALB,
2562
- input EXTFEEDBACK,
2563
- input [7:0] DYNAMICDELAY,
2564
- output LOCK,
2565
- input BYPASS,
2566
- input RESETB,
2567
- input LATCHINPUTVALUE,
2568
- output SDO,
2569
- input SDI,
2570
- input SCLK
2571
- );
2572
- parameter FEEDBACK_PATH = "SIMPLE";
2573
- parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2574
- parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2575
- parameter SHIFTREG_DIV_MODE = 2'b00;
2576
- parameter FDA_FEEDBACK = 4'b0000;
2577
- parameter FDA_RELATIVE = 4'b0000;
2578
- parameter PLLOUT_SELECT_PORTA = "GENCLK";
2579
- parameter PLLOUT_SELECT_PORTB = "GENCLK";
2580
- parameter DIVR = 4'b0000;
2581
- parameter DIVF = 7'b0000000;
2582
- parameter DIVQ = 3'b000;
2583
- parameter FILTER_RANGE = 3'b000;
2584
- parameter ENABLE_ICEGATE_PORTA = 1'b0;
2585
- parameter ENABLE_ICEGATE_PORTB = 1'b0;
2586
- parameter TEST_MODE = 1'b0;
2587
- parameter EXTERNAL_DIVIDE_FACTOR = 1;
2588
- endmodule
2589
-
2590
- // SiliconBlue Device Configuration Cells
2591
-
2592
- (* blackbox, keep *)
2593
- module SB_WARMBOOT (
2594
- input BOOT,
2595
- input S1,
2596
- input S0
2597
- );
2598
- endmodule
2599
-
2600
- module SB_SPRAM256KA (
2601
- input [13:0] ADDRESS,
2602
- input [15:0] DATAIN,
2603
- input [3:0] MASKWREN,
2604
- input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
2605
- output reg [15:0] DATAOUT
2606
- );
2607
- `ifndef BLACKBOX
2608
- `ifndef EQUIV
2609
- reg [15:0] mem [0:16383];
2610
- wire off = SLEEP || !POWEROFF;
2611
- integer i;
2612
-
2613
- always @(negedge POWEROFF) begin
2614
- for (i = 0; i <= 16383; i = i+1)
2615
- mem[i] = 16'bx;
2616
- end
2617
-
2618
- always @(posedge CLOCK, posedge off) begin
2619
- if (off) begin
2620
- DATAOUT <= 0;
2621
- end else
2622
- if (STANDBY) begin
2623
- DATAOUT <= 16'bx;
2624
- end else
2625
- if (CHIPSELECT) begin
2626
- if (!WREN) begin
2627
- DATAOUT <= mem[ADDRESS];
2628
- end else begin
2629
- if (MASKWREN[0]) mem[ADDRESS][ 3: 0] <= DATAIN[ 3: 0];
2630
- if (MASKWREN[1]) mem[ADDRESS][ 7: 4] <= DATAIN[ 7: 4];
2631
- if (MASKWREN[2]) mem[ADDRESS][11: 8] <= DATAIN[11: 8];
2632
- if (MASKWREN[3]) mem[ADDRESS][15:12] <= DATAIN[15:12];
2633
- DATAOUT <= 16'bx;
2634
- end
2635
- end
2636
- end
2637
- `endif
2638
- `endif
2639
- `ifdef ICE40_U
2640
- specify
2641
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13169-L13182
2642
- $setup(posedge ADDRESS, posedge CLOCK, 268);
2643
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13183
2644
- $setup(CHIPSELECT, posedge CLOCK, 404);
2645
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13184-L13199
2646
- $setup(DATAIN, posedge CLOCK, 143);
2647
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13200-L13203
2648
- $setup(MASKWREN, posedge CLOCK, 143);
2649
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
2650
- //$setup(negedge SLEEP, posedge CLOCK, 41505);
2651
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
2652
- //$setup(negedge STANDBY, posedge CLOCK, 1715);
2653
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206
2654
- $setup(WREN, posedge CLOCK, 289);
2655
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222
2656
- (posedge CLOCK *> (DATAOUT : 16'bx)) = 1821;
2657
- // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238
2658
- (posedge SLEEP *> (DATAOUT : 16'b0)) = 1099;
2659
- endspecify
2660
- `endif
2661
- endmodule
2662
-
2663
- (* blackbox *)
2664
- module SB_HFOSC(
2665
- input TRIM0,
2666
- input TRIM1,
2667
- input TRIM2,
2668
- input TRIM3,
2669
- input TRIM4,
2670
- input TRIM5,
2671
- input TRIM6,
2672
- input TRIM7,
2673
- input TRIM8,
2674
- input TRIM9,
2675
- input CLKHFPU,
2676
- input CLKHFEN,
2677
- output CLKHF
2678
- );
2679
- parameter TRIM_EN = "0b0";
2680
- parameter CLKHF_DIV = "0b00";
2681
- endmodule
2682
-
2683
- (* blackbox *)
2684
- module SB_LFOSC(
2685
- input CLKLFPU,
2686
- input CLKLFEN,
2687
- output CLKLF
2688
- );
2689
- endmodule
2690
-
2691
- (* blackbox *)
2692
- module SB_RGBA_DRV(
2693
- input CURREN,
2694
- input RGBLEDEN,
2695
- input RGB0PWM,
2696
- input RGB1PWM,
2697
- input RGB2PWM,
2698
- output RGB0,
2699
- output RGB1,
2700
- output RGB2
2701
- );
2702
- parameter CURRENT_MODE = "0b0";
2703
- parameter RGB0_CURRENT = "0b000000";
2704
- parameter RGB1_CURRENT = "0b000000";
2705
- parameter RGB2_CURRENT = "0b000000";
2706
- endmodule
2707
-
2708
- (* blackbox *)
2709
- module SB_LED_DRV_CUR(
2710
- input EN,
2711
- output LEDPU
2712
- );
2713
- endmodule
2714
-
2715
- (* blackbox *)
2716
- module SB_RGB_DRV(
2717
- input RGBLEDEN,
2718
- input RGB0PWM,
2719
- input RGB1PWM,
2720
- input RGB2PWM,
2721
- input RGBPU,
2722
- output RGB0,
2723
- output RGB1,
2724
- output RGB2
2725
- );
2726
- parameter CURRENT_MODE = "0b0";
2727
- parameter RGB0_CURRENT = "0b000000";
2728
- parameter RGB1_CURRENT = "0b000000";
2729
- parameter RGB2_CURRENT = "0b000000";
2730
- endmodule
2731
-
2732
- (* blackbox *)
2733
- module SB_I2C(
2734
- input SBCLKI,
2735
- input SBRWI,
2736
- input SBSTBI,
2737
- input SBADRI7,
2738
- input SBADRI6,
2739
- input SBADRI5,
2740
- input SBADRI4,
2741
- input SBADRI3,
2742
- input SBADRI2,
2743
- input SBADRI1,
2744
- input SBADRI0,
2745
- input SBDATI7,
2746
- input SBDATI6,
2747
- input SBDATI5,
2748
- input SBDATI4,
2749
- input SBDATI3,
2750
- input SBDATI2,
2751
- input SBDATI1,
2752
- input SBDATI0,
2753
- input SCLI,
2754
- input SDAI,
2755
- output SBDATO7,
2756
- output SBDATO6,
2757
- output SBDATO5,
2758
- output SBDATO4,
2759
- output SBDATO3,
2760
- output SBDATO2,
2761
- output SBDATO1,
2762
- output SBDATO0,
2763
- output SBACKO,
2764
- output I2CIRQ,
2765
- output I2CWKUP,
2766
- output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
2767
- output SCLOE,
2768
- output SDAO,
2769
- output SDAOE
2770
- );
2771
- parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
2772
- parameter BUS_ADDR74 = "0b0001";
2773
- endmodule
2774
-
2775
- (* blackbox *)
2776
- module SB_SPI (
2777
- input SBCLKI,
2778
- input SBRWI,
2779
- input SBSTBI,
2780
- input SBADRI7,
2781
- input SBADRI6,
2782
- input SBADRI5,
2783
- input SBADRI4,
2784
- input SBADRI3,
2785
- input SBADRI2,
2786
- input SBADRI1,
2787
- input SBADRI0,
2788
- input SBDATI7,
2789
- input SBDATI6,
2790
- input SBDATI5,
2791
- input SBDATI4,
2792
- input SBDATI3,
2793
- input SBDATI2,
2794
- input SBDATI1,
2795
- input SBDATI0,
2796
- input MI,
2797
- input SI,
2798
- input SCKI,
2799
- input SCSNI,
2800
- output SBDATO7,
2801
- output SBDATO6,
2802
- output SBDATO5,
2803
- output SBDATO4,
2804
- output SBDATO3,
2805
- output SBDATO2,
2806
- output SBDATO1,
2807
- output SBDATO0,
2808
- output SBACKO,
2809
- output SPIIRQ,
2810
- output SPIWKUP,
2811
- output SO,
2812
- output SOE,
2813
- output MO,
2814
- output MOE,
2815
- output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
2816
- output SCKOE,
2817
- output MCSNO3,
2818
- output MCSNO2,
2819
- output MCSNO1,
2820
- output MCSNO0,
2821
- output MCSNOE3,
2822
- output MCSNOE2,
2823
- output MCSNOE1,
2824
- output MCSNOE0
2825
- );
2826
- parameter BUS_ADDR74 = "0b0000";
2827
- endmodule
2828
-
2829
- (* blackbox *)
2830
- module SB_LEDDA_IP(
2831
- input LEDDCS,
2832
- input LEDDCLK,
2833
- input LEDDDAT7,
2834
- input LEDDDAT6,
2835
- input LEDDDAT5,
2836
- input LEDDDAT4,
2837
- input LEDDDAT3,
2838
- input LEDDDAT2,
2839
- input LEDDDAT1,
2840
- input LEDDDAT0,
2841
- input LEDDADDR3,
2842
- input LEDDADDR2,
2843
- input LEDDADDR1,
2844
- input LEDDADDR0,
2845
- input LEDDDEN,
2846
- input LEDDEXE,
2847
- input LEDDRST,
2848
- output PWMOUT0,
2849
- output PWMOUT1,
2850
- output PWMOUT2,
2851
- output LEDDON
2852
- );
2853
- endmodule
2854
-
2855
- (* blackbox *)
2856
- module SB_FILTER_50NS(
2857
- input FILTERIN,
2858
- output FILTEROUT
2859
- );
2860
- endmodule
2861
-
2862
- module SB_IO_I3C (
2863
- inout PACKAGE_PIN,
2864
- input LATCH_INPUT_VALUE,
2865
- input CLOCK_ENABLE,
2866
- input INPUT_CLK,
2867
- input OUTPUT_CLK,
2868
- input OUTPUT_ENABLE,
2869
- input D_OUT_0,
2870
- input D_OUT_1,
2871
- output D_IN_0,
2872
- output D_IN_1,
2873
- input PU_ENB,
2874
- input WEAK_PU_ENB
2875
- );
2876
- parameter [5:0] PIN_TYPE = 6'b000000;
2877
- parameter [0:0] PULLUP = 1'b0;
2878
- parameter [0:0] WEAK_PULLUP = 1'b0;
2879
- parameter [0:0] NEG_TRIGGER = 1'b0;
2880
- parameter IO_STANDARD = "SB_LVCMOS";
2881
-
2882
- `ifndef BLACKBOX
2883
- reg dout, din_0, din_1;
2884
- reg din_q_0, din_q_1;
2885
- reg dout_q_0, dout_q_1;
2886
- reg outena_q;
2887
-
2888
- generate if (!NEG_TRIGGER) begin
2889
- always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
2890
- always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
2891
- always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
2892
- always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
2893
- always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
2894
- end else begin
2895
- always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
2896
- always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
2897
- always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
2898
- always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
2899
- always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
2900
- end endgenerate
2901
-
2902
- always @* begin
2903
- if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
2904
- din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
2905
- din_1 = din_q_1;
2906
- end
2907
-
2908
- // work around simulation glitches on dout in DDR mode
2909
- reg outclk_delayed_1;
2910
- reg outclk_delayed_2;
2911
- always @* outclk_delayed_1 <= OUTPUT_CLK;
2912
- always @* outclk_delayed_2 <= outclk_delayed_1;
2913
-
2914
- always @* begin
2915
- if (PIN_TYPE[3])
2916
- dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
2917
- else
2918
- dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
2919
- end
2920
-
2921
- assign D_IN_0 = din_0, D_IN_1 = din_1;
2922
-
2923
- generate
2924
- if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
2925
- if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
2926
- if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
2927
- endgenerate
2928
- `endif
2929
- endmodule
2930
-
2931
- module SB_IO_OD (
2932
- inout PACKAGEPIN,
2933
- input LATCHINPUTVALUE,
2934
- input CLOCKENABLE,
2935
- input INPUTCLK,
2936
- input OUTPUTCLK,
2937
- input OUTPUTENABLE,
2938
- input DOUT1,
2939
- input DOUT0,
2940
- output DIN1,
2941
- output DIN0
2942
- );
2943
- parameter [5:0] PIN_TYPE = 6'b000000;
2944
- parameter [0:0] NEG_TRIGGER = 1'b0;
2945
-
2946
- `ifndef BLACKBOX
2947
- reg dout, din_0, din_1;
2948
- reg din_q_0, din_q_1;
2949
- reg dout_q_0, dout_q_1;
2950
- reg outena_q;
2951
-
2952
- generate if (!NEG_TRIGGER) begin
2953
- always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
2954
- always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
2955
- always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
2956
- always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
2957
- always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
2958
- end else begin
2959
- always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
2960
- always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
2961
- always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
2962
- always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
2963
- always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
2964
- end endgenerate
2965
-
2966
- always @* begin
2967
- if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
2968
- din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
2969
- din_1 = din_q_1;
2970
- end
2971
-
2972
- // work around simulation glitches on dout in DDR mode
2973
- reg outclk_delayed_1;
2974
- reg outclk_delayed_2;
2975
- always @* outclk_delayed_1 <= OUTPUTCLK;
2976
- always @* outclk_delayed_2 <= outclk_delayed_1;
2977
-
2978
- always @* begin
2979
- if (PIN_TYPE[3])
2980
- dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
2981
- else
2982
- dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
2983
- end
2984
-
2985
- assign DIN0 = din_0, DIN1 = din_1;
2986
-
2987
- generate
2988
- if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
2989
- if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
2990
- if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
2991
- endgenerate
2992
- `endif
2993
- endmodule
2994
-
2995
- //(* abc9_box, lib_whitebox *) // TODO
2996
- module SB_MAC16 (
2997
- input CLK, CE,
2998
- input [15:0] C, A, B, D,
2999
- input AHOLD, BHOLD, CHOLD, DHOLD,
3000
- input IRSTTOP, IRSTBOT,
3001
- input ORSTTOP, ORSTBOT,
3002
- input OLOADTOP, OLOADBOT,
3003
- input ADDSUBTOP, ADDSUBBOT,
3004
- input OHOLDTOP, OHOLDBOT,
3005
- input CI, ACCUMCI, SIGNEXTIN,
3006
- output [31:0] O,
3007
- output CO, ACCUMCO, SIGNEXTOUT
3008
- );
3009
- parameter [0:0] NEG_TRIGGER = 0;
3010
- parameter [0:0] C_REG = 0;
3011
- parameter [0:0] A_REG = 0;
3012
- parameter [0:0] B_REG = 0;
3013
- parameter [0:0] D_REG = 0;
3014
- parameter [0:0] TOP_8x8_MULT_REG = 0;
3015
- parameter [0:0] BOT_8x8_MULT_REG = 0;
3016
- parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
3017
- parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
3018
- parameter [1:0] TOPOUTPUT_SELECT = 0;
3019
- parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
3020
- parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
3021
- parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
3022
- parameter [1:0] BOTOUTPUT_SELECT = 0;
3023
- parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
3024
- parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
3025
- parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
3026
- parameter [0:0] MODE_8x8 = 0;
3027
- parameter [0:0] A_SIGNED = 0;
3028
- parameter [0:0] B_SIGNED = 0;
3029
-
3030
- wire clock = CLK ^ NEG_TRIGGER;
3031
-
3032
- // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
3033
- // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
3034
- // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
3035
- wire [15:0] iA, iB, iC, iD;
3036
- wire [15:0] iF, iJ, iK, iG;
3037
- wire [31:0] iL, iH;
3038
- wire [15:0] iW, iX, iP, iQ;
3039
- wire [15:0] iY, iZ, iR, iS;
3040
- wire HCI, LCI, LCO;
3041
-
3042
- // Regs C and A
3043
- reg [15:0] rC, rA;
3044
- always @(posedge clock, posedge IRSTTOP) begin
3045
- if (IRSTTOP) begin
3046
- rC <= 0;
3047
- rA <= 0;
3048
- end else if (CE) begin
3049
- if (!CHOLD) rC <= C;
3050
- if (!AHOLD) rA <= A;
3051
- end
3052
- end
3053
- assign iC = C_REG ? rC : C;
3054
- assign iA = A_REG ? rA : A;
3055
-
3056
- // Regs B and D
3057
- reg [15:0] rB, rD;
3058
- always @(posedge clock, posedge IRSTBOT) begin
3059
- if (IRSTBOT) begin
3060
- rB <= 0;
3061
- rD <= 0;
3062
- end else if (CE) begin
3063
- if (!BHOLD) rB <= B;
3064
- if (!DHOLD) rD <= D;
3065
- end
3066
- end
3067
- assign iB = B_REG ? rB : B;
3068
- assign iD = D_REG ? rD : D;
3069
-
3070
- // Multiplier Stage
3071
- wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
3072
- wire [15:0] Ah, Al, Bh, Bl;
3073
- assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
3074
- assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
3075
- assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
3076
- assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
3077
- assign p_Ah_Bh = Ah * Bh; // F
3078
- assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
3079
- assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
3080
- assign p_Al_Bl = Al * Bl; // G
3081
-
3082
- // Regs F and J
3083
- reg [15:0] rF, rJ;
3084
- always @(posedge clock, posedge IRSTTOP) begin
3085
- if (IRSTTOP) begin
3086
- rF <= 0;
3087
- rJ <= 0;
3088
- end else if (CE) begin
3089
- rF <= p_Ah_Bh;
3090
- if (!MODE_8x8) rJ <= p_Al_Bh;
3091
- end
3092
- end
3093
- assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
3094
- assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
3095
-
3096
- // Regs K and G
3097
- reg [15:0] rK, rG;
3098
- always @(posedge clock, posedge IRSTBOT) begin
3099
- if (IRSTBOT) begin
3100
- rK <= 0;
3101
- rG <= 0;
3102
- end else if (CE) begin
3103
- if (!MODE_8x8) rK <= p_Ah_Bl;
3104
- rG <= p_Al_Bl;
3105
- end
3106
- end
3107
- assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
3108
- assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
3109
-
3110
- // Adder Stage
3111
- wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
3112
- wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
3113
- assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
3114
-
3115
- // Reg H
3116
- reg [31:0] rH;
3117
- always @(posedge clock, posedge IRSTBOT) begin
3118
- if (IRSTBOT) begin
3119
- rH <= 0;
3120
- end else if (CE) begin
3121
- if (!MODE_8x8) rH <= iL;
3122
- end
3123
- end
3124
- assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
3125
-
3126
- // Hi Output Stage
3127
- wire [15:0] XW, Oh;
3128
- reg [15:0] rQ;
3129
- assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
3130
- assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
3131
- assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
3132
- assign CO = ACCUMCO ^ ADDSUBTOP;
3133
- assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
3134
- always @(posedge clock, posedge ORSTTOP) begin
3135
- if (ORSTTOP) begin
3136
- rQ <= 0;
3137
- end else if (CE) begin
3138
- if (!OHOLDTOP) rQ <= iP;
3139
- end
3140
- end
3141
- assign iQ = rQ;
3142
- assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
3143
- assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
3144
- assign SIGNEXTOUT = iX[15];
3145
-
3146
- // Lo Output Stage
3147
- wire [15:0] YZ, Ol;
3148
- reg [15:0] rS;
3149
- assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
3150
- assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
3151
- assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
3152
- assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
3153
- always @(posedge clock, posedge ORSTBOT) begin
3154
- if (ORSTBOT) begin
3155
- rS <= 0;
3156
- end else if (CE) begin
3157
- if (!OHOLDBOT) rS <= iR;
3158
- end
3159
- end
3160
- assign iS = rS;
3161
- assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
3162
- assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
3163
- assign O = {Oh, Ol};
3164
- endmodule
3165
-
3166
- // Post-place-and-route RAM model
3167
- module ICESTORM_RAM(
3168
- output RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0,
3169
- input RCLK, RCLKE, RE,
3170
- input RADDR_10, RADDR_9, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0,
3171
- input WCLK, WCLKE, WE,
3172
- input WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2, WADDR_1, WADDR_0,
3173
- input MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0,
3174
- input WDATA_15, WDATA_14, WDATA_13, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0
3175
- );
3176
- parameter WRITE_MODE = 0;
3177
- parameter READ_MODE = 0;
3178
-
3179
- parameter NEG_CLK_R = 1'b0;
3180
- parameter NEG_CLK_W = 1'b0;
3181
-
3182
- parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3183
- parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3184
- parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3185
- parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3186
- parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3187
- parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3188
- parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3189
- parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3190
- parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3191
- parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3192
- parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3193
- parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3194
- parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3195
- parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3196
- parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3197
- parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
3198
-
3199
- // Pull-down and pull-up functions
3200
- function pd;
3201
- input x;
3202
- begin
3203
- pd = (x === 1'bz) ? 1'b0 : x;
3204
- end
3205
- endfunction
3206
-
3207
- function pu;
3208
- input x;
3209
- begin
3210
- pu = (x === 1'bz) ? 1'b1 : x;
3211
- end
3212
- endfunction
3213
-
3214
- SB_RAM40_4K #(
3215
- .WRITE_MODE(WRITE_MODE),
3216
- .READ_MODE (READ_MODE ),
3217
- .INIT_0 (INIT_0 ),
3218
- .INIT_1 (INIT_1 ),
3219
- .INIT_2 (INIT_2 ),
3220
- .INIT_3 (INIT_3 ),
3221
- .INIT_4 (INIT_4 ),
3222
- .INIT_5 (INIT_5 ),
3223
- .INIT_6 (INIT_6 ),
3224
- .INIT_7 (INIT_7 ),
3225
- .INIT_8 (INIT_8 ),
3226
- .INIT_9 (INIT_9 ),
3227
- .INIT_A (INIT_A ),
3228
- .INIT_B (INIT_B ),
3229
- .INIT_C (INIT_C ),
3230
- .INIT_D (INIT_D ),
3231
- .INIT_E (INIT_E ),
3232
- .INIT_F (INIT_F )
3233
- ) RAM (
3234
- .RDATA({RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0}),
3235
- .RCLK (pd(RCLK) ^ NEG_CLK_R),
3236
- .RCLKE(pu(RCLKE)),
3237
- .RE (pd(RE)),
3238
- .RADDR({pd(RADDR_10), pd(RADDR_9), pd(RADDR_8), pd(RADDR_7), pd(RADDR_6), pd(RADDR_5), pd(RADDR_4), pd(RADDR_3), pd(RADDR_2), pd(RADDR_1), pd(RADDR_0)}),
3239
- .WCLK (pd(WCLK) ^ NEG_CLK_W),
3240
- .WCLKE(pu(WCLKE)),
3241
- .WE (pd(WE)),
3242
- .WADDR({pd(WADDR_10), pd(WADDR_9), pd(WADDR_8), pd(WADDR_7), pd(WADDR_6), pd(WADDR_5), pd(WADDR_4), pd(WADDR_3), pd(WADDR_2), pd(WADDR_1), pd(WADDR_0)}),
3243
- .MASK ({pd(MASK_15), pd(MASK_14), pd(MASK_13), pd(MASK_12), pd(MASK_11), pd(MASK_10), pd(MASK_9), pd(MASK_8),
3244
- pd(MASK_7), pd(MASK_6), pd(MASK_5), pd(MASK_4), pd(MASK_3), pd(MASK_2), pd(MASK_1), pd(MASK_0)}),
3245
- .WDATA({pd(WDATA_15), pd(WDATA_14), pd(WDATA_13), pd(WDATA_12), pd(WDATA_11), pd(WDATA_10), pd(WDATA_9), pd(WDATA_8),
3246
- pd(WDATA_7), pd(WDATA_6), pd(WDATA_5), pd(WDATA_4), pd(WDATA_3), pd(WDATA_2), pd(WDATA_1), pd(WDATA_0)})
3247
- );
3248
-
3249
- `ifdef TIMING
3250
- specify
3251
- (RCLK => RDATA_15) = (0:0:0, 0:0:0);
3252
- (RCLK => RDATA_14) = (0:0:0, 0:0:0);
3253
- (RCLK => RDATA_13) = (0:0:0, 0:0:0);
3254
- (RCLK => RDATA_12) = (0:0:0, 0:0:0);
3255
- (RCLK => RDATA_11) = (0:0:0, 0:0:0);
3256
- (RCLK => RDATA_10) = (0:0:0, 0:0:0);
3257
- (RCLK => RDATA_9) = (0:0:0, 0:0:0);
3258
- (RCLK => RDATA_8) = (0:0:0, 0:0:0);
3259
- (RCLK => RDATA_7) = (0:0:0, 0:0:0);
3260
- (RCLK => RDATA_6) = (0:0:0, 0:0:0);
3261
- (RCLK => RDATA_5) = (0:0:0, 0:0:0);
3262
- (RCLK => RDATA_4) = (0:0:0, 0:0:0);
3263
- (RCLK => RDATA_3) = (0:0:0, 0:0:0);
3264
- (RCLK => RDATA_2) = (0:0:0, 0:0:0);
3265
- (RCLK => RDATA_1) = (0:0:0, 0:0:0);
3266
- (RCLK => RDATA_0) = (0:0:0, 0:0:0);
3267
- $setuphold(posedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
3268
- $setuphold(posedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
3269
- $setuphold(negedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
3270
- $setuphold(negedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
3271
- $setuphold(posedge RCLK, posedge RE, 0:0:0, 0:0:0);
3272
- $setuphold(posedge RCLK, negedge RE, 0:0:0, 0:0:0);
3273
- $setuphold(negedge RCLK, posedge RE, 0:0:0, 0:0:0);
3274
- $setuphold(negedge RCLK, negedge RE, 0:0:0, 0:0:0);
3275
- $setuphold(posedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
3276
- $setuphold(posedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
3277
- $setuphold(negedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
3278
- $setuphold(negedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
3279
- $setuphold(posedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
3280
- $setuphold(posedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
3281
- $setuphold(negedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
3282
- $setuphold(negedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
3283
- $setuphold(posedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
3284
- $setuphold(posedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
3285
- $setuphold(negedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
3286
- $setuphold(negedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
3287
- $setuphold(posedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
3288
- $setuphold(posedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
3289
- $setuphold(negedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
3290
- $setuphold(negedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
3291
- $setuphold(posedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
3292
- $setuphold(posedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
3293
- $setuphold(negedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
3294
- $setuphold(negedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
3295
- $setuphold(posedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
3296
- $setuphold(posedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
3297
- $setuphold(negedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
3298
- $setuphold(negedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
3299
- $setuphold(posedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
3300
- $setuphold(posedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
3301
- $setuphold(negedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
3302
- $setuphold(negedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
3303
- $setuphold(posedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
3304
- $setuphold(posedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
3305
- $setuphold(negedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
3306
- $setuphold(negedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
3307
- $setuphold(posedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
3308
- $setuphold(posedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
3309
- $setuphold(negedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
3310
- $setuphold(negedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
3311
- $setuphold(posedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
3312
- $setuphold(posedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
3313
- $setuphold(negedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
3314
- $setuphold(negedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
3315
- $setuphold(posedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
3316
- $setuphold(posedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
3317
- $setuphold(negedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
3318
- $setuphold(negedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
3319
- $setuphold(posedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
3320
- $setuphold(posedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
3321
- $setuphold(negedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
3322
- $setuphold(negedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
3323
- $setuphold(posedge WCLK, posedge WE, 0:0:0, 0:0:0);
3324
- $setuphold(posedge WCLK, negedge WE, 0:0:0, 0:0:0);
3325
- $setuphold(negedge WCLK, posedge WE, 0:0:0, 0:0:0);
3326
- $setuphold(negedge WCLK, negedge WE, 0:0:0, 0:0:0);
3327
- $setuphold(posedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
3328
- $setuphold(posedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
3329
- $setuphold(negedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
3330
- $setuphold(negedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
3331
- $setuphold(posedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
3332
- $setuphold(posedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
3333
- $setuphold(negedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
3334
- $setuphold(negedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
3335
- $setuphold(posedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
3336
- $setuphold(posedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
3337
- $setuphold(negedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
3338
- $setuphold(negedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
3339
- $setuphold(posedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
3340
- $setuphold(posedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
3341
- $setuphold(negedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
3342
- $setuphold(negedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
3343
- $setuphold(posedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
3344
- $setuphold(posedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
3345
- $setuphold(negedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
3346
- $setuphold(negedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
3347
- $setuphold(posedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
3348
- $setuphold(posedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
3349
- $setuphold(negedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
3350
- $setuphold(negedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
3351
- $setuphold(posedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
3352
- $setuphold(posedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
3353
- $setuphold(negedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
3354
- $setuphold(negedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
3355
- $setuphold(posedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
3356
- $setuphold(posedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
3357
- $setuphold(negedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
3358
- $setuphold(negedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
3359
- $setuphold(posedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
3360
- $setuphold(posedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
3361
- $setuphold(negedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
3362
- $setuphold(negedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
3363
- $setuphold(posedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
3364
- $setuphold(posedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
3365
- $setuphold(negedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
3366
- $setuphold(negedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
3367
- $setuphold(posedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
3368
- $setuphold(posedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
3369
- $setuphold(negedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
3370
- $setuphold(negedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
3371
- $setuphold(posedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
3372
- $setuphold(posedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
3373
- $setuphold(negedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
3374
- $setuphold(negedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
3375
- $setuphold(posedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
3376
- $setuphold(posedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
3377
- $setuphold(negedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
3378
- $setuphold(negedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
3379
- $setuphold(posedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
3380
- $setuphold(posedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
3381
- $setuphold(negedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
3382
- $setuphold(negedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
3383
- $setuphold(posedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
3384
- $setuphold(posedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
3385
- $setuphold(negedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
3386
- $setuphold(negedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
3387
- $setuphold(posedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
3388
- $setuphold(posedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
3389
- $setuphold(negedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
3390
- $setuphold(negedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
3391
- $setuphold(posedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
3392
- $setuphold(posedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
3393
- $setuphold(negedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
3394
- $setuphold(negedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
3395
- $setuphold(posedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
3396
- $setuphold(posedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
3397
- $setuphold(negedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
3398
- $setuphold(negedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
3399
- $setuphold(posedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
3400
- $setuphold(posedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
3401
- $setuphold(negedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
3402
- $setuphold(negedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
3403
- $setuphold(posedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
3404
- $setuphold(posedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
3405
- $setuphold(negedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
3406
- $setuphold(negedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
3407
- $setuphold(posedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
3408
- $setuphold(posedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
3409
- $setuphold(negedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
3410
- $setuphold(negedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
3411
- $setuphold(posedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
3412
- $setuphold(posedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
3413
- $setuphold(negedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
3414
- $setuphold(negedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
3415
- $setuphold(posedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
3416
- $setuphold(posedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
3417
- $setuphold(negedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
3418
- $setuphold(negedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
3419
- $setuphold(posedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
3420
- $setuphold(posedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
3421
- $setuphold(negedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
3422
- $setuphold(negedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
3423
- $setuphold(posedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
3424
- $setuphold(posedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
3425
- $setuphold(negedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
3426
- $setuphold(negedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
3427
- $setuphold(posedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
3428
- $setuphold(posedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
3429
- $setuphold(negedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
3430
- $setuphold(negedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
3431
- $setuphold(posedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
3432
- $setuphold(posedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
3433
- $setuphold(negedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
3434
- $setuphold(negedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
3435
- $setuphold(posedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
3436
- $setuphold(posedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
3437
- $setuphold(negedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
3438
- $setuphold(negedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
3439
- $setuphold(posedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
3440
- $setuphold(posedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
3441
- $setuphold(negedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
3442
- $setuphold(negedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
3443
- $setuphold(posedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
3444
- $setuphold(posedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
3445
- $setuphold(negedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
3446
- $setuphold(negedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
3447
- $setuphold(posedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
3448
- $setuphold(posedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
3449
- $setuphold(negedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
3450
- $setuphold(negedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
3451
- $setuphold(posedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
3452
- $setuphold(posedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
3453
- $setuphold(negedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
3454
- $setuphold(negedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
3455
- $setuphold(posedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
3456
- $setuphold(posedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
3457
- $setuphold(negedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
3458
- $setuphold(negedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
3459
- $setuphold(posedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
3460
- $setuphold(posedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
3461
- $setuphold(negedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
3462
- $setuphold(negedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
3463
- $setuphold(posedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
3464
- $setuphold(posedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
3465
- $setuphold(negedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
3466
- $setuphold(negedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
3467
- $setuphold(posedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
3468
- $setuphold(posedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
3469
- $setuphold(negedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
3470
- $setuphold(negedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
3471
- $setuphold(posedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
3472
- $setuphold(posedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
3473
- $setuphold(negedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
3474
- $setuphold(negedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
3475
- $setuphold(posedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
3476
- $setuphold(posedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
3477
- $setuphold(negedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
3478
- $setuphold(negedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
3479
- $setuphold(posedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
3480
- $setuphold(posedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
3481
- $setuphold(negedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
3482
- $setuphold(negedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
3483
- $setuphold(posedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
3484
- $setuphold(posedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
3485
- $setuphold(negedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
3486
- $setuphold(negedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
3487
- $setuphold(posedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
3488
- $setuphold(posedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
3489
- $setuphold(negedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
3490
- $setuphold(negedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
3491
- $setuphold(posedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
3492
- $setuphold(posedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
3493
- $setuphold(negedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
3494
- $setuphold(negedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
3495
- $setuphold(posedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
3496
- $setuphold(posedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
3497
- $setuphold(negedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
3498
- $setuphold(negedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
3499
-
3500
- endspecify
3501
- `endif
3502
- endmodule