npm - @yowasp/yosys - Versions diffs - 0.58.1009 → 0.59.35-dev.1011 - Mend

@yowasp/yosys 0.58.1009 → 0.59.35-dev.1011

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.

Files changed (5) hide show

package/gen/bundle.js +1 -1
package/gen/resources-yosys.js +27 -31
package/gen/share/lattice/cells_bb_nexus.v +10389 -0
package/gen/yosys.core.wasm +0 -0
package/package.json +2 -2

package/gen/resources-yosys.js CHANGED Viewed

@@ -44,18 +44,12 @@ export const filesystem = {
         },
         "dff2ff.v": "(* techmap_celltype = \"$dff\" *)\nmodule dff2ff (CLK, D, Q);\n\tparameter WIDTH = 1;\n\tparameter CLK_POLARITY = 1;\n\n\tinput CLK;\n\t(* force_downto *)\n\tinput [WIDTH-1:0] D;\n\t(* force_downto *)\n\toutput reg [WIDTH-1:0] Q;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc;;\";\n\n\talways @($global_clock)\n\t\tQ <= D;\nendmodule\n",
         "ecp5": {
-            "arith_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2018  gatecat <gatecat@ds0.me>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_ecp5_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 4;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\tfunction integer round_up2;\n\t\tinput integer N;\n\t\tbegin\n\t\t\tround_up2 = ((N + 1) / 2) * 2;\n\t\tend\n\tendfunction\n\n\tlocalparam Y_WIDTH2 = round_up2(Y_WIDTH);\n\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BX = B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] FCO, Y1;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice\n\t\tCCU2C #(\n\t\t\t.INIT0(16'b1001011010101010),\n\t\t\t.INIT1(16'b1001011010101010),\n\t\t\t.INJECT1_0(\"NO\"),\n\t\t\t.INJECT1_1(\"NO\")\n\t   ) ccu2c_i (\n\t\t\t.CIN(C[i]),\n\t\t\t.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),\n\t\t\t.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),\n\t\t\t.S0(Y[i]), .S1(Y1[i]),\n\t\t\t.COUT(FCO[i])\n\t\t);\n\n\t\tassign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));\n\t\tif (i+1 < Y_WIDTH) begin\n\t\t\tassign CO[i+1] = FCO[i];\n\t\t\tassign Y[i+1] = Y1[i];\n\t\tend\n\tend endgenerate\n\n\tassign X = AA ^ BB;\nendmodule\n",
-            "brams.txt": "ram block $__ECP5_DP16KD_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\tportoption \"WRITEMODE\" \"NORMAL\" {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"WRITETHROUGH\" {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"READBEFOREWRITE\" {\n\t\t\trdwr old;\n\t\t}\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated block_wr;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n}\n\nram block $__ECP5_PDPW16KD_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\twidth 36;\n\t\tclock anyedge;\n\t\tclken;\n\t}\n}\n",
-            "brams_map.v": "module $__ECP5_DP16KD_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_WR_BE_WIDTH = 2;\nparameter PORT_A_CLK_POL = 1;\nparameter PORT_A_OPTION_WRITEMODE = \"NORMAL\";\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_WR_BE_WIDTH = 2;\nparameter PORT_B_CLK_POL = 1;\nparameter PORT_B_OPTION_WRITEMODE = \"NORMAL\";\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 16; i = i + 1) begin\n\t\tinit_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];\n\tend\nendfunction\n\nwire [17:0] DOA;\nwire [17:0] DOB;\nwire [17:0] DIA = PORT_A_WR_DATA;\nwire [17:0] DIB = PORT_B_WR_DATA;\n\nassign PORT_A_RD_DATA = DOA;\nassign PORT_B_RD_DATA = DOB;\n\nDP16KD #(\n\t.INITVAL_00(init_slice('h00)),\n\t.INITVAL_01(init_slice('h01)),\n\t.INITVAL_02(init_slice('h02)),\n\t.INITVAL_03(init_slice('h03)),\n\t.INITVAL_04(init_slice('h04)),\n\t.INITVAL_05(init_slice('h05)),\n\t.INITVAL_06(init_slice('h06)),\n\t.INITVAL_07(init_slice('h07)),\n\t.INITVAL_08(init_slice('h08)),\n\t.INITVAL_09(init_slice('h09)),\n\t.INITVAL_0A(init_slice('h0a)),\n\t.INITVAL_0B(init_slice('h0b)),\n\t.INITVAL_0C(init_slice('h0c)),\n\t.INITVAL_0D(init_slice('h0d)),\n\t.INITVAL_0E(init_slice('h0e)),\n\t.INITVAL_0F(init_slice('h0f)),\n\t.INITVAL_10(init_slice('h10)),\n\t.INITVAL_11(init_slice('h11)),\n\t.INITVAL_12(init_slice('h12)),\n\t.INITVAL_13(init_slice('h13)),\n\t.INITVAL_14(init_slice('h14)),\n\t.INITVAL_15(init_slice('h15)),\n\t.INITVAL_16(init_slice('h16)),\n\t.INITVAL_17(init_slice('h17)),\n\t.INITVAL_18(init_slice('h18)),\n\t.INITVAL_19(init_slice('h19)),\n\t.INITVAL_1A(init_slice('h1a)),\n\t.INITVAL_1B(init_slice('h1b)),\n\t.INITVAL_1C(init_slice('h1c)),\n\t.INITVAL_1D(init_slice('h1d)),\n\t.INITVAL_1E(init_slice('h1e)),\n\t.INITVAL_1F(init_slice('h1f)),\n\t.INITVAL_20(init_slice('h20)),\n\t.INITVAL_21(init_slice('h21)),\n\t.INITVAL_22(init_slice('h22)),\n\t.INITVAL_23(init_slice('h23)),\n\t.INITVAL_24(init_slice('h24)),\n\t.INITVAL_25(init_slice('h25)),\n\t.INITVAL_26(init_slice('h26)),\n\t.INITVAL_27(init_slice('h27)),\n\t.INITVAL_28(init_slice('h28)),\n\t.INITVAL_29(init_slice('h29)),\n\t.INITVAL_2A(init_slice('h2a)),\n\t.INITVAL_2B(init_slice('h2b)),\n\t.INITVAL_2C(init_slice('h2c)),\n\t.INITVAL_2D(init_slice('h2d)),\n\t.INITVAL_2E(init_slice('h2e)),\n\t.INITVAL_2F(init_slice('h2f)),\n\t.INITVAL_30(init_slice('h30)),\n\t.INITVAL_31(init_slice('h31)),\n\t.INITVAL_32(init_slice('h32)),\n\t.INITVAL_33(init_slice('h33)),\n\t.INITVAL_34(init_slice('h34)),\n\t.INITVAL_35(init_slice('h35)),\n\t.INITVAL_36(init_slice('h36)),\n\t.INITVAL_37(init_slice('h37)),\n\t.INITVAL_38(init_slice('h38)),\n\t.INITVAL_39(init_slice('h39)),\n\t.INITVAL_3A(init_slice('h3a)),\n\t.INITVAL_3B(init_slice('h3b)),\n\t.INITVAL_3C(init_slice('h3c)),\n\t.INITVAL_3D(init_slice('h3d)),\n\t.INITVAL_3E(init_slice('h3e)),\n\t.INITVAL_3F(init_slice('h3f)),\n\t.DATA_WIDTH_A(PORT_A_WIDTH),\n\t.DATA_WIDTH_B(PORT_B_WIDTH),\n\t.REGMODE_A(\"NOREG\"),\n\t.REGMODE_B(\"NOREG\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n\t.CSDECODE_A(\"0b000\"),\n\t.CSDECODE_B(\"0b000\"),\n\t.CLKAMUX(PORT_A_CLK_POL ? \"CLKA\" : \"INV\"),\n\t.CLKBMUX(PORT_B_CLK_POL ? \"CLKB\" : \"INV\"),\n\t.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),\n\t.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),\n\t.GSR(\"AUTO\")\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_A_CLK),\n\t.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),\n\t.CEA(PORT_A_CLK_EN),\n\t.OCEA(1'b1),\n\t.RSTA(OPTION_RESETMODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t.CSA0(1'b0),\n\t.CSA1(1'b0),\n\t.CSA2(1'b0),\n\t.ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]),\n\t.ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]),\n\t.ADA2(PORT_A_ADDR[2]),\n\t.ADA3(PORT_A_ADDR[3]),\n\t.ADA4(PORT_A_ADDR[4]),\n\t.ADA5(PORT_A_ADDR[5]),\n\t.ADA6(PORT_A_ADDR[6]),\n\t.ADA7(PORT_A_ADDR[7]),\n\t.ADA8(PORT_A_ADDR[8]),\n\t.ADA9(PORT_A_ADDR[9]),\n\t.ADA10(PORT_A_ADDR[10]),\n\t.ADA11(PORT_A_ADDR[11]),\n\t.ADA12(PORT_A_ADDR[12]),\n\t.ADA13(PORT_A_ADDR[13]),\n\t.DIA0(DIA[0]),\n\t.DIA1(DIA[1]),\n\t.DIA2(DIA[2]),\n\t.DIA3(DIA[3]),\n\t.DIA4(DIA[4]),\n\t.DIA5(DIA[5]),\n\t.DIA6(DIA[6]),\n\t.DIA7(DIA[7]),\n\t.DIA8(DIA[8]),\n\t.DIA9(DIA[9]),\n\t.DIA10(DIA[10]),\n\t.DIA11(DIA[11]),\n\t.DIA12(DIA[12]),\n\t.DIA13(DIA[13]),\n\t.DIA14(DIA[14]),\n\t.DIA15(DIA[15]),\n\t.DIA16(DIA[16]),\n\t.DIA17(DIA[17]),\n\t.DOA0(DOA[0]),\n\t.DOA1(DOA[1]),\n\t.DOA2(DOA[2]),\n\t.DOA3(DOA[3]),\n\t.DOA4(DOA[4]),\n\t.DOA5(DOA[5]),\n\t.DOA6(DOA[6]),\n\t.DOA7(DOA[7]),\n\t.DOA8(DOA[8]),\n\t.DOA9(DOA[9]),\n\t.DOA10(DOA[10]),\n\t.DOA11(DOA[11]),\n\t.DOA12(DOA[12]),\n\t.DOA13(DOA[13]),\n\t.DOA14(DOA[14]),\n\t.DOA15(DOA[15]),\n\t.DOA16(DOA[16]),\n\t.DOA17(DOA[17]),\n\n\t.CLKB(PORT_B_CLK),\n\t.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),\n\t.CEB(PORT_B_CLK_EN),\n\t.OCEB(1'b1),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t.CSB0(1'b0),\n\t.CSB1(1'b0),\n\t.CSB2(1'b0),\n\t.ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]),\n\t.ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]),\n\t.ADB2(PORT_B_ADDR[2]),\n\t.ADB3(PORT_B_ADDR[3]),\n\t.ADB4(PORT_B_ADDR[4]),\n\t.ADB5(PORT_B_ADDR[5]),\n\t.ADB6(PORT_B_ADDR[6]),\n\t.ADB7(PORT_B_ADDR[7]),\n\t.ADB8(PORT_B_ADDR[8]),\n\t.ADB9(PORT_B_ADDR[9]),\n\t.ADB10(PORT_B_ADDR[10]),\n\t.ADB11(PORT_B_ADDR[11]),\n\t.ADB12(PORT_B_ADDR[12]),\n\t.ADB13(PORT_B_ADDR[13]),\n\t.DIB0(DIB[0]),\n\t.DIB1(DIB[1]),\n\t.DIB2(DIB[2]),\n\t.DIB3(DIB[3]),\n\t.DIB4(DIB[4]),\n\t.DIB5(DIB[5]),\n\t.DIB6(DIB[6]),\n\t.DIB7(DIB[7]),\n\t.DIB8(DIB[8]),\n\t.DIB9(DIB[9]),\n\t.DIB10(DIB[10]),\n\t.DIB11(DIB[11]),\n\t.DIB12(DIB[12]),\n\t.DIB13(DIB[13]),\n\t.DIB14(DIB[14]),\n\t.DIB15(DIB[15]),\n\t.DIB16(DIB[16]),\n\t.DIB17(DIB[17]),\n\t.DOB0(DOB[0]),\n\t.DOB1(DOB[1]),\n\t.DOB2(DOB[2]),\n\t.DOB3(DOB[3]),\n\t.DOB4(DOB[4]),\n\t.DOB5(DOB[5]),\n\t.DOB6(DOB[6]),\n\t.DOB7(DOB[7]),\n\t.DOB8(DOB[8]),\n\t.DOB9(DOB[9]),\n\t.DOB10(DOB[10]),\n\t.DOB11(DOB[11]),\n\t.DOB12(DOB[12]),\n\t.DOB13(DOB[13]),\n\t.DOB14(DOB[14]),\n\t.DOB15(DOB[15]),\n\t.DOB16(DOB[16]),\n\t.DOB17(DOB[17]),\n);\n\nendmodule\n\n\nmodule $__ECP5_PDPW16KD_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 36;\nparameter PORT_R_CLK_POL = 1;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\nparameter PORT_W_WIDTH = 36;\nparameter PORT_W_WR_EN_WIDTH = 4;\nparameter PORT_W_CLK_POL = 1;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 16; i = i + 1) begin\n\t\tinit_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];\n\tend\nendfunction\n\nwire [35:0] DI = PORT_W_WR_DATA;\nwire [35:0] DO;\n\nassign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18];\n\nDP16KD #(\n\t.INITVAL_00(init_slice('h00)),\n\t.INITVAL_01(init_slice('h01)),\n\t.INITVAL_02(init_slice('h02)),\n\t.INITVAL_03(init_slice('h03)),\n\t.INITVAL_04(init_slice('h04)),\n\t.INITVAL_05(init_slice('h05)),\n\t.INITVAL_06(init_slice('h06)),\n\t.INITVAL_07(init_slice('h07)),\n\t.INITVAL_08(init_slice('h08)),\n\t.INITVAL_09(init_slice('h09)),\n\t.INITVAL_0A(init_slice('h0a)),\n\t.INITVAL_0B(init_slice('h0b)),\n\t.INITVAL_0C(init_slice('h0c)),\n\t.INITVAL_0D(init_slice('h0d)),\n\t.INITVAL_0E(init_slice('h0e)),\n\t.INITVAL_0F(init_slice('h0f)),\n\t.INITVAL_10(init_slice('h10)),\n\t.INITVAL_11(init_slice('h11)),\n\t.INITVAL_12(init_slice('h12)),\n\t.INITVAL_13(init_slice('h13)),\n\t.INITVAL_14(init_slice('h14)),\n\t.INITVAL_15(init_slice('h15)),\n\t.INITVAL_16(init_slice('h16)),\n\t.INITVAL_17(init_slice('h17)),\n\t.INITVAL_18(init_slice('h18)),\n\t.INITVAL_19(init_slice('h19)),\n\t.INITVAL_1A(init_slice('h1a)),\n\t.INITVAL_1B(init_slice('h1b)),\n\t.INITVAL_1C(init_slice('h1c)),\n\t.INITVAL_1D(init_slice('h1d)),\n\t.INITVAL_1E(init_slice('h1e)),\n\t.INITVAL_1F(init_slice('h1f)),\n\t.INITVAL_20(init_slice('h20)),\n\t.INITVAL_21(init_slice('h21)),\n\t.INITVAL_22(init_slice('h22)),\n\t.INITVAL_23(init_slice('h23)),\n\t.INITVAL_24(init_slice('h24)),\n\t.INITVAL_25(init_slice('h25)),\n\t.INITVAL_26(init_slice('h26)),\n\t.INITVAL_27(init_slice('h27)),\n\t.INITVAL_28(init_slice('h28)),\n\t.INITVAL_29(init_slice('h29)),\n\t.INITVAL_2A(init_slice('h2a)),\n\t.INITVAL_2B(init_slice('h2b)),\n\t.INITVAL_2C(init_slice('h2c)),\n\t.INITVAL_2D(init_slice('h2d)),\n\t.INITVAL_2E(init_slice('h2e)),\n\t.INITVAL_2F(init_slice('h2f)),\n\t.INITVAL_30(init_slice('h30)),\n\t.INITVAL_31(init_slice('h31)),\n\t.INITVAL_32(init_slice('h32)),\n\t.INITVAL_33(init_slice('h33)),\n\t.INITVAL_34(init_slice('h34)),\n\t.INITVAL_35(init_slice('h35)),\n\t.INITVAL_36(init_slice('h36)),\n\t.INITVAL_37(init_slice('h37)),\n\t.INITVAL_38(init_slice('h38)),\n\t.INITVAL_39(init_slice('h39)),\n\t.INITVAL_3A(init_slice('h3a)),\n\t.INITVAL_3B(init_slice('h3b)),\n\t.INITVAL_3C(init_slice('h3c)),\n\t.INITVAL_3D(init_slice('h3d)),\n\t.INITVAL_3E(init_slice('h3e)),\n\t.INITVAL_3F(init_slice('h3f)),\n\t.DATA_WIDTH_A(PORT_W_WIDTH),\n\t.DATA_WIDTH_B(PORT_R_WIDTH),\n\t.REGMODE_A(\"NOREG\"),\n\t.REGMODE_B(\"NOREG\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n\t.CSDECODE_A(\"0b000\"),\n\t.CSDECODE_B(\"0b000\"),\n\t.CLKAMUX(PORT_W_CLK_POL ? \"CLKA\" : \"INV\"),\n\t.CLKBMUX(PORT_R_CLK_POL ? \"CLKB\" : \"INV\"),\n\t.GSR(\"AUTO\")\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_W_CLK),\n\t.WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]),\n\t.CEA(PORT_W_CLK_EN),\n\t.OCEA(1'b0),\n\t.RSTA(1'b0),\n\t.CSA0(1'b0),\n\t.CSA1(1'b0),\n\t.CSA2(1'b0),\n\t.ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),\n\t.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),\n\t.ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]),\n\t.ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]),\n\t.ADA4(PORT_W_ADDR[4]),\n\t.ADA5(PORT_W_ADDR[5]),\n\t.ADA6(PORT_W_ADDR[6]),\n\t.ADA7(PORT_W_ADDR[7]),\n\t.ADA8(PORT_W_ADDR[8]),\n\t.ADA9(PORT_W_ADDR[9]),\n\t.ADA10(PORT_W_ADDR[10]),\n\t.ADA11(PORT_W_ADDR[11]),\n\t.ADA12(PORT_W_ADDR[12]),\n\t.ADA13(PORT_W_ADDR[13]),\n\t.DIA0(DI[0]),\n\t.DIA1(DI[1]),\n\t.DIA2(DI[2]),\n\t.DIA3(DI[3]),\n\t.DIA4(DI[4]),\n\t.DIA5(DI[5]),\n\t.DIA6(DI[6]),\n\t.DIA7(DI[7]),\n\t.DIA8(DI[8]),\n\t.DIA9(DI[9]),\n\t.DIA10(DI[10]),\n\t.DIA11(DI[11]),\n\t.DIA12(DI[12]),\n\t.DIA13(DI[13]),\n\t.DIA14(DI[14]),\n\t.DIA15(DI[15]),\n\t.DIA16(DI[16]),\n\t.DIA17(DI[17]),\n\t.DIB0(DI[18]),\n\t.DIB1(DI[19]),\n\t.DIB2(DI[20]),\n\t.DIB3(DI[21]),\n\t.DIB4(DI[22]),\n\t.DIB5(DI[23]),\n\t.DIB6(DI[24]),\n\t.DIB7(DI[25]),\n\t.DIB8(DI[26]),\n\t.DIB9(DI[27]),\n\t.DIB10(DI[28]),\n\t.DIB11(DI[29]),\n\t.DIB12(DI[30]),\n\t.DIB13(DI[31]),\n\t.DIB14(DI[32]),\n\t.DIB15(DI[33]),\n\t.DIB16(DI[34]),\n\t.DIB17(DI[35]),\n\n\t.CLKB(PORT_R_CLK),\n\t.WEB(1'b0),\n\t.CEB(PORT_R_CLK_EN),\n\t.OCEB(1'b1),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST),\n\t.CSB0(1'b0),\n\t.CSB1(1'b0),\n\t.CSB2(1'b0),\n\t.ADB0(PORT_R_ADDR[0]),\n\t.ADB1(PORT_R_ADDR[1]),\n\t.ADB2(PORT_R_ADDR[2]),\n\t.ADB3(PORT_R_ADDR[3]),\n\t.ADB4(PORT_R_ADDR[4]),\n\t.ADB5(PORT_R_ADDR[5]),\n\t.ADB6(PORT_R_ADDR[6]),\n\t.ADB7(PORT_R_ADDR[7]),\n\t.ADB8(PORT_R_ADDR[8]),\n\t.ADB9(PORT_R_ADDR[9]),\n\t.ADB10(PORT_R_ADDR[10]),\n\t.ADB11(PORT_R_ADDR[11]),\n\t.ADB12(PORT_R_ADDR[12]),\n\t.ADB13(PORT_R_ADDR[13]),\n\t.DOA0(DO[0]),\n\t.DOA1(DO[1]),\n\t.DOA2(DO[2]),\n\t.DOA3(DO[3]),\n\t.DOA4(DO[4]),\n\t.DOA5(DO[5]),\n\t.DOA6(DO[6]),\n\t.DOA7(DO[7]),\n\t.DOA8(DO[8]),\n\t.DOA9(DO[9]),\n\t.DOA10(DO[10]),\n\t.DOA11(DO[11]),\n\t.DOA12(DO[12]),\n\t.DOA13(DO[13]),\n\t.DOA14(DO[14]),\n\t.DOA15(DO[15]),\n\t.DOA16(DO[16]),\n\t.DOA17(DO[17]),\n\t.DOB0(DO[18]),\n\t.DOB1(DO[19]),\n\t.DOB2(DO[20]),\n\t.DOB3(DO[21]),\n\t.DOB4(DO[22]),\n\t.DOB5(DO[23]),\n\t.DOB6(DO[24]),\n\t.DOB7(DO[25]),\n\t.DOB8(DO[26]),\n\t.DOB9(DO[27]),\n\t.DOB10(DO[28]),\n\t.DOB11(DO[29]),\n\t.DOB12(DO[30]),\n\t.DOB13(DO[31]),\n\t.DOB14(DO[32]),\n\t.DOB15(DO[33]),\n\t.DOB16(DO[34]),\n\t.DOB17(DO[35]),\n);\n\nendmodule\n",
-            "cells_bb.v": "// ECP5 Blackbox cells\n// FIXME: Create sim models\n\n(* blackbox *)\nmodule MULT18X18D(\n\tinput A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,\n\tinput B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,\n\tinput C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,\n\tinput SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,\n\tinput CLK0, CLK1, CLK2, CLK3,\n\tinput CE0, CE1, CE2, CE3,\n\tinput RST0, RST1, RST2, RST3,\n\tinput SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,\n\tinput SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,\n\toutput SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,\n\toutput SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,\n\toutput ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,\n\toutput ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,\n\toutput ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,\n\toutput P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,\n\toutput SIGNEDP\n);\n\tparameter REG_INPUTA_CLK = \"NONE\";\n\tparameter REG_INPUTA_CE = \"CE0\";\n\tparameter REG_INPUTA_RST = \"RST0\";\n\tparameter REG_INPUTB_CLK = \"NONE\";\n\tparameter REG_INPUTB_CE = \"CE0\";\n\tparameter REG_INPUTB_RST = \"RST0\";\n\tparameter REG_INPUTC_CLK = \"NONE\";\n\tparameter REG_INPUTC_CE = \"CE0\";\n\tparameter REG_INPUTC_RST = \"RST0\";\n\tparameter REG_PIPELINE_CLK = \"NONE\";\n\tparameter REG_PIPELINE_CE = \"CE0\";\n\tparameter REG_PIPELINE_RST = \"RST0\";\n\tparameter REG_OUTPUT_CLK = \"NONE\";\n\tparameter REG_OUTPUT_CE = \"CE0\";\n\tparameter REG_OUTPUT_RST = \"RST0\";\n\tparameter [127:0] CLK0_DIV = \"ENABLED\";\n\tparameter [127:0] CLK1_DIV = \"ENABLED\";\n\tparameter [127:0] CLK2_DIV = \"ENABLED\";\n\tparameter [127:0] CLK3_DIV = \"ENABLED\";\n\tparameter HIGHSPEED_CLK = \"NONE\";\n\tparameter [127:0] GSR = \"ENABLED\";\n\tparameter CAS_MATCH_REG = \"FALSE\";\n\tparameter [127:0] SOURCEB_MODE = \"B_SHIFT\";\n\tparameter [127:0] MULT_BYPASS = \"DISABLED\";\n\tparameter [127:0] RESETMODE = \"SYNC\";\nendmodule\n\n(* blackbox *)\nmodule ALU54B(\n\tinput CLK0, CLK1, CLK2, CLK3,\n\tinput CE0, CE1, CE2, CE3,\n\tinput RST0, RST1, RST2, RST3,\n\tinput SIGNEDIA, SIGNEDIB, SIGNEDCIN,\n\tinput A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,\n\tinput B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,\n\tinput C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,\n\tinput CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,\n\tinput MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,\n\tinput MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,\n\tinput CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,\n\tinput OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,\n\toutput R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,\n\toutput CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,\n\toutput EQZ, EQZM, EQOM, EQPAT, EQPATB,\n\toutput OVER, UNDER, OVERUNDER,\n\toutput SIGNEDR\n);\n\tparameter REG_INPUTC0_CLK = \"NONE\";\n\tparameter REG_INPUTC0_CE = \"CE0\";\n\tparameter REG_INPUTC0_RST = \"RST0\";\n\tparameter REG_INPUTC1_CLK = \"NONE\";\n\tparameter REG_INPUTC1_CE = \"CE0\";\n\tparameter REG_INPUTC1_RST = \"RST0\";\n\tparameter REG_OPCODEOP0_0_CLK = \"NONE\";\n\tparameter REG_OPCODEOP0_0_CE = \"CE0\";\n\tparameter REG_OPCODEOP0_0_RST = \"RST0\";\n\tparameter REG_OPCODEOP1_0_CLK = \"NONE\";\n\tparameter REG_OPCODEOP0_1_CLK = \"NONE\";\n\tparameter REG_OPCODEOP0_1_CE = \"CE0\";\n\tparameter REG_OPCODEOP0_1_RST = \"RST0\";\n\tparameter REG_OPCODEOP1_1_CLK = \"NONE\";\n\tparameter REG_OPCODEIN_0_CLK = \"NONE\";\n\tparameter REG_OPCODEIN_0_CE = \"CE0\";\n\tparameter REG_OPCODEIN_0_RST = \"RST0\";\n\tparameter REG_OPCODEIN_1_CLK = \"NONE\";\n\tparameter REG_OPCODEIN_1_CE = \"CE0\";\n\tparameter REG_OPCODEIN_1_RST = \"RST0\";\n\tparameter REG_OUTPUT0_CLK = \"NONE\";\n\tparameter REG_OUTPUT0_CE = \"CE0\";\n\tparameter REG_OUTPUT0_RST = \"RST0\";\n\tparameter REG_OUTPUT1_CLK = \"NONE\";\n\tparameter REG_OUTPUT1_CE = \"CE0\";\n\tparameter REG_OUTPUT1_RST = \"RST0\";\n\tparameter REG_FLAG_CLK = \"NONE\";\n\tparameter REG_FLAG_CE = \"CE0\";\n\tparameter REG_FLAG_RST = \"RST0\";\n\tparameter REG_INPUTCFB_CLK = \"NONE\";\n\tparameter REG_INPUTCFB_CE = \"CE0\";\n\tparameter REG_INPUTCFB_RST = \"RST0\";\n\tparameter [127:0] MCPAT_SOURCE = \"STATIC\";\n\tparameter [127:0] MASKPAT_SOURCE = \"STATIC\";\n\tparameter MASK01 = \"0x00000000000000\";\n\tparameter [127:0] CLK0_DIV = \"ENABLED\";\n\tparameter [127:0] CLK1_DIV = \"ENABLED\";\n\tparameter [127:0] CLK2_DIV = \"ENABLED\";\n\tparameter [127:0] CLK3_DIV = \"ENABLED\";\n\tparameter MCPAT = \"0x00000000000000\";\n\tparameter MASKPAT = \"0x00000000000000\";\n\tparameter RNDPAT = \"0x00000000000000\";\n\tparameter [127:0] GSR = \"ENABLED\";\n\tparameter [127:0] RESETMODE = \"SYNC\";\n\tparameter MULT9_MODE = \"DISABLED\";\n\tparameter FORCE_ZERO_BARREL_SHIFT = \"DISABLED\";\n\tparameter LEGACY = \"DISABLED\";\nendmodule\n\n(* blackbox *)\nmodule EHXPLLL (\n\tinput CLKI, CLKFB,\n\tinput PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,\n\tinput STDBY, PLLWAKESYNC,\n\tinput RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,\n\toutput CLKOP, CLKOS, CLKOS2, CLKOS3,\n\toutput LOCK, INTLOCK,\n\toutput REFCLK, CLKINTFB\n);\n\tparameter CLKI_DIV = 1;\n\tparameter CLKFB_DIV = 1;\n\tparameter CLKOP_DIV = 8;\n\tparameter CLKOS_DIV = 8;\n\tparameter CLKOS2_DIV = 8;\n\tparameter CLKOS3_DIV = 8;\n\tparameter CLKOP_ENABLE = \"ENABLED\";\n\tparameter CLKOS_ENABLE = \"DISABLED\";\n\tparameter CLKOS2_ENABLE = \"DISABLED\";\n\tparameter CLKOS3_ENABLE = \"DISABLED\";\n\tparameter CLKOP_CPHASE = 0;\n\tparameter CLKOS_CPHASE = 0;\n\tparameter CLKOS2_CPHASE = 0;\n\tparameter CLKOS3_CPHASE = 0;\n\tparameter CLKOP_FPHASE = 0;\n\tparameter CLKOS_FPHASE = 0;\n\tparameter CLKOS2_FPHASE = 0;\n\tparameter CLKOS3_FPHASE = 0;\n\tparameter FEEDBK_PATH = \"CLKOP\";\n\tparameter CLKOP_TRIM_POL = \"RISING\";\n\tparameter CLKOP_TRIM_DELAY = 0;\n\tparameter CLKOS_TRIM_POL = \"RISING\";\n\tparameter CLKOS_TRIM_DELAY = 0;\n\tparameter OUTDIVIDER_MUXA = \"DIVA\";\n\tparameter OUTDIVIDER_MUXB = \"DIVB\";\n\tparameter OUTDIVIDER_MUXC = \"DIVC\";\n\tparameter OUTDIVIDER_MUXD = \"DIVD\";\n\tparameter PLL_LOCK_MODE = 0;\n\tparameter PLL_LOCK_DELAY = 200;\n\tparameter STDBY_ENABLE = \"DISABLED\";\n\tparameter REFIN_RESET = \"DISABLED\";\n\tparameter SYNC_ENABLE = \"DISABLED\";\n\tparameter INT_LOCK_STICKY = \"ENABLED\";\n\tparameter DPHASE_SOURCE = \"DISABLED\";\n\tparameter PLLRST_ENA = \"DISABLED\";\n\tparameter INTFB_WAKE = \"DISABLED\";\nendmodule\n\n(* blackbox *)\nmodule DTR(\n\tinput STARTPULSE,\n\toutput DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0\n);\nendmodule\n\n(* blackbox *)\nmodule OSCG(\n\toutput OSC\n);\nparameter DIV = 128;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule USRMCLK(\n\tinput USRMCLKI, USRMCLKTS,\n\toutput USRMCLKO\n);\nendmodule\n\n(* blackbox *) (* keep *)\nmodule JTAGG(\n\t(* iopad_external_pin *)\n\tinput TCK, \n\t(* iopad_external_pin *)\n\tinput TMS, \n\t(* iopad_external_pin *)\n\tinput TDI,\n\tinput JTDO2, JTDO1,\n\t(* iopad_external_pin *)\n\toutput TDO,\n\toutput JTDI, JTCK, JRTI2, JRTI1,\n\toutput JSHIFT, JUPDATE, JRSTN, JCE2, JCE1\n);\nparameter ER1 = \"ENABLED\";\nparameter ER2 = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule DELAYF(\n\tinput A, LOADN, MOVE, DIRECTION,\n\toutput Z, CFLAG\n);\n\tparameter DEL_MODE = \"USER_DEFINED\";\n\tparameter DEL_VALUE = 0;\nendmodule\n\n(* blackbox *)\nmodule DELAYG(\n\tinput A,\n\toutput Z\n);\n\tparameter DEL_MODE = \"USER_DEFINED\";\n\tparameter DEL_VALUE = 0;\nendmodule\n\n(* blackbox *)\nmodule IDDRX1F(\n\tinput D, SCLK, RST,\n\toutput Q0, Q1\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule IDDRX2F(\n\tinput D, SCLK, ECLK, RST, ALIGNWD,\n\toutput Q0, Q1, Q2, Q3\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule IDDR71B(\n\tinput D, SCLK, ECLK, RST, ALIGNWD,\n\toutput Q0, Q1, Q2, Q3, Q4, Q5, Q6\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule IDDRX2DQA(\n\tinput D, DQSR90, ECLK, SCLK, RST,\n\tinput RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,\n\toutput Q0, Q1, Q2, Q3, QWL\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule ODDRX1F(\n\tinput SCLK, RST, D0, D1,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule ODDRX2F(\n\tinput SCLK, ECLK, RST, D0, D1, D2, D3,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule ODDR71B(\n\tinput SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule OSHX2A(\n\tinput D0, D1, RST, ECLK, SCLK,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQA(\n\tinput D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQSB(\n\tinput D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQA(\n\tinput T0, T1, SCLK, ECLK, DQSW270, RST,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\n\tparameter REGSET = \"SET\";\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQSA(\n\tinput T0, T1, SCLK, ECLK, DQSW, RST,\n\toutput Q\n);\n\tparameter GSR = \"ENABLED\";\n\tparameter REGSET = \"SET\";\nendmodule\n\n(* blackbox *)\nmodule DQSBUFM(\n\tinput DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,\n\tinput ECLK, SCLK,\n\tinput DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,\n\tinput DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, \n\tinput RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,\n\toutput DQSR90, DQSW, DQSW270,\n\toutput RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,\n\toutput DATAVALID, BURSTDET, RDCFLAG, WRCFLAG\n);\n\tparameter DQS_LI_DEL_ADJ = \"FACTORYONLY\";\n\tparameter DQS_LI_DEL_VAL = 0;\n\tparameter DQS_LO_DEL_ADJ = \"FACTORYONLY\";\n\tparameter DQS_LO_DEL_VAL = 0;\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule DDRDLLA(\n\tinput CLK, RST, UDDCNTLN, FREEZE,\n\toutput LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0\n);\n\tparameter FORCE_MAX_DELAY = \"NO\";\n\tparameter GSR = \"ENABLED\";\nendmodule\n\n(* blackbox *)\nmodule DLLDELD(\n\tinput A, DDRDEL, LOADN, MOVE, DIRECTION,\n\toutput Z, CFLAG\n);\n\tparameter DEL_ADJ = \"PLUS\";\n\tparameter DEL_VAL = 0;\nendmodule\n\n(* blackbox *)\nmodule CLKDIVF(\n\tinput CLKI, RST, ALIGNWD,\n\toutput CDIVX\n);\n\tparameter GSR = \"DISABLED\";\n\tparameter DIV = \"2.0\";\nendmodule\n\n(* blackbox *)\nmodule ECLKSYNCB(\n\tinput ECLKI, STOP,\n\toutput ECLKO\n);\nendmodule\n\n(* blackbox *)\nmodule ECLKBRIDGECS(\n\tinput CLK0, CLK1, SEL,\n\toutput ECSOUT\n);\nendmodule\n\n(* blackbox *)\nmodule DCCA(\n\tinput CLKI, CE,\n\toutput CLKO\n);\nendmodule\n\n(* blackbox *)\nmodule DCSC(\n\tinput CLK1, CLK0,\n\tinput SEL1, SEL0,\n\tinput MODESEL,\n\toutput DCSOUT\n);\n\tparameter DCSMODE = \"POS\";\nendmodule\n\n(* blackbox *) (* keep *)\nmodule DCUA(\n\t(* iopad_external_pin *)\n\tinput CH0_HDINP,\n\t(* iopad_external_pin *)\n\tinput CH1_HDINP,\n\t(* iopad_external_pin *)\n\tinput CH0_HDINN,\n\t(* iopad_external_pin *)\n\tinput CH1_HDINN,\n\tinput D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,\n\tinput CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,\n\tinput CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,\n\tinput CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,\n\tinput CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,\n\tinput CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,\n\tinput CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,\n\tinput CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,\n\tinput CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,\n\tinput CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,\n\tinput CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,\n\tinput CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,\n\tinput CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,\n\tinput D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,\n\tinput D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,\n\tinput CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,\n\tinput D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,\n\tinput D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,\n\tinput D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,\n\toutput CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,\n\toutput CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,\n\toutput CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,\n\toutput CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,\n\toutput CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,\n\toutput CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,\n\toutput CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,\n\toutput CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,\n\toutput CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,\n\toutput CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,\n\toutput CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,\n\toutput CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,\n\toutput D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,\n\toutput D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,\n\n\tinput  D_REFCLKI,\n\toutput D_FFS_PLOL\n);\n\tparameter CH0_AUTO_CALIB_EN = \"0b0\";\n\tparameter CH0_AUTO_FACQ_EN = \"0b0\";\n\tparameter CH0_BAND_THRESHOLD = \"0b000000\";\n\tparameter CH0_CALIB_CK_MODE = \"0b0\";\n\tparameter CH0_CC_MATCH_1 = \"0b0000000000\";\n\tparameter CH0_CC_MATCH_2 = \"0b0000000000\";\n\tparameter CH0_CC_MATCH_3 = \"0b0000000000\";\n\tparameter CH0_CC_MATCH_4 = \"0b0000000000\";\n\tparameter CH0_CDR_CNT4SEL = \"0b00\";\n\tparameter CH0_CDR_CNT8SEL = \"0b00\";\n\tparameter CH0_CTC_BYPASS = \"0b0\";\n\tparameter CH0_DCOATDCFG = \"0b00\";\n\tparameter CH0_DCOATDDLY = \"0b00\";\n\tparameter CH0_DCOBYPSATD = \"0b0\";\n\tparameter CH0_DCOCALDIV = \"0b000\";\n\tparameter CH0_DCOCTLGI = \"0b000\";\n\tparameter CH0_DCODISBDAVOID = \"0b0\";\n\tparameter CH0_DCOFLTDAC = \"0b00\";\n\tparameter CH0_DCOFTNRG = \"0b000\";\n\tparameter CH0_DCOIOSTUNE = \"0b000\";\n\tparameter CH0_DCOITUNE = \"0b00\";\n\tparameter CH0_DCOITUNE4LSB = \"0b000\";\n\tparameter CH0_DCOIUPDNX2 = \"0b0\";\n\tparameter CH0_DCONUOFLSB = \"0b000\";\n\tparameter CH0_DCOSCALEI = \"0b00\";\n\tparameter CH0_DCOSTARTVAL = \"0b000\";\n\tparameter CH0_DCOSTEP = \"0b00\";\n\tparameter CH0_DEC_BYPASS = \"0b0\";\n\tparameter CH0_ENABLE_CG_ALIGN = \"0b0\";\n\tparameter CH0_ENC_BYPASS = \"0b0\";\n\tparameter CH0_FF_RX_F_CLK_DIS = \"0b0\";\n\tparameter CH0_FF_RX_H_CLK_EN = \"0b0\";\n\tparameter CH0_FF_TX_F_CLK_DIS = \"0b0\";\n\tparameter CH0_FF_TX_H_CLK_EN = \"0b0\";\n\tparameter CH0_GE_AN_ENABLE = \"0b0\";\n\tparameter CH0_INVERT_RX = \"0b0\";\n\tparameter CH0_INVERT_TX = \"0b0\";\n\tparameter CH0_LDR_CORE2TX_SEL = \"0b0\";\n\tparameter CH0_LDR_RX2CORE_SEL = \"0b0\";\n\tparameter CH0_LEQ_OFFSET_SEL = \"0b0\";\n\tparameter CH0_LEQ_OFFSET_TRIM = \"0b000\";\n\tparameter CH0_LSM_DISABLE = \"0b0\";\n\tparameter CH0_MATCH_2_ENABLE = \"0b0\";\n\tparameter CH0_MATCH_4_ENABLE = \"0b0\";\n\tparameter CH0_MIN_IPG_CNT = \"0b00\";\n\tparameter CH0_PCIE_EI_EN = \"0b0\";\n\tparameter CH0_PCIE_MODE = \"0b0\";\n\tparameter CH0_PCS_DET_TIME_SEL = \"0b00\";\n\tparameter CH0_PDEN_SEL = \"0b0\";\n\tparameter CH0_PRBS_ENABLE = \"0b0\";\n\tparameter CH0_PRBS_LOCK = \"0b0\";\n\tparameter CH0_PRBS_SELECTION = \"0b0\";\n\tparameter CH0_RATE_MODE_RX = \"0b0\";\n\tparameter CH0_RATE_MODE_TX = \"0b0\";\n\tparameter CH0_RCV_DCC_EN = \"0b0\";\n\tparameter CH0_REG_BAND_OFFSET = \"0b0000\";\n\tparameter CH0_REG_BAND_SEL = \"0b000000\";\n\tparameter CH0_REG_IDAC_EN = \"0b0\";\n\tparameter CH0_REG_IDAC_SEL = \"0b0000000000\";\n\tparameter CH0_REQ_EN = \"0b0\";\n\tparameter CH0_REQ_LVL_SET = \"0b00\";\n\tparameter CH0_RIO_MODE = \"0b0\";\n\tparameter CH0_RLOS_SEL = \"0b0\";\n\tparameter CH0_RPWDNB = \"0b0\";\n\tparameter CH0_RTERM_RX = \"0b00000\";\n\tparameter CH0_RTERM_TX = \"0b00000\";\n\tparameter CH0_RXIN_CM = \"0b00\";\n\tparameter CH0_RXTERM_CM = \"0b00\";\n\tparameter CH0_RX_DCO_CK_DIV = \"0b000\";\n\tparameter CH0_RX_DIV11_SEL = \"0b0\";\n\tparameter CH0_RX_GEAR_BYPASS = \"0b0\";\n\tparameter CH0_RX_GEAR_MODE = \"0b0\";\n\tparameter CH0_RX_LOS_CEQ = \"0b00\";\n\tparameter CH0_RX_LOS_EN = \"0b0\";\n\tparameter CH0_RX_LOS_HYST_EN = \"0b0\";\n\tparameter CH0_RX_LOS_LVL = \"0b000\";\n\tparameter CH0_RX_RATE_SEL = \"0b0000\";\n\tparameter CH0_RX_SB_BYPASS = \"0b0\";\n\tparameter CH0_SB_BYPASS = \"0b0\";\n\tparameter CH0_SEL_SD_RX_CLK = \"0b0\";\n\tparameter CH0_TDRV_DAT_SEL = \"0b00\";\n\tparameter CH0_TDRV_POST_EN = \"0b0\";\n\tparameter CH0_TDRV_PRE_EN = \"0b0\";\n\tparameter CH0_TDRV_SLICE0_CUR = \"0b000\";\n\tparameter CH0_TDRV_SLICE0_SEL = \"0b00\";\n\tparameter CH0_TDRV_SLICE1_CUR = \"0b000\";\n\tparameter CH0_TDRV_SLICE1_SEL = \"0b00\";\n\tparameter CH0_TDRV_SLICE2_CUR = \"0b00\";\n\tparameter CH0_TDRV_SLICE2_SEL = \"0b00\";\n\tparameter CH0_TDRV_SLICE3_CUR = \"0b00\";\n\tparameter CH0_TDRV_SLICE3_SEL = \"0b00\";\n\tparameter CH0_TDRV_SLICE4_CUR = \"0b00\";\n\tparameter CH0_TDRV_SLICE4_SEL = \"0b00\";\n\tparameter CH0_TDRV_SLICE5_CUR = \"0b00\";\n\tparameter CH0_TDRV_SLICE5_SEL = \"0b00\";\n\tparameter CH0_TPWDNB = \"0b0\";\n\tparameter CH0_TX_CM_SEL = \"0b00\";\n\tparameter CH0_TX_DIV11_SEL = \"0b0\";\n\tparameter CH0_TX_GEAR_BYPASS = \"0b0\";\n\tparameter CH0_TX_GEAR_MODE = \"0b0\";\n\tparameter CH0_TX_POST_SIGN = \"0b0\";\n\tparameter CH0_TX_PRE_SIGN = \"0b0\";\n\tparameter CH0_UC_MODE = \"0b0\";\n\tparameter CH0_UDF_COMMA_A = \"0b0000000000\";\n\tparameter CH0_UDF_COMMA_B = \"0b0000000000\";\n\tparameter CH0_UDF_COMMA_MASK = \"0b0000000000\";\n\tparameter CH0_WA_BYPASS = \"0b0\";\n\tparameter CH0_WA_MODE = \"0b0\";\n\tparameter CH1_AUTO_CALIB_EN = \"0b0\";\n\tparameter CH1_AUTO_FACQ_EN = \"0b0\";\n\tparameter CH1_BAND_THRESHOLD = \"0b000000\";\n\tparameter CH1_CALIB_CK_MODE = \"0b0\";\n\tparameter CH1_CC_MATCH_1 = \"0b0000000000\";\n\tparameter CH1_CC_MATCH_2 = \"0b0000000000\";\n\tparameter CH1_CC_MATCH_3 = \"0b0000000000\";\n\tparameter CH1_CC_MATCH_4 = \"0b0000000000\";\n\tparameter CH1_CDR_CNT4SEL = \"0b00\";\n\tparameter CH1_CDR_CNT8SEL = \"0b00\";\n\tparameter CH1_CTC_BYPASS = \"0b0\";\n\tparameter CH1_DCOATDCFG = \"0b00\";\n\tparameter CH1_DCOATDDLY = \"0b00\";\n\tparameter CH1_DCOBYPSATD = \"0b0\";\n\tparameter CH1_DCOCALDIV = \"0b000\";\n\tparameter CH1_DCOCTLGI = \"0b000\";\n\tparameter CH1_DCODISBDAVOID = \"0b0\";\n\tparameter CH1_DCOFLTDAC = \"0b00\";\n\tparameter CH1_DCOFTNRG = \"0b000\";\n\tparameter CH1_DCOIOSTUNE = \"0b000\";\n\tparameter CH1_DCOITUNE = \"0b00\";\n\tparameter CH1_DCOITUNE4LSB = \"0b000\";\n\tparameter CH1_DCOIUPDNX2 = \"0b0\";\n\tparameter CH1_DCONUOFLSB = \"0b000\";\n\tparameter CH1_DCOSCALEI = \"0b00\";\n\tparameter CH1_DCOSTARTVAL = \"0b000\";\n\tparameter CH1_DCOSTEP = \"0b00\";\n\tparameter CH1_DEC_BYPASS = \"0b0\";\n\tparameter CH1_ENABLE_CG_ALIGN = \"0b0\";\n\tparameter CH1_ENC_BYPASS = \"0b0\";\n\tparameter CH1_FF_RX_F_CLK_DIS = \"0b0\";\n\tparameter CH1_FF_RX_H_CLK_EN = \"0b0\";\n\tparameter CH1_FF_TX_F_CLK_DIS = \"0b0\";\n\tparameter CH1_FF_TX_H_CLK_EN = \"0b0\";\n\tparameter CH1_GE_AN_ENABLE = \"0b0\";\n\tparameter CH1_INVERT_RX = \"0b0\";\n\tparameter CH1_INVERT_TX = \"0b0\";\n\tparameter CH1_LDR_CORE2TX_SEL = \"0b0\";\n\tparameter CH1_LDR_RX2CORE_SEL = \"0b0\";\n\tparameter CH1_LEQ_OFFSET_SEL = \"0b0\";\n\tparameter CH1_LEQ_OFFSET_TRIM = \"0b000\";\n\tparameter CH1_LSM_DISABLE = \"0b0\";\n\tparameter CH1_MATCH_2_ENABLE = \"0b0\";\n\tparameter CH1_MATCH_4_ENABLE = \"0b0\";\n\tparameter CH1_MIN_IPG_CNT = \"0b00\";\n\tparameter CH1_PCIE_EI_EN = \"0b0\";\n\tparameter CH1_PCIE_MODE = \"0b0\";\n\tparameter CH1_PCS_DET_TIME_SEL = \"0b00\";\n\tparameter CH1_PDEN_SEL = \"0b0\";\n\tparameter CH1_PRBS_ENABLE = \"0b0\";\n\tparameter CH1_PRBS_LOCK = \"0b0\";\n\tparameter CH1_PRBS_SELECTION = \"0b0\";\n\tparameter CH1_RATE_MODE_RX = \"0b0\";\n\tparameter CH1_RATE_MODE_TX = \"0b0\";\n\tparameter CH1_RCV_DCC_EN = \"0b0\";\n\tparameter CH1_REG_BAND_OFFSET = \"0b0000\";\n\tparameter CH1_REG_BAND_SEL = \"0b000000\";\n\tparameter CH1_REG_IDAC_EN = \"0b0\";\n\tparameter CH1_REG_IDAC_SEL = \"0b0000000000\";\n\tparameter CH1_REQ_EN = \"0b0\";\n\tparameter CH1_REQ_LVL_SET = \"0b00\";\n\tparameter CH1_RIO_MODE = \"0b0\";\n\tparameter CH1_RLOS_SEL = \"0b0\";\n\tparameter CH1_RPWDNB = \"0b0\";\n\tparameter CH1_RTERM_RX = \"0b00000\";\n\tparameter CH1_RTERM_TX = \"0b00000\";\n\tparameter CH1_RXIN_CM = \"0b00\";\n\tparameter CH1_RXTERM_CM = \"0b00\";\n\tparameter CH1_RX_DCO_CK_DIV = \"0b000\";\n\tparameter CH1_RX_DIV11_SEL = \"0b0\";\n\tparameter CH1_RX_GEAR_BYPASS = \"0b0\";\n\tparameter CH1_RX_GEAR_MODE = \"0b0\";\n\tparameter CH1_RX_LOS_CEQ = \"0b00\";\n\tparameter CH1_RX_LOS_EN = \"0b0\";\n\tparameter CH1_RX_LOS_HYST_EN = \"0b0\";\n\tparameter CH1_RX_LOS_LVL = \"0b000\";\n\tparameter CH1_RX_RATE_SEL = \"0b0000\";\n\tparameter CH1_RX_SB_BYPASS = \"0b0\";\n\tparameter CH1_SB_BYPASS = \"0b0\";\n\tparameter CH1_SEL_SD_RX_CLK = \"0b0\";\n\tparameter CH1_TDRV_DAT_SEL = \"0b00\";\n\tparameter CH1_TDRV_POST_EN = \"0b0\";\n\tparameter CH1_TDRV_PRE_EN = \"0b0\";\n\tparameter CH1_TDRV_SLICE0_CUR = \"0b000\";\n\tparameter CH1_TDRV_SLICE0_SEL = \"0b00\";\n\tparameter CH1_TDRV_SLICE1_CUR = \"0b000\";\n\tparameter CH1_TDRV_SLICE1_SEL = \"0b00\";\n\tparameter CH1_TDRV_SLICE2_CUR = \"0b00\";\n\tparameter CH1_TDRV_SLICE2_SEL = \"0b00\";\n\tparameter CH1_TDRV_SLICE3_CUR = \"0b00\";\n\tparameter CH1_TDRV_SLICE3_SEL = \"0b00\";\n\tparameter CH1_TDRV_SLICE4_CUR = \"0b00\";\n\tparameter CH1_TDRV_SLICE4_SEL = \"0b00\";\n\tparameter CH1_TDRV_SLICE5_CUR = \"0b00\";\n\tparameter CH1_TDRV_SLICE5_SEL = \"0b00\";\n\tparameter CH1_TPWDNB = \"0b0\";\n\tparameter CH1_TX_CM_SEL = \"0b00\";\n\tparameter CH1_TX_DIV11_SEL = \"0b0\";\n\tparameter CH1_TX_GEAR_BYPASS = \"0b0\";\n\tparameter CH1_TX_GEAR_MODE = \"0b0\";\n\tparameter CH1_TX_POST_SIGN = \"0b0\";\n\tparameter CH1_TX_PRE_SIGN = \"0b0\";\n\tparameter CH1_UC_MODE = \"0b0\";\n\tparameter CH1_UDF_COMMA_A = \"0b0000000000\";\n\tparameter CH1_UDF_COMMA_B = \"0b0000000000\";\n\tparameter CH1_UDF_COMMA_MASK = \"0b0000000000\";\n\tparameter CH1_WA_BYPASS = \"0b0\";\n\tparameter CH1_WA_MODE = \"0b0\";\n\tparameter D_BITCLK_FROM_ND_EN = \"0b0\";\n\tparameter D_BITCLK_LOCAL_EN = \"0b0\";\n\tparameter D_BITCLK_ND_EN = \"0b0\";\n\tparameter D_BUS8BIT_SEL = \"0b0\";\n\tparameter D_CDR_LOL_SET = \"0b00\";\n\tparameter D_CMUSETBIASI = \"0b00\";\n\tparameter D_CMUSETI4CPP = \"0b0000\";\n\tparameter D_CMUSETI4CPZ = \"0b0000\";\n\tparameter D_CMUSETI4VCO = \"0b00\";\n\tparameter D_CMUSETICP4P = \"0b00\";\n\tparameter D_CMUSETICP4Z = \"0b000\";\n\tparameter D_CMUSETINITVCT = \"0b00\";\n\tparameter D_CMUSETISCL4VCO = \"0b000\";\n\tparameter D_CMUSETP1GM = \"0b000\";\n\tparameter D_CMUSETP2AGM = \"0b000\";\n\tparameter D_CMUSETZGM = \"0b000\";\n\tparameter D_DCO_CALIB_TIME_SEL = \"0b00\";\n\tparameter D_HIGH_MARK = \"0b0000\";\n\tparameter D_IB_PWDNB = \"0b0\";\n\tparameter D_ISETLOS = \"0b00000000\";\n\tparameter D_LOW_MARK = \"0b0000\";\n\tparameter D_MACROPDB = \"0b0\";\n\tparameter D_PD_ISET = \"0b00\";\n\tparameter D_PLL_LOL_SET = \"0b00\";\n\tparameter D_REFCK_MODE = \"0b000\";\n\tparameter D_REQ_ISET = \"0b000\";\n\tparameter D_RG_EN = \"0b0\";\n\tparameter D_RG_SET = \"0b00\";\n\tparameter D_SETICONST_AUX = \"0b00\";\n\tparameter D_SETICONST_CH = \"0b00\";\n\tparameter D_SETIRPOLY_AUX = \"0b00\";\n\tparameter D_SETIRPOLY_CH = \"0b00\";\n\tparameter D_SETPLLRC = \"0b000000\";\n\tparameter D_SYNC_LOCAL_EN = \"0b0\";\n\tparameter D_SYNC_ND_EN = \"0b0\";\n\tparameter D_TXPLL_PWDNB = \"0b0\";\n\tparameter D_TX_VCO_CK_DIV = \"0b000\";\n\tparameter D_XGE_MODE = \"0b0\";\n\n// These parameters don't do anything but are\n// needed for compatibility with Diamond\n\tparameter D_TX_MAX_RATE = \"2.5\";\n\tparameter D_RX_MAX_RATE = \"2.5\";\n\tparameter CH0_TXAMPLITUDE = \"0d1300\";\n\tparameter CH1_TXAMPLITUDE = \"0d1300\";\n\tparameter CH0_PROTOCOL = \"8B10B\";\n\tparameter CH1_PROTOCOL = \"8B10B\";\n\tparameter CH0_CDR_MAX_RATE = \"2.5\";\n\tparameter CH1_CDR_MAX_RATE = \"2.5\";\n\tparameter CH0_TXDEPRE = \"DISABLED\";\n\tparameter CH1_TXDEPRE = \"DISABLED\";\n\tparameter CH0_TXDEPOST = \"DISABLED\";\n\tparameter CH1_TXDEPOST = \"DISABLED\";\nendmodule\n\n(* blackbox *)\nmodule EXTREFB (\n\t(* iopad_external_pin *)\n\tinput REFCLKP,\n\t(* iopad_external_pin *)\n\tinput REFCLKN,\n\toutput REFCLKO\n);\n\tparameter REFCK_PWDNB = \"0b0\";\n\tparameter REFCK_RTERM = \"0b0\";\n\tparameter REFCK_DCBIAS_EN = \"0b0\";\nendmodule\n\n(* blackbox *)\nmodule PCSCLKDIV (\n\tinput CLKI, RST, SEL2, SEL1, SEL0,\n\toutput CDIV1, CDIVX\n);\n\tparameter GSR = \"DISABLED\";\nendmodule\n\n// Note: this module is not marked keep as we want it swept away in synth (sim use only)\n(* blackbox *)\nmodule PUR (\n\tinput PUR\n);\n\tparameter RST_PULSE = 1;\nendmodule\n\n(* blackbox, keep *)\nmodule GSR (\n\tinput GSR\n);\nendmodule\n\n(* blackbox, keep *)\nmodule SGSR (\n\tinput GSR, CLK\n);\nendmodule\n\n\n(* blackbox *)\nmodule PDPW16KD (\n\tinput DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,\n\tinput DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,\n\tinput ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,\n\tinput BE3,  BE2,  BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,\n\tinput ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,\n\tinput CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,\n\toutput DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,\n\toutput DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0\n);\n\tparameter DATA_WIDTH_W = 36;\n\tparameter DATA_WIDTH_R = 36;\n\tparameter GSR = \"ENABLED\";\n\n\tparameter REGMODE = \"NOREG\";\n\n\tparameter RESETMODE = \"SYNC\";\n\tparameter ASYNC_RESET_RELEASE = \"SYNC\";\n\n\tparameter CSDECODE_W = \"0b000\";\n\tparameter CSDECODE_R = \"0b000\";\n\n\tparameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_DATA = \"STATIC\";\n\tparameter CLKWMUX = \"CLKW\";\n\tparameter CLKRMUX = \"CLKR\";\n\nendmodule\n",
+            "ccu2c_sim.vh": "// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule CCU2C(\n\t(* abc9_carry *)\n\tinput  CIN,\n\tinput  A0, B0, C0, D0, A1, B1, C1, D1,\n\toutput S0, S1,\n\t(* abc9_carry *)\n\toutput COUT\n);\n\tparameter [15:0] INIT0 = 16'h0000;\n\tparameter [15:0] INIT1 = 16'h0000;\n\tparameter INJECT1_0 = \"YES\";\n\tparameter INJECT1_1 = \"YES\";\n\n\t// First half\n\twire LUT4_0, LUT2_0;\n\tLUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));\n\tLUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));\n\twire gated_cin_0 = (INJECT1_0 == \"YES\") ? 1'b0 : CIN;\n\tassign S0 = LUT4_0 ^ gated_cin_0;\n\n\twire gated_lut2_0 = (INJECT1_0 == \"YES\") ? 1'b0 : LUT2_0;\n\twire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);\n\n\t// Second half\n\twire LUT4_1, LUT2_1;\n\tLUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));\n\tLUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));\n\twire gated_cin_1 = (INJECT1_1 == \"YES\") ? 1'b0 : cout_0;\n\tassign S1 = LUT4_1 ^ gated_cin_1;\n\n\twire gated_lut2_1 = (INJECT1_1 == \"YES\") ? 1'b0 : LUT2_1;\n\tassign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);\n\n\tspecify\n\t\t(A0 => S0) = 379;\n\t\t(B0 => S0) = 379;\n\t\t(C0 => S0) = 275;\n\t\t(D0 => S0) = 141;\n\t\t(CIN => S0) = 257;\n\t\t(A0 => S1) = 630;\n\t\t(B0 => S1) = 630;\n\t\t(C0 => S1) = 526;\n\t\t(D0 => S1) = 392;\n\t\t(A1 => S1) = 379;\n\t\t(B1 => S1) = 379;\n\t\t(C1 => S1) = 275;\n\t\t(D1 => S1) = 141;\n\t\t(CIN => S1) = 273;\n\t\t(A0 => COUT) = 516;\n\t\t(B0 => COUT) = 516;\n\t\t(C0 => COUT) = 412;\n\t\t(D0 => COUT) = 278;\n\t\t(A1 => COUT) = 516;\n\t\t(B1 => COUT) = 516;\n\t\t(C1 => COUT) = 412;\n\t\t(D1 => COUT) = 278;\n\t\t(CIN => COUT) = 43;\n\tendspecify\nendmodule\n",
+            "cells_bb.v": "// Created by cells_xtra.py from Lattice models\n\n(* blackbox *) (* keep *)\nmodule GSR (...);\n    input GSR;\nendmodule\n\n(* blackbox *)\nmodule PUR (...);\n    parameter RST_PULSE = 1;\n    input PUR;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule SGSR (...);\n    input GSR;\n    input CLK;\nendmodule\n\n(* blackbox *)\nmodule PDPW16KD (...);\n    parameter CLKRMUX = \"CLKR\";\n    parameter CLKWMUX = \"CLKW\";\n    parameter DATA_WIDTH_W = 36;\n    parameter DATA_WIDTH_R = 36;\n    parameter GSR = \"ENABLED\";\n    parameter REGMODE = \"NOREG\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter CSDECODE_W = \"0b000\";\n    parameter CSDECODE_R = \"0b000\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INIT_DATA = \"STATIC\";\n    input DI35;\n    input DI34;\n    input DI33;\n    input DI32;\n    input DI31;\n    input DI30;\n    input DI29;\n    input DI28;\n    input DI27;\n    input DI26;\n    input DI25;\n    input DI24;\n    input DI23;\n    input DI22;\n    input DI21;\n    input DI20;\n    input DI19;\n    input DI18;\n    input DI17;\n    input DI16;\n    input DI15;\n    input DI14;\n    input DI13;\n    input DI12;\n    input DI11;\n    input DI10;\n    input DI9;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input ADW8;\n    input ADW7;\n    input ADW6;\n    input ADW5;\n    input ADW4;\n    input ADW3;\n    input ADW2;\n    input ADW1;\n    input ADW0;\n    input BE3;\n    input BE2;\n    input BE1;\n    input BE0;\n    input CEW;\n    input CLKW;\n    input CSW2;\n    input CSW1;\n    input CSW0;\n    input ADR13;\n    input ADR12;\n    input ADR11;\n    input ADR10;\n    input ADR9;\n    input ADR8;\n    input ADR7;\n    input ADR6;\n    input ADR5;\n    input ADR4;\n    input ADR3;\n    input ADR2;\n    input ADR1;\n    input ADR0;\n    input CER;\n    input OCER;\n    input CLKR;\n    input CSR2;\n    input CSR1;\n    input CSR0;\n    input RST;\n    output DO35;\n    output DO34;\n    output DO33;\n    output DO32;\n    output DO31;\n    output DO30;\n    output DO29;\n    output DO28;\n    output DO27;\n    output DO26;\n    output DO25;\n    output DO24;\n    output DO23;\n    output DO22;\n    output DO21;\n    output DO20;\n    output DO19;\n    output DO18;\n    output DO17;\n    output DO16;\n    output DO15;\n    output DO14;\n    output DO13;\n    output DO12;\n    output DO11;\n    output DO10;\n    output DO9;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule MULT18X18D (...);\n    parameter REG_INPUTA_CLK = \"NONE\";\n    parameter REG_INPUTA_CE = \"CE0\";\n    parameter REG_INPUTA_RST = \"RST0\";\n    parameter REG_INPUTB_CLK = \"NONE\";\n    parameter REG_INPUTB_CE = \"CE0\";\n    parameter REG_INPUTB_RST = \"RST0\";\n    parameter REG_INPUTC_CLK = \"NONE\";\n    parameter REG_INPUTC_CE = \"CE0\";\n    parameter REG_INPUTC_RST = \"RST0\";\n    parameter REG_PIPELINE_CLK = \"NONE\";\n    parameter REG_PIPELINE_CE = \"CE0\";\n    parameter REG_PIPELINE_RST = \"RST0\";\n    parameter REG_OUTPUT_CLK = \"NONE\";\n    parameter REG_OUTPUT_CE = \"CE0\";\n    parameter REG_OUTPUT_RST = \"RST0\";\n    parameter CLK0_DIV = \"ENABLED\";\n    parameter CLK1_DIV = \"ENABLED\";\n    parameter CLK2_DIV = \"ENABLED\";\n    parameter CLK3_DIV = \"ENABLED\";\n    parameter HIGHSPEED_CLK = \"NONE\";\n    parameter GSR = \"ENABLED\";\n    parameter CAS_MATCH_REG = \"FALSE\";\n    parameter SOURCEB_MODE = \"B_SHIFT\";\n    parameter MULT_BYPASS = \"DISABLED\";\n    parameter RESETMODE = \"SYNC\";\n    input A17;\n    input A16;\n    input A15;\n    input A14;\n    input A13;\n    input A12;\n    input A11;\n    input A10;\n    input A9;\n    input A8;\n    input A7;\n    input A6;\n    input A5;\n    input A4;\n    input A3;\n    input A2;\n    input A1;\n    input A0;\n    input B17;\n    input B16;\n    input B15;\n    input B14;\n    input B13;\n    input B12;\n    input B11;\n    input B10;\n    input B9;\n    input B8;\n    input B7;\n    input B6;\n    input B5;\n    input B4;\n    input B3;\n    input B2;\n    input B1;\n    input B0;\n    input C17;\n    input C16;\n    input C15;\n    input C14;\n    input C13;\n    input C12;\n    input C11;\n    input C10;\n    input C9;\n    input C8;\n    input C7;\n    input C6;\n    input C5;\n    input C4;\n    input C3;\n    input C2;\n    input C1;\n    input C0;\n    input SIGNEDA;\n    input SIGNEDB;\n    input SOURCEA;\n    input SOURCEB;\n    input CLK3;\n    input CLK2;\n    input CLK1;\n    input CLK0;\n    input CE3;\n    input CE2;\n    input CE1;\n    input CE0;\n    input RST3;\n    input RST2;\n    input RST1;\n    input RST0;\n    input SRIA17;\n    input SRIA16;\n    input SRIA15;\n    input SRIA14;\n    input SRIA13;\n    input SRIA12;\n    input SRIA11;\n    input SRIA10;\n    input SRIA9;\n    input SRIA8;\n    input SRIA7;\n    input SRIA6;\n    input SRIA5;\n    input SRIA4;\n    input SRIA3;\n    input SRIA2;\n    input SRIA1;\n    input SRIA0;\n    input SRIB17;\n    input SRIB16;\n    input SRIB15;\n    input SRIB14;\n    input SRIB13;\n    input SRIB12;\n    input SRIB11;\n    input SRIB10;\n    input SRIB9;\n    input SRIB8;\n    input SRIB7;\n    input SRIB6;\n    input SRIB5;\n    input SRIB4;\n    input SRIB3;\n    input SRIB2;\n    input SRIB1;\n    input SRIB0;\n    output SROA17;\n    output SROA16;\n    output SROA15;\n    output SROA14;\n    output SROA13;\n    output SROA12;\n    output SROA11;\n    output SROA10;\n    output SROA9;\n    output SROA8;\n    output SROA7;\n    output SROA6;\n    output SROA5;\n    output SROA4;\n    output SROA3;\n    output SROA2;\n    output SROA1;\n    output SROA0;\n    output SROB17;\n    output SROB16;\n    output SROB15;\n    output SROB14;\n    output SROB13;\n    output SROB12;\n    output SROB11;\n    output SROB10;\n    output SROB9;\n    output SROB8;\n    output SROB7;\n    output SROB6;\n    output SROB5;\n    output SROB4;\n    output SROB3;\n    output SROB2;\n    output SROB1;\n    output SROB0;\n    output ROA17;\n    output ROA16;\n    output ROA15;\n    output ROA14;\n    output ROA13;\n    output ROA12;\n    output ROA11;\n    output ROA10;\n    output ROA9;\n    output ROA8;\n    output ROA7;\n    output ROA6;\n    output ROA5;\n    output ROA4;\n    output ROA3;\n    output ROA2;\n    output ROA1;\n    output ROA0;\n    output ROB17;\n    output ROB16;\n    output ROB15;\n    output ROB14;\n    output ROB13;\n    output ROB12;\n    output ROB11;\n    output ROB10;\n    output ROB9;\n    output ROB8;\n    output ROB7;\n    output ROB6;\n    output ROB5;\n    output ROB4;\n    output ROB3;\n    output ROB2;\n    output ROB1;\n    output ROB0;\n    output ROC17;\n    output ROC16;\n    output ROC15;\n    output ROC14;\n    output ROC13;\n    output ROC12;\n    output ROC11;\n    output ROC10;\n    output ROC9;\n    output ROC8;\n    output ROC7;\n    output ROC6;\n    output ROC5;\n    output ROC4;\n    output ROC3;\n    output ROC2;\n    output ROC1;\n    output ROC0;\n    output P35;\n    output P34;\n    output P33;\n    output P32;\n    output P31;\n    output P30;\n    output P29;\n    output P28;\n    output P27;\n    output P26;\n    output P25;\n    output P24;\n    output P23;\n    output P22;\n    output P21;\n    output P20;\n    output P19;\n    output P18;\n    output P17;\n    output P16;\n    output P15;\n    output P14;\n    output P13;\n    output P12;\n    output P11;\n    output P10;\n    output P9;\n    output P8;\n    output P7;\n    output P6;\n    output P5;\n    output P4;\n    output P3;\n    output P2;\n    output P1;\n    output P0;\n    output SIGNEDP;\nendmodule\n\n(* blackbox *)\nmodule ALU54B (...);\n    parameter REG_INPUTC0_CLK = \"NONE\";\n    parameter REG_INPUTC0_CE = \"CE0\";\n    parameter REG_INPUTC0_RST = \"RST0\";\n    parameter REG_INPUTC1_CLK = \"NONE\";\n    parameter REG_INPUTC1_CE = \"CE0\";\n    parameter REG_INPUTC1_RST = \"RST0\";\n    parameter REG_OPCODEOP0_0_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_0_CE = \"CE0\";\n    parameter REG_OPCODEOP0_0_RST = \"RST0\";\n    parameter REG_OPCODEOP1_0_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_1_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_1_CE = \"CE0\";\n    parameter REG_OPCODEOP0_1_RST = \"RST0\";\n    parameter REG_OPCODEOP1_1_CLK = \"NONE\";\n    parameter REG_OPCODEIN_0_CLK = \"NONE\";\n    parameter REG_OPCODEIN_0_CE = \"CE0\";\n    parameter REG_OPCODEIN_0_RST = \"RST0\";\n    parameter REG_OPCODEIN_1_CLK = \"NONE\";\n    parameter REG_OPCODEIN_1_CE = \"CE0\";\n    parameter REG_OPCODEIN_1_RST = \"RST0\";\n    parameter REG_OUTPUT0_CLK = \"NONE\";\n    parameter REG_OUTPUT0_CE = \"CE0\";\n    parameter REG_OUTPUT0_RST = \"RST0\";\n    parameter REG_OUTPUT1_CLK = \"NONE\";\n    parameter REG_OUTPUT1_CE = \"CE0\";\n    parameter REG_OUTPUT1_RST = \"RST0\";\n    parameter REG_FLAG_CLK = \"NONE\";\n    parameter REG_FLAG_CE = \"CE0\";\n    parameter REG_FLAG_RST = \"RST0\";\n    parameter MCPAT_SOURCE = \"STATIC\";\n    parameter MASKPAT_SOURCE = \"STATIC\";\n    parameter MASK01 = \"0x00000000000000\";\n    parameter REG_INPUTCFB_CLK = \"NONE\";\n    parameter REG_INPUTCFB_CE = \"CE0\";\n    parameter REG_INPUTCFB_RST = \"RST0\";\n    parameter CLK0_DIV = \"ENABLED\";\n    parameter CLK1_DIV = \"ENABLED\";\n    parameter CLK2_DIV = \"ENABLED\";\n    parameter CLK3_DIV = \"ENABLED\";\n    parameter MCPAT = \"0x00000000000000\";\n    parameter MASKPAT = \"0x00000000000000\";\n    parameter RNDPAT = \"0x00000000000000\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter MULT9_MODE = \"DISABLED\";\n    parameter FORCE_ZERO_BARREL_SHIFT = \"DISABLED\";\n    parameter LEGACY = \"DISABLED\";\n    input CE3;\n    input CE2;\n    input CE1;\n    input CE0;\n    input CLK3;\n    input CLK2;\n    input CLK1;\n    input CLK0;\n    input RST3;\n    input RST2;\n    input RST1;\n    input RST0;\n    input SIGNEDIA;\n    input SIGNEDIB;\n    input SIGNEDCIN;\n    input A35;\n    input A34;\n    input A33;\n    input A32;\n    input A31;\n    input A30;\n    input A29;\n    input A28;\n    input A27;\n    input A26;\n    input A25;\n    input A24;\n    input A23;\n    input A22;\n    input A21;\n    input A20;\n    input A19;\n    input A18;\n    input A17;\n    input A16;\n    input A15;\n    input A14;\n    input A13;\n    input A12;\n    input A11;\n    input A10;\n    input A9;\n    input A8;\n    input A7;\n    input A6;\n    input A5;\n    input A4;\n    input A3;\n    input A2;\n    input A1;\n    input A0;\n    input B35;\n    input B34;\n    input B33;\n    input B32;\n    input B31;\n    input B30;\n    input B29;\n    input B28;\n    input B27;\n    input B26;\n    input B25;\n    input B24;\n    input B23;\n    input B22;\n    input B21;\n    input B20;\n    input B19;\n    input B18;\n    input B17;\n    input B16;\n    input B15;\n    input B14;\n    input B13;\n    input B12;\n    input B11;\n    input B10;\n    input B9;\n    input B8;\n    input B7;\n    input B6;\n    input B5;\n    input B4;\n    input B3;\n    input B2;\n    input B1;\n    input B0;\n    input C53;\n    input C52;\n    input C51;\n    input C50;\n    input C49;\n    input C48;\n    input C47;\n    input C46;\n    input C45;\n    input C44;\n    input C43;\n    input C42;\n    input C41;\n    input C40;\n    input C39;\n    input C38;\n    input C37;\n    input C36;\n    input C35;\n    input C34;\n    input C33;\n    input C32;\n    input C31;\n    input C30;\n    input C29;\n    input C28;\n    input C27;\n    input C26;\n    input C25;\n    input C24;\n    input C23;\n    input C22;\n    input C21;\n    input C20;\n    input C19;\n    input C18;\n    input C17;\n    input C16;\n    input C15;\n    input C14;\n    input C13;\n    input C12;\n    input C11;\n    input C10;\n    input C9;\n    input C8;\n    input C7;\n    input C6;\n    input C5;\n    input C4;\n    input C3;\n    input C2;\n    input C1;\n    input C0;\n    input CFB53;\n    input CFB52;\n    input CFB51;\n    input CFB50;\n    input CFB49;\n    input CFB48;\n    input CFB47;\n    input CFB46;\n    input CFB45;\n    input CFB44;\n    input CFB43;\n    input CFB42;\n    input CFB41;\n    input CFB40;\n    input CFB39;\n    input CFB38;\n    input CFB37;\n    input CFB36;\n    input CFB35;\n    input CFB34;\n    input CFB33;\n    input CFB32;\n    input CFB31;\n    input CFB30;\n    input CFB29;\n    input CFB28;\n    input CFB27;\n    input CFB26;\n    input CFB25;\n    input CFB24;\n    input CFB23;\n    input CFB22;\n    input CFB21;\n    input CFB20;\n    input CFB19;\n    input CFB18;\n    input CFB17;\n    input CFB16;\n    input CFB15;\n    input CFB14;\n    input CFB13;\n    input CFB12;\n    input CFB11;\n    input CFB10;\n    input CFB9;\n    input CFB8;\n    input CFB7;\n    input CFB6;\n    input CFB5;\n    input CFB4;\n    input CFB3;\n    input CFB2;\n    input CFB1;\n    input CFB0;\n    input MA35;\n    input MA34;\n    input MA33;\n    input MA32;\n    input MA31;\n    input MA30;\n    input MA29;\n    input MA28;\n    input MA27;\n    input MA26;\n    input MA25;\n    input MA24;\n    input MA23;\n    input MA22;\n    input MA21;\n    input MA20;\n    input MA19;\n    input MA18;\n    input MA17;\n    input MA16;\n    input MA15;\n    input MA14;\n    input MA13;\n    input MA12;\n    input MA11;\n    input MA10;\n    input MA9;\n    input MA8;\n    input MA7;\n    input MA6;\n    input MA5;\n    input MA4;\n    input MA3;\n    input MA2;\n    input MA1;\n    input MA0;\n    input MB35;\n    input MB34;\n    input MB33;\n    input MB32;\n    input MB31;\n    input MB30;\n    input MB29;\n    input MB28;\n    input MB27;\n    input MB26;\n    input MB25;\n    input MB24;\n    input MB23;\n    input MB22;\n    input MB21;\n    input MB20;\n    input MB19;\n    input MB18;\n    input MB17;\n    input MB16;\n    input MB15;\n    input MB14;\n    input MB13;\n    input MB12;\n    input MB11;\n    input MB10;\n    input MB9;\n    input MB8;\n    input MB7;\n    input MB6;\n    input MB5;\n    input MB4;\n    input MB3;\n    input MB2;\n    input MB1;\n    input MB0;\n    input CIN53;\n    input CIN52;\n    input CIN51;\n    input CIN50;\n    input CIN49;\n    input CIN48;\n    input CIN47;\n    input CIN46;\n    input CIN45;\n    input CIN44;\n    input CIN43;\n    input CIN42;\n    input CIN41;\n    input CIN40;\n    input CIN39;\n    input CIN38;\n    input CIN37;\n    input CIN36;\n    input CIN35;\n    input CIN34;\n    input CIN33;\n    input CIN32;\n    input CIN31;\n    input CIN30;\n    input CIN29;\n    input CIN28;\n    input CIN27;\n    input CIN26;\n    input CIN25;\n    input CIN24;\n    input CIN23;\n    input CIN22;\n    input CIN21;\n    input CIN20;\n    input CIN19;\n    input CIN18;\n    input CIN17;\n    input CIN16;\n    input CIN15;\n    input CIN14;\n    input CIN13;\n    input CIN12;\n    input CIN11;\n    input CIN10;\n    input CIN9;\n    input CIN8;\n    input CIN7;\n    input CIN6;\n    input CIN5;\n    input CIN4;\n    input CIN3;\n    input CIN2;\n    input CIN1;\n    input CIN0;\n    input OP10;\n    input OP9;\n    input OP8;\n    input OP7;\n    input OP6;\n    input OP5;\n    input OP4;\n    input OP3;\n    input OP2;\n    input OP1;\n    input OP0;\n    output R53;\n    output R52;\n    output R51;\n    output R50;\n    output R49;\n    output R48;\n    output R47;\n    output R46;\n    output R45;\n    output R44;\n    output R43;\n    output R42;\n    output R41;\n    output R40;\n    output R39;\n    output R38;\n    output R37;\n    output R36;\n    output R35;\n    output R34;\n    output R33;\n    output R32;\n    output R31;\n    output R30;\n    output R29;\n    output R28;\n    output R27;\n    output R26;\n    output R25;\n    output R24;\n    output R23;\n    output R22;\n    output R21;\n    output R20;\n    output R19;\n    output R18;\n    output R17;\n    output R16;\n    output R15;\n    output R14;\n    output R13;\n    output R12;\n    output R11;\n    output R10;\n    output R9;\n    output R8;\n    output R7;\n    output R6;\n    output R5;\n    output R4;\n    output R3;\n    output R2;\n    output R1;\n    output R0;\n    output CO53;\n    output CO52;\n    output CO51;\n    output CO50;\n    output CO49;\n    output CO48;\n    output CO47;\n    output CO46;\n    output CO45;\n    output CO44;\n    output CO43;\n    output CO42;\n    output CO41;\n    output CO40;\n    output CO39;\n    output CO38;\n    output CO37;\n    output CO36;\n    output CO35;\n    output CO34;\n    output CO33;\n    output CO32;\n    output CO31;\n    output CO30;\n    output CO29;\n    output CO28;\n    output CO27;\n    output CO26;\n    output CO25;\n    output CO24;\n    output CO23;\n    output CO22;\n    output CO21;\n    output CO20;\n    output CO19;\n    output CO18;\n    output CO17;\n    output CO16;\n    output CO15;\n    output CO14;\n    output CO13;\n    output CO12;\n    output CO11;\n    output CO10;\n    output CO9;\n    output CO8;\n    output CO7;\n    output CO6;\n    output CO5;\n    output CO4;\n    output CO3;\n    output CO2;\n    output CO1;\n    output CO0;\n    output EQZ;\n    output EQZM;\n    output EQOM;\n    output EQPAT;\n    output EQPATB;\n    output OVER;\n    output UNDER;\n    output OVERUNDER;\n    output SIGNEDR;\nendmodule\n\n(* blackbox *)\nmodule CLKDIVF (...);\n    parameter GSR = \"DISABLED\";\n    parameter DIV = \"2.0\";\n    input CLKI;\n    input RST;\n    input ALIGNWD;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule PCSCLKDIV (...);\n    parameter GSR = \"DISABLED\";\n    input CLKI;\n    input RST;\n    input SEL2;\n    input SEL1;\n    input SEL0;\n    output CDIV1;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule DCSC (...);\n    parameter DCSMODE = \"POS\";\n    input CLK1;\n    input CLK0;\n    input SEL1;\n    input SEL0;\n    input MODESEL;\n    output DCSOUT;\nendmodule\n\n(* blackbox *)\nmodule DCCA (...);\n    input CLKI;\n    input CE;\n    output CLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKSYNCB (...);\n    input ECLKI;\n    input STOP;\n    output ECLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKBRIDGECS (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output ECSOUT;\nendmodule\n\n(* blackbox *)\nmodule DELAYF (...);\n    parameter DEL_MODE = \"USER_DEFINED\";\n    parameter DEL_VALUE = 0;\n    input A;\n    input LOADN;\n    input MOVE;\n    input DIRECTION;\n    output Z;\n    output CFLAG;\nendmodule\n\n(* blackbox *)\nmodule DELAYG (...);\n    parameter DEL_MODE = \"USER_DEFINED\";\n    parameter DEL_VALUE = 0;\n    input A;\n    output Z;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule USRMCLK (...);\n    input USRMCLKI;\n    input USRMCLKTS;\nendmodule\n\n(* blackbox *)\nmodule DQSBUFM (...);\n    parameter DQS_LI_DEL_VAL = 4;\n    parameter DQS_LI_DEL_ADJ = \"FACTORYONLY\";\n    parameter DQS_LO_DEL_VAL = 0;\n    parameter DQS_LO_DEL_ADJ = \"FACTORYONLY\";\n    parameter GSR = \"ENABLED\";\n    input DQSI;\n    input READ1;\n    input READ0;\n    input READCLKSEL2;\n    input READCLKSEL1;\n    input READCLKSEL0;\n    input DDRDEL;\n    input ECLK;\n    input SCLK;\n    input RST;\n    input DYNDELAY7;\n    input DYNDELAY6;\n    input DYNDELAY5;\n    input DYNDELAY4;\n    input DYNDELAY3;\n    input DYNDELAY2;\n    input DYNDELAY1;\n    input DYNDELAY0;\n    input PAUSE;\n    input RDLOADN;\n    input RDMOVE;\n    input RDDIRECTION;\n    input WRLOADN;\n    input WRMOVE;\n    input WRDIRECTION;\n    output DQSR90;\n    output DQSW;\n    output DQSW270;\n    output RDPNTR2;\n    output RDPNTR1;\n    output RDPNTR0;\n    output WRPNTR2;\n    output WRPNTR1;\n    output WRPNTR0;\n    output DATAVALID;\n    output BURSTDET;\n    output RDCFLAG;\n    output WRCFLAG;\nendmodule\n\n(* blackbox *)\nmodule DDRDLLA (...);\n    parameter FORCE_MAX_DELAY = \"NO\";\n    parameter GSR = \"ENABLED\";\n    input CLK;\n    input RST;\n    input UDDCNTLN;\n    input FREEZE;\n    output DDRDEL;\n    output LOCK;\n    output DCNTL7;\n    output DCNTL6;\n    output DCNTL5;\n    output DCNTL4;\n    output DCNTL3;\n    output DCNTL2;\n    output DCNTL1;\n    output DCNTL0;\nendmodule\n\n(* blackbox *)\nmodule DLLDELD (...);\n    input A;\n    input DDRDEL;\n    input LOADN;\n    input MOVE;\n    input DIRECTION;\n    output Z;\n    output CFLAG;\nendmodule\n\n(* blackbox *)\nmodule IDDRX1F (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input RST;\n    output Q0;\n    output Q1;\nendmodule\n\n(* blackbox *)\nmodule IDDRX2F (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input ECLK;\n    input RST;\n    input ALIGNWD;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\nendmodule\n\n(* blackbox *)\nmodule IDDR71B (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input ECLK;\n    input RST;\n    input ALIGNWD;\n    output Q6;\n    output Q5;\n    output Q4;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\nendmodule\n\n(* blackbox *)\nmodule IDDRX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input DQSR90;\n    input D;\n    input RST;\n    input RDPNTR2;\n    input RDPNTR1;\n    input RDPNTR0;\n    input WRPNTR2;\n    input WRPNTR1;\n    input WRPNTR0;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\n    output QWL;\nendmodule\n\n(* blackbox *)\nmodule ODDRX1F (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input RST;\n    input D0;\n    input D1;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2F (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input RST;\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDR71B (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input RST;\n    input D6;\n    input D5;\n    input D4;\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule OSHX2A (...);\n    parameter GSR = \"ENABLED\";\n    input D1;\n    input D0;\n    input SCLK;\n    input ECLK;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    parameter REGSET = \"SET\";\n    input T1;\n    input T0;\n    input SCLK;\n    input ECLK;\n    input DQSW270;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQSA (...);\n    parameter GSR = \"ENABLED\";\n    parameter REGSET = \"SET\";\n    input T1;\n    input T0;\n    input SCLK;\n    input ECLK;\n    input DQSW;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    input DQSW270;\n    input SCLK;\n    input ECLK;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQSB (...);\n    parameter GSR = \"ENABLED\";\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    input SCLK;\n    input ECLK;\n    input DQSW;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule EHXPLLL (...);\n    parameter CLKI_DIV = 1;\n    parameter CLKFB_DIV = 1;\n    parameter CLKOP_DIV = 8;\n    parameter CLKOS_DIV = 8;\n    parameter CLKOS2_DIV = 8;\n    parameter CLKOS3_DIV = 8;\n    parameter CLKOP_ENABLE = \"ENABLED\";\n    parameter CLKOS_ENABLE = \"DISABLED\";\n    parameter CLKOS2_ENABLE = \"DISABLED\";\n    parameter CLKOS3_ENABLE = \"DISABLED\";\n    parameter CLKOP_CPHASE = 0;\n    parameter CLKOS_CPHASE = 0;\n    parameter CLKOS2_CPHASE = 0;\n    parameter CLKOS3_CPHASE = 0;\n    parameter CLKOP_FPHASE = 0;\n    parameter CLKOS_FPHASE = 0;\n    parameter CLKOS2_FPHASE = 0;\n    parameter CLKOS3_FPHASE = 0;\n    parameter FEEDBK_PATH = \"CLKOP\";\n    parameter CLKOP_TRIM_POL = \"RISING\";\n    parameter CLKOP_TRIM_DELAY = 0;\n    parameter CLKOS_TRIM_POL = \"RISING\";\n    parameter CLKOS_TRIM_DELAY = 0;\n    parameter OUTDIVIDER_MUXA = \"DIVA\";\n    parameter OUTDIVIDER_MUXB = \"DIVB\";\n    parameter OUTDIVIDER_MUXC = \"DIVC\";\n    parameter OUTDIVIDER_MUXD = \"DIVD\";\n    parameter PLL_LOCK_MODE = 0;\n    parameter PLL_LOCK_DELAY = 200;\n    parameter STDBY_ENABLE = \"DISABLED\";\n    parameter REFIN_RESET = \"DISABLED\";\n    parameter SYNC_ENABLE = \"DISABLED\";\n    parameter INT_LOCK_STICKY = \"ENABLED\";\n    parameter DPHASE_SOURCE = \"DISABLED\";\n    parameter PLLRST_ENA = \"DISABLED\";\n    parameter INTFB_WAKE = \"DISABLED\";\n    input CLKI;\n    input CLKFB;\n    input PHASESEL1;\n    input PHASESEL0;\n    input PHASEDIR;\n    input PHASESTEP;\n    input PHASELOADREG;\n    input STDBY;\n    input PLLWAKESYNC;\n    input RST;\n    input ENCLKOP;\n    input ENCLKOS;\n    input ENCLKOS2;\n    input ENCLKOS3;\n    output CLKOP;\n    output CLKOS;\n    output CLKOS2;\n    output CLKOS3;\n    output LOCK;\n    output INTLOCK;\n    output REFCLK;\n    output CLKINTFB;\nendmodule\n\n(* blackbox *)\nmodule DTR (...);\n    parameter DTR_TEMP = 25;\n    input STARTPULSE;\n    output DTROUT7;\n    output DTROUT6;\n    output DTROUT5;\n    output DTROUT4;\n    output DTROUT3;\n    output DTROUT2;\n    output DTROUT1;\n    output DTROUT0;\nendmodule\n\n(* blackbox *)\nmodule OSCG (...);\n    parameter DIV = 128;\n    output OSC;\nendmodule\n\n(* blackbox *)\nmodule EXTREFB (...);\n    parameter REFCK_PWDNB = \"DONTCARE\";\n    parameter REFCK_RTERM = \"DONTCARE\";\n    parameter REFCK_DCBIAS_EN = \"DONTCARE\";\n    (* iopad_external_pin *)\n    input REFCLKP;\n    (* iopad_external_pin *)\n    input REFCLKN;\n    output REFCLKO;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule JTAGG (...);\n    parameter ER1 = \"ENABLED\";\n    parameter ER2 = \"ENABLED\";\n    (* iopad_external_pin *)\n    input TCK;\n    (* iopad_external_pin *)\n    input TMS;\n    (* iopad_external_pin *)\n    input TDI;\n    input JTDO2;\n    input JTDO1;\n    (* iopad_external_pin *)\n    output TDO;\n    output JTDI;\n    output JTCK;\n    output JRTI2;\n    output JRTI1;\n    output JSHIFT;\n    output JUPDATE;\n    output JRSTN;\n    output JCE2;\n    output JCE1;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule DCUA (...);\n    parameter D_MACROPDB = \"DONTCARE\";\n    parameter D_IB_PWDNB = \"DONTCARE\";\n    parameter D_XGE_MODE = \"DONTCARE\";\n    parameter D_LOW_MARK = \"DONTCARE\";\n    parameter D_HIGH_MARK = \"DONTCARE\";\n    parameter D_BUS8BIT_SEL = \"DONTCARE\";\n    parameter D_CDR_LOL_SET = \"DONTCARE\";\n    parameter D_BITCLK_LOCAL_EN = \"DONTCARE\";\n    parameter D_BITCLK_ND_EN = \"DONTCARE\";\n    parameter D_BITCLK_FROM_ND_EN = \"DONTCARE\";\n    parameter D_SYNC_LOCAL_EN = \"DONTCARE\";\n    parameter D_SYNC_ND_EN = \"DONTCARE\";\n    parameter CH0_UC_MODE = \"DONTCARE\";\n    parameter CH1_UC_MODE = \"DONTCARE\";\n    parameter CH0_PCIE_MODE = \"DONTCARE\";\n    parameter CH1_PCIE_MODE = \"DONTCARE\";\n    parameter CH0_RIO_MODE = \"DONTCARE\";\n    parameter CH1_RIO_MODE = \"DONTCARE\";\n    parameter CH0_WA_MODE = \"DONTCARE\";\n    parameter CH1_WA_MODE = \"DONTCARE\";\n    parameter CH0_INVERT_RX = \"DONTCARE\";\n    parameter CH1_INVERT_RX = \"DONTCARE\";\n    parameter CH0_INVERT_TX = \"DONTCARE\";\n    parameter CH1_INVERT_TX = \"DONTCARE\";\n    parameter CH0_PRBS_SELECTION = \"DONTCARE\";\n    parameter CH1_PRBS_SELECTION = \"DONTCARE\";\n    parameter CH0_GE_AN_ENABLE = \"DONTCARE\";\n    parameter CH1_GE_AN_ENABLE = \"DONTCARE\";\n    parameter CH0_PRBS_LOCK = \"DONTCARE\";\n    parameter CH1_PRBS_LOCK = \"DONTCARE\";\n    parameter CH0_PRBS_ENABLE = \"DONTCARE\";\n    parameter CH1_PRBS_ENABLE = \"DONTCARE\";\n    parameter CH0_ENABLE_CG_ALIGN = \"DONTCARE\";\n    parameter CH1_ENABLE_CG_ALIGN = \"DONTCARE\";\n    parameter CH0_TX_GEAR_MODE = \"DONTCARE\";\n    parameter CH1_TX_GEAR_MODE = \"DONTCARE\";\n    parameter CH0_RX_GEAR_MODE = \"DONTCARE\";\n    parameter CH1_RX_GEAR_MODE = \"DONTCARE\";\n    parameter CH0_PCS_DET_TIME_SEL = \"DONTCARE\";\n    parameter CH1_PCS_DET_TIME_SEL = \"DONTCARE\";\n    parameter CH0_PCIE_EI_EN = \"DONTCARE\";\n    parameter CH1_PCIE_EI_EN = \"DONTCARE\";\n    parameter CH0_TX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH1_TX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH0_ENC_BYPASS = \"DONTCARE\";\n    parameter CH1_ENC_BYPASS = \"DONTCARE\";\n    parameter CH0_SB_BYPASS = \"DONTCARE\";\n    parameter CH1_SB_BYPASS = \"DONTCARE\";\n    parameter CH0_RX_SB_BYPASS = \"DONTCARE\";\n    parameter CH1_RX_SB_BYPASS = \"DONTCARE\";\n    parameter CH0_WA_BYPASS = \"DONTCARE\";\n    parameter CH1_WA_BYPASS = \"DONTCARE\";\n    parameter CH0_DEC_BYPASS = \"DONTCARE\";\n    parameter CH1_DEC_BYPASS = \"DONTCARE\";\n    parameter CH0_CTC_BYPASS = \"DONTCARE\";\n    parameter CH1_CTC_BYPASS = \"DONTCARE\";\n    parameter CH0_RX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH1_RX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH0_LSM_DISABLE = \"DONTCARE\";\n    parameter CH1_LSM_DISABLE = \"DONTCARE\";\n    parameter CH0_MATCH_2_ENABLE = \"DONTCARE\";\n    parameter CH1_MATCH_2_ENABLE = \"DONTCARE\";\n    parameter CH0_MATCH_4_ENABLE = \"DONTCARE\";\n    parameter CH1_MATCH_4_ENABLE = \"DONTCARE\";\n    parameter CH0_MIN_IPG_CNT = \"DONTCARE\";\n    parameter CH1_MIN_IPG_CNT = \"DONTCARE\";\n    parameter CH0_CC_MATCH_1 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_1 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_2 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_2 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_3 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_3 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_4 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_4 = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_MASK = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_MASK = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_A = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_A = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_B = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_B = \"DONTCARE\";\n    parameter CH0_RX_DCO_CK_DIV = \"DONTCARE\";\n    parameter CH1_RX_DCO_CK_DIV = \"DONTCARE\";\n    parameter CH0_RCV_DCC_EN = \"DONTCARE\";\n    parameter CH1_RCV_DCC_EN = \"DONTCARE\";\n    parameter CH0_REQ_LVL_SET = \"DONTCARE\";\n    parameter CH1_REQ_LVL_SET = \"DONTCARE\";\n    parameter CH0_REQ_EN = \"DONTCARE\";\n    parameter CH1_REQ_EN = \"DONTCARE\";\n    parameter CH0_RTERM_RX = \"DONTCARE\";\n    parameter CH1_RTERM_RX = \"DONTCARE\";\n    parameter CH0_PDEN_SEL = \"DONTCARE\";\n    parameter CH1_PDEN_SEL = \"DONTCARE\";\n    parameter CH0_LDR_RX2CORE_SEL = \"DONTCARE\";\n    parameter CH1_LDR_RX2CORE_SEL = \"DONTCARE\";\n    parameter CH0_LDR_CORE2TX_SEL = \"DONTCARE\";\n    parameter CH1_LDR_CORE2TX_SEL = \"DONTCARE\";\n    parameter CH0_TPWDNB = \"DONTCARE\";\n    parameter CH1_TPWDNB = \"DONTCARE\";\n    parameter CH0_RATE_MODE_TX = \"DONTCARE\";\n    parameter CH1_RATE_MODE_TX = \"DONTCARE\";\n    parameter CH0_RTERM_TX = \"DONTCARE\";\n    parameter CH1_RTERM_TX = \"DONTCARE\";\n    parameter CH0_TX_CM_SEL = \"DONTCARE\";\n    parameter CH1_TX_CM_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_PRE_EN = \"DONTCARE\";\n    parameter CH1_TDRV_PRE_EN = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE0_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE0_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE1_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE1_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE2_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE2_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE3_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE3_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE4_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE4_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE5_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE5_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE0_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE0_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE1_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE1_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE2_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE2_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE3_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE3_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE4_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE4_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE5_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE5_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_DAT_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_DAT_SEL = \"DONTCARE\";\n    parameter CH0_TX_DIV11_SEL = \"DONTCARE\";\n    parameter CH1_TX_DIV11_SEL = \"DONTCARE\";\n    parameter CH0_RPWDNB = \"DONTCARE\";\n    parameter CH1_RPWDNB = \"DONTCARE\";\n    parameter CH0_RATE_MODE_RX = \"DONTCARE\";\n    parameter CH1_RATE_MODE_RX = \"DONTCARE\";\n    parameter CH0_RLOS_SEL = \"DONTCARE\";\n    parameter CH1_RLOS_SEL = \"DONTCARE\";\n    parameter CH0_RX_LOS_LVL = \"DONTCARE\";\n    parameter CH1_RX_LOS_LVL = \"DONTCARE\";\n    parameter CH0_RX_LOS_CEQ = \"DONTCARE\";\n    parameter CH1_RX_LOS_CEQ = \"DONTCARE\";\n    parameter CH0_RX_LOS_HYST_EN = \"DONTCARE\";\n    parameter CH1_RX_LOS_HYST_EN = \"DONTCARE\";\n    parameter CH0_RX_LOS_EN = \"DONTCARE\";\n    parameter CH1_RX_LOS_EN = \"DONTCARE\";\n    parameter CH0_RX_DIV11_SEL = \"DONTCARE\";\n    parameter CH1_RX_DIV11_SEL = \"DONTCARE\";\n    parameter CH0_SEL_SD_RX_CLK = \"DONTCARE\";\n    parameter CH1_SEL_SD_RX_CLK = \"DONTCARE\";\n    parameter CH0_FF_RX_H_CLK_EN = \"DONTCARE\";\n    parameter CH1_FF_RX_H_CLK_EN = \"DONTCARE\";\n    parameter CH0_FF_RX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH1_FF_RX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH0_FF_TX_H_CLK_EN = \"DONTCARE\";\n    parameter CH1_FF_TX_H_CLK_EN = \"DONTCARE\";\n    parameter CH0_FF_TX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH1_FF_TX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH0_RX_RATE_SEL = \"DONTCARE\";\n    parameter CH1_RX_RATE_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_POST_EN = \"DONTCARE\";\n    parameter CH1_TDRV_POST_EN = \"DONTCARE\";\n    parameter CH0_TX_POST_SIGN = \"DONTCARE\";\n    parameter CH1_TX_POST_SIGN = \"DONTCARE\";\n    parameter CH0_TX_PRE_SIGN = \"DONTCARE\";\n    parameter CH1_TX_PRE_SIGN = \"DONTCARE\";\n    parameter CH0_RXTERM_CM = \"DONTCARE\";\n    parameter CH1_RXTERM_CM = \"DONTCARE\";\n    parameter CH0_RXIN_CM = \"DONTCARE\";\n    parameter CH1_RXIN_CM = \"DONTCARE\";\n    parameter CH0_LEQ_OFFSET_SEL = \"DONTCARE\";\n    parameter CH1_LEQ_OFFSET_SEL = \"DONTCARE\";\n    parameter CH0_LEQ_OFFSET_TRIM = \"DONTCARE\";\n    parameter CH1_LEQ_OFFSET_TRIM = \"DONTCARE\";\n    parameter D_TX_MAX_RATE = \"DONTCARE\";\n    parameter CH0_CDR_MAX_RATE = \"DONTCARE\";\n    parameter CH1_CDR_MAX_RATE = \"DONTCARE\";\n    parameter CH0_TXAMPLITUDE = \"DONTCARE\";\n    parameter CH1_TXAMPLITUDE = \"DONTCARE\";\n    parameter CH0_TXDEPRE = \"DONTCARE\";\n    parameter CH1_TXDEPRE = \"DONTCARE\";\n    parameter CH0_TXDEPOST = \"DONTCARE\";\n    parameter CH1_TXDEPOST = \"DONTCARE\";\n    parameter CH0_PROTOCOL = \"DONTCARE\";\n    parameter CH1_PROTOCOL = \"DONTCARE\";\n    parameter D_ISETLOS = \"DONTCARE\";\n    parameter D_SETIRPOLY_AUX = \"DONTCARE\";\n    parameter D_SETICONST_AUX = \"DONTCARE\";\n    parameter D_SETIRPOLY_CH = \"DONTCARE\";\n    parameter D_SETICONST_CH = \"DONTCARE\";\n    parameter D_REQ_ISET = \"DONTCARE\";\n    parameter D_PD_ISET = \"DONTCARE\";\n    parameter D_DCO_CALIB_TIME_SEL = \"DONTCARE\";\n    parameter CH0_DCOCTLGI = \"DONTCARE\";\n    parameter CH1_DCOCTLGI = \"DONTCARE\";\n    parameter CH0_DCOATDDLY = \"DONTCARE\";\n    parameter CH1_DCOATDDLY = \"DONTCARE\";\n    parameter CH0_DCOATDCFG = \"DONTCARE\";\n    parameter CH1_DCOATDCFG = \"DONTCARE\";\n    parameter CH0_DCOBYPSATD = \"DONTCARE\";\n    parameter CH1_DCOBYPSATD = \"DONTCARE\";\n    parameter CH0_DCOSCALEI = \"DONTCARE\";\n    parameter CH1_DCOSCALEI = \"DONTCARE\";\n    parameter CH0_DCOITUNE4LSB = \"DONTCARE\";\n    parameter CH1_DCOITUNE4LSB = \"DONTCARE\";\n    parameter CH0_DCOIOSTUNE = \"DONTCARE\";\n    parameter CH1_DCOIOSTUNE = \"DONTCARE\";\n    parameter CH0_DCODISBDAVOID = \"DONTCARE\";\n    parameter CH1_DCODISBDAVOID = \"DONTCARE\";\n    parameter CH0_DCOCALDIV = \"DONTCARE\";\n    parameter CH1_DCOCALDIV = \"DONTCARE\";\n    parameter CH0_DCONUOFLSB = \"DONTCARE\";\n    parameter CH1_DCONUOFLSB = \"DONTCARE\";\n    parameter CH0_DCOIUPDNX2 = \"DONTCARE\";\n    parameter CH1_DCOIUPDNX2 = \"DONTCARE\";\n    parameter CH0_DCOSTEP = \"DONTCARE\";\n    parameter CH1_DCOSTEP = \"DONTCARE\";\n    parameter CH0_DCOSTARTVAL = \"DONTCARE\";\n    parameter CH1_DCOSTARTVAL = \"DONTCARE\";\n    parameter CH0_DCOFLTDAC = \"DONTCARE\";\n    parameter CH1_DCOFLTDAC = \"DONTCARE\";\n    parameter CH0_DCOITUNE = \"DONTCARE\";\n    parameter CH1_DCOITUNE = \"DONTCARE\";\n    parameter CH0_DCOFTNRG = \"DONTCARE\";\n    parameter CH1_DCOFTNRG = \"DONTCARE\";\n    parameter CH0_CDR_CNT4SEL = \"DONTCARE\";\n    parameter CH1_CDR_CNT4SEL = \"DONTCARE\";\n    parameter CH0_CDR_CNT8SEL = \"DONTCARE\";\n    parameter CH1_CDR_CNT8SEL = \"DONTCARE\";\n    parameter CH0_BAND_THRESHOLD = \"DONTCARE\";\n    parameter CH1_BAND_THRESHOLD = \"DONTCARE\";\n    parameter CH0_AUTO_FACQ_EN = \"DONTCARE\";\n    parameter CH1_AUTO_FACQ_EN = \"DONTCARE\";\n    parameter CH0_AUTO_CALIB_EN = \"DONTCARE\";\n    parameter CH1_AUTO_CALIB_EN = \"DONTCARE\";\n    parameter CH0_CALIB_CK_MODE = \"DONTCARE\";\n    parameter CH1_CALIB_CK_MODE = \"DONTCARE\";\n    parameter CH0_REG_BAND_OFFSET = \"DONTCARE\";\n    parameter CH1_REG_BAND_OFFSET = \"DONTCARE\";\n    parameter CH0_REG_BAND_SEL = \"DONTCARE\";\n    parameter CH1_REG_BAND_SEL = \"DONTCARE\";\n    parameter CH0_REG_IDAC_SEL = \"DONTCARE\";\n    parameter CH1_REG_IDAC_SEL = \"DONTCARE\";\n    parameter CH0_REG_IDAC_EN = \"DONTCARE\";\n    parameter CH1_REG_IDAC_EN = \"DONTCARE\";\n    parameter D_TXPLL_PWDNB = \"DONTCARE\";\n    parameter D_SETPLLRC = \"DONTCARE\";\n    parameter D_REFCK_MODE = \"DONTCARE\";\n    parameter D_TX_VCO_CK_DIV = \"DONTCARE\";\n    parameter D_PLL_LOL_SET = \"DONTCARE\";\n    parameter D_RG_EN = \"DONTCARE\";\n    parameter D_RG_SET = \"DONTCARE\";\n    parameter D_CMUSETISCL4VCO = \"DONTCARE\";\n    parameter D_CMUSETI4VCO = \"DONTCARE\";\n    parameter D_CMUSETINITVCT = \"DONTCARE\";\n    parameter D_CMUSETZGM = \"DONTCARE\";\n    parameter D_CMUSETP2AGM = \"DONTCARE\";\n    parameter D_CMUSETP1GM = \"DONTCARE\";\n    parameter D_CMUSETI4CPZ = \"DONTCARE\";\n    parameter D_CMUSETI4CPP = \"DONTCARE\";\n    parameter D_CMUSETICP4Z = \"DONTCARE\";\n    parameter D_CMUSETICP4P = \"DONTCARE\";\n    parameter D_CMUSETBIASI = \"DONTCARE\";\n    (* iopad_external_pin *)\n    (* iopad_external_pin *)\n    input CH0_HDINP;\n    (* iopad_external_pin *)\n    input CH1_HDINP;\n    (* iopad_external_pin *)\n    input CH0_HDINN;\n    (* iopad_external_pin *)\n    input CH1_HDINN;\n    input D_TXBIT_CLKP_FROM_ND;\n    input D_TXBIT_CLKN_FROM_ND;\n    input D_SYNC_ND;\n    input D_TXPLL_LOL_FROM_ND;\n    input CH0_RX_REFCLK;\n    input CH1_RX_REFCLK;\n    input CH0_FF_RXI_CLK;\n    input CH1_FF_RXI_CLK;\n    input CH0_FF_TXI_CLK;\n    input CH1_FF_TXI_CLK;\n    input CH0_FF_EBRD_CLK;\n    input CH1_FF_EBRD_CLK;\n    input CH0_FF_TX_D_0;\n    input CH1_FF_TX_D_0;\n    input CH0_FF_TX_D_1;\n    input CH1_FF_TX_D_1;\n    input CH0_FF_TX_D_2;\n    input CH1_FF_TX_D_2;\n    input CH0_FF_TX_D_3;\n    input CH1_FF_TX_D_3;\n    input CH0_FF_TX_D_4;\n    input CH1_FF_TX_D_4;\n    input CH0_FF_TX_D_5;\n    input CH1_FF_TX_D_5;\n    input CH0_FF_TX_D_6;\n    input CH1_FF_TX_D_6;\n    input CH0_FF_TX_D_7;\n    input CH1_FF_TX_D_7;\n    input CH0_FF_TX_D_8;\n    input CH1_FF_TX_D_8;\n    input CH0_FF_TX_D_9;\n    input CH1_FF_TX_D_9;\n    input CH0_FF_TX_D_10;\n    input CH1_FF_TX_D_10;\n    input CH0_FF_TX_D_11;\n    input CH1_FF_TX_D_11;\n    input CH0_FF_TX_D_12;\n    input CH1_FF_TX_D_12;\n    input CH0_FF_TX_D_13;\n    input CH1_FF_TX_D_13;\n    input CH0_FF_TX_D_14;\n    input CH1_FF_TX_D_14;\n    input CH0_FF_TX_D_15;\n    input CH1_FF_TX_D_15;\n    input CH0_FF_TX_D_16;\n    input CH1_FF_TX_D_16;\n    input CH0_FF_TX_D_17;\n    input CH1_FF_TX_D_17;\n    input CH0_FF_TX_D_18;\n    input CH1_FF_TX_D_18;\n    input CH0_FF_TX_D_19;\n    input CH1_FF_TX_D_19;\n    input CH0_FF_TX_D_20;\n    input CH1_FF_TX_D_20;\n    input CH0_FF_TX_D_21;\n    input CH1_FF_TX_D_21;\n    input CH0_FF_TX_D_22;\n    input CH1_FF_TX_D_22;\n    input CH0_FF_TX_D_23;\n    input CH1_FF_TX_D_23;\n    input CH0_FFC_EI_EN;\n    input CH1_FFC_EI_EN;\n    input CH0_FFC_PCIE_DET_EN;\n    input CH1_FFC_PCIE_DET_EN;\n    input CH0_FFC_PCIE_CT;\n    input CH1_FFC_PCIE_CT;\n    input CH0_FFC_SB_INV_RX;\n    input CH1_FFC_SB_INV_RX;\n    input CH0_FFC_ENABLE_CGALIGN;\n    input CH1_FFC_ENABLE_CGALIGN;\n    input CH0_FFC_SIGNAL_DETECT;\n    input CH1_FFC_SIGNAL_DETECT;\n    input CH0_FFC_FB_LOOPBACK;\n    input CH1_FFC_FB_LOOPBACK;\n    input CH0_FFC_SB_PFIFO_LP;\n    input CH1_FFC_SB_PFIFO_LP;\n    input CH0_FFC_PFIFO_CLR;\n    input CH1_FFC_PFIFO_CLR;\n    input CH0_FFC_RATE_MODE_RX;\n    input CH1_FFC_RATE_MODE_RX;\n    input CH0_FFC_RATE_MODE_TX;\n    input CH1_FFC_RATE_MODE_TX;\n    input CH0_FFC_DIV11_MODE_RX;\n    input CH1_FFC_DIV11_MODE_RX;\n    input CH0_FFC_RX_GEAR_MODE;\n    input CH1_FFC_RX_GEAR_MODE;\n    input CH0_FFC_TX_GEAR_MODE;\n    input CH1_FFC_TX_GEAR_MODE;\n    input CH0_FFC_DIV11_MODE_TX;\n    input CH1_FFC_DIV11_MODE_TX;\n    input CH0_FFC_LDR_CORE2TX_EN;\n    input CH1_FFC_LDR_CORE2TX_EN;\n    input CH0_FFC_LANE_TX_RST;\n    input CH1_FFC_LANE_TX_RST;\n    input CH0_FFC_LANE_RX_RST;\n    input CH1_FFC_LANE_RX_RST;\n    input CH0_FFC_RRST;\n    input CH1_FFC_RRST;\n    input CH0_FFC_TXPWDNB;\n    input CH1_FFC_TXPWDNB;\n    input CH0_FFC_RXPWDNB;\n    input CH1_FFC_RXPWDNB;\n    input CH0_LDR_CORE2TX;\n    input CH1_LDR_CORE2TX;\n    input D_SCIWDATA0;\n    input D_SCIWDATA1;\n    input D_SCIWDATA2;\n    input D_SCIWDATA3;\n    input D_SCIWDATA4;\n    input D_SCIWDATA5;\n    input D_SCIWDATA6;\n    input D_SCIWDATA7;\n    input D_SCIADDR0;\n    input D_SCIADDR1;\n    input D_SCIADDR2;\n    input D_SCIADDR3;\n    input D_SCIADDR4;\n    input D_SCIADDR5;\n    input D_SCIENAUX;\n    input D_SCISELAUX;\n    input CH0_SCIEN;\n    input CH1_SCIEN;\n    input CH0_SCISEL;\n    input CH1_SCISEL;\n    input D_SCIRD;\n    input D_SCIWSTN;\n    input D_CYAWSTN;\n    input D_FFC_SYNC_TOGGLE;\n    input D_FFC_DUAL_RST;\n    input D_FFC_MACRO_RST;\n    input D_FFC_MACROPDB;\n    input D_FFC_TRST;\n    input CH0_FFC_CDR_EN_BITSLIP;\n    input CH1_FFC_CDR_EN_BITSLIP;\n    input D_SCAN_ENABLE;\n    input D_SCAN_IN_0;\n    input D_SCAN_IN_1;\n    input D_SCAN_IN_2;\n    input D_SCAN_IN_3;\n    input D_SCAN_IN_4;\n    input D_SCAN_IN_5;\n    input D_SCAN_IN_6;\n    input D_SCAN_IN_7;\n    input D_SCAN_MODE;\n    input D_SCAN_RESET;\n    input D_CIN0;\n    input D_CIN1;\n    input D_CIN2;\n    input D_CIN3;\n    input D_CIN4;\n    input D_CIN5;\n    input D_CIN6;\n    input D_CIN7;\n    input D_CIN8;\n    input D_CIN9;\n    input D_CIN10;\n    input D_CIN11;\n    output CH0_HDOUTP;\n    output CH1_HDOUTP;\n    output CH0_HDOUTN;\n    output CH1_HDOUTN;\n    output D_TXBIT_CLKP_TO_ND;\n    output D_TXBIT_CLKN_TO_ND;\n    output D_SYNC_PULSE2ND;\n    output D_TXPLL_LOL_TO_ND;\n    output CH0_FF_RX_F_CLK;\n    output CH1_FF_RX_F_CLK;\n    output CH0_FF_RX_H_CLK;\n    output CH1_FF_RX_H_CLK;\n    output CH0_FF_TX_F_CLK;\n    output CH1_FF_TX_F_CLK;\n    output CH0_FF_TX_H_CLK;\n    output CH1_FF_TX_H_CLK;\n    output CH0_FF_RX_PCLK;\n    output CH1_FF_RX_PCLK;\n    output CH0_FF_TX_PCLK;\n    output CH1_FF_TX_PCLK;\n    output CH0_FF_RX_D_0;\n    output CH1_FF_RX_D_0;\n    output CH0_FF_RX_D_1;\n    output CH1_FF_RX_D_1;\n    output CH0_FF_RX_D_2;\n    output CH1_FF_RX_D_2;\n    output CH0_FF_RX_D_3;\n    output CH1_FF_RX_D_3;\n    output CH0_FF_RX_D_4;\n    output CH1_FF_RX_D_4;\n    output CH0_FF_RX_D_5;\n    output CH1_FF_RX_D_5;\n    output CH0_FF_RX_D_6;\n    output CH1_FF_RX_D_6;\n    output CH0_FF_RX_D_7;\n    output CH1_FF_RX_D_7;\n    output CH0_FF_RX_D_8;\n    output CH1_FF_RX_D_8;\n    output CH0_FF_RX_D_9;\n    output CH1_FF_RX_D_9;\n    output CH0_FF_RX_D_10;\n    output CH1_FF_RX_D_10;\n    output CH0_FF_RX_D_11;\n    output CH1_FF_RX_D_11;\n    output CH0_FF_RX_D_12;\n    output CH1_FF_RX_D_12;\n    output CH0_FF_RX_D_13;\n    output CH1_FF_RX_D_13;\n    output CH0_FF_RX_D_14;\n    output CH1_FF_RX_D_14;\n    output CH0_FF_RX_D_15;\n    output CH1_FF_RX_D_15;\n    output CH0_FF_RX_D_16;\n    output CH1_FF_RX_D_16;\n    output CH0_FF_RX_D_17;\n    output CH1_FF_RX_D_17;\n    output CH0_FF_RX_D_18;\n    output CH1_FF_RX_D_18;\n    output CH0_FF_RX_D_19;\n    output CH1_FF_RX_D_19;\n    output CH0_FF_RX_D_20;\n    output CH1_FF_RX_D_20;\n    output CH0_FF_RX_D_21;\n    output CH1_FF_RX_D_21;\n    output CH0_FF_RX_D_22;\n    output CH1_FF_RX_D_22;\n    output CH0_FF_RX_D_23;\n    output CH1_FF_RX_D_23;\n    output CH0_FFS_PCIE_DONE;\n    output CH1_FFS_PCIE_DONE;\n    output CH0_FFS_PCIE_CON;\n    output CH1_FFS_PCIE_CON;\n    output CH0_FFS_RLOS;\n    output CH1_FFS_RLOS;\n    output CH0_FFS_LS_SYNC_STATUS;\n    output CH1_FFS_LS_SYNC_STATUS;\n    output CH0_FFS_CC_UNDERRUN;\n    output CH1_FFS_CC_UNDERRUN;\n    output CH0_FFS_CC_OVERRUN;\n    output CH1_FFS_CC_OVERRUN;\n    output CH0_FFS_RXFBFIFO_ERROR;\n    output CH1_FFS_RXFBFIFO_ERROR;\n    output CH0_FFS_TXFBFIFO_ERROR;\n    output CH1_FFS_TXFBFIFO_ERROR;\n    output CH0_FFS_RLOL;\n    output CH1_FFS_RLOL;\n    output CH0_FFS_SKP_ADDED;\n    output CH1_FFS_SKP_ADDED;\n    output CH0_FFS_SKP_DELETED;\n    output CH1_FFS_SKP_DELETED;\n    output CH0_LDR_RX2CORE;\n    output CH1_LDR_RX2CORE;\n    output D_SCIRDATA0;\n    output D_SCIRDATA1;\n    output D_SCIRDATA2;\n    output D_SCIRDATA3;\n    output D_SCIRDATA4;\n    output D_SCIRDATA5;\n    output D_SCIRDATA6;\n    output D_SCIRDATA7;\n    output D_SCIINT;\n    output D_SCAN_OUT_0;\n    output D_SCAN_OUT_1;\n    output D_SCAN_OUT_2;\n    output D_SCAN_OUT_3;\n    output D_SCAN_OUT_4;\n    output D_SCAN_OUT_5;\n    output D_SCAN_OUT_6;\n    output D_SCAN_OUT_7;\n    output D_COUT0;\n    output D_COUT1;\n    output D_COUT2;\n    output D_COUT3;\n    output D_COUT4;\n    output D_COUT5;\n    output D_COUT6;\n    output D_COUT7;\n    output D_COUT8;\n    output D_COUT9;\n    output D_COUT10;\n    output D_COUT11;\n    output D_COUT12;\n    output D_COUT13;\n    output D_COUT14;\n    output D_COUT15;\n    output D_COUT16;\n    output D_COUT17;\n    output D_COUT18;\n    output D_COUT19;\n    input D_REFCLKI;\n    output D_FFS_PLOL;\nendmodule\n\n",
             "cells_ff.vh": "// Diamond flip-flops\nmodule FD1P3AX(input     D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3AY(input     D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1S3AX(input     D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3AY(input     D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3BX(input PD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3DX(input CD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3IX(input CD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3JX(input PD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule\n\n// TODO: Diamond latches\n// module FL1P3AY(); endmodule\n// module FL1P3AZ(); endmodule\n// module FL1P3BX(); endmodule\n// module FL1P3DX(); endmodule\n// module FL1P3IY(); endmodule\n// module FL1P3JY(); endmodule\n// module FL1S3AX(); endmodule\n// module FL1S3AY(); endmodule\n\n// Diamond I/O registers\nmodule IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\n\nmodule OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\n\n// TODO: Diamond I/O latches\n// module IFS1S1B(input PD, D, SCLK, output Q); endmodule\n// module IFS1S1D(input CD, D, SCLK, output Q); endmodule\n// module IFS1S1I(input PD, D, SCLK, output Q); endmodule\n// module IFS1S1J(input CD, D, SCLK, output Q); endmodule\n",
             "cells_io.vh": "// Diamond I/O buffers\nmodule IB   ((* iopad_external_pin *) input I,     output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule IBPU ((* iopad_external_pin *) input I,     output O); (* PULLMODE=\"UP\"   *) TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule IBPD ((* iopad_external_pin *) input I,     output O); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule OB   (input I,     (* iopad_external_pin *) output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule\nmodule OBZ  (input I, T,  (* iopad_external_pin *) output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBZPU(input I, T,  (* iopad_external_pin *) output O); (* PULLMODE=\"UP\"   *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBZPD(input I, T,  (* iopad_external_pin *) output O); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule\nmodule BB   (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule BBPU (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"UP\"   *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule BBPD (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule ILVDS(input A, AN, (* iopad_external_pin *) output Z    ); TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule\nmodule OLVDS(input A,     (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule\n",
-            "cells_map.v": "module  \\$_DFF_N_ (input D, C, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFF_P_ (input D, C, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_NN_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_PN_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_NP_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\nmodule \\$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n    parameter WIDTH = 0;\n    parameter LUT = 0;\n\n    (* force_downto *)\n    input [WIDTH-1:0] A;\n    output Y;\n\n    generate\n        if (WIDTH == 1) begin\n            localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));\n        end else\n        if (WIDTH == 2) begin\n            localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));\n        end else\n        if (WIDTH == 3) begin\n            localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));\n        end else\n        if (WIDTH == 4) begin\n            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n        `ifndef NO_PFUMUX\n        end else\n        if (WIDTH == 5) begin\n            wire f0, f1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));\n        end else\n        if (WIDTH == 6) begin\n            wire f0, f1, f2, f3, g0, g1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));\n        end else\n        if (WIDTH == 7) begin\n            wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));\n            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));\n            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));\n            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));\n            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));\n        `endif\n        end else begin\n            wire _TECHMAP_FAIL_ = 1;\n        end\n    endgenerate\nendmodule\n`endif\n",
-            "cells_sim.v": "// ---------------------------------------\n\n(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n    parameter [15:0] INIT = 16'h0000;\n    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];\n    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];\n    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\n    specify\n        (A => Z) = 141;\n        (B => Z) = 275;\n        (C => Z) = 379;\n        (D => Z) = 379;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   cost of 5-input LUTs and is not intended to be instantiated\n// LUT5 = 2x LUT4 + PFUMX\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input M0, D, C, B, A, output Z);\n    specify\n        (M0 => Z) = 151;\n        (D => Z) = 239;\n        (C => Z) = 373;\n        (B => Z) = 477;\n        (A => Z) = 477;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 6-input LUTs and is not intended to be instantiated\n// LUT6 = 2x LUT5 + MUX2\n(* abc9_lut=4 *)\nmodule \\$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);\n    specify\n        (M1 => Z) = 148;\n        (M0 => Z) = 292;\n        (D => Z) = 380;\n        (C => Z) = 514;\n        (B => Z) = 618;\n        (A => Z) = 618;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 7-input LUTs and is not intended to be instantiated\n// LUT7 = 2x LUT6 + MUX2\n(* abc9_lut=8 *)\nmodule \\$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);\n    specify\n        (M2 => Z) = 148;\n        (M1 => Z) = 289;\n        (M0 => Z) = 433;\n        (D => Z) = 521;\n        (C => Z) = 655;\n        (B => Z) = 759;\n        (A => Z) = 759;\n    endspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule L6MUX21 (input D0, D1, SD, output Z);\n\tassign Z = SD ? D1 : D0;\n\tspecify\n\t\t(D0 => Z) = 140;\n\t\t(D1 => Z) = 141;\n\t\t(SD => Z) = 148;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule CCU2C(\n\t(* abc9_carry *)\n\tinput  CIN,\n\tinput  A0, B0, C0, D0, A1, B1, C1, D1,\n\toutput S0, S1,\n\t(* abc9_carry *)\n\toutput COUT\n);\n\tparameter [15:0] INIT0 = 16'h0000;\n\tparameter [15:0] INIT1 = 16'h0000;\n\tparameter INJECT1_0 = \"YES\";\n\tparameter INJECT1_1 = \"YES\";\n\n\t// First half\n\twire LUT4_0, LUT2_0;\n\tLUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));\n\tLUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));\n\twire gated_cin_0 = (INJECT1_0 == \"YES\") ? 1'b0 : CIN;\n\tassign S0 = LUT4_0 ^ gated_cin_0;\n\n\twire gated_lut2_0 = (INJECT1_0 == \"YES\") ? 1'b0 : LUT2_0;\n\twire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);\n\n\t// Second half\n\twire LUT4_1, LUT2_1;\n\tLUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));\n\tLUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));\n\twire gated_cin_1 = (INJECT1_1 == \"YES\") ? 1'b0 : cout_0;\n\tassign S1 = LUT4_1 ^ gated_cin_1;\n\n\twire gated_lut2_1 = (INJECT1_1 == \"YES\") ? 1'b0 : LUT2_1;\n\tassign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);\n\n\tspecify\n\t\t(A0 => S0) = 379;\n\t\t(B0 => S0) = 379;\n\t\t(C0 => S0) = 275;\n\t\t(D0 => S0) = 141;\n\t\t(CIN => S0) = 257;\n\t\t(A0 => S1) = 630;\n\t\t(B0 => S1) = 630;\n\t\t(C0 => S1) = 526;\n\t\t(D0 => S1) = 392;\n\t\t(A1 => S1) = 379;\n\t\t(B1 => S1) = 379;\n\t\t(C1 => S1) = 275;\n\t\t(D1 => S1) = 141;\n\t\t(CIN => S1) = 273;\n\t\t(A0 => COUT) = 516;\n\t\t(B0 => COUT) = 516;\n\t\t(C0 => COUT) = 412;\n\t\t(D0 => COUT) = 278;\n\t\t(A1 => COUT) = 516;\n\t\t(B1 => COUT) = 516;\n\t\t(C1 => COUT) = 412;\n\t\t(D1 => COUT) = 278;\n\t\t(CIN => COUT) = 43;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_RAM16X2 (\n\tinput DI0, DI1,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\tinput RAD0, RAD1, RAD2, RAD3,\n\toutput DO0, DO1\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter INITVAL_0 = 16'h0000;\n\tparameter INITVAL_1 = 16'h0000;\n\n\treg [1:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= {INITVAL_1[i], INITVAL_0[i]};\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};\n\n\tassign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule PFUMX (input ALUT, BLUT, C0, output Z);\n\tassign Z = C0 ? ALUT : BLUT;\n\tspecify\n\t\t(ALUT => Z) = 98;\n\t\t(BLUT => Z) = 98;\n\t\t(C0 => Z) = 151;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule TRELLIS_DPR16X4 (\n\tinput  [3:0] DI,\n\tinput  [3:0] WAD,\n\tinput        WRE,\n\tinput        WCK,\n\tinput  [3:0] RAD,\n\toutput [3:0] DO\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter [63:0] INITVAL = 64'h0000000000000000;\n\n\treg [3:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= INITVAL[4*i +: 4];\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[WAD] <= DI;\n\n\tassign DO = mem[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* abc9_box, lib_whitebox *)\nmodule DPR16X4C (\n\t\tinput [3:0] DI,\n\t\tinput WCK, WRE,\n\t\tinput [3:0] RAD,\n\t\tinput [3:0] WAD,\n\t\toutput [3:0] DO\n);\n\t// For legacy Lattice compatibility, INITIVAL is a hex\n\t// string rather than a numeric parameter\n\tparameter INITVAL = \"0x0000000000000000\";\n\n\tfunction [63:0] convert_initval;\n\t\tinput [143:0] hex_initval;\n\t\treg done;\n\t\treg [63:0] temp;\n\t\treg [7:0] char;\n\t\tinteger i;\n\t\tbegin\n\t\t\tdone = 1'b0;\n\t\t\ttemp = 0;\n\t\t\tfor (i = 0; i < 16; i = i + 1) begin\n\t\t\t\tif (!done) begin\n\t\t\t\t\tchar = hex_initval[8*i +: 8];\n\t\t\t\t\tif (char == \"x\") begin\n\t\t\t\t\t\tdone = 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (char >= \"0\" && char <= \"9\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = char - \"0\";\n\t\t\t\t\t\telse if (char >= \"A\" && char <= \"F\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"A\";\n\t\t\t\t\t\telse if (char >= \"a\" && char <= \"f\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"a\";\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tconvert_initval = temp;\n\t\tend\n\tendfunction\n\n\tlocalparam conv_initval = convert_initval(INITVAL);\n\n\treg [3:0] ram[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i = i + 1) begin\n\t\t\tram[i] <= conv_initval[4*i +: 4];\n\t\tend\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tram[WAD] <= DI;\n\n\tassign DO = ram[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* lib_whitebox *)\nmodule LUT2(input A, B, output Z);\n    parameter [3:0] INIT = 4'h0;\n    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\nendmodule\n\n// ---------------------------------------\n\n`ifdef YOSYS\n(* abc9_flop=(SRMODE != \"ASYNC\"), abc9_box=(SRMODE == \"ASYNC\"), lib_whitebox *)\n`endif\nmodule TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend else begin\n\t\t\talways @(posedge muxclk)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend\n\tendgenerate\n\n\tspecify\n\t\t$setup(DI, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(CE, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(LSR, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(DI, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(CE, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(LSR, posedge CLK &&& CLKMUX != \"INV\", 0);\n`ifndef YOSYS\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX == \"INV\") (negedge CLK => (Q : srval)) = 0;\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX != \"INV\") (posedge CLK => (Q : srval)) = 0;\n`else\n\t\tif (SRMODE == \"ASYNC\" && muxlsr) (LSR => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!muxlsr && muxce && CLKMUX == \"INV\") (negedge CLK => (Q : DI)) = 0;\n\t\tif (!muxlsr && muxce && CLKMUX != \"INV\") (posedge CLK => (Q : DI)) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* keep *)\nmodule TRELLIS_IO(\n\t(* iopad_external_pin *)\n\tinout B,\n\tinput I,\n\tinput T,\n\toutput O\n);\n\tparameter DIR = \"INPUT\";\n\treg T_pd;\n\talways @(*) if (T === 1'bz) T_pd = 1'b0; else T_pd = T;\n\n\tgenerate\n\t\tif (DIR == \"INPUT\") begin\n\t\t\tassign B = 1'bz;\n\t\t\tassign O = B;\n\t\tend else if (DIR == \"OUTPUT\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = 1'bx;\n\t\tend else if (DIR == \"BIDIR\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = B;\n\t\tend else begin\n\t\t\tERROR_UNKNOWN_IO_MODE error();\n\t\tend\n\tendgenerate\n\nendmodule\n\n// ---------------------------------------\n\nmodule INV(input A, output Z);\n\tassign Z = !A;\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_COMB(\n\tinput A, B, C, D, M,\n\tinput FCI, F1, FXA, FXB,\n\tinput WD,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\toutput F, FCO, OFX\n);\n\tparameter MODE = \"LOGIC\";\n\tparameter INITVAL = 16'h0;\n\tparameter CCU2_INJECT1 = \"NO\";\n\tparameter WREMUX = \"WRE\";\n\tparameter IS_Z1 = 1'b0;\n\n\tgenerate\n\t\tif (MODE == \"LOGIC\") begin: mode_logic\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));\n\t\tend else if (MODE == \"CCU2\") begin: mode_ccu2\n\t\t\twire l4o, l2o;\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));\n\t\t\tLUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));\n\t\t\twire gated_cin_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : FCI;\n\t\t\tassign F = l4o ^ gated_cin_0;\n\t\t\twire gated_lut2_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : l2o;\n\t\t\twire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);\n\t\tend else if (MODE == \"DPRAM\") begin: mode_dpram\n\t\t\treg [15:0] ram = INITVAL;\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tram[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\t\tassign F = ram[{A, C, B, D}];\n\t\tend else begin\n\t\t\t$error(\"unsupported COMB mode %s\", MODE);\n\t\tend\n\n \t\tif (IS_Z1)\n\t\t\tL6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));\n\t\telse\n\t\t\tPFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));\n\tendgenerate\n\nendmodule\n\n(* blackbox *)\nmodule DP16KD(\n  input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,\n  input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,\n  input CEA, OCEA, CLKA, WEA, RSTA,\n  input CSA2, CSA1, CSA0,\n  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,\n\n  input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,\n  input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,\n  input CEB, OCEB, CLKB, WEB, RSTB,\n  input CSB2, CSB1, CSB0,\n  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0\n);\n\tparameter DATA_WIDTH_A = 18;\n\tparameter DATA_WIDTH_B = 18;\n\n\tparameter REGMODE_A = \"NOREG\";\n\tparameter REGMODE_B = \"NOREG\";\n\n\tparameter RESETMODE = \"SYNC\";\n\tparameter ASYNC_RESET_RELEASE = \"SYNC\";\n\n\tparameter CSDECODE_A = \"0b000\";\n\tparameter CSDECODE_B = \"0b000\";\n\n\tparameter WRITEMODE_A = \"NORMAL\";\n\tparameter WRITEMODE_B = \"NORMAL\";\n\n\tparameter DIA17MUX = \"DIA17\";\n\tparameter DIA16MUX = \"DIA16\";\n\tparameter DIA15MUX = \"DIA15\";\n\tparameter DIA14MUX = \"DIA14\";\n\tparameter DIA13MUX = \"DIA13\";\n\tparameter DIA12MUX = \"DIA12\";\n\tparameter DIA11MUX = \"DIA11\";\n\tparameter DIA10MUX = \"DIA10\";\n\tparameter DIA9MUX = \"DIA9\";\n\tparameter DIA8MUX = \"DIA8\";\n\tparameter DIA7MUX = \"DIA7\";\n\tparameter DIA6MUX = \"DIA6\";\n\tparameter DIA5MUX = \"DIA5\";\n\tparameter DIA4MUX = \"DIA4\";\n\tparameter DIA3MUX = \"DIA3\";\n\tparameter DIA2MUX = \"DIA2\";\n\tparameter DIA1MUX = \"DIA1\";\n\tparameter DIA0MUX = \"DIA0\";\n\tparameter ADA13MUX = \"ADA13\";\n\tparameter ADA12MUX = \"ADA12\";\n\tparameter ADA11MUX = \"ADA11\";\n\tparameter ADA10MUX = \"ADA10\";\n\tparameter ADA9MUX = \"ADA9\";\n\tparameter ADA8MUX = \"ADA8\";\n\tparameter ADA7MUX = \"ADA7\";\n\tparameter ADA6MUX = \"ADA6\";\n\tparameter ADA5MUX = \"ADA5\";\n\tparameter ADA4MUX = \"ADA4\";\n\tparameter ADA3MUX = \"ADA3\";\n\tparameter ADA2MUX = \"ADA2\";\n\tparameter ADA1MUX = \"ADA1\";\n\tparameter ADA0MUX = \"ADA0\";\n\tparameter CEAMUX = \"CEA\";\n\tparameter OCEAMUX = \"OCEA\";\n\tparameter CLKAMUX = \"CLKA\";\n\tparameter WEAMUX = \"WEA\";\n\tparameter RSTAMUX = \"RSTA\";\n\tparameter CSA2MUX = \"CSA2\";\n\tparameter CSA1MUX = \"CSA1\";\n\tparameter CSA0MUX = \"CSA0\";\n\tparameter DOA17MUX = \"DOA17\";\n\tparameter DOA16MUX = \"DOA16\";\n\tparameter DOA15MUX = \"DOA15\";\n\tparameter DOA14MUX = \"DOA14\";\n\tparameter DOA13MUX = \"DOA13\";\n\tparameter DOA12MUX = \"DOA12\";\n\tparameter DOA11MUX = \"DOA11\";\n\tparameter DOA10MUX = \"DOA10\";\n\tparameter DOA9MUX = \"DOA9\";\n\tparameter DOA8MUX = \"DOA8\";\n\tparameter DOA7MUX = \"DOA7\";\n\tparameter DOA6MUX = \"DOA6\";\n\tparameter DOA5MUX = \"DOA5\";\n\tparameter DOA4MUX = \"DOA4\";\n\tparameter DOA3MUX = \"DOA3\";\n\tparameter DOA2MUX = \"DOA2\";\n\tparameter DOA1MUX = \"DOA1\";\n\tparameter DOA0MUX = \"DOA0\";\n\tparameter DIB17MUX = \"DIB17\";\n\tparameter DIB16MUX = \"DIB16\";\n\tparameter DIB15MUX = \"DIB15\";\n\tparameter DIB14MUX = \"DIB14\";\n\tparameter DIB13MUX = \"DIB13\";\n\tparameter DIB12MUX = \"DIB12\";\n\tparameter DIB11MUX = \"DIB11\";\n\tparameter DIB10MUX = \"DIB10\";\n\tparameter DIB9MUX = \"DIB9\";\n\tparameter DIB8MUX = \"DIB8\";\n\tparameter DIB7MUX = \"DIB7\";\n\tparameter DIB6MUX = \"DIB6\";\n\tparameter DIB5MUX = \"DIB5\";\n\tparameter DIB4MUX = \"DIB4\";\n\tparameter DIB3MUX = \"DIB3\";\n\tparameter DIB2MUX = \"DIB2\";\n\tparameter DIB1MUX = \"DIB1\";\n\tparameter DIB0MUX = \"DIB0\";\n\tparameter ADB13MUX = \"ADB13\";\n\tparameter ADB12MUX = \"ADB12\";\n\tparameter ADB11MUX = \"ADB11\";\n\tparameter ADB10MUX = \"ADB10\";\n\tparameter ADB9MUX = \"ADB9\";\n\tparameter ADB8MUX = \"ADB8\";\n\tparameter ADB7MUX = \"ADB7\";\n\tparameter ADB6MUX = \"ADB6\";\n\tparameter ADB5MUX = \"ADB5\";\n\tparameter ADB4MUX = \"ADB4\";\n\tparameter ADB3MUX = \"ADB3\";\n\tparameter ADB2MUX = \"ADB2\";\n\tparameter ADB1MUX = \"ADB1\";\n\tparameter ADB0MUX = \"ADB0\";\n\tparameter CEBMUX = \"CEB\";\n\tparameter OCEBMUX = \"OCEB\";\n\tparameter CLKBMUX = \"CLKB\";\n\tparameter WEBMUX = \"WEB\";\n\tparameter RSTBMUX = \"RSTB\";\n\tparameter CSB2MUX = \"CSB2\";\n\tparameter CSB1MUX = \"CSB1\";\n\tparameter CSB0MUX = \"CSB0\";\n\tparameter DOB17MUX = \"DOB17\";\n\tparameter DOB16MUX = \"DOB16\";\n\tparameter DOB15MUX = \"DOB15\";\n\tparameter DOB14MUX = \"DOB14\";\n\tparameter DOB13MUX = \"DOB13\";\n\tparameter DOB12MUX = \"DOB12\";\n\tparameter DOB11MUX = \"DOB11\";\n\tparameter DOB10MUX = \"DOB10\";\n\tparameter DOB9MUX = \"DOB9\";\n\tparameter DOB8MUX = \"DOB8\";\n\tparameter DOB7MUX = \"DOB7\";\n\tparameter DOB6MUX = \"DOB6\";\n\tparameter DOB5MUX = \"DOB5\";\n\tparameter DOB4MUX = \"DOB4\";\n\tparameter DOB3MUX = \"DOB3\";\n\tparameter DOB2MUX = \"DOB2\";\n\tparameter DOB1MUX = \"DOB1\";\n\tparameter DOB0MUX = \"DOB0\";\n\n\tparameter WID = 0;\n\n\tparameter GSR = \"ENABLED\";\n\n\tparameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_DATA = \"STATIC\";\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
-            "dsp_map.v": "module \\$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\n\tparameter A_WIDTH = 18;\n\tparameter B_WIDTH = 18;\n\tparameter Y_WIDTH = 36;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT18X18D _TECHMAP_REPLACE_ (\n\t\t.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),\n\t\t.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),\n\t\t.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),\n\n\t\t.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])\n\t);\nendmodule\n",
-            "latches_map.v": "module \\$_DLATCH_N_ (E, D, Q);\n  wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n  input E, D;\n  output Q = !E ? D : Q;\nendmodule\n\nmodule \\$_DLATCH_P_ (E, D, Q);\n  wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n  input E, D;\n  output Q = E ? D : Q;\nendmodule\n",
-            "lutrams.txt": "ram distributed $__TRELLIS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit any;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock anyedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
-            "lutrams_map.v": "module $__TRELLIS_DPR16X4_(...);\n\nparameter INIT = 64'bx;\nparameter PORT_W_CLK_POL = 1;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput [3:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nlocalparam WCKMUX = PORT_W_CLK_POL ? \"WCK\" : \"INV\";\n\nTRELLIS_DPR16X4 #(\n\t.INITVAL(INIT),\n\t.WCKMUX(WCKMUX),\n\t.WREMUX(\"WRE\")\n) _TECHMAP_REPLACE_ (\n\t.RAD(PORT_R_ADDR),\n\t.DO(PORT_R_RD_DATA),\n\n\t.WAD(PORT_W_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.WCK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n\nendmodule\n",
+            "cells_sim.v": "`include \"common_sim.vh\"\n`include \"ccu2c_sim.vh\"\n\n(* blackbox *)\nmodule DP16KD(\n  input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,\n  input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,\n  input CEA, OCEA, CLKA, WEA, RSTA,\n  input CSA2, CSA1, CSA0,\n  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,\n\n  input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,\n  input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,\n  input CEB, OCEB, CLKB, WEB, RSTB,\n  input CSB2, CSB1, CSB0,\n  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0\n);\n\tparameter DATA_WIDTH_A = 18;\n\tparameter DATA_WIDTH_B = 18;\n\n\tparameter REGMODE_A = \"NOREG\";\n\tparameter REGMODE_B = \"NOREG\";\n\n\tparameter RESETMODE = \"SYNC\";\n\tparameter ASYNC_RESET_RELEASE = \"SYNC\";\n\n\tparameter CSDECODE_A = \"0b000\";\n\tparameter CSDECODE_B = \"0b000\";\n\n\tparameter WRITEMODE_A = \"NORMAL\";\n\tparameter WRITEMODE_B = \"NORMAL\";\n\n\tparameter DIA17MUX = \"DIA17\";\n\tparameter DIA16MUX = \"DIA16\";\n\tparameter DIA15MUX = \"DIA15\";\n\tparameter DIA14MUX = \"DIA14\";\n\tparameter DIA13MUX = \"DIA13\";\n\tparameter DIA12MUX = \"DIA12\";\n\tparameter DIA11MUX = \"DIA11\";\n\tparameter DIA10MUX = \"DIA10\";\n\tparameter DIA9MUX = \"DIA9\";\n\tparameter DIA8MUX = \"DIA8\";\n\tparameter DIA7MUX = \"DIA7\";\n\tparameter DIA6MUX = \"DIA6\";\n\tparameter DIA5MUX = \"DIA5\";\n\tparameter DIA4MUX = \"DIA4\";\n\tparameter DIA3MUX = \"DIA3\";\n\tparameter DIA2MUX = \"DIA2\";\n\tparameter DIA1MUX = \"DIA1\";\n\tparameter DIA0MUX = \"DIA0\";\n\tparameter ADA13MUX = \"ADA13\";\n\tparameter ADA12MUX = \"ADA12\";\n\tparameter ADA11MUX = \"ADA11\";\n\tparameter ADA10MUX = \"ADA10\";\n\tparameter ADA9MUX = \"ADA9\";\n\tparameter ADA8MUX = \"ADA8\";\n\tparameter ADA7MUX = \"ADA7\";\n\tparameter ADA6MUX = \"ADA6\";\n\tparameter ADA5MUX = \"ADA5\";\n\tparameter ADA4MUX = \"ADA4\";\n\tparameter ADA3MUX = \"ADA3\";\n\tparameter ADA2MUX = \"ADA2\";\n\tparameter ADA1MUX = \"ADA1\";\n\tparameter ADA0MUX = \"ADA0\";\n\tparameter CEAMUX = \"CEA\";\n\tparameter OCEAMUX = \"OCEA\";\n\tparameter CLKAMUX = \"CLKA\";\n\tparameter WEAMUX = \"WEA\";\n\tparameter RSTAMUX = \"RSTA\";\n\tparameter CSA2MUX = \"CSA2\";\n\tparameter CSA1MUX = \"CSA1\";\n\tparameter CSA0MUX = \"CSA0\";\n\tparameter DOA17MUX = \"DOA17\";\n\tparameter DOA16MUX = \"DOA16\";\n\tparameter DOA15MUX = \"DOA15\";\n\tparameter DOA14MUX = \"DOA14\";\n\tparameter DOA13MUX = \"DOA13\";\n\tparameter DOA12MUX = \"DOA12\";\n\tparameter DOA11MUX = \"DOA11\";\n\tparameter DOA10MUX = \"DOA10\";\n\tparameter DOA9MUX = \"DOA9\";\n\tparameter DOA8MUX = \"DOA8\";\n\tparameter DOA7MUX = \"DOA7\";\n\tparameter DOA6MUX = \"DOA6\";\n\tparameter DOA5MUX = \"DOA5\";\n\tparameter DOA4MUX = \"DOA4\";\n\tparameter DOA3MUX = \"DOA3\";\n\tparameter DOA2MUX = \"DOA2\";\n\tparameter DOA1MUX = \"DOA1\";\n\tparameter DOA0MUX = \"DOA0\";\n\tparameter DIB17MUX = \"DIB17\";\n\tparameter DIB16MUX = \"DIB16\";\n\tparameter DIB15MUX = \"DIB15\";\n\tparameter DIB14MUX = \"DIB14\";\n\tparameter DIB13MUX = \"DIB13\";\n\tparameter DIB12MUX = \"DIB12\";\n\tparameter DIB11MUX = \"DIB11\";\n\tparameter DIB10MUX = \"DIB10\";\n\tparameter DIB9MUX = \"DIB9\";\n\tparameter DIB8MUX = \"DIB8\";\n\tparameter DIB7MUX = \"DIB7\";\n\tparameter DIB6MUX = \"DIB6\";\n\tparameter DIB5MUX = \"DIB5\";\n\tparameter DIB4MUX = \"DIB4\";\n\tparameter DIB3MUX = \"DIB3\";\n\tparameter DIB2MUX = \"DIB2\";\n\tparameter DIB1MUX = \"DIB1\";\n\tparameter DIB0MUX = \"DIB0\";\n\tparameter ADB13MUX = \"ADB13\";\n\tparameter ADB12MUX = \"ADB12\";\n\tparameter ADB11MUX = \"ADB11\";\n\tparameter ADB10MUX = \"ADB10\";\n\tparameter ADB9MUX = \"ADB9\";\n\tparameter ADB8MUX = \"ADB8\";\n\tparameter ADB7MUX = \"ADB7\";\n\tparameter ADB6MUX = \"ADB6\";\n\tparameter ADB5MUX = \"ADB5\";\n\tparameter ADB4MUX = \"ADB4\";\n\tparameter ADB3MUX = \"ADB3\";\n\tparameter ADB2MUX = \"ADB2\";\n\tparameter ADB1MUX = \"ADB1\";\n\tparameter ADB0MUX = \"ADB0\";\n\tparameter CEBMUX = \"CEB\";\n\tparameter OCEBMUX = \"OCEB\";\n\tparameter CLKBMUX = \"CLKB\";\n\tparameter WEBMUX = \"WEB\";\n\tparameter RSTBMUX = \"RSTB\";\n\tparameter CSB2MUX = \"CSB2\";\n\tparameter CSB1MUX = \"CSB1\";\n\tparameter CSB0MUX = \"CSB0\";\n\tparameter DOB17MUX = \"DOB17\";\n\tparameter DOB16MUX = \"DOB16\";\n\tparameter DOB15MUX = \"DOB15\";\n\tparameter DOB14MUX = \"DOB14\";\n\tparameter DOB13MUX = \"DOB13\";\n\tparameter DOB12MUX = \"DOB12\";\n\tparameter DOB11MUX = \"DOB11\";\n\tparameter DOB10MUX = \"DOB10\";\n\tparameter DOB9MUX = \"DOB9\";\n\tparameter DOB8MUX = \"DOB8\";\n\tparameter DOB7MUX = \"DOB7\";\n\tparameter DOB6MUX = \"DOB6\";\n\tparameter DOB5MUX = \"DOB5\";\n\tparameter DOB4MUX = \"DOB4\";\n\tparameter DOB3MUX = \"DOB3\";\n\tparameter DOB2MUX = \"DOB2\";\n\tparameter DOB1MUX = \"DOB1\";\n\tparameter DOB0MUX = \"DOB0\";\n\n\tparameter WID = 0;\n\n\tparameter GSR = \"ENABLED\";\n\n\tparameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_DATA = \"STATIC\";\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
+            "common_sim.vh": "// ---------------------------------------\n\n(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n    parameter [15:0] INIT = 16'h0000;\n    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];\n    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];\n    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\n    specify\n        (A => Z) = 141;\n        (B => Z) = 275;\n        (C => Z) = 379;\n        (D => Z) = 379;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   cost of 5-input LUTs and is not intended to be instantiated\n// LUT5 = 2x LUT4 + PFUMX\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input M0, D, C, B, A, output Z);\n    specify\n        (M0 => Z) = 151;\n        (D => Z) = 239;\n        (C => Z) = 373;\n        (B => Z) = 477;\n        (A => Z) = 477;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 6-input LUTs and is not intended to be instantiated\n// LUT6 = 2x LUT5 + MUX2\n(* abc9_lut=4 *)\nmodule \\$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);\n    specify\n        (M1 => Z) = 148;\n        (M0 => Z) = 292;\n        (D => Z) = 380;\n        (C => Z) = 514;\n        (B => Z) = 618;\n        (A => Z) = 618;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 7-input LUTs and is not intended to be instantiated\n// LUT7 = 2x LUT6 + MUX2\n(* abc9_lut=8 *)\nmodule \\$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);\n    specify\n        (M2 => Z) = 148;\n        (M1 => Z) = 289;\n        (M0 => Z) = 433;\n        (D => Z) = 521;\n        (C => Z) = 655;\n        (B => Z) = 759;\n        (A => Z) = 759;\n    endspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule L6MUX21 (input D0, D1, SD, output Z);\n\tassign Z = SD ? D1 : D0;\n\tspecify\n\t\t(D0 => Z) = 140;\n\t\t(D1 => Z) = 141;\n\t\t(SD => Z) = 148;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_RAM16X2 (\n\tinput DI0, DI1,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\tinput RAD0, RAD1, RAD2, RAD3,\n\toutput DO0, DO1\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter INITVAL_0 = 16'h0000;\n\tparameter INITVAL_1 = 16'h0000;\n\n\treg [1:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= {INITVAL_1[i], INITVAL_0[i]};\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};\n\n\tassign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule PFUMX (input ALUT, BLUT, C0, output Z);\n\tassign Z = C0 ? ALUT : BLUT;\n\tspecify\n\t\t(ALUT => Z) = 98;\n\t\t(BLUT => Z) = 98;\n\t\t(C0 => Z) = 151;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule TRELLIS_DPR16X4 (\n\tinput  [3:0] DI,\n\tinput  [3:0] WAD,\n\tinput        WRE,\n\tinput        WCK,\n\tinput  [3:0] RAD,\n\toutput [3:0] DO\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter [63:0] INITVAL = 64'h0000000000000000;\n\n\treg [3:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= INITVAL[4*i +: 4];\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[WAD] <= DI;\n\n\tassign DO = mem[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* abc9_box, lib_whitebox *)\nmodule DPR16X4C (\n\t\tinput [3:0] DI,\n\t\tinput WCK, WRE,\n\t\tinput [3:0] RAD,\n\t\tinput [3:0] WAD,\n\t\toutput [3:0] DO\n);\n\t// For legacy Lattice compatibility, INITIVAL is a hex\n\t// string rather than a numeric parameter\n\tparameter INITVAL = \"0x0000000000000000\";\n\n\tfunction [63:0] convert_initval;\n\t\tinput [143:0] hex_initval;\n\t\treg done;\n\t\treg [63:0] temp;\n\t\treg [7:0] char;\n\t\tinteger i;\n\t\tbegin\n\t\t\tdone = 1'b0;\n\t\t\ttemp = 0;\n\t\t\tfor (i = 0; i < 16; i = i + 1) begin\n\t\t\t\tif (!done) begin\n\t\t\t\t\tchar = hex_initval[8*i +: 8];\n\t\t\t\t\tif (char == \"x\") begin\n\t\t\t\t\t\tdone = 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (char >= \"0\" && char <= \"9\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = char - \"0\";\n\t\t\t\t\t\telse if (char >= \"A\" && char <= \"F\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"A\";\n\t\t\t\t\t\telse if (char >= \"a\" && char <= \"f\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"a\";\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tconvert_initval = temp;\n\t\tend\n\tendfunction\n\n\tlocalparam conv_initval = convert_initval(INITVAL);\n\n\treg [3:0] ram[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i = i + 1) begin\n\t\t\tram[i] <= conv_initval[4*i +: 4];\n\t\tend\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tram[WAD] <= DI;\n\n\tassign DO = ram[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* lib_whitebox *)\nmodule LUT2(input A, B, output Z);\n    parameter [3:0] INIT = 4'h0;\n    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\nendmodule\n\n// ---------------------------------------\n\n`ifdef YOSYS\n(* abc9_flop=(SRMODE != \"ASYNC\"), abc9_box=(SRMODE == \"ASYNC\"), lib_whitebox *)\n`endif\nmodule TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend else begin\n\t\t\talways @(posedge muxclk)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend\n\tendgenerate\n\n\tspecify\n\t\t$setup(DI, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(CE, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(LSR, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(DI, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(CE, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(LSR, posedge CLK &&& CLKMUX != \"INV\", 0);\n`ifndef YOSYS\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX == \"INV\") (negedge CLK => (Q : srval)) = 0;\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX != \"INV\") (posedge CLK => (Q : srval)) = 0;\n`else\n\t\tif (SRMODE == \"ASYNC\" && muxlsr) (LSR => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!muxlsr && muxce && CLKMUX == \"INV\") (negedge CLK => (Q : DI)) = 0;\n\t\tif (!muxlsr && muxce && CLKMUX != \"INV\") (posedge CLK => (Q : DI)) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* keep *)\nmodule TRELLIS_IO(\n\t(* iopad_external_pin *)\n\tinout B,\n\tinput I,\n\tinput T,\n\toutput O\n);\n\tparameter DIR = \"INPUT\";\n\treg T_pd;\n\talways @(*) if (T === 1'bz) T_pd = 1'b0; else T_pd = T;\n\n\tgenerate\n\t\tif (DIR == \"INPUT\") begin\n\t\t\tassign B = 1'bz;\n\t\t\tassign O = B;\n\t\tend else if (DIR == \"OUTPUT\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = 1'bx;\n\t\tend else if (DIR == \"BIDIR\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = B;\n\t\tend else begin\n\t\t\tERROR_UNKNOWN_IO_MODE error();\n\t\tend\n\tendgenerate\n\nendmodule\n\n// ---------------------------------------\n\nmodule INV(input A, output Z);\n\tassign Z = !A;\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_COMB(\n\tinput A, B, C, D, M,\n\tinput FCI, F1, FXA, FXB,\n\tinput WD,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\toutput F, FCO, OFX\n);\n\tparameter MODE = \"LOGIC\";\n\tparameter INITVAL = 16'h0;\n\tparameter CCU2_INJECT1 = \"NO\";\n\tparameter WREMUX = \"WRE\";\n\tparameter IS_Z1 = 1'b0;\n\n\tgenerate\n\t\tif (MODE == \"LOGIC\") begin: mode_logic\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));\n\t\tend else if (MODE == \"CCU2\") begin: mode_ccu2\n\t\t\twire l4o, l2o;\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));\n\t\t\tLUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));\n\t\t\twire gated_cin_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : FCI;\n\t\t\tassign F = l4o ^ gated_cin_0;\n\t\t\twire gated_lut2_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : l2o;\n\t\t\twire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);\n\t\tend else if (MODE == \"DPRAM\") begin: mode_dpram\n\t\t\treg [15:0] ram = INITVAL;\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tram[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\t\tassign F = ram[{A, C, B, D}];\n\t\tend else begin\n\t\t\t$error(\"unsupported COMB mode %s\", MODE);\n\t\tend\n\n \t\tif (IS_Z1)\n\t\t\tL6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));\n\t\telse\n\t\t\tPFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));\n\tendgenerate\n\nendmodule\n\n// Constants\nmodule VLO(output Z);\n\tassign Z = 1'b0;\nendmodule\n\nmodule VHI(output Z);\n\tassign Z = 1'b1;\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
         },
         "efinix": {
             "arith_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2018  Miodrag Milanovic <micko@yosyshq.com>\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_efinix_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH  = 1;\n\tparameter B_WIDTH  = 1;\n\tparameter Y_WIDTH  = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n   \n    wire CIx;\n    (* force_downto *)\n    wire [Y_WIDTH-1:0] COx;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] C = { COx, CIx };\n\n    EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))\n    adder_cin  (\n        .I0(CI),\n        .I1(1'b1),\n        .CI(1'b0),\n        .CO(CIx)\n\t);\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice\n\t\tEFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))\n\t\tadder_i (\n\t\t\t.I0(AA[i]),\n\t\t\t.I1(BB[i]),\n\t\t\t.CI(C[i]),\n\t\t\t.O(Y[i]),\n\t\t\t.CO(COx[i])\n\t\t);\n\t\tEFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))\t\t\t\t\n\t\tadder_cout  (\n\t\t\t.I0(1'b0),\n\t\t\t.I1(1'b0),\n\t\t\t.CI(COx[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\t  end: slice\t  \n\tendgenerate\n\n   /* End implementation */\n   assign X = AA ^ BB;\nendmodule\n",
@@ -173,8 +167,8 @@ export const filesystem = {
                 "ffmerge.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2021  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFMERGE_H\n#define FFMERGE_H\n\n#include \"kernel/ffinit.h\"\n#include \"kernel/ff.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// A helper class for passes that want to merge FFs on the input or output\n// of a cell into the cell itself.\n//\n// The procedure is:\n//\n// 1. Construct this class (at beginning of processing for a given module).\n// 2. For every considered cell:\n//\n//    a. Call find_output_ff for every considered output.\n//    b. Call find_input_ff for every considered input.\n//    c. Look at the FF description returned (if any) from each call, reject\n//       results that cannot be merged into given cell for any reason.\n//       If both inputs and outputs are being merged, take care of FF bits that\n//       are returned in both input and output results (a FF bit cannot be\n//       merged to both).  Decide on the final set of FF bits to merge.\n//    d. Call remove_output_ff for every find_output_ff result that will be used\n//       for merging.  This removes the actual FF bits from design and from index.\n//    e. Call mark_input_ff for every find_input_ff result that will be used\n//       for merging.  This updates the index disallowing further usage of these\n//       FF bits for output FF merging, if they were eligible before.  The actual\n//       FF bits are still left in the design and can be merged into other inputs.\n//       If the FF bits are not otherwise used, they will be removed by later\n//       opt passes.\n//    f. Merge the FFs into the cell.\n//\n// Note that, if both inputs and outputs are being considered for merging in\n// a single pass, the result may be nondeterministic (depending on cell iteration\n// order) because a given FF bit could be eligible for both input and output merge,\n// perhaps in different cells.  For this reason, it may be a good idea to separate\n// input and output merging.\n\nstruct FfMergeHelper\n{\n\tconst SigMapView *sigmap;\n\tRTLIL::Module *module;\n\tFfInitVals *initvals;\n\n\tdict<SigBit, std::pair<Cell*, int>> dff_driver;\n\tdict<SigBit, pool<std::pair<Cell*, int>>> dff_sink;\n\tdict<SigBit, int> sigbit_users_count;\n\n\t// Returns true if all bits in sig are completely unused.\n\tbool is_output_unused(RTLIL::SigSpec sig);\n\n\t// Finds the FF to merge into a given cell output.  Takes sig, which\n\t// is the current cell output — it will be the sig_d of the found FF.\n\t// If found, returns true, and fills the two output arguments.\n\t//\n\t// For every bit of sig, this function finds a FF bit that has\n\t// the same sig_d, and fills the output FfData according to the FF\n\t// bits found.  This function will only consider FF bits that are\n\t// the only user of the given sig bits — if any bit in sig is used\n\t// by anything other than a single FF, this function will return false.\n\t//\n\t// The returned FfData structure does not correspond to any actual FF\n\t// cell in the design — it is the amalgamation of extracted FF bits,\n\t// possibly coming from several FF cells.\n\t//\n\t// If some of the bits in sig have no users at all, this function\n\t// will accept them as well (and fill returned FfData with dummy values\n\t// for the given bit, effectively synthesizing an unused FF bit of the\n\t// appropriate type).  However, if all bits in sig are completely\n\t// unused, this function will fail and return false (having no idea\n\t// what kind of FF to produce) — use the above helper if that case\n\t// is important to handle.\n\t//\n\t// Note that this function does not remove the FF bits returned from\n\t// the design — this is so that the caller can decide whether to accept\n\t// this FF for merging or not.  If the result is accepted,\n\t// remove_output_ff should be called on the second output argument.\n\tbool find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// Like above, but returns a FF to merge into a given cell input.  Takes\n\t// sig_q, which is the current cell input — it will search for FFs with\n\t// matching sig_q.\n\t//\n\t// As opposed to find_output_ff, this function doesn't care about usage\n\t// counts, and may return FF bits that also have other fanout.  This\n\t// should not be a problem for input FF merging.\n\t//\n\t// As a special case, if some of the bits in sig_q are constant, this\n\t// function will accept them as well, by synthesizing in-place\n\t// a constant-input FF bit (with matching initial value and reset value).\n\t// However, this will not work if the input is all-constant — if the caller\n\t// cares about this case, it needs to check for it explicitely.\n\tbool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_output_ff result that will be merged.  This\n\t// marks the given FF bits as used up (and not to be considered for\n\t// further merging as inputs), and reconnects their Q ports to a dummy\n\t// wire (since the wire previously connected there will now be driven\n\t// by the merged-to cell instead).\n\tvoid remove_output_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_input_ff result that will be merged.  This\n\t// marks the given FF bits as used, and disallows merging them as\n\t// outputs.  They can, however, still be merged as inputs again\n\t// (perhaps for another cell).\n\tvoid mark_input_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\tvoid set(FfInitVals *initvals_, RTLIL::Module *module_);\n\n\tvoid clear();\n\n\tFfMergeHelper(FfInitVals *initvals, RTLIL::Module *module) {\n\t\tset(initvals, module);\n\t}\n\n\tFfMergeHelper() {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "fmt.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2020  whitequark <whitequark@whitequark.org>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n//   $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING  = 0,\n\t\tINTEGER = 1,\n\t\tTIME    = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n//   \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tLITERAL  \t= 0,\n\t\tINTEGER \t= 1,\n\t\tSTRING    = 2,\n\t\tUNICHAR   = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign = MINUS;\n\tbool hex_upper = false;\n\tbool show_base = false;\n\tbool group = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_literal(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "gzip.h": "#include <string>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_GZIP_H\n#define YOSYS_GZIP_H\n\nYOSYS_NAMESPACE_BEGIN\n\n#ifdef YOSYS_ENABLE_ZLIB\n\nnamespace Zlib {\n#include <zlib.h>\n}\n\n/*\nAn output stream that uses a stringbuf to buffer data internally,\nusing zlib to write gzip-compressed data every time the stream is flushed.\n*/\nclass gzip_ostream : public std::ostream {\npublic:\n\tgzip_ostream(): std::ostream(nullptr) {\n\t\trdbuf(&outbuf);\n\t}\n\tbool open(const std::string &filename) {\n\t\treturn outbuf.open(filename);\n\t}\nprivate:\n\tclass obuf : public std::stringbuf {\n\tpublic:\n\t\tobuf();\n\t\tbool open(const std::string &filename);\n\t\tvirtual int sync() override;\n\t\tvirtual ~obuf();\n\tprivate:\n\t\tstatic const int buffer_size = 4096;\n\t\tchar buffer[buffer_size];             // Internal buffer for compressed data\n\t\tZlib::gzFile gzf = nullptr;                 // Handle to the gzip file\n\t};\n\n\tobuf outbuf;  // The stream buffer instance\n};\n\n/*\nAn input stream that uses zlib to read gzip-compressed data from a file,\nbuffering the decompressed data internally using its own buffer.\n*/\nclass gzip_istream final : public std::istream {\npublic:\n\tgzip_istream() : std::istream(&inbuf) {}\n\tbool open(const std::string& filename) {\n\t\treturn inbuf.open(filename);\n\t}\nprivate:\n\tclass ibuf final : public std::streambuf {\n\tpublic:\n\t\tibuf() : gzf(nullptr) {}\n\t\tbool open(const std::string& filename);\n\t\tvirtual ~ibuf();\n\n\tprotected:\n\t\t// Called when the buffer is empty and more input is needed\n\t\tvirtual int_type underflow() override;\n\tprivate:\n\t\tstatic const int buffer_size = 8192;\n\t\tchar buffer[buffer_size];\n\t\tZlib::gzFile gzf;\n\t};\n\n\tibuf inbuf;  // The stream buffer instance\n};\n\n#endif // YOSYS_ENABLE_ZLIB\n\nstd::istream* uncompressed(const std::string filename, std::ios_base::openmode mode = std::ios_base::in);\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_GZIP_H\n",
-                "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <array>\n#include <stdexcept>\n#include <algorithm>\n#include <optional>\n#include <string>\n#include <variant>\n#include <vector>\n#include <type_traits>\n#include <stdint.h>\n\n#define YS_HASHING_VERSION 1\n\nnamespace hashlib {\n\n/**\n * HASHING\n *\n * Also refer to docs/source/yosys_internals/hashing.rst\n *\n * The Hasher knows how to hash 32 and 64-bit integers. That's it.\n * In the future, it could be expanded to do vectors with SIMD.\n *\n * The Hasher doesn't know how to hash common standard containers\n * and compositions. However, hashlib provides centralized wrappers.\n *\n * Hashlib doesn't know how to hash silly Yosys-specific types.\n * Hashlib doesn't depend on Yosys and can be used standalone.\n * Please don't use hashlib standalone for new projects.\n * Never directly include kernel/hashlib.h in Yosys code.\n * Instead include kernel/yosys_common.h\n *\n * The hash_ops type is now always left to its default value, derived\n * from templated functions through SFINAE. Providing custom ops is\n * still supported.\n *\n * HASH TABLES\n *\n * We implement associative data structures with separate chaining.\n * Linked lists use integers into the indirection hashtable array\n * instead of pointers.\n */\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\nnamespace legacy {\n\tinline uint32_t djb2_add(uint32_t a, uint32_t b) {\n\t\treturn ((a << 5) + a) + b;\n\t}\n};\n\ntemplate<typename T>\nstruct hash_ops;\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\nclass HasherDJB32 {\npublic:\n\tusing hash_t = uint32_t;\n\n\tHasherDJB32() {\n\t\t// traditionally 5381 is used as starting value for the djb2 hash\n\t\tstate = 5381;\n\t}\n\tstatic void set_fudge(hash_t f) {\n\t\tfudge = f;\n\t}\n\nprivate:\n\tuint32_t state;\n\tstatic uint32_t fudge;\n\t// The XOR version of DJB2\n\t[[nodiscard]]\n\tstatic uint32_t djb2_xor(uint32_t a, uint32_t b) {\n\t\tuint32_t hash = ((a << 5) + a) ^ b;\n\t\treturn hash;\n\t}\npublic:\n\tvoid hash32(uint32_t i) {\n\t\tstate = djb2_xor(i, state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\tvoid hash64(uint64_t i) {\n\t\tstate = djb2_xor((uint32_t)(i & 0xFFFFFFFFULL), state);\n\t\tstate = djb2_xor((uint32_t)(i >> 32ULL), state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\t[[nodiscard]]\n\thash_t yield() const {\n\t\treturn (hash_t)state;\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(T&& t) {\n\t\t*this = hash_ops<std::remove_cv_t<std::remove_reference_t<T>>>::hash_into(std::forward<T>(t), *this);\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(const T& t) {\n\t\t*this = hash_ops<T>::hash_into(t, *this);\n\t}\n\n\t[[deprecated]]\n\tvoid commutative_eat(hash_t t) {\n\t\tstate ^= t;\n\t}\n\n\tvoid force(hash_t new_state) {\n\t\tstate = new_state;\n\t}\n};\n\nusing Hasher = HasherDJB32;\n\n// Boilerplate compressor for trivially implementing\n// top-level hash method with hash_into\n#define HASH_TOP_LOOP_FST [[nodiscard]] static inline Hasher hash\n#define HASH_TOP_LOOP_SND { \\\n\tHasher h; \\\n\th = hash_into(a, h); \\\n\treturn h; \\\n}\n\ntemplate<typename T>\nstruct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const T &a, Hasher h) {\n\t\tif constexpr (std::is_integral_v<T>) {\n\t\t\tstatic_assert(sizeof(T) <= sizeof(uint64_t));\n\t\t\tif (sizeof(T) == sizeof(uint64_t))\n\t\t\t\th.hash64(a);\n\t\t\telse\n\t\t\t\th.hash32(a);\n\t\t\treturn h;\n\t\t} else if constexpr (std::is_enum_v<T>) {\n\t\t\tusing u_type = std::underlying_type_t<T>;\n\t\t\treturn hash_ops<u_type>::hash_into((u_type) a, h);\n\t\t} else if constexpr (std::is_pointer_v<T>) {\n\t\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t) a, h);\n\t\t} else if constexpr (std::is_same_v<T, std::string>) {\n\t\t\tint size = a.size();\n\t\t\tint i = 0;\n\t\t\twhile (i + 8 < size) {\n\t\t\t\tuint64_t v;\n\t\t\t\tmemcpy(&v, a.data() + i, 8);\n\t\t\t\th.hash64(v);\n\t\t\t\ti += 8;\n\t\t\t}\n\t\t\tuint64_t v = 0;\n\t\t\tmemcpy(&v, a.data() + i, size - i);\n\t\t\th.hash64(v);\n\t\t\treturn h;\n\t\t} else {\n\t\t\treturn a.hash_into(h);\n\t\t}\n\t}\n\tHASH_TOP_LOOP_FST (const T &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(const std::pair<P, Q> &a, const std::pair<P, Q> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::pair<P, Q> &a, Hasher h) {\n\t\th = hash_ops<P>::hash_into(a.first, h);\n\t\th = hash_ops<Q>::hash_into(a.second, h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const std::pair<P, Q> &a) HASH_TOP_LOOP_SND\n\t[[nodiscard]] static inline Hasher hash(const P &p, const Q &q) {\n\t\tHasher h;\n\t\th = hash_ops<P>::hash_into(p, h);\n\t\th = hash_ops<Q>::hash_into(q, h);\n\t\treturn h;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(const std::tuple<T...> &a, const std::tuple<T...> &b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), Hasher>::type hash_into(const std::tuple<T...> &, Hasher h) {\n\t\treturn h;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), Hasher>::type hash_into(const std::tuple<T...> &a, Hasher h) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\th = hash_into<I+1>(a, h);\n\t\th = element_ops_t::hash_into(std::get<I>(a), h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const std::tuple<T...> &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(const std::vector<T> &a, const std::vector<T> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::vector<T> &a, Hasher h) {\n\t\th.eat((uint32_t)a.size());\n\t\tfor (auto k : a)\n\t\t\th.eat(k);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const std::vector<T> &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T, size_t N> struct hash_ops<std::array<T, N>> {\n    static inline bool cmp(const std::array<T, N> &a, const std::array<T, N> &b) {\n        return a == b;\n    }\n    [[nodiscard]] static inline Hasher hash_into(const std::array<T, N> &a, Hasher h) {\n        for (const auto& k : a)\n            h = hash_ops<T>::hash_into(k, h);\n        return h;\n    }\n\tHASH_TOP_LOOP_FST (const std::array<T, N> &a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\treturn strcmp(a, b) == 0;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const char *a, Hasher h) {\n\t\twhile (*a)\n\t\t\th.hash32(*(a++));\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const char *a) HASH_TOP_LOOP_SND\n};\n\ntemplate <> struct hash_ops<char*> : hash_cstr_ops {};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const void *a, Hasher h) {\n\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t)a, h);\n\t}\n\tHASH_TOP_LOOP_FST (const void *a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\t[[nodiscard]] static inline Hasher hash_into(const T *a, Hasher h) {\n\t\tif (a)\n\t\t\th = a->hash_into(h);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n\ttemplate<typename T>\n\tHASH_TOP_LOOP_FST (const T *a) HASH_TOP_LOOP_SND\n};\n/**\n * If you find yourself using this function, think hard\n * about if it's the right thing to do. Mixing finalized\n * hashes together with XORs or worse can destroy\n * desirable qualities of the hash function\n */\ntemplate<typename T>\n[[nodiscard]]\nHasher::hash_t run_hash(const T& obj) {\n\treturn hash_ops<T>::hash(obj).yield();\n}\n\n/** Refer to docs/source/yosys_internals/hashing.rst */\ntemplate<typename T>\n[[nodiscard]]\n[[deprecated]]\ninline unsigned int mkhash(const T &v) {\n\treturn (unsigned int) run_hash<T>(v);\n}\n\ntemplate<> struct hash_ops<std::monostate> {\n\tstatic inline bool cmp(std::monostate a, std::monostate b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::monostate, Hasher h) {\n\t\treturn h;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::variant<T...>> {\n\tstatic inline bool cmp(const std::variant<T...> &a, const std::variant<T...> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::variant<T...> &a, Hasher h) {\n\t\tstd::visit([& h](const auto &v) { h.eat(v); }, a);\n\t\th.eat(a.index());\n\t\treturn h;\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::optional<T>> {\n\tstatic inline bool cmp(const std::optional<T> &a, const std::optional<T> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::optional<T> &a, Hasher h) {\n\t\tif(a.has_value())\n\t\t\th.eat(*a);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n};\n\ninline unsigned int hashtable_size(unsigned int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<unsigned int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713, 2211715897, 2764644887, 3455806139\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(unsigned int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\n// Computes the hash value of an unordered set of elements.\n// See https://www.preprints.org/manuscript/201710.0192/v1/download.\n// This is the Sum(4) algorithm from that paper, which has good collision resistance,\n// much better than Sum(1) or Xor(1) (and somewhat better than Xor(4)).\nclass commutative_hash {\npublic:\n\tcommutative_hash() {\n\t\tbuckets.fill(0);\n\t}\n\ttemplate <typename T>\n\tvoid eat(const T &obj) {\n\t\teat(hash_ops<T>::hash(obj));\n\t}\n\tvoid eat(const Hasher &h) {\n\t\tHasher::hash_t v = h.yield();\n\t\tsize_t index = v & (buckets.size() - 1);\n\t\tbuckets[index] += v;\n\t}\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto b : buckets)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\nprivate:\n\tstd::array<Hasher::hash_t, 4> buckets;\n};\n\ntemplate<typename K, typename T, typename OPS>\nclass dict {\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_lookup_internal(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_insert(const K &key, const Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, const Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, const Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::bidirectional_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef const std::pair<K, T>* pointer;\n\t\ttypedef const std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator++(int) { const_iterator tmp = *this; index--; return tmp; }\n\t\tconst_iterator operator--() { index++; return *this; }\n\t\tconst_iterator operator--(int) { const_iterator tmp = *this; index++; return tmp; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\tusing reverse_iterator = std::reverse_iterator<const_iterator>;\n\treverse_iterator rbegin() const {\n\t\treturn std::make_reverse_iterator(end());\n\t}\n\treverse_iterator rend() const {\n\t\treturn std::make_reverse_iterator(begin());\n\t}\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tcommutative_hash comm;\n\t\tfor (auto &it : entries) {\n\t\t\tHasher entry_hash;\n\t\t\tentry_hash.eat(it.udata.first);\n\t\t\tentry_hash.eat(it.udata.second);\n\t\t\tcomm.eat(entry_hash);\n\t\t}\n\t\treturn comm.hash_into(h);\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(this, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_lookup_internal(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_insert(const K &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tcommutative_hash comm;\n\t\tfor (auto &it : entries) {\n\t\t\tcomm.eat(ops.hash(it.udata));\n\t\t}\n\t\treturn comm.hash_into(h);\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets.\n\t// Makes ifind(j) the root of the merged set.\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
-                "io.h": "#include <string>\n#include <stdarg.h>\n#include <type_traits>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_IO_H\n#define YOSYS_IO_H\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL {\n\tstruct IdString;\n}\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n\t// For the common case of strings shorter than 128, save a heap\n\t// allocation by using a stack allocated buffer.\n\tconst int kBufSize = 128;\n\tchar buf[kBufSize];\n\tbuf[0] = '\\0';\n\tva_list apc;\n\tva_copy(apc, ap);\n\tint n = vsnprintf(buf, kBufSize, fmt, apc);\n\tva_end(apc);\n\tif (n < kBufSize)\n\t\treturn std::string(buf);\n\n\tstd::string string;\n\tchar *str = NULL;\n#if defined(_WIN32) || defined(__CYGWIN__)\n\tint sz = 2 * kBufSize, rc;\n\twhile (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char *)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n\tif (vasprintf(&str, fmt, ap) < 0)\n\t\tstr = NULL;\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#endif\n}\n\nenum ConversionSpecifier : uint8_t\n{\n\tCONVSPEC_NONE,\n\t// Specifier not understood/supported\n\tCONVSPEC_ERROR,\n\t// Consumes a \"long long\"\n\tCONVSPEC_SIGNED_INT,\n\t// Consumes a \"unsigned long long\"\n\tCONVSPEC_UNSIGNED_INT,\n\t// Consumes a \"double\"\n\tCONVSPEC_DOUBLE,\n\t// Consumes a \"const char*\" or other string type\n\tCONVSPEC_CHAR_PTR,\n\t// Consumes a \"void*\"\n\tCONVSPEC_VOID_PTR,\n};\n\nconstexpr ConversionSpecifier parse_conversion_specifier(char ch, char prev_ch)\n{\n\tswitch (ch) {\n\tcase 'd':\n\tcase 'i':\n\t\treturn CONVSPEC_SIGNED_INT;\n\tcase 'o':\n\tcase 'u':\n\tcase 'x':\n\tcase 'X':\n\tcase 'm':\n\t\treturn CONVSPEC_UNSIGNED_INT;\n\tcase 'c':\n\t\tif (prev_ch == 'l' || prev_ch == 'q' || prev_ch == 'L') {\n\t\t\t// wchar not supported\n\t\t\treturn CONVSPEC_ERROR;\n\t\t}\n\t\treturn CONVSPEC_UNSIGNED_INT;\n\tcase 'e':\n\tcase 'E':\n\tcase 'f':\n\tcase 'F':\n\tcase 'g':\n\tcase 'G':\n\tcase 'a':\n\tcase 'A':\n\t\treturn CONVSPEC_DOUBLE;\n\tcase 's':\n\t\tif (prev_ch == 'l' || prev_ch == 'q' || prev_ch == 'L') {\n\t\t\t// wchar not supported\n\t\t\treturn CONVSPEC_ERROR;\n\t\t}\n\t\treturn CONVSPEC_CHAR_PTR;\n\tcase 'p':\n\t\treturn CONVSPEC_VOID_PTR;\n\tcase '$': // positional parameters\n\tcase 'n':\n\tcase 'S':\n\t\treturn CONVSPEC_ERROR;\n\tdefault:\n\t\treturn CONVSPEC_NONE;\n\t}\n}\n\nenum class DynamicIntCount : uint8_t {\n\tNONE = 0,\n\tONE = 1,\n\tTWO = 2,\n};\n\n// Describes a printf-style format conversion specifier found in a format string.\nstruct FoundFormatSpec\n{\n\t// The start offset of the conversion spec in the format string.\n\tint start;\n\t// The end offset of the conversion spec in the format string.\n\tint end;\n\tConversionSpecifier spec;\n\t// Number of int args consumed by '*' dynamic width/precision args.\n\tDynamicIntCount num_dynamic_ints;\n};\n\n// Ensure there is no format spec.\nconstexpr void ensure_no_format_spec(std::string_view fmt, int index, bool *has_escapes)\n{\n\tint fmt_size = static_cast<int>(fmt.size());\n\t// A trailing '%' is not a format spec.\n\twhile (index + 1 < fmt_size) {\n\t\tif (fmt[index] != '%') {\n\t\t\t++index;\n\t\t\tcontinue;\n\t\t}\n\t\tif (fmt[index + 1] != '%') {\n\t\t\tYOSYS_ABORT(\"More format conversion specifiers than arguments\");\n\t\t}\n\t\t*has_escapes = true;\n\t\tindex += 2;\n\t}\n}\n\n// Returns the next format conversion specifier (starting with '%').\n// Returns CONVSPEC_NONE if there isn't a format conversion specifier.\nconstexpr FoundFormatSpec find_next_format_spec(std::string_view fmt, int fmt_start, bool *has_escapes)\n{\n\tint index = fmt_start;\n\tint fmt_size = static_cast<int>(fmt.size());\n\twhile (index < fmt_size) {\n\t\tif (fmt[index] != '%') {\n\t\t\t++index;\n\t\t\tcontinue;\n\t\t}\n\t\tint p = index + 1;\n\t\tuint8_t num_dynamic_ints = 0;\n\t\twhile (true) {\n\t\t\tif (p == fmt_size) {\n\t\t\t\treturn {0, 0, CONVSPEC_NONE, DynamicIntCount::NONE};\n\t\t\t}\n\t\t\tif (fmt[p] == '%') {\n\t\t\t\t*has_escapes = true;\n\t\t\t\tindex = p + 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (fmt[p] == '*') {\n\t\t\t\tif (num_dynamic_ints >= 2) {\n\t\t\t\t\treturn {0, 0, CONVSPEC_ERROR, DynamicIntCount::NONE};\n\t\t\t\t}\n\t\t\t\t++num_dynamic_ints;\n\t\t\t}\n\t\t\tConversionSpecifier spec = parse_conversion_specifier(fmt[p], fmt[p - 1]);\n\t\t\tif (spec != CONVSPEC_NONE) {\n\t\t\t\treturn {index, p + 1, spec, static_cast<DynamicIntCount>(num_dynamic_ints)};\n\t\t\t}\n\t\t\t++p;\n\t\t}\n\t}\n\treturn {0, 0, CONVSPEC_NONE, DynamicIntCount::NONE};\n}\n\ntemplate <typename... Args>\nconstexpr typename std::enable_if<sizeof...(Args) == 0>::type\ncheck_format(std::string_view fmt, int fmt_start, bool *has_escapes, FoundFormatSpec*, DynamicIntCount)\n{\n\tensure_no_format_spec(fmt, fmt_start, has_escapes);\n}\n\n// Check that the format string `fmt.substr(fmt_start)` is valid for the given type arguments.\n// Fills `specs` with the FoundFormatSpecs found in the format string.\n// `int_args_consumed` is the number of int arguments already consumed to satisfy the\n// dynamic width/precision args for the next format conversion specifier.\ntemplate <typename Arg, typename... Args>\nconstexpr void check_format(std::string_view fmt, int fmt_start, bool *has_escapes, FoundFormatSpec* specs,\n        DynamicIntCount int_args_consumed)\n{\n\tFoundFormatSpec found = find_next_format_spec(fmt, fmt_start, has_escapes);\n\tif (found.num_dynamic_ints > int_args_consumed) {\n\t\t// We need to consume at least one more int for the dynamic\n\t\t// width/precision of this format conversion specifier.\n\t\tif constexpr (!std::is_convertible_v<Arg, int>) {\n\t\t\tYOSYS_ABORT(\"Expected dynamic int argument\");\n\t\t}\n\t\tcheck_format<Args...>(fmt, fmt_start, has_escapes, specs,\n\t\t\tstatic_cast<DynamicIntCount>(static_cast<uint8_t>(int_args_consumed) + 1));\n\t\treturn;\n\t}\n\tswitch (found.spec) {\n\tcase CONVSPEC_NONE:\n\t\tYOSYS_ABORT(\"Expected format conversion specifier for argument\");\n\t\tbreak;\n\tcase CONVSPEC_ERROR:\n\t\tYOSYS_ABORT(\"Found unsupported format conversion specifier\");\n\t\tbreak;\n\tcase CONVSPEC_SIGNED_INT:\n\t\tif constexpr (!std::is_convertible_v<Arg, long long>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to signed integer\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_UNSIGNED_INT:\n\t\tif constexpr (!std::is_convertible_v<Arg, unsigned long long>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to unsigned integer\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_DOUBLE:\n\t\tif constexpr (!std::is_convertible_v<Arg, double>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to double\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_CHAR_PTR:\n\t\tif constexpr (!std::is_convertible_v<Arg, const char *> &&\n\t\t        !std::is_convertible_v<Arg, const std::string &> &&\n\t\t\t!std::is_convertible_v<Arg, const std::string_view &> &&\n\t\t\t!std::is_convertible_v<Arg, const RTLIL::IdString &>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to char *\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_VOID_PTR:\n\t\tif constexpr (!std::is_convertible_v<Arg, const void *>) {\n\t\t\tYOSYS_ABORT(\"Expected pointer type\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\t}\n\tcheck_format<Args...>(fmt, found.end, has_escapes, specs + 1, DynamicIntCount::NONE);\n}\n\n// Emit the string representation of `arg` that has been converted to a `long long'.\nvoid format_emit_long_long(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, long long arg);\n\n// Emit the string representation of `arg` that has been converted to a `unsigned long long'.\nvoid format_emit_unsigned_long_long(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, unsigned long long arg);\n\n// Emit the string representation of `arg` that has been converted to a `double'.\nvoid format_emit_double(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, double arg);\n\n// Emit the string representation of `arg` that has been converted to a `const char*'.\nvoid format_emit_char_ptr(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const char *arg);\n\n// Emit the string representation of `arg` that has been converted to a `std::string'.\nvoid format_emit_string(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const std::string &arg);\n\n// Emit the string representation of `arg` that has been converted to a `std::string_view'.\nvoid format_emit_string_view(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, std::string_view arg);\n\n// Emit the string representation of `arg` that has been converted to a `RTLIL::IdString'.\nvoid format_emit_idstring(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const RTLIL::IdString &arg);\n\n// Emit the string representation of `arg` that has been converted to a `double'.\nvoid format_emit_void_ptr(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const void *arg);\n\n// Emit the string representation of `arg` according to the given `FoundFormatSpec`,\n// appending it to `result`.\ntemplate <typename Arg>\ninline void format_emit_one(std::string &result, std::string_view fmt, const FoundFormatSpec &ffspec,\n\tint *dynamic_ints, const Arg& arg)\n{\n\tstd::string_view spec = fmt.substr(ffspec.start, ffspec.end - ffspec.start);\n\tDynamicIntCount num_dynamic_ints = ffspec.num_dynamic_ints;\n\tswitch (ffspec.spec) {\n\tcase CONVSPEC_SIGNED_INT:\n\t\tif constexpr (std::is_convertible_v<Arg, long long>) {\n\t\t\tlong long s = arg;\n\t\t\tformat_emit_long_long(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_UNSIGNED_INT:\n\t\tif constexpr (std::is_convertible_v<Arg, unsigned long long>) {\n\t\t\tunsigned long long s = arg;\n\t\t\tformat_emit_unsigned_long_long(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_DOUBLE:\n\t\tif constexpr (std::is_convertible_v<Arg, double>) {\n\t\t\tdouble s = arg;\n\t\t\tformat_emit_double(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_CHAR_PTR:\n\t\tif constexpr (std::is_convertible_v<Arg, const char *>) {\n\t\t\tconst char *s = arg;\n\t\t\tformat_emit_char_ptr(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tif constexpr (std::is_convertible_v<Arg, const std::string &>) {\n\t\t\tconst std::string &s = arg;\n\t\t\tformat_emit_string(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tif constexpr (std::is_convertible_v<Arg, const std::string_view &>) {\n\t\t\tconst std::string_view &s = arg;\n\t\t\tformat_emit_string_view(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tif constexpr (std::is_convertible_v<Arg, const RTLIL::IdString &>) {\n\t\t\tconst RTLIL::IdString &s = arg;\n\t\t\tformat_emit_idstring(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_VOID_PTR:\n\t\tif constexpr (std::is_convertible_v<Arg, const void *>) {\n\t\t\tconst void *s = arg;\n\t\t\tformat_emit_void_ptr(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tYOSYS_ABORT(\"Internal error\");\n}\n\n// Append the format string `fmt` to `result`, assuming there are no format conversion\n// specifiers other than \"%%\" and therefore no arguments. Unescape \"%%\".\nvoid format_emit_unescaped(std::string &result, std::string_view fmt);\nstd::string unescape_format_string(std::string_view fmt);\n\ninline void format_emit(std::string &result, std::string_view fmt, int fmt_start,\n\tbool has_escapes, const FoundFormatSpec*, int*, DynamicIntCount)\n{\n\tfmt = fmt.substr(fmt_start);\n\tif (has_escapes) {\n\t\tformat_emit_unescaped(result, fmt);\n\t} else {\n\t\tresult += fmt;\n\t}\n}\n// Format `args` according to `fmt` (starting at `fmt_start`) and `specs` and append to `result`.\n// `num_dynamic_ints` in `dynamic_ints[]` have already been collected to provide as\n// dynamic width/precision args for the next format conversion specifier.\ntemplate <typename Arg, typename... Args>\ninline void format_emit(std::string &result, std::string_view fmt, int fmt_start, bool has_escapes,\n\tconst FoundFormatSpec* specs, int *dynamic_ints, DynamicIntCount num_dynamic_ints,\n\tconst Arg &arg, const Args &... args)\n{\n\tif (specs->num_dynamic_ints > num_dynamic_ints) {\n\t\t// Collect another int for the dynamic width precision/args\n\t\t// for the next format conversion specifier.\n\t\tif constexpr (std::is_convertible_v<Arg, int>) {\n\t\t\tdynamic_ints[static_cast<uint8_t>(num_dynamic_ints)] = arg;\n\t\t} else {\n\t\t\tYOSYS_ABORT(\"Internal error\");\n\t\t}\n\t\tformat_emit(result, fmt, fmt_start, has_escapes, specs, dynamic_ints,\n\t\t            static_cast<DynamicIntCount>(static_cast<uint8_t>(num_dynamic_ints) + 1), args...);\n\t\treturn;\n\t}\n\tstd::string_view str = fmt.substr(fmt_start, specs->start - fmt_start);\n\tif (has_escapes) {\n\t\tformat_emit_unescaped(result, str);\n\t} else {\n\t\tresult += str;\n\t}\n\tformat_emit_one(result, fmt, *specs, dynamic_ints, arg);\n\tformat_emit(result, fmt, specs->end, has_escapes, specs + 1, dynamic_ints, DynamicIntCount::NONE, args...);\n}\n\ntemplate <typename... Args>\ninline std::string format_emit_toplevel(std::string_view fmt, bool has_escapes, const FoundFormatSpec* specs, const Args &... args)\n{\n\tstd::string result;\n\tint dynamic_ints[2] = { 0, 0 };\n\tformat_emit(result, fmt, 0, has_escapes, specs, dynamic_ints, DynamicIntCount::NONE, args...);\n\treturn result;\n}\ntemplate <>\ninline std::string format_emit_toplevel(std::string_view fmt, bool has_escapes, const FoundFormatSpec*)\n{\n\tif (!has_escapes) {\n\t\treturn std::string(fmt);\n\t}\n\treturn unescape_format_string(fmt);\n}\n\n// This class parses format strings to build a list of `FoundFormatSpecs` in `specs`.\n// When the compiler supports `consteval` (C++20), this parsing happens at compile time and\n// type errors will be reported at compile time. Otherwise the parsing happens at\n// runtime and type errors will trigger an `abort()` at runtime.\ntemplate <typename... Args>\nclass FmtString\n{\npublic:\n\t// Implicit conversion from const char * means that users can pass\n\t// C string constants which are automatically parsed.\n\tYOSYS_CONSTEVAL FmtString(const char *p) : fmt(p)\n\t{\n\t\tcheck_format<Args...>(fmt, 0, &has_escapes, specs, DynamicIntCount::NONE);\n\t}\n\tstd::string format(const Args &... args)\n\t{\n\t\treturn format_emit_toplevel(fmt, has_escapes, specs, args...);\n\t}\n\tstd::string_view format_string() const { return fmt; }\nprivate:\n\tstd::string_view fmt;\n\tbool has_escapes = false;\n\tFoundFormatSpec specs[sizeof...(Args)] = {};\n};\n\ntemplate <typename T> struct WrapType { using type = T; };\ntemplate <typename T> using TypeIdentity = typename WrapType<T>::type;\n\ntemplate <typename... Args>\ninline std::string stringf(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\treturn fmt.format(args...);\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(const std::string& filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname, bool is_exec = false);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_IO_H\n",
+                "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <array>\n#include <atomic>\n#include <stdexcept>\n#include <algorithm>\n#include <optional>\n#include <string>\n#include <variant>\n#include <vector>\n#include <type_traits>\n#include <stdint.h>\n\n#define YS_HASHING_VERSION 1\n\nnamespace hashlib {\n\n/**\n * HASHING\n *\n * Also refer to docs/source/yosys_internals/hashing.rst\n *\n * The Hasher knows how to hash 32 and 64-bit integers. That's it.\n * In the future, it could be expanded to do vectors with SIMD.\n *\n * The Hasher doesn't know how to hash common standard containers\n * and compositions. However, hashlib provides centralized wrappers.\n *\n * Hashlib doesn't know how to hash silly Yosys-specific types.\n * Hashlib doesn't depend on Yosys and can be used standalone.\n * Please don't use hashlib standalone for new projects.\n * Never directly include kernel/hashlib.h in Yosys code.\n * Instead include kernel/yosys_common.h\n *\n * The hash_ops type is now always left to its default value, derived\n * from templated functions through SFINAE. Providing custom ops is\n * still supported.\n *\n * HASH TABLES\n *\n * We implement associative data structures with separate chaining.\n * Linked lists use integers into the indirection hashtable array\n * instead of pointers.\n */\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\nnamespace legacy {\n\tinline uint32_t djb2_add(uint32_t a, uint32_t b) {\n\t\treturn ((a << 5) + a) + b;\n\t}\n};\n\ntemplate<typename T>\nstruct hash_ops;\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\nclass HasherDJB32 {\npublic:\n\tusing hash_t = uint32_t;\n\n\tHasherDJB32() {\n\t\t// traditionally 5381 is used as starting value for the djb2 hash\n\t\tstate = 5381;\n\t}\n\tstatic void set_fudge(hash_t f) {\n\t\tfudge = f;\n\t}\n\nprivate:\n\tuint32_t state;\n\tstatic uint32_t fudge;\n\t// The XOR version of DJB2\n\t[[nodiscard]]\n\tstatic uint32_t djb2_xor(uint32_t a, uint32_t b) {\n\t\tuint32_t hash = ((a << 5) + a) ^ b;\n\t\treturn hash;\n\t}\npublic:\n\tvoid hash32(uint32_t i) {\n\t\tstate = djb2_xor(i, state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\tvoid hash64(uint64_t i) {\n\t\tstate = djb2_xor((uint32_t)(i & 0xFFFFFFFFULL), state);\n\t\tstate = djb2_xor((uint32_t)(i >> 32ULL), state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\t[[nodiscard]]\n\thash_t yield() const {\n\t\treturn (hash_t)state;\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(T&& t) {\n\t\t*this = hash_ops<std::remove_cv_t<std::remove_reference_t<T>>>::hash_into(std::forward<T>(t), *this);\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(const T& t) {\n\t\t*this = hash_ops<T>::hash_into(t, *this);\n\t}\n\n\t[[deprecated]]\n\tvoid commutative_eat(hash_t t) {\n\t\tstate ^= t;\n\t}\n\n\tvoid force(hash_t new_state) {\n\t\tstate = new_state;\n\t}\n};\n\nusing Hasher = HasherDJB32;\n\n// Boilerplate compressor for trivially implementing\n// top-level hash method with hash_into\n#define HASH_TOP_LOOP_FST [[nodiscard]] static inline Hasher hash\n#define HASH_TOP_LOOP_SND { \\\n\tHasher h; \\\n\th = hash_into(a, h); \\\n\treturn h; \\\n}\n\ntemplate<typename T>\nstruct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const T &a, Hasher h) {\n\t\tif constexpr (std::is_integral_v<T>) {\n\t\t\tstatic_assert(sizeof(T) <= sizeof(uint64_t));\n\t\t\tif (sizeof(T) == sizeof(uint64_t))\n\t\t\t\th.hash64(a);\n\t\t\telse\n\t\t\t\th.hash32(a);\n\t\t\treturn h;\n\t\t} else if constexpr (std::is_enum_v<T>) {\n\t\t\tusing u_type = std::underlying_type_t<T>;\n\t\t\treturn hash_ops<u_type>::hash_into((u_type) a, h);\n\t\t} else if constexpr (std::is_pointer_v<T>) {\n\t\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t) a, h);\n\t\t} else if constexpr (std::is_same_v<T, std::string>) {\n\t\t\tint size = a.size();\n\t\t\tint i = 0;\n\t\t\twhile (i + 8 < size) {\n\t\t\t\tuint64_t v;\n\t\t\t\tmemcpy(&v, a.data() + i, 8);\n\t\t\t\th.hash64(v);\n\t\t\t\ti += 8;\n\t\t\t}\n\t\t\tuint64_t v = 0;\n\t\t\tmemcpy(&v, a.data() + i, size - i);\n\t\t\th.hash64(v);\n\t\t\treturn h;\n\t\t} else {\n\t\t\treturn a.hash_into(h);\n\t\t}\n\t}\n\tHASH_TOP_LOOP_FST (const T &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(const std::pair<P, Q> &a, const std::pair<P, Q> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::pair<P, Q> &a, Hasher h) {\n\t\th = hash_ops<P>::hash_into(a.first, h);\n\t\th = hash_ops<Q>::hash_into(a.second, h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const std::pair<P, Q> &a) HASH_TOP_LOOP_SND\n\t[[nodiscard]] static inline Hasher hash(const P &p, const Q &q) {\n\t\tHasher h;\n\t\th = hash_ops<P>::hash_into(p, h);\n\t\th = hash_ops<Q>::hash_into(q, h);\n\t\treturn h;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(const std::tuple<T...> &a, const std::tuple<T...> &b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), Hasher>::type hash_into(const std::tuple<T...> &, Hasher h) {\n\t\treturn h;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), Hasher>::type hash_into(const std::tuple<T...> &a, Hasher h) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\th = hash_into<I+1>(a, h);\n\t\th = element_ops_t::hash_into(std::get<I>(a), h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const std::tuple<T...> &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(const std::vector<T> &a, const std::vector<T> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::vector<T> &a, Hasher h) {\n\t\th.eat((uint32_t)a.size());\n\t\tfor (auto k : a)\n\t\t\th.eat(k);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const std::vector<T> &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T, size_t N> struct hash_ops<std::array<T, N>> {\n    static inline bool cmp(const std::array<T, N> &a, const std::array<T, N> &b) {\n        return a == b;\n    }\n    [[nodiscard]] static inline Hasher hash_into(const std::array<T, N> &a, Hasher h) {\n        for (const auto& k : a)\n            h = hash_ops<T>::hash_into(k, h);\n        return h;\n    }\n\tHASH_TOP_LOOP_FST (const std::array<T, N> &a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\treturn strcmp(a, b) == 0;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const char *a, Hasher h) {\n\t\twhile (*a)\n\t\t\th.hash32(*(a++));\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const char *a) HASH_TOP_LOOP_SND\n};\n\ntemplate <> struct hash_ops<char*> : hash_cstr_ops {};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const void *a, Hasher h) {\n\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t)a, h);\n\t}\n\tHASH_TOP_LOOP_FST (const void *a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\t[[nodiscard]] static inline Hasher hash_into(const T *a, Hasher h) {\n\t\tif (a)\n\t\t\th = a->hash_into(h);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n\ttemplate<typename T>\n\tHASH_TOP_LOOP_FST (const T *a) HASH_TOP_LOOP_SND\n};\n/**\n * If you find yourself using this function, think hard\n * about if it's the right thing to do. Mixing finalized\n * hashes together with XORs or worse can destroy\n * desirable qualities of the hash function\n */\ntemplate<typename T>\n[[nodiscard]]\nHasher::hash_t run_hash(const T& obj) {\n\treturn hash_ops<T>::hash(obj).yield();\n}\n\n/** Refer to docs/source/yosys_internals/hashing.rst */\ntemplate<typename T>\n[[nodiscard]]\n[[deprecated]]\ninline unsigned int mkhash(const T &v) {\n\treturn (unsigned int) run_hash<T>(v);\n}\n\ntemplate<> struct hash_ops<std::monostate> {\n\tstatic inline bool cmp(std::monostate a, std::monostate b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::monostate, Hasher h) {\n\t\treturn h;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::variant<T...>> {\n\tstatic inline bool cmp(const std::variant<T...> &a, const std::variant<T...> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::variant<T...> &a, Hasher h) {\n\t\tstd::visit([& h](const auto &v) { h.eat(v); }, a);\n\t\th.eat(a.index());\n\t\treturn h;\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::optional<T>> {\n\tstatic inline bool cmp(const std::optional<T> &a, const std::optional<T> &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const std::optional<T> &a, Hasher h) {\n\t\tif(a.has_value())\n\t\t\th.eat(*a);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n};\n\ninline unsigned int hashtable_size(unsigned int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<unsigned int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713, 2211715897, 2764644887, 3455806139\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(unsigned int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\n// Computes the hash value of an unordered set of elements.\n// See https://www.preprints.org/manuscript/201710.0192/v1/download.\n// This is the Sum(4) algorithm from that paper, which has good collision resistance,\n// much better than Sum(1) or Xor(1) (and somewhat better than Xor(4)).\nclass commutative_hash {\npublic:\n\tcommutative_hash() {\n\t\tbuckets.fill(0);\n\t}\n\ttemplate <typename T>\n\tvoid eat(const T &obj) {\n\t\teat(hash_ops<T>::hash(obj));\n\t}\n\tvoid eat(const Hasher &h) {\n\t\tHasher::hash_t v = h.yield();\n\t\tsize_t index = v & (buckets.size() - 1);\n\t\tbuckets[index] += v;\n\t}\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto b : buckets)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\nprivate:\n\tstd::array<Hasher::hash_t, 4> buckets;\n};\n\ntemplate<typename K, typename T, typename OPS>\nclass dict {\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_lookup_internal(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_insert(const K &key, const Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, const Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, const Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::bidirectional_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef const std::pair<K, T>* pointer;\n\t\ttypedef const std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator++(int) { const_iterator tmp = *this; index--; return tmp; }\n\t\tconst_iterator operator--() { index++; return *this; }\n\t\tconst_iterator operator--(int) { const_iterator tmp = *this; index++; return tmp; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\tusing reverse_iterator = std::reverse_iterator<const_iterator>;\n\treverse_iterator rbegin() const {\n\t\treturn std::make_reverse_iterator(end());\n\t}\n\treverse_iterator rend() const {\n\t\treturn std::make_reverse_iterator(begin());\n\t}\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tcommutative_hash comm;\n\t\tfor (auto &it : entries) {\n\t\t\tHasher entry_hash;\n\t\t\tentry_hash.eat(it.udata.first);\n\t\t\tentry_hash.eat(it.udata.second);\n\t\t\tcomm.eat(entry_hash);\n\t\t}\n\t\treturn comm.hash_into(h);\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(this, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_lookup_internal(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\treturn do_lookup_internal(key, hash);\n\t}\n\n\tint do_insert(const K &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tcommutative_hash comm;\n\t\tfor (auto &it : entries) {\n\t\t\tcomm.eat(ops.hash(it.udata));\n\t\t}\n\t\treturn comm.hash_into(h);\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup_no_rehash(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup_no_rehash(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tidict<K, 0, OPS> database;\n\tclass AtomicParent {\n\tpublic:\n\t\texplicit AtomicParent(int p) : parent(p) {}\n\t\tAtomicParent(const AtomicParent &other) : parent(other.get()) {}\n\t\tAtomicParent &operator=(const AtomicParent &other) { set(other.get()); return *this; }\n\t\tint get() const { return parent.load(std::memory_order_relaxed); }\n\t\tvoid set(int p) { parent.store(p, std::memory_order_relaxed); }\n\tprivate:\n\t\tstd::atomic<int> parent;\n\t};\n\tstd::vector<AtomicParent> parents;\n\npublic:\n\ttypedef typename idict<K, 0>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key)\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tif (parents.size() < database.size()) {\n\t\t\tparents.emplace_back(-1);\n\t\t}\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\t// Why this method is correct for concurent ifind() calls:\n\t// Consider the mfp state after the last non-const method call before\n\t// a particular call to ifind(i). In this state, i's parent chain leads\n\t// to some root R. Let S be the set of integers s such that ifind(s) = R\n\t// in this state. Let 'orig_parents' be the value of 'parents' in this state.\n\t//\n\t// Now consider the concurrent calls to ifind(s), s ∈ S, before the next non-const method\n\t// call. Consider the atomic writes performed by various ifind() calls, in any causally\n\t// consistent order. The first atomic write can only set parents[k] to R, because the\n\t// atomic read of parents[p] in the first while loop can only observe the value\n\t// 'orig_parents[p]'. Subsequent writes can also only set parents[k] to R, because the\n\t// parents[p] reads either observe 'orig_parents[p]' or R (and observing R ends the first\n\t// while loop immediately). Thus all parents[p] reads observe either 'orig_parents[p]'\n\t// or R, so ifind() always returns R.\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (true) {\n\t\t\tint pp = parents[p].get();\n\t\t\tif (pp < 0)\n\t\t\t\tbreak;\n\t\t\tp = pp;\n\t\t}\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k].get();\n\t\t\tconst_cast<AtomicParent*>(&parents[k])->set(p);\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets.\n\t// Makes ifind(j) the root of the merged set.\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i].set(j);\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k].get();\n\t\t\tparents[k].set(i);\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i].set(-1);\n\t}\n\n\tint lookup(const K &a)\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
+                "io.h": "#include <string>\n#include <stdarg.h>\n#include <type_traits>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_IO_H\n#define YOSYS_IO_H\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL {\n\tstruct IdString;\n}\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n\t// For the common case of strings shorter than 128, save a heap\n\t// allocation by using a stack allocated buffer.\n\tconst int kBufSize = 128;\n\tchar buf[kBufSize];\n\tbuf[0] = '\\0';\n\tva_list apc;\n\tva_copy(apc, ap);\n\tint n = vsnprintf(buf, kBufSize, fmt, apc);\n\tva_end(apc);\n\tif (n < kBufSize)\n\t\treturn std::string(buf);\n\n\tstd::string string;\n\tchar *str = NULL;\n#if defined(_WIN32) || defined(__CYGWIN__)\n\tint sz = 2 * kBufSize, rc;\n\twhile (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char *)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n\tif (vasprintf(&str, fmt, ap) < 0)\n\t\tstr = NULL;\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#endif\n}\n\nenum ConversionSpecifier : uint8_t\n{\n\tCONVSPEC_NONE,\n\t// Specifier not understood/supported\n\tCONVSPEC_ERROR,\n\t// Consumes a \"long long\"\n\tCONVSPEC_SIGNED_INT,\n\t// Consumes a \"unsigned long long\"\n\tCONVSPEC_UNSIGNED_INT,\n\t// Consumes a \"double\"\n\tCONVSPEC_DOUBLE,\n\t// Consumes a \"const char*\" or other string type\n\tCONVSPEC_CHAR_PTR,\n\t// Consumes a \"void*\"\n\tCONVSPEC_VOID_PTR,\n};\n\nconstexpr ConversionSpecifier parse_conversion_specifier(char ch, char prev_ch)\n{\n\tswitch (ch) {\n\tcase 'd':\n\tcase 'i':\n\t\treturn CONVSPEC_SIGNED_INT;\n\tcase 'o':\n\tcase 'u':\n\tcase 'x':\n\tcase 'X':\n\tcase 'm':\n\t\treturn CONVSPEC_UNSIGNED_INT;\n\tcase 'c':\n\t\tif (prev_ch == 'l' || prev_ch == 'q' || prev_ch == 'L') {\n\t\t\t// wchar not supported\n\t\t\treturn CONVSPEC_ERROR;\n\t\t}\n\t\treturn CONVSPEC_UNSIGNED_INT;\n\tcase 'e':\n\tcase 'E':\n\tcase 'f':\n\tcase 'F':\n\tcase 'g':\n\tcase 'G':\n\tcase 'a':\n\tcase 'A':\n\t\treturn CONVSPEC_DOUBLE;\n\tcase 's':\n\t\tif (prev_ch == 'l' || prev_ch == 'q' || prev_ch == 'L') {\n\t\t\t// wchar not supported\n\t\t\treturn CONVSPEC_ERROR;\n\t\t}\n\t\treturn CONVSPEC_CHAR_PTR;\n\tcase 'p':\n\t\treturn CONVSPEC_VOID_PTR;\n\tcase '$': // positional parameters\n\tcase 'n':\n\tcase 'S':\n\t\treturn CONVSPEC_ERROR;\n\tdefault:\n\t\treturn CONVSPEC_NONE;\n\t}\n}\n\nenum class DynamicIntCount : uint8_t {\n\tNONE = 0,\n\tONE = 1,\n\tTWO = 2,\n};\n\n// Describes a printf-style format conversion specifier found in a format string.\nstruct FoundFormatSpec\n{\n\t// The start offset of the conversion spec in the format string.\n\tint start;\n\t// The end offset of the conversion spec in the format string.\n\tint end;\n\tConversionSpecifier spec;\n\t// Number of int args consumed by '*' dynamic width/precision args.\n\tDynamicIntCount num_dynamic_ints;\n};\n\n// Ensure there is no format spec.\nconstexpr void ensure_no_format_spec(std::string_view fmt, int index, bool *has_escapes)\n{\n\tint fmt_size = static_cast<int>(fmt.size());\n\t// A trailing '%' is not a format spec.\n\twhile (index + 1 < fmt_size) {\n\t\tif (fmt[index] != '%') {\n\t\t\t++index;\n\t\t\tcontinue;\n\t\t}\n\t\tif (fmt[index + 1] != '%') {\n\t\t\tYOSYS_ABORT(\"More format conversion specifiers than arguments\");\n\t\t}\n\t\t*has_escapes = true;\n\t\tindex += 2;\n\t}\n}\n\n// Returns the next format conversion specifier (starting with '%').\n// Returns CONVSPEC_NONE if there isn't a format conversion specifier.\nconstexpr FoundFormatSpec find_next_format_spec(std::string_view fmt, int fmt_start, bool *has_escapes)\n{\n\tint index = fmt_start;\n\tint fmt_size = static_cast<int>(fmt.size());\n\twhile (index < fmt_size) {\n\t\tif (fmt[index] != '%') {\n\t\t\t++index;\n\t\t\tcontinue;\n\t\t}\n\t\tint p = index + 1;\n\t\tuint8_t num_dynamic_ints = 0;\n\t\twhile (true) {\n\t\t\tif (p == fmt_size) {\n\t\t\t\treturn {0, 0, CONVSPEC_NONE, DynamicIntCount::NONE};\n\t\t\t}\n\t\t\tif (fmt[p] == '%') {\n\t\t\t\t*has_escapes = true;\n\t\t\t\tindex = p + 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (fmt[p] == '*') {\n\t\t\t\tif (num_dynamic_ints >= 2) {\n\t\t\t\t\treturn {0, 0, CONVSPEC_ERROR, DynamicIntCount::NONE};\n\t\t\t\t}\n\t\t\t\t++num_dynamic_ints;\n\t\t\t}\n\t\t\tConversionSpecifier spec = parse_conversion_specifier(fmt[p], fmt[p - 1]);\n\t\t\tif (spec != CONVSPEC_NONE) {\n\t\t\t\treturn {index, p + 1, spec, static_cast<DynamicIntCount>(num_dynamic_ints)};\n\t\t\t}\n\t\t\t++p;\n\t\t}\n\t}\n\treturn {0, 0, CONVSPEC_NONE, DynamicIntCount::NONE};\n}\n\ntemplate <typename... Args>\nconstexpr typename std::enable_if<sizeof...(Args) == 0>::type\ncheck_format(std::string_view fmt, int fmt_start, bool *has_escapes, FoundFormatSpec*, DynamicIntCount)\n{\n\tensure_no_format_spec(fmt, fmt_start, has_escapes);\n}\n\n// Check that the format string `fmt.substr(fmt_start)` is valid for the given type arguments.\n// Fills `specs` with the FoundFormatSpecs found in the format string.\n// `int_args_consumed` is the number of int arguments already consumed to satisfy the\n// dynamic width/precision args for the next format conversion specifier.\ntemplate <typename Arg, typename... Args>\nconstexpr void check_format(std::string_view fmt, int fmt_start, bool *has_escapes, FoundFormatSpec* specs,\n        DynamicIntCount int_args_consumed)\n{\n\tFoundFormatSpec found = find_next_format_spec(fmt, fmt_start, has_escapes);\n\tif (found.num_dynamic_ints > int_args_consumed) {\n\t\t// We need to consume at least one more int for the dynamic\n\t\t// width/precision of this format conversion specifier.\n\t\tif constexpr (!std::is_convertible_v<Arg, int>) {\n\t\t\tYOSYS_ABORT(\"Expected dynamic int argument\");\n\t\t}\n\t\tcheck_format<Args...>(fmt, fmt_start, has_escapes, specs,\n\t\t\tstatic_cast<DynamicIntCount>(static_cast<uint8_t>(int_args_consumed) + 1));\n\t\treturn;\n\t}\n\tswitch (found.spec) {\n\tcase CONVSPEC_NONE:\n\t\tYOSYS_ABORT(\"Expected format conversion specifier for argument\");\n\t\tbreak;\n\tcase CONVSPEC_ERROR:\n\t\tYOSYS_ABORT(\"Found unsupported format conversion specifier\");\n\t\tbreak;\n\tcase CONVSPEC_SIGNED_INT:\n\t\tif constexpr (!std::is_convertible_v<Arg, long long>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to signed integer\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_UNSIGNED_INT:\n\t\tif constexpr (!std::is_convertible_v<Arg, unsigned long long>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to unsigned integer\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_DOUBLE:\n\t\tif constexpr (!std::is_convertible_v<Arg, double>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to double\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_CHAR_PTR:\n\t\tif constexpr (!std::is_convertible_v<Arg, const char *> &&\n\t\t        !std::is_convertible_v<Arg, const std::string &> &&\n\t\t\t!std::is_convertible_v<Arg, const std::string_view &> &&\n\t\t\t!std::is_convertible_v<Arg, const RTLIL::IdString &>) {\n\t\t\tYOSYS_ABORT(\"Expected type convertible to char *\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\tcase CONVSPEC_VOID_PTR:\n\t\tif constexpr (!std::is_convertible_v<Arg, const void *>) {\n\t\t\tYOSYS_ABORT(\"Expected pointer type\");\n\t\t}\n\t\t*specs = found;\n\t\tbreak;\n\t}\n\tcheck_format<Args...>(fmt, found.end, has_escapes, specs + 1, DynamicIntCount::NONE);\n}\n\n// Emit the string representation of `arg` that has been converted to a `long long'.\nvoid format_emit_long_long(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, long long arg);\n\n// Emit the string representation of `arg` that has been converted to a `unsigned long long'.\nvoid format_emit_unsigned_long_long(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, unsigned long long arg);\n\n// Emit the string representation of `arg` that has been converted to a `double'.\nvoid format_emit_double(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, double arg);\n\n// Emit the string representation of `arg` that has been converted to a `const char*'.\nvoid format_emit_char_ptr(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const char *arg);\n\n// Emit the string representation of `arg` that has been converted to a `std::string'.\nvoid format_emit_string(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const std::string &arg);\n\n// Emit the string representation of `arg` that has been converted to a `std::string_view'.\nvoid format_emit_string_view(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, std::string_view arg);\n\n// Emit the string representation of `arg` that has been converted to a `RTLIL::IdString'.\nvoid format_emit_idstring(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const RTLIL::IdString &arg);\n\n// Emit the string representation of `arg` that has been converted to a `double'.\nvoid format_emit_void_ptr(std::string &result, std::string_view spec, int *dynamic_ints,\n\tDynamicIntCount num_dynamic_ints, const void *arg);\n\n// Emit the string representation of `arg` according to the given `FoundFormatSpec`,\n// appending it to `result`.\ntemplate <typename Arg>\ninline void format_emit_one(std::string &result, std::string_view fmt, const FoundFormatSpec &ffspec,\n\tint *dynamic_ints, const Arg& arg)\n{\n\tstd::string_view spec = fmt.substr(ffspec.start, ffspec.end - ffspec.start);\n\tDynamicIntCount num_dynamic_ints = ffspec.num_dynamic_ints;\n\tswitch (ffspec.spec) {\n\tcase CONVSPEC_SIGNED_INT:\n\t\tif constexpr (std::is_convertible_v<Arg, long long>) {\n\t\t\tlong long s = arg;\n\t\t\tformat_emit_long_long(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_UNSIGNED_INT:\n\t\tif constexpr (std::is_convertible_v<Arg, unsigned long long>) {\n\t\t\tunsigned long long s = arg;\n\t\t\tformat_emit_unsigned_long_long(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_DOUBLE:\n\t\tif constexpr (std::is_convertible_v<Arg, double>) {\n\t\t\tdouble s = arg;\n\t\t\tformat_emit_double(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_CHAR_PTR:\n\t\tif constexpr (std::is_convertible_v<Arg, const char *>) {\n\t\t\tconst char *s = arg;\n\t\t\tformat_emit_char_ptr(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tif constexpr (std::is_convertible_v<Arg, const std::string &>) {\n\t\t\tconst std::string &s = arg;\n\t\t\tformat_emit_string(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tif constexpr (std::is_convertible_v<Arg, const std::string_view &>) {\n\t\t\tconst std::string_view &s = arg;\n\t\t\tformat_emit_string_view(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tif constexpr (std::is_convertible_v<Arg, const RTLIL::IdString &>) {\n\t\t\tconst RTLIL::IdString &s = arg;\n\t\t\tformat_emit_idstring(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tcase CONVSPEC_VOID_PTR:\n\t\tif constexpr (std::is_convertible_v<Arg, const void *>) {\n\t\t\tconst void *s = arg;\n\t\t\tformat_emit_void_ptr(result, spec, dynamic_ints, num_dynamic_ints, s);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tYOSYS_ABORT(\"Internal error\");\n}\n\n// Append the format string `fmt` to `result`, assuming there are no format conversion\n// specifiers other than \"%%\" and therefore no arguments. Unescape \"%%\".\nvoid format_emit_unescaped(std::string &result, std::string_view fmt);\nstd::string unescape_format_string(std::string_view fmt);\n\ninline void format_emit(std::string &result, std::string_view fmt, int fmt_start,\n\tbool has_escapes, const FoundFormatSpec*, int*, DynamicIntCount)\n{\n\tfmt = fmt.substr(fmt_start);\n\tif (has_escapes) {\n\t\tformat_emit_unescaped(result, fmt);\n\t} else {\n\t\tresult += fmt;\n\t}\n}\n// Format `args` according to `fmt` (starting at `fmt_start`) and `specs` and append to `result`.\n// `num_dynamic_ints` in `dynamic_ints[]` have already been collected to provide as\n// dynamic width/precision args for the next format conversion specifier.\ntemplate <typename Arg, typename... Args>\ninline void format_emit(std::string &result, std::string_view fmt, int fmt_start, bool has_escapes,\n\tconst FoundFormatSpec* specs, int *dynamic_ints, DynamicIntCount num_dynamic_ints,\n\tconst Arg &arg, const Args &... args)\n{\n\tif (specs->num_dynamic_ints > num_dynamic_ints) {\n\t\t// Collect another int for the dynamic width precision/args\n\t\t// for the next format conversion specifier.\n\t\tif constexpr (std::is_convertible_v<Arg, int>) {\n\t\t\tdynamic_ints[static_cast<uint8_t>(num_dynamic_ints)] = arg;\n\t\t} else {\n\t\t\tYOSYS_ABORT(\"Internal error\");\n\t\t}\n\t\tformat_emit(result, fmt, fmt_start, has_escapes, specs, dynamic_ints,\n\t\t            static_cast<DynamicIntCount>(static_cast<uint8_t>(num_dynamic_ints) + 1), args...);\n\t\treturn;\n\t}\n\tstd::string_view str = fmt.substr(fmt_start, specs->start - fmt_start);\n\tif (has_escapes) {\n\t\tformat_emit_unescaped(result, str);\n\t} else {\n\t\tresult += str;\n\t}\n\tformat_emit_one(result, fmt, *specs, dynamic_ints, arg);\n\tformat_emit(result, fmt, specs->end, has_escapes, specs + 1, dynamic_ints, DynamicIntCount::NONE, args...);\n}\n\ntemplate <typename... Args>\ninline std::string format_emit_toplevel(std::string_view fmt, bool has_escapes, const FoundFormatSpec* specs, const Args &... args)\n{\n\tstd::string result;\n\tint dynamic_ints[2] = { 0, 0 };\n\tformat_emit(result, fmt, 0, has_escapes, specs, dynamic_ints, DynamicIntCount::NONE, args...);\n\treturn result;\n}\ntemplate <>\ninline std::string format_emit_toplevel(std::string_view fmt, bool has_escapes, const FoundFormatSpec*)\n{\n\tif (!has_escapes) {\n\t\treturn std::string(fmt);\n\t}\n\treturn unescape_format_string(fmt);\n}\n\n// This class parses format strings to build a list of `FoundFormatSpecs` in `specs`.\n// When the compiler supports `consteval` (C++20), this parsing happens at compile time and\n// type errors will be reported at compile time. Otherwise the parsing happens at\n// runtime and type errors will trigger an `abort()` at runtime.\ntemplate <typename... Args>\nclass FmtString\n{\npublic:\n\t// Implicit conversion from const char * means that users can pass\n\t// C string constants which are automatically parsed.\n\tYOSYS_CONSTEVAL FmtString(const char *p) : fmt(p)\n\t{\n\t\tcheck_format<Args...>(fmt, 0, &has_escapes, specs, DynamicIntCount::NONE);\n\t}\n\tstd::string format(const Args &... args)\n\t{\n\t\treturn format_emit_toplevel(fmt, has_escapes, specs, args...);\n\t}\n\tstd::string_view format_string() const { return fmt; }\nprivate:\n\tstd::string_view fmt;\n\tbool has_escapes = false;\n\tFoundFormatSpec specs[sizeof...(Args)] = {};\n};\n\ntemplate <typename T> struct WrapType { using type = T; };\ntemplate <typename T> using TypeIdentity = typename WrapType<T>::type;\n\ntemplate <typename... Args>\ninline std::string stringf(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\treturn fmt.format(args...);\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(const std::string& filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname, bool is_exec = false);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\nvoid append_globbed(std::vector<std::string>& paths, std::string pattern);\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_IO_H\n",
                 "json.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n    enum Scope {\n        VALUE,\n        OBJECT_FIRST,\n        OBJECT,\n        ARRAY_FIRST,\n        ARRAY,\n    };\n\n    struct Target {\n        virtual void emit(const char *data) = 0;\n        virtual void flush() {};\n        virtual ~Target() {};\n    };\n\n    std::string newline_indent = \"\\n\";\n    std::vector<std::unique_ptr<Target>> targets;\n    std::vector<Scope> state = {VALUE};\n    int compact_depth = INT_MAX;\npublic:\n\n    void emit_to_log();\n    void append_to_string(std::string &target);\n    bool write_to_file(const std::string &path);\n\n    bool active() { return !targets.empty(); }\n\n    void compact() { compact_depth = GetSize(state); }\n\n    void line(bool space_if_inline = true);\n    void raw(const char *raw_json);\n    void flush();\n    void begin_object();\n    void begin_array();\n    void end_object();\n    void end_array();\n    void name(const char *name);\n    void begin_value();\n    void end_value();\n    void value_json(const Json &value);\n    void value(unsigned int value) { value_json(Json((int)value)); }\n    template<typename T>\n    void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n    void entry_json(const char *name, const Json &value);\n    void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n    template<typename T>\n    void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n    template<typename T>\n    void object(const T &&values)\n    {\n        begin_object();\n        for (auto &item : values)\n            entry(item.first, item.second);\n        end_object();\n    }\n\n    template<typename T>\n    void array(const T &&values)\n    {\n        begin_array();\n        for (auto &item : values)\n            value(item);\n        end_array();\n    }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "log.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n#  include <intrin.h>\n#else\n#  include <sys/time.h>\n#  include <sys/resource.h>\n#  if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n#    include <signal.h>\n#  endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n#  define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n#  define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n#  define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n#  define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n#  define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\n[[deprecated]]\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n#  define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nvoid log_formatted_string(std::string_view format, std::string str);\ntemplate <typename... Args>\ninline void log(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tif (log_make_debug && !ys_debug(1))\n\t\treturn;\n\tlog_formatted_string(fmt.format_string(), fmt.format(args...));\n}\n\nvoid log_formatted_header(RTLIL::Design *design, std::string_view format, std::string str);\ntemplate <typename... Args>\ninline void log_header(RTLIL::Design *design, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tlog_formatted_header(design, fmt.format_string(), fmt.format(args...));\n}\n\nvoid log_formatted_warning(std::string_view prefix, std::string str);\ntemplate <typename... Args>\ninline void log_warning(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tlog_formatted_warning(\"Warning: \", fmt.format(args...));\n}\n\ninline void log_formatted_warning_noprefix(std::string str)\n{\n\tlog_formatted_warning(\"\", str);\n}\ntemplate <typename... Args>\ninline void log_warning_noprefix(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tlog_formatted_warning(\"\", fmt.format(args...));\n}\n\nvoid log_experimental(const std::string &str);\n\n// Log with filename to report a problem in a source file.\nvoid log_formatted_file_warning(std::string_view filename, int lineno, std::string str);\ntemplate <typename... Args>\nvoid log_file_warning(std::string_view filename, int lineno, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tlog_formatted_file_warning(filename, lineno, fmt.format(args...));\n}\n\nvoid log_formatted_file_info(std::string_view filename, int lineno, std::string str);\ntemplate <typename... Args>\nvoid log_file_info(std::string_view filename, int lineno, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tif (log_make_debug && !ys_debug(1))\n\t\treturn;\n\tlog_formatted_file_info(filename, lineno, fmt.format(args...));\n}\n\n[[noreturn]] void log_formatted_error(std::string str);\ntemplate <typename... Args>\n[[noreturn]] void log_error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tlog_formatted_error(fmt.format(args...));\n}\n\n[[noreturn]] void log_formatted_file_error(std::string_view filename, int lineno, std::string str);\ntemplate <typename... Args>\n[[noreturn]] void log_file_error(std::string_view filename, int lineno, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tlog_formatted_file_error(filename, lineno, fmt.format(args...));\n}\n\n[[noreturn]] void log_formatted_cmd_error(std::string str);\ntemplate <typename... Args>\n[[noreturn]] void log_cmd_error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)\n{\n\tlog_formatted_cmd_error(fmt.format(args...));\n}\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nextern dict<std::string, LogExpectedItem> log_expect_prefix_log, log_expect_prefix_warning, log_expect_prefix_error;\nvoid log_check_expected();\n\nstd::string log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nstd::string log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n[[noreturn]]\nvoid log_assert_failure(const char *expr, const char *file, int line);\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_assert_failure(expr, file, line);\n}\n#  define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n#  define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n[[noreturn]]\nvoid log_abort_internal(const char *file, int line);\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_abort_internal(__FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n    static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n    __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n#  define cover(...) do { } while (0)\n#  define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n#  ifdef _WIN32\n\t\treturn 0;\n#  elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n#  else\n#    error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n#  endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c)\n{\n\tif (c >= 32 && c < 127) {\n\t\tlog(\"'%c'\", c);\n\t} else {\n\t\tlog(\"'\\\\x%02x'\", c);\n\t}\n}\nstatic inline void log_dump_val_worker(unsigned char c)\n{\n\tif (c >= 32 && c < 127) {\n\t\tlog(\"'%c'\", c);\n\t} else {\n\t\tlog(\"'\\\\x%02x'\", c);\n\t}\n}\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T> static inline void log_dump_val_worker(dict<K, T> &v);\ntemplate<typename K> static inline void log_dump_val_worker(pool<K> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T>\nstatic inline void log_dump_val_worker(dict<K, T> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(\"%s \", first ? \"\" : \",\");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(pool<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(\"%s \", first ? \"\" : \",\");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(\"%s \", first ? \"\" : \",\");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
                 "macc.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct term_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\tstd::vector<term_t> terms;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<term_t> new_terms;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : terms)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_terms.push_back(port);\n\t\t}\n\n\t\tif (off.as_bool()) {\n\t\t\tterm_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_terms.push_back(port);\n\t\t}\n\n\t\tnew_terms.swap(terms);\n\t}\n\n\tvoid from_cell_v1(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tterms.clear();\n\n\t\tauto config_bits = cell->getParam(ID::CONFIG);\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tterm_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tterms.push_back(this_port);\n\t\t}\n\n\t\tfor (auto bit : cell->getPort(ID::B))\n\t\t\tterms.push_back(term_t{{bit}, {}, false, false});\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (cell->type == ID($macc)) {\n\t\t\tfrom_cell_v1(cell);\n\t\t\treturn;\n\t\t}\n\t\tlog_assert(cell->type == ID($macc_v2));\n\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\t\tRTLIL::SigSpec port_b = cell->getPort(ID::B);\n\t\tRTLIL::SigSpec port_c = cell->getPort(ID::C);\n\n\t\tterms.clear();\n\n\t\tint nproducts = cell->getParam(ID::NPRODUCTS).as_int();\n\t\tconst Const &product_neg = cell->getParam(ID::PRODUCT_NEGATED);\n\t\tconst Const &a_widths = cell->getParam(ID::A_WIDTHS);\n\t\tconst Const &b_widths = cell->getParam(ID::B_WIDTHS);\n\t\tconst Const &a_signed = cell->getParam(ID::A_SIGNED);\n\t\tconst Const &b_signed = cell->getParam(ID::B_SIGNED);\n\t\tint ai = 0, bi = 0;\n\t\tfor (int i = 0; i < nproducts; i++) {\n\t\t\tterm_t term;\n\n\t\t\tlog_assert(a_signed[i] == b_signed[i]);\n\t\t\tterm.is_signed = (a_signed[i] == State::S1);\n\t\t\tint a_width = a_widths.extract(16 * i, 16).as_int(false);\n\t\t\tint b_width = b_widths.extract(16 * i, 16).as_int(false);\n\n\t\t\tterm.in_a = port_a.extract(ai, a_width);\n\t\t\tai += a_width;\n\t\t\tterm.in_b = port_b.extract(bi, b_width);\n\t\t\tbi += b_width;\n\t\t\tterm.do_subtract = (product_neg[i] == State::S1);\n\n\t\t\tterms.push_back(term);\n\t\t}\n\t\tlog_assert(port_a.size() == ai);\n\t\tlog_assert(port_b.size() == bi);\n\n\t\tint naddends = cell->getParam(ID::NADDENDS).as_int();\n\t\tconst Const &addend_neg = cell->getParam(ID::ADDEND_NEGATED);\n\t\tconst Const &c_widths = cell->getParam(ID::C_WIDTHS);\n\t\tconst Const &c_signed = cell->getParam(ID::C_SIGNED);\n\t\tint ci = 0;\n\t\tfor (int i = 0; i < naddends; i++) {\n\t\t\tterm_t term;\n\n\t\t\tterm.is_signed = (c_signed[i] == State::S1);\n\t\t\tint c_width = c_widths.extract(16 * i, 16).as_int(false);\n\n\t\t\tterm.in_a = port_c.extract(ci, c_width);\n\t\t\tci += c_width;\n\t\t\tterm.do_subtract = (addend_neg[i] == State::S1);\n\n\t\t\tterms.push_back(term);\n\t\t}\n\t\tlog_assert(port_c.size() == ci);\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell)\n\t{\n\t\tcell->type = ID($macc_v2);\n\n\t\tint nproducts = 0, naddends = 0;\n\t\tConst a_signed, b_signed, a_widths, b_widths, product_negated;\n\t\tConst c_signed, c_widths, addend_negated;\n\t\tSigSpec a, b, c;\n\n\t\tfor (int i = 0; i < (int) terms.size(); i++) {\n\t\t\tSigSpec term_a = terms[i].in_a, term_b = terms[i].in_b;\n\n\t\t\tif (term_b.empty()) {\n\t\t\t\t// addend\n\t\t\t\tc_widths.append(Const(term_a.size(), 16));\n\t\t\t\tc_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\taddend_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tc.append(term_a);\n\t\t\t\tnaddends++;\n\t\t\t} else {\n\t\t\t\t// product\n\t\t\t\ta_widths.append(Const(term_a.size(), 16));\n\t\t\t\tb_widths.append(Const(term_b.size(), 16));\n\t\t\t\ta_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tb_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tproduct_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\ta.append(term_a);\n\t\t\t\tb.append(term_b);\n\t\t\t\tnproducts++;\n\t\t\t}\n\t\t}\n\n\t\tif (a_signed.empty())\n\t\t\ta_signed = {RTLIL::Sx};\n\t\tif (b_signed.empty())\n\t\t\tb_signed = {RTLIL::Sx};\n\t\tif (c_signed.empty())\n\t\t\tc_signed = {RTLIL::Sx};\n\t\tif (a_widths.empty())\n\t\t\ta_widths = {RTLIL::Sx};\n\t\tif (b_widths.empty())\n\t\t\tb_widths = {RTLIL::Sx};\n\t\tif (c_widths.empty())\n\t\t\tc_widths = {RTLIL::Sx};\n\t\tif (product_negated.empty())\n\t\t\tproduct_negated = {RTLIL::Sx};\n\t\tif (addend_negated.empty())\n\t\t\taddend_negated = {RTLIL::Sx};\n\n\t\tcell->setParam(ID::NPRODUCTS, nproducts);\n\t\tcell->setParam(ID::PRODUCT_NEGATED, product_negated);\n\t\tcell->setParam(ID::NADDENDS, naddends);\n\t\tcell->setParam(ID::ADDEND_NEGATED, addend_negated);\n\t\tcell->setParam(ID::A_SIGNED, a_signed);\n\t\tcell->setParam(ID::B_SIGNED, b_signed);\n\t\tcell->setParam(ID::C_SIGNED, c_signed);\n\t\tcell->setParam(ID::A_WIDTHS, a_widths);\n\t\tcell->setParam(ID::B_WIDTHS, b_widths);\n\t\tcell->setParam(ID::C_WIDTHS, c_widths);\n\t\tcell->setPort(ID::A, a);\n\t\tcell->setPort(ID::B, b);\n\t\tcell->setPort(ID::C, c);\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto bit : result)\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : terms)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool is_simple_product()\n\t{\n\t\treturn terms.size() == 1 &&\n\t\t\t\t!terms[0].in_b.empty() &&\n\t\t\t\t!terms[0].do_subtract;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
@@ -182,7 +176,7 @@ export const filesystem = {
                 "modtools.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MODTOOLS_H\n#define MODTOOLS_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ModIndex : public RTLIL::Monitor\n{\n\tstruct PortInfo {\n\t\tRTLIL::Cell* cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tPortInfo() : cell(), port(), offset() { }\n\t\tPortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }\n\n\t\tbool operator<(const PortInfo &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (offset != other.offset)\n\t\t\t\treturn offset < other.offset;\n\t\t\treturn port < other.port;\n\t\t}\n\n\t\tbool operator==(const PortInfo &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tstruct SigBitInfo\n\t{\n\t\tbool is_input, is_output;\n\t\tpool<PortInfo> ports;\n\n\t\tSigBitInfo() : is_input(false), is_output(false) { }\n\n\t\tbool operator==(const SigBitInfo &other) const {\n\t\t\treturn is_input == other.is_input && is_output == other.is_output && ports == other.ports;\n\t\t}\n\n\t\tvoid merge(const SigBitInfo &other)\n\t\t{\n\t\t\tis_input = is_input || other.is_input;\n\t\t\tis_output = is_output || other.is_output;\n\t\t\tports.insert(other.ports.begin(), other.ports.end());\n\t\t}\n\t};\n\n\tSigMap sigmap;\n\tRTLIL::Module *module;\n\tstd::map<RTLIL::SigBit, SigBitInfo> database;\n\tint auto_reload_counter;\n\tbool auto_reload_module;\n\n\tvoid port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.insert(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tvoid port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.erase(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tconst SigBitInfo &info(RTLIL::SigBit bit)\n\t{\n\t\treturn database[sigmap(bit)];\n\t}\n\n\tvoid reload_module(bool reset_sigmap = true)\n\t{\n\t\tif (reset_sigmap) {\n\t\t\tsigmap.clear();\n\t\t\tsigmap.set(module);\n\t\t}\n\n\t\tdatabase.clear();\n\t\tfor (auto wire : module->wires())\n\t\t\tif (wire->port_input || wire->port_output)\n\t\t\t\tfor (int i = 0; i < GetSize(wire); i++) {\n\t\t\t\t\tRTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));\n\t\t\t\t\tif (bit.wire && wire->port_input)\n\t\t\t\t\t\tdatabase[bit].is_input = true;\n\t\t\t\t\tif (bit.wire && wire->port_output)\n\t\t\t\t\t\tdatabase[bit].is_output = true;\n\t\t\t\t}\n\t\tfor (auto cell : module->cells())\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tport_add(cell, conn.first, conn.second);\n\n\t\tif (auto_reload_module) {\n\t\t\tif (++auto_reload_counter > 2)\n\t\t\t\tlog_warning(\"Auto-reload in ModIndex -- possible performance bug!\\n\");\n\t\t\tauto_reload_module = false;\n\t\t}\n\t}\n\n\tvoid check()\n\t{\n#ifndef NDEBUG\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (auto it : database)\n\t\t\tlog_assert(it.first == sigmap(it.first));\n\n\t\tauto database_bak = std::move(database);\n\t\treload_module(false);\n\n\t\tif (!(database == database_bak))\n\t\t{\n\t\t\tfor (auto &it : database_bak)\n\t\t\t\tif (!database.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database_bak, not database: %s\\n\", log_signal(it.first));\n\n\t\t\tfor (auto &it : database)\n\t\t\t\tif (!database_bak.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database, not database_bak: %s\\n\", log_signal(it.first));\n\t\t\t\telse if (!(it.second == database_bak.at(it.first)))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Different content for database[%s].\\n\", log_signal(it.first));\n\n\t\t\tlog_assert(database == database_bak);\n\t\t}\n#endif\n\t}\n\n\tvoid notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override\n\t{\n\t\tlog_assert(module == cell->module);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tport_del(cell, port, old_sig);\n\t\tport_add(cell, port, sig);\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override\n\t{\n\t\tlog_assert(module == mod);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (int i = 0; i < GetSize(sigsig.first); i++)\n\t\t{\n\t\t\tRTLIL::SigBit lhs = sigmap(sigsig.first[i]);\n\t\t\tRTLIL::SigBit rhs = sigmap(sigsig.second[i]);\n\t\t\tbool has_lhs = database.count(lhs) != 0;\n\t\t\tbool has_rhs = database.count(rhs) != 0;\n\n\t\t\tif (!has_lhs && !has_rhs) {\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t} else\n\t\t\tif (!has_rhs) {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\tlhs = sigmap(lhs);\n\t\t\t\tif (lhs.wire)\n\t\t\t\t\tdatabase[lhs] = new_info;\n\t\t\t} else\n\t\t\tif (!has_lhs) {\n\t\t\t\tSigBitInfo new_info = database.at(rhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t} else {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tnew_info.merge(database.at(rhs));\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tvoid notify_blackout(RTLIL::Module *mod) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)\n\t{\n\t\tauto_reload_counter = 0;\n\t\tauto_reload_module = true;\n\t\tmodule->monitors.insert(this);\n\t}\n\n\t~ModIndex()\n\t{\n\t\tmodule->monitors.erase(this);\n\t}\n\n\tSigBitInfo *query(RTLIL::SigBit bit)\n\t{\n\t\tif (auto_reload_module)\n\t\t\treload_module();\n\n\t\tauto it = database.find(sigmap(bit));\n\t\tif (it == database.end())\n\t\t\treturn nullptr;\n\t\telse\n\t\t\treturn &it->second;\n\t}\n\n\tbool query_is_input(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_input;\n\t}\n\n\tbool query_is_output(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_output;\n\t}\n\n\tpool<PortInfo> &query_ports(RTLIL::SigBit bit)\n\t{\n\t\tstatic pool<PortInfo> empty_result_set;\n\t\tSigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn empty_result_set;\n\t\treturn info->ports;\n\t}\n\n\tvoid dump_db()\n\t{\n\t\tlog(\"--- ModIndex Dump ---\\n\");\n\n\t\tif (auto_reload_module) {\n\t\t\tlog(\"AUTO-RELOAD\\n\");\n\t\t\treload_module();\n\t\t}\n\n\t\tfor (auto &it : database) {\n\t\t\tlog(\"BIT %s:\\n\", log_signal(it.first));\n\t\t\tif (it.second.is_input)\n\t\t\t\tlog(\"  PRIMARY INPUT\\n\");\n\t\t\tif (it.second.is_output)\n\t\t\t\tlog(\"  PRIMARY OUTPUT\\n\");\n\t\t\tfor (auto &port : it.second.ports)\n\t\t\t\tlog(\"  PORT: %s.%s[%d] (%s)\\n\", log_id(port.cell),\n\t\t\t\t\t\tlog_id(port.port), port.offset, log_id(port.cell->type));\n\t\t}\n\t}\n};\n\nstruct ModWalker\n{\n\tstruct PortBit\n\t{\n\t\tRTLIL::Cell *cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\t\tPortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}\n\n\t\tbool operator<(const PortBit &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (port != other.port)\n\t\t\t\treturn port < other.port;\n\t\t\treturn offset < other.offset;\n\t\t}\n\n\t\tbool operator==(const PortBit &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tRTLIL::Design *design;\n\tRTLIL::Module *module;\n\n\tCellTypes ct;\n\tSigMap sigmap;\n\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_drivers;\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_consumers;\n\tpool<RTLIL::SigBit> signal_inputs, signal_outputs;\n\n\tdict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;\n\n\tvoid add_wire(RTLIL::Wire *wire)\n\t{\n\t\tif (wire->port_input) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_inputs.insert(bit);\n\t\t}\n\n\t\tif (wire->port_output) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_outputs.insert(bit);\n\t\t}\n\t}\n\n\tvoid add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)\n\t{\n\t\tfor (int i = 0; i < int(bits.size()); i++)\n\t\t\tif (bits[i].wire != NULL) {\n\t\t\t\tPortBit pbit {cell, port, i};\n\t\t\t\tif (is_output) {\n\t\t\t\t\tsignal_drivers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_outputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t\tif (is_input) {\n\t\t\t\t\tsignal_consumers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_inputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\tvoid add_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (ct.cell_known(cell->type)) {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second),\n\t\t\t\t\t\tct.cell_output(cell->type, conn.first),\n\t\t\t\t\t\tct.cell_input(cell->type, conn.first));\n\t\t} else {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second), true, true);\n\t\t}\n\t}\n\n\tModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)\n\t{\n\t\tct.setup(design);\n\t\tif (module)\n\t\t\tsetup(module);\n\t}\n\n\tvoid setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)\n\t{\n\t\tthis->module = module;\n\n\t\tsigmap.set(module);\n\n\t\tsignal_drivers.clear();\n\t\tsignal_consumers.clear();\n\t\tsignal_inputs.clear();\n\t\tsignal_outputs.clear();\n\t\tcell_inputs.clear();\n\t\tcell_outputs.clear();\n\n\t\tfor (auto &it : module->wires_)\n\t\t\tadd_wire(it.second);\n\t\tfor (auto &it : module->cells_)\n\t\t\tif (filter_ct == NULL || filter_ct->cell_known(it.second->type))\n\t\t\t\tadd_cell(it.second);\n\t}\n\n\t// get_* methods -- single RTLIL::SigBit\n\n\tinline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_drivers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_consumers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_inputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_outputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- container of RTLIL::SigBit's (always by reference)\n\n\ttemplate<typename T>\n\tinline bool get_drivers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_drivers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_consumers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_consumers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_inputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_outputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- call by RTLIL::SigSpec (always by value)\n\n\tbool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_drivers(result, bits);\n\t}\n\n\tbool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_consumers(result, bits);\n\t}\n\n\tbool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_inputs(result, bits);\n\t}\n\n\tbool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_outputs(result, bits);\n\t}\n\n\t// has_* methods -- call by reference\n\n\ttemplate<typename T>\n\tinline bool has_drivers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_consumers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_inputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_outputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n\n\t// has_* methods -- call by value\n\n\tinline bool has_drivers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\tinline bool has_consumers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\tinline bool has_inputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\tinline bool has_outputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "qcsat.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2021  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef QCSAT_H\n#define QCSAT_H\n\n#include \"kernel/satgen.h\"\n#include \"kernel/modtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// This is a helper class meant for easy construction of quick SAT queries\n// to a combinatorial input cone of some set of signals, meant for SAT-based\n// optimizations.  Various knobs are provided to set just how much of the\n// cone should be included in the model — since this class is meant for\n// optimization, it should not be a correctness problem when some cells are\n// skipped and the solver spuriously returns SAT with a solution that\n// cannot exist in reality due to skipped constraints (ie. only UNSAT results\n// from this class should be considered binding).\nstruct QuickConeSat {\n\tModWalker &modwalker;\n\tezSatPtr ez;\n\tSatGen satgen;\n\n\t// The effort level knobs.\n\n\t// The maximum \"complexity level\" of cells that will be imported.\n\t// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa\n\t// - 2: addition, subtraction, greater/less than comparisons, lcu\n\t// - 3: shifts\n\t// - 4: multiplication, division, power\n\tint max_cell_complexity = 2;\n\t// The maximum number of cells to import, or 0 for no limit.\n\tint max_cell_count = 0;\n\t// If non-0, skip importing cells with more than this number of output bits.\n\tint max_cell_outs = 0;\n\n\t// Internal state.\n\tpool<RTLIL::Cell*> imported_cells;\n\tpool<RTLIL::Wire*> imported_onehot;\n\tpool<RTLIL::SigBit> bits_queue;\n\n\tQuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}\n\n\t// Imports a signal into the SAT solver, queues its input cone to be\n\t// imported in the next prepare() call.\n\tstd::vector<int> importSig(SigSpec sig);\n\tint importSigBit(SigBit bit);\n\n\t// Imports the input cones of all previously importSig'd signals into\n\t// the SAT solver.\n\tvoid prepare();\n\n\t// Returns the \"complexity level\" of a given cell.\n\tstatic int cell_complexity(RTLIL::Cell *cell);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "register.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\n#ifdef YOSYS_ENABLE_HELP_SOURCE\n\t#include <version>\n#\tif __cpp_lib_source_location == 201907L\n\t\t#include <source_location>\n\t\tusing std::source_location;\n\t\t#define HAS_SOURCE_LOCATION\n#\telif defined(__has_include)\n#\t\tif __has_include(<experimental/source_location>)\n\t\t\t#include <experimental/source_location>\n\t\t\tusing std::experimental::source_location;\n\t\t\t#define HAS_SOURCE_LOCATION\n#\t\tendif\n#\tendif\n#endif\n\n#ifndef HAS_SOURCE_LOCATION\nstruct source_location { // dummy placeholder\n\tint line() const { return 0; }\n\tint column() const { return 0; }\n\tconst char* file_name() const { return \"unknown\"; }\n\tconst char* function_name() const { return \"unknown\"; }\n\tstatic const source_location current(...) { return source_location(); }\n};\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tsource_location location;\n\tPass(std::string name, std::string short_help = \"** document me **\",\n\t\tsource_location location = source_location::current());\n\t// Prefer overriding 'Pass::on_shutdown()' if possible\n\tvirtual ~Pass();\n\n\t// Makes calls to log() to generate help message\n\tvirtual void help();\n\t// Uses PrettyHelp::get_current() to produce a more portable formatted help message\n\tvirtual bool formatted_help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\tbool internal_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tvoid internal() {\n\t\tinternal_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\", source_location location = source_location::current()) :\n\t\tPass(name, short_help, location) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\",\n\t\tsource_location location = source_location::current());\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\",\n\t\tsource_location location = source_location::current());\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename,  std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "rtlil.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\n#include <string_view>\n#include <unordered_map>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5  // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7  // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE   = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2,  // only used for parameters\n\t\tCONST_FLAG_REAL   = 4   // only used for parameters\n\t};\n\n\tenum SelectPartials : unsigned char {\n\t\tSELECT_ALL = 0,          // include partial modules\n\t\tSELECT_WHOLE_ONLY = 1,   // ignore partial modules\n\t\tSELECT_WHOLE_WARN = 2,   // call log_warning on partial module\n\t\tSELECT_WHOLE_ERR = 3,    // call log_error on partial module\n\t\tSELECT_WHOLE_CMDERR = 4  // call log_cmd_error on partial module\n\t};\n\n\tenum SelectBoxes : unsigned char {\n\t\tSB_ALL = 0,            // include boxed modules\n\t\tSB_WARN = 1,           // helper for log_warning (not for direct use)\n\t\tSB_ERR = 2,            // helper for log_error (not for direct use)\n\t\tSB_CMDERR = 3,         // helper for log_cmd_error (not for direct use)\n\t\tSB_UNBOXED_ONLY = 4,   // ignore boxed modules\n\t\tSB_UNBOXED_WARN = 5,   // call log_warning on boxed module\n\t\tSB_UNBOXED_ERR = 6,    // call log_error on boxed module\n\t\tSB_UNBOXED_CMDERR = 7, // call log_cmd_error on boxed module\n\t\tSB_INCL_WB = 8,        // helper for white boxes (not for direct use)\n\t\tSB_EXCL_BB_ONLY = 12,  // ignore black boxes, but not white boxes\n\t\tSB_EXCL_BB_WARN = 13,  // call log_warning on black boxed module\n\t\tSB_EXCL_BB_ERR = 14,   // call log_error on black boxed module\n\t\tSB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module\n\t};\n\n\tenum class StaticId : short {\n\t\tSTATIC_ID_BEGIN = 0,\n#define X(N) N,\n#include \"kernel/constids.inc\"\n#undef X\n\t\tSTATIC_ID_END,\n\t};\n\n\tenum PortDir : unsigned char  {\n\t\tPD_UNKNOWN = 0,\n\t\tPD_INPUT = 1,\n\t\tPD_OUTPUT = 2,\n\t\tPD_INOUT = 3\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct NamedObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\tstruct StaticIdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct StaticIdString {\n\t\tconstexpr StaticIdString(StaticId id, const IdString &id_str) : id_str(id_str), id(id) {}\n\t\tconstexpr inline operator const IdString &() const { return id_str; }\n\t\tconstexpr inline int index() const { return static_cast<short>(id); }\n\t\tconstexpr inline const IdString &id_string() const { return id_str; }\n\n\t\tconst IdString &id_str;\n\t\tconst StaticId id;\n\t};\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic std::unordered_map<std::string_view, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\t// For prepopulated IdStrings, the refcount is meaningless since they\n\t// are never freed even if the refcount is zero. For code efficiency\n\t// we increment the refcount of prepopulated IdStrings like any other string,\n\t// but we never decrement the refcount or check whether it's zero.\n\t// So, make this unsigned because refcounts of preopulated IdStrings may overflow\n\t// and overflow of signed integers is undefined behavior.\n\tstatic std::vector<uint32_t> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %u)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace && idx >= static_cast<short>(StaticId::STATIC_ID_END))\n\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tauto it = global_id_index_.find((char*)p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tensure_prepopulated();\n\n\t\tif (!p[0])\n\t\t\treturn 0;\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tlog_assert(p[1] != 0);\n\t\tfor (const char *c = p; *c; c++)\n\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (idx < static_cast<short>(StaticId::STATIC_ID_END) || !destruct_guard_ok)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tuint32_t &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\t\tlog_assert(idx >= static_cast<short>(StaticId::STATIC_ID_END));\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\tinline IdString(StaticId id) : index_(static_cast<short>(id)) {}\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tconstexpr inline const IdString &id_string() const { return *this; }\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\tinline bool operator==(const StaticIdString &rhs) const;\n\tinline bool operator!=(const StaticIdString &rhs) const;\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn index_ == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(const Args &... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const StaticIdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\nprivate:\n\tstatic void prepopulate();\n\npublic:\n\tstatic void ensure_prepopulated() {\n\t\tif (global_id_index_.empty())\n\t\t\tprepopulate();\n\t}\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString &id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString &id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\ninline bool RTLIL::IdString::operator==(const RTLIL::StaticIdString &rhs) const {\n\treturn index_ == rhs.index();\n}\ninline bool RTLIL::IdString::operator!=(const RTLIL::StaticIdString &rhs) const {\n\treturn index_ != rhs.index();\n}\n\nnamespace RTLIL {\n\tnamespace IDInternal {\n#define X(_id) extern const IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t}\n\tnamespace ID {\n#define X(_id) constexpr StaticIdString _id(StaticId::_id, IDInternal::_id);\n#include \"kernel/constids.inc\"\n#undef X\n\t}\n}\n\nstruct IdTableEntry {\n\tconst std::string_view name;\n\tconst RTLIL::StaticIdString static_id;\n};\n\nconstexpr IdTableEntry IdTable[] = {\n#define X(_id) {#_id, ID::_id},\n#include \"kernel/constids.inc\"\n#undef X\n};\n\nconstexpr int lookup_well_known_id(std::string_view name)\n{\n\tint low = 0;\n\tint high = sizeof(IdTable) / sizeof(IdTable[0]);\n\twhile (high - low >= 2) {\n\t\tint mid = (low + high) / 2;\n\t\tif (name < IdTable[mid].name)\n\t\t\thigh = mid;\n\t\telse\n\t\t\tlow = mid;\n\t}\n\tif (IdTable[low].name == name)\n\t\treturn low;\n\treturn -1;\n}\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n//  sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\ntypedef const RTLIL::IdString &IDMacroHelperFunc();\n\ntemplate <int IdTableIndex> struct IDMacroHelper {\n\tstatic constexpr RTLIL::StaticIdString eval(IDMacroHelperFunc) {\n\t\treturn IdTable[IdTableIndex].static_id;\n\t}\n};\ntemplate <> struct IDMacroHelper<-1> {\n\tstatic constexpr const RTLIL::IdString &eval(IDMacroHelperFunc func) {\n\t\treturn func();\n\t}\n};\n\n#define ID(_id) \\\n\t\tYOSYS_NAMESPACE_PREFIX IDMacroHelper< \\\n\t\t\t\tYOSYS_NAMESPACE_PREFIX lookup_well_known_id(#_id) \\\n\t\t>::eval([]() \\\n\t\t-> const YOSYS_NAMESPACE_PREFIX RTLIL::IdString & { \\\n\t\t\tconst char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n\t\t\tstatic const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); \\\n\t\t\treturn id; \\\n        })\n\nnamespace RTLIL {\n\textern dict<std::string, std::string> constpad;\n\n\t[[deprecated(\"Call cell->is_builtin_ff() instead\")]]\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx      (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tbacking_tag tag;\n\tunion {\n\t\tbitvectype bits_;\n\t\tstd::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() { return is_str() ? &str_ : NULL; }\n\tconst bitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tconst std::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits();\n\tstd::string& get_str();\n\tconst bitvectype& get_bits() const;\n\tconst std::string& get_str() const;\n\tstd::vector<RTLIL::State>& bits_internal();\n\tvoid bitvectorize_internal();\n\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val); // default width is 32\n\tConst(long long val, int width);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(std::vector<RTLIL::State> bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::move(bits)) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tstruct Builder\n\t{\n\t\tBuilder() {}\n\t\tBuilder(int expected_width) { bits.reserve(expected_width); }\n\t\tvoid push_back(RTLIL::State b) { bits.push_back(b); }\n\t\tint size() const { return static_cast<int>(bits.size()); }\n\t\tConst build() { return Const(std::move(bits)); }\n\tprivate:\n\t\tstd::vector<RTLIL::State> bits;\n\t};\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\t[[deprecated(\"Don't use direct access to the internal std::vector<State>, that's an implementation detail.\")]]\n\tstd::vector<RTLIL::State>& bits() { return bits_internal(); }\n\t[[deprecated(\"Don't call bitvectorize() directly, it's an implementation detail.\")]]\n\tvoid bitvectorize() const { const_cast<Const*>(this)->bitvectorize_internal(); }\n\n\tbool as_bool() const;\n\n\t// Convert the constant value to a C++ int.\n\t// NOTE: If the constant is too wide to fit in int (32 bits) this will\n\t// truncate any higher bits, potentially over/underflowing. Consider using\n\t// try_as_int, as_int_saturating, or guarding behind convertible_to_int\n\t// instead.\n\tint as_int(bool is_signed = false) const;\n\n\t// Returns true iff the constant can be converted to an int without\n\t// over/underflow.\n\tbool convertible_to_int(bool is_signed = false) const;\n\n\t// Returns the constant's value as an int if it can be represented without\n\t// over/underflow, or std::nullopt otherwise.\n\tstd::optional<int> try_as_int(bool is_signed = false) const;\n\n\t// Returns the constant's value as an int if it can be represented without\n\t// over/underflow, otherwise the max/min value for int depending on the sign.\n\tint as_int_saturating(bool is_signed = false) const;\n\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\n\tvoid append(const RTLIL::Const &other);\n\tvoid set(int i, RTLIL::State state) {\n\t\tbits_internal()[i] = state;\n\t}\n\tvoid resize(int size, RTLIL::State fill) {\n\t\tbits_internal().resize(size, fill);\n\t}\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const* parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::bidirectional_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(&c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator operator++(int) { const_iterator result(*this); ++idx; return result; }\n\t\tconst_iterator operator--(int) { const_iterator result(*this); --idx; return result; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(*parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(*parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tclass iterator {\n\tprivate:\n\t\tConst* parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tclass proxy {\n\t\tprivate:\n\t\t\tConst* parent;\n\t\t\tsize_t idx;\n\t\tpublic:\n\t\t\tproxy(Const* parent, size_t idx) : parent(parent), idx(idx) {}\n\t\t\toperator State() const { return (*parent)[idx]; }\n\t\t\tproxy& operator=(State s) { parent->set(idx, s); return *this; }\n\t\t\tproxy& operator=(const proxy& other) { parent->set(idx, (*other.parent)[other.idx]); return *this; }\n\t\t};\n\n\t\tusing iterator_category = std::bidirectional_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = proxy*;\n\t\tusing reference = proxy;\n\n\t\titerator(Const& c, size_t i) : parent(&c), idx(i) {}\n\n\t\tproxy operator*() const { return proxy(parent, idx); }\n\t\titerator& operator++() { ++idx; return *this; }\n\t\titerator& operator--() { --idx; return *this; }\n\t\titerator operator++(int) { iterator result(*this); ++idx; return result; }\n\t\titerator operator--(int) { iterator result(*this); --idx; return result; }\n\t\titerator& operator+=(int i) { idx += i; return *this; }\n\n\t\titerator operator+(int add) {\n\t\t\treturn iterator(*parent, idx + add);\n\t\t}\n\t\titerator operator-(int sub) {\n\t\t\treturn iterator(*parent, idx - sub);\n\t\t}\n\t\tint operator-(const iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\titerator begin() {\n\t\treturn iterator(*this, 0);\n\t}\n\titerator end() {\n\t\treturn iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tresize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tresize(width, empty() ? RTLIL::State::Sx : back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::NamedObject : public RTLIL::AttrObject\n{\n\tRTLIL::IdString name;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val) /*default width 32*/ : SigChunk(RTLIL::Const(val)) {}\n\tSigChunk(int val, int width) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset;        // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\tSigSpec(const SigSpec &value) = default;\n\tSigSpec(SigSpec &&value) = default;\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tSigSpec &operator=(const SigSpec &rhs) = default;\n\tSigSpec &operator=(SigSpec &&rhs) = default;\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool known_driver() const;\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_const(State state) const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\n\t// Convert the SigSpec to a C++ int, assuming all bits are constant.\n\t// NOTE: If the value is too wide to fit in int (32 bits) this will\n\t// truncate any higher bits, potentially over/underflowing. Consider using\n\t// try_as_int, as_int_saturating, or guarding behind convertible_to_int\n\t// instead.\n\tint as_int(bool is_signed = false) const;\n\n\t// Returns true iff the SigSpec is constant and can be converted to an int\n\t// without over/underflow.\n\tbool convertible_to_int(bool is_signed = false) const;\n\n\t// Returns the SigSpec's value as an int if it is a constant and can be\n\t// represented without over/underflow, or std::nullopt otherwise.\n\tstd::optional<int> try_as_int(bool is_signed = false) const;\n\n\t// Returns an all constant SigSpec's value as an int if it can be represented\n\t// without over/underflow, otherwise the max/min value for int depending on\n\t// the sign.\n\tint as_int_saturating(bool is_signed = false) const;\n\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\t// selection includes boxed modules\n\tbool selects_boxes;\n\t// selection covers full design, including boxed modules\n\tbool complete_selection;\n\t// selection covers full design, not including boxed modules\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\tRTLIL::Design *current_design;\n\n\t// create a new selection\n\tSelection(\n\t\t// should the selection cover the full design\n\t\tbool full = true,\n\t\t// should the selection include boxed modules\n\t\tbool boxes = false,\n\t\t// the design to select from\n\t\tRTLIL::Design *design = nullptr\n\t) :\n\t\tselects_boxes(boxes), complete_selection(full && boxes), full_selection(full && !boxes), current_design(design) { }\n\n\t// checks if the given module exists in the current design and is a\n\t// boxed module, warning the user if the current design is not set\n\tbool boxed_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is included in this selection\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is wholly included in this selection,\n\t// i.e. not partially selected\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given member from the given module is included in this\n\t// selection\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\t// optimizes this selection for the given design by:\n\t// - removing non-existent modules and members, any boxed modules and\n\t//   their members (if selection does not include boxes), and any\n\t//   partially selected modules with no selected members;\n\t// - marking partially selected modules as wholly selected if all\n\t//   members of that module are selected; and\n\t// - marking selection as a complete_selection if all modules in the\n\t//   given design are selected, or a full_selection if it does not\n\t//   include boxes.\n\tvoid optimize(RTLIL::Design *design);\n\n\t// checks if selection covers full design (may or may not include\n\t// boxed-modules)\n\tbool selects_all() const {\n\t\treturn full_selection || complete_selection;\n\t}\n\n\t// add whole module to this selection\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!selects_all() && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t\tif (module->get_blackbox_attribute())\n\t\t\t\tselects_boxes = true;\n\t\t}\n\t}\n\n\t// add member of module to this selection\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!selects_all() && selected_modules.count(module->name) == 0) {\n\t\t\tselected_members[module->name].insert(member->name);\n\t\t\tif (module->get_blackbox_attribute())\n\t\t\t\tselects_boxes = true;\n\t\t}\n\t}\n\n\t// checks if selection is empty\n\tbool empty() const {\n\t\treturn !selects_all() && selected_modules.empty() && selected_members.empty();\n\t}\n\n\t// clear this selection, leaving it empty\n\tvoid clear();\n\n\t// create a new selection which is empty\n\tstatic Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };\n\n\t// create a new selection with all non-boxed modules\n\tstatic Selection FullSelection(RTLIL::Design *design = nullptr) { return Selection(true, false, design); };\n\n\t// create a new selection with all modules, including boxes\n\tstatic Selection CompleteSelection(RTLIL::Design *design = nullptr) { return Selection(true, true, design); };\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module() const;\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid sort_modules();\n\tvoid check();\n\tvoid optimize();\n\n\t// checks if the given module is included in the current selection\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is wholly included in the current\n\t// selection, i.e. not partially selected\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given member from the given module is included in the\n\t// current selection\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\t// checks if the given module is included in the current selection\n\tbool selected_module(RTLIL::Module *mod) const;\n\n\t// checks if the given module is wholly included in the current\n\t// selection, i.e. not partially selected\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\t// push the given selection to the selection stack\n\tvoid push_selection(RTLIL::Selection sel);\n\t// push a new selection to the selection stack, with nothing selected\n\tvoid push_empty_selection();\n\t// push a new selection to the selection stack, with all non-boxed\n\t// modules selected\n\tvoid push_full_selection();\n\t// push a new selection to the selection stack, with all modules\n\t// selected including boxes\n\tvoid push_complete_selection();\n\t// pop the current selection from the stack, returning to a full\n\t// selection (no boxes) if the stack is empty\n\tvoid pop_selection();\n\n\t// get the current selection\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\t// get the current selection\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\t// is the current selection a full selection (no boxes)\n\tbool full_selection() const {\n\t\treturn selection().full_selection;\n\t}\n\n\t// is the given module in the current selection\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\t// is the given member of the given module in the current selection\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\t// add whole module to the current selection\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tRTLIL::Selection &sel = selection();\n\t\tsel.select(module);\n\t}\n\n\t// add member of module to the current selection\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tRTLIL::Selection &sel = selection();\n\t\tsel.select(module, member);\n\t}\n\n\n\t// returns all selected modules\n\tstd::vector<RTLIL::Module*> selected_modules(\n\t\t// controls if partially selected modules are included\n\t\tRTLIL::SelectPartials partials = SELECT_ALL,\n\t\t// controls if boxed modules are included\n\t\tRTLIL::SelectBoxes boxes = SB_UNBOXED_WARN\n\t) const;\n\n\t// returns all selected modules, and may include boxes\n\tstd::vector<RTLIL::Module*> all_selected_modules() const { return selected_modules(SELECT_ALL, SB_ALL); }\n\t// returns all selected unboxed modules, silently ignoring any boxed\n\t// modules in the selection\n\tstd::vector<RTLIL::Module*> selected_unboxed_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_ONLY); }\n\t// returns all selected unboxed modules, warning the user if any boxed\n\t// modules have been ignored\n\tstd::vector<RTLIL::Module*> selected_unboxed_modules_warn() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }\n\n\t[[deprecated(\"Use select_unboxed_whole_modules() to maintain prior behaviour, or consider one of the other selected whole module helpers.\")]]\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_WARN); }\n\t// returns all selected whole modules, silently ignoring partially\n\t// selected modules, and may include boxes\n\tstd::vector<RTLIL::Module*> all_selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_ALL); }\n\t// returns all selected whole modules, warning the user if any partially\n\t// selected or boxed modules have been ignored; optionally includes\n\t// selected whole modules with the 'whitebox' attribute\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(\n\t\t// should whole modules with the 'whitebox' attribute be\n\t\t// included\n\t\tbool include_wb = false\n\t) const { return selected_modules(SELECT_WHOLE_WARN, include_wb ? SB_EXCL_BB_WARN : SB_UNBOXED_WARN); }\n\t// returns all selected unboxed whole modules, silently ignoring\n\t// partially selected or boxed modules\n\tstd::vector<RTLIL::Module*> selected_unboxed_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_ONLY); }\n\t// returns all selected unboxed whole modules, warning the user if any\n\t// partially selected or boxed modules have been ignored\n\tstd::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig>   connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<RTLIL::Cell *> buf_norm_cell_queue;\n\tpool<pair<RTLIL::Cell *, RTLIL::IdString>> buf_norm_cell_port_queue;\n\tpool<RTLIL::Wire *> buf_norm_wire_queue;\n\tpool<RTLIL::Cell *> pending_deleted_cells;\n\tdict<RTLIL::Wire *, pool<RTLIL::Cell *>> buf_norm_connect_index;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tbool is_selected() const;\n\tbool is_selected_whole() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\tstd::vector<RTLIL::Memory*> selected_memories() const;\n\tstd::vector<RTLIL::Process*> selected_processes() const;\n\tstd::vector<RTLIL::NamedObject*> selected_members() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tbool known_driver() const { return driverCell_ != nullptr; }\n\n\tRTLIL::Cell *driverCell() const    { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n\tint from_hdl_index(int hdl_index) {\n\t\tint zero_index = hdl_index - start_offset;\n\t\tint rtlil_index = upto ? width - 1 - zero_index : zero_index;\n\t\treturn rtlil_index >= 0 && rtlil_index < width ? rtlil_index : INT_MIN;\n\t}\n\n\tint to_hdl_index(int rtlil_index) {\n\t\tif (rtlil_index < 0 || rtlil_index >= width)\n\t\t\treturn INT_MIN;\n\t\tint zero_index = upto ? width - 1 - rtlil_index : rtlil_index;\n\t\treturn zero_index + start_offset;\n\t}\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\tPortDir port_dir(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n\tbool is_builtin_ff() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "rtlil.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\n#include <string_view>\n#include <unordered_map>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5  // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7  // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE   = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2,  // only used for parameters\n\t\tCONST_FLAG_REAL   = 4   // only used for parameters\n\t};\n\n\tenum SelectPartials : unsigned char {\n\t\tSELECT_ALL = 0,          // include partial modules\n\t\tSELECT_WHOLE_ONLY = 1,   // ignore partial modules\n\t\tSELECT_WHOLE_WARN = 2,   // call log_warning on partial module\n\t\tSELECT_WHOLE_ERR = 3,    // call log_error on partial module\n\t\tSELECT_WHOLE_CMDERR = 4  // call log_cmd_error on partial module\n\t};\n\n\tenum SelectBoxes : unsigned char {\n\t\tSB_ALL = 0,            // include boxed modules\n\t\tSB_WARN = 1,           // helper for log_warning (not for direct use)\n\t\tSB_ERR = 2,            // helper for log_error (not for direct use)\n\t\tSB_CMDERR = 3,         // helper for log_cmd_error (not for direct use)\n\t\tSB_UNBOXED_ONLY = 4,   // ignore boxed modules\n\t\tSB_UNBOXED_WARN = 5,   // call log_warning on boxed module\n\t\tSB_UNBOXED_ERR = 6,    // call log_error on boxed module\n\t\tSB_UNBOXED_CMDERR = 7, // call log_cmd_error on boxed module\n\t\tSB_INCL_WB = 8,        // helper for white boxes (not for direct use)\n\t\tSB_EXCL_BB_ONLY = 12,  // ignore black boxes, but not white boxes\n\t\tSB_EXCL_BB_WARN = 13,  // call log_warning on black boxed module\n\t\tSB_EXCL_BB_ERR = 14,   // call log_error on black boxed module\n\t\tSB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module\n\t};\n\n\tenum class StaticId : short {\n\t\tSTATIC_ID_BEGIN = 0,\n#define X(N) N,\n#include \"kernel/constids.inc\"\n#undef X\n\t\tSTATIC_ID_END,\n\t};\n\n\tenum PortDir : unsigned char  {\n\t\tPD_UNKNOWN = 0,\n\t\tPD_INPUT = 1,\n\t\tPD_OUTPUT = 2,\n\t\tPD_INOUT = 3\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct NamedObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\tstruct StaticIdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct StaticIdString {\n\t\tconstexpr StaticIdString(StaticId id, const IdString &id_str) : id_str(id_str), id(id) {}\n\t\tconstexpr inline operator const IdString &() const { return id_str; }\n\t\tconstexpr inline int index() const { return static_cast<short>(id); }\n\t\tconstexpr inline const IdString &id_string() const { return id_str; }\n\n\t\tconst IdString &id_str;\n\t\tconst StaticId id;\n\t};\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic std::unordered_map<std::string_view, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\t// For prepopulated IdStrings, the refcount is meaningless since they\n\t// are never freed even if the refcount is zero. For code efficiency\n\t// we increment the refcount of prepopulated IdStrings like any other string,\n\t// but we never decrement the refcount or check whether it's zero.\n\t// So, make this unsigned because refcounts of preopulated IdStrings may overflow\n\t// and overflow of signed integers is undefined behavior.\n\tstatic std::vector<uint32_t> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %u)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace && idx >= static_cast<short>(StaticId::STATIC_ID_END))\n\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\treturn get_reference(std::string_view(p));\n\t}\n\n\tstatic int get_reference(std::string_view p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tauto it = global_id_index_.find(p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tensure_prepopulated();\n\n\t\tif (p.empty())\n\t\t\treturn 0;\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tfor (char ch : p)\n\t\t\tif ((unsigned)ch <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", ch, std::string(p).c_str());\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tchar* buf = static_cast<char*>(malloc(p.size() + 1));\n\t\tmemcpy(buf, p.data(), p.size());\n\t\tbuf[p.size()] = 0;\n\t\tglobal_id_storage_.at(idx) = buf;\n\t\tglobal_id_index_.insert(it, {std::string_view(buf, p.size()), idx});\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (idx < static_cast<short>(StaticId::STATIC_ID_END) || !destruct_guard_ok)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %u)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tuint32_t &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\t\tlog_assert(idx >= static_cast<short>(StaticId::STATIC_ID_END));\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(std::string_view(str))) { }\n\tinline IdString(std::string_view str) : index_(get_reference(str)) { }\n\tinline IdString(StaticId id) : index_(static_cast<short>(id)) {}\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(IdString &&rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = rhs.index_;\n\t\trhs.index_ = 0;\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tconstexpr inline const IdString &id_string() const { return *this; }\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\tinline bool operator==(const StaticIdString &rhs) const;\n\tinline bool operator!=(const StaticIdString &rhs) const;\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn index_ == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(const Args &... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const StaticIdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\nprivate:\n\tstatic void prepopulate();\n\npublic:\n\tstatic void ensure_prepopulated() {\n\t\tif (global_id_index_.empty())\n\t\t\tprepopulate();\n\t}\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString &id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString &id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\ninline bool RTLIL::IdString::operator==(const RTLIL::StaticIdString &rhs) const {\n\treturn index_ == rhs.index();\n}\ninline bool RTLIL::IdString::operator!=(const RTLIL::StaticIdString &rhs) const {\n\treturn index_ != rhs.index();\n}\n\nnamespace RTLIL {\n\tnamespace IDInternal {\n#define X(_id) extern const IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t}\n\tnamespace ID {\n#define X(_id) constexpr StaticIdString _id(StaticId::_id, IDInternal::_id);\n#include \"kernel/constids.inc\"\n#undef X\n\t}\n}\n\nstruct IdTableEntry {\n\tconst std::string_view name;\n\tconst RTLIL::StaticIdString static_id;\n};\n\nconstexpr IdTableEntry IdTable[] = {\n#define X(_id) {#_id, ID::_id},\n#include \"kernel/constids.inc\"\n#undef X\n};\n\nconstexpr int lookup_well_known_id(std::string_view name)\n{\n\tint low = 0;\n\tint high = sizeof(IdTable) / sizeof(IdTable[0]);\n\twhile (high - low >= 2) {\n\t\tint mid = (low + high) / 2;\n\t\tif (name < IdTable[mid].name)\n\t\t\thigh = mid;\n\t\telse\n\t\t\tlow = mid;\n\t}\n\tif (IdTable[low].name == name)\n\t\treturn low;\n\treturn -1;\n}\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n//  sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\ntypedef const RTLIL::IdString &IDMacroHelperFunc();\n\ntemplate <int IdTableIndex> struct IDMacroHelper {\n\tstatic constexpr RTLIL::StaticIdString eval(IDMacroHelperFunc) {\n\t\treturn IdTable[IdTableIndex].static_id;\n\t}\n};\ntemplate <> struct IDMacroHelper<-1> {\n\tstatic constexpr const RTLIL::IdString &eval(IDMacroHelperFunc func) {\n\t\treturn func();\n\t}\n};\n\n#define ID(_id) \\\n\t\tYOSYS_NAMESPACE_PREFIX IDMacroHelper< \\\n\t\t\t\tYOSYS_NAMESPACE_PREFIX lookup_well_known_id(#_id) \\\n\t\t>::eval([]() \\\n\t\t-> const YOSYS_NAMESPACE_PREFIX RTLIL::IdString & { \\\n\t\t\tconst char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n\t\t\tstatic const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); \\\n\t\t\treturn id; \\\n        })\n\nnamespace RTLIL {\n\textern dict<std::string, std::string> constpad;\n\n\t[[deprecated(\"Call cell->is_builtin_ff() instead\")]]\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx      (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tbacking_tag tag;\n\tunion {\n\t\tbitvectype bits_;\n\t\tstd::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() { return is_str() ? &str_ : NULL; }\n\tconst bitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tconst std::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits();\n\tstd::string& get_str();\n\tconst bitvectype& get_bits() const;\n\tconst std::string& get_str() const;\n\tstd::vector<RTLIL::State>& bits_internal();\n\tvoid bitvectorize_internal();\n\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(std::string str);\n\tConst(long long val); // default width is 32\n\tConst(long long val, int width);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(std::vector<RTLIL::State> bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::move(bits)) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tstruct Builder\n\t{\n\t\tBuilder() {}\n\t\tBuilder(int expected_width) { bits.reserve(expected_width); }\n\t\tvoid push_back(RTLIL::State b) { bits.push_back(b); }\n\t\tint size() const { return static_cast<int>(bits.size()); }\n\t\tConst build() { return Const(std::move(bits)); }\n\tprivate:\n\t\tstd::vector<RTLIL::State> bits;\n\t};\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\t[[deprecated(\"Don't use direct access to the internal std::vector<State>, that's an implementation detail.\")]]\n\tstd::vector<RTLIL::State>& bits() { return bits_internal(); }\n\t[[deprecated(\"Don't call bitvectorize() directly, it's an implementation detail.\")]]\n\tvoid bitvectorize() const { const_cast<Const*>(this)->bitvectorize_internal(); }\n\n\tbool as_bool() const;\n\n\t// Convert the constant value to a C++ int.\n\t// NOTE: If the constant is too wide to fit in int (32 bits) this will\n\t// truncate any higher bits, potentially over/underflowing. Consider using\n\t// try_as_int, as_int_saturating, or guarding behind convertible_to_int\n\t// instead.\n\tint as_int(bool is_signed = false) const;\n\n\t// Returns true iff the constant can be converted to an int without\n\t// over/underflow.\n\tbool convertible_to_int(bool is_signed = false) const;\n\n\t// Returns the constant's value as an int if it can be represented without\n\t// over/underflow, or std::nullopt otherwise.\n\tstd::optional<int> try_as_int(bool is_signed = false) const;\n\n\t// Returns the constant's value as an int if it can be represented without\n\t// over/underflow, otherwise the max/min value for int depending on the sign.\n\tint as_int_saturating(bool is_signed = false) const;\n\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\n\tvoid append(const RTLIL::Const &other);\n\tvoid set(int i, RTLIL::State state) {\n\t\tbits_internal()[i] = state;\n\t}\n\tvoid resize(int size, RTLIL::State fill) {\n\t\tbits_internal().resize(size, fill);\n\t}\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const* parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::bidirectional_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(&c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator operator++(int) { const_iterator result(*this); ++idx; return result; }\n\t\tconst_iterator operator--(int) { const_iterator result(*this); --idx; return result; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(*parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(*parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tclass iterator {\n\tprivate:\n\t\tConst* parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tclass proxy {\n\t\tprivate:\n\t\t\tConst* parent;\n\t\t\tsize_t idx;\n\t\tpublic:\n\t\t\tproxy(Const* parent, size_t idx) : parent(parent), idx(idx) {}\n\t\t\toperator State() const { return (*parent)[idx]; }\n\t\t\tproxy& operator=(State s) { parent->set(idx, s); return *this; }\n\t\t\tproxy& operator=(const proxy& other) { parent->set(idx, (*other.parent)[other.idx]); return *this; }\n\t\t};\n\n\t\tusing iterator_category = std::bidirectional_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = proxy*;\n\t\tusing reference = proxy;\n\n\t\titerator(Const& c, size_t i) : parent(&c), idx(i) {}\n\n\t\tproxy operator*() const { return proxy(parent, idx); }\n\t\titerator& operator++() { ++idx; return *this; }\n\t\titerator& operator--() { --idx; return *this; }\n\t\titerator operator++(int) { iterator result(*this); ++idx; return result; }\n\t\titerator operator--(int) { iterator result(*this); --idx; return result; }\n\t\titerator& operator+=(int i) { idx += i; return *this; }\n\n\t\titerator operator+(int add) {\n\t\t\treturn iterator(*parent, idx + add);\n\t\t}\n\t\titerator operator-(int sub) {\n\t\t\treturn iterator(*parent, idx - sub);\n\t\t}\n\t\tint operator-(const iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\titerator begin() {\n\t\treturn iterator(*this, 0);\n\t}\n\titerator end() {\n\t\treturn iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tresize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tresize(width, empty() ? RTLIL::State::Sx : back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::NamedObject : public RTLIL::AttrObject\n{\n\tRTLIL::IdString name;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val) /*default width 32*/ : SigChunk(RTLIL::Const(val)) {}\n\tSigChunk(int val, int width) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset;        // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\tSigSpec(const SigSpec &value) = default;\n\tSigSpec(SigSpec &&value) = default;\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tSigSpec &operator=(const SigSpec &rhs) = default;\n\tSigSpec &operator=(SigSpec &&rhs) = default;\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool known_driver() const;\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_const(State state) const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\n\t// Convert the SigSpec to a C++ int, assuming all bits are constant.\n\t// NOTE: If the value is too wide to fit in int (32 bits) this will\n\t// truncate any higher bits, potentially over/underflowing. Consider using\n\t// try_as_int, as_int_saturating, or guarding behind convertible_to_int\n\t// instead.\n\tint as_int(bool is_signed = false) const;\n\n\t// Returns true iff the SigSpec is constant and can be converted to an int\n\t// without over/underflow.\n\tbool convertible_to_int(bool is_signed = false) const;\n\n\t// Returns the SigSpec's value as an int if it is a constant and can be\n\t// represented without over/underflow, or std::nullopt otherwise.\n\tstd::optional<int> try_as_int(bool is_signed = false) const;\n\n\t// Returns an all constant SigSpec's value as an int if it can be represented\n\t// without over/underflow, otherwise the max/min value for int depending on\n\t// the sign.\n\tint as_int_saturating(bool is_signed = false) const;\n\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\t// selection includes boxed modules\n\tbool selects_boxes;\n\t// selection covers full design, including boxed modules\n\tbool complete_selection;\n\t// selection covers full design, not including boxed modules\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\tRTLIL::Design *current_design;\n\n\t// create a new selection\n\tSelection(\n\t\t// should the selection cover the full design\n\t\tbool full = true,\n\t\t// should the selection include boxed modules\n\t\tbool boxes = false,\n\t\t// the design to select from\n\t\tRTLIL::Design *design = nullptr\n\t) :\n\t\tselects_boxes(boxes), complete_selection(full && boxes), full_selection(full && !boxes), current_design(design) { }\n\n\t// checks if the given module exists in the current design and is a\n\t// boxed module, warning the user if the current design is not set\n\tbool boxed_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is included in this selection\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is wholly included in this selection,\n\t// i.e. not partially selected\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given member from the given module is included in this\n\t// selection\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\t// optimizes this selection for the given design by:\n\t// - removing non-existent modules and members, any boxed modules and\n\t//   their members (if selection does not include boxes), and any\n\t//   partially selected modules with no selected members;\n\t// - marking partially selected modules as wholly selected if all\n\t//   members of that module are selected; and\n\t// - marking selection as a complete_selection if all modules in the\n\t//   given design are selected, or a full_selection if it does not\n\t//   include boxes.\n\tvoid optimize(RTLIL::Design *design);\n\n\t// checks if selection covers full design (may or may not include\n\t// boxed-modules)\n\tbool selects_all() const {\n\t\treturn full_selection || complete_selection;\n\t}\n\n\t// add whole module to this selection\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!selects_all() && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t\tif (module->get_blackbox_attribute())\n\t\t\t\tselects_boxes = true;\n\t\t}\n\t}\n\n\t// add member of module to this selection\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!selects_all() && selected_modules.count(module->name) == 0) {\n\t\t\tselected_members[module->name].insert(member->name);\n\t\t\tif (module->get_blackbox_attribute())\n\t\t\t\tselects_boxes = true;\n\t\t}\n\t}\n\n\t// checks if selection is empty\n\tbool empty() const {\n\t\treturn !selects_all() && selected_modules.empty() && selected_members.empty();\n\t}\n\n\t// clear this selection, leaving it empty\n\tvoid clear();\n\n\t// create a new selection which is empty\n\tstatic Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };\n\n\t// create a new selection with all non-boxed modules\n\tstatic Selection FullSelection(RTLIL::Design *design = nullptr) { return Selection(true, false, design); };\n\n\t// create a new selection with all modules, including boxes\n\tstatic Selection CompleteSelection(RTLIL::Design *design = nullptr) { return Selection(true, true, design); };\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module() const;\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid sort_modules();\n\tvoid check();\n\tvoid optimize();\n\n\t// checks if the given module is included in the current selection\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is wholly included in the current\n\t// selection, i.e. not partially selected\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given member from the given module is included in the\n\t// current selection\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\t// checks if the given module is included in the current selection\n\tbool selected_module(RTLIL::Module *mod) const;\n\n\t// checks if the given module is wholly included in the current\n\t// selection, i.e. not partially selected\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\t// push the given selection to the selection stack\n\tvoid push_selection(RTLIL::Selection sel);\n\t// push a new selection to the selection stack, with nothing selected\n\tvoid push_empty_selection();\n\t// push a new selection to the selection stack, with all non-boxed\n\t// modules selected\n\tvoid push_full_selection();\n\t// push a new selection to the selection stack, with all modules\n\t// selected including boxes\n\tvoid push_complete_selection();\n\t// pop the current selection from the stack, returning to a full\n\t// selection (no boxes) if the stack is empty\n\tvoid pop_selection();\n\n\t// get the current selection\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\t// get the current selection\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\t// is the current selection a full selection (no boxes)\n\tbool full_selection() const {\n\t\treturn selection().full_selection;\n\t}\n\n\t// is the given module in the current selection\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\t// is the given member of the given module in the current selection\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\t// add whole module to the current selection\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tRTLIL::Selection &sel = selection();\n\t\tsel.select(module);\n\t}\n\n\t// add member of module to the current selection\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tRTLIL::Selection &sel = selection();\n\t\tsel.select(module, member);\n\t}\n\n\n\t// returns all selected modules\n\tstd::vector<RTLIL::Module*> selected_modules(\n\t\t// controls if partially selected modules are included\n\t\tRTLIL::SelectPartials partials = SELECT_ALL,\n\t\t// controls if boxed modules are included\n\t\tRTLIL::SelectBoxes boxes = SB_UNBOXED_WARN\n\t) const;\n\n\t// returns all selected modules, and may include boxes\n\tstd::vector<RTLIL::Module*> all_selected_modules() const { return selected_modules(SELECT_ALL, SB_ALL); }\n\t// returns all selected unboxed modules, silently ignoring any boxed\n\t// modules in the selection\n\tstd::vector<RTLIL::Module*> selected_unboxed_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_ONLY); }\n\t// returns all selected unboxed modules, warning the user if any boxed\n\t// modules have been ignored\n\tstd::vector<RTLIL::Module*> selected_unboxed_modules_warn() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }\n\n\t[[deprecated(\"Use select_unboxed_whole_modules() to maintain prior behaviour, or consider one of the other selected whole module helpers.\")]]\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_WARN); }\n\t// returns all selected whole modules, silently ignoring partially\n\t// selected modules, and may include boxes\n\tstd::vector<RTLIL::Module*> all_selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_ALL); }\n\t// returns all selected whole modules, warning the user if any partially\n\t// selected or boxed modules have been ignored; optionally includes\n\t// selected whole modules with the 'whitebox' attribute\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(\n\t\t// should whole modules with the 'whitebox' attribute be\n\t\t// included\n\t\tbool include_wb = false\n\t) const { return selected_modules(SELECT_WHOLE_WARN, include_wb ? SB_EXCL_BB_WARN : SB_UNBOXED_WARN); }\n\t// returns all selected unboxed whole modules, silently ignoring\n\t// partially selected or boxed modules\n\tstd::vector<RTLIL::Module*> selected_unboxed_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_ONLY); }\n\t// returns all selected unboxed whole modules, warning the user if any\n\t// partially selected or boxed modules have been ignored\n\tstd::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }\n#ifdef YOSYS_ENABLE_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig>   connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<RTLIL::Cell *> buf_norm_cell_queue;\n\tpool<pair<RTLIL::Cell *, RTLIL::IdString>> buf_norm_cell_port_queue;\n\tpool<RTLIL::Wire *> buf_norm_wire_queue;\n\tpool<RTLIL::Cell *> pending_deleted_cells;\n\tdict<RTLIL::Wire *, pool<RTLIL::Cell *>> buf_norm_connect_index;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tbool is_selected() const;\n\tbool is_selected_whole() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\tstd::vector<RTLIL::Memory*> selected_memories() const;\n\tstd::vector<RTLIL::Process*> selected_processes() const;\n\tstd::vector<RTLIL::NamedObject*> selected_members() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef YOSYS_ENABLE_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tbool known_driver() const { return driverCell_ != nullptr; }\n\n\tRTLIL::Cell *driverCell() const    { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n\tint from_hdl_index(int hdl_index) {\n\t\tint zero_index = hdl_index - start_offset;\n\t\tint rtlil_index = upto ? width - 1 - zero_index : zero_index;\n\t\treturn rtlil_index >= 0 && rtlil_index < width ? rtlil_index : INT_MIN;\n\t}\n\n\tint to_hdl_index(int rtlil_index) {\n\t\tif (rtlil_index < 0 || rtlil_index >= width)\n\t\t\treturn INT_MIN;\n\t\tint zero_index = upto ? width - 1 - rtlil_index : rtlil_index;\n\t\treturn zero_index + start_offset;\n\t}\n\n#ifdef YOSYS_ENABLE_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tint width, start_offset, size;\n#ifdef YOSYS_ENABLE_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\tPortDir port_dir(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef YOSYS_ENABLE_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n\tbool is_builtin_ff() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "satgen.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tconst SigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, const SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(const SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string wire_name = RTLIL::unescape_id(bit.wire->name);\n\t\t\t\tstd::string name = pf +\n\t\t\t\t\t(bit.wire->width == 1 ? wire_name : stringf(\"%s [%d]\", wire_name, bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "scopeinfo.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const\n\t\t{\n\t\t\th.eat(scope_name);\n\t\t\th.eat(target);\n\t\t\treturn h;\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(ptr); return h; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty() && object->name.isPublic())\n\t\tpath.push_back(object->name);\n\tif (!path.empty() && !(object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\"))) {\n\t\tpath.pop_back();\n\t\tpath.push_back(object->name);\n\t}\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\")) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else if (object->has_attribute(ID::hdlname)) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "sexpr.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SEXPR_H\n#define SEXPR_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nclass SExpr {\npublic:\n\tstd::variant<std::vector<SExpr>, std::string> _v;\npublic:\n\tSExpr(std::string a) : _v(std::move(a)) {}\n    SExpr(const char *a) : _v(a) {}\n    // FIXME: should maybe be defined for all integral types\n\tSExpr(int n) : _v(std::to_string(n)) {}\n\tSExpr(std::vector<SExpr> const &l) : _v(l) {}\n\tSExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}\n    // It would be nicer to have an std::initializer_list constructor,\n    // but that causes confusing issues with overload resolution sometimes.\n    template<typename... Args> static SExpr list(Args&&... args) {\n\t    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n    }\n    bool is_atom() const { return std::holds_alternative<std::string>(_v); }\n    std::string const &atom() const { return std::get<std::string>(_v); }\n    bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }\n    std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }\n\tstd::string to_string() const;\n};\n\nstd::ostream &operator<<(std::ostream &os, SExpr const &sexpr);\n\nnamespace SExprUtil {\n    // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list`\n    template<typename... Args> SExpr list(Args&&... args) {\n\t    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n    }\n}\n\n// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout.\nclass SExprWriter {\n    std::ostream &os;\n    int _max_line_width;\n    int _indent = 0;\n    int _pos = 0;\n    // If _pending_nl is set, print a newline before the next character.\n    // This lets us \"undo\" the last newline so we can put\n    // closing parentheses or a hanging comment on the same line.\n    bool _pending_nl = false;\n    // Unclosed parentheses (boolean stored is indent_rest)\n\tvector<bool> _unclosed;\n    // Used only for push() and pop() (stores _unclosed.size())\n\tvector<size_t> _unclosed_stack;\n\tvoid nl_if_pending();\n    void puts(std::string_view s);\n    int check_fit(SExpr const &sexpr, int space);\n    void print(SExpr const &sexpr, bool close = true, bool indent_rest = true);\npublic:\n    SExprWriter(std::ostream &os, int max_line_width = 80)\n        : os(os)\n        , _max_line_width(max_line_width)\n    {}\n    // Print an s-expr.\n    SExprWriter &operator <<(SExpr const &sexpr) {\n        print(sexpr);\n        _pending_nl = true;\n        return *this;\n    }\n    // Print an s-expr (which must be a list), but leave room for extra elements\n    // which may be printed using either << or further calls to open.\n    // If indent_rest = false, the remaining elements are not intended\n    // (for avoiding unreasonable indentation on deeply nested structures).\n    void open(SExpr const &sexpr, bool indent_rest = true) {\n        log_assert(sexpr.is_list());\n        print(sexpr, false, indent_rest);\n    }\n    // Close the s-expr opened with the last call to open\n    // (if an argument is given, close that many s-exprs).\n    void close(size_t n = 1);\n    // push() remembers how many s-exprs are currently open\n\tvoid push() {\n\t\t_unclosed_stack.push_back(_unclosed.size());\n\t}\n    // pop() closes all s-expr opened since the corresponding call to push()\n\tvoid pop() {\n\t\tauto t = _unclosed_stack.back();\n\t\tlog_assert(_unclosed.size() >= t);\n\t\tclose(_unclosed.size() - t);\n\t\t_unclosed_stack.pop_back();\n\t}\n    // Print a comment.\n    // If hanging = true, append it to the end of the last printed s-expr.\n\tvoid comment(std::string const &str, bool hanging = false);\n    // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses.\n    void flush() {\n        nl_if_pending();\n    }\n    // Destructor closes any unclosed parentheses and flushes.\n    ~SExprWriter();\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
@@ -190,8 +184,8 @@ export const filesystem = {
                 "threading.h": "#include <deque>\n\n#ifdef YOSYS_ENABLE_THREADS\n#include <condition_variable>\n#include <mutex>\n#include <thread>\n#endif\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/log.h\"\n\n#ifndef YOSYS_THREADING_H\n#define YOSYS_THREADING_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// Concurrent queue implementation. Not fast, but simple.\n// Multi-producer, multi-consumer, optionally bounded.\n// When YOSYS_ENABLE_THREADS is not defined, this is just a non-thread-safe non-blocking deque.\ntemplate <typename T>\nclass ConcurrentQueue\n{\npublic:\n\tConcurrentQueue(int capacity = INT_MAX)\n\t\t: capacity(capacity) {}\n\t// Push an element into the queue. If it's at capacity, block until there is room.\n\tvoid push_back(T t)\n\t{\n#ifdef YOSYS_ENABLE_THREADS\n\t\tstd::unique_lock<std::mutex> lock(mutex);\n\t\tnot_full_condition.wait(lock, [this] { return static_cast<int>(contents.size()) < capacity; });\n\t\tif (contents.empty())\n\t\t\tnot_empty_condition.notify_one();\n#endif\n\t\tlog_assert(!closed);\n\t\tcontents.push_back(std::move(t));\n#ifdef YOSYS_ENABLE_THREADS\n\t\tif (static_cast<int>(contents.size()) < capacity)\n\t\t\tnot_full_condition.notify_one();\n#endif\n\t}\n\t// Signal that no more elements will be produced. `pop_front()` will return nullopt.\n\tvoid close()\n\t{\n#ifdef YOSYS_ENABLE_THREADS\n\t\tstd::unique_lock<std::mutex> lock(mutex);\n\t\tnot_empty_condition.notify_all();\n#endif\n\t\tclosed = true;\n\t}\n\t// Pop an element from the queue. Blocks until an element is available\n\t// or the queue is closed and empty.\n\tstd::optional<T> pop_front()\n\t{\n\t\treturn pop_front_internal(true);\n\t}\n\t// Pop an element from the queue. Does not block, just returns nullopt if the\n\t// queue is empty.\n\tstd::optional<T> try_pop_front()\n\t{\n\t\treturn pop_front_internal(false);\n\t}\nprivate:\n#ifdef YOSYS_ENABLE_THREADS\n\tstd::optional<T> pop_front_internal(bool wait)\n\t{\n\t\tstd::unique_lock<std::mutex> lock(mutex);\n\t\tif (wait) {\n\t\t\tnot_empty_condition.wait(lock, [this] { return !contents.empty() || closed; });\n\t\t}\n#else\n\tstd::optional<T> pop_front_internal(bool)\n\t{\n#endif\n\t\tif (contents.empty())\n\t\t\treturn std::nullopt;\n#ifdef YOSYS_ENABLE_THREADS\n\t\tif (static_cast<int>(contents.size()) == capacity)\n\t\t\tnot_full_condition.notify_one();\n#endif\n\t\tT result = std::move(contents.front());\n\t\tcontents.pop_front();\n#ifdef YOSYS_ENABLE_THREADS\n\t\tif (!contents.empty())\n\t\t\tnot_empty_condition.notify_one();\n#endif\n\t\treturn std::move(result);\n\t}\n\n#ifdef YOSYS_ENABLE_THREADS\n\tstd::mutex mutex;\n\t// Signals one waiter thread when the queue changes and is not full.\n\tstd::condition_variable not_full_condition;\n\t// Signals one waiter thread when the queue changes and is not empty.\n\tstd::condition_variable not_empty_condition;\n#endif\n\tstd::deque<T> contents;\n\tint capacity;\n\tbool closed = false;\n};\n\nclass DeferredLogs\n{\npublic:\n\ttemplate <typename... Args>\n\tvoid log(FmtString<TypeIdentity<Args>...> fmt, Args... args)\n\t{\n\t\tlogs.push_back({fmt.format(args...), false});\n\t}\n\ttemplate <typename... Args>\n\tvoid log_error(FmtString<TypeIdentity<Args>...> fmt, Args... args)\n\t{\n\t\tlogs.push_back({fmt.format(args...), true});\n\t}\n\tvoid flush();\nprivate:\n\tstruct Message\n\t{\n\t\tstd::string text;\n\t\tbool error;\n\t};\n\tstd::vector<Message> logs;\n};\n\nclass ThreadPool\n{\npublic:\n\t// Computes the number of worker threads to use.\n\t// `reserved_cores` cores are set aside for other threads (e.g. work on the main thread).\n\t// `max_threads` --- don't return more workers than this.\n\t// The result may be 0.\n\tstatic int pool_size(int reserved_cores, int max_threads);\n\n\t// Create a pool of threads running the given closure (parameterized by thread number).\n\t// `pool_size` must be the result of a `pool_size()` call.\n\tThreadPool(int pool_size, std::function<void(int)> b);\n\tThreadPool(ThreadPool &&other) = delete;\n\t// Waits for all threads to terminate. Make sure those closures return!\n\t~ThreadPool();\n\n\t// Return the number of threads in the pool.\n\tint num_threads() const\n\t{\n#ifdef YOSYS_ENABLE_THREADS\n\t\treturn threads.size();\n#else\n\t\treturn 0;\n#endif\n\t}\nprivate:\n\tstd::function<void(int)> body;\n#ifdef YOSYS_ENABLE_THREADS\n\tstd::vector<std::thread> threads;\n#endif\n};\n\ntemplate <class T>\nclass ConcurrentStack\n{\npublic:\n\tvoid push_back(T &&t) {\n#ifdef YOSYS_ENABLE_THREADS\n\t\tstd::lock_guard<std::mutex> lock(mutex);\n#endif\n\t\tcontents.push_back(std::move(t));\n\t}\n\tstd::optional<T> try_pop_back() {\n#ifdef YOSYS_ENABLE_THREADS\n\t\tstd::lock_guard<std::mutex> lock(mutex);\n#endif\n\t\tif (contents.empty())\n\t\t\treturn std::nullopt;\n\t\tT result = std::move(contents.back());\n\t\tcontents.pop_back();\n\t\treturn result;\n\t}\nprivate:\n#ifdef YOSYS_ENABLE_THREADS\n\tstd::mutex mutex;\n#endif\n\tstd::vector<T> contents;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_THREADING_H\n",
                 "timinginfo.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *            (C) 2020  Eddie Hung    <eddie@fpgeh.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tstd::optional<SigBit> get_connection(RTLIL::Cell *cell) {\n\t\t\tif (!cell->hasPort(name))\n\t\t\t\treturn {};\n\t\t\tauto &port = cell->getPort(name);\n\t\t\tif (offset >= port.size())\n\t\t\t\treturn {};\n\t\t\treturn port[offset];\n\t\t}\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(name);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(first);\n\t\t\th.eat(second);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "utils.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n#include <iterator>\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*>> backup_state;\n\tdict<Key, T> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>> class TopoSort\n{\n      public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n                IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n                        log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n                auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n                if (rv.second) {\n      \t              nodes.push_back(n);\n\t\t      edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n      private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\n// this class is used for implementing operator-> on iterators that return values rather than references\n// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained\ntemplate<class T>\nstruct arrow_proxy {\n\tT v;\n\texplicit arrow_proxy(T const & v) : v(v) {}\n\tT* operator->() { return &v; }\n};\n\ninline int ceil_log2(int x)\n{\n#if defined(__GNUC__)\n        return x > 1 ? (8*sizeof(int)) - __builtin_clz(x-1) : 0;\n#else\n\tif (x <= 0)\n\t\treturn 0;\n\tfor (int i = 0; i < 32; i++)\n\t\tif (((x-1) >> i) == 0)\n\t\t\treturn i;\n\tlog_abort();\n#endif\n}\n\ntemplate <typename T>\nauto reversed(const T& container) {\n    struct reverse_view {\n        const T& cont;\n        auto begin() const { return cont.rbegin(); }\n        auto end() const { return cont.rend(); }\n    };\n    return reverse_view{container};\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "yosys.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision!  ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\n#ifdef YOSYS_ENABLE_TCL\nstruct Tcl_Interp;\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\nconst char* yosys_maybe_version();\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "yosys_common.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <array>\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n#  error It looks like you are trying to build Yosys without the config defines set. \\\n         When building Yosys with a custom make system, make sure you set all the \\\n         defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#define FRIEND_TEST(test_case_name, test_name) \\\n  friend class test_case_name##_##test_name##_Test\n\n#ifdef _WIN32\n#  undef NOMINMAX\n#  define NOMINMAX 1\n#  undef YY_NO_UNISTD_H\n#  define YY_NO_UNISTD_H 1\n\n#  include <windows.h>\n#  include <io.h>\n#  include <direct.h>\n\n#  define strtok_r strtok_s\n#  define strdup _strdup\n#  define snprintf _snprintf\n#  define getcwd _getcwd\n#  define mkdir _mkdir\n#  define popen _popen\n#  define pclose _pclose\n\n#  ifndef __MINGW32__\n#    define PATH_MAX MAX_PATH\n#    define isatty _isatty\n#    define fileno _fileno\n#  endif\n\n// The following defines conflict with our identifiers:\n#  undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n#  undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n#  define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE          Yosys\n#define PRIVATE_NAMESPACE_BEGIN  namespace {\n#define PRIVATE_NAMESPACE_END    }\n#define YOSYS_NAMESPACE_BEGIN    namespace Yosys {\n#define YOSYS_NAMESPACE_END      }\n#define YOSYS_NAMESPACE_PREFIX   Yosys::\n#define USING_YOSYS_NAMESPACE    using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n#  define YS_ATTRIBUTE(...)\n#else\n#  define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n#  define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n#  define YS_FALLTHROUGH [[fallthrough]];\n#else\n#  error \"C++17 or later compatible compiler is required\"\n#endif\n\n#if defined(__has_cpp_attribute) && __has_cpp_attribute(gnu::cold)\n#  define YS_COLD [[gnu::cold]]\n#else\n#  define YS_COLD\n#endif\n\n#ifdef __cpp_consteval\n#define YOSYS_CONSTEVAL consteval\n#else\n// If we can't use consteval we can at least make it constexpr.\n#define YOSYS_CONSTEVAL constexpr\n#endif\n\n#define YOSYS_ABORT(s) YOSYS_NAMESPACE_PREFIX log_yosys_abort_message(__FILE__, __LINE__, __FUNCTION__, s)\n\n// This has to precede including \"kernel/io.h\"\nYOSYS_NAMESPACE_BEGIN\n[[noreturn]] void log_yosys_abort_message(std::string_view file, int line, std::string_view func, std::string_view message);\nYOSYS_NAMESPACE_END\n\n#include \"kernel/io.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n#  error \"You've probably included hashlib.h under two namespace paths. Bad idea.\"\n#else\n#  include \"kernel/hashlib.h\"\n#  undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\nusing hashlib::Hasher;\nusing hashlib::run_hash;\nusing hashlib::hash_ops;\nusing hashlib::mkhash_xorshift;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(*content);\n\t\treturn h;\n\t}\n};\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n\tstruct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tnamespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\nextern bool yosys_write_versions;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\nnamespace ID = RTLIL::ID;\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "yosys.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision!  ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\n#ifdef YOSYS_ENABLE_TCL\nstruct Tcl_Interp;\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef YOSYS_ENABLE_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\nconst char* yosys_maybe_version();\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef YOSYS_ENABLE_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "yosys_common.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <array>\n#include <atomic>\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifndef _YOSYS_\n#  error It looks like you are trying to build Yosys without the config defines set. \\\n         When building Yosys with a custom make system, make sure you set all the \\\n         defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#define FRIEND_TEST(test_case_name, test_name) \\\n  friend class test_case_name##_##test_name##_Test\n\n#ifdef _WIN32\n#  undef NOMINMAX\n#  define NOMINMAX 1\n#  undef YY_NO_UNISTD_H\n#  define YY_NO_UNISTD_H 1\n\n#  include <windows.h>\n#  include <io.h>\n#  include <direct.h>\n\n#  define strtok_r strtok_s\n#  define strdup _strdup\n#  define snprintf _snprintf\n#  define getcwd _getcwd\n#  define mkdir _mkdir\n#  define popen _popen\n#  define pclose _pclose\n\n#  ifndef __MINGW32__\n#    define PATH_MAX MAX_PATH\n#    define isatty _isatty\n#    define fileno _fileno\n#  endif\n\n// The following defines conflict with our identifiers:\n#  undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n#  undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n#  define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE          Yosys\n#define PRIVATE_NAMESPACE_BEGIN  namespace {\n#define PRIVATE_NAMESPACE_END    }\n#define YOSYS_NAMESPACE_BEGIN    namespace Yosys {\n#define YOSYS_NAMESPACE_END      }\n#define YOSYS_NAMESPACE_PREFIX   Yosys::\n#define USING_YOSYS_NAMESPACE    using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n#  define YS_ATTRIBUTE(...)\n#else\n#  define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n#  define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n#  define YS_FALLTHROUGH [[fallthrough]];\n#else\n#  error \"C++17 or later compatible compiler is required\"\n#endif\n\n#if defined(__has_cpp_attribute) && __has_cpp_attribute(gnu::cold)\n#  define YS_COLD [[gnu::cold]]\n#else\n#  define YS_COLD\n#endif\n\n#ifdef __cpp_consteval\n#define YOSYS_CONSTEVAL consteval\n#else\n// If we can't use consteval we can at least make it constexpr.\n#define YOSYS_CONSTEVAL constexpr\n#endif\n\n#define YOSYS_ABORT(s) YOSYS_NAMESPACE_PREFIX log_yosys_abort_message(__FILE__, __LINE__, __FUNCTION__, s)\n\n// This has to precede including \"kernel/io.h\"\nYOSYS_NAMESPACE_BEGIN\n[[noreturn]] void log_yosys_abort_message(std::string_view file, int line, std::string_view func, std::string_view message);\nYOSYS_NAMESPACE_END\n\n#include \"kernel/io.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n#  error \"You've probably included hashlib.h under two namespace paths. Bad idea.\"\n#else\n#  include \"kernel/hashlib.h\"\n#  undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\nusing hashlib::Hasher;\nusing hashlib::run_hash;\nusing hashlib::hash_ops;\nusing hashlib::mkhash_xorshift;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(*content);\n\t\treturn h;\n\t}\n};\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n\tstruct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tnamespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\nextern bool yosys_write_versions;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\nnamespace ID = RTLIL::ID;\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "yw.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YW_H\n#define YW_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/mem.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct IdPath : public std::vector<RTLIL::IdString>\n{\n\ttemplate<typename... T>\n\tIdPath(T&&... args) : std::vector<RTLIL::IdString>(std::forward<T>(args)...) { }\n\tIdPath prefix() const { return {begin(), end() - !empty()}; }\n\tstd::string str() const;\n\n\tbool has_address() const { int tmp; return get_address(tmp); };\n\tbool get_address(int &addr) const;\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(static_cast<const std::vector<RTLIL::IdString>&&>(*this));\n\t\treturn h;\n\t}\n};\n\nstruct WitnessHierarchyItem {\n\tRTLIL::Module *module;\n\tRTLIL::Wire *wire = nullptr;\n\tRTLIL::Cell *cell = nullptr;\n\tMem *mem = nullptr;\n\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Wire *wire) : module(module), wire(wire) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, Mem *mem) : module(module), mem(mem) {}\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback);\n\ntemplate<class T> static std::vector<std::string> witness_path(T *obj) {\n\tstd::vector<std::string> path;\n\tif (obj->name.isPublic()) {\n\t\tauto hdlname = obj->get_string_attribute(ID::hdlname);\n\t\tfor (auto token : split_tokens(hdlname))\n\t\t\tpath.push_back(\"\\\\\" + token);\n\t}\n\tif (path.empty())\n\t\tpath.push_back(obj->name.str());\n\treturn path;\n}\n\nstruct ReadWitness\n{\n\tstruct Clock {\n\t\tIdPath path;\n\t\tint offset;\n\t\tbool is_posedge = false;\n\t\tbool is_negedge = false;\n\t};\n\n\tstruct Signal {\n\t\tIdPath path;\n\t\tint offset;\n\t\tint width;\n\t\tbool init_only;\n\n\t\tint bits_offset;\n\t};\n\n\tstruct Step {\n\t\tstd::string bits;\n\t};\n\n\tstd::string filename;\n\tstd::vector<Clock> clocks;\n\tstd::vector<Signal> signals;\n\tstd::vector<Step> steps;\n\n\tReadWitness(const std::string &filename);\n\n\tRTLIL::Const get_bits(int t, int bits_offset, int width) const;\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *module, D data, T &callback)\n{\n\tauto const &const_path = path;\n\tsize_t path_size = path.size();\n\tfor (auto wire : module->wires())\n\t{\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : wire->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == wire->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty())\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(wire->name);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto cell : module->cells())\n\t{\n\t\tModule *child = module->design->module(cell->type);\n\t\tif (child == nullptr)\n\t\t\tcontinue;\n\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, 1, child, child_data, callback);\n\t\t}\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(cell->name);\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, hdlname.empty() ? hdlname_mode : -1, child, child_data, callback);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto mem : Mem::get_all_memories(module)) {\n\t\tstd::vector<std::string> hdlname;\n\n\t\tif (hdlname_mode >= 0 && mem.cell != nullptr)\n\t\t\thdlname = mem.cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == mem.cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t}\n\t\tpath.resize(path_size);\n\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(mem.memid);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\tpath.pop_back();\n\n\t\t\tif (mem.cell != nullptr && mem.cell->name != mem.memid) {\n\t\t\t\tpath.push_back(mem.cell->name);\n\t\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\t\tpath.pop_back();\n\t\t\t}\n\t\t}\n\t}\n}\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback)\n{\n\tIdPath path;\n\twitness_hierarchy_recursion<D, T>(path, 0, module, data, callback);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
             },
             "libs": {
@@ -266,28 +260,40 @@ export const filesystem = {
         "lattice": {
             "arith_map_ccu2c.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2018  gatecat <gatecat@ds0.me>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_ccu2c_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 4;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\tfunction integer round_up2;\n\t\tinput integer N;\n\t\tbegin\n\t\t\tround_up2 = ((N + 1) / 2) * 2;\n\t\tend\n\tendfunction\n\n\tlocalparam Y_WIDTH2 = round_up2(Y_WIDTH);\n\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BX = B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] FCO, Y1;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice\n\t\tCCU2C #(\n\t\t\t.INIT0(16'b1001011010101010),\n\t\t\t.INIT1(16'b1001011010101010),\n\t\t\t.INJECT1_0(\"NO\"),\n\t\t\t.INJECT1_1(\"NO\")\n\t   ) ccu2c_i (\n\t\t\t.CIN(C[i]),\n\t\t\t.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),\n\t\t\t.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),\n\t\t\t.S0(Y[i]), .S1(Y1[i]),\n\t\t\t.COUT(FCO[i])\n\t\t);\n\n\t\tassign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));\n\t\tif (i+1 < Y_WIDTH) begin\n\t\t\tassign CO[i+1] = FCO[i];\n\t\t\tassign Y[i+1] = Y1[i];\n\t\tend\n\tend endgenerate\n\n\tassign X = AA ^ BB;\nendmodule\n",
             "arith_map_ccu2d.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2018  gatecat <gatecat@ds0.me>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_ccu2d_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 4;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\tfunction integer round_up2;\n\t\tinput integer N;\n\t\tbegin\n\t\t\tround_up2 = ((N + 1) / 2) * 2;\n\t\tend\n\tendfunction\n\n\tlocalparam Y_WIDTH2 = round_up2(Y_WIDTH);\n\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BX = B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] FCO, Y1;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice\n\t\tCCU2D #(\n\t\t\t.INIT0(16'b0101_1010_1001_0110),\n\t\t\t.INIT1(16'b0101_1010_1001_0110),\n\t\t\t.INJECT1_0(\"NO\"),\n\t\t\t.INJECT1_1(\"NO\")\n\t\t) ccu2d_i (\n\t\t\t.CIN(C[i]),\n\t\t\t.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b0),\n\t\t\t.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b0),\n\t\t\t.S0(Y[i]), .S1(Y1[i]),\n\t\t\t.COUT(FCO[i])\n\t\t);\n\n\t\tassign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));\n\t\tif (i+1 < Y_WIDTH) begin\n\t\t\tassign CO[i+1] = FCO[i];\n\t\t\tassign Y[i+1] = Y1[i];\n\t\tend\n\tend endgenerate\n\n\tassign X = AA ^ BB;\nendmodule\n",
+            "arith_map_nexus.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2018  gatecat <gatecat@ds0.me>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_nexus_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 4;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\tfunction integer round_up2;\n\t\tinput integer N;\n\t\tbegin\n\t\t\tround_up2 = ((N + 1) / 2) * 2;\n\t\tend\n\tendfunction\n\n\tlocalparam Y_WIDTH2 = round_up2(Y_WIDTH);\n\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BX = B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2+1:0] FCO, Y1;\n\n\tgenvar i;\n\n\t// Carry feed-in\n\tCCU2 #(\n\t\t.INIT0(\"0xFFFF\"),\n\t\t.INIT1(\"0x00AA\"),\n\t\t.INJECT(\"NO\")\n\t) ccu2c_i (\n\t\t.A0(1'b1), .B0(1'b1), .C0(1'b1), .D0(1'b1),\n\t\t.A1(CI), .B1(1'b1), .C1(1'b1), .D1(1'b1),\n\t\t.COUT(FCO[0])\n\t);\n\n\tgenerate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice\n\t\tCCU2 #(\n\t\t\t.INIT0(\"0x96AA\"),\n\t\t\t.INIT1(\"0x96AA\"),\n\t\t\t.INJECT(\"NO\")\n\t\t) ccu2c_i (\n\t\t\t.CIN(FCO[i]),\n\t\t\t.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),\n\t\t\t.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),\n\t\t\t.S0(Y[i]), .S1(Y1[i]),\n\t\t\t.COUT(FCO[i+2])\n\t\t);\n\n\t\tassign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));\n\t\tif (i+1 < Y_WIDTH) begin\n\t\t\tassign CO[i + 1] = (AA[i + 1] && BB[i + 1]) || ((Y[i + 1] ^ AA[i + 1] ^ BB[i + 1]) && (AA[i + 1] || BB[i + 1]));\n\t\t\tassign Y[i+1] = Y1[i];\n\t\tend\n\tend endgenerate\n\n\tassign X = AA ^ BB;\nendmodule\n",
             "brams_16kd.txt": "ram block $__DP16KD_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\tportoption \"WRITEMODE\" \"NORMAL\" {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"WRITETHROUGH\" {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"READBEFOREWRITE\" {\n\t\t\trdwr old;\n\t\t}\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated block_wr;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n}\n\nram block $__PDPW16KD_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\twidth 36;\n\t\tclock anyedge;\n\t\tclken;\n\t}\n}\n",
             "brams_8kc.txt": "ram block $__DP8KC_ {\n\tabits 13;\n\twidths 1 2 4 9 per_port;\n\tcost 64;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\tportoption \"WRITEMODE\" \"NORMAL\" {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"WRITETHROUGH\" {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITEMODE\" \"READBEFOREWRITE\" {\n\t\t\trdwr old;\n\t\t}\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated block_wr;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n}\n\nram block $__PDPW8KC_ {\n\tabits 13;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 64;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\t# width 2 cannot be supported because of quirks\n\t\t# of the primitive, and memlib requires us to\n\t\t# remove width 1 as well\n\t\twidth 4 9 18;\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\twidth 18;\n\t\tclock posedge;\n\t\tclken;\n\t}\n}\n",
             "brams_map_16kd.v": "module $__DP16KD_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_WR_BE_WIDTH = 2;\nparameter PORT_A_CLK_POL = 1;\nparameter PORT_A_OPTION_WRITEMODE = \"NORMAL\";\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_WR_BE_WIDTH = 2;\nparameter PORT_B_CLK_POL = 1;\nparameter PORT_B_OPTION_WRITEMODE = \"NORMAL\";\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 16; i = i + 1) begin\n\t\tinit_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];\n\tend\nendfunction\n\nwire [17:0] DOA;\nwire [17:0] DOB;\nwire [17:0] DIA = PORT_A_WR_DATA;\nwire [17:0] DIB = PORT_B_WR_DATA;\n\nassign PORT_A_RD_DATA = DOA;\nassign PORT_B_RD_DATA = DOB;\n\nDP16KD #(\n\t.INITVAL_00(init_slice('h00)),\n\t.INITVAL_01(init_slice('h01)),\n\t.INITVAL_02(init_slice('h02)),\n\t.INITVAL_03(init_slice('h03)),\n\t.INITVAL_04(init_slice('h04)),\n\t.INITVAL_05(init_slice('h05)),\n\t.INITVAL_06(init_slice('h06)),\n\t.INITVAL_07(init_slice('h07)),\n\t.INITVAL_08(init_slice('h08)),\n\t.INITVAL_09(init_slice('h09)),\n\t.INITVAL_0A(init_slice('h0a)),\n\t.INITVAL_0B(init_slice('h0b)),\n\t.INITVAL_0C(init_slice('h0c)),\n\t.INITVAL_0D(init_slice('h0d)),\n\t.INITVAL_0E(init_slice('h0e)),\n\t.INITVAL_0F(init_slice('h0f)),\n\t.INITVAL_10(init_slice('h10)),\n\t.INITVAL_11(init_slice('h11)),\n\t.INITVAL_12(init_slice('h12)),\n\t.INITVAL_13(init_slice('h13)),\n\t.INITVAL_14(init_slice('h14)),\n\t.INITVAL_15(init_slice('h15)),\n\t.INITVAL_16(init_slice('h16)),\n\t.INITVAL_17(init_slice('h17)),\n\t.INITVAL_18(init_slice('h18)),\n\t.INITVAL_19(init_slice('h19)),\n\t.INITVAL_1A(init_slice('h1a)),\n\t.INITVAL_1B(init_slice('h1b)),\n\t.INITVAL_1C(init_slice('h1c)),\n\t.INITVAL_1D(init_slice('h1d)),\n\t.INITVAL_1E(init_slice('h1e)),\n\t.INITVAL_1F(init_slice('h1f)),\n\t.INITVAL_20(init_slice('h20)),\n\t.INITVAL_21(init_slice('h21)),\n\t.INITVAL_22(init_slice('h22)),\n\t.INITVAL_23(init_slice('h23)),\n\t.INITVAL_24(init_slice('h24)),\n\t.INITVAL_25(init_slice('h25)),\n\t.INITVAL_26(init_slice('h26)),\n\t.INITVAL_27(init_slice('h27)),\n\t.INITVAL_28(init_slice('h28)),\n\t.INITVAL_29(init_slice('h29)),\n\t.INITVAL_2A(init_slice('h2a)),\n\t.INITVAL_2B(init_slice('h2b)),\n\t.INITVAL_2C(init_slice('h2c)),\n\t.INITVAL_2D(init_slice('h2d)),\n\t.INITVAL_2E(init_slice('h2e)),\n\t.INITVAL_2F(init_slice('h2f)),\n\t.INITVAL_30(init_slice('h30)),\n\t.INITVAL_31(init_slice('h31)),\n\t.INITVAL_32(init_slice('h32)),\n\t.INITVAL_33(init_slice('h33)),\n\t.INITVAL_34(init_slice('h34)),\n\t.INITVAL_35(init_slice('h35)),\n\t.INITVAL_36(init_slice('h36)),\n\t.INITVAL_37(init_slice('h37)),\n\t.INITVAL_38(init_slice('h38)),\n\t.INITVAL_39(init_slice('h39)),\n\t.INITVAL_3A(init_slice('h3a)),\n\t.INITVAL_3B(init_slice('h3b)),\n\t.INITVAL_3C(init_slice('h3c)),\n\t.INITVAL_3D(init_slice('h3d)),\n\t.INITVAL_3E(init_slice('h3e)),\n\t.INITVAL_3F(init_slice('h3f)),\n\t.DATA_WIDTH_A(PORT_A_WIDTH),\n\t.DATA_WIDTH_B(PORT_B_WIDTH),\n\t.REGMODE_A(\"NOREG\"),\n\t.REGMODE_B(\"NOREG\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n\t.CSDECODE_A(\"0b000\"),\n\t.CSDECODE_B(\"0b000\"),\n\t.CLKAMUX(PORT_A_CLK_POL ? \"CLKA\" : \"INV\"),\n\t.CLKBMUX(PORT_B_CLK_POL ? \"CLKB\" : \"INV\"),\n\t.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),\n\t.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),\n\t.GSR(\"AUTO\")\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_A_CLK),\n\t.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),\n\t.CEA(PORT_A_CLK_EN),\n\t.OCEA(1'b1),\n\t.RSTA(OPTION_RESETMODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t.CSA0(1'b0),\n\t.CSA1(1'b0),\n\t.CSA2(1'b0),\n\t.ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]),\n\t.ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]),\n\t.ADA2(PORT_A_ADDR[2]),\n\t.ADA3(PORT_A_ADDR[3]),\n\t.ADA4(PORT_A_ADDR[4]),\n\t.ADA5(PORT_A_ADDR[5]),\n\t.ADA6(PORT_A_ADDR[6]),\n\t.ADA7(PORT_A_ADDR[7]),\n\t.ADA8(PORT_A_ADDR[8]),\n\t.ADA9(PORT_A_ADDR[9]),\n\t.ADA10(PORT_A_ADDR[10]),\n\t.ADA11(PORT_A_ADDR[11]),\n\t.ADA12(PORT_A_ADDR[12]),\n\t.ADA13(PORT_A_ADDR[13]),\n\t.DIA0(DIA[0]),\n\t.DIA1(DIA[1]),\n\t.DIA2(DIA[2]),\n\t.DIA3(DIA[3]),\n\t.DIA4(DIA[4]),\n\t.DIA5(DIA[5]),\n\t.DIA6(DIA[6]),\n\t.DIA7(DIA[7]),\n\t.DIA8(DIA[8]),\n\t.DIA9(DIA[9]),\n\t.DIA10(DIA[10]),\n\t.DIA11(DIA[11]),\n\t.DIA12(DIA[12]),\n\t.DIA13(DIA[13]),\n\t.DIA14(DIA[14]),\n\t.DIA15(DIA[15]),\n\t.DIA16(DIA[16]),\n\t.DIA17(DIA[17]),\n\t.DOA0(DOA[0]),\n\t.DOA1(DOA[1]),\n\t.DOA2(DOA[2]),\n\t.DOA3(DOA[3]),\n\t.DOA4(DOA[4]),\n\t.DOA5(DOA[5]),\n\t.DOA6(DOA[6]),\n\t.DOA7(DOA[7]),\n\t.DOA8(DOA[8]),\n\t.DOA9(DOA[9]),\n\t.DOA10(DOA[10]),\n\t.DOA11(DOA[11]),\n\t.DOA12(DOA[12]),\n\t.DOA13(DOA[13]),\n\t.DOA14(DOA[14]),\n\t.DOA15(DOA[15]),\n\t.DOA16(DOA[16]),\n\t.DOA17(DOA[17]),\n\n\t.CLKB(PORT_B_CLK),\n\t.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),\n\t.CEB(PORT_B_CLK_EN),\n\t.OCEB(1'b1),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t.CSB0(1'b0),\n\t.CSB1(1'b0),\n\t.CSB2(1'b0),\n\t.ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]),\n\t.ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]),\n\t.ADB2(PORT_B_ADDR[2]),\n\t.ADB3(PORT_B_ADDR[3]),\n\t.ADB4(PORT_B_ADDR[4]),\n\t.ADB5(PORT_B_ADDR[5]),\n\t.ADB6(PORT_B_ADDR[6]),\n\t.ADB7(PORT_B_ADDR[7]),\n\t.ADB8(PORT_B_ADDR[8]),\n\t.ADB9(PORT_B_ADDR[9]),\n\t.ADB10(PORT_B_ADDR[10]),\n\t.ADB11(PORT_B_ADDR[11]),\n\t.ADB12(PORT_B_ADDR[12]),\n\t.ADB13(PORT_B_ADDR[13]),\n\t.DIB0(DIB[0]),\n\t.DIB1(DIB[1]),\n\t.DIB2(DIB[2]),\n\t.DIB3(DIB[3]),\n\t.DIB4(DIB[4]),\n\t.DIB5(DIB[5]),\n\t.DIB6(DIB[6]),\n\t.DIB7(DIB[7]),\n\t.DIB8(DIB[8]),\n\t.DIB9(DIB[9]),\n\t.DIB10(DIB[10]),\n\t.DIB11(DIB[11]),\n\t.DIB12(DIB[12]),\n\t.DIB13(DIB[13]),\n\t.DIB14(DIB[14]),\n\t.DIB15(DIB[15]),\n\t.DIB16(DIB[16]),\n\t.DIB17(DIB[17]),\n\t.DOB0(DOB[0]),\n\t.DOB1(DOB[1]),\n\t.DOB2(DOB[2]),\n\t.DOB3(DOB[3]),\n\t.DOB4(DOB[4]),\n\t.DOB5(DOB[5]),\n\t.DOB6(DOB[6]),\n\t.DOB7(DOB[7]),\n\t.DOB8(DOB[8]),\n\t.DOB9(DOB[9]),\n\t.DOB10(DOB[10]),\n\t.DOB11(DOB[11]),\n\t.DOB12(DOB[12]),\n\t.DOB13(DOB[13]),\n\t.DOB14(DOB[14]),\n\t.DOB15(DOB[15]),\n\t.DOB16(DOB[16]),\n\t.DOB17(DOB[17]),\n);\n\nendmodule\n\n\nmodule $__PDPW16KD_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 36;\nparameter PORT_R_CLK_POL = 1;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\nparameter PORT_W_WIDTH = 36;\nparameter PORT_W_WR_EN_WIDTH = 4;\nparameter PORT_W_CLK_POL = 1;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 16; i = i + 1) begin\n\t\tinit_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];\n\tend\nendfunction\n\nwire [35:0] DI = PORT_W_WR_DATA;\nwire [35:0] DO;\n\nassign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18];\n\nDP16KD #(\n\t.INITVAL_00(init_slice('h00)),\n\t.INITVAL_01(init_slice('h01)),\n\t.INITVAL_02(init_slice('h02)),\n\t.INITVAL_03(init_slice('h03)),\n\t.INITVAL_04(init_slice('h04)),\n\t.INITVAL_05(init_slice('h05)),\n\t.INITVAL_06(init_slice('h06)),\n\t.INITVAL_07(init_slice('h07)),\n\t.INITVAL_08(init_slice('h08)),\n\t.INITVAL_09(init_slice('h09)),\n\t.INITVAL_0A(init_slice('h0a)),\n\t.INITVAL_0B(init_slice('h0b)),\n\t.INITVAL_0C(init_slice('h0c)),\n\t.INITVAL_0D(init_slice('h0d)),\n\t.INITVAL_0E(init_slice('h0e)),\n\t.INITVAL_0F(init_slice('h0f)),\n\t.INITVAL_10(init_slice('h10)),\n\t.INITVAL_11(init_slice('h11)),\n\t.INITVAL_12(init_slice('h12)),\n\t.INITVAL_13(init_slice('h13)),\n\t.INITVAL_14(init_slice('h14)),\n\t.INITVAL_15(init_slice('h15)),\n\t.INITVAL_16(init_slice('h16)),\n\t.INITVAL_17(init_slice('h17)),\n\t.INITVAL_18(init_slice('h18)),\n\t.INITVAL_19(init_slice('h19)),\n\t.INITVAL_1A(init_slice('h1a)),\n\t.INITVAL_1B(init_slice('h1b)),\n\t.INITVAL_1C(init_slice('h1c)),\n\t.INITVAL_1D(init_slice('h1d)),\n\t.INITVAL_1E(init_slice('h1e)),\n\t.INITVAL_1F(init_slice('h1f)),\n\t.INITVAL_20(init_slice('h20)),\n\t.INITVAL_21(init_slice('h21)),\n\t.INITVAL_22(init_slice('h22)),\n\t.INITVAL_23(init_slice('h23)),\n\t.INITVAL_24(init_slice('h24)),\n\t.INITVAL_25(init_slice('h25)),\n\t.INITVAL_26(init_slice('h26)),\n\t.INITVAL_27(init_slice('h27)),\n\t.INITVAL_28(init_slice('h28)),\n\t.INITVAL_29(init_slice('h29)),\n\t.INITVAL_2A(init_slice('h2a)),\n\t.INITVAL_2B(init_slice('h2b)),\n\t.INITVAL_2C(init_slice('h2c)),\n\t.INITVAL_2D(init_slice('h2d)),\n\t.INITVAL_2E(init_slice('h2e)),\n\t.INITVAL_2F(init_slice('h2f)),\n\t.INITVAL_30(init_slice('h30)),\n\t.INITVAL_31(init_slice('h31)),\n\t.INITVAL_32(init_slice('h32)),\n\t.INITVAL_33(init_slice('h33)),\n\t.INITVAL_34(init_slice('h34)),\n\t.INITVAL_35(init_slice('h35)),\n\t.INITVAL_36(init_slice('h36)),\n\t.INITVAL_37(init_slice('h37)),\n\t.INITVAL_38(init_slice('h38)),\n\t.INITVAL_39(init_slice('h39)),\n\t.INITVAL_3A(init_slice('h3a)),\n\t.INITVAL_3B(init_slice('h3b)),\n\t.INITVAL_3C(init_slice('h3c)),\n\t.INITVAL_3D(init_slice('h3d)),\n\t.INITVAL_3E(init_slice('h3e)),\n\t.INITVAL_3F(init_slice('h3f)),\n\t.DATA_WIDTH_A(PORT_W_WIDTH),\n\t.DATA_WIDTH_B(PORT_R_WIDTH),\n\t.REGMODE_A(\"NOREG\"),\n\t.REGMODE_B(\"NOREG\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n\t.CSDECODE_A(\"0b000\"),\n\t.CSDECODE_B(\"0b000\"),\n\t.CLKAMUX(PORT_W_CLK_POL ? \"CLKA\" : \"INV\"),\n\t.CLKBMUX(PORT_R_CLK_POL ? \"CLKB\" : \"INV\"),\n\t.GSR(\"AUTO\")\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_W_CLK),\n\t.WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]),\n\t.CEA(PORT_W_CLK_EN),\n\t.OCEA(1'b0),\n\t.RSTA(1'b0),\n\t.CSA0(1'b0),\n\t.CSA1(1'b0),\n\t.CSA2(1'b0),\n\t.ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),\n\t.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),\n\t.ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]),\n\t.ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]),\n\t.ADA4(PORT_W_ADDR[4]),\n\t.ADA5(PORT_W_ADDR[5]),\n\t.ADA6(PORT_W_ADDR[6]),\n\t.ADA7(PORT_W_ADDR[7]),\n\t.ADA8(PORT_W_ADDR[8]),\n\t.ADA9(PORT_W_ADDR[9]),\n\t.ADA10(PORT_W_ADDR[10]),\n\t.ADA11(PORT_W_ADDR[11]),\n\t.ADA12(PORT_W_ADDR[12]),\n\t.ADA13(PORT_W_ADDR[13]),\n\t.DIA0(DI[0]),\n\t.DIA1(DI[1]),\n\t.DIA2(DI[2]),\n\t.DIA3(DI[3]),\n\t.DIA4(DI[4]),\n\t.DIA5(DI[5]),\n\t.DIA6(DI[6]),\n\t.DIA7(DI[7]),\n\t.DIA8(DI[8]),\n\t.DIA9(DI[9]),\n\t.DIA10(DI[10]),\n\t.DIA11(DI[11]),\n\t.DIA12(DI[12]),\n\t.DIA13(DI[13]),\n\t.DIA14(DI[14]),\n\t.DIA15(DI[15]),\n\t.DIA16(DI[16]),\n\t.DIA17(DI[17]),\n\t.DIB0(DI[18]),\n\t.DIB1(DI[19]),\n\t.DIB2(DI[20]),\n\t.DIB3(DI[21]),\n\t.DIB4(DI[22]),\n\t.DIB5(DI[23]),\n\t.DIB6(DI[24]),\n\t.DIB7(DI[25]),\n\t.DIB8(DI[26]),\n\t.DIB9(DI[27]),\n\t.DIB10(DI[28]),\n\t.DIB11(DI[29]),\n\t.DIB12(DI[30]),\n\t.DIB13(DI[31]),\n\t.DIB14(DI[32]),\n\t.DIB15(DI[33]),\n\t.DIB16(DI[34]),\n\t.DIB17(DI[35]),\n\n\t.CLKB(PORT_R_CLK),\n\t.WEB(1'b0),\n\t.CEB(PORT_R_CLK_EN),\n\t.OCEB(1'b1),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST),\n\t.CSB0(1'b0),\n\t.CSB1(1'b0),\n\t.CSB2(1'b0),\n\t.ADB0(PORT_R_ADDR[0]),\n\t.ADB1(PORT_R_ADDR[1]),\n\t.ADB2(PORT_R_ADDR[2]),\n\t.ADB3(PORT_R_ADDR[3]),\n\t.ADB4(PORT_R_ADDR[4]),\n\t.ADB5(PORT_R_ADDR[5]),\n\t.ADB6(PORT_R_ADDR[6]),\n\t.ADB7(PORT_R_ADDR[7]),\n\t.ADB8(PORT_R_ADDR[8]),\n\t.ADB9(PORT_R_ADDR[9]),\n\t.ADB10(PORT_R_ADDR[10]),\n\t.ADB11(PORT_R_ADDR[11]),\n\t.ADB12(PORT_R_ADDR[12]),\n\t.ADB13(PORT_R_ADDR[13]),\n\t.DOA0(DO[0]),\n\t.DOA1(DO[1]),\n\t.DOA2(DO[2]),\n\t.DOA3(DO[3]),\n\t.DOA4(DO[4]),\n\t.DOA5(DO[5]),\n\t.DOA6(DO[6]),\n\t.DOA7(DO[7]),\n\t.DOA8(DO[8]),\n\t.DOA9(DO[9]),\n\t.DOA10(DO[10]),\n\t.DOA11(DO[11]),\n\t.DOA12(DO[12]),\n\t.DOA13(DO[13]),\n\t.DOA14(DO[14]),\n\t.DOA15(DO[15]),\n\t.DOA16(DO[16]),\n\t.DOA17(DO[17]),\n\t.DOB0(DO[18]),\n\t.DOB1(DO[19]),\n\t.DOB2(DO[20]),\n\t.DOB3(DO[21]),\n\t.DOB4(DO[22]),\n\t.DOB5(DO[23]),\n\t.DOB6(DO[24]),\n\t.DOB7(DO[25]),\n\t.DOB8(DO[26]),\n\t.DOB9(DO[27]),\n\t.DOB10(DO[28]),\n\t.DOB11(DO[29]),\n\t.DOB12(DO[30]),\n\t.DOB13(DO[31]),\n\t.DOB14(DO[32]),\n\t.DOB15(DO[33]),\n\t.DOB16(DO[34]),\n\t.DOB17(DO[35]),\n);\n\nendmodule\n",
             "brams_map_8kc.v": "module $__DP8KC_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_OPTION_WRITEMODE = \"NORMAL\";\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [12:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_OPTION_WRITEMODE = \"NORMAL\";\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [12:0] PORT_B_ADDR;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 16; i = i + 1) begin\n\t\tinit_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];\n\tend\nendfunction\n\nwire [8:0] DOA;\nwire [8:0] DOB;\nwire [8:0] DIA;\nwire [8:0] DIB;\n\ncase(PORT_A_WIDTH)\n\t1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx};\n\t2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx};\n\tdefault: assign DIA = PORT_A_WR_DATA;\nendcase\n\ncase(PORT_B_WIDTH)\n\t1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx};\n\t2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx};\n\tdefault: assign DIB = PORT_B_WR_DATA;\nendcase\n\nassign PORT_A_RD_DATA = DOA;\nassign PORT_B_RD_DATA = DOB;\n\nDP8KC #(\n\t.INITVAL_00(init_slice('h00)),\n\t.INITVAL_01(init_slice('h01)),\n\t.INITVAL_02(init_slice('h02)),\n\t.INITVAL_03(init_slice('h03)),\n\t.INITVAL_04(init_slice('h04)),\n\t.INITVAL_05(init_slice('h05)),\n\t.INITVAL_06(init_slice('h06)),\n\t.INITVAL_07(init_slice('h07)),\n\t.INITVAL_08(init_slice('h08)),\n\t.INITVAL_09(init_slice('h09)),\n\t.INITVAL_0A(init_slice('h0a)),\n\t.INITVAL_0B(init_slice('h0b)),\n\t.INITVAL_0C(init_slice('h0c)),\n\t.INITVAL_0D(init_slice('h0d)),\n\t.INITVAL_0E(init_slice('h0e)),\n\t.INITVAL_0F(init_slice('h0f)),\n\t.INITVAL_10(init_slice('h10)),\n\t.INITVAL_11(init_slice('h11)),\n\t.INITVAL_12(init_slice('h12)),\n\t.INITVAL_13(init_slice('h13)),\n\t.INITVAL_14(init_slice('h14)),\n\t.INITVAL_15(init_slice('h15)),\n\t.INITVAL_16(init_slice('h16)),\n\t.INITVAL_17(init_slice('h17)),\n\t.INITVAL_18(init_slice('h18)),\n\t.INITVAL_19(init_slice('h19)),\n\t.INITVAL_1A(init_slice('h1a)),\n\t.INITVAL_1B(init_slice('h1b)),\n\t.INITVAL_1C(init_slice('h1c)),\n\t.INITVAL_1D(init_slice('h1d)),\n\t.INITVAL_1E(init_slice('h1e)),\n\t.INITVAL_1F(init_slice('h1f)),\n\t.DATA_WIDTH_A(PORT_A_WIDTH),\n\t.DATA_WIDTH_B(PORT_B_WIDTH),\n\t.REGMODE_A(\"NOREG\"),\n\t.REGMODE_B(\"NOREG\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n\t.CSDECODE_A(\"0b000\"),\n\t.CSDECODE_B(\"0b000\"),\n\t.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),\n\t.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),\n\t.GSR(\"AUTO\")\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_A_CLK),\n\t.WEA(PORT_A_WR_EN),\n\t.CEA(PORT_A_CLK_EN),\n\t.OCEA(1'b1),\n\t.RSTA(OPTION_RESETMODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t.CSA0(1'b0),\n\t.CSA1(1'b0),\n\t.CSA2(1'b0),\n\t.ADA0(PORT_A_WIDTH == 9 ? 1'b1 : PORT_A_ADDR[0]),\n\t.ADA1(PORT_A_ADDR[1]),\n\t.ADA2(PORT_A_ADDR[2]),\n\t.ADA3(PORT_A_ADDR[3]),\n\t.ADA4(PORT_A_ADDR[4]),\n\t.ADA5(PORT_A_ADDR[5]),\n\t.ADA6(PORT_A_ADDR[6]),\n\t.ADA7(PORT_A_ADDR[7]),\n\t.ADA8(PORT_A_ADDR[8]),\n\t.ADA9(PORT_A_ADDR[9]),\n\t.ADA10(PORT_A_ADDR[10]),\n\t.ADA11(PORT_A_ADDR[11]),\n\t.ADA12(PORT_A_ADDR[12]),\n\t.DIA0(DIA[0]),\n\t.DIA1(DIA[1]),\n\t.DIA2(DIA[2]),\n\t.DIA3(DIA[3]),\n\t.DIA4(DIA[4]),\n\t.DIA5(DIA[5]),\n\t.DIA6(DIA[6]),\n\t.DIA7(DIA[7]),\n\t.DIA8(DIA[8]),\n\t.DOA0(DOA[0]),\n\t.DOA1(DOA[1]),\n\t.DOA2(DOA[2]),\n\t.DOA3(DOA[3]),\n\t.DOA4(DOA[4]),\n\t.DOA5(DOA[5]),\n\t.DOA6(DOA[6]),\n\t.DOA7(DOA[7]),\n\t.DOA8(DOA[8]),\n\n\t.CLKB(PORT_B_CLK),\n\t.WEB(PORT_B_WR_EN),\n\t.CEB(PORT_B_CLK_EN),\n\t.OCEB(1'b1),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t.CSB0(1'b0),\n\t.CSB1(1'b0),\n\t.CSB2(1'b0),\n\t.ADB0(PORT_B_WIDTH == 9 ? 1'b1 : PORT_B_ADDR[0]),\n\t.ADB1(PORT_B_ADDR[1]),\n\t.ADB2(PORT_B_ADDR[2]),\n\t.ADB3(PORT_B_ADDR[3]),\n\t.ADB4(PORT_B_ADDR[4]),\n\t.ADB5(PORT_B_ADDR[5]),\n\t.ADB6(PORT_B_ADDR[6]),\n\t.ADB7(PORT_B_ADDR[7]),\n\t.ADB8(PORT_B_ADDR[8]),\n\t.ADB9(PORT_B_ADDR[9]),\n\t.ADB10(PORT_B_ADDR[10]),\n\t.ADB11(PORT_B_ADDR[11]),\n\t.ADB12(PORT_B_ADDR[12]),\n\t.DIB0(DIB[0]),\n\t.DIB1(DIB[1]),\n\t.DIB2(DIB[2]),\n\t.DIB3(DIB[3]),\n\t.DIB4(DIB[4]),\n\t.DIB5(DIB[5]),\n\t.DIB6(DIB[6]),\n\t.DIB7(DIB[7]),\n\t.DIB8(DIB[8]),\n\t.DOB0(DOB[0]),\n\t.DOB1(DOB[1]),\n\t.DOB2(DOB[2]),\n\t.DOB3(DOB[3]),\n\t.DOB4(DOB[4]),\n\t.DOB5(DOB[5]),\n\t.DOB6(DOB[6]),\n\t.DOB7(DOB[7]),\n\t.DOB8(DOB[8]),\n);\n\nendmodule\n\n\nmodule $__PDPW8KC_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 18;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [12:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\nparameter PORT_W_WIDTH = 18;\nparameter PORT_W_WR_EN_WIDTH = 2;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput [12:0] PORT_W_ADDR;\ninput [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 16; i = i + 1) begin\n\t\tinit_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];\n\tend\nendfunction\n\nwire [17:0] DI = PORT_W_WR_DATA;\nwire [17:0] DO;\n\nassign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9];\n\nDP8KC #(\n\t.INITVAL_00(init_slice('h00)),\n\t.INITVAL_01(init_slice('h01)),\n\t.INITVAL_02(init_slice('h02)),\n\t.INITVAL_03(init_slice('h03)),\n\t.INITVAL_04(init_slice('h04)),\n\t.INITVAL_05(init_slice('h05)),\n\t.INITVAL_06(init_slice('h06)),\n\t.INITVAL_07(init_slice('h07)),\n\t.INITVAL_08(init_slice('h08)),\n\t.INITVAL_09(init_slice('h09)),\n\t.INITVAL_0A(init_slice('h0a)),\n\t.INITVAL_0B(init_slice('h0b)),\n\t.INITVAL_0C(init_slice('h0c)),\n\t.INITVAL_0D(init_slice('h0d)),\n\t.INITVAL_0E(init_slice('h0e)),\n\t.INITVAL_0F(init_slice('h0f)),\n\t.INITVAL_10(init_slice('h10)),\n\t.INITVAL_11(init_slice('h11)),\n\t.INITVAL_12(init_slice('h12)),\n\t.INITVAL_13(init_slice('h13)),\n\t.INITVAL_14(init_slice('h14)),\n\t.INITVAL_15(init_slice('h15)),\n\t.INITVAL_16(init_slice('h16)),\n\t.INITVAL_17(init_slice('h17)),\n\t.INITVAL_18(init_slice('h18)),\n\t.INITVAL_19(init_slice('h19)),\n\t.INITVAL_1A(init_slice('h1a)),\n\t.INITVAL_1B(init_slice('h1b)),\n\t.INITVAL_1C(init_slice('h1c)),\n\t.INITVAL_1D(init_slice('h1d)),\n\t.INITVAL_1E(init_slice('h1e)),\n\t.INITVAL_1F(init_slice('h1f)),\n\t.DATA_WIDTH_A(PORT_W_WIDTH),\n\t.DATA_WIDTH_B(PORT_R_WIDTH),\n\t.REGMODE_A(\"NOREG\"),\n\t.REGMODE_B(\"NOREG\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n\t.CSDECODE_A(\"0b000\"),\n\t.CSDECODE_B(\"0b000\"),\n\t.GSR(\"AUTO\")\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_W_CLK),\n\t.WEA(PORT_W_WIDTH >= 9 ? 1'b1 : PORT_W_WR_EN[0]),\n\t.CEA(PORT_W_CLK_EN),\n\t.OCEA(1'b0),\n\t.RSTA(1'b0),\n\t.CSA0(1'b0),\n\t.CSA1(1'b0),\n\t.CSA2(1'b0),\n\t.ADA0(PORT_W_WIDTH >= 9 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),\n\t.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),\n\t.ADA2(PORT_W_ADDR[2]),\n\t.ADA3(PORT_W_ADDR[3]),\n\t.ADA4(PORT_W_ADDR[4]),\n\t.ADA5(PORT_W_ADDR[5]),\n\t.ADA6(PORT_W_ADDR[6]),\n\t.ADA7(PORT_W_ADDR[7]),\n\t.ADA8(PORT_W_ADDR[8]),\n\t.ADA9(PORT_W_ADDR[9]),\n\t.ADA10(PORT_W_ADDR[10]),\n\t.ADA11(PORT_W_ADDR[11]),\n\t.ADA12(PORT_W_ADDR[12]),\n\t.DIA0(DI[0]),\n\t.DIA1(DI[1]),\n\t.DIA2(DI[2]),\n\t.DIA3(DI[3]),\n\t.DIA4(DI[4]),\n\t.DIA5(DI[5]),\n\t.DIA6(DI[6]),\n\t.DIA7(DI[7]),\n\t.DIA8(DI[8]),\n\t.DIB0(DI[9]),\n\t.DIB1(DI[10]),\n\t.DIB2(DI[11]),\n\t.DIB3(DI[12]),\n\t.DIB4(DI[13]),\n\t.DIB5(DI[14]),\n\t.DIB6(DI[15]),\n\t.DIB7(DI[16]),\n\t.DIB8(DI[17]),\n\n\t.CLKB(PORT_R_CLK),\n\t.WEB(1'b0),\n\t.CEB(PORT_R_CLK_EN),\n\t.OCEB(1'b1),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST),\n\t.CSB0(1'b0),\n\t.CSB1(1'b0),\n\t.CSB2(1'b0),\n\t.ADB0(PORT_R_ADDR[0]),\n\t.ADB1(PORT_R_ADDR[1]),\n\t.ADB2(PORT_R_ADDR[2]),\n\t.ADB3(PORT_R_ADDR[3]),\n\t.ADB4(PORT_R_ADDR[4]),\n\t.ADB5(PORT_R_ADDR[5]),\n\t.ADB6(PORT_R_ADDR[6]),\n\t.ADB7(PORT_R_ADDR[7]),\n\t.ADB8(PORT_R_ADDR[8]),\n\t.ADB9(PORT_R_ADDR[9]),\n\t.ADB10(PORT_R_ADDR[10]),\n\t.ADB11(PORT_R_ADDR[11]),\n\t.ADB12(PORT_R_ADDR[12]),\n\t.DOA0(DO[0]),\n\t.DOA1(DO[1]),\n\t.DOA2(DO[2]),\n\t.DOA3(DO[3]),\n\t.DOA4(DO[4]),\n\t.DOA5(DO[5]),\n\t.DOA6(DO[6]),\n\t.DOA7(DO[7]),\n\t.DOA8(DO[8]),\n\t.DOB0(DO[9]),\n\t.DOB1(DO[10]),\n\t.DOB2(DO[11]),\n\t.DOB3(DO[12]),\n\t.DOB4(DO[13]),\n\t.DOB5(DO[14]),\n\t.DOB6(DO[15]),\n\t.DOB7(DO[16]),\n\t.DOB8(DO[17]),\n);\n\nendmodule\n",
+            "brams_map_nexus.v": "module $__NX_DP16K_ (...);\n\nparameter INIT = 0;\n\nparameter PORT_A_OPTION_RESETMODE = \"SYNC\";\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_WR_BE_WIDTH = 2;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\nparameter PORT_B_OPTION_RESETMODE = \"SYNC\";\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_WR_BE_WIDTH = 2;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i;\n\tinit_slice = 0;\n\tfor (i = 0; i < 32; i = i + 1) begin\n\t\tinit_slice[i*10+:9] = INIT[(idx * 32 + i) * 9+:9];\n\tend\nendfunction\n\nwire [17:0] DOA;\nwire [17:0] DOB;\nwire [17:0] DIA = PORT_A_WR_DATA;\nwire [17:0] DIB = PORT_B_WR_DATA;\nwire [13:0] ADA;\nwire [13:0] ADB;\n\ngenerate\n\ncase(PORT_A_WIDTH)\n1: assign ADA = PORT_A_ADDR;\n2: assign ADA = {PORT_A_ADDR[13:1], 1'b1};\n4: assign ADA = {PORT_A_ADDR[13:2], 2'b11};\n9: assign ADA = {PORT_A_ADDR[13:3], 3'b111};\n18: assign ADA = {PORT_A_ADDR[13:4], 2'b11, PORT_A_WR_BE};\nendcase\n\ncase(PORT_B_WIDTH)\n1: assign ADB = PORT_B_ADDR;\n2: assign ADB = {PORT_B_ADDR[13:1], 1'b1};\n4: assign ADB = {PORT_B_ADDR[13:2], 2'b11};\n9: assign ADB = {PORT_B_ADDR[13:3], 3'b111};\n18: assign ADB = {PORT_B_ADDR[13:4], 2'b11, PORT_B_WR_BE};\nendcase\n\nendgenerate\n\nassign PORT_A_RD_DATA = DOA;\nassign PORT_B_RD_DATA = DOB;\n\nDP16K #(\n\t.INITVAL_00($sformatf(\"0x%080x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%080x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%080x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%080x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%080x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%080x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%080x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%080x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%080x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%080x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%080x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%080x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%080x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%080x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%080x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%080x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%080x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%080x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%080x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%080x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%080x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%080x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%080x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%080x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%080x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%080x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%080x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%080x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%080x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%080x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%080x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%080x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%080x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%080x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%080x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%080x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%080x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%080x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%080x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%080x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%080x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%080x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%080x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%080x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%080x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%080x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%080x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%080x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%080x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%080x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%080x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%080x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%080x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%080x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%080x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%080x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%080x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%080x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%080x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%080x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%080x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%080x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%080x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%080x\", init_slice('h3f))),\n\t.DATA_WIDTH_A($sformatf(\"X%0d\", PORT_A_WIDTH)),\n\t.DATA_WIDTH_B($sformatf(\"X%0d\", PORT_B_WIDTH)),\n\t.OUTREG_A(\"BYPASSED\"),\n\t.OUTREG_B(\"BYPASSED\"),\n\t.RESETMODE_A(PORT_A_OPTION_RESETMODE),\n\t.RESETMODE_B(PORT_B_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE_A(PORT_A_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE_B(PORT_B_OPTION_RESETMODE),\n\t.CSDECODE_A(\"111\"),\n\t.CSDECODE_B(\"111\"),\n\t.GSR(\"DISABLED\"),\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_A_CLK),\n\t.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),\n\t.CEA(PORT_A_CLK_EN),\n\t.RSTA(PORT_A_OPTION_RESETMODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t.CSA(3'b111),\n\t.DIA(DIA),\n\t.DOA(DOA),\n\t.ADA(ADA),\n\n\t.CLKB(PORT_B_CLK),\n\t.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),\n\t.CEB(PORT_B_CLK_EN),\n\t.RSTB(PORT_B_OPTION_RESETMODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t.CSB(3'b111),\n\t.ADB(ADB),\n\t.DIB(DIB),\n\t.DOB(DOB),\n);\n\nendmodule\n\n\nmodule $__NX_PDP16K_ (...);\n\nparameter INIT = 0;\nparameter OPTION_SAME_CLOCK = 1;\n\nparameter PORT_R_WIDTH = 36;\nparameter PORT_R_OPTION_RESETMODE = \"SYNC\";\n\ninput CLK_C;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\nparameter PORT_W_WIDTH = 36;\nparameter PORT_W_WR_EN_WIDTH = 4;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i;\n\tinit_slice = 0;\n\tfor (i = 0; i < 32; i = i + 1) begin\n\t\tinit_slice[i*10+:9] = INIT[(idx * 32 + i) * 9+:9];\n\tend\nendfunction\n\nwire [35:0] DI = PORT_W_WR_DATA;\nwire [35:0] DO;\n\nassign PORT_R_RD_DATA = DO;\n\nwire [13:0] ADW;\nwire [13:0] ADR;\n\ngenerate\n\ncase (PORT_W_WIDTH)\n1: assign ADW = PORT_W_ADDR;\n2: assign ADW = {PORT_W_ADDR[13:1], 1'b1};\n4: assign ADW = {PORT_W_ADDR[13:2], 2'b11};\n9: assign ADW = {PORT_W_ADDR[13:3], 3'b111};\n18: assign ADW = {PORT_W_ADDR[13:4], 2'b11, PORT_W_WR_EN};\n36: assign ADW = {PORT_W_ADDR[13:5], 1'b1, PORT_W_WR_EN};\nendcase\n\ncase (PORT_R_WIDTH)\n1: assign ADR = PORT_R_ADDR;\n2: assign ADR = {PORT_R_ADDR[13:1], 1'b1};\n4: assign ADR = {PORT_R_ADDR[13:2], 2'b11};\n9: assign ADR = {PORT_R_ADDR[13:3], 3'b111};\n18: assign ADR = {PORT_R_ADDR[13:4], 4'b1111};\n36: assign ADR = {PORT_R_ADDR[13:5], 5'b11111};\nendcase\n\nif (OPTION_SAME_CLOCK) begin\n\nPDPSC16K #(\n\t.INITVAL_00($sformatf(\"0x%080x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%080x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%080x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%080x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%080x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%080x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%080x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%080x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%080x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%080x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%080x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%080x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%080x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%080x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%080x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%080x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%080x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%080x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%080x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%080x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%080x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%080x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%080x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%080x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%080x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%080x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%080x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%080x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%080x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%080x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%080x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%080x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%080x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%080x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%080x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%080x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%080x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%080x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%080x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%080x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%080x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%080x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%080x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%080x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%080x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%080x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%080x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%080x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%080x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%080x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%080x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%080x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%080x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%080x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%080x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%080x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%080x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%080x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%080x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%080x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%080x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%080x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%080x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%080x\", init_slice('h3f))),\n\t.DATA_WIDTH_W($sformatf(\"X%0d\", PORT_W_WIDTH)),\n\t.DATA_WIDTH_R($sformatf(\"X%0d\", PORT_R_WIDTH)),\n\t.OUTREG(\"BYPASSED\"),\n\t.RESETMODE(PORT_R_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE),\n\t.CSDECODE_W(\"111\"),\n\t.CSDECODE_R(\"111\"),\n\t.ECC(\"DISABLED\"),\n\t.GSR(\"DISABLED\"),\n) _TECHMAP_REPLACE_ (\n\t.CLK(CLK_C),\n\n\t.CEW(PORT_W_CLK_EN & (|PORT_W_WR_EN)),\n\t.CSW(3'b111),\n\t.ADW(ADW),\n\t.DI(DI),\n\n\t.CER(PORT_R_CLK_EN),\n\t.RST(PORT_R_OPTION_RESETMODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST),\n\t.CSR(3'b111),\n\t.ADR(ADR),\n\t.DO(DO),\n);\n\nend else begin\n\nPDP16K #(\n\t.INITVAL_00($sformatf(\"0x%080x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%080x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%080x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%080x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%080x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%080x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%080x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%080x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%080x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%080x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%080x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%080x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%080x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%080x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%080x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%080x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%080x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%080x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%080x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%080x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%080x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%080x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%080x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%080x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%080x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%080x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%080x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%080x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%080x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%080x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%080x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%080x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%080x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%080x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%080x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%080x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%080x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%080x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%080x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%080x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%080x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%080x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%080x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%080x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%080x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%080x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%080x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%080x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%080x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%080x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%080x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%080x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%080x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%080x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%080x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%080x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%080x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%080x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%080x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%080x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%080x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%080x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%080x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%080x\", init_slice('h3f))),\n\t.DATA_WIDTH_W($sformatf(\"X%0d\", PORT_W_WIDTH)),\n\t.DATA_WIDTH_R($sformatf(\"X%0d\", PORT_R_WIDTH)),\n\t.OUTREG(\"BYPASSED\"),\n\t.RESETMODE(PORT_R_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE),\n\t.CSDECODE_W(\"111\"),\n\t.CSDECODE_R(\"111\"),\n\t.ECC(\"DISABLED\"),\n\t.GSR(\"DISABLED\"),\n) _TECHMAP_REPLACE_ (\n\t.CLKW(PORT_W_CLK),\n\t.CEW(PORT_W_CLK_EN & (|PORT_W_WR_EN)),\n\t.CSW(3'b111),\n\t.ADW(ADW),\n\t.DI(DI),\n\n\t.CLKR(PORT_R_CLK),\n\t.CER(PORT_R_CLK_EN),\n\t.RST(PORT_R_OPTION_RESETMODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST),\n\t.CSR(3'b111),\n\t.ADR(ADR),\n\t.DO(DO),\n);\n\nend\n\nendgenerate\n\nendmodule\n",
+            "brams_nexus.txt": "ram block $__NX_DP16K_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 129;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\trdwr no_change;\n\t\tportoption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\tportoption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n}\n\nram block $__NX_PDP16K_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\toption \"SAME_CLOCK\" 1 cost 128;\n\toption \"SAME_CLOCK\" 0 cost 129;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\toption \"SAME_CLOCK\" 1 clock posedge \"C\";\n\t\toption \"SAME_CLOCK\" 0 clock posedge;\n\t\tclken;\n\t\tportoption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\tportoption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\toption \"SAME_CLOCK\" 1 clock posedge \"C\";\n\t\toption \"SAME_CLOCK\" 0 clock posedge;\n\t\tclken;\n\t\toption \"SAME_CLOCK\" 1 wrtrans all old;\n\t}\n}\n",
             "ccu2c_sim.vh": "// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule CCU2C(\n\t(* abc9_carry *)\n\tinput  CIN,\n\tinput  A0, B0, C0, D0, A1, B1, C1, D1,\n\toutput S0, S1,\n\t(* abc9_carry *)\n\toutput COUT\n);\n\tparameter [15:0] INIT0 = 16'h0000;\n\tparameter [15:0] INIT1 = 16'h0000;\n\tparameter INJECT1_0 = \"YES\";\n\tparameter INJECT1_1 = \"YES\";\n\n\t// First half\n\twire LUT4_0, LUT2_0;\n\tLUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));\n\tLUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));\n\twire gated_cin_0 = (INJECT1_0 == \"YES\") ? 1'b0 : CIN;\n\tassign S0 = LUT4_0 ^ gated_cin_0;\n\n\twire gated_lut2_0 = (INJECT1_0 == \"YES\") ? 1'b0 : LUT2_0;\n\twire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);\n\n\t// Second half\n\twire LUT4_1, LUT2_1;\n\tLUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));\n\tLUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));\n\twire gated_cin_1 = (INJECT1_1 == \"YES\") ? 1'b0 : cout_0;\n\tassign S1 = LUT4_1 ^ gated_cin_1;\n\n\twire gated_lut2_1 = (INJECT1_1 == \"YES\") ? 1'b0 : LUT2_1;\n\tassign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);\n\n\tspecify\n\t\t(A0 => S0) = 379;\n\t\t(B0 => S0) = 379;\n\t\t(C0 => S0) = 275;\n\t\t(D0 => S0) = 141;\n\t\t(CIN => S0) = 257;\n\t\t(A0 => S1) = 630;\n\t\t(B0 => S1) = 630;\n\t\t(C0 => S1) = 526;\n\t\t(D0 => S1) = 392;\n\t\t(A1 => S1) = 379;\n\t\t(B1 => S1) = 379;\n\t\t(C1 => S1) = 275;\n\t\t(D1 => S1) = 141;\n\t\t(CIN => S1) = 273;\n\t\t(A0 => COUT) = 516;\n\t\t(B0 => COUT) = 516;\n\t\t(C0 => COUT) = 412;\n\t\t(D0 => COUT) = 278;\n\t\t(A1 => COUT) = 516;\n\t\t(B1 => COUT) = 516;\n\t\t(C1 => COUT) = 412;\n\t\t(D1 => COUT) = 278;\n\t\t(CIN => COUT) = 43;\n\tendspecify\nendmodule\n",
             "ccu2d_sim.vh": "// ---------------------------------------\n(* lib_whitebox *)\nmodule CCU2D (\n\tinput  CIN,\n\tinput  A0, B0, C0, D0, A1, B1, C1, D1,\n\toutput S0, S1,\n\toutput COUT\n);\n\tparameter [15:0] INIT0 = 16'h0000;\n\tparameter [15:0] INIT1 = 16'h0000;\n\tparameter INJECT1_0 = \"YES\";\n\tparameter INJECT1_1 = \"YES\";\n\n\t// First half\n\twire LUT4_0, LUT2_0;\n\tLUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));\n\tLUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));\n\twire gated_cin_0 = (INJECT1_0 == \"YES\") ? 1'b0 : CIN;\n\tassign S0 = LUT4_0 ^ gated_cin_0;\n\n\twire gated_lut2_0 = (INJECT1_0 == \"YES\") ? 1'b0 : LUT2_0;\n\twire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);\n\n\t// Second half\n\twire LUT4_1, LUT2_1;\n\tLUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));\n\tLUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));\n\twire gated_cin_1 = (INJECT1_1 == \"YES\") ? 1'b0 : cout_0;\n\tassign S1 = LUT4_1 ^ gated_cin_1;\n\n\twire gated_lut2_1 = (INJECT1_1 == \"YES\") ? 1'b0 : LUT2_1;\n\tassign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);\nendmodule\n",
-            "cells_bb_ecp5.v": "// Created by cells_xtra.py from Lattice models\n\n(* blackbox *) (* keep *)\nmodule GSR (...);\n    input GSR;\nendmodule\n\n(* blackbox *)\nmodule PUR (...);\n    parameter RST_PULSE = 1;\n    input PUR;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule SGSR (...);\n    input GSR;\n    input CLK;\nendmodule\n\n(* blackbox *)\nmodule DP16KD (...);\n    parameter CLKAMUX = \"CLKA\";\n    parameter CLKBMUX = \"CLKB\";\n    parameter DATA_WIDTH_A = 18;\n    parameter DATA_WIDTH_B = 18;\n    parameter REGMODE_A = \"NOREG\";\n    parameter REGMODE_B = \"NOREG\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter WRITEMODE_A = \"NORMAL\";\n    parameter WRITEMODE_B = \"NORMAL\";\n    parameter CSDECODE_A = \"0b000\";\n    parameter CSDECODE_B = \"0b000\";\n    parameter GSR = \"ENABLED\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INIT_DATA = \"STATIC\";\n    input DIA17;\n    input DIA16;\n    input DIA15;\n    input DIA14;\n    input DIA13;\n    input DIA12;\n    input DIA11;\n    input DIA10;\n    input DIA9;\n    input DIA8;\n    input DIA7;\n    input DIA6;\n    input DIA5;\n    input DIA4;\n    input DIA3;\n    input DIA2;\n    input DIA1;\n    input DIA0;\n    input ADA13;\n    input ADA12;\n    input ADA11;\n    input ADA10;\n    input ADA9;\n    input ADA8;\n    input ADA7;\n    input ADA6;\n    input ADA5;\n    input ADA4;\n    input ADA3;\n    input ADA2;\n    input ADA1;\n    input ADA0;\n    input CEA;\n    input OCEA;\n    input CLKA;\n    input WEA;\n    input CSA2;\n    input CSA1;\n    input CSA0;\n    input RSTA;\n    input DIB17;\n    input DIB16;\n    input DIB15;\n    input DIB14;\n    input DIB13;\n    input DIB12;\n    input DIB11;\n    input DIB10;\n    input DIB9;\n    input DIB8;\n    input DIB7;\n    input DIB6;\n    input DIB5;\n    input DIB4;\n    input DIB3;\n    input DIB2;\n    input DIB1;\n    input DIB0;\n    input ADB13;\n    input ADB12;\n    input ADB11;\n    input ADB10;\n    input ADB9;\n    input ADB8;\n    input ADB7;\n    input ADB6;\n    input ADB5;\n    input ADB4;\n    input ADB3;\n    input ADB2;\n    input ADB1;\n    input ADB0;\n    input CEB;\n    input OCEB;\n    input CLKB;\n    input WEB;\n    input CSB2;\n    input CSB1;\n    input CSB0;\n    input RSTB;\n    output DOA17;\n    output DOA16;\n    output DOA15;\n    output DOA14;\n    output DOA13;\n    output DOA12;\n    output DOA11;\n    output DOA10;\n    output DOA9;\n    output DOA8;\n    output DOA7;\n    output DOA6;\n    output DOA5;\n    output DOA4;\n    output DOA3;\n    output DOA2;\n    output DOA1;\n    output DOA0;\n    output DOB17;\n    output DOB16;\n    output DOB15;\n    output DOB14;\n    output DOB13;\n    output DOB12;\n    output DOB11;\n    output DOB10;\n    output DOB9;\n    output DOB8;\n    output DOB7;\n    output DOB6;\n    output DOB5;\n    output DOB4;\n    output DOB3;\n    output DOB2;\n    output DOB1;\n    output DOB0;\nendmodule\n\n(* blackbox *)\nmodule PDPW16KD (...);\n    parameter CLKRMUX = \"CLKR\";\n    parameter CLKWMUX = \"CLKW\";\n    parameter DATA_WIDTH_W = 36;\n    parameter DATA_WIDTH_R = 36;\n    parameter GSR = \"ENABLED\";\n    parameter REGMODE = \"NOREG\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter CSDECODE_W = \"0b000\";\n    parameter CSDECODE_R = \"0b000\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INIT_DATA = \"STATIC\";\n    input DI35;\n    input DI34;\n    input DI33;\n    input DI32;\n    input DI31;\n    input DI30;\n    input DI29;\n    input DI28;\n    input DI27;\n    input DI26;\n    input DI25;\n    input DI24;\n    input DI23;\n    input DI22;\n    input DI21;\n    input DI20;\n    input DI19;\n    input DI18;\n    input DI17;\n    input DI16;\n    input DI15;\n    input DI14;\n    input DI13;\n    input DI12;\n    input DI11;\n    input DI10;\n    input DI9;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input ADW8;\n    input ADW7;\n    input ADW6;\n    input ADW5;\n    input ADW4;\n    input ADW3;\n    input ADW2;\n    input ADW1;\n    input ADW0;\n    input BE3;\n    input BE2;\n    input BE1;\n    input BE0;\n    input CEW;\n    input CLKW;\n    input CSW2;\n    input CSW1;\n    input CSW0;\n    input ADR13;\n    input ADR12;\n    input ADR11;\n    input ADR10;\n    input ADR9;\n    input ADR8;\n    input ADR7;\n    input ADR6;\n    input ADR5;\n    input ADR4;\n    input ADR3;\n    input ADR2;\n    input ADR1;\n    input ADR0;\n    input CER;\n    input OCER;\n    input CLKR;\n    input CSR2;\n    input CSR1;\n    input CSR0;\n    input RST;\n    output DO35;\n    output DO34;\n    output DO33;\n    output DO32;\n    output DO31;\n    output DO30;\n    output DO29;\n    output DO28;\n    output DO27;\n    output DO26;\n    output DO25;\n    output DO24;\n    output DO23;\n    output DO22;\n    output DO21;\n    output DO20;\n    output DO19;\n    output DO18;\n    output DO17;\n    output DO16;\n    output DO15;\n    output DO14;\n    output DO13;\n    output DO12;\n    output DO11;\n    output DO10;\n    output DO9;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule MULT18X18D (...);\n    parameter REG_INPUTA_CLK = \"NONE\";\n    parameter REG_INPUTA_CE = \"CE0\";\n    parameter REG_INPUTA_RST = \"RST0\";\n    parameter REG_INPUTB_CLK = \"NONE\";\n    parameter REG_INPUTB_CE = \"CE0\";\n    parameter REG_INPUTB_RST = \"RST0\";\n    parameter REG_INPUTC_CLK = \"NONE\";\n    parameter REG_INPUTC_CE = \"CE0\";\n    parameter REG_INPUTC_RST = \"RST0\";\n    parameter REG_PIPELINE_CLK = \"NONE\";\n    parameter REG_PIPELINE_CE = \"CE0\";\n    parameter REG_PIPELINE_RST = \"RST0\";\n    parameter REG_OUTPUT_CLK = \"NONE\";\n    parameter REG_OUTPUT_CE = \"CE0\";\n    parameter REG_OUTPUT_RST = \"RST0\";\n    parameter CLK0_DIV = \"ENABLED\";\n    parameter CLK1_DIV = \"ENABLED\";\n    parameter CLK2_DIV = \"ENABLED\";\n    parameter CLK3_DIV = \"ENABLED\";\n    parameter HIGHSPEED_CLK = \"NONE\";\n    parameter GSR = \"ENABLED\";\n    parameter CAS_MATCH_REG = \"FALSE\";\n    parameter SOURCEB_MODE = \"B_SHIFT\";\n    parameter MULT_BYPASS = \"DISABLED\";\n    parameter RESETMODE = \"SYNC\";\n    input A17;\n    input A16;\n    input A15;\n    input A14;\n    input A13;\n    input A12;\n    input A11;\n    input A10;\n    input A9;\n    input A8;\n    input A7;\n    input A6;\n    input A5;\n    input A4;\n    input A3;\n    input A2;\n    input A1;\n    input A0;\n    input B17;\n    input B16;\n    input B15;\n    input B14;\n    input B13;\n    input B12;\n    input B11;\n    input B10;\n    input B9;\n    input B8;\n    input B7;\n    input B6;\n    input B5;\n    input B4;\n    input B3;\n    input B2;\n    input B1;\n    input B0;\n    input C17;\n    input C16;\n    input C15;\n    input C14;\n    input C13;\n    input C12;\n    input C11;\n    input C10;\n    input C9;\n    input C8;\n    input C7;\n    input C6;\n    input C5;\n    input C4;\n    input C3;\n    input C2;\n    input C1;\n    input C0;\n    input SIGNEDA;\n    input SIGNEDB;\n    input SOURCEA;\n    input SOURCEB;\n    input CLK3;\n    input CLK2;\n    input CLK1;\n    input CLK0;\n    input CE3;\n    input CE2;\n    input CE1;\n    input CE0;\n    input RST3;\n    input RST2;\n    input RST1;\n    input RST0;\n    input SRIA17;\n    input SRIA16;\n    input SRIA15;\n    input SRIA14;\n    input SRIA13;\n    input SRIA12;\n    input SRIA11;\n    input SRIA10;\n    input SRIA9;\n    input SRIA8;\n    input SRIA7;\n    input SRIA6;\n    input SRIA5;\n    input SRIA4;\n    input SRIA3;\n    input SRIA2;\n    input SRIA1;\n    input SRIA0;\n    input SRIB17;\n    input SRIB16;\n    input SRIB15;\n    input SRIB14;\n    input SRIB13;\n    input SRIB12;\n    input SRIB11;\n    input SRIB10;\n    input SRIB9;\n    input SRIB8;\n    input SRIB7;\n    input SRIB6;\n    input SRIB5;\n    input SRIB4;\n    input SRIB3;\n    input SRIB2;\n    input SRIB1;\n    input SRIB0;\n    output SROA17;\n    output SROA16;\n    output SROA15;\n    output SROA14;\n    output SROA13;\n    output SROA12;\n    output SROA11;\n    output SROA10;\n    output SROA9;\n    output SROA8;\n    output SROA7;\n    output SROA6;\n    output SROA5;\n    output SROA4;\n    output SROA3;\n    output SROA2;\n    output SROA1;\n    output SROA0;\n    output SROB17;\n    output SROB16;\n    output SROB15;\n    output SROB14;\n    output SROB13;\n    output SROB12;\n    output SROB11;\n    output SROB10;\n    output SROB9;\n    output SROB8;\n    output SROB7;\n    output SROB6;\n    output SROB5;\n    output SROB4;\n    output SROB3;\n    output SROB2;\n    output SROB1;\n    output SROB0;\n    output ROA17;\n    output ROA16;\n    output ROA15;\n    output ROA14;\n    output ROA13;\n    output ROA12;\n    output ROA11;\n    output ROA10;\n    output ROA9;\n    output ROA8;\n    output ROA7;\n    output ROA6;\n    output ROA5;\n    output ROA4;\n    output ROA3;\n    output ROA2;\n    output ROA1;\n    output ROA0;\n    output ROB17;\n    output ROB16;\n    output ROB15;\n    output ROB14;\n    output ROB13;\n    output ROB12;\n    output ROB11;\n    output ROB10;\n    output ROB9;\n    output ROB8;\n    output ROB7;\n    output ROB6;\n    output ROB5;\n    output ROB4;\n    output ROB3;\n    output ROB2;\n    output ROB1;\n    output ROB0;\n    output ROC17;\n    output ROC16;\n    output ROC15;\n    output ROC14;\n    output ROC13;\n    output ROC12;\n    output ROC11;\n    output ROC10;\n    output ROC9;\n    output ROC8;\n    output ROC7;\n    output ROC6;\n    output ROC5;\n    output ROC4;\n    output ROC3;\n    output ROC2;\n    output ROC1;\n    output ROC0;\n    output P35;\n    output P34;\n    output P33;\n    output P32;\n    output P31;\n    output P30;\n    output P29;\n    output P28;\n    output P27;\n    output P26;\n    output P25;\n    output P24;\n    output P23;\n    output P22;\n    output P21;\n    output P20;\n    output P19;\n    output P18;\n    output P17;\n    output P16;\n    output P15;\n    output P14;\n    output P13;\n    output P12;\n    output P11;\n    output P10;\n    output P9;\n    output P8;\n    output P7;\n    output P6;\n    output P5;\n    output P4;\n    output P3;\n    output P2;\n    output P1;\n    output P0;\n    output SIGNEDP;\nendmodule\n\n(* blackbox *)\nmodule ALU54B (...);\n    parameter REG_INPUTC0_CLK = \"NONE\";\n    parameter REG_INPUTC0_CE = \"CE0\";\n    parameter REG_INPUTC0_RST = \"RST0\";\n    parameter REG_INPUTC1_CLK = \"NONE\";\n    parameter REG_INPUTC1_CE = \"CE0\";\n    parameter REG_INPUTC1_RST = \"RST0\";\n    parameter REG_OPCODEOP0_0_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_0_CE = \"CE0\";\n    parameter REG_OPCODEOP0_0_RST = \"RST0\";\n    parameter REG_OPCODEOP1_0_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_1_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_1_CE = \"CE0\";\n    parameter REG_OPCODEOP0_1_RST = \"RST0\";\n    parameter REG_OPCODEOP1_1_CLK = \"NONE\";\n    parameter REG_OPCODEIN_0_CLK = \"NONE\";\n    parameter REG_OPCODEIN_0_CE = \"CE0\";\n    parameter REG_OPCODEIN_0_RST = \"RST0\";\n    parameter REG_OPCODEIN_1_CLK = \"NONE\";\n    parameter REG_OPCODEIN_1_CE = \"CE0\";\n    parameter REG_OPCODEIN_1_RST = \"RST0\";\n    parameter REG_OUTPUT0_CLK = \"NONE\";\n    parameter REG_OUTPUT0_CE = \"CE0\";\n    parameter REG_OUTPUT0_RST = \"RST0\";\n    parameter REG_OUTPUT1_CLK = \"NONE\";\n    parameter REG_OUTPUT1_CE = \"CE0\";\n    parameter REG_OUTPUT1_RST = \"RST0\";\n    parameter REG_FLAG_CLK = \"NONE\";\n    parameter REG_FLAG_CE = \"CE0\";\n    parameter REG_FLAG_RST = \"RST0\";\n    parameter MCPAT_SOURCE = \"STATIC\";\n    parameter MASKPAT_SOURCE = \"STATIC\";\n    parameter MASK01 = \"0x00000000000000\";\n    parameter REG_INPUTCFB_CLK = \"NONE\";\n    parameter REG_INPUTCFB_CE = \"CE0\";\n    parameter REG_INPUTCFB_RST = \"RST0\";\n    parameter CLK0_DIV = \"ENABLED\";\n    parameter CLK1_DIV = \"ENABLED\";\n    parameter CLK2_DIV = \"ENABLED\";\n    parameter CLK3_DIV = \"ENABLED\";\n    parameter MCPAT = \"0x00000000000000\";\n    parameter MASKPAT = \"0x00000000000000\";\n    parameter RNDPAT = \"0x00000000000000\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter MULT9_MODE = \"DISABLED\";\n    parameter FORCE_ZERO_BARREL_SHIFT = \"DISABLED\";\n    parameter LEGACY = \"DISABLED\";\n    input CE3;\n    input CE2;\n    input CE1;\n    input CE0;\n    input CLK3;\n    input CLK2;\n    input CLK1;\n    input CLK0;\n    input RST3;\n    input RST2;\n    input RST1;\n    input RST0;\n    input SIGNEDIA;\n    input SIGNEDIB;\n    input SIGNEDCIN;\n    input A35;\n    input A34;\n    input A33;\n    input A32;\n    input A31;\n    input A30;\n    input A29;\n    input A28;\n    input A27;\n    input A26;\n    input A25;\n    input A24;\n    input A23;\n    input A22;\n    input A21;\n    input A20;\n    input A19;\n    input A18;\n    input A17;\n    input A16;\n    input A15;\n    input A14;\n    input A13;\n    input A12;\n    input A11;\n    input A10;\n    input A9;\n    input A8;\n    input A7;\n    input A6;\n    input A5;\n    input A4;\n    input A3;\n    input A2;\n    input A1;\n    input A0;\n    input B35;\n    input B34;\n    input B33;\n    input B32;\n    input B31;\n    input B30;\n    input B29;\n    input B28;\n    input B27;\n    input B26;\n    input B25;\n    input B24;\n    input B23;\n    input B22;\n    input B21;\n    input B20;\n    input B19;\n    input B18;\n    input B17;\n    input B16;\n    input B15;\n    input B14;\n    input B13;\n    input B12;\n    input B11;\n    input B10;\n    input B9;\n    input B8;\n    input B7;\n    input B6;\n    input B5;\n    input B4;\n    input B3;\n    input B2;\n    input B1;\n    input B0;\n    input C53;\n    input C52;\n    input C51;\n    input C50;\n    input C49;\n    input C48;\n    input C47;\n    input C46;\n    input C45;\n    input C44;\n    input C43;\n    input C42;\n    input C41;\n    input C40;\n    input C39;\n    input C38;\n    input C37;\n    input C36;\n    input C35;\n    input C34;\n    input C33;\n    input C32;\n    input C31;\n    input C30;\n    input C29;\n    input C28;\n    input C27;\n    input C26;\n    input C25;\n    input C24;\n    input C23;\n    input C22;\n    input C21;\n    input C20;\n    input C19;\n    input C18;\n    input C17;\n    input C16;\n    input C15;\n    input C14;\n    input C13;\n    input C12;\n    input C11;\n    input C10;\n    input C9;\n    input C8;\n    input C7;\n    input C6;\n    input C5;\n    input C4;\n    input C3;\n    input C2;\n    input C1;\n    input C0;\n    input CFB53;\n    input CFB52;\n    input CFB51;\n    input CFB50;\n    input CFB49;\n    input CFB48;\n    input CFB47;\n    input CFB46;\n    input CFB45;\n    input CFB44;\n    input CFB43;\n    input CFB42;\n    input CFB41;\n    input CFB40;\n    input CFB39;\n    input CFB38;\n    input CFB37;\n    input CFB36;\n    input CFB35;\n    input CFB34;\n    input CFB33;\n    input CFB32;\n    input CFB31;\n    input CFB30;\n    input CFB29;\n    input CFB28;\n    input CFB27;\n    input CFB26;\n    input CFB25;\n    input CFB24;\n    input CFB23;\n    input CFB22;\n    input CFB21;\n    input CFB20;\n    input CFB19;\n    input CFB18;\n    input CFB17;\n    input CFB16;\n    input CFB15;\n    input CFB14;\n    input CFB13;\n    input CFB12;\n    input CFB11;\n    input CFB10;\n    input CFB9;\n    input CFB8;\n    input CFB7;\n    input CFB6;\n    input CFB5;\n    input CFB4;\n    input CFB3;\n    input CFB2;\n    input CFB1;\n    input CFB0;\n    input MA35;\n    input MA34;\n    input MA33;\n    input MA32;\n    input MA31;\n    input MA30;\n    input MA29;\n    input MA28;\n    input MA27;\n    input MA26;\n    input MA25;\n    input MA24;\n    input MA23;\n    input MA22;\n    input MA21;\n    input MA20;\n    input MA19;\n    input MA18;\n    input MA17;\n    input MA16;\n    input MA15;\n    input MA14;\n    input MA13;\n    input MA12;\n    input MA11;\n    input MA10;\n    input MA9;\n    input MA8;\n    input MA7;\n    input MA6;\n    input MA5;\n    input MA4;\n    input MA3;\n    input MA2;\n    input MA1;\n    input MA0;\n    input MB35;\n    input MB34;\n    input MB33;\n    input MB32;\n    input MB31;\n    input MB30;\n    input MB29;\n    input MB28;\n    input MB27;\n    input MB26;\n    input MB25;\n    input MB24;\n    input MB23;\n    input MB22;\n    input MB21;\n    input MB20;\n    input MB19;\n    input MB18;\n    input MB17;\n    input MB16;\n    input MB15;\n    input MB14;\n    input MB13;\n    input MB12;\n    input MB11;\n    input MB10;\n    input MB9;\n    input MB8;\n    input MB7;\n    input MB6;\n    input MB5;\n    input MB4;\n    input MB3;\n    input MB2;\n    input MB1;\n    input MB0;\n    input CIN53;\n    input CIN52;\n    input CIN51;\n    input CIN50;\n    input CIN49;\n    input CIN48;\n    input CIN47;\n    input CIN46;\n    input CIN45;\n    input CIN44;\n    input CIN43;\n    input CIN42;\n    input CIN41;\n    input CIN40;\n    input CIN39;\n    input CIN38;\n    input CIN37;\n    input CIN36;\n    input CIN35;\n    input CIN34;\n    input CIN33;\n    input CIN32;\n    input CIN31;\n    input CIN30;\n    input CIN29;\n    input CIN28;\n    input CIN27;\n    input CIN26;\n    input CIN25;\n    input CIN24;\n    input CIN23;\n    input CIN22;\n    input CIN21;\n    input CIN20;\n    input CIN19;\n    input CIN18;\n    input CIN17;\n    input CIN16;\n    input CIN15;\n    input CIN14;\n    input CIN13;\n    input CIN12;\n    input CIN11;\n    input CIN10;\n    input CIN9;\n    input CIN8;\n    input CIN7;\n    input CIN6;\n    input CIN5;\n    input CIN4;\n    input CIN3;\n    input CIN2;\n    input CIN1;\n    input CIN0;\n    input OP10;\n    input OP9;\n    input OP8;\n    input OP7;\n    input OP6;\n    input OP5;\n    input OP4;\n    input OP3;\n    input OP2;\n    input OP1;\n    input OP0;\n    output R53;\n    output R52;\n    output R51;\n    output R50;\n    output R49;\n    output R48;\n    output R47;\n    output R46;\n    output R45;\n    output R44;\n    output R43;\n    output R42;\n    output R41;\n    output R40;\n    output R39;\n    output R38;\n    output R37;\n    output R36;\n    output R35;\n    output R34;\n    output R33;\n    output R32;\n    output R31;\n    output R30;\n    output R29;\n    output R28;\n    output R27;\n    output R26;\n    output R25;\n    output R24;\n    output R23;\n    output R22;\n    output R21;\n    output R20;\n    output R19;\n    output R18;\n    output R17;\n    output R16;\n    output R15;\n    output R14;\n    output R13;\n    output R12;\n    output R11;\n    output R10;\n    output R9;\n    output R8;\n    output R7;\n    output R6;\n    output R5;\n    output R4;\n    output R3;\n    output R2;\n    output R1;\n    output R0;\n    output CO53;\n    output CO52;\n    output CO51;\n    output CO50;\n    output CO49;\n    output CO48;\n    output CO47;\n    output CO46;\n    output CO45;\n    output CO44;\n    output CO43;\n    output CO42;\n    output CO41;\n    output CO40;\n    output CO39;\n    output CO38;\n    output CO37;\n    output CO36;\n    output CO35;\n    output CO34;\n    output CO33;\n    output CO32;\n    output CO31;\n    output CO30;\n    output CO29;\n    output CO28;\n    output CO27;\n    output CO26;\n    output CO25;\n    output CO24;\n    output CO23;\n    output CO22;\n    output CO21;\n    output CO20;\n    output CO19;\n    output CO18;\n    output CO17;\n    output CO16;\n    output CO15;\n    output CO14;\n    output CO13;\n    output CO12;\n    output CO11;\n    output CO10;\n    output CO9;\n    output CO8;\n    output CO7;\n    output CO6;\n    output CO5;\n    output CO4;\n    output CO3;\n    output CO2;\n    output CO1;\n    output CO0;\n    output EQZ;\n    output EQZM;\n    output EQOM;\n    output EQPAT;\n    output EQPATB;\n    output OVER;\n    output UNDER;\n    output OVERUNDER;\n    output SIGNEDR;\nendmodule\n\n(* blackbox *)\nmodule CLKDIVF (...);\n    parameter GSR = \"DISABLED\";\n    parameter DIV = \"2.0\";\n    input CLKI;\n    input RST;\n    input ALIGNWD;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule PCSCLKDIV (...);\n    parameter GSR = \"DISABLED\";\n    input CLKI;\n    input RST;\n    input SEL2;\n    input SEL1;\n    input SEL0;\n    output CDIV1;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule DCSC (...);\n    parameter DCSMODE = \"POS\";\n    input CLK1;\n    input CLK0;\n    input SEL1;\n    input SEL0;\n    input MODESEL;\n    output DCSOUT;\nendmodule\n\n(* blackbox *)\nmodule DCCA (...);\n    input CLKI;\n    input CE;\n    output CLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKSYNCB (...);\n    input ECLKI;\n    input STOP;\n    output ECLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKBRIDGECS (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output ECSOUT;\nendmodule\n\n(* blackbox *)\nmodule DELAYF (...);\n    parameter DEL_MODE = \"USER_DEFINED\";\n    parameter DEL_VALUE = 0;\n    input A;\n    input LOADN;\n    input MOVE;\n    input DIRECTION;\n    output Z;\n    output CFLAG;\nendmodule\n\n(* blackbox *)\nmodule DELAYG (...);\n    parameter DEL_MODE = \"USER_DEFINED\";\n    parameter DEL_VALUE = 0;\n    input A;\n    output Z;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule USRMCLK (...);\n    input USRMCLKI;\n    input USRMCLKTS;\nendmodule\n\n(* blackbox *)\nmodule DQSBUFM (...);\n    parameter DQS_LI_DEL_VAL = 4;\n    parameter DQS_LI_DEL_ADJ = \"FACTORYONLY\";\n    parameter DQS_LO_DEL_VAL = 0;\n    parameter DQS_LO_DEL_ADJ = \"FACTORYONLY\";\n    parameter GSR = \"ENABLED\";\n    input DQSI;\n    input READ1;\n    input READ0;\n    input READCLKSEL2;\n    input READCLKSEL1;\n    input READCLKSEL0;\n    input DDRDEL;\n    input ECLK;\n    input SCLK;\n    input RST;\n    input DYNDELAY7;\n    input DYNDELAY6;\n    input DYNDELAY5;\n    input DYNDELAY4;\n    input DYNDELAY3;\n    input DYNDELAY2;\n    input DYNDELAY1;\n    input DYNDELAY0;\n    input PAUSE;\n    input RDLOADN;\n    input RDMOVE;\n    input RDDIRECTION;\n    input WRLOADN;\n    input WRMOVE;\n    input WRDIRECTION;\n    output DQSR90;\n    output DQSW;\n    output DQSW270;\n    output RDPNTR2;\n    output RDPNTR1;\n    output RDPNTR0;\n    output WRPNTR2;\n    output WRPNTR1;\n    output WRPNTR0;\n    output DATAVALID;\n    output BURSTDET;\n    output RDCFLAG;\n    output WRCFLAG;\nendmodule\n\n(* blackbox *)\nmodule DDRDLLA (...);\n    parameter FORCE_MAX_DELAY = \"NO\";\n    parameter GSR = \"ENABLED\";\n    input CLK;\n    input RST;\n    input UDDCNTLN;\n    input FREEZE;\n    output DDRDEL;\n    output LOCK;\n    output DCNTL7;\n    output DCNTL6;\n    output DCNTL5;\n    output DCNTL4;\n    output DCNTL3;\n    output DCNTL2;\n    output DCNTL1;\n    output DCNTL0;\nendmodule\n\n(* blackbox *)\nmodule DLLDELD (...);\n    input A;\n    input DDRDEL;\n    input LOADN;\n    input MOVE;\n    input DIRECTION;\n    output Z;\n    output CFLAG;\nendmodule\n\n(* blackbox *)\nmodule IDDRX1F (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input RST;\n    output Q0;\n    output Q1;\nendmodule\n\n(* blackbox *)\nmodule IDDRX2F (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input ECLK;\n    input RST;\n    input ALIGNWD;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\nendmodule\n\n(* blackbox *)\nmodule IDDR71B (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input ECLK;\n    input RST;\n    input ALIGNWD;\n    output Q6;\n    output Q5;\n    output Q4;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\nendmodule\n\n(* blackbox *)\nmodule IDDRX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input DQSR90;\n    input D;\n    input RST;\n    input RDPNTR2;\n    input RDPNTR1;\n    input RDPNTR0;\n    input WRPNTR2;\n    input WRPNTR1;\n    input WRPNTR0;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\n    output QWL;\nendmodule\n\n(* blackbox *)\nmodule ODDRX1F (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input RST;\n    input D0;\n    input D1;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2F (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input RST;\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDR71B (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input RST;\n    input D6;\n    input D5;\n    input D4;\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule OSHX2A (...);\n    parameter GSR = \"ENABLED\";\n    input D1;\n    input D0;\n    input SCLK;\n    input ECLK;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    parameter REGSET = \"SET\";\n    input T1;\n    input T0;\n    input SCLK;\n    input ECLK;\n    input DQSW270;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQSA (...);\n    parameter GSR = \"ENABLED\";\n    parameter REGSET = \"SET\";\n    input T1;\n    input T0;\n    input SCLK;\n    input ECLK;\n    input DQSW;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    input DQSW270;\n    input SCLK;\n    input ECLK;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQSB (...);\n    parameter GSR = \"ENABLED\";\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    input SCLK;\n    input ECLK;\n    input DQSW;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule EHXPLLL (...);\n    parameter CLKI_DIV = 1;\n    parameter CLKFB_DIV = 1;\n    parameter CLKOP_DIV = 8;\n    parameter CLKOS_DIV = 8;\n    parameter CLKOS2_DIV = 8;\n    parameter CLKOS3_DIV = 8;\n    parameter CLKOP_ENABLE = \"ENABLED\";\n    parameter CLKOS_ENABLE = \"DISABLED\";\n    parameter CLKOS2_ENABLE = \"DISABLED\";\n    parameter CLKOS3_ENABLE = \"DISABLED\";\n    parameter CLKOP_CPHASE = 0;\n    parameter CLKOS_CPHASE = 0;\n    parameter CLKOS2_CPHASE = 0;\n    parameter CLKOS3_CPHASE = 0;\n    parameter CLKOP_FPHASE = 0;\n    parameter CLKOS_FPHASE = 0;\n    parameter CLKOS2_FPHASE = 0;\n    parameter CLKOS3_FPHASE = 0;\n    parameter FEEDBK_PATH = \"CLKOP\";\n    parameter CLKOP_TRIM_POL = \"RISING\";\n    parameter CLKOP_TRIM_DELAY = 0;\n    parameter CLKOS_TRIM_POL = \"RISING\";\n    parameter CLKOS_TRIM_DELAY = 0;\n    parameter OUTDIVIDER_MUXA = \"DIVA\";\n    parameter OUTDIVIDER_MUXB = \"DIVB\";\n    parameter OUTDIVIDER_MUXC = \"DIVC\";\n    parameter OUTDIVIDER_MUXD = \"DIVD\";\n    parameter PLL_LOCK_MODE = 0;\n    parameter PLL_LOCK_DELAY = 200;\n    parameter STDBY_ENABLE = \"DISABLED\";\n    parameter REFIN_RESET = \"DISABLED\";\n    parameter SYNC_ENABLE = \"DISABLED\";\n    parameter INT_LOCK_STICKY = \"ENABLED\";\n    parameter DPHASE_SOURCE = \"DISABLED\";\n    parameter PLLRST_ENA = \"DISABLED\";\n    parameter INTFB_WAKE = \"DISABLED\";\n    input CLKI;\n    input CLKFB;\n    input PHASESEL1;\n    input PHASESEL0;\n    input PHASEDIR;\n    input PHASESTEP;\n    input PHASELOADREG;\n    input STDBY;\n    input PLLWAKESYNC;\n    input RST;\n    input ENCLKOP;\n    input ENCLKOS;\n    input ENCLKOS2;\n    input ENCLKOS3;\n    output CLKOP;\n    output CLKOS;\n    output CLKOS2;\n    output CLKOS3;\n    output LOCK;\n    output INTLOCK;\n    output REFCLK;\n    output CLKINTFB;\nendmodule\n\n(* blackbox *)\nmodule DTR (...);\n    parameter DTR_TEMP = 25;\n    input STARTPULSE;\n    output DTROUT7;\n    output DTROUT6;\n    output DTROUT5;\n    output DTROUT4;\n    output DTROUT3;\n    output DTROUT2;\n    output DTROUT1;\n    output DTROUT0;\nendmodule\n\n(* blackbox *)\nmodule OSCG (...);\n    parameter DIV = 128;\n    output OSC;\nendmodule\n\n(* blackbox *)\nmodule EXTREFB (...);\n    parameter REFCK_PWDNB = \"DONTCARE\";\n    parameter REFCK_RTERM = \"DONTCARE\";\n    parameter REFCK_DCBIAS_EN = \"DONTCARE\";\n    (* iopad_external_pin *)\n    input REFCLKP;\n    (* iopad_external_pin *)\n    input REFCLKN;\n    output REFCLKO;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule JTAGG (...);\n    parameter ER1 = \"ENABLED\";\n    parameter ER2 = \"ENABLED\";\n    (* iopad_external_pin *)\n    input TCK;\n    (* iopad_external_pin *)\n    input TMS;\n    (* iopad_external_pin *)\n    input TDI;\n    input JTDO2;\n    input JTDO1;\n    (* iopad_external_pin *)\n    output TDO;\n    output JTDI;\n    output JTCK;\n    output JRTI2;\n    output JRTI1;\n    output JSHIFT;\n    output JUPDATE;\n    output JRSTN;\n    output JCE2;\n    output JCE1;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule DCUA (...);\n    parameter D_MACROPDB = \"DONTCARE\";\n    parameter D_IB_PWDNB = \"DONTCARE\";\n    parameter D_XGE_MODE = \"DONTCARE\";\n    parameter D_LOW_MARK = \"DONTCARE\";\n    parameter D_HIGH_MARK = \"DONTCARE\";\n    parameter D_BUS8BIT_SEL = \"DONTCARE\";\n    parameter D_CDR_LOL_SET = \"DONTCARE\";\n    parameter D_BITCLK_LOCAL_EN = \"DONTCARE\";\n    parameter D_BITCLK_ND_EN = \"DONTCARE\";\n    parameter D_BITCLK_FROM_ND_EN = \"DONTCARE\";\n    parameter D_SYNC_LOCAL_EN = \"DONTCARE\";\n    parameter D_SYNC_ND_EN = \"DONTCARE\";\n    parameter CH0_UC_MODE = \"DONTCARE\";\n    parameter CH1_UC_MODE = \"DONTCARE\";\n    parameter CH0_PCIE_MODE = \"DONTCARE\";\n    parameter CH1_PCIE_MODE = \"DONTCARE\";\n    parameter CH0_RIO_MODE = \"DONTCARE\";\n    parameter CH1_RIO_MODE = \"DONTCARE\";\n    parameter CH0_WA_MODE = \"DONTCARE\";\n    parameter CH1_WA_MODE = \"DONTCARE\";\n    parameter CH0_INVERT_RX = \"DONTCARE\";\n    parameter CH1_INVERT_RX = \"DONTCARE\";\n    parameter CH0_INVERT_TX = \"DONTCARE\";\n    parameter CH1_INVERT_TX = \"DONTCARE\";\n    parameter CH0_PRBS_SELECTION = \"DONTCARE\";\n    parameter CH1_PRBS_SELECTION = \"DONTCARE\";\n    parameter CH0_GE_AN_ENABLE = \"DONTCARE\";\n    parameter CH1_GE_AN_ENABLE = \"DONTCARE\";\n    parameter CH0_PRBS_LOCK = \"DONTCARE\";\n    parameter CH1_PRBS_LOCK = \"DONTCARE\";\n    parameter CH0_PRBS_ENABLE = \"DONTCARE\";\n    parameter CH1_PRBS_ENABLE = \"DONTCARE\";\n    parameter CH0_ENABLE_CG_ALIGN = \"DONTCARE\";\n    parameter CH1_ENABLE_CG_ALIGN = \"DONTCARE\";\n    parameter CH0_TX_GEAR_MODE = \"DONTCARE\";\n    parameter CH1_TX_GEAR_MODE = \"DONTCARE\";\n    parameter CH0_RX_GEAR_MODE = \"DONTCARE\";\n    parameter CH1_RX_GEAR_MODE = \"DONTCARE\";\n    parameter CH0_PCS_DET_TIME_SEL = \"DONTCARE\";\n    parameter CH1_PCS_DET_TIME_SEL = \"DONTCARE\";\n    parameter CH0_PCIE_EI_EN = \"DONTCARE\";\n    parameter CH1_PCIE_EI_EN = \"DONTCARE\";\n    parameter CH0_TX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH1_TX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH0_ENC_BYPASS = \"DONTCARE\";\n    parameter CH1_ENC_BYPASS = \"DONTCARE\";\n    parameter CH0_SB_BYPASS = \"DONTCARE\";\n    parameter CH1_SB_BYPASS = \"DONTCARE\";\n    parameter CH0_RX_SB_BYPASS = \"DONTCARE\";\n    parameter CH1_RX_SB_BYPASS = \"DONTCARE\";\n    parameter CH0_WA_BYPASS = \"DONTCARE\";\n    parameter CH1_WA_BYPASS = \"DONTCARE\";\n    parameter CH0_DEC_BYPASS = \"DONTCARE\";\n    parameter CH1_DEC_BYPASS = \"DONTCARE\";\n    parameter CH0_CTC_BYPASS = \"DONTCARE\";\n    parameter CH1_CTC_BYPASS = \"DONTCARE\";\n    parameter CH0_RX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH1_RX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH0_LSM_DISABLE = \"DONTCARE\";\n    parameter CH1_LSM_DISABLE = \"DONTCARE\";\n    parameter CH0_MATCH_2_ENABLE = \"DONTCARE\";\n    parameter CH1_MATCH_2_ENABLE = \"DONTCARE\";\n    parameter CH0_MATCH_4_ENABLE = \"DONTCARE\";\n    parameter CH1_MATCH_4_ENABLE = \"DONTCARE\";\n    parameter CH0_MIN_IPG_CNT = \"DONTCARE\";\n    parameter CH1_MIN_IPG_CNT = \"DONTCARE\";\n    parameter CH0_CC_MATCH_1 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_1 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_2 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_2 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_3 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_3 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_4 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_4 = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_MASK = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_MASK = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_A = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_A = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_B = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_B = \"DONTCARE\";\n    parameter CH0_RX_DCO_CK_DIV = \"DONTCARE\";\n    parameter CH1_RX_DCO_CK_DIV = \"DONTCARE\";\n    parameter CH0_RCV_DCC_EN = \"DONTCARE\";\n    parameter CH1_RCV_DCC_EN = \"DONTCARE\";\n    parameter CH0_REQ_LVL_SET = \"DONTCARE\";\n    parameter CH1_REQ_LVL_SET = \"DONTCARE\";\n    parameter CH0_REQ_EN = \"DONTCARE\";\n    parameter CH1_REQ_EN = \"DONTCARE\";\n    parameter CH0_RTERM_RX = \"DONTCARE\";\n    parameter CH1_RTERM_RX = \"DONTCARE\";\n    parameter CH0_PDEN_SEL = \"DONTCARE\";\n    parameter CH1_PDEN_SEL = \"DONTCARE\";\n    parameter CH0_LDR_RX2CORE_SEL = \"DONTCARE\";\n    parameter CH1_LDR_RX2CORE_SEL = \"DONTCARE\";\n    parameter CH0_LDR_CORE2TX_SEL = \"DONTCARE\";\n    parameter CH1_LDR_CORE2TX_SEL = \"DONTCARE\";\n    parameter CH0_TPWDNB = \"DONTCARE\";\n    parameter CH1_TPWDNB = \"DONTCARE\";\n    parameter CH0_RATE_MODE_TX = \"DONTCARE\";\n    parameter CH1_RATE_MODE_TX = \"DONTCARE\";\n    parameter CH0_RTERM_TX = \"DONTCARE\";\n    parameter CH1_RTERM_TX = \"DONTCARE\";\n    parameter CH0_TX_CM_SEL = \"DONTCARE\";\n    parameter CH1_TX_CM_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_PRE_EN = \"DONTCARE\";\n    parameter CH1_TDRV_PRE_EN = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE0_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE0_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE1_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE1_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE2_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE2_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE3_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE3_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE4_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE4_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE5_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE5_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE0_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE0_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE1_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE1_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE2_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE2_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE3_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE3_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE4_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE4_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE5_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE5_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_DAT_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_DAT_SEL = \"DONTCARE\";\n    parameter CH0_TX_DIV11_SEL = \"DONTCARE\";\n    parameter CH1_TX_DIV11_SEL = \"DONTCARE\";\n    parameter CH0_RPWDNB = \"DONTCARE\";\n    parameter CH1_RPWDNB = \"DONTCARE\";\n    parameter CH0_RATE_MODE_RX = \"DONTCARE\";\n    parameter CH1_RATE_MODE_RX = \"DONTCARE\";\n    parameter CH0_RLOS_SEL = \"DONTCARE\";\n    parameter CH1_RLOS_SEL = \"DONTCARE\";\n    parameter CH0_RX_LOS_LVL = \"DONTCARE\";\n    parameter CH1_RX_LOS_LVL = \"DONTCARE\";\n    parameter CH0_RX_LOS_CEQ = \"DONTCARE\";\n    parameter CH1_RX_LOS_CEQ = \"DONTCARE\";\n    parameter CH0_RX_LOS_HYST_EN = \"DONTCARE\";\n    parameter CH1_RX_LOS_HYST_EN = \"DONTCARE\";\n    parameter CH0_RX_LOS_EN = \"DONTCARE\";\n    parameter CH1_RX_LOS_EN = \"DONTCARE\";\n    parameter CH0_RX_DIV11_SEL = \"DONTCARE\";\n    parameter CH1_RX_DIV11_SEL = \"DONTCARE\";\n    parameter CH0_SEL_SD_RX_CLK = \"DONTCARE\";\n    parameter CH1_SEL_SD_RX_CLK = \"DONTCARE\";\n    parameter CH0_FF_RX_H_CLK_EN = \"DONTCARE\";\n    parameter CH1_FF_RX_H_CLK_EN = \"DONTCARE\";\n    parameter CH0_FF_RX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH1_FF_RX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH0_FF_TX_H_CLK_EN = \"DONTCARE\";\n    parameter CH1_FF_TX_H_CLK_EN = \"DONTCARE\";\n    parameter CH0_FF_TX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH1_FF_TX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH0_RX_RATE_SEL = \"DONTCARE\";\n    parameter CH1_RX_RATE_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_POST_EN = \"DONTCARE\";\n    parameter CH1_TDRV_POST_EN = \"DONTCARE\";\n    parameter CH0_TX_POST_SIGN = \"DONTCARE\";\n    parameter CH1_TX_POST_SIGN = \"DONTCARE\";\n    parameter CH0_TX_PRE_SIGN = \"DONTCARE\";\n    parameter CH1_TX_PRE_SIGN = \"DONTCARE\";\n    parameter CH0_RXTERM_CM = \"DONTCARE\";\n    parameter CH1_RXTERM_CM = \"DONTCARE\";\n    parameter CH0_RXIN_CM = \"DONTCARE\";\n    parameter CH1_RXIN_CM = \"DONTCARE\";\n    parameter CH0_LEQ_OFFSET_SEL = \"DONTCARE\";\n    parameter CH1_LEQ_OFFSET_SEL = \"DONTCARE\";\n    parameter CH0_LEQ_OFFSET_TRIM = \"DONTCARE\";\n    parameter CH1_LEQ_OFFSET_TRIM = \"DONTCARE\";\n    parameter D_TX_MAX_RATE = \"DONTCARE\";\n    parameter CH0_CDR_MAX_RATE = \"DONTCARE\";\n    parameter CH1_CDR_MAX_RATE = \"DONTCARE\";\n    parameter CH0_TXAMPLITUDE = \"DONTCARE\";\n    parameter CH1_TXAMPLITUDE = \"DONTCARE\";\n    parameter CH0_TXDEPRE = \"DONTCARE\";\n    parameter CH1_TXDEPRE = \"DONTCARE\";\n    parameter CH0_TXDEPOST = \"DONTCARE\";\n    parameter CH1_TXDEPOST = \"DONTCARE\";\n    parameter CH0_PROTOCOL = \"DONTCARE\";\n    parameter CH1_PROTOCOL = \"DONTCARE\";\n    parameter D_ISETLOS = \"DONTCARE\";\n    parameter D_SETIRPOLY_AUX = \"DONTCARE\";\n    parameter D_SETICONST_AUX = \"DONTCARE\";\n    parameter D_SETIRPOLY_CH = \"DONTCARE\";\n    parameter D_SETICONST_CH = \"DONTCARE\";\n    parameter D_REQ_ISET = \"DONTCARE\";\n    parameter D_PD_ISET = \"DONTCARE\";\n    parameter D_DCO_CALIB_TIME_SEL = \"DONTCARE\";\n    parameter CH0_DCOCTLGI = \"DONTCARE\";\n    parameter CH1_DCOCTLGI = \"DONTCARE\";\n    parameter CH0_DCOATDDLY = \"DONTCARE\";\n    parameter CH1_DCOATDDLY = \"DONTCARE\";\n    parameter CH0_DCOATDCFG = \"DONTCARE\";\n    parameter CH1_DCOATDCFG = \"DONTCARE\";\n    parameter CH0_DCOBYPSATD = \"DONTCARE\";\n    parameter CH1_DCOBYPSATD = \"DONTCARE\";\n    parameter CH0_DCOSCALEI = \"DONTCARE\";\n    parameter CH1_DCOSCALEI = \"DONTCARE\";\n    parameter CH0_DCOITUNE4LSB = \"DONTCARE\";\n    parameter CH1_DCOITUNE4LSB = \"DONTCARE\";\n    parameter CH0_DCOIOSTUNE = \"DONTCARE\";\n    parameter CH1_DCOIOSTUNE = \"DONTCARE\";\n    parameter CH0_DCODISBDAVOID = \"DONTCARE\";\n    parameter CH1_DCODISBDAVOID = \"DONTCARE\";\n    parameter CH0_DCOCALDIV = \"DONTCARE\";\n    parameter CH1_DCOCALDIV = \"DONTCARE\";\n    parameter CH0_DCONUOFLSB = \"DONTCARE\";\n    parameter CH1_DCONUOFLSB = \"DONTCARE\";\n    parameter CH0_DCOIUPDNX2 = \"DONTCARE\";\n    parameter CH1_DCOIUPDNX2 = \"DONTCARE\";\n    parameter CH0_DCOSTEP = \"DONTCARE\";\n    parameter CH1_DCOSTEP = \"DONTCARE\";\n    parameter CH0_DCOSTARTVAL = \"DONTCARE\";\n    parameter CH1_DCOSTARTVAL = \"DONTCARE\";\n    parameter CH0_DCOFLTDAC = \"DONTCARE\";\n    parameter CH1_DCOFLTDAC = \"DONTCARE\";\n    parameter CH0_DCOITUNE = \"DONTCARE\";\n    parameter CH1_DCOITUNE = \"DONTCARE\";\n    parameter CH0_DCOFTNRG = \"DONTCARE\";\n    parameter CH1_DCOFTNRG = \"DONTCARE\";\n    parameter CH0_CDR_CNT4SEL = \"DONTCARE\";\n    parameter CH1_CDR_CNT4SEL = \"DONTCARE\";\n    parameter CH0_CDR_CNT8SEL = \"DONTCARE\";\n    parameter CH1_CDR_CNT8SEL = \"DONTCARE\";\n    parameter CH0_BAND_THRESHOLD = \"DONTCARE\";\n    parameter CH1_BAND_THRESHOLD = \"DONTCARE\";\n    parameter CH0_AUTO_FACQ_EN = \"DONTCARE\";\n    parameter CH1_AUTO_FACQ_EN = \"DONTCARE\";\n    parameter CH0_AUTO_CALIB_EN = \"DONTCARE\";\n    parameter CH1_AUTO_CALIB_EN = \"DONTCARE\";\n    parameter CH0_CALIB_CK_MODE = \"DONTCARE\";\n    parameter CH1_CALIB_CK_MODE = \"DONTCARE\";\n    parameter CH0_REG_BAND_OFFSET = \"DONTCARE\";\n    parameter CH1_REG_BAND_OFFSET = \"DONTCARE\";\n    parameter CH0_REG_BAND_SEL = \"DONTCARE\";\n    parameter CH1_REG_BAND_SEL = \"DONTCARE\";\n    parameter CH0_REG_IDAC_SEL = \"DONTCARE\";\n    parameter CH1_REG_IDAC_SEL = \"DONTCARE\";\n    parameter CH0_REG_IDAC_EN = \"DONTCARE\";\n    parameter CH1_REG_IDAC_EN = \"DONTCARE\";\n    parameter D_TXPLL_PWDNB = \"DONTCARE\";\n    parameter D_SETPLLRC = \"DONTCARE\";\n    parameter D_REFCK_MODE = \"DONTCARE\";\n    parameter D_TX_VCO_CK_DIV = \"DONTCARE\";\n    parameter D_PLL_LOL_SET = \"DONTCARE\";\n    parameter D_RG_EN = \"DONTCARE\";\n    parameter D_RG_SET = \"DONTCARE\";\n    parameter D_CMUSETISCL4VCO = \"DONTCARE\";\n    parameter D_CMUSETI4VCO = \"DONTCARE\";\n    parameter D_CMUSETINITVCT = \"DONTCARE\";\n    parameter D_CMUSETZGM = \"DONTCARE\";\n    parameter D_CMUSETP2AGM = \"DONTCARE\";\n    parameter D_CMUSETP1GM = \"DONTCARE\";\n    parameter D_CMUSETI4CPZ = \"DONTCARE\";\n    parameter D_CMUSETI4CPP = \"DONTCARE\";\n    parameter D_CMUSETICP4Z = \"DONTCARE\";\n    parameter D_CMUSETICP4P = \"DONTCARE\";\n    parameter D_CMUSETBIASI = \"DONTCARE\";\n    (* iopad_external_pin *)\n    (* iopad_external_pin *)\n    input CH0_HDINP;\n    (* iopad_external_pin *)\n    input CH1_HDINP;\n    (* iopad_external_pin *)\n    input CH0_HDINN;\n    (* iopad_external_pin *)\n    input CH1_HDINN;\n    input D_TXBIT_CLKP_FROM_ND;\n    input D_TXBIT_CLKN_FROM_ND;\n    input D_SYNC_ND;\n    input D_TXPLL_LOL_FROM_ND;\n    input CH0_RX_REFCLK;\n    input CH1_RX_REFCLK;\n    input CH0_FF_RXI_CLK;\n    input CH1_FF_RXI_CLK;\n    input CH0_FF_TXI_CLK;\n    input CH1_FF_TXI_CLK;\n    input CH0_FF_EBRD_CLK;\n    input CH1_FF_EBRD_CLK;\n    input CH0_FF_TX_D_0;\n    input CH1_FF_TX_D_0;\n    input CH0_FF_TX_D_1;\n    input CH1_FF_TX_D_1;\n    input CH0_FF_TX_D_2;\n    input CH1_FF_TX_D_2;\n    input CH0_FF_TX_D_3;\n    input CH1_FF_TX_D_3;\n    input CH0_FF_TX_D_4;\n    input CH1_FF_TX_D_4;\n    input CH0_FF_TX_D_5;\n    input CH1_FF_TX_D_5;\n    input CH0_FF_TX_D_6;\n    input CH1_FF_TX_D_6;\n    input CH0_FF_TX_D_7;\n    input CH1_FF_TX_D_7;\n    input CH0_FF_TX_D_8;\n    input CH1_FF_TX_D_8;\n    input CH0_FF_TX_D_9;\n    input CH1_FF_TX_D_9;\n    input CH0_FF_TX_D_10;\n    input CH1_FF_TX_D_10;\n    input CH0_FF_TX_D_11;\n    input CH1_FF_TX_D_11;\n    input CH0_FF_TX_D_12;\n    input CH1_FF_TX_D_12;\n    input CH0_FF_TX_D_13;\n    input CH1_FF_TX_D_13;\n    input CH0_FF_TX_D_14;\n    input CH1_FF_TX_D_14;\n    input CH0_FF_TX_D_15;\n    input CH1_FF_TX_D_15;\n    input CH0_FF_TX_D_16;\n    input CH1_FF_TX_D_16;\n    input CH0_FF_TX_D_17;\n    input CH1_FF_TX_D_17;\n    input CH0_FF_TX_D_18;\n    input CH1_FF_TX_D_18;\n    input CH0_FF_TX_D_19;\n    input CH1_FF_TX_D_19;\n    input CH0_FF_TX_D_20;\n    input CH1_FF_TX_D_20;\n    input CH0_FF_TX_D_21;\n    input CH1_FF_TX_D_21;\n    input CH0_FF_TX_D_22;\n    input CH1_FF_TX_D_22;\n    input CH0_FF_TX_D_23;\n    input CH1_FF_TX_D_23;\n    input CH0_FFC_EI_EN;\n    input CH1_FFC_EI_EN;\n    input CH0_FFC_PCIE_DET_EN;\n    input CH1_FFC_PCIE_DET_EN;\n    input CH0_FFC_PCIE_CT;\n    input CH1_FFC_PCIE_CT;\n    input CH0_FFC_SB_INV_RX;\n    input CH1_FFC_SB_INV_RX;\n    input CH0_FFC_ENABLE_CGALIGN;\n    input CH1_FFC_ENABLE_CGALIGN;\n    input CH0_FFC_SIGNAL_DETECT;\n    input CH1_FFC_SIGNAL_DETECT;\n    input CH0_FFC_FB_LOOPBACK;\n    input CH1_FFC_FB_LOOPBACK;\n    input CH0_FFC_SB_PFIFO_LP;\n    input CH1_FFC_SB_PFIFO_LP;\n    input CH0_FFC_PFIFO_CLR;\n    input CH1_FFC_PFIFO_CLR;\n    input CH0_FFC_RATE_MODE_RX;\n    input CH1_FFC_RATE_MODE_RX;\n    input CH0_FFC_RATE_MODE_TX;\n    input CH1_FFC_RATE_MODE_TX;\n    input CH0_FFC_DIV11_MODE_RX;\n    input CH1_FFC_DIV11_MODE_RX;\n    input CH0_FFC_RX_GEAR_MODE;\n    input CH1_FFC_RX_GEAR_MODE;\n    input CH0_FFC_TX_GEAR_MODE;\n    input CH1_FFC_TX_GEAR_MODE;\n    input CH0_FFC_DIV11_MODE_TX;\n    input CH1_FFC_DIV11_MODE_TX;\n    input CH0_FFC_LDR_CORE2TX_EN;\n    input CH1_FFC_LDR_CORE2TX_EN;\n    input CH0_FFC_LANE_TX_RST;\n    input CH1_FFC_LANE_TX_RST;\n    input CH0_FFC_LANE_RX_RST;\n    input CH1_FFC_LANE_RX_RST;\n    input CH0_FFC_RRST;\n    input CH1_FFC_RRST;\n    input CH0_FFC_TXPWDNB;\n    input CH1_FFC_TXPWDNB;\n    input CH0_FFC_RXPWDNB;\n    input CH1_FFC_RXPWDNB;\n    input CH0_LDR_CORE2TX;\n    input CH1_LDR_CORE2TX;\n    input D_SCIWDATA0;\n    input D_SCIWDATA1;\n    input D_SCIWDATA2;\n    input D_SCIWDATA3;\n    input D_SCIWDATA4;\n    input D_SCIWDATA5;\n    input D_SCIWDATA6;\n    input D_SCIWDATA7;\n    input D_SCIADDR0;\n    input D_SCIADDR1;\n    input D_SCIADDR2;\n    input D_SCIADDR3;\n    input D_SCIADDR4;\n    input D_SCIADDR5;\n    input D_SCIENAUX;\n    input D_SCISELAUX;\n    input CH0_SCIEN;\n    input CH1_SCIEN;\n    input CH0_SCISEL;\n    input CH1_SCISEL;\n    input D_SCIRD;\n    input D_SCIWSTN;\n    input D_CYAWSTN;\n    input D_FFC_SYNC_TOGGLE;\n    input D_FFC_DUAL_RST;\n    input D_FFC_MACRO_RST;\n    input D_FFC_MACROPDB;\n    input D_FFC_TRST;\n    input CH0_FFC_CDR_EN_BITSLIP;\n    input CH1_FFC_CDR_EN_BITSLIP;\n    input D_SCAN_ENABLE;\n    input D_SCAN_IN_0;\n    input D_SCAN_IN_1;\n    input D_SCAN_IN_2;\n    input D_SCAN_IN_3;\n    input D_SCAN_IN_4;\n    input D_SCAN_IN_5;\n    input D_SCAN_IN_6;\n    input D_SCAN_IN_7;\n    input D_SCAN_MODE;\n    input D_SCAN_RESET;\n    input D_CIN0;\n    input D_CIN1;\n    input D_CIN2;\n    input D_CIN3;\n    input D_CIN4;\n    input D_CIN5;\n    input D_CIN6;\n    input D_CIN7;\n    input D_CIN8;\n    input D_CIN9;\n    input D_CIN10;\n    input D_CIN11;\n    output CH0_HDOUTP;\n    output CH1_HDOUTP;\n    output CH0_HDOUTN;\n    output CH1_HDOUTN;\n    output D_TXBIT_CLKP_TO_ND;\n    output D_TXBIT_CLKN_TO_ND;\n    output D_SYNC_PULSE2ND;\n    output D_TXPLL_LOL_TO_ND;\n    output CH0_FF_RX_F_CLK;\n    output CH1_FF_RX_F_CLK;\n    output CH0_FF_RX_H_CLK;\n    output CH1_FF_RX_H_CLK;\n    output CH0_FF_TX_F_CLK;\n    output CH1_FF_TX_F_CLK;\n    output CH0_FF_TX_H_CLK;\n    output CH1_FF_TX_H_CLK;\n    output CH0_FF_RX_PCLK;\n    output CH1_FF_RX_PCLK;\n    output CH0_FF_TX_PCLK;\n    output CH1_FF_TX_PCLK;\n    output CH0_FF_RX_D_0;\n    output CH1_FF_RX_D_0;\n    output CH0_FF_RX_D_1;\n    output CH1_FF_RX_D_1;\n    output CH0_FF_RX_D_2;\n    output CH1_FF_RX_D_2;\n    output CH0_FF_RX_D_3;\n    output CH1_FF_RX_D_3;\n    output CH0_FF_RX_D_4;\n    output CH1_FF_RX_D_4;\n    output CH0_FF_RX_D_5;\n    output CH1_FF_RX_D_5;\n    output CH0_FF_RX_D_6;\n    output CH1_FF_RX_D_6;\n    output CH0_FF_RX_D_7;\n    output CH1_FF_RX_D_7;\n    output CH0_FF_RX_D_8;\n    output CH1_FF_RX_D_8;\n    output CH0_FF_RX_D_9;\n    output CH1_FF_RX_D_9;\n    output CH0_FF_RX_D_10;\n    output CH1_FF_RX_D_10;\n    output CH0_FF_RX_D_11;\n    output CH1_FF_RX_D_11;\n    output CH0_FF_RX_D_12;\n    output CH1_FF_RX_D_12;\n    output CH0_FF_RX_D_13;\n    output CH1_FF_RX_D_13;\n    output CH0_FF_RX_D_14;\n    output CH1_FF_RX_D_14;\n    output CH0_FF_RX_D_15;\n    output CH1_FF_RX_D_15;\n    output CH0_FF_RX_D_16;\n    output CH1_FF_RX_D_16;\n    output CH0_FF_RX_D_17;\n    output CH1_FF_RX_D_17;\n    output CH0_FF_RX_D_18;\n    output CH1_FF_RX_D_18;\n    output CH0_FF_RX_D_19;\n    output CH1_FF_RX_D_19;\n    output CH0_FF_RX_D_20;\n    output CH1_FF_RX_D_20;\n    output CH0_FF_RX_D_21;\n    output CH1_FF_RX_D_21;\n    output CH0_FF_RX_D_22;\n    output CH1_FF_RX_D_22;\n    output CH0_FF_RX_D_23;\n    output CH1_FF_RX_D_23;\n    output CH0_FFS_PCIE_DONE;\n    output CH1_FFS_PCIE_DONE;\n    output CH0_FFS_PCIE_CON;\n    output CH1_FFS_PCIE_CON;\n    output CH0_FFS_RLOS;\n    output CH1_FFS_RLOS;\n    output CH0_FFS_LS_SYNC_STATUS;\n    output CH1_FFS_LS_SYNC_STATUS;\n    output CH0_FFS_CC_UNDERRUN;\n    output CH1_FFS_CC_UNDERRUN;\n    output CH0_FFS_CC_OVERRUN;\n    output CH1_FFS_CC_OVERRUN;\n    output CH0_FFS_RXFBFIFO_ERROR;\n    output CH1_FFS_RXFBFIFO_ERROR;\n    output CH0_FFS_TXFBFIFO_ERROR;\n    output CH1_FFS_TXFBFIFO_ERROR;\n    output CH0_FFS_RLOL;\n    output CH1_FFS_RLOL;\n    output CH0_FFS_SKP_ADDED;\n    output CH1_FFS_SKP_ADDED;\n    output CH0_FFS_SKP_DELETED;\n    output CH1_FFS_SKP_DELETED;\n    output CH0_LDR_RX2CORE;\n    output CH1_LDR_RX2CORE;\n    output D_SCIRDATA0;\n    output D_SCIRDATA1;\n    output D_SCIRDATA2;\n    output D_SCIRDATA3;\n    output D_SCIRDATA4;\n    output D_SCIRDATA5;\n    output D_SCIRDATA6;\n    output D_SCIRDATA7;\n    output D_SCIINT;\n    output D_SCAN_OUT_0;\n    output D_SCAN_OUT_1;\n    output D_SCAN_OUT_2;\n    output D_SCAN_OUT_3;\n    output D_SCAN_OUT_4;\n    output D_SCAN_OUT_5;\n    output D_SCAN_OUT_6;\n    output D_SCAN_OUT_7;\n    output D_COUT0;\n    output D_COUT1;\n    output D_COUT2;\n    output D_COUT3;\n    output D_COUT4;\n    output D_COUT5;\n    output D_COUT6;\n    output D_COUT7;\n    output D_COUT8;\n    output D_COUT9;\n    output D_COUT10;\n    output D_COUT11;\n    output D_COUT12;\n    output D_COUT13;\n    output D_COUT14;\n    output D_COUT15;\n    output D_COUT16;\n    output D_COUT17;\n    output D_COUT18;\n    output D_COUT19;\n    input D_REFCLKI;\n    output D_FFS_PLOL;\nendmodule\n\n",
+            "cells_bb_ecp5.v": "// Created by cells_xtra.py from Lattice models\n\n(* blackbox *) (* keep *)\nmodule GSR (...);\n    input GSR;\nendmodule\n\n(* blackbox *)\nmodule PUR (...);\n    parameter RST_PULSE = 1;\n    input PUR;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule SGSR (...);\n    input GSR;\n    input CLK;\nendmodule\n\n(* blackbox *)\nmodule PDPW16KD (...);\n    parameter CLKRMUX = \"CLKR\";\n    parameter CLKWMUX = \"CLKW\";\n    parameter DATA_WIDTH_W = 36;\n    parameter DATA_WIDTH_R = 36;\n    parameter GSR = \"ENABLED\";\n    parameter REGMODE = \"NOREG\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter CSDECODE_W = \"0b000\";\n    parameter CSDECODE_R = \"0b000\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INIT_DATA = \"STATIC\";\n    input DI35;\n    input DI34;\n    input DI33;\n    input DI32;\n    input DI31;\n    input DI30;\n    input DI29;\n    input DI28;\n    input DI27;\n    input DI26;\n    input DI25;\n    input DI24;\n    input DI23;\n    input DI22;\n    input DI21;\n    input DI20;\n    input DI19;\n    input DI18;\n    input DI17;\n    input DI16;\n    input DI15;\n    input DI14;\n    input DI13;\n    input DI12;\n    input DI11;\n    input DI10;\n    input DI9;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input ADW8;\n    input ADW7;\n    input ADW6;\n    input ADW5;\n    input ADW4;\n    input ADW3;\n    input ADW2;\n    input ADW1;\n    input ADW0;\n    input BE3;\n    input BE2;\n    input BE1;\n    input BE0;\n    input CEW;\n    input CLKW;\n    input CSW2;\n    input CSW1;\n    input CSW0;\n    input ADR13;\n    input ADR12;\n    input ADR11;\n    input ADR10;\n    input ADR9;\n    input ADR8;\n    input ADR7;\n    input ADR6;\n    input ADR5;\n    input ADR4;\n    input ADR3;\n    input ADR2;\n    input ADR1;\n    input ADR0;\n    input CER;\n    input OCER;\n    input CLKR;\n    input CSR2;\n    input CSR1;\n    input CSR0;\n    input RST;\n    output DO35;\n    output DO34;\n    output DO33;\n    output DO32;\n    output DO31;\n    output DO30;\n    output DO29;\n    output DO28;\n    output DO27;\n    output DO26;\n    output DO25;\n    output DO24;\n    output DO23;\n    output DO22;\n    output DO21;\n    output DO20;\n    output DO19;\n    output DO18;\n    output DO17;\n    output DO16;\n    output DO15;\n    output DO14;\n    output DO13;\n    output DO12;\n    output DO11;\n    output DO10;\n    output DO9;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule MULT18X18D (...);\n    parameter REG_INPUTA_CLK = \"NONE\";\n    parameter REG_INPUTA_CE = \"CE0\";\n    parameter REG_INPUTA_RST = \"RST0\";\n    parameter REG_INPUTB_CLK = \"NONE\";\n    parameter REG_INPUTB_CE = \"CE0\";\n    parameter REG_INPUTB_RST = \"RST0\";\n    parameter REG_INPUTC_CLK = \"NONE\";\n    parameter REG_INPUTC_CE = \"CE0\";\n    parameter REG_INPUTC_RST = \"RST0\";\n    parameter REG_PIPELINE_CLK = \"NONE\";\n    parameter REG_PIPELINE_CE = \"CE0\";\n    parameter REG_PIPELINE_RST = \"RST0\";\n    parameter REG_OUTPUT_CLK = \"NONE\";\n    parameter REG_OUTPUT_CE = \"CE0\";\n    parameter REG_OUTPUT_RST = \"RST0\";\n    parameter CLK0_DIV = \"ENABLED\";\n    parameter CLK1_DIV = \"ENABLED\";\n    parameter CLK2_DIV = \"ENABLED\";\n    parameter CLK3_DIV = \"ENABLED\";\n    parameter HIGHSPEED_CLK = \"NONE\";\n    parameter GSR = \"ENABLED\";\n    parameter CAS_MATCH_REG = \"FALSE\";\n    parameter SOURCEB_MODE = \"B_SHIFT\";\n    parameter MULT_BYPASS = \"DISABLED\";\n    parameter RESETMODE = \"SYNC\";\n    input A17;\n    input A16;\n    input A15;\n    input A14;\n    input A13;\n    input A12;\n    input A11;\n    input A10;\n    input A9;\n    input A8;\n    input A7;\n    input A6;\n    input A5;\n    input A4;\n    input A3;\n    input A2;\n    input A1;\n    input A0;\n    input B17;\n    input B16;\n    input B15;\n    input B14;\n    input B13;\n    input B12;\n    input B11;\n    input B10;\n    input B9;\n    input B8;\n    input B7;\n    input B6;\n    input B5;\n    input B4;\n    input B3;\n    input B2;\n    input B1;\n    input B0;\n    input C17;\n    input C16;\n    input C15;\n    input C14;\n    input C13;\n    input C12;\n    input C11;\n    input C10;\n    input C9;\n    input C8;\n    input C7;\n    input C6;\n    input C5;\n    input C4;\n    input C3;\n    input C2;\n    input C1;\n    input C0;\n    input SIGNEDA;\n    input SIGNEDB;\n    input SOURCEA;\n    input SOURCEB;\n    input CLK3;\n    input CLK2;\n    input CLK1;\n    input CLK0;\n    input CE3;\n    input CE2;\n    input CE1;\n    input CE0;\n    input RST3;\n    input RST2;\n    input RST1;\n    input RST0;\n    input SRIA17;\n    input SRIA16;\n    input SRIA15;\n    input SRIA14;\n    input SRIA13;\n    input SRIA12;\n    input SRIA11;\n    input SRIA10;\n    input SRIA9;\n    input SRIA8;\n    input SRIA7;\n    input SRIA6;\n    input SRIA5;\n    input SRIA4;\n    input SRIA3;\n    input SRIA2;\n    input SRIA1;\n    input SRIA0;\n    input SRIB17;\n    input SRIB16;\n    input SRIB15;\n    input SRIB14;\n    input SRIB13;\n    input SRIB12;\n    input SRIB11;\n    input SRIB10;\n    input SRIB9;\n    input SRIB8;\n    input SRIB7;\n    input SRIB6;\n    input SRIB5;\n    input SRIB4;\n    input SRIB3;\n    input SRIB2;\n    input SRIB1;\n    input SRIB0;\n    output SROA17;\n    output SROA16;\n    output SROA15;\n    output SROA14;\n    output SROA13;\n    output SROA12;\n    output SROA11;\n    output SROA10;\n    output SROA9;\n    output SROA8;\n    output SROA7;\n    output SROA6;\n    output SROA5;\n    output SROA4;\n    output SROA3;\n    output SROA2;\n    output SROA1;\n    output SROA0;\n    output SROB17;\n    output SROB16;\n    output SROB15;\n    output SROB14;\n    output SROB13;\n    output SROB12;\n    output SROB11;\n    output SROB10;\n    output SROB9;\n    output SROB8;\n    output SROB7;\n    output SROB6;\n    output SROB5;\n    output SROB4;\n    output SROB3;\n    output SROB2;\n    output SROB1;\n    output SROB0;\n    output ROA17;\n    output ROA16;\n    output ROA15;\n    output ROA14;\n    output ROA13;\n    output ROA12;\n    output ROA11;\n    output ROA10;\n    output ROA9;\n    output ROA8;\n    output ROA7;\n    output ROA6;\n    output ROA5;\n    output ROA4;\n    output ROA3;\n    output ROA2;\n    output ROA1;\n    output ROA0;\n    output ROB17;\n    output ROB16;\n    output ROB15;\n    output ROB14;\n    output ROB13;\n    output ROB12;\n    output ROB11;\n    output ROB10;\n    output ROB9;\n    output ROB8;\n    output ROB7;\n    output ROB6;\n    output ROB5;\n    output ROB4;\n    output ROB3;\n    output ROB2;\n    output ROB1;\n    output ROB0;\n    output ROC17;\n    output ROC16;\n    output ROC15;\n    output ROC14;\n    output ROC13;\n    output ROC12;\n    output ROC11;\n    output ROC10;\n    output ROC9;\n    output ROC8;\n    output ROC7;\n    output ROC6;\n    output ROC5;\n    output ROC4;\n    output ROC3;\n    output ROC2;\n    output ROC1;\n    output ROC0;\n    output P35;\n    output P34;\n    output P33;\n    output P32;\n    output P31;\n    output P30;\n    output P29;\n    output P28;\n    output P27;\n    output P26;\n    output P25;\n    output P24;\n    output P23;\n    output P22;\n    output P21;\n    output P20;\n    output P19;\n    output P18;\n    output P17;\n    output P16;\n    output P15;\n    output P14;\n    output P13;\n    output P12;\n    output P11;\n    output P10;\n    output P9;\n    output P8;\n    output P7;\n    output P6;\n    output P5;\n    output P4;\n    output P3;\n    output P2;\n    output P1;\n    output P0;\n    output SIGNEDP;\nendmodule\n\n(* blackbox *)\nmodule ALU54B (...);\n    parameter REG_INPUTC0_CLK = \"NONE\";\n    parameter REG_INPUTC0_CE = \"CE0\";\n    parameter REG_INPUTC0_RST = \"RST0\";\n    parameter REG_INPUTC1_CLK = \"NONE\";\n    parameter REG_INPUTC1_CE = \"CE0\";\n    parameter REG_INPUTC1_RST = \"RST0\";\n    parameter REG_OPCODEOP0_0_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_0_CE = \"CE0\";\n    parameter REG_OPCODEOP0_0_RST = \"RST0\";\n    parameter REG_OPCODEOP1_0_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_1_CLK = \"NONE\";\n    parameter REG_OPCODEOP0_1_CE = \"CE0\";\n    parameter REG_OPCODEOP0_1_RST = \"RST0\";\n    parameter REG_OPCODEOP1_1_CLK = \"NONE\";\n    parameter REG_OPCODEIN_0_CLK = \"NONE\";\n    parameter REG_OPCODEIN_0_CE = \"CE0\";\n    parameter REG_OPCODEIN_0_RST = \"RST0\";\n    parameter REG_OPCODEIN_1_CLK = \"NONE\";\n    parameter REG_OPCODEIN_1_CE = \"CE0\";\n    parameter REG_OPCODEIN_1_RST = \"RST0\";\n    parameter REG_OUTPUT0_CLK = \"NONE\";\n    parameter REG_OUTPUT0_CE = \"CE0\";\n    parameter REG_OUTPUT0_RST = \"RST0\";\n    parameter REG_OUTPUT1_CLK = \"NONE\";\n    parameter REG_OUTPUT1_CE = \"CE0\";\n    parameter REG_OUTPUT1_RST = \"RST0\";\n    parameter REG_FLAG_CLK = \"NONE\";\n    parameter REG_FLAG_CE = \"CE0\";\n    parameter REG_FLAG_RST = \"RST0\";\n    parameter MCPAT_SOURCE = \"STATIC\";\n    parameter MASKPAT_SOURCE = \"STATIC\";\n    parameter MASK01 = \"0x00000000000000\";\n    parameter REG_INPUTCFB_CLK = \"NONE\";\n    parameter REG_INPUTCFB_CE = \"CE0\";\n    parameter REG_INPUTCFB_RST = \"RST0\";\n    parameter CLK0_DIV = \"ENABLED\";\n    parameter CLK1_DIV = \"ENABLED\";\n    parameter CLK2_DIV = \"ENABLED\";\n    parameter CLK3_DIV = \"ENABLED\";\n    parameter MCPAT = \"0x00000000000000\";\n    parameter MASKPAT = \"0x00000000000000\";\n    parameter RNDPAT = \"0x00000000000000\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter MULT9_MODE = \"DISABLED\";\n    parameter FORCE_ZERO_BARREL_SHIFT = \"DISABLED\";\n    parameter LEGACY = \"DISABLED\";\n    input CE3;\n    input CE2;\n    input CE1;\n    input CE0;\n    input CLK3;\n    input CLK2;\n    input CLK1;\n    input CLK0;\n    input RST3;\n    input RST2;\n    input RST1;\n    input RST0;\n    input SIGNEDIA;\n    input SIGNEDIB;\n    input SIGNEDCIN;\n    input A35;\n    input A34;\n    input A33;\n    input A32;\n    input A31;\n    input A30;\n    input A29;\n    input A28;\n    input A27;\n    input A26;\n    input A25;\n    input A24;\n    input A23;\n    input A22;\n    input A21;\n    input A20;\n    input A19;\n    input A18;\n    input A17;\n    input A16;\n    input A15;\n    input A14;\n    input A13;\n    input A12;\n    input A11;\n    input A10;\n    input A9;\n    input A8;\n    input A7;\n    input A6;\n    input A5;\n    input A4;\n    input A3;\n    input A2;\n    input A1;\n    input A0;\n    input B35;\n    input B34;\n    input B33;\n    input B32;\n    input B31;\n    input B30;\n    input B29;\n    input B28;\n    input B27;\n    input B26;\n    input B25;\n    input B24;\n    input B23;\n    input B22;\n    input B21;\n    input B20;\n    input B19;\n    input B18;\n    input B17;\n    input B16;\n    input B15;\n    input B14;\n    input B13;\n    input B12;\n    input B11;\n    input B10;\n    input B9;\n    input B8;\n    input B7;\n    input B6;\n    input B5;\n    input B4;\n    input B3;\n    input B2;\n    input B1;\n    input B0;\n    input C53;\n    input C52;\n    input C51;\n    input C50;\n    input C49;\n    input C48;\n    input C47;\n    input C46;\n    input C45;\n    input C44;\n    input C43;\n    input C42;\n    input C41;\n    input C40;\n    input C39;\n    input C38;\n    input C37;\n    input C36;\n    input C35;\n    input C34;\n    input C33;\n    input C32;\n    input C31;\n    input C30;\n    input C29;\n    input C28;\n    input C27;\n    input C26;\n    input C25;\n    input C24;\n    input C23;\n    input C22;\n    input C21;\n    input C20;\n    input C19;\n    input C18;\n    input C17;\n    input C16;\n    input C15;\n    input C14;\n    input C13;\n    input C12;\n    input C11;\n    input C10;\n    input C9;\n    input C8;\n    input C7;\n    input C6;\n    input C5;\n    input C4;\n    input C3;\n    input C2;\n    input C1;\n    input C0;\n    input CFB53;\n    input CFB52;\n    input CFB51;\n    input CFB50;\n    input CFB49;\n    input CFB48;\n    input CFB47;\n    input CFB46;\n    input CFB45;\n    input CFB44;\n    input CFB43;\n    input CFB42;\n    input CFB41;\n    input CFB40;\n    input CFB39;\n    input CFB38;\n    input CFB37;\n    input CFB36;\n    input CFB35;\n    input CFB34;\n    input CFB33;\n    input CFB32;\n    input CFB31;\n    input CFB30;\n    input CFB29;\n    input CFB28;\n    input CFB27;\n    input CFB26;\n    input CFB25;\n    input CFB24;\n    input CFB23;\n    input CFB22;\n    input CFB21;\n    input CFB20;\n    input CFB19;\n    input CFB18;\n    input CFB17;\n    input CFB16;\n    input CFB15;\n    input CFB14;\n    input CFB13;\n    input CFB12;\n    input CFB11;\n    input CFB10;\n    input CFB9;\n    input CFB8;\n    input CFB7;\n    input CFB6;\n    input CFB5;\n    input CFB4;\n    input CFB3;\n    input CFB2;\n    input CFB1;\n    input CFB0;\n    input MA35;\n    input MA34;\n    input MA33;\n    input MA32;\n    input MA31;\n    input MA30;\n    input MA29;\n    input MA28;\n    input MA27;\n    input MA26;\n    input MA25;\n    input MA24;\n    input MA23;\n    input MA22;\n    input MA21;\n    input MA20;\n    input MA19;\n    input MA18;\n    input MA17;\n    input MA16;\n    input MA15;\n    input MA14;\n    input MA13;\n    input MA12;\n    input MA11;\n    input MA10;\n    input MA9;\n    input MA8;\n    input MA7;\n    input MA6;\n    input MA5;\n    input MA4;\n    input MA3;\n    input MA2;\n    input MA1;\n    input MA0;\n    input MB35;\n    input MB34;\n    input MB33;\n    input MB32;\n    input MB31;\n    input MB30;\n    input MB29;\n    input MB28;\n    input MB27;\n    input MB26;\n    input MB25;\n    input MB24;\n    input MB23;\n    input MB22;\n    input MB21;\n    input MB20;\n    input MB19;\n    input MB18;\n    input MB17;\n    input MB16;\n    input MB15;\n    input MB14;\n    input MB13;\n    input MB12;\n    input MB11;\n    input MB10;\n    input MB9;\n    input MB8;\n    input MB7;\n    input MB6;\n    input MB5;\n    input MB4;\n    input MB3;\n    input MB2;\n    input MB1;\n    input MB0;\n    input CIN53;\n    input CIN52;\n    input CIN51;\n    input CIN50;\n    input CIN49;\n    input CIN48;\n    input CIN47;\n    input CIN46;\n    input CIN45;\n    input CIN44;\n    input CIN43;\n    input CIN42;\n    input CIN41;\n    input CIN40;\n    input CIN39;\n    input CIN38;\n    input CIN37;\n    input CIN36;\n    input CIN35;\n    input CIN34;\n    input CIN33;\n    input CIN32;\n    input CIN31;\n    input CIN30;\n    input CIN29;\n    input CIN28;\n    input CIN27;\n    input CIN26;\n    input CIN25;\n    input CIN24;\n    input CIN23;\n    input CIN22;\n    input CIN21;\n    input CIN20;\n    input CIN19;\n    input CIN18;\n    input CIN17;\n    input CIN16;\n    input CIN15;\n    input CIN14;\n    input CIN13;\n    input CIN12;\n    input CIN11;\n    input CIN10;\n    input CIN9;\n    input CIN8;\n    input CIN7;\n    input CIN6;\n    input CIN5;\n    input CIN4;\n    input CIN3;\n    input CIN2;\n    input CIN1;\n    input CIN0;\n    input OP10;\n    input OP9;\n    input OP8;\n    input OP7;\n    input OP6;\n    input OP5;\n    input OP4;\n    input OP3;\n    input OP2;\n    input OP1;\n    input OP0;\n    output R53;\n    output R52;\n    output R51;\n    output R50;\n    output R49;\n    output R48;\n    output R47;\n    output R46;\n    output R45;\n    output R44;\n    output R43;\n    output R42;\n    output R41;\n    output R40;\n    output R39;\n    output R38;\n    output R37;\n    output R36;\n    output R35;\n    output R34;\n    output R33;\n    output R32;\n    output R31;\n    output R30;\n    output R29;\n    output R28;\n    output R27;\n    output R26;\n    output R25;\n    output R24;\n    output R23;\n    output R22;\n    output R21;\n    output R20;\n    output R19;\n    output R18;\n    output R17;\n    output R16;\n    output R15;\n    output R14;\n    output R13;\n    output R12;\n    output R11;\n    output R10;\n    output R9;\n    output R8;\n    output R7;\n    output R6;\n    output R5;\n    output R4;\n    output R3;\n    output R2;\n    output R1;\n    output R0;\n    output CO53;\n    output CO52;\n    output CO51;\n    output CO50;\n    output CO49;\n    output CO48;\n    output CO47;\n    output CO46;\n    output CO45;\n    output CO44;\n    output CO43;\n    output CO42;\n    output CO41;\n    output CO40;\n    output CO39;\n    output CO38;\n    output CO37;\n    output CO36;\n    output CO35;\n    output CO34;\n    output CO33;\n    output CO32;\n    output CO31;\n    output CO30;\n    output CO29;\n    output CO28;\n    output CO27;\n    output CO26;\n    output CO25;\n    output CO24;\n    output CO23;\n    output CO22;\n    output CO21;\n    output CO20;\n    output CO19;\n    output CO18;\n    output CO17;\n    output CO16;\n    output CO15;\n    output CO14;\n    output CO13;\n    output CO12;\n    output CO11;\n    output CO10;\n    output CO9;\n    output CO8;\n    output CO7;\n    output CO6;\n    output CO5;\n    output CO4;\n    output CO3;\n    output CO2;\n    output CO1;\n    output CO0;\n    output EQZ;\n    output EQZM;\n    output EQOM;\n    output EQPAT;\n    output EQPATB;\n    output OVER;\n    output UNDER;\n    output OVERUNDER;\n    output SIGNEDR;\nendmodule\n\n(* blackbox *)\nmodule CLKDIVF (...);\n    parameter GSR = \"DISABLED\";\n    parameter DIV = \"2.0\";\n    input CLKI;\n    input RST;\n    input ALIGNWD;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule PCSCLKDIV (...);\n    parameter GSR = \"DISABLED\";\n    input CLKI;\n    input RST;\n    input SEL2;\n    input SEL1;\n    input SEL0;\n    output CDIV1;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule DCSC (...);\n    parameter DCSMODE = \"POS\";\n    input CLK1;\n    input CLK0;\n    input SEL1;\n    input SEL0;\n    input MODESEL;\n    output DCSOUT;\nendmodule\n\n(* blackbox *)\nmodule DCCA (...);\n    input CLKI;\n    input CE;\n    output CLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKSYNCB (...);\n    input ECLKI;\n    input STOP;\n    output ECLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKBRIDGECS (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output ECSOUT;\nendmodule\n\n(* blackbox *)\nmodule DELAYF (...);\n    parameter DEL_MODE = \"USER_DEFINED\";\n    parameter DEL_VALUE = 0;\n    input A;\n    input LOADN;\n    input MOVE;\n    input DIRECTION;\n    output Z;\n    output CFLAG;\nendmodule\n\n(* blackbox *)\nmodule DELAYG (...);\n    parameter DEL_MODE = \"USER_DEFINED\";\n    parameter DEL_VALUE = 0;\n    input A;\n    output Z;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule USRMCLK (...);\n    input USRMCLKI;\n    input USRMCLKTS;\nendmodule\n\n(* blackbox *)\nmodule DQSBUFM (...);\n    parameter DQS_LI_DEL_VAL = 4;\n    parameter DQS_LI_DEL_ADJ = \"FACTORYONLY\";\n    parameter DQS_LO_DEL_VAL = 0;\n    parameter DQS_LO_DEL_ADJ = \"FACTORYONLY\";\n    parameter GSR = \"ENABLED\";\n    input DQSI;\n    input READ1;\n    input READ0;\n    input READCLKSEL2;\n    input READCLKSEL1;\n    input READCLKSEL0;\n    input DDRDEL;\n    input ECLK;\n    input SCLK;\n    input RST;\n    input DYNDELAY7;\n    input DYNDELAY6;\n    input DYNDELAY5;\n    input DYNDELAY4;\n    input DYNDELAY3;\n    input DYNDELAY2;\n    input DYNDELAY1;\n    input DYNDELAY0;\n    input PAUSE;\n    input RDLOADN;\n    input RDMOVE;\n    input RDDIRECTION;\n    input WRLOADN;\n    input WRMOVE;\n    input WRDIRECTION;\n    output DQSR90;\n    output DQSW;\n    output DQSW270;\n    output RDPNTR2;\n    output RDPNTR1;\n    output RDPNTR0;\n    output WRPNTR2;\n    output WRPNTR1;\n    output WRPNTR0;\n    output DATAVALID;\n    output BURSTDET;\n    output RDCFLAG;\n    output WRCFLAG;\nendmodule\n\n(* blackbox *)\nmodule DDRDLLA (...);\n    parameter FORCE_MAX_DELAY = \"NO\";\n    parameter GSR = \"ENABLED\";\n    input CLK;\n    input RST;\n    input UDDCNTLN;\n    input FREEZE;\n    output DDRDEL;\n    output LOCK;\n    output DCNTL7;\n    output DCNTL6;\n    output DCNTL5;\n    output DCNTL4;\n    output DCNTL3;\n    output DCNTL2;\n    output DCNTL1;\n    output DCNTL0;\nendmodule\n\n(* blackbox *)\nmodule DLLDELD (...);\n    input A;\n    input DDRDEL;\n    input LOADN;\n    input MOVE;\n    input DIRECTION;\n    output Z;\n    output CFLAG;\nendmodule\n\n(* blackbox *)\nmodule IDDRX1F (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input RST;\n    output Q0;\n    output Q1;\nendmodule\n\n(* blackbox *)\nmodule IDDRX2F (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input ECLK;\n    input RST;\n    input ALIGNWD;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\nendmodule\n\n(* blackbox *)\nmodule IDDR71B (...);\n    parameter GSR = \"ENABLED\";\n    input D;\n    input SCLK;\n    input ECLK;\n    input RST;\n    input ALIGNWD;\n    output Q6;\n    output Q5;\n    output Q4;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\nendmodule\n\n(* blackbox *)\nmodule IDDRX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input DQSR90;\n    input D;\n    input RST;\n    input RDPNTR2;\n    input RDPNTR1;\n    input RDPNTR0;\n    input WRPNTR2;\n    input WRPNTR1;\n    input WRPNTR0;\n    output Q3;\n    output Q2;\n    output Q1;\n    output Q0;\n    output QWL;\nendmodule\n\n(* blackbox *)\nmodule ODDRX1F (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input RST;\n    input D0;\n    input D1;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2F (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input RST;\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDR71B (...);\n    parameter GSR = \"ENABLED\";\n    input SCLK;\n    input ECLK;\n    input RST;\n    input D6;\n    input D5;\n    input D4;\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule OSHX2A (...);\n    parameter GSR = \"ENABLED\";\n    input D1;\n    input D0;\n    input SCLK;\n    input ECLK;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    parameter REGSET = \"SET\";\n    input T1;\n    input T0;\n    input SCLK;\n    input ECLK;\n    input DQSW270;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule TSHX2DQSA (...);\n    parameter GSR = \"ENABLED\";\n    parameter REGSET = \"SET\";\n    input T1;\n    input T0;\n    input SCLK;\n    input ECLK;\n    input DQSW;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQA (...);\n    parameter GSR = \"ENABLED\";\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    input DQSW270;\n    input SCLK;\n    input ECLK;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule ODDRX2DQSB (...);\n    parameter GSR = \"ENABLED\";\n    input D3;\n    input D2;\n    input D1;\n    input D0;\n    input SCLK;\n    input ECLK;\n    input DQSW;\n    input RST;\n    output Q;\nendmodule\n\n(* blackbox *)\nmodule EHXPLLL (...);\n    parameter CLKI_DIV = 1;\n    parameter CLKFB_DIV = 1;\n    parameter CLKOP_DIV = 8;\n    parameter CLKOS_DIV = 8;\n    parameter CLKOS2_DIV = 8;\n    parameter CLKOS3_DIV = 8;\n    parameter CLKOP_ENABLE = \"ENABLED\";\n    parameter CLKOS_ENABLE = \"DISABLED\";\n    parameter CLKOS2_ENABLE = \"DISABLED\";\n    parameter CLKOS3_ENABLE = \"DISABLED\";\n    parameter CLKOP_CPHASE = 0;\n    parameter CLKOS_CPHASE = 0;\n    parameter CLKOS2_CPHASE = 0;\n    parameter CLKOS3_CPHASE = 0;\n    parameter CLKOP_FPHASE = 0;\n    parameter CLKOS_FPHASE = 0;\n    parameter CLKOS2_FPHASE = 0;\n    parameter CLKOS3_FPHASE = 0;\n    parameter FEEDBK_PATH = \"CLKOP\";\n    parameter CLKOP_TRIM_POL = \"RISING\";\n    parameter CLKOP_TRIM_DELAY = 0;\n    parameter CLKOS_TRIM_POL = \"RISING\";\n    parameter CLKOS_TRIM_DELAY = 0;\n    parameter OUTDIVIDER_MUXA = \"DIVA\";\n    parameter OUTDIVIDER_MUXB = \"DIVB\";\n    parameter OUTDIVIDER_MUXC = \"DIVC\";\n    parameter OUTDIVIDER_MUXD = \"DIVD\";\n    parameter PLL_LOCK_MODE = 0;\n    parameter PLL_LOCK_DELAY = 200;\n    parameter STDBY_ENABLE = \"DISABLED\";\n    parameter REFIN_RESET = \"DISABLED\";\n    parameter SYNC_ENABLE = \"DISABLED\";\n    parameter INT_LOCK_STICKY = \"ENABLED\";\n    parameter DPHASE_SOURCE = \"DISABLED\";\n    parameter PLLRST_ENA = \"DISABLED\";\n    parameter INTFB_WAKE = \"DISABLED\";\n    input CLKI;\n    input CLKFB;\n    input PHASESEL1;\n    input PHASESEL0;\n    input PHASEDIR;\n    input PHASESTEP;\n    input PHASELOADREG;\n    input STDBY;\n    input PLLWAKESYNC;\n    input RST;\n    input ENCLKOP;\n    input ENCLKOS;\n    input ENCLKOS2;\n    input ENCLKOS3;\n    output CLKOP;\n    output CLKOS;\n    output CLKOS2;\n    output CLKOS3;\n    output LOCK;\n    output INTLOCK;\n    output REFCLK;\n    output CLKINTFB;\nendmodule\n\n(* blackbox *)\nmodule DTR (...);\n    parameter DTR_TEMP = 25;\n    input STARTPULSE;\n    output DTROUT7;\n    output DTROUT6;\n    output DTROUT5;\n    output DTROUT4;\n    output DTROUT3;\n    output DTROUT2;\n    output DTROUT1;\n    output DTROUT0;\nendmodule\n\n(* blackbox *)\nmodule OSCG (...);\n    parameter DIV = 128;\n    output OSC;\nendmodule\n\n(* blackbox *)\nmodule EXTREFB (...);\n    parameter REFCK_PWDNB = \"DONTCARE\";\n    parameter REFCK_RTERM = \"DONTCARE\";\n    parameter REFCK_DCBIAS_EN = \"DONTCARE\";\n    (* iopad_external_pin *)\n    input REFCLKP;\n    (* iopad_external_pin *)\n    input REFCLKN;\n    output REFCLKO;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule JTAGG (...);\n    parameter ER1 = \"ENABLED\";\n    parameter ER2 = \"ENABLED\";\n    (* iopad_external_pin *)\n    input TCK;\n    (* iopad_external_pin *)\n    input TMS;\n    (* iopad_external_pin *)\n    input TDI;\n    input JTDO2;\n    input JTDO1;\n    (* iopad_external_pin *)\n    output TDO;\n    output JTDI;\n    output JTCK;\n    output JRTI2;\n    output JRTI1;\n    output JSHIFT;\n    output JUPDATE;\n    output JRSTN;\n    output JCE2;\n    output JCE1;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule DCUA (...);\n    parameter D_MACROPDB = \"DONTCARE\";\n    parameter D_IB_PWDNB = \"DONTCARE\";\n    parameter D_XGE_MODE = \"DONTCARE\";\n    parameter D_LOW_MARK = \"DONTCARE\";\n    parameter D_HIGH_MARK = \"DONTCARE\";\n    parameter D_BUS8BIT_SEL = \"DONTCARE\";\n    parameter D_CDR_LOL_SET = \"DONTCARE\";\n    parameter D_BITCLK_LOCAL_EN = \"DONTCARE\";\n    parameter D_BITCLK_ND_EN = \"DONTCARE\";\n    parameter D_BITCLK_FROM_ND_EN = \"DONTCARE\";\n    parameter D_SYNC_LOCAL_EN = \"DONTCARE\";\n    parameter D_SYNC_ND_EN = \"DONTCARE\";\n    parameter CH0_UC_MODE = \"DONTCARE\";\n    parameter CH1_UC_MODE = \"DONTCARE\";\n    parameter CH0_PCIE_MODE = \"DONTCARE\";\n    parameter CH1_PCIE_MODE = \"DONTCARE\";\n    parameter CH0_RIO_MODE = \"DONTCARE\";\n    parameter CH1_RIO_MODE = \"DONTCARE\";\n    parameter CH0_WA_MODE = \"DONTCARE\";\n    parameter CH1_WA_MODE = \"DONTCARE\";\n    parameter CH0_INVERT_RX = \"DONTCARE\";\n    parameter CH1_INVERT_RX = \"DONTCARE\";\n    parameter CH0_INVERT_TX = \"DONTCARE\";\n    parameter CH1_INVERT_TX = \"DONTCARE\";\n    parameter CH0_PRBS_SELECTION = \"DONTCARE\";\n    parameter CH1_PRBS_SELECTION = \"DONTCARE\";\n    parameter CH0_GE_AN_ENABLE = \"DONTCARE\";\n    parameter CH1_GE_AN_ENABLE = \"DONTCARE\";\n    parameter CH0_PRBS_LOCK = \"DONTCARE\";\n    parameter CH1_PRBS_LOCK = \"DONTCARE\";\n    parameter CH0_PRBS_ENABLE = \"DONTCARE\";\n    parameter CH1_PRBS_ENABLE = \"DONTCARE\";\n    parameter CH0_ENABLE_CG_ALIGN = \"DONTCARE\";\n    parameter CH1_ENABLE_CG_ALIGN = \"DONTCARE\";\n    parameter CH0_TX_GEAR_MODE = \"DONTCARE\";\n    parameter CH1_TX_GEAR_MODE = \"DONTCARE\";\n    parameter CH0_RX_GEAR_MODE = \"DONTCARE\";\n    parameter CH1_RX_GEAR_MODE = \"DONTCARE\";\n    parameter CH0_PCS_DET_TIME_SEL = \"DONTCARE\";\n    parameter CH1_PCS_DET_TIME_SEL = \"DONTCARE\";\n    parameter CH0_PCIE_EI_EN = \"DONTCARE\";\n    parameter CH1_PCIE_EI_EN = \"DONTCARE\";\n    parameter CH0_TX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH1_TX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH0_ENC_BYPASS = \"DONTCARE\";\n    parameter CH1_ENC_BYPASS = \"DONTCARE\";\n    parameter CH0_SB_BYPASS = \"DONTCARE\";\n    parameter CH1_SB_BYPASS = \"DONTCARE\";\n    parameter CH0_RX_SB_BYPASS = \"DONTCARE\";\n    parameter CH1_RX_SB_BYPASS = \"DONTCARE\";\n    parameter CH0_WA_BYPASS = \"DONTCARE\";\n    parameter CH1_WA_BYPASS = \"DONTCARE\";\n    parameter CH0_DEC_BYPASS = \"DONTCARE\";\n    parameter CH1_DEC_BYPASS = \"DONTCARE\";\n    parameter CH0_CTC_BYPASS = \"DONTCARE\";\n    parameter CH1_CTC_BYPASS = \"DONTCARE\";\n    parameter CH0_RX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH1_RX_GEAR_BYPASS = \"DONTCARE\";\n    parameter CH0_LSM_DISABLE = \"DONTCARE\";\n    parameter CH1_LSM_DISABLE = \"DONTCARE\";\n    parameter CH0_MATCH_2_ENABLE = \"DONTCARE\";\n    parameter CH1_MATCH_2_ENABLE = \"DONTCARE\";\n    parameter CH0_MATCH_4_ENABLE = \"DONTCARE\";\n    parameter CH1_MATCH_4_ENABLE = \"DONTCARE\";\n    parameter CH0_MIN_IPG_CNT = \"DONTCARE\";\n    parameter CH1_MIN_IPG_CNT = \"DONTCARE\";\n    parameter CH0_CC_MATCH_1 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_1 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_2 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_2 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_3 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_3 = \"DONTCARE\";\n    parameter CH0_CC_MATCH_4 = \"DONTCARE\";\n    parameter CH1_CC_MATCH_4 = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_MASK = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_MASK = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_A = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_A = \"DONTCARE\";\n    parameter CH0_UDF_COMMA_B = \"DONTCARE\";\n    parameter CH1_UDF_COMMA_B = \"DONTCARE\";\n    parameter CH0_RX_DCO_CK_DIV = \"DONTCARE\";\n    parameter CH1_RX_DCO_CK_DIV = \"DONTCARE\";\n    parameter CH0_RCV_DCC_EN = \"DONTCARE\";\n    parameter CH1_RCV_DCC_EN = \"DONTCARE\";\n    parameter CH0_REQ_LVL_SET = \"DONTCARE\";\n    parameter CH1_REQ_LVL_SET = \"DONTCARE\";\n    parameter CH0_REQ_EN = \"DONTCARE\";\n    parameter CH1_REQ_EN = \"DONTCARE\";\n    parameter CH0_RTERM_RX = \"DONTCARE\";\n    parameter CH1_RTERM_RX = \"DONTCARE\";\n    parameter CH0_PDEN_SEL = \"DONTCARE\";\n    parameter CH1_PDEN_SEL = \"DONTCARE\";\n    parameter CH0_LDR_RX2CORE_SEL = \"DONTCARE\";\n    parameter CH1_LDR_RX2CORE_SEL = \"DONTCARE\";\n    parameter CH0_LDR_CORE2TX_SEL = \"DONTCARE\";\n    parameter CH1_LDR_CORE2TX_SEL = \"DONTCARE\";\n    parameter CH0_TPWDNB = \"DONTCARE\";\n    parameter CH1_TPWDNB = \"DONTCARE\";\n    parameter CH0_RATE_MODE_TX = \"DONTCARE\";\n    parameter CH1_RATE_MODE_TX = \"DONTCARE\";\n    parameter CH0_RTERM_TX = \"DONTCARE\";\n    parameter CH1_RTERM_TX = \"DONTCARE\";\n    parameter CH0_TX_CM_SEL = \"DONTCARE\";\n    parameter CH1_TX_CM_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_PRE_EN = \"DONTCARE\";\n    parameter CH1_TDRV_PRE_EN = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE0_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE0_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE1_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE1_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE2_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE2_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE3_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE3_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE4_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE4_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE5_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE5_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE0_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE0_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE1_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE1_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE2_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE2_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE3_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE3_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE4_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE4_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_SLICE5_CUR = \"DONTCARE\";\n    parameter CH1_TDRV_SLICE5_CUR = \"DONTCARE\";\n    parameter CH0_TDRV_DAT_SEL = \"DONTCARE\";\n    parameter CH1_TDRV_DAT_SEL = \"DONTCARE\";\n    parameter CH0_TX_DIV11_SEL = \"DONTCARE\";\n    parameter CH1_TX_DIV11_SEL = \"DONTCARE\";\n    parameter CH0_RPWDNB = \"DONTCARE\";\n    parameter CH1_RPWDNB = \"DONTCARE\";\n    parameter CH0_RATE_MODE_RX = \"DONTCARE\";\n    parameter CH1_RATE_MODE_RX = \"DONTCARE\";\n    parameter CH0_RLOS_SEL = \"DONTCARE\";\n    parameter CH1_RLOS_SEL = \"DONTCARE\";\n    parameter CH0_RX_LOS_LVL = \"DONTCARE\";\n    parameter CH1_RX_LOS_LVL = \"DONTCARE\";\n    parameter CH0_RX_LOS_CEQ = \"DONTCARE\";\n    parameter CH1_RX_LOS_CEQ = \"DONTCARE\";\n    parameter CH0_RX_LOS_HYST_EN = \"DONTCARE\";\n    parameter CH1_RX_LOS_HYST_EN = \"DONTCARE\";\n    parameter CH0_RX_LOS_EN = \"DONTCARE\";\n    parameter CH1_RX_LOS_EN = \"DONTCARE\";\n    parameter CH0_RX_DIV11_SEL = \"DONTCARE\";\n    parameter CH1_RX_DIV11_SEL = \"DONTCARE\";\n    parameter CH0_SEL_SD_RX_CLK = \"DONTCARE\";\n    parameter CH1_SEL_SD_RX_CLK = \"DONTCARE\";\n    parameter CH0_FF_RX_H_CLK_EN = \"DONTCARE\";\n    parameter CH1_FF_RX_H_CLK_EN = \"DONTCARE\";\n    parameter CH0_FF_RX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH1_FF_RX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH0_FF_TX_H_CLK_EN = \"DONTCARE\";\n    parameter CH1_FF_TX_H_CLK_EN = \"DONTCARE\";\n    parameter CH0_FF_TX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH1_FF_TX_F_CLK_DIS = \"DONTCARE\";\n    parameter CH0_RX_RATE_SEL = \"DONTCARE\";\n    parameter CH1_RX_RATE_SEL = \"DONTCARE\";\n    parameter CH0_TDRV_POST_EN = \"DONTCARE\";\n    parameter CH1_TDRV_POST_EN = \"DONTCARE\";\n    parameter CH0_TX_POST_SIGN = \"DONTCARE\";\n    parameter CH1_TX_POST_SIGN = \"DONTCARE\";\n    parameter CH0_TX_PRE_SIGN = \"DONTCARE\";\n    parameter CH1_TX_PRE_SIGN = \"DONTCARE\";\n    parameter CH0_RXTERM_CM = \"DONTCARE\";\n    parameter CH1_RXTERM_CM = \"DONTCARE\";\n    parameter CH0_RXIN_CM = \"DONTCARE\";\n    parameter CH1_RXIN_CM = \"DONTCARE\";\n    parameter CH0_LEQ_OFFSET_SEL = \"DONTCARE\";\n    parameter CH1_LEQ_OFFSET_SEL = \"DONTCARE\";\n    parameter CH0_LEQ_OFFSET_TRIM = \"DONTCARE\";\n    parameter CH1_LEQ_OFFSET_TRIM = \"DONTCARE\";\n    parameter D_TX_MAX_RATE = \"DONTCARE\";\n    parameter CH0_CDR_MAX_RATE = \"DONTCARE\";\n    parameter CH1_CDR_MAX_RATE = \"DONTCARE\";\n    parameter CH0_TXAMPLITUDE = \"DONTCARE\";\n    parameter CH1_TXAMPLITUDE = \"DONTCARE\";\n    parameter CH0_TXDEPRE = \"DONTCARE\";\n    parameter CH1_TXDEPRE = \"DONTCARE\";\n    parameter CH0_TXDEPOST = \"DONTCARE\";\n    parameter CH1_TXDEPOST = \"DONTCARE\";\n    parameter CH0_PROTOCOL = \"DONTCARE\";\n    parameter CH1_PROTOCOL = \"DONTCARE\";\n    parameter D_ISETLOS = \"DONTCARE\";\n    parameter D_SETIRPOLY_AUX = \"DONTCARE\";\n    parameter D_SETICONST_AUX = \"DONTCARE\";\n    parameter D_SETIRPOLY_CH = \"DONTCARE\";\n    parameter D_SETICONST_CH = \"DONTCARE\";\n    parameter D_REQ_ISET = \"DONTCARE\";\n    parameter D_PD_ISET = \"DONTCARE\";\n    parameter D_DCO_CALIB_TIME_SEL = \"DONTCARE\";\n    parameter CH0_DCOCTLGI = \"DONTCARE\";\n    parameter CH1_DCOCTLGI = \"DONTCARE\";\n    parameter CH0_DCOATDDLY = \"DONTCARE\";\n    parameter CH1_DCOATDDLY = \"DONTCARE\";\n    parameter CH0_DCOATDCFG = \"DONTCARE\";\n    parameter CH1_DCOATDCFG = \"DONTCARE\";\n    parameter CH0_DCOBYPSATD = \"DONTCARE\";\n    parameter CH1_DCOBYPSATD = \"DONTCARE\";\n    parameter CH0_DCOSCALEI = \"DONTCARE\";\n    parameter CH1_DCOSCALEI = \"DONTCARE\";\n    parameter CH0_DCOITUNE4LSB = \"DONTCARE\";\n    parameter CH1_DCOITUNE4LSB = \"DONTCARE\";\n    parameter CH0_DCOIOSTUNE = \"DONTCARE\";\n    parameter CH1_DCOIOSTUNE = \"DONTCARE\";\n    parameter CH0_DCODISBDAVOID = \"DONTCARE\";\n    parameter CH1_DCODISBDAVOID = \"DONTCARE\";\n    parameter CH0_DCOCALDIV = \"DONTCARE\";\n    parameter CH1_DCOCALDIV = \"DONTCARE\";\n    parameter CH0_DCONUOFLSB = \"DONTCARE\";\n    parameter CH1_DCONUOFLSB = \"DONTCARE\";\n    parameter CH0_DCOIUPDNX2 = \"DONTCARE\";\n    parameter CH1_DCOIUPDNX2 = \"DONTCARE\";\n    parameter CH0_DCOSTEP = \"DONTCARE\";\n    parameter CH1_DCOSTEP = \"DONTCARE\";\n    parameter CH0_DCOSTARTVAL = \"DONTCARE\";\n    parameter CH1_DCOSTARTVAL = \"DONTCARE\";\n    parameter CH0_DCOFLTDAC = \"DONTCARE\";\n    parameter CH1_DCOFLTDAC = \"DONTCARE\";\n    parameter CH0_DCOITUNE = \"DONTCARE\";\n    parameter CH1_DCOITUNE = \"DONTCARE\";\n    parameter CH0_DCOFTNRG = \"DONTCARE\";\n    parameter CH1_DCOFTNRG = \"DONTCARE\";\n    parameter CH0_CDR_CNT4SEL = \"DONTCARE\";\n    parameter CH1_CDR_CNT4SEL = \"DONTCARE\";\n    parameter CH0_CDR_CNT8SEL = \"DONTCARE\";\n    parameter CH1_CDR_CNT8SEL = \"DONTCARE\";\n    parameter CH0_BAND_THRESHOLD = \"DONTCARE\";\n    parameter CH1_BAND_THRESHOLD = \"DONTCARE\";\n    parameter CH0_AUTO_FACQ_EN = \"DONTCARE\";\n    parameter CH1_AUTO_FACQ_EN = \"DONTCARE\";\n    parameter CH0_AUTO_CALIB_EN = \"DONTCARE\";\n    parameter CH1_AUTO_CALIB_EN = \"DONTCARE\";\n    parameter CH0_CALIB_CK_MODE = \"DONTCARE\";\n    parameter CH1_CALIB_CK_MODE = \"DONTCARE\";\n    parameter CH0_REG_BAND_OFFSET = \"DONTCARE\";\n    parameter CH1_REG_BAND_OFFSET = \"DONTCARE\";\n    parameter CH0_REG_BAND_SEL = \"DONTCARE\";\n    parameter CH1_REG_BAND_SEL = \"DONTCARE\";\n    parameter CH0_REG_IDAC_SEL = \"DONTCARE\";\n    parameter CH1_REG_IDAC_SEL = \"DONTCARE\";\n    parameter CH0_REG_IDAC_EN = \"DONTCARE\";\n    parameter CH1_REG_IDAC_EN = \"DONTCARE\";\n    parameter D_TXPLL_PWDNB = \"DONTCARE\";\n    parameter D_SETPLLRC = \"DONTCARE\";\n    parameter D_REFCK_MODE = \"DONTCARE\";\n    parameter D_TX_VCO_CK_DIV = \"DONTCARE\";\n    parameter D_PLL_LOL_SET = \"DONTCARE\";\n    parameter D_RG_EN = \"DONTCARE\";\n    parameter D_RG_SET = \"DONTCARE\";\n    parameter D_CMUSETISCL4VCO = \"DONTCARE\";\n    parameter D_CMUSETI4VCO = \"DONTCARE\";\n    parameter D_CMUSETINITVCT = \"DONTCARE\";\n    parameter D_CMUSETZGM = \"DONTCARE\";\n    parameter D_CMUSETP2AGM = \"DONTCARE\";\n    parameter D_CMUSETP1GM = \"DONTCARE\";\n    parameter D_CMUSETI4CPZ = \"DONTCARE\";\n    parameter D_CMUSETI4CPP = \"DONTCARE\";\n    parameter D_CMUSETICP4Z = \"DONTCARE\";\n    parameter D_CMUSETICP4P = \"DONTCARE\";\n    parameter D_CMUSETBIASI = \"DONTCARE\";\n    (* iopad_external_pin *)\n    (* iopad_external_pin *)\n    input CH0_HDINP;\n    (* iopad_external_pin *)\n    input CH1_HDINP;\n    (* iopad_external_pin *)\n    input CH0_HDINN;\n    (* iopad_external_pin *)\n    input CH1_HDINN;\n    input D_TXBIT_CLKP_FROM_ND;\n    input D_TXBIT_CLKN_FROM_ND;\n    input D_SYNC_ND;\n    input D_TXPLL_LOL_FROM_ND;\n    input CH0_RX_REFCLK;\n    input CH1_RX_REFCLK;\n    input CH0_FF_RXI_CLK;\n    input CH1_FF_RXI_CLK;\n    input CH0_FF_TXI_CLK;\n    input CH1_FF_TXI_CLK;\n    input CH0_FF_EBRD_CLK;\n    input CH1_FF_EBRD_CLK;\n    input CH0_FF_TX_D_0;\n    input CH1_FF_TX_D_0;\n    input CH0_FF_TX_D_1;\n    input CH1_FF_TX_D_1;\n    input CH0_FF_TX_D_2;\n    input CH1_FF_TX_D_2;\n    input CH0_FF_TX_D_3;\n    input CH1_FF_TX_D_3;\n    input CH0_FF_TX_D_4;\n    input CH1_FF_TX_D_4;\n    input CH0_FF_TX_D_5;\n    input CH1_FF_TX_D_5;\n    input CH0_FF_TX_D_6;\n    input CH1_FF_TX_D_6;\n    input CH0_FF_TX_D_7;\n    input CH1_FF_TX_D_7;\n    input CH0_FF_TX_D_8;\n    input CH1_FF_TX_D_8;\n    input CH0_FF_TX_D_9;\n    input CH1_FF_TX_D_9;\n    input CH0_FF_TX_D_10;\n    input CH1_FF_TX_D_10;\n    input CH0_FF_TX_D_11;\n    input CH1_FF_TX_D_11;\n    input CH0_FF_TX_D_12;\n    input CH1_FF_TX_D_12;\n    input CH0_FF_TX_D_13;\n    input CH1_FF_TX_D_13;\n    input CH0_FF_TX_D_14;\n    input CH1_FF_TX_D_14;\n    input CH0_FF_TX_D_15;\n    input CH1_FF_TX_D_15;\n    input CH0_FF_TX_D_16;\n    input CH1_FF_TX_D_16;\n    input CH0_FF_TX_D_17;\n    input CH1_FF_TX_D_17;\n    input CH0_FF_TX_D_18;\n    input CH1_FF_TX_D_18;\n    input CH0_FF_TX_D_19;\n    input CH1_FF_TX_D_19;\n    input CH0_FF_TX_D_20;\n    input CH1_FF_TX_D_20;\n    input CH0_FF_TX_D_21;\n    input CH1_FF_TX_D_21;\n    input CH0_FF_TX_D_22;\n    input CH1_FF_TX_D_22;\n    input CH0_FF_TX_D_23;\n    input CH1_FF_TX_D_23;\n    input CH0_FFC_EI_EN;\n    input CH1_FFC_EI_EN;\n    input CH0_FFC_PCIE_DET_EN;\n    input CH1_FFC_PCIE_DET_EN;\n    input CH0_FFC_PCIE_CT;\n    input CH1_FFC_PCIE_CT;\n    input CH0_FFC_SB_INV_RX;\n    input CH1_FFC_SB_INV_RX;\n    input CH0_FFC_ENABLE_CGALIGN;\n    input CH1_FFC_ENABLE_CGALIGN;\n    input CH0_FFC_SIGNAL_DETECT;\n    input CH1_FFC_SIGNAL_DETECT;\n    input CH0_FFC_FB_LOOPBACK;\n    input CH1_FFC_FB_LOOPBACK;\n    input CH0_FFC_SB_PFIFO_LP;\n    input CH1_FFC_SB_PFIFO_LP;\n    input CH0_FFC_PFIFO_CLR;\n    input CH1_FFC_PFIFO_CLR;\n    input CH0_FFC_RATE_MODE_RX;\n    input CH1_FFC_RATE_MODE_RX;\n    input CH0_FFC_RATE_MODE_TX;\n    input CH1_FFC_RATE_MODE_TX;\n    input CH0_FFC_DIV11_MODE_RX;\n    input CH1_FFC_DIV11_MODE_RX;\n    input CH0_FFC_RX_GEAR_MODE;\n    input CH1_FFC_RX_GEAR_MODE;\n    input CH0_FFC_TX_GEAR_MODE;\n    input CH1_FFC_TX_GEAR_MODE;\n    input CH0_FFC_DIV11_MODE_TX;\n    input CH1_FFC_DIV11_MODE_TX;\n    input CH0_FFC_LDR_CORE2TX_EN;\n    input CH1_FFC_LDR_CORE2TX_EN;\n    input CH0_FFC_LANE_TX_RST;\n    input CH1_FFC_LANE_TX_RST;\n    input CH0_FFC_LANE_RX_RST;\n    input CH1_FFC_LANE_RX_RST;\n    input CH0_FFC_RRST;\n    input CH1_FFC_RRST;\n    input CH0_FFC_TXPWDNB;\n    input CH1_FFC_TXPWDNB;\n    input CH0_FFC_RXPWDNB;\n    input CH1_FFC_RXPWDNB;\n    input CH0_LDR_CORE2TX;\n    input CH1_LDR_CORE2TX;\n    input D_SCIWDATA0;\n    input D_SCIWDATA1;\n    input D_SCIWDATA2;\n    input D_SCIWDATA3;\n    input D_SCIWDATA4;\n    input D_SCIWDATA5;\n    input D_SCIWDATA6;\n    input D_SCIWDATA7;\n    input D_SCIADDR0;\n    input D_SCIADDR1;\n    input D_SCIADDR2;\n    input D_SCIADDR3;\n    input D_SCIADDR4;\n    input D_SCIADDR5;\n    input D_SCIENAUX;\n    input D_SCISELAUX;\n    input CH0_SCIEN;\n    input CH1_SCIEN;\n    input CH0_SCISEL;\n    input CH1_SCISEL;\n    input D_SCIRD;\n    input D_SCIWSTN;\n    input D_CYAWSTN;\n    input D_FFC_SYNC_TOGGLE;\n    input D_FFC_DUAL_RST;\n    input D_FFC_MACRO_RST;\n    input D_FFC_MACROPDB;\n    input D_FFC_TRST;\n    input CH0_FFC_CDR_EN_BITSLIP;\n    input CH1_FFC_CDR_EN_BITSLIP;\n    input D_SCAN_ENABLE;\n    input D_SCAN_IN_0;\n    input D_SCAN_IN_1;\n    input D_SCAN_IN_2;\n    input D_SCAN_IN_3;\n    input D_SCAN_IN_4;\n    input D_SCAN_IN_5;\n    input D_SCAN_IN_6;\n    input D_SCAN_IN_7;\n    input D_SCAN_MODE;\n    input D_SCAN_RESET;\n    input D_CIN0;\n    input D_CIN1;\n    input D_CIN2;\n    input D_CIN3;\n    input D_CIN4;\n    input D_CIN5;\n    input D_CIN6;\n    input D_CIN7;\n    input D_CIN8;\n    input D_CIN9;\n    input D_CIN10;\n    input D_CIN11;\n    output CH0_HDOUTP;\n    output CH1_HDOUTP;\n    output CH0_HDOUTN;\n    output CH1_HDOUTN;\n    output D_TXBIT_CLKP_TO_ND;\n    output D_TXBIT_CLKN_TO_ND;\n    output D_SYNC_PULSE2ND;\n    output D_TXPLL_LOL_TO_ND;\n    output CH0_FF_RX_F_CLK;\n    output CH1_FF_RX_F_CLK;\n    output CH0_FF_RX_H_CLK;\n    output CH1_FF_RX_H_CLK;\n    output CH0_FF_TX_F_CLK;\n    output CH1_FF_TX_F_CLK;\n    output CH0_FF_TX_H_CLK;\n    output CH1_FF_TX_H_CLK;\n    output CH0_FF_RX_PCLK;\n    output CH1_FF_RX_PCLK;\n    output CH0_FF_TX_PCLK;\n    output CH1_FF_TX_PCLK;\n    output CH0_FF_RX_D_0;\n    output CH1_FF_RX_D_0;\n    output CH0_FF_RX_D_1;\n    output CH1_FF_RX_D_1;\n    output CH0_FF_RX_D_2;\n    output CH1_FF_RX_D_2;\n    output CH0_FF_RX_D_3;\n    output CH1_FF_RX_D_3;\n    output CH0_FF_RX_D_4;\n    output CH1_FF_RX_D_4;\n    output CH0_FF_RX_D_5;\n    output CH1_FF_RX_D_5;\n    output CH0_FF_RX_D_6;\n    output CH1_FF_RX_D_6;\n    output CH0_FF_RX_D_7;\n    output CH1_FF_RX_D_7;\n    output CH0_FF_RX_D_8;\n    output CH1_FF_RX_D_8;\n    output CH0_FF_RX_D_9;\n    output CH1_FF_RX_D_9;\n    output CH0_FF_RX_D_10;\n    output CH1_FF_RX_D_10;\n    output CH0_FF_RX_D_11;\n    output CH1_FF_RX_D_11;\n    output CH0_FF_RX_D_12;\n    output CH1_FF_RX_D_12;\n    output CH0_FF_RX_D_13;\n    output CH1_FF_RX_D_13;\n    output CH0_FF_RX_D_14;\n    output CH1_FF_RX_D_14;\n    output CH0_FF_RX_D_15;\n    output CH1_FF_RX_D_15;\n    output CH0_FF_RX_D_16;\n    output CH1_FF_RX_D_16;\n    output CH0_FF_RX_D_17;\n    output CH1_FF_RX_D_17;\n    output CH0_FF_RX_D_18;\n    output CH1_FF_RX_D_18;\n    output CH0_FF_RX_D_19;\n    output CH1_FF_RX_D_19;\n    output CH0_FF_RX_D_20;\n    output CH1_FF_RX_D_20;\n    output CH0_FF_RX_D_21;\n    output CH1_FF_RX_D_21;\n    output CH0_FF_RX_D_22;\n    output CH1_FF_RX_D_22;\n    output CH0_FF_RX_D_23;\n    output CH1_FF_RX_D_23;\n    output CH0_FFS_PCIE_DONE;\n    output CH1_FFS_PCIE_DONE;\n    output CH0_FFS_PCIE_CON;\n    output CH1_FFS_PCIE_CON;\n    output CH0_FFS_RLOS;\n    output CH1_FFS_RLOS;\n    output CH0_FFS_LS_SYNC_STATUS;\n    output CH1_FFS_LS_SYNC_STATUS;\n    output CH0_FFS_CC_UNDERRUN;\n    output CH1_FFS_CC_UNDERRUN;\n    output CH0_FFS_CC_OVERRUN;\n    output CH1_FFS_CC_OVERRUN;\n    output CH0_FFS_RXFBFIFO_ERROR;\n    output CH1_FFS_RXFBFIFO_ERROR;\n    output CH0_FFS_TXFBFIFO_ERROR;\n    output CH1_FFS_TXFBFIFO_ERROR;\n    output CH0_FFS_RLOL;\n    output CH1_FFS_RLOL;\n    output CH0_FFS_SKP_ADDED;\n    output CH1_FFS_SKP_ADDED;\n    output CH0_FFS_SKP_DELETED;\n    output CH1_FFS_SKP_DELETED;\n    output CH0_LDR_RX2CORE;\n    output CH1_LDR_RX2CORE;\n    output D_SCIRDATA0;\n    output D_SCIRDATA1;\n    output D_SCIRDATA2;\n    output D_SCIRDATA3;\n    output D_SCIRDATA4;\n    output D_SCIRDATA5;\n    output D_SCIRDATA6;\n    output D_SCIRDATA7;\n    output D_SCIINT;\n    output D_SCAN_OUT_0;\n    output D_SCAN_OUT_1;\n    output D_SCAN_OUT_2;\n    output D_SCAN_OUT_3;\n    output D_SCAN_OUT_4;\n    output D_SCAN_OUT_5;\n    output D_SCAN_OUT_6;\n    output D_SCAN_OUT_7;\n    output D_COUT0;\n    output D_COUT1;\n    output D_COUT2;\n    output D_COUT3;\n    output D_COUT4;\n    output D_COUT5;\n    output D_COUT6;\n    output D_COUT7;\n    output D_COUT8;\n    output D_COUT9;\n    output D_COUT10;\n    output D_COUT11;\n    output D_COUT12;\n    output D_COUT13;\n    output D_COUT14;\n    output D_COUT15;\n    output D_COUT16;\n    output D_COUT17;\n    output D_COUT18;\n    output D_COUT19;\n    input D_REFCLKI;\n    output D_FFS_PLOL;\nendmodule\n\n",
+            "cells_bb_nexus.v": new URL("./share/lattice/cells_bb_nexus.v", import.meta.url),
             "cells_bb_xo2.v": "// Created by cells_xtra.py from Lattice models\n\n(* blackbox *) (* keep *)\nmodule GSR (...);\n    input GSR;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule SGSR (...);\n    input GSR;\n    input CLK;\nendmodule\n\n(* blackbox *)\nmodule DP8KC (...);\n    parameter DATA_WIDTH_A = 9;\n    parameter DATA_WIDTH_B = 9;\n    parameter REGMODE_A = \"NOREG\";\n    parameter REGMODE_B = \"NOREG\";\n    parameter CSDECODE_A = \"0b000\";\n    parameter CSDECODE_B = \"0b000\";\n    parameter WRITEMODE_A = \"NORMAL\";\n    parameter WRITEMODE_B = \"NORMAL\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DIA8;\n    input DIA7;\n    input DIA6;\n    input DIA5;\n    input DIA4;\n    input DIA3;\n    input DIA2;\n    input DIA1;\n    input DIA0;\n    input ADA12;\n    input ADA11;\n    input ADA10;\n    input ADA9;\n    input ADA8;\n    input ADA7;\n    input ADA6;\n    input ADA5;\n    input ADA4;\n    input ADA3;\n    input ADA2;\n    input ADA1;\n    input ADA0;\n    input CEA;\n    input OCEA;\n    input CLKA;\n    input WEA;\n    input CSA2;\n    input CSA1;\n    input CSA0;\n    input RSTA;\n    input DIB8;\n    input DIB7;\n    input DIB6;\n    input DIB5;\n    input DIB4;\n    input DIB3;\n    input DIB2;\n    input DIB1;\n    input DIB0;\n    input ADB12;\n    input ADB11;\n    input ADB10;\n    input ADB9;\n    input ADB8;\n    input ADB7;\n    input ADB6;\n    input ADB5;\n    input ADB4;\n    input ADB3;\n    input ADB2;\n    input ADB1;\n    input ADB0;\n    input CEB;\n    input OCEB;\n    input CLKB;\n    input WEB;\n    input CSB2;\n    input CSB1;\n    input CSB0;\n    input RSTB;\n    output DOA8;\n    output DOA7;\n    output DOA6;\n    output DOA5;\n    output DOA4;\n    output DOA3;\n    output DOA2;\n    output DOA1;\n    output DOA0;\n    output DOB8;\n    output DOB7;\n    output DOB6;\n    output DOB5;\n    output DOB4;\n    output DOB3;\n    output DOB2;\n    output DOB1;\n    output DOB0;\nendmodule\n\n(* blackbox *)\nmodule PDPW8KC (...);\n    parameter DATA_WIDTH_W = 18;\n    parameter DATA_WIDTH_R = 9;\n    parameter REGMODE = \"NOREG\";\n    parameter CSDECODE_W = \"0b000\";\n    parameter CSDECODE_R = \"0b000\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DI17;\n    input DI16;\n    input DI15;\n    input DI14;\n    input DI13;\n    input DI12;\n    input DI11;\n    input DI10;\n    input DI9;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input ADW8;\n    input ADW7;\n    input ADW6;\n    input ADW5;\n    input ADW4;\n    input ADW3;\n    input ADW2;\n    input ADW1;\n    input ADW0;\n    input BE1;\n    input BE0;\n    input CEW;\n    input CLKW;\n    input CSW2;\n    input CSW1;\n    input CSW0;\n    input ADR12;\n    input ADR11;\n    input ADR10;\n    input ADR9;\n    input ADR8;\n    input ADR7;\n    input ADR6;\n    input ADR5;\n    input ADR4;\n    input ADR3;\n    input ADR2;\n    input ADR1;\n    input ADR0;\n    input CER;\n    input OCER;\n    input CLKR;\n    input CSR2;\n    input CSR1;\n    input CSR0;\n    input RST;\n    output DO17;\n    output DO16;\n    output DO15;\n    output DO14;\n    output DO13;\n    output DO12;\n    output DO11;\n    output DO10;\n    output DO9;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule SP8KC (...);\n    parameter DATA_WIDTH = 9;\n    parameter REGMODE = \"NOREG\";\n    parameter CSDECODE = \"0b000\";\n    parameter WRITEMODE = \"NORMAL\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input AD12;\n    input AD11;\n    input AD10;\n    input AD9;\n    input AD8;\n    input AD7;\n    input AD6;\n    input AD5;\n    input AD4;\n    input AD3;\n    input AD2;\n    input AD1;\n    input AD0;\n    input CE;\n    input OCE;\n    input CLK;\n    input WE;\n    input CS2;\n    input CS1;\n    input CS0;\n    input RST;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule FIFO8KB (...);\n    parameter DATA_WIDTH_W = 18;\n    parameter DATA_WIDTH_R = 18;\n    parameter REGMODE = \"NOREG\";\n    parameter RESETMODE = \"ASYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter CSDECODE_W = \"0b00\";\n    parameter CSDECODE_R = \"0b00\";\n    parameter AEPOINTER = \"0b00000000000000\";\n    parameter AEPOINTER1 = \"0b00000000000000\";\n    parameter AFPOINTER = \"0b00000000000000\";\n    parameter AFPOINTER1 = \"0b00000000000000\";\n    parameter FULLPOINTER = \"0b00000000000000\";\n    parameter FULLPOINTER1 = \"0b00000000000000\";\n    parameter GSR = \"DISABLED\";\n    input DI0;\n    input DI1;\n    input DI2;\n    input DI3;\n    input DI4;\n    input DI5;\n    input DI6;\n    input DI7;\n    input DI8;\n    input DI9;\n    input DI10;\n    input DI11;\n    input DI12;\n    input DI13;\n    input DI14;\n    input DI15;\n    input DI16;\n    input DI17;\n    input CSW0;\n    input CSW1;\n    input CSR0;\n    input CSR1;\n    input WE;\n    input RE;\n    input ORE;\n    input CLKW;\n    input CLKR;\n    input RST;\n    input RPRST;\n    input FULLI;\n    input EMPTYI;\n    output DO0;\n    output DO1;\n    output DO2;\n    output DO3;\n    output DO4;\n    output DO5;\n    output DO6;\n    output DO7;\n    output DO8;\n    output DO9;\n    output DO10;\n    output DO11;\n    output DO12;\n    output DO13;\n    output DO14;\n    output DO15;\n    output DO16;\n    output DO17;\n    output EF;\n    output AEF;\n    output AFF;\n    output FF;\nendmodule\n\n(* blackbox *)\nmodule CLKDIVC (...);\n    parameter GSR = \"DISABLED\";\n    parameter DIV = \"2.0\";\n    input RST;\n    input CLKI;\n    input ALIGNWD;\n    output CDIV1;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule DCMA (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output DCMOUT;\nendmodule\n\n(* blackbox *)\nmodule ECLKSYNCA (...);\n    input ECLKI;\n    input STOP;\n    output ECLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKBRIDGECS (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output ECSOUT;\nendmodule\n\n(* blackbox *)\nmodule DCCA (...);\n    input CLKI;\n    input CE;\n    output CLKO;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule START (...);\n    input STARTCLK;\nendmodule\n\n(* blackbox *)\nmodule EHXPLLJ (...);\n    parameter CLKI_DIV = 1;\n    parameter CLKFB_DIV = 1;\n    parameter CLKOP_DIV = 8;\n    parameter CLKOS_DIV = 8;\n    parameter CLKOS2_DIV = 8;\n    parameter CLKOS3_DIV = 8;\n    parameter CLKOP_ENABLE = \"ENABLED\";\n    parameter CLKOS_ENABLE = \"ENABLED\";\n    parameter CLKOS2_ENABLE = \"ENABLED\";\n    parameter CLKOS3_ENABLE = \"ENABLED\";\n    parameter VCO_BYPASS_A0 = \"DISABLED\";\n    parameter VCO_BYPASS_B0 = \"DISABLED\";\n    parameter VCO_BYPASS_C0 = \"DISABLED\";\n    parameter VCO_BYPASS_D0 = \"DISABLED\";\n    parameter CLKOP_CPHASE = 0;\n    parameter CLKOS_CPHASE = 0;\n    parameter CLKOS2_CPHASE = 0;\n    parameter CLKOS3_CPHASE = 0;\n    parameter CLKOP_FPHASE = 0;\n    parameter CLKOS_FPHASE = 0;\n    parameter CLKOS2_FPHASE = 0;\n    parameter CLKOS3_FPHASE = 0;\n    parameter FEEDBK_PATH = \"CLKOP\";\n    parameter FRACN_ENABLE = \"DISABLED\";\n    parameter FRACN_DIV = 0;\n    parameter CLKOP_TRIM_POL = \"RISING\";\n    parameter CLKOP_TRIM_DELAY = 0;\n    parameter CLKOS_TRIM_POL = \"RISING\";\n    parameter CLKOS_TRIM_DELAY = 0;\n    parameter PLL_USE_WB = \"DISABLED\";\n    parameter PREDIVIDER_MUXA1 = 0;\n    parameter PREDIVIDER_MUXB1 = 0;\n    parameter PREDIVIDER_MUXC1 = 0;\n    parameter PREDIVIDER_MUXD1 = 0;\n    parameter OUTDIVIDER_MUXA2 = \"DIVA\";\n    parameter OUTDIVIDER_MUXB2 = \"DIVB\";\n    parameter OUTDIVIDER_MUXC2 = \"DIVC\";\n    parameter OUTDIVIDER_MUXD2 = \"DIVD\";\n    parameter PLL_LOCK_MODE = 0;\n    parameter STDBY_ENABLE = \"DISABLED\";\n    parameter DPHASE_SOURCE = \"DISABLED\";\n    parameter PLLRST_ENA = \"DISABLED\";\n    parameter MRST_ENA = \"DISABLED\";\n    parameter DCRST_ENA = \"DISABLED\";\n    parameter DDRST_ENA = \"DISABLED\";\n    parameter INTFB_WAKE = \"DISABLED\";\n    input CLKI;\n    input CLKFB;\n    input PHASESEL1;\n    input PHASESEL0;\n    input PHASEDIR;\n    input PHASESTEP;\n    input LOADREG;\n    input STDBY;\n    input PLLWAKESYNC;\n    input RST;\n    input RESETM;\n    input RESETC;\n    input RESETD;\n    input ENCLKOP;\n    input ENCLKOS;\n    input ENCLKOS2;\n    input ENCLKOS3;\n    input PLLCLK;\n    input PLLRST;\n    input PLLSTB;\n    input PLLWE;\n    input PLLDATI7;\n    input PLLDATI6;\n    input PLLDATI5;\n    input PLLDATI4;\n    input PLLDATI3;\n    input PLLDATI2;\n    input PLLDATI1;\n    input PLLDATI0;\n    input PLLADDR4;\n    input PLLADDR3;\n    input PLLADDR2;\n    input PLLADDR1;\n    input PLLADDR0;\n    output CLKOP;\n    output CLKOS;\n    output CLKOS2;\n    output CLKOS3;\n    output LOCK;\n    output INTLOCK;\n    output REFCLK;\n    output PLLDATO7;\n    output PLLDATO6;\n    output PLLDATO5;\n    output PLLDATO4;\n    output PLLDATO3;\n    output PLLDATO2;\n    output PLLDATO1;\n    output PLLDATO0;\n    output PLLACK;\n    output DPHSRC;\n    output CLKINTFB;\nendmodule\n\n(* blackbox *)\nmodule OSCH (...);\n    parameter NOM_FREQ = \"2.08\";\n    input STDBY;\n    output OSC;\n    output SEDSTDBY;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule TSALL (...);\n    input TSALL;\nendmodule\n\n",
             "cells_bb_xo3.v": "// Created by cells_xtra.py from Lattice models\n\n(* blackbox *) (* keep *)\nmodule GSR (...);\n    input GSR;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule SGSR (...);\n    input GSR;\n    input CLK;\nendmodule\n\n(* blackbox *)\nmodule DP8KC (...);\n    parameter DATA_WIDTH_A = 9;\n    parameter DATA_WIDTH_B = 9;\n    parameter REGMODE_A = \"NOREG\";\n    parameter REGMODE_B = \"NOREG\";\n    parameter CSDECODE_A = \"0b000\";\n    parameter CSDECODE_B = \"0b000\";\n    parameter WRITEMODE_A = \"NORMAL\";\n    parameter WRITEMODE_B = \"NORMAL\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DIA8;\n    input DIA7;\n    input DIA6;\n    input DIA5;\n    input DIA4;\n    input DIA3;\n    input DIA2;\n    input DIA1;\n    input DIA0;\n    input ADA12;\n    input ADA11;\n    input ADA10;\n    input ADA9;\n    input ADA8;\n    input ADA7;\n    input ADA6;\n    input ADA5;\n    input ADA4;\n    input ADA3;\n    input ADA2;\n    input ADA1;\n    input ADA0;\n    input CEA;\n    input OCEA;\n    input CLKA;\n    input WEA;\n    input CSA2;\n    input CSA1;\n    input CSA0;\n    input RSTA;\n    input DIB8;\n    input DIB7;\n    input DIB6;\n    input DIB5;\n    input DIB4;\n    input DIB3;\n    input DIB2;\n    input DIB1;\n    input DIB0;\n    input ADB12;\n    input ADB11;\n    input ADB10;\n    input ADB9;\n    input ADB8;\n    input ADB7;\n    input ADB6;\n    input ADB5;\n    input ADB4;\n    input ADB3;\n    input ADB2;\n    input ADB1;\n    input ADB0;\n    input CEB;\n    input OCEB;\n    input CLKB;\n    input WEB;\n    input CSB2;\n    input CSB1;\n    input CSB0;\n    input RSTB;\n    output DOA8;\n    output DOA7;\n    output DOA6;\n    output DOA5;\n    output DOA4;\n    output DOA3;\n    output DOA2;\n    output DOA1;\n    output DOA0;\n    output DOB8;\n    output DOB7;\n    output DOB6;\n    output DOB5;\n    output DOB4;\n    output DOB3;\n    output DOB2;\n    output DOB1;\n    output DOB0;\nendmodule\n\n(* blackbox *)\nmodule PDPW8KC (...);\n    parameter DATA_WIDTH_W = 18;\n    parameter DATA_WIDTH_R = 9;\n    parameter REGMODE = \"NOREG\";\n    parameter CSDECODE_W = \"0b000\";\n    parameter CSDECODE_R = \"0b000\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DI17;\n    input DI16;\n    input DI15;\n    input DI14;\n    input DI13;\n    input DI12;\n    input DI11;\n    input DI10;\n    input DI9;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input ADW8;\n    input ADW7;\n    input ADW6;\n    input ADW5;\n    input ADW4;\n    input ADW3;\n    input ADW2;\n    input ADW1;\n    input ADW0;\n    input BE1;\n    input BE0;\n    input CEW;\n    input CLKW;\n    input CSW2;\n    input CSW1;\n    input CSW0;\n    input ADR12;\n    input ADR11;\n    input ADR10;\n    input ADR9;\n    input ADR8;\n    input ADR7;\n    input ADR6;\n    input ADR5;\n    input ADR4;\n    input ADR3;\n    input ADR2;\n    input ADR1;\n    input ADR0;\n    input CER;\n    input OCER;\n    input CLKR;\n    input CSR2;\n    input CSR1;\n    input CSR0;\n    input RST;\n    output DO17;\n    output DO16;\n    output DO15;\n    output DO14;\n    output DO13;\n    output DO12;\n    output DO11;\n    output DO10;\n    output DO9;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule SP8KC (...);\n    parameter DATA_WIDTH = 9;\n    parameter REGMODE = \"NOREG\";\n    parameter CSDECODE = \"0b000\";\n    parameter WRITEMODE = \"NORMAL\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input AD12;\n    input AD11;\n    input AD10;\n    input AD9;\n    input AD8;\n    input AD7;\n    input AD6;\n    input AD5;\n    input AD4;\n    input AD3;\n    input AD2;\n    input AD1;\n    input AD0;\n    input CE;\n    input OCE;\n    input CLK;\n    input WE;\n    input CS2;\n    input CS1;\n    input CS0;\n    input RST;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule FIFO8KB (...);\n    parameter DATA_WIDTH_W = 18;\n    parameter DATA_WIDTH_R = 18;\n    parameter REGMODE = \"NOREG\";\n    parameter RESETMODE = \"ASYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter CSDECODE_W = \"0b00\";\n    parameter CSDECODE_R = \"0b00\";\n    parameter AEPOINTER = \"0b00000000000000\";\n    parameter AEPOINTER1 = \"0b00000000000000\";\n    parameter AFPOINTER = \"0b00000000000000\";\n    parameter AFPOINTER1 = \"0b00000000000000\";\n    parameter FULLPOINTER = \"0b00000000000000\";\n    parameter FULLPOINTER1 = \"0b00000000000000\";\n    parameter GSR = \"DISABLED\";\n    input DI0;\n    input DI1;\n    input DI2;\n    input DI3;\n    input DI4;\n    input DI5;\n    input DI6;\n    input DI7;\n    input DI8;\n    input DI9;\n    input DI10;\n    input DI11;\n    input DI12;\n    input DI13;\n    input DI14;\n    input DI15;\n    input DI16;\n    input DI17;\n    input CSW0;\n    input CSW1;\n    input CSR0;\n    input CSR1;\n    input WE;\n    input RE;\n    input ORE;\n    input CLKW;\n    input CLKR;\n    input RST;\n    input RPRST;\n    input FULLI;\n    input EMPTYI;\n    output DO0;\n    output DO1;\n    output DO2;\n    output DO3;\n    output DO4;\n    output DO5;\n    output DO6;\n    output DO7;\n    output DO8;\n    output DO9;\n    output DO10;\n    output DO11;\n    output DO12;\n    output DO13;\n    output DO14;\n    output DO15;\n    output DO16;\n    output DO17;\n    output EF;\n    output AEF;\n    output AFF;\n    output FF;\nendmodule\n\n(* blackbox *)\nmodule CLKDIVC (...);\n    parameter GSR = \"DISABLED\";\n    parameter DIV = \"2.0\";\n    input RST;\n    input CLKI;\n    input ALIGNWD;\n    output CDIV1;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule DCMA (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output DCMOUT;\nendmodule\n\n(* blackbox *)\nmodule ECLKSYNCA (...);\n    input ECLKI;\n    input STOP;\n    output ECLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKBRIDGECS (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output ECSOUT;\nendmodule\n\n(* blackbox *)\nmodule DCCA (...);\n    input CLKI;\n    input CE;\n    output CLKO;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule START (...);\n    input STARTCLK;\nendmodule\n\n(* blackbox *)\nmodule EHXPLLJ (...);\n    parameter CLKI_DIV = 1;\n    parameter CLKFB_DIV = 1;\n    parameter CLKOP_DIV = 8;\n    parameter CLKOS_DIV = 8;\n    parameter CLKOS2_DIV = 8;\n    parameter CLKOS3_DIV = 8;\n    parameter CLKOP_ENABLE = \"ENABLED\";\n    parameter CLKOS_ENABLE = \"ENABLED\";\n    parameter CLKOS2_ENABLE = \"ENABLED\";\n    parameter CLKOS3_ENABLE = \"ENABLED\";\n    parameter VCO_BYPASS_A0 = \"DISABLED\";\n    parameter VCO_BYPASS_B0 = \"DISABLED\";\n    parameter VCO_BYPASS_C0 = \"DISABLED\";\n    parameter VCO_BYPASS_D0 = \"DISABLED\";\n    parameter CLKOP_CPHASE = 0;\n    parameter CLKOS_CPHASE = 0;\n    parameter CLKOS2_CPHASE = 0;\n    parameter CLKOS3_CPHASE = 0;\n    parameter CLKOP_FPHASE = 0;\n    parameter CLKOS_FPHASE = 0;\n    parameter CLKOS2_FPHASE = 0;\n    parameter CLKOS3_FPHASE = 0;\n    parameter FEEDBK_PATH = \"CLKOP\";\n    parameter FRACN_ENABLE = \"DISABLED\";\n    parameter FRACN_DIV = 0;\n    parameter CLKOP_TRIM_POL = \"RISING\";\n    parameter CLKOP_TRIM_DELAY = 0;\n    parameter CLKOS_TRIM_POL = \"RISING\";\n    parameter CLKOS_TRIM_DELAY = 0;\n    parameter PLL_USE_WB = \"DISABLED\";\n    parameter PREDIVIDER_MUXA1 = 0;\n    parameter PREDIVIDER_MUXB1 = 0;\n    parameter PREDIVIDER_MUXC1 = 0;\n    parameter PREDIVIDER_MUXD1 = 0;\n    parameter OUTDIVIDER_MUXA2 = \"DIVA\";\n    parameter OUTDIVIDER_MUXB2 = \"DIVB\";\n    parameter OUTDIVIDER_MUXC2 = \"DIVC\";\n    parameter OUTDIVIDER_MUXD2 = \"DIVD\";\n    parameter PLL_LOCK_MODE = 0;\n    parameter STDBY_ENABLE = \"DISABLED\";\n    parameter DPHASE_SOURCE = \"DISABLED\";\n    parameter PLLRST_ENA = \"DISABLED\";\n    parameter MRST_ENA = \"DISABLED\";\n    parameter DCRST_ENA = \"DISABLED\";\n    parameter DDRST_ENA = \"DISABLED\";\n    parameter INTFB_WAKE = \"DISABLED\";\n    input CLKI;\n    input CLKFB;\n    input PHASESEL1;\n    input PHASESEL0;\n    input PHASEDIR;\n    input PHASESTEP;\n    input LOADREG;\n    input STDBY;\n    input PLLWAKESYNC;\n    input RST;\n    input RESETM;\n    input RESETC;\n    input RESETD;\n    input ENCLKOP;\n    input ENCLKOS;\n    input ENCLKOS2;\n    input ENCLKOS3;\n    input PLLCLK;\n    input PLLRST;\n    input PLLSTB;\n    input PLLWE;\n    input PLLDATI7;\n    input PLLDATI6;\n    input PLLDATI5;\n    input PLLDATI4;\n    input PLLDATI3;\n    input PLLDATI2;\n    input PLLDATI1;\n    input PLLDATI0;\n    input PLLADDR4;\n    input PLLADDR3;\n    input PLLADDR2;\n    input PLLADDR1;\n    input PLLADDR0;\n    output CLKOP;\n    output CLKOS;\n    output CLKOS2;\n    output CLKOS3;\n    output LOCK;\n    output INTLOCK;\n    output REFCLK;\n    output PLLDATO7;\n    output PLLDATO6;\n    output PLLDATO5;\n    output PLLDATO4;\n    output PLLDATO3;\n    output PLLDATO2;\n    output PLLDATO1;\n    output PLLDATO0;\n    output PLLACK;\n    output DPHSRC;\n    output CLKINTFB;\nendmodule\n\n(* blackbox *)\nmodule OSCH (...);\n    parameter NOM_FREQ = \"2.08\";\n    input STDBY;\n    output OSC;\n    output SEDSTDBY;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule TSALL (...);\n    input TSALL;\nendmodule\n\n",
             "cells_bb_xo3d.v": "// Created by cells_xtra.py from Lattice models\n\n(* blackbox *) (* keep *)\nmodule GSR (...);\n    input GSR;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule SGSR (...);\n    input GSR;\n    input CLK;\nendmodule\n\n(* blackbox *)\nmodule DP8KC (...);\n    parameter DATA_WIDTH_A = 9;\n    parameter DATA_WIDTH_B = 9;\n    parameter REGMODE_A = \"NOREG\";\n    parameter REGMODE_B = \"NOREG\";\n    parameter CSDECODE_A = \"0b000\";\n    parameter CSDECODE_B = \"0b000\";\n    parameter WRITEMODE_A = \"NORMAL\";\n    parameter WRITEMODE_B = \"NORMAL\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DIA8;\n    input DIA7;\n    input DIA6;\n    input DIA5;\n    input DIA4;\n    input DIA3;\n    input DIA2;\n    input DIA1;\n    input DIA0;\n    input ADA12;\n    input ADA11;\n    input ADA10;\n    input ADA9;\n    input ADA8;\n    input ADA7;\n    input ADA6;\n    input ADA5;\n    input ADA4;\n    input ADA3;\n    input ADA2;\n    input ADA1;\n    input ADA0;\n    input CEA;\n    input OCEA;\n    input CLKA;\n    input WEA;\n    input CSA2;\n    input CSA1;\n    input CSA0;\n    input RSTA;\n    input DIB8;\n    input DIB7;\n    input DIB6;\n    input DIB5;\n    input DIB4;\n    input DIB3;\n    input DIB2;\n    input DIB1;\n    input DIB0;\n    input ADB12;\n    input ADB11;\n    input ADB10;\n    input ADB9;\n    input ADB8;\n    input ADB7;\n    input ADB6;\n    input ADB5;\n    input ADB4;\n    input ADB3;\n    input ADB2;\n    input ADB1;\n    input ADB0;\n    input CEB;\n    input OCEB;\n    input CLKB;\n    input WEB;\n    input CSB2;\n    input CSB1;\n    input CSB0;\n    input RSTB;\n    output DOA8;\n    output DOA7;\n    output DOA6;\n    output DOA5;\n    output DOA4;\n    output DOA3;\n    output DOA2;\n    output DOA1;\n    output DOA0;\n    output DOB8;\n    output DOB7;\n    output DOB6;\n    output DOB5;\n    output DOB4;\n    output DOB3;\n    output DOB2;\n    output DOB1;\n    output DOB0;\nendmodule\n\n(* blackbox *)\nmodule PDPW8KC (...);\n    parameter DATA_WIDTH_W = 18;\n    parameter DATA_WIDTH_R = 9;\n    parameter REGMODE = \"NOREG\";\n    parameter CSDECODE_W = \"0b000\";\n    parameter CSDECODE_R = \"0b000\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DI17;\n    input DI16;\n    input DI15;\n    input DI14;\n    input DI13;\n    input DI12;\n    input DI11;\n    input DI10;\n    input DI9;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input ADW8;\n    input ADW7;\n    input ADW6;\n    input ADW5;\n    input ADW4;\n    input ADW3;\n    input ADW2;\n    input ADW1;\n    input ADW0;\n    input BE1;\n    input BE0;\n    input CEW;\n    input CLKW;\n    input CSW2;\n    input CSW1;\n    input CSW0;\n    input ADR12;\n    input ADR11;\n    input ADR10;\n    input ADR9;\n    input ADR8;\n    input ADR7;\n    input ADR6;\n    input ADR5;\n    input ADR4;\n    input ADR3;\n    input ADR2;\n    input ADR1;\n    input ADR0;\n    input CER;\n    input OCER;\n    input CLKR;\n    input CSR2;\n    input CSR1;\n    input CSR0;\n    input RST;\n    output DO17;\n    output DO16;\n    output DO15;\n    output DO14;\n    output DO13;\n    output DO12;\n    output DO11;\n    output DO10;\n    output DO9;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule SP8KC (...);\n    parameter DATA_WIDTH = 9;\n    parameter REGMODE = \"NOREG\";\n    parameter CSDECODE = \"0b000\";\n    parameter WRITEMODE = \"NORMAL\";\n    parameter GSR = \"ENABLED\";\n    parameter RESETMODE = \"SYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter INIT_DATA = \"STATIC\";\n    parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n    input DI8;\n    input DI7;\n    input DI6;\n    input DI5;\n    input DI4;\n    input DI3;\n    input DI2;\n    input DI1;\n    input DI0;\n    input AD12;\n    input AD11;\n    input AD10;\n    input AD9;\n    input AD8;\n    input AD7;\n    input AD6;\n    input AD5;\n    input AD4;\n    input AD3;\n    input AD2;\n    input AD1;\n    input AD0;\n    input CE;\n    input OCE;\n    input CLK;\n    input WE;\n    input CS2;\n    input CS1;\n    input CS0;\n    input RST;\n    output DO8;\n    output DO7;\n    output DO6;\n    output DO5;\n    output DO4;\n    output DO3;\n    output DO2;\n    output DO1;\n    output DO0;\nendmodule\n\n(* blackbox *)\nmodule FIFO8KB (...);\n    parameter DATA_WIDTH_W = 18;\n    parameter DATA_WIDTH_R = 18;\n    parameter REGMODE = \"NOREG\";\n    parameter RESETMODE = \"ASYNC\";\n    parameter ASYNC_RESET_RELEASE = \"SYNC\";\n    parameter CSDECODE_W = \"0b00\";\n    parameter CSDECODE_R = \"0b00\";\n    parameter AEPOINTER = \"0b00000000000000\";\n    parameter AEPOINTER1 = \"0b00000000000000\";\n    parameter AFPOINTER = \"0b00000000000000\";\n    parameter AFPOINTER1 = \"0b00000000000000\";\n    parameter FULLPOINTER = \"0b00000000000000\";\n    parameter FULLPOINTER1 = \"0b00000000000000\";\n    parameter GSR = \"DISABLED\";\n    input DI0;\n    input DI1;\n    input DI2;\n    input DI3;\n    input DI4;\n    input DI5;\n    input DI6;\n    input DI7;\n    input DI8;\n    input DI9;\n    input DI10;\n    input DI11;\n    input DI12;\n    input DI13;\n    input DI14;\n    input DI15;\n    input DI16;\n    input DI17;\n    input CSW0;\n    input CSW1;\n    input CSR0;\n    input CSR1;\n    input WE;\n    input RE;\n    input ORE;\n    input CLKW;\n    input CLKR;\n    input RST;\n    input RPRST;\n    input FULLI;\n    input EMPTYI;\n    output DO0;\n    output DO1;\n    output DO2;\n    output DO3;\n    output DO4;\n    output DO5;\n    output DO6;\n    output DO7;\n    output DO8;\n    output DO9;\n    output DO10;\n    output DO11;\n    output DO12;\n    output DO13;\n    output DO14;\n    output DO15;\n    output DO16;\n    output DO17;\n    output EF;\n    output AEF;\n    output AFF;\n    output FF;\nendmodule\n\n(* blackbox *)\nmodule CLKDIVC (...);\n    parameter GSR = \"DISABLED\";\n    parameter DIV = \"2.0\";\n    input RST;\n    input CLKI;\n    input ALIGNWD;\n    output CDIV1;\n    output CDIVX;\nendmodule\n\n(* blackbox *)\nmodule DCMA (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output DCMOUT;\nendmodule\n\n(* blackbox *)\nmodule ECLKSYNCA (...);\n    input ECLKI;\n    input STOP;\n    output ECLKO;\nendmodule\n\n(* blackbox *)\nmodule ECLKBRIDGECS (...);\n    input CLK0;\n    input CLK1;\n    input SEL;\n    output ECSOUT;\nendmodule\n\n(* blackbox *)\nmodule DCCA (...);\n    input CLKI;\n    input CE;\n    output CLKO;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule START (...);\n    input STARTCLK;\nendmodule\n\n(* blackbox *)\nmodule EHXPLLJ (...);\n    parameter CLKI_DIV = 1;\n    parameter CLKFB_DIV = 1;\n    parameter CLKOP_DIV = 8;\n    parameter CLKOS_DIV = 8;\n    parameter CLKOS2_DIV = 8;\n    parameter CLKOS3_DIV = 8;\n    parameter CLKOP_ENABLE = \"ENABLED\";\n    parameter CLKOS_ENABLE = \"ENABLED\";\n    parameter CLKOS2_ENABLE = \"ENABLED\";\n    parameter CLKOS3_ENABLE = \"ENABLED\";\n    parameter VCO_BYPASS_A0 = \"DISABLED\";\n    parameter VCO_BYPASS_B0 = \"DISABLED\";\n    parameter VCO_BYPASS_C0 = \"DISABLED\";\n    parameter VCO_BYPASS_D0 = \"DISABLED\";\n    parameter CLKOP_CPHASE = 0;\n    parameter CLKOS_CPHASE = 0;\n    parameter CLKOS2_CPHASE = 0;\n    parameter CLKOS3_CPHASE = 0;\n    parameter CLKOP_FPHASE = 0;\n    parameter CLKOS_FPHASE = 0;\n    parameter CLKOS2_FPHASE = 0;\n    parameter CLKOS3_FPHASE = 0;\n    parameter FEEDBK_PATH = \"CLKOP\";\n    parameter FRACN_ENABLE = \"DISABLED\";\n    parameter FRACN_DIV = 0;\n    parameter CLKOP_TRIM_POL = \"RISING\";\n    parameter CLKOP_TRIM_DELAY = 0;\n    parameter CLKOS_TRIM_POL = \"RISING\";\n    parameter CLKOS_TRIM_DELAY = 0;\n    parameter PLL_USE_WB = \"DISABLED\";\n    parameter PREDIVIDER_MUXA1 = 0;\n    parameter PREDIVIDER_MUXB1 = 0;\n    parameter PREDIVIDER_MUXC1 = 0;\n    parameter PREDIVIDER_MUXD1 = 0;\n    parameter OUTDIVIDER_MUXA2 = \"DIVA\";\n    parameter OUTDIVIDER_MUXB2 = \"DIVB\";\n    parameter OUTDIVIDER_MUXC2 = \"DIVC\";\n    parameter OUTDIVIDER_MUXD2 = \"DIVD\";\n    parameter PLL_LOCK_MODE = 0;\n    parameter STDBY_ENABLE = \"DISABLED\";\n    parameter DPHASE_SOURCE = \"DISABLED\";\n    parameter PLLRST_ENA = \"DISABLED\";\n    parameter MRST_ENA = \"DISABLED\";\n    parameter DCRST_ENA = \"DISABLED\";\n    parameter DDRST_ENA = \"DISABLED\";\n    parameter INTFB_WAKE = \"DISABLED\";\n    input CLKI;\n    input CLKFB;\n    input PHASESEL1;\n    input PHASESEL0;\n    input PHASEDIR;\n    input PHASESTEP;\n    input LOADREG;\n    input STDBY;\n    input PLLWAKESYNC;\n    input RST;\n    input RESETM;\n    input RESETC;\n    input RESETD;\n    input ENCLKOP;\n    input ENCLKOS;\n    input ENCLKOS2;\n    input ENCLKOS3;\n    input PLLCLK;\n    input PLLRST;\n    input PLLSTB;\n    input PLLWE;\n    input PLLDATI7;\n    input PLLDATI6;\n    input PLLDATI5;\n    input PLLDATI4;\n    input PLLDATI3;\n    input PLLDATI2;\n    input PLLDATI1;\n    input PLLDATI0;\n    input PLLADDR4;\n    input PLLADDR3;\n    input PLLADDR2;\n    input PLLADDR1;\n    input PLLADDR0;\n    output CLKOP;\n    output CLKOS;\n    output CLKOS2;\n    output CLKOS3;\n    output LOCK;\n    output INTLOCK;\n    output REFCLK;\n    output PLLDATO7;\n    output PLLDATO6;\n    output PLLDATO5;\n    output PLLDATO4;\n    output PLLDATO3;\n    output PLLDATO2;\n    output PLLDATO1;\n    output PLLDATO0;\n    output PLLACK;\n    output DPHSRC;\n    output CLKINTFB;\nendmodule\n\n(* blackbox *)\nmodule OSCJ (...);\n    parameter NOM_FREQ = \"2.08\";\n    input STDBY;\n    output OSC;\n    output SEDSTDBY;\n    output OSCESB;\nendmodule\n\n(* blackbox *) (* keep *)\nmodule TSALL (...);\n    input TSALL;\nendmodule\n\n",
             "cells_ff.vh": "// Diamond flip-flops\nmodule FD1P3AX(input     D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3AY(input     D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1S3AX(input     D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3AY(input     D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3BX(input PD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3DX(input CD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3IX(input CD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule\nmodule FD1S3JX(input PD, D,     CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"),  .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule\n\n// TODO: Diamond latches\n// module FL1P3AY(); endmodule\n// module FL1P3AZ(); endmodule\n// module FL1P3BX(); endmodule\n// module FL1P3DX(); endmodule\n// module FL1P3IY(); endmodule\n// module FL1P3JY(); endmodule\n// module FL1S3AX(); endmodule\n// module FL1S3AY(); endmodule\n\n// Diamond I/O registers\nmodule IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\n\nmodule OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"),   .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\n\n// TODO: Diamond I/O latches\n// module IFS1S1B(input PD, D, SCLK, output Q); endmodule\n// module IFS1S1D(input CD, D, SCLK, output Q); endmodule\n// module IFS1S1I(input PD, D, SCLK, output Q); endmodule\n// module IFS1S1J(input CD, D, SCLK, output Q); endmodule\n",
             "cells_io.vh": "// Diamond I/O buffers\nmodule IB   ((* iopad_external_pin *) input I,     output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule IBPU ((* iopad_external_pin *) input I,     output O); (* PULLMODE=\"UP\"   *) TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule IBPD ((* iopad_external_pin *) input I,     output O); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule OB   (input I,     (* iopad_external_pin *) output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule\nmodule OBZ  (input I, T,  (* iopad_external_pin *) output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBZPU(input I, T,  (* iopad_external_pin *) output O); (* PULLMODE=\"UP\"   *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBZPD(input I, T,  (* iopad_external_pin *) output O); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule\nmodule BB   (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule BBPU (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"UP\"   *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule BBPD (input I, T,  output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule ILVDS(input A, AN, (* iopad_external_pin *) output Z    ); TRELLIS_IO #(.DIR(\"INPUT\"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule\nmodule OLVDS(input A,     (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule\n",
-            "cells_map.v": "module  \\$_DFF_N_ (input D, C, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFF_P_ (input D, C, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_NN_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_PN_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_NP_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\nmodule \\$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n    parameter WIDTH = 0;\n    parameter LUT = 0;\n\n    (* force_downto *)\n    input [WIDTH-1:0] A;\n    output Y;\n\n    generate\n        if (WIDTH == 1) begin\n            localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));\n        end else\n        if (WIDTH == 2) begin\n            localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));\n        end else\n        if (WIDTH == 3) begin\n            localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));\n        end else\n        if (WIDTH == 4) begin\n            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n        `ifndef NO_PFUMUX\n        end else\n        if (WIDTH == 5) begin\n            wire f0, f1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));\n        end else\n        if (WIDTH == 6) begin\n            wire f0, f1, f2, f3, g0, g1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));\n        end else\n        if (WIDTH == 7) begin\n            wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));\n            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));\n            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));\n            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));\n            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));\n        `endif\n        end else begin\n            wire _TECHMAP_FAIL_ = 1;\n        end\n    endgenerate\nendmodule\n`endif\n",
-            "cells_sim_ecp5.v": "`include \"common_sim.vh\"\n`include \"ccu2c_sim.vh\"\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
+            "cells_map_nexus.v": "// Flipflop intermediate map level\nmodule \\$__FF_NOLSR (input D, C, E, output Q);\n\tparameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n\twire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n\tgenerate\n\t\tif (_TECHMAP_WIREINIT_Q_ === 1'b1)\n\t\t\tFD1P3JX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(1'b0), .Q(Q));\n\t\telse\n\t\t\tFD1P3IX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(1'b0), .Q(Q));\n\tendgenerate\nendmodule\n\nmodule \\$__FF_SYNCLSR (input D, C, E, R, output Q);\n\tparameter SR_VAL = 1'b0;\n\tparameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n\twire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n\twire Ci, Ei, Ri, Rg, Dd;\n\tgenerate\n\t\tif (SR_VAL)\n\t\t\tFD1P3JX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));\n\t\telse\n\t\t\tFD1P3IX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));\n\tendgenerate\nendmodule\n\nmodule \\$__FF_ASYNCLSR (input D, C, E, R, output Q);\n\tparameter SR_VAL = 1'b0;\n\tparameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n\twire _TECHMAP_REMOVEINIT_Q_ = (_TECHMAP_WIREINIT_Q_ === 1'bx || _TECHMAP_WIREINIT_Q_ === SR_VAL);\n\twire Ci, Ei, Ri, Rg, Dd;\n\tgenerate\n\t\tif (SR_VAL)\n\t\t\tFD1P3BX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));\n\t\telse\n\t\t\tFD1P3DX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));\n\tendgenerate\nendmodule\n\n\nmodule  \\$_DFF_P_ (input D, C, output Q); \\$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(1'b1), .Q(Q)); endmodule\n\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q); \\$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(E), .Q(Q)); endmodule\n\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); \\$__FF_ASYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); \\$__FF_ASYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\n\nmodule  \\$_SDFF_PP0_ (input D, C, R, output Q); \\$__FF_SYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\nmodule  \\$_SDFF_PP1_ (input D, C, R, output Q); \\$__FF_SYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\n\nmodule  \\$_DFFE_PP0P_ (input D, C, E, R, output Q); \\$__FF_ASYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\nmodule  \\$_DFFE_PP1P_ (input D, C, E, R, output Q); \\$__FF_ASYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\n\nmodule  \\$_SDFFE_PP0P_ (input D, C, E, R, output Q); \\$__FF_SYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\nmodule  \\$_SDFFE_PP1P_ (input D, C, E, R, output Q); \\$__FF_SYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\t\tif (LUT == 2'b01)\n\t\t\t\tINV _TECHMAP_REPLACE_ (.A(A[0]), .Z(Y));\n\t\t\telse\n\t\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\", {{8{LUT[1]}}, {8{LUT[0]}}}))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t\t.D(A[0]));\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tlocalparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};\n\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\",  INIT))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t.C(A[0]), .D(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tlocalparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};\n\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\", INIT))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t.B(A[0]), .C(A[1]), .D(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\", LUT))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\t\tend else\n\t\tif (WIDTH == 5) begin\n\t\t\tWIDEFN9 #(\n\t\t\t\t.INIT0($sformatf(\"0x%04x\", LUT[15:0 ])),\n\t\t\t\t.INIT1($sformatf(\"0x%04x\", LUT[31:16])),\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.A0(A[0]), .B0(A[1]), .C0(A[2]), .D0(A[3]),\n\t\t\t\t.A1(A[0]), .B1(A[1]), .C1(A[2]), .D1(A[3]),\n\t\t\t\t.SEL(A[4]), .Z(Y)\n\t\t\t);\n\t\tend\n\tendgenerate\nendmodule\n`endif\n",
+            "cells_map_trellis.v": "module  \\$_DFF_N_ (input D, C, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFF_P_ (input D, C, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_NN_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_PN_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_NP_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q);\n    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n    generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    else\n        TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n    endgenerate\n    wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule  \\$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule  \\$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule  \\$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\nmodule \\$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n    parameter WIDTH = 0;\n    parameter LUT = 0;\n\n    (* force_downto *)\n    input [WIDTH-1:0] A;\n    output Y;\n\n    generate\n        if (WIDTH == 1) begin\n            localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));\n        end else\n        if (WIDTH == 2) begin\n            localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));\n        end else\n        if (WIDTH == 3) begin\n            localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};\n            LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));\n        end else\n        if (WIDTH == 4) begin\n            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n        `ifndef NO_PFUMUX\n        end else\n        if (WIDTH == 5) begin\n            wire f0, f1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));\n        end else\n        if (WIDTH == 6) begin\n            wire f0, f1, f2, f3, g0, g1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));\n        end else\n        if (WIDTH == 7) begin\n            wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;\n            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n            LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),\n                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));\n            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));\n            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));\n            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));\n            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));\n        `endif\n        end else begin\n            wire _TECHMAP_FAIL_ = 1;\n        end\n    endgenerate\nendmodule\n`endif\n",
+            "cells_sim_ecp5.v": "`include \"common_sim.vh\"\n`include \"ccu2c_sim.vh\"\n\n(* blackbox *)\nmodule DP16KD(\n  input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,\n  input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,\n  input CEA, OCEA, CLKA, WEA, RSTA,\n  input CSA2, CSA1, CSA0,\n  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,\n\n  input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,\n  input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,\n  input CEB, OCEB, CLKB, WEB, RSTB,\n  input CSB2, CSB1, CSB0,\n  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0\n);\n\tparameter DATA_WIDTH_A = 18;\n\tparameter DATA_WIDTH_B = 18;\n\n\tparameter REGMODE_A = \"NOREG\";\n\tparameter REGMODE_B = \"NOREG\";\n\n\tparameter RESETMODE = \"SYNC\";\n\tparameter ASYNC_RESET_RELEASE = \"SYNC\";\n\n\tparameter CSDECODE_A = \"0b000\";\n\tparameter CSDECODE_B = \"0b000\";\n\n\tparameter WRITEMODE_A = \"NORMAL\";\n\tparameter WRITEMODE_B = \"NORMAL\";\n\n\tparameter DIA17MUX = \"DIA17\";\n\tparameter DIA16MUX = \"DIA16\";\n\tparameter DIA15MUX = \"DIA15\";\n\tparameter DIA14MUX = \"DIA14\";\n\tparameter DIA13MUX = \"DIA13\";\n\tparameter DIA12MUX = \"DIA12\";\n\tparameter DIA11MUX = \"DIA11\";\n\tparameter DIA10MUX = \"DIA10\";\n\tparameter DIA9MUX = \"DIA9\";\n\tparameter DIA8MUX = \"DIA8\";\n\tparameter DIA7MUX = \"DIA7\";\n\tparameter DIA6MUX = \"DIA6\";\n\tparameter DIA5MUX = \"DIA5\";\n\tparameter DIA4MUX = \"DIA4\";\n\tparameter DIA3MUX = \"DIA3\";\n\tparameter DIA2MUX = \"DIA2\";\n\tparameter DIA1MUX = \"DIA1\";\n\tparameter DIA0MUX = \"DIA0\";\n\tparameter ADA13MUX = \"ADA13\";\n\tparameter ADA12MUX = \"ADA12\";\n\tparameter ADA11MUX = \"ADA11\";\n\tparameter ADA10MUX = \"ADA10\";\n\tparameter ADA9MUX = \"ADA9\";\n\tparameter ADA8MUX = \"ADA8\";\n\tparameter ADA7MUX = \"ADA7\";\n\tparameter ADA6MUX = \"ADA6\";\n\tparameter ADA5MUX = \"ADA5\";\n\tparameter ADA4MUX = \"ADA4\";\n\tparameter ADA3MUX = \"ADA3\";\n\tparameter ADA2MUX = \"ADA2\";\n\tparameter ADA1MUX = \"ADA1\";\n\tparameter ADA0MUX = \"ADA0\";\n\tparameter CEAMUX = \"CEA\";\n\tparameter OCEAMUX = \"OCEA\";\n\tparameter CLKAMUX = \"CLKA\";\n\tparameter WEAMUX = \"WEA\";\n\tparameter RSTAMUX = \"RSTA\";\n\tparameter CSA2MUX = \"CSA2\";\n\tparameter CSA1MUX = \"CSA1\";\n\tparameter CSA0MUX = \"CSA0\";\n\tparameter DOA17MUX = \"DOA17\";\n\tparameter DOA16MUX = \"DOA16\";\n\tparameter DOA15MUX = \"DOA15\";\n\tparameter DOA14MUX = \"DOA14\";\n\tparameter DOA13MUX = \"DOA13\";\n\tparameter DOA12MUX = \"DOA12\";\n\tparameter DOA11MUX = \"DOA11\";\n\tparameter DOA10MUX = \"DOA10\";\n\tparameter DOA9MUX = \"DOA9\";\n\tparameter DOA8MUX = \"DOA8\";\n\tparameter DOA7MUX = \"DOA7\";\n\tparameter DOA6MUX = \"DOA6\";\n\tparameter DOA5MUX = \"DOA5\";\n\tparameter DOA4MUX = \"DOA4\";\n\tparameter DOA3MUX = \"DOA3\";\n\tparameter DOA2MUX = \"DOA2\";\n\tparameter DOA1MUX = \"DOA1\";\n\tparameter DOA0MUX = \"DOA0\";\n\tparameter DIB17MUX = \"DIB17\";\n\tparameter DIB16MUX = \"DIB16\";\n\tparameter DIB15MUX = \"DIB15\";\n\tparameter DIB14MUX = \"DIB14\";\n\tparameter DIB13MUX = \"DIB13\";\n\tparameter DIB12MUX = \"DIB12\";\n\tparameter DIB11MUX = \"DIB11\";\n\tparameter DIB10MUX = \"DIB10\";\n\tparameter DIB9MUX = \"DIB9\";\n\tparameter DIB8MUX = \"DIB8\";\n\tparameter DIB7MUX = \"DIB7\";\n\tparameter DIB6MUX = \"DIB6\";\n\tparameter DIB5MUX = \"DIB5\";\n\tparameter DIB4MUX = \"DIB4\";\n\tparameter DIB3MUX = \"DIB3\";\n\tparameter DIB2MUX = \"DIB2\";\n\tparameter DIB1MUX = \"DIB1\";\n\tparameter DIB0MUX = \"DIB0\";\n\tparameter ADB13MUX = \"ADB13\";\n\tparameter ADB12MUX = \"ADB12\";\n\tparameter ADB11MUX = \"ADB11\";\n\tparameter ADB10MUX = \"ADB10\";\n\tparameter ADB9MUX = \"ADB9\";\n\tparameter ADB8MUX = \"ADB8\";\n\tparameter ADB7MUX = \"ADB7\";\n\tparameter ADB6MUX = \"ADB6\";\n\tparameter ADB5MUX = \"ADB5\";\n\tparameter ADB4MUX = \"ADB4\";\n\tparameter ADB3MUX = \"ADB3\";\n\tparameter ADB2MUX = \"ADB2\";\n\tparameter ADB1MUX = \"ADB1\";\n\tparameter ADB0MUX = \"ADB0\";\n\tparameter CEBMUX = \"CEB\";\n\tparameter OCEBMUX = \"OCEB\";\n\tparameter CLKBMUX = \"CLKB\";\n\tparameter WEBMUX = \"WEB\";\n\tparameter RSTBMUX = \"RSTB\";\n\tparameter CSB2MUX = \"CSB2\";\n\tparameter CSB1MUX = \"CSB1\";\n\tparameter CSB0MUX = \"CSB0\";\n\tparameter DOB17MUX = \"DOB17\";\n\tparameter DOB16MUX = \"DOB16\";\n\tparameter DOB15MUX = \"DOB15\";\n\tparameter DOB14MUX = \"DOB14\";\n\tparameter DOB13MUX = \"DOB13\";\n\tparameter DOB12MUX = \"DOB12\";\n\tparameter DOB11MUX = \"DOB11\";\n\tparameter DOB10MUX = \"DOB10\";\n\tparameter DOB9MUX = \"DOB9\";\n\tparameter DOB8MUX = \"DOB8\";\n\tparameter DOB7MUX = \"DOB7\";\n\tparameter DOB6MUX = \"DOB6\";\n\tparameter DOB5MUX = \"DOB5\";\n\tparameter DOB4MUX = \"DOB4\";\n\tparameter DOB3MUX = \"DOB3\";\n\tparameter DOB2MUX = \"DOB2\";\n\tparameter DOB1MUX = \"DOB1\";\n\tparameter DOB0MUX = \"DOB0\";\n\n\tparameter WID = 0;\n\n\tparameter GSR = \"ENABLED\";\n\n\tparameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_DATA = \"STATIC\";\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
+            "cells_sim_nexus.v": "(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n\tparameter INIT = \"0x0000\";\n`include \"parse_init.vh\"\n\tlocalparam initp = parse_init(INIT);\n\twire [7:0] s3 = D ?     initp[15:8] :    initp[7:0];\n\twire [3:0] s2 = C ?       s3[ 7:4]  :       s3[3:0];\n\twire [1:0] s1 = B ?       s2[ 3:2]  :       s2[1:0];\n\tassign Z =      A ?          s1[1]  :         s1[0];\n\n\t// Per-input delay differences are considered 'interconnect'\n\t// so not known yet\n\tspecify\n\t\t(A => Z) = 233;\n\t\t(B => Z) = 233;\n\t\t(C => Z) = 233;\n\t\t(D => Z) = 233;\n\tendspecify\n\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   cost of 5-input LUTs and is not intended to be instantiated\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input SEL, D, C, B, A, output Z);\n\tspecify\n\t\t(SEL => Z) = 171;\n\t\t(D => Z) = 303;\n\t\t(C => Z) = 311;\n\t\t(B => Z) = 309;\n\t\t(A => Z) = 306;\n\tendspecify\nendmodule\n\n// Two LUT4s and MUX2\nmodule WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);\n\tparameter INIT0 = \"0x0000\";\n\tparameter INIT1 = \"0x0000\";\n\twire z0, z1;\n\tLUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));\n\tLUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));\n\tassign Z = SEL ? z1 : z0;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule INV(input A, output Z);\n\tassign Z = !A;\n\n\tspecify\n\t\t(A => Z) = 10;\n\tendspecify\nendmodule\n\n// Bidirectional IO buffer\nmodule BB(input T, I, output O,\n\t(* iopad_external_pin *) inout B);\n\tassign B = T ? 1'bz : I;\n\tassign O = B;\nendmodule\n\n// Input buffer\nmodule IB(\n\t(* iopad_external_pin *) input I,\n\toutput O);\n\tassign O = I;\nendmodule\n\n// Output buffer\nmodule OB(input I,\n\t(* iopad_external_pin *) output O);\n\tassign O = I;\nendmodule\n\n// Output buffer with tristate\nmodule OBZ(input I, T,\n\t(* iopad_external_pin *) output O);\n\tassign O = T ? 1'bz : I;\nendmodule\n\n// Constants\nmodule VLO(output Z);\n\tassign Z = 1'b0;\nendmodule\n\nmodule VHI(output Z);\n\tassign Z = 1'b1;\nendmodule\n\n// Vendor flipflops\n// (all have active high clock, enable and set/reset - use INV to invert)\n\n// Async preset\n(* abc9_box, lib_whitebox *)\nmodule FD1P3BX(input D, CK, SP, PD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b1;\n\talways @(posedge CK or posedge PD)\n\t\tif (PD)\n\t\t\tQ <= 1'b1;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(PD, posedge CK, 224);\n`ifndef YOSYS\n\t\tif (PD) (posedge CLK => (Q : 1)) = 0;\n`else\n\t\tif (PD) (PD => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!PD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// Async clear\n(* abc9_box, lib_whitebox *)\nmodule FD1P3DX(input D, CK, SP, CD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b0;\n\talways @(posedge CK or posedge CD)\n\t\tif (CD)\n\t\t\tQ <= 1'b0;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(CD, posedge CK, 224);\n`ifndef YOSYS\n\t\tif (CD) (posedge CLK => (Q : 0)) = 0;\n`else\n\t\tif (CD) (CD => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!CD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// Sync clear\n(* abc9_flop, lib_whitebox *)\nmodule FD1P3IX(input D, CK, SP, CD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b0;\n\talways @(posedge CK)\n\t\tif (CD)\n\t\t\tQ <= 1'b0;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(CD, posedge CK, 224);\n\t\tif (!CD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// Sync preset\n(* abc9_flop, lib_whitebox *)\nmodule FD1P3JX(input D, CK, SP, PD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b1;\n\talways @(posedge CK)\n\t\tif (PD)\n\t\t\tQ <= 1'b1;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(PD, posedge CK, 224);\n\t\tif (!PD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// LUT4 with LUT3 tap for CCU2 use only\n(* lib_whitebox *)\nmodule LUT4_3(input A, B, C, D, output Z, Z3);\n\tparameter INIT = \"0x0000\";\n`include \"parse_init.vh\"\n\tlocalparam initp = parse_init(INIT);\n\twire [7:0] s3 = D ?     initp[15:8] :     initp[7:0];\n\twire [3:0] s2 = C ?        s3[ 7:4] :        s3[3:0];\n\twire [1:0] s1 = B ?        s2[ 3:2] :        s2[1:0];\n\tassign Z =      A ?           s1[1] :          s1[0];\n\n\twire [3:0] s2_3 = C ?   initp[ 7:4] :     initp[3:0];\n\twire [1:0] s1_3 = B ?    s2_3[ 3:2] :      s2_3[1:0];\n\tassign Z3 =       A ?       s1_3[1] :        s1_3[0];\n\nendmodule\n\n// Carry primitive (incoporating two LUTs)\n(* abc9_box, lib_whitebox *)\nmodule CCU2(\n\t(* abc9_carry *) input CIN,\n\tinput A1, B1, C1, D1, A0, B0, C0, D0,\n\toutput S1, S0,\n\t(* abc9_carry *) output COUT);\n\tparameter INJECT = \"YES\";\n\tparameter INIT0 = \"0x0000\";\n\tparameter INIT1 = \"0x1111\";\n\n\tlocalparam inject_p = (INJECT == \"YES\") ? 1'b1 : 1'b0;\n\n\twire LUT3_0, LUT4_0, LUT3_1, LUT4_1, carry_0;\n\tLUT4_3 #(.INIT(INIT0)) lut0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0), .Z3(LUT3_0));\n\tLUT4_3 #(.INIT(INIT1)) lut1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1), .Z3(LUT3_1));\n\n\tassign S0 = LUT4_0 ^ (CIN & ~inject_p);\n\tassign carry_0 = LUT4_0 ? CIN : (LUT3_0 & ~inject_p);\n\tassign S1 = LUT4_1 ^ (carry_0 & ~inject_p);\n\tassign COUT = LUT4_1 ? carry_0 : (LUT3_1 & ~inject_p);\n\n\tspecify\n\t\t(A0 => S0) = 233;\n\t\t(B0 => S0) = 233;\n\t\t(C0 => S0) = 233;\n\t\t(D0 => S0) = 233;\n\t\t(CIN => S0) = 228;\n\t\t(A0 => S1) = 481;\n\t\t(B0 => S1) = 481;\n\t\t(C0 => S1) = 481;\n\t\t(D0 => S1) = 481;\n\t\t(A1 => S1) = 233;\n\t\t(B1 => S1) = 233;\n\t\t(C1 => S1) = 233;\n\t\t(D1 => S1) = 233;\n\t\t(CIN => S1) = 307;\n\t\t(A0 => COUT) = 347;\n\t\t(B0 => COUT) = 347;\n\t\t(C0 => COUT) = 347;\n\t\t(D0 => COUT) = 347;\n\t\t(A1 => COUT) = 347;\n\t\t(B1 => COUT) = 347;\n\t\t(C1 => COUT) = 347;\n\t\t(D1 => COUT) = 347;\n\t\t(CIN => COUT) = 59;\n\tendspecify\n\nendmodule\n\n// Packed flipflop\nmodule OXIDE_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter REGDDR = \"DISABLED\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (REGDDR == \"ENABLED\") begin\n\t\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\t\talways @(posedge muxclk, negedge muxclk, posedge muxlsr)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend else begin\n\t\t\t\talways @(posedge muxclk, negedge muxclk)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend\n\t\tend else begin\n\t\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend else begin\n\t\t\t\talways @(posedge muxclk)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n// Packed combinational logic (for post-pnr sim)\nmodule OXIDE_COMB(\n\tinput A, B, C, D, // LUT inputs\n\tinput SEL, // mux select input\n\tinput F1, // output from LUT 1 for mux\n\tinput FCI, // carry input\n\tinput WAD0, WAD1, WAD2, WAD3, // LUTRAM write address inputs\n\tinput WD, // LUTRAM write data input\n\tinput WCK, WRE, // LUTRAM write clock and enable\n\toutput F, // LUT/carry output\n\toutput OFX // mux output\n);\n\tparameter MODE = \"LOGIC\"; // LOGIC, CCU2, DPRAM\n\tparameter [15:0] INIT = 16'h0000;\n\tparameter INJECT = \"YES\";\n\n\tlocalparam inject_p = (INJECT == \"YES\") ? 1'b1 : 1'b0;\n\n\treg [15:0] lut = INIT;\n\n\twire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];\n\twire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];\n\twire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];\n\twire Z =        A ?          s1[1] :         s1[0];\n\n\twire [3:0] s2_3 = C ?   INIT[ 7:4] :     INIT[3:0];\n\twire [1:0] s1_3 = B ?   s2_3[ 3:2] :     s2_3[1:0];\n\twire Z3 =         A ?      s1_3[1] :       s1_3[0];\n\n\tgenerate\n\t\tif (MODE == \"DPRAM\") begin\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tlut[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\tend\n\t\tif (MODE == \"CCU2\") begin\n\t\t\tassign F = Z ^ (FCI & ~inject_p);\n\t\t\tassign FCO = Z ? FCI : (Z3 & ~inject_p);\n\t\tend else begin\n\t\t\tassign F = Z;\n\t\tend\n\tendgenerate\n\n\tassign OFX = SEL ? F1 : F;\n\nendmodule\n\n// LUTRAM\nmodule DPR16X4(\n\tinput [3:0] RAD, DI, WAD,\n\tinput WRE, WCK,\n\toutput [3:0] DO\n);\n\tparameter INITVAL = \"0x0000000000000000\";\n`include \"parse_init.vh\"\n\tlocalparam [63:0] parsed_init = parse_init_64(INITVAL);\n\n\treg [3:0] mem[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i++)\n\t\t\tmem[i] = parsed_init[i * 4 +: 4];\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tmem[WAD] <= DI;\n\tassign DO = mem[RAD];\nendmodule\n\n// Used for all the DSP models to reduce duplication\nmodule OXIDE_DSP_REG #(\n\tparameter W = 18,\n\tparameter USED = \"REGISTER\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput CLK, CE, RST,\n\tinput [W-1:0] D,\n\toutput reg [W-1:0] Q\n);\n\tgenerate\n\t\tif (USED == \"BYPASS\")\n\t\t\talways @* Q = D;\n\t\telse if (USED == \"REGISTER\") begin\n\t\t\tinitial Q = 0;\n\t\t\tif (RESETMODE == \"ASYNC\")\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif (RST)\n\t\t\t\t\t\tQ <= 0;\n\t\t\t\t\telse if (CE)\n\t\t\t\t\t\tQ <= D;\n\t\t\t\tend\n\t\t\telse if (RESETMODE == \"SYNC\")\n\t\t\t\talways @(posedge CLK) begin\n\t\t\t\t\tif (RST)\n\t\t\t\t\t\tQ <= 0;\n\t\t\t\t\telse if (CE)\n\t\t\t\t\t\tQ <= D;\n\t\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\nmodule OXIDE_DSP_SIM #(\n\t// User facing parameters\n\tparameter REGINPUTA = \"BYPASS\",\n\tparameter REGINPUTB = \"BYPASS\",\n\tparameter REGINPUTC = \"BYPASS\",\n\tparameter REGADDSUB = \"BYPASS\",\n\tparameter REGLOADC = \"BYPASS\",\n\tparameter REGLOADC2 = \"BYPASS\",\n\tparameter REGCIN = \"BYPASS\",\n\tparameter REGPIPELINE = \"BYPASS\",\n\tparameter REGOUTPUT = \"BYPASS\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\",\n\t// Internally used parameters\n\tparameter A_WIDTH = 36,\n\tparameter B_WIDTH = 36,\n\tparameter C_WIDTH = 36,\n\tparameter Z_WIDTH = 72,\n\tparameter PREADD_USED = 0,\n\tparameter ADDSUB_USED = 0\n) (\n\tinput [A_WIDTH-1:0] A,\n\tinput [B_WIDTH-1:0] B,\n\tinput [C_WIDTH-1:0] C,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput SIGNEDC,\n\tinput CIN,\n\tinput LOADC,\n\tinput ADDSUB,\n\tinput CLK,\n\tinput CEA, CEB, CEC, CEPIPE, CECTRL, CECIN, CEOUT,\n\tinput RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,\n\toutput wire [Z_WIDTH-1:0] Z\n);\n\t\n\tlocalparam M_WIDTH = (A_WIDTH+B_WIDTH);\n\n\t/******** REGISTERS ********/\n\n\twire [M_WIDTH-1:0] pipe_d, pipe_q;\n\twire [Z_WIDTH-1:0] z_d;\n\n\twire [A_WIDTH-1:0] a_r;\n\twire [B_WIDTH-1:0] b_r;\n\twire [C_WIDTH-1:0] c_r, c_r2;\n\twire asgd_r, bsgd_r, csgd_r, csgd_r2;\n\n\twire addsub_r, addsub_r2, cin_r, cin_r2, sgd_r, sgd_r2;\n\twire loadc_r, loadc_r2;\n\n\tOXIDE_DSP_REG #(A_WIDTH+1, REGINPUTA, RESETMODE) a_reg(CLK, CEA, RSTA, {SIGNEDA, A}, {asgd_r, a_r});\n\tOXIDE_DSP_REG #(B_WIDTH+1, REGINPUTB, RESETMODE) b_reg(CLK, CEB, RSTB, {SIGNEDB, B}, {bsgd_r, b_r});\n\tOXIDE_DSP_REG #(C_WIDTH+1, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNEDC, C}, {csgd_r, c_r});\n\n\tOXIDE_DSP_REG #(M_WIDTH, REGPIPELINE, RESETMODE) pipe_reg(CLK, CEPIPE, RSTPIPE, pipe_d, pipe_q);\n\n\tOXIDE_DSP_REG #(2, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNEDA, ADDSUB}, {sgd_r, addsub_r});\n\tOXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);\n\tOXIDE_DSP_REG #(2, REGPIPELINE, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});\n\tOXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);\n\n\tOXIDE_DSP_REG #(1, REGCIN, RESETMODE) cin_reg(CLK, CECIN, RSTCIN, CIN, cin_r);\n\tOXIDE_DSP_REG #(1, REGPIPELINE, RESETMODE) cin2_reg(CLK, CECIN, RSTCIN, cin_r, cin_r2);\n\n\tOXIDE_DSP_REG #(C_WIDTH+1, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});\n\n\tOXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);\n\n\t/******** PREADDER ********/\n\n\twire [B_WIDTH-1:0] mult_b;\n\twire mult_b_sgd;\n\n\tgenerate\n\t\tif (PREADD_USED) begin\n\t\t\tassign mult_b = (b_r + c_r);\n\t\t\tassign mult_b_sgd = (bsgd_r | csgd_r);\n\t\tend else begin\n\t\t\tassign mult_b = b_r;\n\t\t\tassign mult_b_sgd = bsgd_r;\n\t\tend\n\tendgenerate\n\n\t/******** MULTIPLIER ********/\n\n\t// sign extend operands if needed\n\twire [M_WIDTH-1:0] mult_a_ext = {{(M_WIDTH-A_WIDTH){asgd_r ? a_r[A_WIDTH-1] : 1'b0}}, a_r};\n\twire [M_WIDTH-1:0] mult_b_ext = {{(M_WIDTH-B_WIDTH){mult_b_sgd ? mult_b[B_WIDTH-1] : 1'b0}}, mult_b};\n\n\twire [M_WIDTH-1:0] mult_m = mult_a_ext * mult_b_ext;\n\n\t/******** ACCUMULATOR ********/\n\n\twire [Z_WIDTH-1:0] m_ext;\n\n\tgenerate\n\t\tif (ADDSUB_USED) begin\n\t\t\tassign pipe_d = mult_m;\n\t\t\tassign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};\n\t\t\tassign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);  \n\t\tend else begin\n\t\t\tassign z_d = mult_m;\n\t\tend\n\tendgenerate\n\n\nendmodule\n\nmodule MULT9X9 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [8:0] A,\n\tinput [8:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [17:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(9),\n\t\t.B_WIDTH(9),\n\t\t.Z_WIDTH(18),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULT18X18 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [17:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [35:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(18),\n\t\t.Z_WIDTH(36),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULT18X36 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [35:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [53:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(36),\n\t\t.Z_WIDTH(54),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULT36X36 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [35:0] A,\n\tinput [35:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [71:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(36),\n\t\t.B_WIDTH(36),\n\t\t.Z_WIDTH(72),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTPREADD9X9 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [8:0] A,\n\tinput [8:0] B,\n\tinput [8:0] C,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput CEC,\n\tinput RSTC,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput SIGNEDC,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [17:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(9),\n\t\t.B_WIDTH(9),\n\t\t.C_WIDTH(9),\n\t\t.Z_WIDTH(18),\n\t\t.PREADD_USED(1),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTPREADD18X18 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [17:0] B,\n\tinput [17:0] C,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput CEC,\n\tinput RSTC,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput SIGNEDC,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [35:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(18),\n\t\t.C_WIDTH(18),\n\t\t.Z_WIDTH(36),\n\t\t.PREADD_USED(1),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTADDSUB18X18 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGADDSUB = \"REGISTER\",\n\tparameter REGLOADC = \"REGISTER\",\n\tparameter REGLOADC2 = \"REGISTER\",\n\tparameter REGCIN = \"REGISTER\",\n\tparameter REGPIPELINE = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [17:0] B,\n\tinput [53:0] C,\n    input CLK,\n    input CEA,\n    input RSTA,\n    input CEB,\n    input RSTB,\n    input CEC,\n    input RSTC,\n    input SIGNED,\n    input RSTPIPE,\n    input CEPIPE,\n    input RSTCTRL,\n    input CECTRL,\n    input RSTCIN,\n    input CECIN,\n    input LOADC,\n    input ADDSUB,\n    output [53:0] Z,\n    input RSTOUT,\n    input CEOUT,\n    input CIN\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGADDSUB(REGADDSUB),\n\t\t.REGLOADC(REGLOADC),\n\t\t.REGLOADC2(REGLOADC2),\n\t\t.REGCIN(REGCIN),\n\t\t.REGPIPELINE(REGPIPELINE),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(18),\n\t\t.C_WIDTH(54),\n\t\t.Z_WIDTH(54),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(1)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),\n\t\t.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),\n\t\t.CECIN(CECIN), .RSTCIN(RSTCIN),\n\t\t.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),\n\t\t.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTADDSUB36X36 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGADDSUB = \"REGISTER\",\n\tparameter REGLOADC = \"REGISTER\",\n\tparameter REGLOADC2 = \"REGISTER\",\n\tparameter REGCIN = \"REGISTER\",\n\tparameter REGPIPELINE = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [35:0] A,\n\tinput [35:0] B,\n\tinput [107:0] C,\n    input CLK,\n    input CEA,\n    input RSTA,\n    input CEB,\n    input RSTB,\n    input CEC,\n    input RSTC,\n    input SIGNED,\n    input RSTPIPE,\n    input CEPIPE,\n    input RSTCTRL,\n    input CECTRL,\n    input RSTCIN,\n    input CECIN,\n    input LOADC,\n    input ADDSUB,\n    output [107:0] Z,\n    input RSTOUT,\n    input CEOUT,\n    input CIN\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGADDSUB(REGADDSUB),\n\t\t.REGLOADC(REGLOADC),\n\t\t.REGLOADC2(REGLOADC2),\n\t\t.REGCIN(REGCIN),\n\t\t.REGPIPELINE(REGPIPELINE),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(36),\n\t\t.B_WIDTH(36),\n\t\t.C_WIDTH(108),\n\t\t.Z_WIDTH(108),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(1)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),\n\t\t.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),\n\t\t.CECIN(CECIN), .RSTCIN(RSTCIN),\n\t\t.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),\n\t\t.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULTADDSUB9X9WIDE #(\n\tparameter REGINPUTAB0 = \"REGISTER\",\n\tparameter REGINPUTAB1 = \"REGISTER\",\n\tparameter REGINPUTAB2 = \"REGISTER\",\n\tparameter REGINPUTAB3 = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGADDSUB = \"REGISTER\",\n\tparameter REGLOADC = \"REGISTER\",\n\tparameter REGLOADC2 = \"REGISTER\",\n\tparameter REGPIPELINE = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [8:0] A0, B0, A1, B1, A2, B2, A3, B3,\n\tinput [53:0] C,\n\tinput CLK,\n\tinput CEA0A1, CEA2A3,\n\tinput RSTA0A1, RSTA2A3,\n\tinput CEB0B1, CEB2B3,\n\tinput RSTB0B1, RSTB2B3,\n\tinput CEC, RSTC,\n\tinput CECTRL, RSTCTRL,\n\tinput SIGNED,\n\tinput RSTPIPE, CEPIPE,\n\tinput RSTOUT, CEOUT,\n\tinput LOADC,\n\tinput [3:0] ADDSUB,\n\toutput [53:0] Z\n);\n\twire [17:0] m0, m1, m2, m3;\n\n\tlocalparam M_WIDTH = 18;\n\tlocalparam Z_WIDTH = 54;\n\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB0), .REGINPUTB(REGINPUTAB0), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_0 (\n\t\t.A(A0), .B(B0), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA0A1), .RSTA(RSTA0A1),\n\t\t.CEB(CEB0B1), .RSTB(RSTB0B1),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m0)\n\t);\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB1), .REGINPUTB(REGINPUTAB1), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_1 (\n\t\t.A(A1), .B(B1), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA0A1), .RSTA(RSTA0A1),\n\t\t.CEB(CEB0B1), .RSTB(RSTB0B1),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m1)\n\t);\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB2), .REGINPUTB(REGINPUTAB2), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_2 (\n\t\t.A(A2), .B(B2), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA2A3), .RSTA(RSTA2A3),\n\t\t.CEB(CEB2B3), .RSTB(RSTB2B3),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m2)\n\t);\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB3), .REGINPUTB(REGINPUTAB3), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_3 (\n\t\t.A(A3), .B(B3), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA2A3), .RSTA(RSTA2A3),\n\t\t.CEB(CEB2B3), .RSTB(RSTB2B3),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m3)\n\t);\n\n\twire [53:0] c_r, c_r2;\n\twire [3:0] addsub_r, addsub_r2;\n\twire sgd_r, sgd_r2, csgd_r, csgd_r2;\n\twire loadc_r, loadc_r2;\n\n\tOXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNED, ADDSUB}, {sgd_r, addsub_r});\n\tOXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});\n\n\tOXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);\n\tOXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);\n\n\tOXIDE_DSP_REG #(55, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNED, C}, {csgd_r, c_r});\n\tOXIDE_DSP_REG #(55, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});\n\n\n\twire [18:0] m0_ext, m1_ext, m2_ext, m3_ext;\n\n\tassign m0_ext = {sgd_r2 ? m0[M_WIDTH-1] : 1'b0, m0};\n\tassign m1_ext = {sgd_r2 ? m1[M_WIDTH-1] : 1'b0, m1};\n\tassign m2_ext = {sgd_r2 ? m2[M_WIDTH-1] : 1'b0, m2};\n\tassign m3_ext = {sgd_r2 ? m3[M_WIDTH-1] : 1'b0, m3};\n\n\twire [18:0] s0 = addsub_r2[2] ? (m0_ext - m1_ext) : (m0_ext + m1_ext);\n\twire [18:0] s1 = addsub_r2[3] ? (m2_ext - m3_ext) : (m2_ext + m3_ext);\n\n\twire [53:0] s0_ext = {{(54-19){sgd_r2 ? s0[18] : 1'b0}}, s0};\n\twire [53:0] s1_ext = {{(54-19){sgd_r2 ? s1[18] : 1'b0}}, s1};\n\n\twire [53:0] c_op = loadc_r2 ? c_r2 : Z;\n\n\t// The diagram in the docs is wrong! It is not two cascaded 2-input add/subs as shown,\n\t// but a three-input unit with negation controls on two inputs (i.e. addsub_r2[0]\n\t// negates s1 not (s1 +/- s0))\n\twire [53:0] z_d =  c_op + (addsub_r2[0] ? -s1_ext : s1_ext) + (addsub_r2[1] ? -s0_ext : s0_ext);\n\n\tOXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);\n\nendmodule\n",
             "cells_sim_xo2.v": "`include \"common_sim.vh\"\n`include \"ccu2d_sim.vh\"\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
             "cells_sim_xo3.v": "`include \"common_sim.vh\"\n`include \"ccu2d_sim.vh\"\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
             "cells_sim_xo3d.v": "`include \"common_sim.vh\"\n`include \"ccu2d_sim.vh\"\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
-            "common_sim.vh": "// ---------------------------------------\n\n(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n    parameter [15:0] INIT = 16'h0000;\n    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];\n    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];\n    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\n    specify\n        (A => Z) = 141;\n        (B => Z) = 275;\n        (C => Z) = 379;\n        (D => Z) = 379;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   cost of 5-input LUTs and is not intended to be instantiated\n// LUT5 = 2x LUT4 + PFUMX\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input M0, D, C, B, A, output Z);\n    specify\n        (M0 => Z) = 151;\n        (D => Z) = 239;\n        (C => Z) = 373;\n        (B => Z) = 477;\n        (A => Z) = 477;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 6-input LUTs and is not intended to be instantiated\n// LUT6 = 2x LUT5 + MUX2\n(* abc9_lut=4 *)\nmodule \\$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);\n    specify\n        (M1 => Z) = 148;\n        (M0 => Z) = 292;\n        (D => Z) = 380;\n        (C => Z) = 514;\n        (B => Z) = 618;\n        (A => Z) = 618;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 7-input LUTs and is not intended to be instantiated\n// LUT7 = 2x LUT6 + MUX2\n(* abc9_lut=8 *)\nmodule \\$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);\n    specify\n        (M2 => Z) = 148;\n        (M1 => Z) = 289;\n        (M0 => Z) = 433;\n        (D => Z) = 521;\n        (C => Z) = 655;\n        (B => Z) = 759;\n        (A => Z) = 759;\n    endspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule L6MUX21 (input D0, D1, SD, output Z);\n\tassign Z = SD ? D1 : D0;\n\tspecify\n\t\t(D0 => Z) = 140;\n\t\t(D1 => Z) = 141;\n\t\t(SD => Z) = 148;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_RAM16X2 (\n\tinput DI0, DI1,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\tinput RAD0, RAD1, RAD2, RAD3,\n\toutput DO0, DO1\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter INITVAL_0 = 16'h0000;\n\tparameter INITVAL_1 = 16'h0000;\n\n\treg [1:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= {INITVAL_1[i], INITVAL_0[i]};\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};\n\n\tassign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule PFUMX (input ALUT, BLUT, C0, output Z);\n\tassign Z = C0 ? ALUT : BLUT;\n\tspecify\n\t\t(ALUT => Z) = 98;\n\t\t(BLUT => Z) = 98;\n\t\t(C0 => Z) = 151;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule TRELLIS_DPR16X4 (\n\tinput  [3:0] DI,\n\tinput  [3:0] WAD,\n\tinput        WRE,\n\tinput        WCK,\n\tinput  [3:0] RAD,\n\toutput [3:0] DO\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter [63:0] INITVAL = 64'h0000000000000000;\n\n\treg [3:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= INITVAL[4*i +: 4];\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[WAD] <= DI;\n\n\tassign DO = mem[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* abc9_box, lib_whitebox *)\nmodule DPR16X4C (\n\t\tinput [3:0] DI,\n\t\tinput WCK, WRE,\n\t\tinput [3:0] RAD,\n\t\tinput [3:0] WAD,\n\t\toutput [3:0] DO\n);\n\t// For legacy Lattice compatibility, INITIVAL is a hex\n\t// string rather than a numeric parameter\n\tparameter INITVAL = \"0x0000000000000000\";\n\n\tfunction [63:0] convert_initval;\n\t\tinput [143:0] hex_initval;\n\t\treg done;\n\t\treg [63:0] temp;\n\t\treg [7:0] char;\n\t\tinteger i;\n\t\tbegin\n\t\t\tdone = 1'b0;\n\t\t\ttemp = 0;\n\t\t\tfor (i = 0; i < 16; i = i + 1) begin\n\t\t\t\tif (!done) begin\n\t\t\t\t\tchar = hex_initval[8*i +: 8];\n\t\t\t\t\tif (char == \"x\") begin\n\t\t\t\t\t\tdone = 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (char >= \"0\" && char <= \"9\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = char - \"0\";\n\t\t\t\t\t\telse if (char >= \"A\" && char <= \"F\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"A\";\n\t\t\t\t\t\telse if (char >= \"a\" && char <= \"f\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"a\";\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tconvert_initval = temp;\n\t\tend\n\tendfunction\n\n\tlocalparam conv_initval = convert_initval(INITVAL);\n\n\treg [3:0] ram[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i = i + 1) begin\n\t\t\tram[i] <= conv_initval[4*i +: 4];\n\t\tend\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tram[WAD] <= DI;\n\n\tassign DO = ram[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* lib_whitebox *)\nmodule LUT2(input A, B, output Z);\n    parameter [3:0] INIT = 4'h0;\n    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\nendmodule\n\n// ---------------------------------------\n\n`ifdef YOSYS\n(* abc9_flop=(SRMODE != \"ASYNC\"), abc9_box=(SRMODE == \"ASYNC\"), lib_whitebox *)\n`endif\nmodule TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend else begin\n\t\t\talways @(posedge muxclk)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend\n\tendgenerate\n\n\tspecify\n\t\t$setup(DI, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(CE, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(LSR, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(DI, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(CE, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(LSR, posedge CLK &&& CLKMUX != \"INV\", 0);\n`ifndef YOSYS\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX == \"INV\") (negedge CLK => (Q : srval)) = 0;\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX != \"INV\") (posedge CLK => (Q : srval)) = 0;\n`else\n\t\tif (SRMODE == \"ASYNC\" && muxlsr) (LSR => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!muxlsr && muxce && CLKMUX == \"INV\") (negedge CLK => (Q : DI)) = 0;\n\t\tif (!muxlsr && muxce && CLKMUX != \"INV\") (posedge CLK => (Q : DI)) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* keep *)\nmodule TRELLIS_IO(\n\t(* iopad_external_pin *)\n\tinout B,\n\tinput I,\n\tinput T,\n\toutput O\n);\n\tparameter DIR = \"INPUT\";\n\treg T_pd;\n\talways @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;\n\n\tgenerate\n\t\tif (DIR == \"INPUT\") begin\n\t\t\tassign B = 1'bz;\n\t\t\tassign O = B;\n\t\tend else if (DIR == \"OUTPUT\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = 1'bx;\n\t\tend else if (DIR == \"BIDIR\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = B;\n\t\tend else begin\n\t\t\tERROR_UNKNOWN_IO_MODE error();\n\t\tend\n\tendgenerate\n\nendmodule\n\n// ---------------------------------------\n\nmodule INV(input A, output Z);\n\tassign Z = !A;\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_COMB(\n\tinput A, B, C, D, M,\n\tinput FCI, F1, FXA, FXB,\n\tinput WD,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\toutput F, FCO, OFX\n);\n\tparameter MODE = \"LOGIC\";\n\tparameter INITVAL = 16'h0;\n\tparameter CCU2_INJECT1 = \"NO\";\n\tparameter WREMUX = \"WRE\";\n\tparameter IS_Z1 = 1'b0;\n\n\tgenerate\n\t\tif (MODE == \"LOGIC\") begin: mode_logic\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));\n\t\tend else if (MODE == \"CCU2\") begin: mode_ccu2\n\t\t\twire l4o, l2o;\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));\n\t\t\tLUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));\n\t\t\twire gated_cin_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : FCI;\n\t\t\tassign F = l4o ^ gated_cin_0;\n\t\t\twire gated_lut2_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : l2o;\n\t\t\twire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);\n\t\tend else if (MODE == \"DPRAM\") begin: mode_dpram\n\t\t\treg [15:0] ram = INITVAL;\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tram[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\t\tassign F = ram[{A, C, B, D}];\n\t\tend else begin\n\t\t\t$error(\"unsupported COMB mode %s\", MODE);\n\t\tend\n\n \t\tif (IS_Z1)\n\t\t\tL6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));\n\t\telse\n\t\t\tPFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));\n\tendgenerate\n\nendmodule\n\n// Constants\nmodule VLO(output Z);\n\tassign Z = 1'b0;\nendmodule\n\nmodule VHI(output Z);\n\tassign Z = 1'b1;\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
+            "common_sim.vh": "// ---------------------------------------\n\n(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n    parameter [15:0] INIT = 16'h0000;\n    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];\n    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];\n    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\n    specify\n        (A => Z) = 141;\n        (B => Z) = 275;\n        (C => Z) = 379;\n        (D => Z) = 379;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   cost of 5-input LUTs and is not intended to be instantiated\n// LUT5 = 2x LUT4 + PFUMX\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input M0, D, C, B, A, output Z);\n    specify\n        (M0 => Z) = 151;\n        (D => Z) = 239;\n        (C => Z) = 373;\n        (B => Z) = 477;\n        (A => Z) = 477;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 6-input LUTs and is not intended to be instantiated\n// LUT6 = 2x LUT5 + MUX2\n(* abc9_lut=4 *)\nmodule \\$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);\n    specify\n        (M1 => Z) = 148;\n        (M0 => Z) = 292;\n        (D => Z) = 380;\n        (C => Z) = 514;\n        (B => Z) = 618;\n        (A => Z) = 618;\n    endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   of 7-input LUTs and is not intended to be instantiated\n// LUT7 = 2x LUT6 + MUX2\n(* abc9_lut=8 *)\nmodule \\$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);\n    specify\n        (M2 => Z) = 148;\n        (M1 => Z) = 289;\n        (M0 => Z) = 433;\n        (D => Z) = 521;\n        (C => Z) = 655;\n        (B => Z) = 759;\n        (A => Z) = 759;\n    endspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule L6MUX21 (input D0, D1, SD, output Z);\n\tassign Z = SD ? D1 : D0;\n\tspecify\n\t\t(D0 => Z) = 140;\n\t\t(D1 => Z) = 141;\n\t\t(SD => Z) = 148;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_RAM16X2 (\n\tinput DI0, DI1,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\tinput RAD0, RAD1, RAD2, RAD3,\n\toutput DO0, DO1\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter INITVAL_0 = 16'h0000;\n\tparameter INITVAL_1 = 16'h0000;\n\n\treg [1:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= {INITVAL_1[i], INITVAL_0[i]};\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};\n\n\tassign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule PFUMX (input ALUT, BLUT, C0, output Z);\n\tassign Z = C0 ? ALUT : BLUT;\n\tspecify\n\t\t(ALUT => Z) = 98;\n\t\t(BLUT => Z) = 98;\n\t\t(C0 => Z) = 151;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule TRELLIS_DPR16X4 (\n\tinput  [3:0] DI,\n\tinput  [3:0] WAD,\n\tinput        WRE,\n\tinput        WCK,\n\tinput  [3:0] RAD,\n\toutput [3:0] DO\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter [63:0] INITVAL = 64'h0000000000000000;\n\n\treg [3:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= INITVAL[4*i +: 4];\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[WAD] <= DI;\n\n\tassign DO = mem[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* abc9_box, lib_whitebox *)\nmodule DPR16X4C (\n\t\tinput [3:0] DI,\n\t\tinput WCK, WRE,\n\t\tinput [3:0] RAD,\n\t\tinput [3:0] WAD,\n\t\toutput [3:0] DO\n);\n\t// For legacy Lattice compatibility, INITIVAL is a hex\n\t// string rather than a numeric parameter\n\tparameter INITVAL = \"0x0000000000000000\";\n\n\tfunction [63:0] convert_initval;\n\t\tinput [143:0] hex_initval;\n\t\treg done;\n\t\treg [63:0] temp;\n\t\treg [7:0] char;\n\t\tinteger i;\n\t\tbegin\n\t\t\tdone = 1'b0;\n\t\t\ttemp = 0;\n\t\t\tfor (i = 0; i < 16; i = i + 1) begin\n\t\t\t\tif (!done) begin\n\t\t\t\t\tchar = hex_initval[8*i +: 8];\n\t\t\t\t\tif (char == \"x\") begin\n\t\t\t\t\t\tdone = 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (char >= \"0\" && char <= \"9\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = char - \"0\";\n\t\t\t\t\t\telse if (char >= \"A\" && char <= \"F\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"A\";\n\t\t\t\t\t\telse if (char >= \"a\" && char <= \"f\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"a\";\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tconvert_initval = temp;\n\t\tend\n\tendfunction\n\n\tlocalparam conv_initval = convert_initval(INITVAL);\n\n\treg [3:0] ram[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i = i + 1) begin\n\t\t\tram[i] <= conv_initval[4*i +: 4];\n\t\tend\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tram[WAD] <= DI;\n\n\tassign DO = ram[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* lib_whitebox *)\nmodule LUT2(input A, B, output Z);\n    parameter [3:0] INIT = 4'h0;\n    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];\n    assign Z =      A ?          s1[1] :         s1[0];\nendmodule\n\n// ---------------------------------------\n\n`ifdef YOSYS\n(* abc9_flop=(SRMODE != \"ASYNC\"), abc9_box=(SRMODE == \"ASYNC\"), lib_whitebox *)\n`endif\nmodule TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend else begin\n\t\t\talways @(posedge muxclk)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend\n\tendgenerate\n\n\tspecify\n\t\t$setup(DI, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(CE, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(LSR, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(DI, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(CE, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(LSR, posedge CLK &&& CLKMUX != \"INV\", 0);\n`ifndef YOSYS\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX == \"INV\") (negedge CLK => (Q : srval)) = 0;\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX != \"INV\") (posedge CLK => (Q : srval)) = 0;\n`else\n\t\tif (SRMODE == \"ASYNC\" && muxlsr) (LSR => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!muxlsr && muxce && CLKMUX == \"INV\") (negedge CLK => (Q : DI)) = 0;\n\t\tif (!muxlsr && muxce && CLKMUX != \"INV\") (posedge CLK => (Q : DI)) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* keep *)\nmodule TRELLIS_IO(\n\t(* iopad_external_pin *)\n\tinout B,\n\tinput I,\n\tinput T,\n\toutput O\n);\n\tparameter DIR = \"INPUT\";\n\treg T_pd;\n\talways @(*) if (T === 1'bz) T_pd = 1'b0; else T_pd = T;\n\n\tgenerate\n\t\tif (DIR == \"INPUT\") begin\n\t\t\tassign B = 1'bz;\n\t\t\tassign O = B;\n\t\tend else if (DIR == \"OUTPUT\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = 1'bx;\n\t\tend else if (DIR == \"BIDIR\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = B;\n\t\tend else begin\n\t\t\tERROR_UNKNOWN_IO_MODE error();\n\t\tend\n\tendgenerate\n\nendmodule\n\n// ---------------------------------------\n\nmodule INV(input A, output Z);\n\tassign Z = !A;\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_COMB(\n\tinput A, B, C, D, M,\n\tinput FCI, F1, FXA, FXB,\n\tinput WD,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\toutput F, FCO, OFX\n);\n\tparameter MODE = \"LOGIC\";\n\tparameter INITVAL = 16'h0;\n\tparameter CCU2_INJECT1 = \"NO\";\n\tparameter WREMUX = \"WRE\";\n\tparameter IS_Z1 = 1'b0;\n\n\tgenerate\n\t\tif (MODE == \"LOGIC\") begin: mode_logic\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));\n\t\tend else if (MODE == \"CCU2\") begin: mode_ccu2\n\t\t\twire l4o, l2o;\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));\n\t\t\tLUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));\n\t\t\twire gated_cin_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : FCI;\n\t\t\tassign F = l4o ^ gated_cin_0;\n\t\t\twire gated_lut2_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : l2o;\n\t\t\twire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);\n\t\tend else if (MODE == \"DPRAM\") begin: mode_dpram\n\t\t\treg [15:0] ram = INITVAL;\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tram[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\t\tassign F = ram[{A, C, B, D}];\n\t\tend else begin\n\t\t\t$error(\"unsupported COMB mode %s\", MODE);\n\t\tend\n\n \t\tif (IS_Z1)\n\t\t\tL6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));\n\t\telse\n\t\t\tPFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));\n\tendgenerate\n\nendmodule\n\n// Constants\nmodule VLO(output Z);\n\tassign Z = 1'b0;\nendmodule\n\nmodule VHI(output Z);\n\tassign Z = 1'b1;\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
             "dsp_map_18x18.v": "module \\$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\n\tparameter A_WIDTH = 18;\n\tparameter B_WIDTH = 18;\n\tparameter Y_WIDTH = 36;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT18X18D _TECHMAP_REPLACE_ (\n\t\t.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),\n\t\t.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),\n\t\t.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),\n\n\t\t.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])\n\t);\nendmodule\n",
+            "dsp_map_nexus.v": "module \\$__NX_MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y);\n\n\tparameter A_WIDTH = 36;\n\tparameter B_WIDTH = 36;\n\tparameter Y_WIDTH = 72;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT36X36 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(A), .B(B),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n\nmodule \\$__NX_MUL36X18 (input [35:0] A, input [17:0] B, output [53:0] Y);\n\n\tparameter A_WIDTH = 36;\n\tparameter B_WIDTH = 18;\n\tparameter Y_WIDTH = 54;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT18X36 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(B), .B(A),\n\t\t.SIGNEDA(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n\nmodule \\$__NX_MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\n\tparameter A_WIDTH = 18;\n\tparameter B_WIDTH = 18;\n\tparameter Y_WIDTH = 36;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT18X18 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(A), .B(B),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n\nmodule \\$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);\n\n\tparameter A_WIDTH = 9;\n\tparameter B_WIDTH = 9;\n\tparameter Y_WIDTH = 18;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT9X9 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(A), .B(B),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n",
             "latches_map.v": "module \\$_DLATCH_N_ (E, D, Q);\n  wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n  input E, D;\n  output Q = !E ? D : Q;\nendmodule\n\nmodule \\$_DLATCH_P_ (E, D, Q);\n  wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n  input E, D;\n  output Q = E ? D : Q;\nendmodule\n",
-            "lutrams.txt": "ram distributed $__TRELLIS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit any;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock anyedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
-            "lutrams_map.v": "module $__TRELLIS_DPR16X4_(...);\n\nparameter INIT = 64'bx;\nparameter PORT_W_CLK_POL = 1;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput [3:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nlocalparam WCKMUX = PORT_W_CLK_POL ? \"WCK\" : \"INV\";\n\nTRELLIS_DPR16X4 #(\n\t.INITVAL(INIT),\n\t.WCKMUX(WCKMUX),\n\t.WREMUX(\"WRE\")\n) _TECHMAP_REPLACE_ (\n\t.RAD(PORT_R_ADDR),\n\t.DO(PORT_R_RD_DATA),\n\n\t.WAD(PORT_W_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.WCK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n\nendmodule\n",
+            "lrams_map_nexus.v": "module $__NX_DPSC512K_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\ninput CLK_C;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [3:0] PORT_A_WR_BE;\ninput [31:0] PORT_A_WR_DATA;\noutput [31:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [3:0] PORT_B_WR_BE;\ninput [31:0] PORT_B_WR_DATA;\noutput [31:0] PORT_B_RD_DATA;\n\nfunction [5119:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 128; i = i + 1) begin\n\t\tinit_slice[i*40+:32] = INIT[(idx * 128 + i) * 32+:32];\n\tend\nendfunction\n\nDPSC512K #(\n\t.INITVAL_00($sformatf(\"0x%01280x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%01280x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%01280x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%01280x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%01280x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%01280x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%01280x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%01280x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%01280x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%01280x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%01280x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%01280x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%01280x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%01280x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%01280x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%01280x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%01280x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%01280x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%01280x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%01280x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%01280x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%01280x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%01280x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%01280x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%01280x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%01280x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%01280x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%01280x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%01280x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%01280x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%01280x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%01280x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%01280x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%01280x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%01280x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%01280x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%01280x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%01280x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%01280x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%01280x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%01280x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%01280x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%01280x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%01280x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%01280x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%01280x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%01280x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%01280x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%01280x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%01280x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%01280x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%01280x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%01280x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%01280x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%01280x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%01280x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%01280x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%01280x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%01280x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%01280x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%01280x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%01280x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%01280x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%01280x\", init_slice('h3f))),\n\t.INITVAL_40($sformatf(\"0x%01280x\", init_slice('h40))),\n\t.INITVAL_41($sformatf(\"0x%01280x\", init_slice('h41))),\n\t.INITVAL_42($sformatf(\"0x%01280x\", init_slice('h42))),\n\t.INITVAL_43($sformatf(\"0x%01280x\", init_slice('h43))),\n\t.INITVAL_44($sformatf(\"0x%01280x\", init_slice('h44))),\n\t.INITVAL_45($sformatf(\"0x%01280x\", init_slice('h45))),\n\t.INITVAL_46($sformatf(\"0x%01280x\", init_slice('h46))),\n\t.INITVAL_47($sformatf(\"0x%01280x\", init_slice('h47))),\n\t.INITVAL_48($sformatf(\"0x%01280x\", init_slice('h48))),\n\t.INITVAL_49($sformatf(\"0x%01280x\", init_slice('h49))),\n\t.INITVAL_4A($sformatf(\"0x%01280x\", init_slice('h4a))),\n\t.INITVAL_4B($sformatf(\"0x%01280x\", init_slice('h4b))),\n\t.INITVAL_4C($sformatf(\"0x%01280x\", init_slice('h4c))),\n\t.INITVAL_4D($sformatf(\"0x%01280x\", init_slice('h4d))),\n\t.INITVAL_4E($sformatf(\"0x%01280x\", init_slice('h4e))),\n\t.INITVAL_4F($sformatf(\"0x%01280x\", init_slice('h4f))),\n\t.INITVAL_50($sformatf(\"0x%01280x\", init_slice('h50))),\n\t.INITVAL_51($sformatf(\"0x%01280x\", init_slice('h51))),\n\t.INITVAL_52($sformatf(\"0x%01280x\", init_slice('h52))),\n\t.INITVAL_53($sformatf(\"0x%01280x\", init_slice('h53))),\n\t.INITVAL_54($sformatf(\"0x%01280x\", init_slice('h54))),\n\t.INITVAL_55($sformatf(\"0x%01280x\", init_slice('h55))),\n\t.INITVAL_56($sformatf(\"0x%01280x\", init_slice('h56))),\n\t.INITVAL_57($sformatf(\"0x%01280x\", init_slice('h57))),\n\t.INITVAL_58($sformatf(\"0x%01280x\", init_slice('h58))),\n\t.INITVAL_59($sformatf(\"0x%01280x\", init_slice('h59))),\n\t.INITVAL_5A($sformatf(\"0x%01280x\", init_slice('h5a))),\n\t.INITVAL_5B($sformatf(\"0x%01280x\", init_slice('h5b))),\n\t.INITVAL_5C($sformatf(\"0x%01280x\", init_slice('h5c))),\n\t.INITVAL_5D($sformatf(\"0x%01280x\", init_slice('h5d))),\n\t.INITVAL_5E($sformatf(\"0x%01280x\", init_slice('h5e))),\n\t.INITVAL_5F($sformatf(\"0x%01280x\", init_slice('h5f))),\n\t.INITVAL_60($sformatf(\"0x%01280x\", init_slice('h60))),\n\t.INITVAL_61($sformatf(\"0x%01280x\", init_slice('h61))),\n\t.INITVAL_62($sformatf(\"0x%01280x\", init_slice('h62))),\n\t.INITVAL_63($sformatf(\"0x%01280x\", init_slice('h63))),\n\t.INITVAL_64($sformatf(\"0x%01280x\", init_slice('h64))),\n\t.INITVAL_65($sformatf(\"0x%01280x\", init_slice('h65))),\n\t.INITVAL_66($sformatf(\"0x%01280x\", init_slice('h66))),\n\t.INITVAL_67($sformatf(\"0x%01280x\", init_slice('h67))),\n\t.INITVAL_68($sformatf(\"0x%01280x\", init_slice('h68))),\n\t.INITVAL_69($sformatf(\"0x%01280x\", init_slice('h69))),\n\t.INITVAL_6A($sformatf(\"0x%01280x\", init_slice('h6a))),\n\t.INITVAL_6B($sformatf(\"0x%01280x\", init_slice('h6b))),\n\t.INITVAL_6C($sformatf(\"0x%01280x\", init_slice('h6c))),\n\t.INITVAL_6D($sformatf(\"0x%01280x\", init_slice('h6d))),\n\t.INITVAL_6E($sformatf(\"0x%01280x\", init_slice('h6e))),\n\t.INITVAL_6F($sformatf(\"0x%01280x\", init_slice('h6f))),\n\t.INITVAL_70($sformatf(\"0x%01280x\", init_slice('h70))),\n\t.INITVAL_71($sformatf(\"0x%01280x\", init_slice('h71))),\n\t.INITVAL_72($sformatf(\"0x%01280x\", init_slice('h72))),\n\t.INITVAL_73($sformatf(\"0x%01280x\", init_slice('h73))),\n\t.INITVAL_74($sformatf(\"0x%01280x\", init_slice('h74))),\n\t.INITVAL_75($sformatf(\"0x%01280x\", init_slice('h75))),\n\t.INITVAL_76($sformatf(\"0x%01280x\", init_slice('h76))),\n\t.INITVAL_77($sformatf(\"0x%01280x\", init_slice('h77))),\n\t.INITVAL_78($sformatf(\"0x%01280x\", init_slice('h78))),\n\t.INITVAL_79($sformatf(\"0x%01280x\", init_slice('h79))),\n\t.INITVAL_7A($sformatf(\"0x%01280x\", init_slice('h7a))),\n\t.INITVAL_7B($sformatf(\"0x%01280x\", init_slice('h7b))),\n\t.INITVAL_7C($sformatf(\"0x%01280x\", init_slice('h7c))),\n\t.INITVAL_7D($sformatf(\"0x%01280x\", init_slice('h7d))),\n\t.INITVAL_7E($sformatf(\"0x%01280x\", init_slice('h7e))),\n\t.INITVAL_7F($sformatf(\"0x%01280x\", init_slice('h7f))),\n\t.OUTREG_A(\"NO_REG\"),\n\t.OUTREG_B(\"NO_REG\"),\n\t.ECC_BYTE_SEL(\"BYTE_EN\"),\n\t.GSR(\"DISABLED\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n) _TECHMAP_REPLACE_ (\n\t.CLK(CLK_C),\n\n\t.WEA(PORT_A_WR_EN),\n\t.CEA(PORT_A_CLK_EN),\n\t.RSTA(OPTION_RESETMODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t.CSA(1'b1),\n\t.ADA(PORT_A_ADDR),\n\t.BENA_N(~PORT_A_WR_BE),\n\t.DIA(PORT_A_WR_DATA),\n\t.DOA(PORT_A_RD_DATA),\n\n\t.WEB(PORT_B_WR_EN),\n\t.CEB(PORT_B_CLK_EN),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t.CSB(1'b1),\n\t.BENB_N(~PORT_B_WR_BE),\n\t.ADB(PORT_B_ADDR),\n\t.DIB(PORT_B_WR_DATA),\n\t.DOB(PORT_B_RD_DATA),\n);\n\nendmodule\n",
+            "lrams_nexus.txt": "ram huge $__NX_DPSC512K_ {\n\tabits 14;\n\twidth 32;\n\tbyte 8;\n\tcost 2048;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge \"C\";\n\t\tclken;\n\t\twrbe_separate;\n\t\trdwr no_change;\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\twrtrans all old;\n\t}\n}\n",
+            "lutrams_map_nexus.v": "module $__NEXUS_DPR16X4_ (...);\n\tparameter INIT = 64'b0;\n\n\tinput PORT_W_CLK;\n\tinput [3:0] PORT_W_ADDR;\n\tinput [3:0] PORT_W_WR_DATA;\n\tinput PORT_W_WR_EN;\n\n\tinput [3:0] PORT_R_ADDR;\n\toutput [3:0] PORT_R_RD_DATA;\n\n\tDPR16X4 #(\n\t\t.INITVAL($sformatf(\"0x%08x\", INIT))\n\t) _TECHMAP_REPLACE_ (\n\t\t.RAD(PORT_R_ADDR),\n\t\t.DO(PORT_R_RD_DATA),\n\n\t\t.WAD(PORT_W_ADDR),\n\t\t.DI(PORT_W_WR_DATA),\n\t\t.WCK(PORT_W_CLK),\n\t\t.WRE(PORT_W_WR_EN)\n\t);\nendmodule\n",
+            "lutrams_map_trellis.v": "module $__TRELLIS_DPR16X4_(...);\n\nparameter INIT = 64'bx;\nparameter PORT_W_CLK_POL = 1;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput [3:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nlocalparam WCKMUX = PORT_W_CLK_POL ? \"WCK\" : \"INV\";\n\nTRELLIS_DPR16X4 #(\n\t.INITVAL(INIT),\n\t.WCKMUX(WCKMUX),\n\t.WREMUX(\"WRE\")\n) _TECHMAP_REPLACE_ (\n\t.RAD(PORT_R_ADDR),\n\t.DO(PORT_R_RD_DATA),\n\n\t.WAD(PORT_W_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.WCK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n\nendmodule\n",
+            "lutrams_nexus.txt": "ram distributed $__NEXUS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
+            "lutrams_trellis.txt": "ram distributed $__TRELLIS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit any;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock anyedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
+            "parse_init.vh": "function [15:0] parse_init;\n\tinput [((2+(16/4))*8)-1:0] init;\n\treg [7:0] c;\n\tinteger i;\n\tbegin\n\t\tfor (i = 0; i < (16/4); i = i + 1) begin\n\t\t\tc = init[(i * 8) +: 8];\n\t\t\tif (c >= \"0\" && c <= \"9\")\n\t\t\t\tparse_init[(i * 4) +: 4] = (c - \"0\");\n\t\t\telse if (c >= \"A\" && c <= \"F\")\n\t\t\t\tparse_init[(i * 4) +: 4] = (c - \"A\") + 10;\n\t\t\telse if (c >= \"a\" && c <= \"f\")\n\t\t\t\tparse_init[(i * 4) +: 4] = (c - \"a\") + 10;\n\t\tend\n\tend\nendfunction\n\nfunction [63:0] parse_init_64;\n\tinput [((2+(64/4))*8)-1:0] init;\n\treg [7:0] c;\n\tinteger i;\n\tbegin\n\t\tfor (i = 0; i < (64/4); i = i + 1) begin\n\t\t\tc = init[(i * 8) +: 8];\n\t\t\tif (c >= \"0\" && c <= \"9\")\n\t\t\t\tparse_init_64[(i * 4) +: 4] = (c - \"0\");\n\t\t\telse if (c >= \"A\" && c <= \"F\")\n\t\t\t\tparse_init_64[(i * 4) +: 4] = (c - \"A\") + 10;\n\t\t\telse if (c >= \"a\" && c <= \"f\")\n\t\t\t\tparse_init_64[(i * 4) +: 4] = (c - \"a\") + 10;\n\t\tend\n\tend\nendfunction\n",
         },
         "microchip": {
             "LSRAM.txt": "# ISC License\n# \n# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n# \n# Permission to use, copy, modify, and/or distribute this software for any\n# purpose with or without fee is hereby granted, provided that the above\n# copyright notice and this permission notice appear in all copies.\n# \n# THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n\n\n\n# LSRAM true dual-port\nram block $__LSRAM_TDP_ {\n\n\t# Cost of a given cell is assumed to be:\n\t#   (cost-widthscale) + [widthscale * (used_bits/14)]\n\tcost 129;\n\n\t# INIT is supported\n\tinit any;\n\n\t# port A and port B are allowed to have different widths, but they MUST have\n\t# \tWIDTH values of the same set. \n\t#      Example: Port A has a Data Width of 1. Then Port B's Data Width must be either\n\t#      1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).\t\n\t# \tWIDTH_1 = {1, 2, 4, 8, 16}\n\t# \tWIDTH_2 = {5, 10, 20}\n\n\t# \"byte\" specifies how many data bits correspond to one write enable bit.\n\t#\t\t\"byte\" must be larger than width, or width must be a multipler of \"byte\"\n\t#\t\tif \"byte\" > WIDTH, a single enable wire is inferred\n\t#\t\totherwise, WIDTH/byte number of enable wires are inferred\n\t# \t\t\n\t# \t\tWIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire\n\t# \t\tWIDTH = {16, 20} requires 2 enable wire\n\n\toption \"WIDTH_CONFIG\" \"REGULAR\" {\n\n\t\t# Data-Width| Address bits\n\t\t# 1 \t\t| 14\n\t\t# 2 \t\t| 13\n\t\t# 4 \t\t| 12\n\t\t# 8 \t\t| 11\n\t\t# 16\t\t| 10\n\n\t\t# 14 address bits\n\t\tabits 14;\n\n\t\twidths 1 2 4 8 16 per_port;\n\t\tbyte 8;\n\t}\n\toption \"WIDTH_CONFIG\" \"ALIGN\" {\n\t\t\n\t\t# Data-Width| Address bits\n\t\t# 5 \t\t| 12\n\t\t# 10\t\t| 11\n\t\t# 20\t\t| 10\n\n\t\t# Quick \"hack\" to fix address bit alignment by setting address bits to 12.\n\t\t#   If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20\n\t\t#   THe LSRAM_map.v file detects if this option is being used, and adjusts the address port alignments accordingly.\n\t\tabits 12;\n\n\t\twidths 5 10 20 per_port;\n\t\tbyte 10;\n\t}\n\t\n\t\n\n\tport srsw \"A\" \"B\" {\n\n\t\t# read & write width must be same\n\t\twidth tied;\n\t\t\n\t\t# clock polarity is rising\n\t\tclock posedge;\n\n\t\t# A/B read-enable\n\t\trden;\n\n\n\t\t# initial value of read port data (not supported)\n\t\trdinit none;\n\n\t\t# write modes (<A/B>_WMODE)\n\t\t# \t1. Simple Write: read-data port holds prev value (similar to \"NO_CHANGE\" for RAMB18E1)\n\t\t# \t2. Feed-through: read-data port takes new write value (similar to \"WRITE_FIRST\" for RAMB18E1)\n\t\t# \t3. Read-Before-Write: read-data port holds old value while being written (similar to \"READ_FIRST\" for RAMB18E1)\n\n\t\tportoption \"WRITE_MODE\" \"NO_CHANGE\" {\n\n\t\t\t# Read-write interaction\n\t\t\trdwr no_change;\n\n\t\t\t# Write transparency:\n\t\t\t#   For write ports, define behaviour when another synchronous read port \n\t\t\t#   reads from the same memory cell that said write port is writing to at the same time. \n\t\t\twrtrans all old;\n\t\t}\n\t\tportoption \"WRITE_MODE\" \"WRITE_FIRST\" {\n\t\t\t# bits corresponding to high A/B_WEN are updated\n\t\t\trdwr new_only;\n\t\t\twrtrans all new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\trdwr old;\n\n\t\t\twrtrans all old;\n\t\t}\n\n\t\t# generate params to indicate if read or write is used for each port\n\t\toptional_rw;\n\t}\n}\n\n# two-port configuration\nram block $__LSRAM_SDP_ {\n\t\n\t# since two-port configuration is dedicated for wide-read/write,\n\t#\twe want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs \n\t#\tinplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should\n\t#\tbe less than 2 TDP.\n\tcost 129;\n\tinit any;\n\n\toption \"WIDTH_CONFIG\" \"REGULAR\" {\n\n\t\t# Data-Width| Address bits\n\t\t# 1 \t\t| 14\n\t\t# 2 \t\t| 13\n\t\t# 4 \t\t| 12\n\t\t# 8 \t\t| 11\n\t\t# 16\t\t| 10\n\t\t# 32\t\t| 9\n\n\t\tabits 14;\n\n\t\twidths 1 2 4 8 16 32 per_port;\n\n\t\t# width = 32, byte-write size is 8, ignore other widths\n\t\tbyte 8;\n\t\t\n\t}\n\toption \"WIDTH_CONFIG\" \"ALIGN\" {\n\t\t\n\t\t# Data-Width| Address bits\n\t\t# 5 \t\t| 12\n\t\t# 10\t\t| 11\n\t\t# 20\t\t| 10\n\t\t# 40\t\t| 9\n\n\t\t# Same trick as TSP RAM for alignment\n\t\tabits 12;\n\t\twidths 5 10 20 40 per_port;\n\t\tbyte 10;\n\t}\n\n\tport sw \"W\" {\n\n\t\t# only consider wide write\n\t\t\n\t\toption \"WIDTH_CONFIG\" \"REGULAR\" width 32;\n\t\toption \"WIDTH_CONFIG\" \"ALIGN\" width 40;\n\n\t\tclock posedge;\n\n\t\t# only simple write supported for two-port mode\n\t\twrtrans all old;\n\t\t\n\t\toptional;\n\t}\n\tport sr \"R\" {\n\n\t\toption \"WIDTH_CONFIG\" \"REGULAR\" width 32;\n\t\toption \"WIDTH_CONFIG\" \"ALIGN\" width 40;\n\n\n\t\tclock posedge;\n\t\trden;\n\t\trdinit none;\n\t\toptional;\n\t}\n}\n",
@@ -330,18 +336,8 @@ export const filesystem = {
             "rf_rams_u.txt": "# Register-File  RAMs for NanoXplore NG-ULTRA\n\n# Dual-port RAMs.\n# NX_RFB_U in mode 0 (DPREG)\n# NX_RFB_U in mode 2 (NX_XRFB_64x18)\n# NX_RFB_U in mode 3 (NX_XRFB_32x36)\n\nram distributed $__NX_RFB_U_DPREG_ {\n\toption \"MODE\" 0 {\n        cost 30;\n        widthscale 30;\n\t\tabits 5;\n\t\twidths 18 global;\n\t}\n\toption \"MODE\" 2 {\n        cost 50;\n        widthscale 30;\n\t\tabits 6;\n\t\twidths 18 global;\n\t}\n\toption \"MODE\" 3 {\n        cost 50;\n        widthscale 30;\n\t\tabits 5;\n\t\twidths 36 global;\n\t}\n    init no_undef;\n\n    port sw \"W\" {\n        clock anyedge;\n    }\n    port ar \"R\" {\n    }\n}\n\n# Single-port RAMs.\n# NX_RFB_U in mode 1 (SPREG)\n\nram distributed $__NX_RFB_U_SPREG_ {\n\tcost 30;\n    widthscale;\n    abits 5;\n    width 18;\n\tinit no_undef;\n\tport arsw \"RW\" {\n\t\tclock anyedge;\n\t}\n}\n\n# Single write dual read RAMs.\n# NX_RFB_U in mode 4 (NX_XRFB_2R_1W)\n\nram distributed $__NX_XRFB_2R_1W_ {\n\tcost 40;\n    widthscale 30;\n    abits 5;\n    width 18;\n\tinit no_undef;\n    port sw \"W\" {\n        clock anyedge;\n    }\n    port ar \"A\" {\n    }\n    port ar \"B\" {\n    }\n}\n",
         },
         "nexus": {
-            "arith_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2018  gatecat <gatecat@ds0.me>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_nexus_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 4;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\tfunction integer round_up2;\n\t\tinput integer N;\n\t\tbegin\n\t\t\tround_up2 = ((N + 1) / 2) * 2;\n\t\tend\n\tendfunction\n\n\tlocalparam Y_WIDTH2 = round_up2(Y_WIDTH);\n\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BX = B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2+1:0] FCO, Y1;\n\n\tgenvar i;\n\n\t// Carry feed-in\n\tCCU2 #(\n\t\t.INIT0(\"0xFFFF\"),\n\t\t.INIT1(\"0x00AA\"),\n\t\t.INJECT(\"NO\")\n\t) ccu2c_i (\n\t\t.A0(1'b1), .B0(1'b1), .C0(1'b1), .D0(1'b1),\n\t\t.A1(CI), .B1(1'b1), .C1(1'b1), .D1(1'b1),\n\t\t.COUT(FCO[0])\n\t);\n\n\tgenerate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice\n\t\tCCU2 #(\n\t\t\t.INIT0(\"0x96AA\"),\n\t\t\t.INIT1(\"0x96AA\"),\n\t\t\t.INJECT(\"NO\")\n\t\t) ccu2c_i (\n\t\t\t.CIN(FCO[i]),\n\t\t\t.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),\n\t\t\t.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),\n\t\t\t.S0(Y[i]), .S1(Y1[i]),\n\t\t\t.COUT(FCO[i+2])\n\t\t);\n\n\t\tassign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));\n\t\tif (i+1 < Y_WIDTH) begin\n\t\t\tassign CO[i + 1] = (AA[i + 1] && BB[i + 1]) || ((Y[i + 1] ^ AA[i + 1] ^ BB[i + 1]) && (AA[i + 1] || BB[i + 1]));\n\t\t\tassign Y[i+1] = Y1[i];\n\t\tend\n\tend endgenerate\n\n\tassign X = AA ^ BB;\nendmodule\n",
-            "brams.txt": "ram block $__NX_DP16K_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 129;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\trdwr no_change;\n\t\tportoption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\tportoption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n}\n\nram block $__NX_PDP16K_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\toption \"SAME_CLOCK\" 1 cost 128;\n\toption \"SAME_CLOCK\" 0 cost 129;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\toption \"SAME_CLOCK\" 1 clock posedge \"C\";\n\t\toption \"SAME_CLOCK\" 0 clock posedge;\n\t\tclken;\n\t\tportoption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\tportoption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\toption \"SAME_CLOCK\" 1 clock posedge \"C\";\n\t\toption \"SAME_CLOCK\" 0 clock posedge;\n\t\tclken;\n\t\toption \"SAME_CLOCK\" 1 wrtrans all old;\n\t}\n}\n",
-            "brams_map.v": "module $__NX_DP16K_ (...);\n\nparameter INIT = 0;\n\nparameter PORT_A_OPTION_RESETMODE = \"SYNC\";\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_WR_BE_WIDTH = 2;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\nparameter PORT_B_OPTION_RESETMODE = \"SYNC\";\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_WR_BE_WIDTH = 2;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i;\n\tinit_slice = 0;\n\tfor (i = 0; i < 32; i = i + 1) begin\n\t\tinit_slice[i*10+:9] = INIT[(idx * 32 + i) * 9+:9];\n\tend\nendfunction\n\nwire [17:0] DOA;\nwire [17:0] DOB;\nwire [17:0] DIA = PORT_A_WR_DATA;\nwire [17:0] DIB = PORT_B_WR_DATA;\nwire [13:0] ADA;\nwire [13:0] ADB;\n\ngenerate\n\ncase(PORT_A_WIDTH)\n1: assign ADA = PORT_A_ADDR;\n2: assign ADA = {PORT_A_ADDR[13:1], 1'b1};\n4: assign ADA = {PORT_A_ADDR[13:2], 2'b11};\n9: assign ADA = {PORT_A_ADDR[13:3], 3'b111};\n18: assign ADA = {PORT_A_ADDR[13:4], 2'b11, PORT_A_WR_BE};\nendcase\n\ncase(PORT_B_WIDTH)\n1: assign ADB = PORT_B_ADDR;\n2: assign ADB = {PORT_B_ADDR[13:1], 1'b1};\n4: assign ADB = {PORT_B_ADDR[13:2], 2'b11};\n9: assign ADB = {PORT_B_ADDR[13:3], 3'b111};\n18: assign ADB = {PORT_B_ADDR[13:4], 2'b11, PORT_B_WR_BE};\nendcase\n\nendgenerate\n\nassign PORT_A_RD_DATA = DOA;\nassign PORT_B_RD_DATA = DOB;\n\nDP16K #(\n\t.INITVAL_00($sformatf(\"0x%080x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%080x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%080x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%080x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%080x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%080x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%080x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%080x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%080x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%080x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%080x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%080x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%080x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%080x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%080x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%080x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%080x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%080x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%080x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%080x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%080x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%080x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%080x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%080x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%080x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%080x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%080x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%080x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%080x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%080x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%080x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%080x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%080x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%080x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%080x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%080x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%080x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%080x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%080x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%080x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%080x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%080x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%080x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%080x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%080x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%080x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%080x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%080x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%080x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%080x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%080x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%080x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%080x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%080x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%080x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%080x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%080x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%080x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%080x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%080x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%080x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%080x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%080x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%080x\", init_slice('h3f))),\n\t.DATA_WIDTH_A($sformatf(\"X%0d\", PORT_A_WIDTH)),\n\t.DATA_WIDTH_B($sformatf(\"X%0d\", PORT_B_WIDTH)),\n\t.OUTREG_A(\"BYPASSED\"),\n\t.OUTREG_B(\"BYPASSED\"),\n\t.RESETMODE_A(PORT_A_OPTION_RESETMODE),\n\t.RESETMODE_B(PORT_B_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE_A(PORT_A_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE_B(PORT_B_OPTION_RESETMODE),\n\t.CSDECODE_A(\"111\"),\n\t.CSDECODE_B(\"111\"),\n\t.GSR(\"DISABLED\"),\n) _TECHMAP_REPLACE_ (\n\t.CLKA(PORT_A_CLK),\n\t.WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])),\n\t.CEA(PORT_A_CLK_EN),\n\t.RSTA(PORT_A_OPTION_RESETMODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t.CSA(3'b111),\n\t.DIA(DIA),\n\t.DOA(DOA),\n\t.ADA(ADA),\n\n\t.CLKB(PORT_B_CLK),\n\t.WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])),\n\t.CEB(PORT_B_CLK_EN),\n\t.RSTB(PORT_B_OPTION_RESETMODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t.CSB(3'b111),\n\t.ADB(ADB),\n\t.DIB(DIB),\n\t.DOB(DOB),\n);\n\nendmodule\n\n\nmodule $__NX_PDP16K_ (...);\n\nparameter INIT = 0;\nparameter OPTION_SAME_CLOCK = 1;\n\nparameter PORT_R_WIDTH = 36;\nparameter PORT_R_OPTION_RESETMODE = \"SYNC\";\n\ninput CLK_C;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\nparameter PORT_W_WIDTH = 36;\nparameter PORT_W_WR_EN_WIDTH = 4;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\nfunction [319:0] init_slice;\n\tinput integer idx;\n\tinteger i;\n\tinit_slice = 0;\n\tfor (i = 0; i < 32; i = i + 1) begin\n\t\tinit_slice[i*10+:9] = INIT[(idx * 32 + i) * 9+:9];\n\tend\nendfunction\n\nwire [35:0] DI = PORT_W_WR_DATA;\nwire [35:0] DO;\n\nassign PORT_R_RD_DATA = DO;\n\nwire [13:0] ADW;\nwire [13:0] ADR;\n\ngenerate\n\ncase (PORT_W_WIDTH)\n1: assign ADW = PORT_W_ADDR;\n2: assign ADW = {PORT_W_ADDR[13:1], 1'b1};\n4: assign ADW = {PORT_W_ADDR[13:2], 2'b11};\n9: assign ADW = {PORT_W_ADDR[13:3], 3'b111};\n18: assign ADW = {PORT_W_ADDR[13:4], 2'b11, PORT_W_WR_EN};\n36: assign ADW = {PORT_W_ADDR[13:5], 1'b1, PORT_W_WR_EN};\nendcase\n\ncase (PORT_R_WIDTH)\n1: assign ADR = PORT_R_ADDR;\n2: assign ADR = {PORT_R_ADDR[13:1], 1'b1};\n4: assign ADR = {PORT_R_ADDR[13:2], 2'b11};\n9: assign ADR = {PORT_R_ADDR[13:3], 3'b111};\n18: assign ADR = {PORT_R_ADDR[13:4], 4'b1111};\n36: assign ADR = {PORT_R_ADDR[13:5], 5'b11111};\nendcase\n\nif (OPTION_SAME_CLOCK) begin\n\nPDPSC16K #(\n\t.INITVAL_00($sformatf(\"0x%080x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%080x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%080x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%080x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%080x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%080x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%080x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%080x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%080x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%080x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%080x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%080x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%080x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%080x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%080x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%080x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%080x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%080x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%080x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%080x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%080x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%080x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%080x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%080x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%080x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%080x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%080x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%080x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%080x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%080x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%080x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%080x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%080x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%080x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%080x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%080x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%080x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%080x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%080x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%080x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%080x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%080x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%080x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%080x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%080x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%080x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%080x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%080x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%080x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%080x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%080x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%080x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%080x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%080x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%080x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%080x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%080x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%080x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%080x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%080x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%080x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%080x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%080x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%080x\", init_slice('h3f))),\n\t.DATA_WIDTH_W($sformatf(\"X%0d\", PORT_W_WIDTH)),\n\t.DATA_WIDTH_R($sformatf(\"X%0d\", PORT_R_WIDTH)),\n\t.OUTREG(\"BYPASSED\"),\n\t.RESETMODE(PORT_R_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE),\n\t.CSDECODE_W(\"111\"),\n\t.CSDECODE_R(\"111\"),\n\t.ECC(\"DISABLED\"),\n\t.GSR(\"DISABLED\"),\n) _TECHMAP_REPLACE_ (\n\t.CLK(CLK_C),\n\n\t.CEW(PORT_W_CLK_EN & (|PORT_W_WR_EN)),\n\t.CSW(3'b111),\n\t.ADW(ADW),\n\t.DI(DI),\n\n\t.CER(PORT_R_CLK_EN),\n\t.RST(PORT_R_OPTION_RESETMODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST),\n\t.CSR(3'b111),\n\t.ADR(ADR),\n\t.DO(DO),\n);\n\nend else begin\n\nPDP16K #(\n\t.INITVAL_00($sformatf(\"0x%080x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%080x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%080x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%080x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%080x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%080x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%080x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%080x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%080x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%080x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%080x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%080x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%080x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%080x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%080x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%080x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%080x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%080x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%080x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%080x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%080x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%080x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%080x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%080x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%080x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%080x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%080x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%080x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%080x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%080x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%080x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%080x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%080x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%080x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%080x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%080x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%080x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%080x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%080x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%080x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%080x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%080x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%080x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%080x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%080x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%080x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%080x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%080x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%080x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%080x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%080x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%080x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%080x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%080x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%080x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%080x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%080x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%080x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%080x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%080x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%080x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%080x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%080x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%080x\", init_slice('h3f))),\n\t.DATA_WIDTH_W($sformatf(\"X%0d\", PORT_W_WIDTH)),\n\t.DATA_WIDTH_R($sformatf(\"X%0d\", PORT_R_WIDTH)),\n\t.OUTREG(\"BYPASSED\"),\n\t.RESETMODE(PORT_R_OPTION_RESETMODE),\n\t.ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE),\n\t.CSDECODE_W(\"111\"),\n\t.CSDECODE_R(\"111\"),\n\t.ECC(\"DISABLED\"),\n\t.GSR(\"DISABLED\"),\n) _TECHMAP_REPLACE_ (\n\t.CLKW(PORT_W_CLK),\n\t.CEW(PORT_W_CLK_EN & (|PORT_W_WR_EN)),\n\t.CSW(3'b111),\n\t.ADW(ADW),\n\t.DI(DI),\n\n\t.CLKR(PORT_R_CLK),\n\t.CER(PORT_R_CLK_EN),\n\t.RST(PORT_R_OPTION_RESETMODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST),\n\t.CSR(3'b111),\n\t.ADR(ADR),\n\t.DO(DO),\n);\n\nend\n\nendgenerate\n\nendmodule\n",
-            "cells_map.v": "// Flipflop intermediate map level\nmodule \\$__FF_NOLSR (input D, C, E, output Q);\n\tparameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n\twire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n\tgenerate\n\t\tif (_TECHMAP_WIREINIT_Q_ === 1'b1)\n\t\t\tFD1P3JX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(1'b0), .Q(Q));\n\t\telse\n\t\t\tFD1P3IX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(1'b0), .Q(Q));\n\tendgenerate\nendmodule\n\nmodule \\$__FF_SYNCLSR (input D, C, E, R, output Q);\n\tparameter SR_VAL = 1'b0;\n\tparameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n\twire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n\twire Ci, Ei, Ri, Rg, Dd;\n\tgenerate\n\t\tif (SR_VAL)\n\t\t\tFD1P3JX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));\n\t\telse\n\t\t\tFD1P3IX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));\n\tendgenerate\nendmodule\n\nmodule \\$__FF_ASYNCLSR (input D, C, E, R, output Q);\n\tparameter SR_VAL = 1'b0;\n\tparameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n\twire _TECHMAP_REMOVEINIT_Q_ = (_TECHMAP_WIREINIT_Q_ === 1'bx || _TECHMAP_WIREINIT_Q_ === SR_VAL);\n\twire Ci, Ei, Ri, Rg, Dd;\n\tgenerate\n\t\tif (SR_VAL)\n\t\t\tFD1P3BX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));\n\t\telse\n\t\t\tFD1P3DX #(.GSR(\"DISABLED\")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));\n\tendgenerate\nendmodule\n\n\nmodule  \\$_DFF_P_ (input D, C, output Q); \\$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(1'b1), .Q(Q)); endmodule\n\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q); \\$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(E), .Q(Q)); endmodule\n\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); \\$__FF_ASYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); \\$__FF_ASYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\n\nmodule  \\$_SDFF_PP0_ (input D, C, R, output Q); \\$__FF_SYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\nmodule  \\$_SDFF_PP1_ (input D, C, R, output Q); \\$__FF_SYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule\n\nmodule  \\$_DFFE_PP0P_ (input D, C, E, R, output Q); \\$__FF_ASYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\nmodule  \\$_DFFE_PP1P_ (input D, C, E, R, output Q); \\$__FF_ASYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\n\nmodule  \\$_SDFFE_PP0P_ (input D, C, E, R, output Q); \\$__FF_SYNCLSR #(0)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\nmodule  \\$_SDFFE_PP1P_ (input D, C, E, R, output Q); \\$__FF_SYNCLSR #(1)  _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\t\tif (LUT == 2'b01)\n\t\t\t\tINV _TECHMAP_REPLACE_ (.A(A[0]), .Z(Y));\n\t\t\telse\n\t\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\", {{8{LUT[1]}}, {8{LUT[0]}}}))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t\t.D(A[0]));\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tlocalparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};\n\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\",  INIT))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t.C(A[0]), .D(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tlocalparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};\n\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\", INIT))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t.B(A[0]), .C(A[1]), .D(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tLUT4 #(.INIT($sformatf(\"0x%04x\", LUT))) _TECHMAP_REPLACE_ (.Z(Y),\n\t\t\t\t.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\t\tend else\n\t\tif (WIDTH == 5) begin\n\t\t\tWIDEFN9 #(\n\t\t\t\t.INIT0($sformatf(\"0x%04x\", LUT[15:0 ])),\n\t\t\t\t.INIT1($sformatf(\"0x%04x\", LUT[31:16])),\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.A0(A[0]), .B0(A[1]), .C0(A[2]), .D0(A[3]),\n\t\t\t\t.A1(A[0]), .B1(A[1]), .C1(A[2]), .D1(A[3]),\n\t\t\t\t.SEL(A[4]), .Z(Y)\n\t\t\t);\n\t\tend\n\tendgenerate\nendmodule\n`endif\n",
             "cells_sim.v": "(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n\tparameter INIT = \"0x0000\";\n`include \"parse_init.vh\"\n\tlocalparam initp = parse_init(INIT);\n\twire [7:0] s3 = D ?     initp[15:8] :    initp[7:0];\n\twire [3:0] s2 = C ?       s3[ 7:4]  :       s3[3:0];\n\twire [1:0] s1 = B ?       s2[ 3:2]  :       s2[1:0];\n\tassign Z =      A ?          s1[1]  :         s1[0];\n\n\t// Per-input delay differences are considered 'interconnect'\n\t// so not known yet\n\tspecify\n\t\t(A => Z) = 233;\n\t\t(B => Z) = 233;\n\t\t(C => Z) = 233;\n\t\t(D => Z) = 233;\n\tendspecify\n\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n//   cost of 5-input LUTs and is not intended to be instantiated\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input SEL, D, C, B, A, output Z);\n\tspecify\n\t\t(SEL => Z) = 171;\n\t\t(D => Z) = 303;\n\t\t(C => Z) = 311;\n\t\t(B => Z) = 309;\n\t\t(A => Z) = 306;\n\tendspecify\nendmodule\n\n// Two LUT4s and MUX2\nmodule WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);\n\tparameter INIT0 = \"0x0000\";\n\tparameter INIT1 = \"0x0000\";\n\twire z0, z1;\n\tLUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));\n\tLUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));\n\tassign Z = SEL ? z1 : z0;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule INV(input A, output Z);\n\tassign Z = !A;\n\n\tspecify\n\t\t(A => Z) = 10;\n\tendspecify\nendmodule\n\n// Bidirectional IO buffer\nmodule BB(input T, I, output O,\n\t(* iopad_external_pin *) inout B);\n\tassign B = T ? 1'bz : I;\n\tassign O = B;\nendmodule\n\n// Input buffer\nmodule IB(\n\t(* iopad_external_pin *) input I,\n\toutput O);\n\tassign O = I;\nendmodule\n\n// Output buffer\nmodule OB(input I,\n\t(* iopad_external_pin *) output O);\n\tassign O = I;\nendmodule\n\n// Output buffer with tristate\nmodule OBZ(input I, T,\n\t(* iopad_external_pin *) output O);\n\tassign O = T ? 1'bz : I;\nendmodule\n\n// Constants\nmodule VLO(output Z);\n\tassign Z = 1'b0;\nendmodule\n\nmodule VHI(output Z);\n\tassign Z = 1'b1;\nendmodule\n\n// Vendor flipflops\n// (all have active high clock, enable and set/reset - use INV to invert)\n\n// Async preset\n(* abc9_box, lib_whitebox *)\nmodule FD1P3BX(input D, CK, SP, PD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b1;\n\talways @(posedge CK or posedge PD)\n\t\tif (PD)\n\t\t\tQ <= 1'b1;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(PD, posedge CK, 224);\n`ifndef YOSYS\n\t\tif (PD) (posedge CLK => (Q : 1)) = 0;\n`else\n\t\tif (PD) (PD => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!PD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// Async clear\n(* abc9_box, lib_whitebox *)\nmodule FD1P3DX(input D, CK, SP, CD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b0;\n\talways @(posedge CK or posedge CD)\n\t\tif (CD)\n\t\t\tQ <= 1'b0;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(CD, posedge CK, 224);\n`ifndef YOSYS\n\t\tif (CD) (posedge CLK => (Q : 0)) = 0;\n`else\n\t\tif (CD) (CD => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!CD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// Sync clear\n(* abc9_flop, lib_whitebox *)\nmodule FD1P3IX(input D, CK, SP, CD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b0;\n\talways @(posedge CK)\n\t\tif (CD)\n\t\t\tQ <= 1'b0;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(CD, posedge CK, 224);\n\t\tif (!CD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// Sync preset\n(* abc9_flop, lib_whitebox *)\nmodule FD1P3JX(input D, CK, SP, PD, output reg Q);\n\tparameter GSR = \"DISABLED\";\n\tinitial Q = 1'b1;\n\talways @(posedge CK)\n\t\tif (PD)\n\t\t\tQ <= 1'b1;\n\t\telse if (SP)\n\t\t\tQ <= D;\n\tspecify\n\t\t$setup(D, posedge CK, 0);\n\t\t$setup(SP, posedge CK, 212);\n\t\t$setup(PD, posedge CK, 224);\n\t\tif (!PD && SP) (posedge CK => (Q : D)) = 336;\n\tendspecify\nendmodule\n\n// LUT4 with LUT3 tap for CCU2 use only\n(* lib_whitebox *)\nmodule LUT4_3(input A, B, C, D, output Z, Z3);\n\tparameter INIT = \"0x0000\";\n`include \"parse_init.vh\"\n\tlocalparam initp = parse_init(INIT);\n\twire [7:0] s3 = D ?     initp[15:8] :     initp[7:0];\n\twire [3:0] s2 = C ?        s3[ 7:4] :        s3[3:0];\n\twire [1:0] s1 = B ?        s2[ 3:2] :        s2[1:0];\n\tassign Z =      A ?           s1[1] :          s1[0];\n\n\twire [3:0] s2_3 = C ?   initp[ 7:4] :     initp[3:0];\n\twire [1:0] s1_3 = B ?    s2_3[ 3:2] :      s2_3[1:0];\n\tassign Z3 =       A ?       s1_3[1] :        s1_3[0];\n\nendmodule\n\n// Carry primitive (incoporating two LUTs)\n(* abc9_box, lib_whitebox *)\nmodule CCU2(\n\t(* abc9_carry *) input CIN,\n\tinput A1, B1, C1, D1, A0, B0, C0, D0,\n\toutput S1, S0,\n\t(* abc9_carry *) output COUT);\n\tparameter INJECT = \"YES\";\n\tparameter INIT0 = \"0x0000\";\n\tparameter INIT1 = \"0x1111\";\n\n\tlocalparam inject_p = (INJECT == \"YES\") ? 1'b1 : 1'b0;\n\n\twire LUT3_0, LUT4_0, LUT3_1, LUT4_1, carry_0;\n\tLUT4_3 #(.INIT(INIT0)) lut0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0), .Z3(LUT3_0));\n\tLUT4_3 #(.INIT(INIT1)) lut1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1), .Z3(LUT3_1));\n\n\tassign S0 = LUT4_0 ^ (CIN & ~inject_p);\n\tassign carry_0 = LUT4_0 ? CIN : (LUT3_0 & ~inject_p);\n\tassign S1 = LUT4_1 ^ (carry_0 & ~inject_p);\n\tassign COUT = LUT4_1 ? carry_0 : (LUT3_1 & ~inject_p);\n\n\tspecify\n\t\t(A0 => S0) = 233;\n\t\t(B0 => S0) = 233;\n\t\t(C0 => S0) = 233;\n\t\t(D0 => S0) = 233;\n\t\t(CIN => S0) = 228;\n\t\t(A0 => S1) = 481;\n\t\t(B0 => S1) = 481;\n\t\t(C0 => S1) = 481;\n\t\t(D0 => S1) = 481;\n\t\t(A1 => S1) = 233;\n\t\t(B1 => S1) = 233;\n\t\t(C1 => S1) = 233;\n\t\t(D1 => S1) = 233;\n\t\t(CIN => S1) = 307;\n\t\t(A0 => COUT) = 347;\n\t\t(B0 => COUT) = 347;\n\t\t(C0 => COUT) = 347;\n\t\t(D0 => COUT) = 347;\n\t\t(A1 => COUT) = 347;\n\t\t(B1 => COUT) = 347;\n\t\t(C1 => COUT) = 347;\n\t\t(D1 => COUT) = 347;\n\t\t(CIN => COUT) = 59;\n\tendspecify\n\nendmodule\n\n// Packed flipflop\nmodule OXIDE_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter REGDDR = \"DISABLED\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (REGDDR == \"ENABLED\") begin\n\t\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\t\talways @(posedge muxclk, negedge muxclk, posedge muxlsr)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend else begin\n\t\t\t\talways @(posedge muxclk, negedge muxclk)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend\n\t\tend else begin\n\t\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend else begin\n\t\t\t\talways @(posedge muxclk)\n\t\t\t\t\tif (muxlsr)\n\t\t\t\t\t\tQ <= srval;\n\t\t\t\t\telse if (muxce)\n\t\t\t\t\t\tQ <= DI;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n// Packed combinational logic (for post-pnr sim)\nmodule OXIDE_COMB(\n\tinput A, B, C, D, // LUT inputs\n\tinput SEL, // mux select input\n\tinput F1, // output from LUT 1 for mux\n\tinput FCI, // carry input\n\tinput WAD0, WAD1, WAD2, WAD3, // LUTRAM write address inputs\n\tinput WD, // LUTRAM write data input\n\tinput WCK, WRE, // LUTRAM write clock and enable\n\toutput F, // LUT/carry output\n\toutput OFX // mux output\n);\n\tparameter MODE = \"LOGIC\"; // LOGIC, CCU2, DPRAM\n\tparameter [15:0] INIT = 16'h0000;\n\tparameter INJECT = \"YES\";\n\n\tlocalparam inject_p = (INJECT == \"YES\") ? 1'b1 : 1'b0;\n\n\treg [15:0] lut = INIT;\n\n\twire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];\n\twire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];\n\twire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];\n\twire Z =        A ?          s1[1] :         s1[0];\n\n\twire [3:0] s2_3 = C ?   INIT[ 7:4] :     INIT[3:0];\n\twire [1:0] s1_3 = B ?   s2_3[ 3:2] :     s2_3[1:0];\n\twire Z3 =         A ?      s1_3[1] :       s1_3[0];\n\n\tgenerate\n\t\tif (MODE == \"DPRAM\") begin\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tlut[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\tend\n\t\tif (MODE == \"CCU2\") begin\n\t\t\tassign F = Z ^ (FCI & ~inject_p);\n\t\t\tassign FCO = Z ? FCI : (Z3 & ~inject_p);\n\t\tend else begin\n\t\t\tassign F = Z;\n\t\tend\n\tendgenerate\n\n\tassign OFX = SEL ? F1 : F;\n\nendmodule\n\n// LUTRAM\nmodule DPR16X4(\n\tinput [3:0] RAD, DI, WAD,\n\tinput WRE, WCK,\n\toutput [3:0] DO\n);\n\tparameter INITVAL = \"0x0000000000000000\";\n`include \"parse_init.vh\"\n\tlocalparam [63:0] parsed_init = parse_init_64(INITVAL);\n\n\treg [3:0] mem[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i++)\n\t\t\tmem[i] = parsed_init[i * 4 +: 4];\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tmem[WAD] <= DI;\n\tassign DO = mem[RAD];\nendmodule\n\n// Used for all the DSP models to reduce duplication\nmodule OXIDE_DSP_REG #(\n\tparameter W = 18,\n\tparameter USED = \"REGISTER\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput CLK, CE, RST,\n\tinput [W-1:0] D,\n\toutput reg [W-1:0] Q\n);\n\tgenerate\n\t\tif (USED == \"BYPASS\")\n\t\t\talways @* Q = D;\n\t\telse if (USED == \"REGISTER\") begin\n\t\t\tinitial Q = 0;\n\t\t\tif (RESETMODE == \"ASYNC\")\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif (RST)\n\t\t\t\t\t\tQ <= 0;\n\t\t\t\t\telse if (CE)\n\t\t\t\t\t\tQ <= D;\n\t\t\t\tend\n\t\t\telse if (RESETMODE == \"SYNC\")\n\t\t\t\talways @(posedge CLK) begin\n\t\t\t\t\tif (RST)\n\t\t\t\t\t\tQ <= 0;\n\t\t\t\t\telse if (CE)\n\t\t\t\t\t\tQ <= D;\n\t\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\nmodule OXIDE_DSP_SIM #(\n\t// User facing parameters\n\tparameter REGINPUTA = \"BYPASS\",\n\tparameter REGINPUTB = \"BYPASS\",\n\tparameter REGINPUTC = \"BYPASS\",\n\tparameter REGADDSUB = \"BYPASS\",\n\tparameter REGLOADC = \"BYPASS\",\n\tparameter REGLOADC2 = \"BYPASS\",\n\tparameter REGCIN = \"BYPASS\",\n\tparameter REGPIPELINE = \"BYPASS\",\n\tparameter REGOUTPUT = \"BYPASS\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\",\n\t// Internally used parameters\n\tparameter A_WIDTH = 36,\n\tparameter B_WIDTH = 36,\n\tparameter C_WIDTH = 36,\n\tparameter Z_WIDTH = 72,\n\tparameter PREADD_USED = 0,\n\tparameter ADDSUB_USED = 0\n) (\n\tinput [A_WIDTH-1:0] A,\n\tinput [B_WIDTH-1:0] B,\n\tinput [C_WIDTH-1:0] C,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput SIGNEDC,\n\tinput CIN,\n\tinput LOADC,\n\tinput ADDSUB,\n\tinput CLK,\n\tinput CEA, CEB, CEC, CEPIPE, CECTRL, CECIN, CEOUT,\n\tinput RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,\n\toutput wire [Z_WIDTH-1:0] Z\n);\n\t\n\tlocalparam M_WIDTH = (A_WIDTH+B_WIDTH);\n\n\t/******** REGISTERS ********/\n\n\twire [M_WIDTH-1:0] pipe_d, pipe_q;\n\twire [Z_WIDTH-1:0] z_d;\n\n\twire [A_WIDTH-1:0] a_r;\n\twire [B_WIDTH-1:0] b_r;\n\twire [C_WIDTH-1:0] c_r, c_r2;\n\twire asgd_r, bsgd_r, csgd_r, csgd_r2;\n\n\twire addsub_r, addsub_r2, cin_r, cin_r2, sgd_r, sgd_r2;\n\twire loadc_r, loadc_r2;\n\n\tOXIDE_DSP_REG #(A_WIDTH+1, REGINPUTA, RESETMODE) a_reg(CLK, CEA, RSTA, {SIGNEDA, A}, {asgd_r, a_r});\n\tOXIDE_DSP_REG #(B_WIDTH+1, REGINPUTB, RESETMODE) b_reg(CLK, CEB, RSTB, {SIGNEDB, B}, {bsgd_r, b_r});\n\tOXIDE_DSP_REG #(C_WIDTH+1, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNEDC, C}, {csgd_r, c_r});\n\n\tOXIDE_DSP_REG #(M_WIDTH, REGPIPELINE, RESETMODE) pipe_reg(CLK, CEPIPE, RSTPIPE, pipe_d, pipe_q);\n\n\tOXIDE_DSP_REG #(2, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNEDA, ADDSUB}, {sgd_r, addsub_r});\n\tOXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);\n\tOXIDE_DSP_REG #(2, REGPIPELINE, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});\n\tOXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);\n\n\tOXIDE_DSP_REG #(1, REGCIN, RESETMODE) cin_reg(CLK, CECIN, RSTCIN, CIN, cin_r);\n\tOXIDE_DSP_REG #(1, REGPIPELINE, RESETMODE) cin2_reg(CLK, CECIN, RSTCIN, cin_r, cin_r2);\n\n\tOXIDE_DSP_REG #(C_WIDTH+1, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});\n\n\tOXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);\n\n\t/******** PREADDER ********/\n\n\twire [B_WIDTH-1:0] mult_b;\n\twire mult_b_sgd;\n\n\tgenerate\n\t\tif (PREADD_USED) begin\n\t\t\tassign mult_b = (b_r + c_r);\n\t\t\tassign mult_b_sgd = (bsgd_r | csgd_r);\n\t\tend else begin\n\t\t\tassign mult_b = b_r;\n\t\t\tassign mult_b_sgd = bsgd_r;\n\t\tend\n\tendgenerate\n\n\t/******** MULTIPLIER ********/\n\n\t// sign extend operands if needed\n\twire [M_WIDTH-1:0] mult_a_ext = {{(M_WIDTH-A_WIDTH){asgd_r ? a_r[A_WIDTH-1] : 1'b0}}, a_r};\n\twire [M_WIDTH-1:0] mult_b_ext = {{(M_WIDTH-B_WIDTH){mult_b_sgd ? mult_b[B_WIDTH-1] : 1'b0}}, mult_b};\n\n\twire [M_WIDTH-1:0] mult_m = mult_a_ext * mult_b_ext;\n\n\t/******** ACCUMULATOR ********/\n\n\twire [Z_WIDTH-1:0] m_ext;\n\n\tgenerate\n\t\tif (ADDSUB_USED) begin\n\t\t\tassign pipe_d = mult_m;\n\t\t\tassign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};\n\t\t\tassign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);  \n\t\tend else begin\n\t\t\tassign z_d = mult_m;\n\t\tend\n\tendgenerate\n\n\nendmodule\n\nmodule MULT9X9 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [8:0] A,\n\tinput [8:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [17:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(9),\n\t\t.B_WIDTH(9),\n\t\t.Z_WIDTH(18),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULT18X18 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [17:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [35:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(18),\n\t\t.Z_WIDTH(36),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULT18X36 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [35:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [53:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(36),\n\t\t.Z_WIDTH(54),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULT36X36 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [35:0] A,\n\tinput [35:0] B,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [71:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(36),\n\t\t.B_WIDTH(36),\n\t\t.Z_WIDTH(72),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTPREADD9X9 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [8:0] A,\n\tinput [8:0] B,\n\tinput [8:0] C,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput CEC,\n\tinput RSTC,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput SIGNEDC,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [17:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(9),\n\t\t.B_WIDTH(9),\n\t\t.C_WIDTH(9),\n\t\t.Z_WIDTH(18),\n\t\t.PREADD_USED(1),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTPREADD18X18 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [17:0] B,\n\tinput [17:0] C,\n\tinput CLK,\n\tinput CEA,\n\tinput RSTA,\n\tinput CEB,\n\tinput RSTB,\n\tinput CEC,\n\tinput RSTC,\n\tinput SIGNEDA,\n\tinput SIGNEDB,\n\tinput SIGNEDC,\n\tinput RSTOUT,\n\tinput CEOUT,\n\toutput [35:0] Z\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(18),\n\t\t.C_WIDTH(18),\n\t\t.Z_WIDTH(36),\n\t\t.PREADD_USED(1),\n\t\t.ADDSUB_USED(0)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTADDSUB18X18 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGADDSUB = \"REGISTER\",\n\tparameter REGLOADC = \"REGISTER\",\n\tparameter REGLOADC2 = \"REGISTER\",\n\tparameter REGCIN = \"REGISTER\",\n\tparameter REGPIPELINE = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [17:0] A,\n\tinput [17:0] B,\n\tinput [53:0] C,\n    input CLK,\n    input CEA,\n    input RSTA,\n    input CEB,\n    input RSTB,\n    input CEC,\n    input RSTC,\n    input SIGNED,\n    input RSTPIPE,\n    input CEPIPE,\n    input RSTCTRL,\n    input CECTRL,\n    input RSTCIN,\n    input CECIN,\n    input LOADC,\n    input ADDSUB,\n    output [53:0] Z,\n    input RSTOUT,\n    input CEOUT,\n    input CIN\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGADDSUB(REGADDSUB),\n\t\t.REGLOADC(REGLOADC),\n\t\t.REGLOADC2(REGLOADC2),\n\t\t.REGCIN(REGCIN),\n\t\t.REGPIPELINE(REGPIPELINE),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(18),\n\t\t.B_WIDTH(18),\n\t\t.C_WIDTH(54),\n\t\t.Z_WIDTH(54),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(1)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),\n\t\t.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),\n\t\t.CECIN(CECIN), .RSTCIN(RSTCIN),\n\t\t.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),\n\t\t.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\n\nmodule MULTADDSUB36X36 #(\n\tparameter REGINPUTA = \"REGISTER\",\n\tparameter REGINPUTB = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGADDSUB = \"REGISTER\",\n\tparameter REGLOADC = \"REGISTER\",\n\tparameter REGLOADC2 = \"REGISTER\",\n\tparameter REGCIN = \"REGISTER\",\n\tparameter REGPIPELINE = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [35:0] A,\n\tinput [35:0] B,\n\tinput [107:0] C,\n    input CLK,\n    input CEA,\n    input RSTA,\n    input CEB,\n    input RSTB,\n    input CEC,\n    input RSTC,\n    input SIGNED,\n    input RSTPIPE,\n    input CEPIPE,\n    input RSTCTRL,\n    input CECTRL,\n    input RSTCIN,\n    input CECIN,\n    input LOADC,\n    input ADDSUB,\n    output [107:0] Z,\n    input RSTOUT,\n    input CEOUT,\n    input CIN\n);\n\tOXIDE_DSP_SIM #(\n\t\t.REGINPUTA(REGINPUTA),\n\t\t.REGINPUTB(REGINPUTB),\n\t\t.REGINPUTC(REGINPUTC),\n\t\t.REGADDSUB(REGADDSUB),\n\t\t.REGLOADC(REGLOADC),\n\t\t.REGLOADC2(REGLOADC2),\n\t\t.REGCIN(REGCIN),\n\t\t.REGPIPELINE(REGPIPELINE),\n\t\t.REGOUTPUT(REGOUTPUT),\n\t\t.GSR(GSR),\n\t\t.RESETMODE(RESETMODE),\n\n\t\t.A_WIDTH(36),\n\t\t.B_WIDTH(36),\n\t\t.C_WIDTH(108),\n\t\t.Z_WIDTH(108),\n\t\t.PREADD_USED(0),\n\t\t.ADDSUB_USED(1)\n\t) dsp_i (\n\t\t.A(A), .B(B), .C(C),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA), .RSTA(RSTA),\n\t\t.CEB(CEB), .RSTB(RSTB),\n\t\t.CEC(CEC), .RSTC(RSTC),\n\t\t.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),\n\t\t.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),\n\t\t.CECIN(CECIN), .RSTCIN(RSTCIN),\n\t\t.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),\n\t\t.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),\n\t\t.RSTOUT(RSTOUT), .CEOUT(CEOUT),\n\t\t.Z(Z)\n\t);\nendmodule\n\nmodule MULTADDSUB9X9WIDE #(\n\tparameter REGINPUTAB0 = \"REGISTER\",\n\tparameter REGINPUTAB1 = \"REGISTER\",\n\tparameter REGINPUTAB2 = \"REGISTER\",\n\tparameter REGINPUTAB3 = \"REGISTER\",\n\tparameter REGINPUTC = \"REGISTER\",\n\tparameter REGADDSUB = \"REGISTER\",\n\tparameter REGLOADC = \"REGISTER\",\n\tparameter REGLOADC2 = \"REGISTER\",\n\tparameter REGPIPELINE = \"REGISTER\",\n\tparameter REGOUTPUT = \"REGISTER\",\n\tparameter GSR = \"ENABLED\",\n\tparameter RESETMODE = \"SYNC\"\n) (\n\tinput [8:0] A0, B0, A1, B1, A2, B2, A3, B3,\n\tinput [53:0] C,\n\tinput CLK,\n\tinput CEA0A1, CEA2A3,\n\tinput RSTA0A1, RSTA2A3,\n\tinput CEB0B1, CEB2B3,\n\tinput RSTB0B1, RSTB2B3,\n\tinput CEC, RSTC,\n\tinput CECTRL, RSTCTRL,\n\tinput SIGNED,\n\tinput RSTPIPE, CEPIPE,\n\tinput RSTOUT, CEOUT,\n\tinput LOADC,\n\tinput [3:0] ADDSUB,\n\toutput [53:0] Z\n);\n\twire [17:0] m0, m1, m2, m3;\n\n\tlocalparam M_WIDTH = 18;\n\tlocalparam Z_WIDTH = 54;\n\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB0), .REGINPUTB(REGINPUTAB0), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_0 (\n\t\t.A(A0), .B(B0), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA0A1), .RSTA(RSTA0A1),\n\t\t.CEB(CEB0B1), .RSTB(RSTB0B1),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m0)\n\t);\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB1), .REGINPUTB(REGINPUTAB1), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_1 (\n\t\t.A(A1), .B(B1), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA0A1), .RSTA(RSTA0A1),\n\t\t.CEB(CEB0B1), .RSTB(RSTB0B1),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m1)\n\t);\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB2), .REGINPUTB(REGINPUTAB2), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_2 (\n\t\t.A(A2), .B(B2), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA2A3), .RSTA(RSTA2A3),\n\t\t.CEB(CEB2B3), .RSTB(RSTB2B3),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m2)\n\t);\n\tMULT9X9 #(\n\t\t.REGINPUTA(REGINPUTAB3), .REGINPUTB(REGINPUTAB3), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)\n\t) m9_3 (\n\t\t.A(A3), .B(B3), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),\n\t\t.CLK(CLK),\n\t\t.CEA(CEA2A3), .RSTA(RSTA2A3),\n\t\t.CEB(CEB2B3), .RSTB(RSTB2B3),\n\t\t.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),\n\t\t.Z(m3)\n\t);\n\n\twire [53:0] c_r, c_r2;\n\twire [3:0] addsub_r, addsub_r2;\n\twire sgd_r, sgd_r2, csgd_r, csgd_r2;\n\twire loadc_r, loadc_r2;\n\n\tOXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNED, ADDSUB}, {sgd_r, addsub_r});\n\tOXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});\n\n\tOXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);\n\tOXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);\n\n\tOXIDE_DSP_REG #(55, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNED, C}, {csgd_r, c_r});\n\tOXIDE_DSP_REG #(55, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});\n\n\n\twire [18:0] m0_ext, m1_ext, m2_ext, m3_ext;\n\n\tassign m0_ext = {sgd_r2 ? m0[M_WIDTH-1] : 1'b0, m0};\n\tassign m1_ext = {sgd_r2 ? m1[M_WIDTH-1] : 1'b0, m1};\n\tassign m2_ext = {sgd_r2 ? m2[M_WIDTH-1] : 1'b0, m2};\n\tassign m3_ext = {sgd_r2 ? m3[M_WIDTH-1] : 1'b0, m3};\n\n\twire [18:0] s0 = addsub_r2[2] ? (m0_ext - m1_ext) : (m0_ext + m1_ext);\n\twire [18:0] s1 = addsub_r2[3] ? (m2_ext - m3_ext) : (m2_ext + m3_ext);\n\n\twire [53:0] s0_ext = {{(54-19){sgd_r2 ? s0[18] : 1'b0}}, s0};\n\twire [53:0] s1_ext = {{(54-19){sgd_r2 ? s1[18] : 1'b0}}, s1};\n\n\twire [53:0] c_op = loadc_r2 ? c_r2 : Z;\n\n\t// The diagram in the docs is wrong! It is not two cascaded 2-input add/subs as shown,\n\t// but a three-input unit with negation controls on two inputs (i.e. addsub_r2[0]\n\t// negates s1 not (s1 +/- s0))\n\twire [53:0] z_d =  c_op + (addsub_r2[0] ? -s1_ext : s1_ext) + (addsub_r2[1] ? -s0_ext : s0_ext);\n\n\tOXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);\n\nendmodule\n",
             "cells_xtra.v": new URL("./share/nexus/cells_xtra.v", import.meta.url),
-            "dsp_map.v": "module \\$__NX_MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y);\n\n\tparameter A_WIDTH = 36;\n\tparameter B_WIDTH = 36;\n\tparameter Y_WIDTH = 72;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT36X36 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(A), .B(B),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n\nmodule \\$__NX_MUL36X18 (input [35:0] A, input [17:0] B, output [53:0] Y);\n\n\tparameter A_WIDTH = 36;\n\tparameter B_WIDTH = 18;\n\tparameter Y_WIDTH = 54;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT18X36 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(B), .B(A),\n\t\t.SIGNEDA(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n\nmodule \\$__NX_MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\n\tparameter A_WIDTH = 18;\n\tparameter B_WIDTH = 18;\n\tparameter Y_WIDTH = 36;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT18X18 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(A), .B(B),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n\nmodule \\$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);\n\n\tparameter A_WIDTH = 9;\n\tparameter B_WIDTH = 9;\n\tparameter Y_WIDTH = 18;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT9X9 #(\n\t\t.REGINPUTA(\"BYPASS\"),\n\t\t.REGINPUTB(\"BYPASS\"),\n\t\t.REGOUTPUT(\"BYPASS\")\n\t) _TECHMAP_REPLACE_ (\n\t\t.A(A), .B(B),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),\n\t\t.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),\n\t\t.Z(Y)\n\t);\nendmodule\n",
-            "latches_map.v": "module \\$_DLATCH_N_ (E, D, Q);\n  wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n  input E, D;\n  output Q = !E ? D : Q;\nendmodule\n\nmodule \\$_DLATCH_P_ (E, D, Q);\n  wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n  input E, D;\n  output Q = E ? D : Q;\nendmodule\n",
-            "lrams.txt": "ram huge $__NX_DPSC512K_ {\n\tabits 14;\n\twidth 32;\n\tbyte 8;\n\tcost 2048;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge \"C\";\n\t\tclken;\n\t\twrbe_separate;\n\t\trdwr no_change;\n\t\toption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\toption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\twrtrans all old;\n\t}\n}\n",
-            "lrams_map.v": "module $__NX_DPSC512K_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESETMODE = \"SYNC\";\n\ninput CLK_C;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [3:0] PORT_A_WR_BE;\ninput [31:0] PORT_A_WR_DATA;\noutput [31:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [3:0] PORT_B_WR_BE;\ninput [31:0] PORT_B_WR_DATA;\noutput [31:0] PORT_B_RD_DATA;\n\nfunction [5119:0] init_slice;\n\tinput integer idx;\n\tinteger i, j;\n\tinit_slice = 0;\n\tfor (i = 0; i < 128; i = i + 1) begin\n\t\tinit_slice[i*40+:32] = INIT[(idx * 128 + i) * 32+:32];\n\tend\nendfunction\n\nDPSC512K #(\n\t.INITVAL_00($sformatf(\"0x%01280x\", init_slice('h00))),\n\t.INITVAL_01($sformatf(\"0x%01280x\", init_slice('h01))),\n\t.INITVAL_02($sformatf(\"0x%01280x\", init_slice('h02))),\n\t.INITVAL_03($sformatf(\"0x%01280x\", init_slice('h03))),\n\t.INITVAL_04($sformatf(\"0x%01280x\", init_slice('h04))),\n\t.INITVAL_05($sformatf(\"0x%01280x\", init_slice('h05))),\n\t.INITVAL_06($sformatf(\"0x%01280x\", init_slice('h06))),\n\t.INITVAL_07($sformatf(\"0x%01280x\", init_slice('h07))),\n\t.INITVAL_08($sformatf(\"0x%01280x\", init_slice('h08))),\n\t.INITVAL_09($sformatf(\"0x%01280x\", init_slice('h09))),\n\t.INITVAL_0A($sformatf(\"0x%01280x\", init_slice('h0a))),\n\t.INITVAL_0B($sformatf(\"0x%01280x\", init_slice('h0b))),\n\t.INITVAL_0C($sformatf(\"0x%01280x\", init_slice('h0c))),\n\t.INITVAL_0D($sformatf(\"0x%01280x\", init_slice('h0d))),\n\t.INITVAL_0E($sformatf(\"0x%01280x\", init_slice('h0e))),\n\t.INITVAL_0F($sformatf(\"0x%01280x\", init_slice('h0f))),\n\t.INITVAL_10($sformatf(\"0x%01280x\", init_slice('h10))),\n\t.INITVAL_11($sformatf(\"0x%01280x\", init_slice('h11))),\n\t.INITVAL_12($sformatf(\"0x%01280x\", init_slice('h12))),\n\t.INITVAL_13($sformatf(\"0x%01280x\", init_slice('h13))),\n\t.INITVAL_14($sformatf(\"0x%01280x\", init_slice('h14))),\n\t.INITVAL_15($sformatf(\"0x%01280x\", init_slice('h15))),\n\t.INITVAL_16($sformatf(\"0x%01280x\", init_slice('h16))),\n\t.INITVAL_17($sformatf(\"0x%01280x\", init_slice('h17))),\n\t.INITVAL_18($sformatf(\"0x%01280x\", init_slice('h18))),\n\t.INITVAL_19($sformatf(\"0x%01280x\", init_slice('h19))),\n\t.INITVAL_1A($sformatf(\"0x%01280x\", init_slice('h1a))),\n\t.INITVAL_1B($sformatf(\"0x%01280x\", init_slice('h1b))),\n\t.INITVAL_1C($sformatf(\"0x%01280x\", init_slice('h1c))),\n\t.INITVAL_1D($sformatf(\"0x%01280x\", init_slice('h1d))),\n\t.INITVAL_1E($sformatf(\"0x%01280x\", init_slice('h1e))),\n\t.INITVAL_1F($sformatf(\"0x%01280x\", init_slice('h1f))),\n\t.INITVAL_20($sformatf(\"0x%01280x\", init_slice('h20))),\n\t.INITVAL_21($sformatf(\"0x%01280x\", init_slice('h21))),\n\t.INITVAL_22($sformatf(\"0x%01280x\", init_slice('h22))),\n\t.INITVAL_23($sformatf(\"0x%01280x\", init_slice('h23))),\n\t.INITVAL_24($sformatf(\"0x%01280x\", init_slice('h24))),\n\t.INITVAL_25($sformatf(\"0x%01280x\", init_slice('h25))),\n\t.INITVAL_26($sformatf(\"0x%01280x\", init_slice('h26))),\n\t.INITVAL_27($sformatf(\"0x%01280x\", init_slice('h27))),\n\t.INITVAL_28($sformatf(\"0x%01280x\", init_slice('h28))),\n\t.INITVAL_29($sformatf(\"0x%01280x\", init_slice('h29))),\n\t.INITVAL_2A($sformatf(\"0x%01280x\", init_slice('h2a))),\n\t.INITVAL_2B($sformatf(\"0x%01280x\", init_slice('h2b))),\n\t.INITVAL_2C($sformatf(\"0x%01280x\", init_slice('h2c))),\n\t.INITVAL_2D($sformatf(\"0x%01280x\", init_slice('h2d))),\n\t.INITVAL_2E($sformatf(\"0x%01280x\", init_slice('h2e))),\n\t.INITVAL_2F($sformatf(\"0x%01280x\", init_slice('h2f))),\n\t.INITVAL_30($sformatf(\"0x%01280x\", init_slice('h30))),\n\t.INITVAL_31($sformatf(\"0x%01280x\", init_slice('h31))),\n\t.INITVAL_32($sformatf(\"0x%01280x\", init_slice('h32))),\n\t.INITVAL_33($sformatf(\"0x%01280x\", init_slice('h33))),\n\t.INITVAL_34($sformatf(\"0x%01280x\", init_slice('h34))),\n\t.INITVAL_35($sformatf(\"0x%01280x\", init_slice('h35))),\n\t.INITVAL_36($sformatf(\"0x%01280x\", init_slice('h36))),\n\t.INITVAL_37($sformatf(\"0x%01280x\", init_slice('h37))),\n\t.INITVAL_38($sformatf(\"0x%01280x\", init_slice('h38))),\n\t.INITVAL_39($sformatf(\"0x%01280x\", init_slice('h39))),\n\t.INITVAL_3A($sformatf(\"0x%01280x\", init_slice('h3a))),\n\t.INITVAL_3B($sformatf(\"0x%01280x\", init_slice('h3b))),\n\t.INITVAL_3C($sformatf(\"0x%01280x\", init_slice('h3c))),\n\t.INITVAL_3D($sformatf(\"0x%01280x\", init_slice('h3d))),\n\t.INITVAL_3E($sformatf(\"0x%01280x\", init_slice('h3e))),\n\t.INITVAL_3F($sformatf(\"0x%01280x\", init_slice('h3f))),\n\t.INITVAL_40($sformatf(\"0x%01280x\", init_slice('h40))),\n\t.INITVAL_41($sformatf(\"0x%01280x\", init_slice('h41))),\n\t.INITVAL_42($sformatf(\"0x%01280x\", init_slice('h42))),\n\t.INITVAL_43($sformatf(\"0x%01280x\", init_slice('h43))),\n\t.INITVAL_44($sformatf(\"0x%01280x\", init_slice('h44))),\n\t.INITVAL_45($sformatf(\"0x%01280x\", init_slice('h45))),\n\t.INITVAL_46($sformatf(\"0x%01280x\", init_slice('h46))),\n\t.INITVAL_47($sformatf(\"0x%01280x\", init_slice('h47))),\n\t.INITVAL_48($sformatf(\"0x%01280x\", init_slice('h48))),\n\t.INITVAL_49($sformatf(\"0x%01280x\", init_slice('h49))),\n\t.INITVAL_4A($sformatf(\"0x%01280x\", init_slice('h4a))),\n\t.INITVAL_4B($sformatf(\"0x%01280x\", init_slice('h4b))),\n\t.INITVAL_4C($sformatf(\"0x%01280x\", init_slice('h4c))),\n\t.INITVAL_4D($sformatf(\"0x%01280x\", init_slice('h4d))),\n\t.INITVAL_4E($sformatf(\"0x%01280x\", init_slice('h4e))),\n\t.INITVAL_4F($sformatf(\"0x%01280x\", init_slice('h4f))),\n\t.INITVAL_50($sformatf(\"0x%01280x\", init_slice('h50))),\n\t.INITVAL_51($sformatf(\"0x%01280x\", init_slice('h51))),\n\t.INITVAL_52($sformatf(\"0x%01280x\", init_slice('h52))),\n\t.INITVAL_53($sformatf(\"0x%01280x\", init_slice('h53))),\n\t.INITVAL_54($sformatf(\"0x%01280x\", init_slice('h54))),\n\t.INITVAL_55($sformatf(\"0x%01280x\", init_slice('h55))),\n\t.INITVAL_56($sformatf(\"0x%01280x\", init_slice('h56))),\n\t.INITVAL_57($sformatf(\"0x%01280x\", init_slice('h57))),\n\t.INITVAL_58($sformatf(\"0x%01280x\", init_slice('h58))),\n\t.INITVAL_59($sformatf(\"0x%01280x\", init_slice('h59))),\n\t.INITVAL_5A($sformatf(\"0x%01280x\", init_slice('h5a))),\n\t.INITVAL_5B($sformatf(\"0x%01280x\", init_slice('h5b))),\n\t.INITVAL_5C($sformatf(\"0x%01280x\", init_slice('h5c))),\n\t.INITVAL_5D($sformatf(\"0x%01280x\", init_slice('h5d))),\n\t.INITVAL_5E($sformatf(\"0x%01280x\", init_slice('h5e))),\n\t.INITVAL_5F($sformatf(\"0x%01280x\", init_slice('h5f))),\n\t.INITVAL_60($sformatf(\"0x%01280x\", init_slice('h60))),\n\t.INITVAL_61($sformatf(\"0x%01280x\", init_slice('h61))),\n\t.INITVAL_62($sformatf(\"0x%01280x\", init_slice('h62))),\n\t.INITVAL_63($sformatf(\"0x%01280x\", init_slice('h63))),\n\t.INITVAL_64($sformatf(\"0x%01280x\", init_slice('h64))),\n\t.INITVAL_65($sformatf(\"0x%01280x\", init_slice('h65))),\n\t.INITVAL_66($sformatf(\"0x%01280x\", init_slice('h66))),\n\t.INITVAL_67($sformatf(\"0x%01280x\", init_slice('h67))),\n\t.INITVAL_68($sformatf(\"0x%01280x\", init_slice('h68))),\n\t.INITVAL_69($sformatf(\"0x%01280x\", init_slice('h69))),\n\t.INITVAL_6A($sformatf(\"0x%01280x\", init_slice('h6a))),\n\t.INITVAL_6B($sformatf(\"0x%01280x\", init_slice('h6b))),\n\t.INITVAL_6C($sformatf(\"0x%01280x\", init_slice('h6c))),\n\t.INITVAL_6D($sformatf(\"0x%01280x\", init_slice('h6d))),\n\t.INITVAL_6E($sformatf(\"0x%01280x\", init_slice('h6e))),\n\t.INITVAL_6F($sformatf(\"0x%01280x\", init_slice('h6f))),\n\t.INITVAL_70($sformatf(\"0x%01280x\", init_slice('h70))),\n\t.INITVAL_71($sformatf(\"0x%01280x\", init_slice('h71))),\n\t.INITVAL_72($sformatf(\"0x%01280x\", init_slice('h72))),\n\t.INITVAL_73($sformatf(\"0x%01280x\", init_slice('h73))),\n\t.INITVAL_74($sformatf(\"0x%01280x\", init_slice('h74))),\n\t.INITVAL_75($sformatf(\"0x%01280x\", init_slice('h75))),\n\t.INITVAL_76($sformatf(\"0x%01280x\", init_slice('h76))),\n\t.INITVAL_77($sformatf(\"0x%01280x\", init_slice('h77))),\n\t.INITVAL_78($sformatf(\"0x%01280x\", init_slice('h78))),\n\t.INITVAL_79($sformatf(\"0x%01280x\", init_slice('h79))),\n\t.INITVAL_7A($sformatf(\"0x%01280x\", init_slice('h7a))),\n\t.INITVAL_7B($sformatf(\"0x%01280x\", init_slice('h7b))),\n\t.INITVAL_7C($sformatf(\"0x%01280x\", init_slice('h7c))),\n\t.INITVAL_7D($sformatf(\"0x%01280x\", init_slice('h7d))),\n\t.INITVAL_7E($sformatf(\"0x%01280x\", init_slice('h7e))),\n\t.INITVAL_7F($sformatf(\"0x%01280x\", init_slice('h7f))),\n\t.OUTREG_A(\"NO_REG\"),\n\t.OUTREG_B(\"NO_REG\"),\n\t.ECC_BYTE_SEL(\"BYTE_EN\"),\n\t.GSR(\"DISABLED\"),\n\t.RESETMODE(OPTION_RESETMODE),\n\t.ASYNC_RESET_RELEASE(OPTION_RESETMODE),\n) _TECHMAP_REPLACE_ (\n\t.CLK(CLK_C),\n\n\t.WEA(PORT_A_WR_EN),\n\t.CEA(PORT_A_CLK_EN),\n\t.RSTA(OPTION_RESETMODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t.CSA(1'b1),\n\t.ADA(PORT_A_ADDR),\n\t.BENA_N(~PORT_A_WR_BE),\n\t.DIA(PORT_A_WR_DATA),\n\t.DOA(PORT_A_RD_DATA),\n\n\t.WEB(PORT_B_WR_EN),\n\t.CEB(PORT_B_CLK_EN),\n\t.RSTB(OPTION_RESETMODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t.CSB(1'b1),\n\t.BENB_N(~PORT_B_WR_BE),\n\t.ADB(PORT_B_ADDR),\n\t.DIB(PORT_B_WR_DATA),\n\t.DOB(PORT_B_RD_DATA),\n);\n\nendmodule\n",
-            "lutrams.txt": "ram distributed $__NEXUS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
-            "lutrams_map.v": "module $__NEXUS_DPR16X4_ (...);\n\tparameter INIT = 64'b0;\n\n\tinput PORT_W_CLK;\n\tinput [3:0] PORT_W_ADDR;\n\tinput [3:0] PORT_W_WR_DATA;\n\tinput PORT_W_WR_EN;\n\n\tinput [3:0] PORT_R_ADDR;\n\toutput [3:0] PORT_R_RD_DATA;\n\n\tDPR16X4 #(\n\t\t.INITVAL($sformatf(\"0x%08x\", INIT))\n\t) _TECHMAP_REPLACE_ (\n\t\t.RAD(PORT_R_ADDR),\n\t\t.DO(PORT_R_RD_DATA),\n\n\t\t.WAD(PORT_W_ADDR),\n\t\t.DI(PORT_W_WR_DATA),\n\t\t.WCK(PORT_W_CLK),\n\t\t.WRE(PORT_W_WR_EN)\n\t);\nendmodule\n",
             "parse_init.vh": "function [15:0] parse_init;\n\tinput [((2+(16/4))*8)-1:0] init;\n\treg [7:0] c;\n\tinteger i;\n\tbegin\n\t\tfor (i = 0; i < (16/4); i = i + 1) begin\n\t\t\tc = init[(i * 8) +: 8];\n\t\t\tif (c >= \"0\" && c <= \"9\")\n\t\t\t\tparse_init[(i * 4) +: 4] = (c - \"0\");\n\t\t\telse if (c >= \"A\" && c <= \"F\")\n\t\t\t\tparse_init[(i * 4) +: 4] = (c - \"A\") + 10;\n\t\t\telse if (c >= \"a\" && c <= \"f\")\n\t\t\t\tparse_init[(i * 4) +: 4] = (c - \"a\") + 10;\n\t\tend\n\tend\nendfunction\n\nfunction [63:0] parse_init_64;\n\tinput [((2+(64/4))*8)-1:0] init;\n\treg [7:0] c;\n\tinteger i;\n\tbegin\n\t\tfor (i = 0; i < (64/4); i = i + 1) begin\n\t\t\tc = init[(i * 8) +: 8];\n\t\t\tif (c >= \"0\" && c <= \"9\")\n\t\t\t\tparse_init_64[(i * 4) +: 4] = (c - \"0\");\n\t\t\telse if (c >= \"A\" && c <= \"F\")\n\t\t\t\tparse_init_64[(i * 4) +: 4] = (c - \"A\") + 10;\n\t\t\telse if (c >= \"a\" && c <= \"f\")\n\t\t\t\tparse_init_64[(i * 4) +: 4] = (c - \"a\") + 10;\n\t\tend\n\tend\nendfunction\n",
         },
         "pmux2mux.v": "module \\$pmux (A, B, S, Y);\n\nwire [1023:0] _TECHMAP_DO_ = \"proc; clean\";\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\n\nalways @* begin\n\tY <= A;\n\tfor (i = 0; i < S_WIDTH; i=i+1)\n\t\tif (S[i]) Y <= B[WIDTH*i +: WIDTH];\nend\n\nendmodule\n",