@yowasp/yosys 0.52.893 → 0.54.929
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/gen/resources-yosys.js +18 -18
- package/gen/yosys.core.wasm +0 -0
- package/package.json +1 -1
package/gen/resources-yosys.js
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@@ -51,7 +51,7 @@ export const filesystem = {
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"cells_ff.vh": "// Diamond flip-flops\nmodule FD1P3AX(input D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3AY(input D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule FD1S3AX(input D, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule\nmodule FD1S3AY(input D, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule\nmodule FD1S3BX(input PD, D, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule\nmodule FD1S3DX(input CD, D, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule\nmodule FD1S3IX(input CD, D, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule\nmodule FD1S3JX(input PD, D, CK, output Q); parameter GSR = \"ENABLED\"; TRELLIS_FF #(.GSR(GSR), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule\n\n// TODO: Diamond latches\n// module FL1P3AY(); endmodule\n// module FL1P3AZ(); endmodule\n// module FL1P3BX(); endmodule\n// module FL1P3DX(); endmodule\n// module FL1P3IY(); endmodule\n// module FL1P3JY(); endmodule\n// module FL1S3AX(); endmodule\n// module FL1S3AY(); endmodule\n\n// Diamond I/O registers\nmodule IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"input\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\n\nmodule OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule\nmodule OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = \"ENABLED\"; (* syn_useioff, ioff_dir=\"output\" *) TRELLIS_FF #(.GSR(GSR), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule\n\n// TODO: Diamond I/O latches\n// module IFS1S1B(input PD, D, SCLK, output Q); endmodule\n// module IFS1S1D(input CD, D, SCLK, output Q); endmodule\n// module IFS1S1I(input PD, D, SCLK, output Q); endmodule\n// module IFS1S1J(input CD, D, SCLK, output Q); endmodule\n",
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"cells_io.vh": "// Diamond I/O buffers\nmodule IB ((* iopad_external_pin *) input I, output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"INPUT\")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule IBPU ((* iopad_external_pin *) input I, output O); (* PULLMODE=\"UP\" *) TRELLIS_IO #(.DIR(\"INPUT\")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule IBPD ((* iopad_external_pin *) input I, output O); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"INPUT\")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule\nmodule OB (input I, (* iopad_external_pin *) output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule\nmodule OBZ (input I, T, (* iopad_external_pin *) output O); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBZPU(input I, T, (* iopad_external_pin *) output O); (* PULLMODE=\"UP\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBZPD(input I, T, (* iopad_external_pin *) output O); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule\nmodule OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule\nmodule BB (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"NONE\" *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule BBPU (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"UP\" *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule BBPD (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE=\"DOWN\" *) TRELLIS_IO #(.DIR(\"BIDIR\")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule\nmodule ILVDS(input A, AN, (* iopad_external_pin *) output Z ); TRELLIS_IO #(.DIR(\"INPUT\")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule\nmodule OLVDS(input A, (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR(\"OUTPUT\")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule\n",
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"cells_map.v": "module \\$_DFF_N_ (input D, C, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n else\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n endgenerate\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule \\$_DFF_P_ (input D, C, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n else\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));\n endgenerate\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule \\$_DFFE_NN_ (input D, C, E, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n else\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n endgenerate\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule \\$_DFFE_PN_ (input D, C, E, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n else\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n endgenerate\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule \\$_DFFE_NP_ (input D, C, E, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n else\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n endgenerate\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule \\$_DFFE_PP_ (input D, C, E, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n else\n TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));\n endgenerate\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\nendmodule\n\nmodule \\$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\nmodule \\$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR(\"AUTO\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMUX(\"LSR\"), .REGSET(\"SET\"), .SRMODE(\"LSR_OVER_CE\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule\n\nmodule \\$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"1\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\nmodule \\$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"INV\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"INV\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\nmodule \\$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR(\"DISABLED\"), .CEMUX(\"CE\"), .CLKMUX(\"CLK\"), .LSRMODE(\"PRLD\"), .LSRMUX(\"LSR\"), .REGSET(\"RESET\"), .SRMODE(\"ASYNC\")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n parameter WIDTH = 0;\n parameter LUT = 0;\n\n (* force_downto *)\n input [WIDTH-1:0] A;\n output Y;\n\n generate\n if (WIDTH == 1) begin\n localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};\n LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));\n end else\n if (WIDTH == 2) begin\n localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};\n LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1]));\n end else\n if (WIDTH == 3) begin\n localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};\n LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y),\n .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2]));\n end else\n if (WIDTH == 4) begin\n LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n `ifndef NO_PFUMUX\n end else\n if (WIDTH == 5) begin\n wire f0, f1;\n LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));\n end else\n if (WIDTH == 6) begin\n wire f0, f1, f2, f3, g0, g1;\n LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));\n end else\n if (WIDTH == 7) begin\n wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;\n LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\n PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));\n PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));\n PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));\n PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));\n L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));\n L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));\n L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));\n `endif\n end else begin\n wire _TECHMAP_FAIL_ = 1;\n end\n endgenerate\nendmodule\n`endif\n",
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"cells_sim.v": "// ---------------------------------------\n\n(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n parameter [15:0] INIT = 16'h0000;\n wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];\n wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];\n wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];\n assign Z = A ? s1[1] : s1[0];\n specify\n (A => Z) = 141;\n (B => Z) = 275;\n (C => Z) = 379;\n (D => Z) = 379;\n endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n// cost of 5-input LUTs and is not intended to be instantiated\n// LUT5 = 2x LUT4 + PFUMX\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input M0, D, C, B, A, output Z);\n specify\n (M0 => Z) = 151;\n (D => Z) = 239;\n (C => Z) = 373;\n (B => Z) = 477;\n (A => Z) = 477;\n endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n// of 6-input LUTs and is not intended to be instantiated\n// LUT6 = 2x LUT5 + MUX2\n(* abc9_lut=4 *)\nmodule \\$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);\n specify\n (M1 => Z) = 148;\n (M0 => Z) = 292;\n (D => Z) = 380;\n (C => Z) = 514;\n (B => Z) = 618;\n (A => Z) = 618;\n endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n// of 7-input LUTs and is not intended to be instantiated\n// LUT7 = 2x LUT6 + MUX2\n(* abc9_lut=8 *)\nmodule \\$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);\n specify\n (M2 => Z) = 148;\n (M1 => Z) = 289;\n (M0 => Z) = 433;\n (D => Z) = 521;\n (C => Z) = 655;\n (B => Z) = 759;\n (A => Z) = 759;\n endspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule L6MUX21 (input D0, D1, SD, output Z);\n\tassign Z = SD ? D1 : D0;\n\tspecify\n\t\t(D0 => Z) = 140;\n\t\t(D1 => Z) = 141;\n\t\t(SD => Z) = 148;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule CCU2C(\n\t(* abc9_carry *)\n\tinput CIN,\n\tinput A0, B0, C0, D0, A1, B1, C1, D1,\n\toutput S0, S1,\n\t(* abc9_carry *)\n\toutput COUT\n);\n\tparameter [15:0] INIT0 = 16'h0000;\n\tparameter [15:0] INIT1 = 16'h0000;\n\tparameter INJECT1_0 = \"YES\";\n\tparameter INJECT1_1 = \"YES\";\n\n\t// First half\n\twire LUT4_0, LUT2_0;\n\tLUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));\n\tLUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));\n\twire gated_cin_0 = (INJECT1_0 == \"YES\") ? 1'b0 : CIN;\n\tassign S0 = LUT4_0 ^ gated_cin_0;\n\n\twire gated_lut2_0 = (INJECT1_0 == \"YES\") ? 1'b0 : LUT2_0;\n\twire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);\n\n\t// Second half\n\twire LUT4_1, LUT2_1;\n\tLUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));\n\tLUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));\n\twire gated_cin_1 = (INJECT1_1 == \"YES\") ? 1'b0 : cout_0;\n\tassign S1 = LUT4_1 ^ gated_cin_1;\n\n\twire gated_lut2_1 = (INJECT1_1 == \"YES\") ? 1'b0 : LUT2_1;\n\tassign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);\n\n\tspecify\n\t\t(A0 => S0) = 379;\n\t\t(B0 => S0) = 379;\n\t\t(C0 => S0) = 275;\n\t\t(D0 => S0) = 141;\n\t\t(CIN => S0) = 257;\n\t\t(A0 => S1) = 630;\n\t\t(B0 => S1) = 630;\n\t\t(C0 => S1) = 526;\n\t\t(D0 => S1) = 392;\n\t\t(A1 => S1) = 379;\n\t\t(B1 => S1) = 379;\n\t\t(C1 => S1) = 275;\n\t\t(D1 => S1) = 141;\n\t\t(CIN => S1) = 273;\n\t\t(A0 => COUT) = 516;\n\t\t(B0 => COUT) = 516;\n\t\t(C0 => COUT) = 412;\n\t\t(D0 => COUT) = 278;\n\t\t(A1 => COUT) = 516;\n\t\t(B1 => COUT) = 516;\n\t\t(C1 => COUT) = 412;\n\t\t(D1 => COUT) = 278;\n\t\t(CIN => COUT) = 43;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_RAM16X2 (\n\tinput DI0, DI1,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\tinput RAD0, RAD1, RAD2, RAD3,\n\toutput DO0, DO1\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter INITVAL_0 = 16'h0000;\n\tparameter INITVAL_1 = 16'h0000;\n\n\treg [1:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= {INITVAL_1[i], INITVAL_0[i]};\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};\n\n\tassign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule PFUMX (input ALUT, BLUT, C0, output Z);\n\tassign Z = C0 ? ALUT : BLUT;\n\tspecify\n\t\t(ALUT => Z) = 98;\n\t\t(BLUT => Z) = 98;\n\t\t(C0 => Z) = 151;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule TRELLIS_DPR16X4 (\n\tinput [3:0] DI,\n\tinput [3:0] WAD,\n\tinput WRE,\n\tinput WCK,\n\tinput [3:0] RAD,\n\toutput [3:0] DO\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter [63:0] INITVAL = 64'h0000000000000000;\n\n\treg [3:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= INITVAL[4*i +: 4];\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[WAD] <= DI;\n\n\tassign DO = mem[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* abc9_box, lib_whitebox *)\nmodule DPR16X4C (\n\t\tinput [3:0] DI,\n\t\tinput WCK, WRE,\n\t\tinput [3:0] RAD,\n\t\tinput [3:0] WAD,\n\t\toutput [3:0] DO\n);\n\t// For legacy Lattice compatibility, INITIVAL is a hex\n\t// string rather than a numeric parameter\n\tparameter INITVAL = \"0x0000000000000000\";\n\n\tfunction [63:0] convert_initval;\n\t\tinput [143:0] hex_initval;\n\t\treg done;\n\t\treg [63:0] temp;\n\t\treg [7:0] char;\n\t\tinteger i;\n\t\tbegin\n\t\t\tdone = 1'b0;\n\t\t\ttemp = 0;\n\t\t\tfor (i = 0; i < 16; i = i + 1) begin\n\t\t\t\tif (!done) begin\n\t\t\t\t\tchar = hex_initval[8*i +: 8];\n\t\t\t\t\tif (char == \"x\") begin\n\t\t\t\t\t\tdone = 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (char >= \"0\" && char <= \"9\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = char - \"0\";\n\t\t\t\t\t\telse if (char >= \"A\" && char <= \"F\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"A\";\n\t\t\t\t\t\telse if (char >= \"a\" && char <= \"f\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"a\";\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tconvert_initval = temp;\n\t\tend\n\tendfunction\n\n\tlocalparam conv_initval = convert_initval(INITVAL);\n\n\treg [3:0] ram[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i = i + 1) begin\n\t\t\tram[i] <= conv_initval[4*i +: 4];\n\t\tend\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tram[WAD] <= DI;\n\n\tassign DO = ram[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* lib_whitebox *)\nmodule LUT2(input A, B, output Z);\n parameter [3:0] INIT = 4'h0;\n wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];\n assign Z = A ? s1[1] : s1[0];\nendmodule\n\n// ---------------------------------------\n\n`ifdef YOSYS\n(* abc9_flop=(SRMODE != \"ASYNC\"), abc9_box=(SRMODE == \"ASYNC\"), lib_whitebox *)\n`endif\nmodule TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend else begin\n\t\t\talways @(posedge muxclk)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend\n\tendgenerate\n\n\tspecify\n\t\t$setup(DI, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(CE, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(LSR, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(DI, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(CE, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(LSR, posedge CLK &&& CLKMUX != \"INV\", 0);\n`ifndef YOSYS\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX == \"INV\") (negedge CLK => (Q : srval)) = 0;\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX != \"INV\") (posedge CLK => (Q : srval)) = 0;\n`else\n\t\tif (SRMODE == \"ASYNC\" && muxlsr) (LSR => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!muxlsr && muxce && CLKMUX == \"INV\") (negedge CLK => (Q : DI)) = 0;\n\t\tif (!muxlsr && muxce && CLKMUX != \"INV\") (posedge CLK => (Q : DI)) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* keep *)\nmodule TRELLIS_IO(\n\t(* iopad_external_pin *)\n\tinout B,\n\tinput I,\n\tinput T,\n\toutput O\n);\n\tparameter DIR = \"INPUT\";\n\treg T_pd;\n\talways @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;\n\n\tgenerate\n\t\tif (DIR == \"INPUT\") begin\n\t\t\tassign B = 1'bz;\n\t\t\tassign O = B;\n\t\tend else if (DIR == \"OUTPUT\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = 1'bx;\n\t\tend else if (DIR == \"BIDIR\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = B;\n\t\tend else begin\n\t\t\tERROR_UNKNOWN_IO_MODE error();\n\t\tend\n\tendgenerate\n\nendmodule\n\n// ---------------------------------------\n\nmodule INV(input A, output Z);\n\tassign Z = !A;\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_COMB(\n\tinput A, B, C, D, M,\n\tinput FCI, F1, FXA, FXB,\n\tinput WD,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\toutput F, FCO, OFX\n);\n\tparameter MODE = \"LOGIC\";\n\tparameter INITVAL = 16'h0;\n\tparameter CCU2_INJECT1 = \"NO\";\n\tparameter WREMUX = \"WRE\";\n\tparameter IS_Z1 = 1'b0;\n\n\tgenerate\n\t\tif (MODE == \"LOGIC\") begin: mode_logic\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));\n\t\tend else if (MODE == \"CCU2\") begin: mode_ccu2\n\t\t\twire l4o, l2o;\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));\n\t\t\tLUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));\n\t\t\twire gated_cin_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : FCI;\n\t\t\tassign F = l4o ^ gated_cin_0;\n\t\t\twire gated_lut2_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : l2o;\n\t\t\twire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);\n\t\tend else if (MODE == \"DPRAM\") begin: mode_dpram\n\t\t\treg [15:0] ram = INITVAL;\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tram[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\t\tassign F = ram[{A, C, B, D}];\n\t\tend else begin\n\t\t\t$error(\"unsupported COMB mode %s\", MODE);\n\t\tend\n\n \t\tif (IS_Z1)\n\t\t\tL6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));\n\t\telse\n\t\t\tPFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));\n\tendgenerate\n\nendmodule\n\n(* blackbox *)\nmodule DP16KD(\n input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,\n input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,\n input CEA, OCEA, CLKA, WEA, RSTA,\n input CSA2, CSA1, CSA0,\n output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,\n\n input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,\n input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,\n input CEB, OCEB, CLKB, WEB, RSTB,\n input CSB2, CSB1, CSB0,\n output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0\n);\n\tparameter DATA_WIDTH_A = 18;\n\tparameter DATA_WIDTH_B = 18;\n\n\tparameter REGMODE_A = \"NOREG\";\n\tparameter REGMODE_B = \"NOREG\";\n\n\tparameter RESETMODE = \"SYNC\";\n\tparameter ASYNC_RESET_RELEASE = \"SYNC\";\n\n\tparameter CSDECODE_A = \"0b000\";\n\tparameter CSDECODE_B = \"0b000\";\n\n\tparameter WRITEMODE_A = \"NORMAL\";\n\tparameter WRITEMODE_B = \"NORMAL\";\n\n\tparameter DIA17MUX = \"DIA17\";\n\tparameter DIA16MUX = \"DIA16\";\n\tparameter DIA15MUX = \"DIA15\";\n\tparameter DIA14MUX = \"DIA14\";\n\tparameter DIA13MUX = \"DIA13\";\n\tparameter DIA12MUX = \"DIA12\";\n\tparameter DIA11MUX = \"DIA11\";\n\tparameter DIA10MUX = \"DIA10\";\n\tparameter DIA9MUX = \"DIA9\";\n\tparameter DIA8MUX = \"DIA8\";\n\tparameter DIA7MUX = \"DIA7\";\n\tparameter DIA6MUX = \"DIA6\";\n\tparameter DIA5MUX = \"DIA5\";\n\tparameter DIA4MUX = \"DIA4\";\n\tparameter DIA3MUX = \"DIA3\";\n\tparameter DIA2MUX = \"DIA2\";\n\tparameter DIA1MUX = \"DIA1\";\n\tparameter DIA0MUX = \"DIA0\";\n\tparameter ADA13MUX = \"ADA13\";\n\tparameter ADA12MUX = \"ADA12\";\n\tparameter ADA11MUX = \"ADA11\";\n\tparameter ADA10MUX = \"ADA10\";\n\tparameter ADA9MUX = \"ADA9\";\n\tparameter ADA8MUX = \"ADA8\";\n\tparameter ADA7MUX = \"ADA7\";\n\tparameter ADA6MUX = \"ADA6\";\n\tparameter ADA5MUX = \"ADA5\";\n\tparameter ADA4MUX = \"ADA4\";\n\tparameter ADA3MUX = \"ADA3\";\n\tparameter ADA2MUX = \"ADA2\";\n\tparameter ADA1MUX = \"ADA1\";\n\tparameter ADA0MUX = \"ADA0\";\n\tparameter CEAMUX = \"CEA\";\n\tparameter OCEAMUX = \"OCEA\";\n\tparameter CLKAMUX = \"CLKA\";\n\tparameter WEAMUX = \"WEA\";\n\tparameter RSTAMUX = \"RSTA\";\n\tparameter CSA2MUX = \"CSA2\";\n\tparameter CSA1MUX = \"CSA1\";\n\tparameter CSA0MUX = \"CSA0\";\n\tparameter DOA17MUX = \"DOA17\";\n\tparameter DOA16MUX = \"DOA16\";\n\tparameter DOA15MUX = \"DOA15\";\n\tparameter DOA14MUX = \"DOA14\";\n\tparameter DOA13MUX = \"DOA13\";\n\tparameter DOA12MUX = \"DOA12\";\n\tparameter DOA11MUX = \"DOA11\";\n\tparameter DOA10MUX = \"DOA10\";\n\tparameter DOA9MUX = \"DOA9\";\n\tparameter DOA8MUX = \"DOA8\";\n\tparameter DOA7MUX = \"DOA7\";\n\tparameter DOA6MUX = \"DOA6\";\n\tparameter DOA5MUX = \"DOA5\";\n\tparameter DOA4MUX = \"DOA4\";\n\tparameter DOA3MUX = \"DOA3\";\n\tparameter DOA2MUX = \"DOA2\";\n\tparameter DOA1MUX = \"DOA1\";\n\tparameter DOA0MUX = \"DOA0\";\n\tparameter DIB17MUX = \"DIB17\";\n\tparameter DIB16MUX = \"DIB16\";\n\tparameter DIB15MUX = \"DIB15\";\n\tparameter DIB14MUX = \"DIB14\";\n\tparameter DIB13MUX = \"DIB13\";\n\tparameter DIB12MUX = \"DIB12\";\n\tparameter DIB11MUX = \"DIB11\";\n\tparameter DIB10MUX = \"DIB10\";\n\tparameter DIB9MUX = \"DIB9\";\n\tparameter DIB8MUX = \"DIB8\";\n\tparameter DIB7MUX = \"DIB7\";\n\tparameter DIB6MUX = \"DIB6\";\n\tparameter DIB5MUX = \"DIB5\";\n\tparameter DIB4MUX = \"DIB4\";\n\tparameter DIB3MUX = \"DIB3\";\n\tparameter DIB2MUX = \"DIB2\";\n\tparameter DIB1MUX = \"DIB1\";\n\tparameter DIB0MUX = \"DIB0\";\n\tparameter ADB13MUX = \"ADB13\";\n\tparameter ADB12MUX = \"ADB12\";\n\tparameter ADB11MUX = \"ADB11\";\n\tparameter ADB10MUX = \"ADB10\";\n\tparameter ADB9MUX = \"ADB9\";\n\tparameter ADB8MUX = \"ADB8\";\n\tparameter ADB7MUX = \"ADB7\";\n\tparameter ADB6MUX = \"ADB6\";\n\tparameter ADB5MUX = \"ADB5\";\n\tparameter ADB4MUX = \"ADB4\";\n\tparameter ADB3MUX = \"ADB3\";\n\tparameter ADB2MUX = \"ADB2\";\n\tparameter ADB1MUX = \"ADB1\";\n\tparameter ADB0MUX = \"ADB0\";\n\tparameter CEBMUX = \"CEB\";\n\tparameter OCEBMUX = \"OCEB\";\n\tparameter CLKBMUX = \"CLKB\";\n\tparameter WEBMUX = \"WEB\";\n\tparameter RSTBMUX = \"RSTB\";\n\tparameter CSB2MUX = \"CSB2\";\n\tparameter CSB1MUX = \"CSB1\";\n\tparameter CSB0MUX = \"CSB0\";\n\tparameter DOB17MUX = \"DOB17\";\n\tparameter DOB16MUX = \"DOB16\";\n\tparameter DOB15MUX = \"DOB15\";\n\tparameter DOB14MUX = \"DOB14\";\n\tparameter DOB13MUX = \"DOB13\";\n\tparameter DOB12MUX = \"DOB12\";\n\tparameter DOB11MUX = \"DOB11\";\n\tparameter DOB10MUX = \"DOB10\";\n\tparameter DOB9MUX = \"DOB9\";\n\tparameter DOB8MUX = \"DOB8\";\n\tparameter DOB7MUX = \"DOB7\";\n\tparameter DOB6MUX = \"DOB6\";\n\tparameter DOB5MUX = \"DOB5\";\n\tparameter DOB4MUX = \"DOB4\";\n\tparameter DOB3MUX = \"DOB3\";\n\tparameter DOB2MUX = \"DOB2\";\n\tparameter DOB1MUX = \"DOB1\";\n\tparameter DOB0MUX = \"DOB0\";\n\n\tparameter WID = 0;\n\n\tparameter GSR = \"ENABLED\";\n\n\tparameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_DATA = \"STATIC\";\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
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"cells_sim.v": "// ---------------------------------------\n\n(* abc9_lut=1, lib_whitebox *)\nmodule LUT4(input A, B, C, D, output Z);\n parameter [15:0] INIT = 16'h0000;\n wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];\n wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];\n wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];\n assign Z = A ? s1[1] : s1[0];\n specify\n (A => Z) = 141;\n (B => Z) = 275;\n (C => Z) = 379;\n (D => Z) = 379;\n endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n// cost of 5-input LUTs and is not intended to be instantiated\n// LUT5 = 2x LUT4 + PFUMX\n(* abc9_lut=2 *)\nmodule \\$__ABC9_LUT5 (input M0, D, C, B, A, output Z);\n specify\n (M0 => Z) = 151;\n (D => Z) = 239;\n (C => Z) = 373;\n (B => Z) = 477;\n (A => Z) = 477;\n endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n// of 6-input LUTs and is not intended to be instantiated\n// LUT6 = 2x LUT5 + MUX2\n(* abc9_lut=4 *)\nmodule \\$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);\n specify\n (M1 => Z) = 148;\n (M0 => Z) = 292;\n (D => Z) = 380;\n (C => Z) = 514;\n (B => Z) = 618;\n (A => Z) = 618;\n endspecify\nendmodule\n\n// This is a placeholder for ABC9 to extract the area/delay\n// of 7-input LUTs and is not intended to be instantiated\n// LUT7 = 2x LUT6 + MUX2\n(* abc9_lut=8 *)\nmodule \\$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);\n specify\n (M2 => Z) = 148;\n (M1 => Z) = 289;\n (M0 => Z) = 433;\n (D => Z) = 521;\n (C => Z) = 655;\n (B => Z) = 759;\n (A => Z) = 759;\n endspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule L6MUX21 (input D0, D1, SD, output Z);\n\tassign Z = SD ? D1 : D0;\n\tspecify\n\t\t(D0 => Z) = 140;\n\t\t(D1 => Z) = 141;\n\t\t(SD => Z) = 148;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule CCU2C(\n\t(* abc9_carry *)\n\tinput CIN,\n\tinput A0, B0, C0, D0, A1, B1, C1, D1,\n\toutput S0, S1,\n\t(* abc9_carry *)\n\toutput COUT\n);\n\tparameter [15:0] INIT0 = 16'h0000;\n\tparameter [15:0] INIT1 = 16'h0000;\n\tparameter INJECT1_0 = \"YES\";\n\tparameter INJECT1_1 = \"YES\";\n\n\t// First half\n\twire LUT4_0, LUT2_0;\n\tLUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));\n\tLUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));\n\twire gated_cin_0 = (INJECT1_0 == \"YES\") ? 1'b0 : CIN;\n\tassign S0 = LUT4_0 ^ gated_cin_0;\n\n\twire gated_lut2_0 = (INJECT1_0 == \"YES\") ? 1'b0 : LUT2_0;\n\twire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);\n\n\t// Second half\n\twire LUT4_1, LUT2_1;\n\tLUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));\n\tLUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));\n\twire gated_cin_1 = (INJECT1_1 == \"YES\") ? 1'b0 : cout_0;\n\tassign S1 = LUT4_1 ^ gated_cin_1;\n\n\twire gated_lut2_1 = (INJECT1_1 == \"YES\") ? 1'b0 : LUT2_1;\n\tassign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);\n\n\tspecify\n\t\t(A0 => S0) = 379;\n\t\t(B0 => S0) = 379;\n\t\t(C0 => S0) = 275;\n\t\t(D0 => S0) = 141;\n\t\t(CIN => S0) = 257;\n\t\t(A0 => S1) = 630;\n\t\t(B0 => S1) = 630;\n\t\t(C0 => S1) = 526;\n\t\t(D0 => S1) = 392;\n\t\t(A1 => S1) = 379;\n\t\t(B1 => S1) = 379;\n\t\t(C1 => S1) = 275;\n\t\t(D1 => S1) = 141;\n\t\t(CIN => S1) = 273;\n\t\t(A0 => COUT) = 516;\n\t\t(B0 => COUT) = 516;\n\t\t(C0 => COUT) = 412;\n\t\t(D0 => COUT) = 278;\n\t\t(A1 => COUT) = 516;\n\t\t(B1 => COUT) = 516;\n\t\t(C1 => COUT) = 412;\n\t\t(D1 => COUT) = 278;\n\t\t(CIN => COUT) = 43;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_RAM16X2 (\n\tinput DI0, DI1,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\tinput RAD0, RAD1, RAD2, RAD3,\n\toutput DO0, DO1\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter INITVAL_0 = 16'h0000;\n\tparameter INITVAL_1 = 16'h0000;\n\n\treg [1:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= {INITVAL_1[i], INITVAL_0[i]};\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};\n\n\tassign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule PFUMX (input ALUT, BLUT, C0, output Z);\n\tassign Z = C0 ? ALUT : BLUT;\n\tspecify\n\t\t(ALUT => Z) = 98;\n\t\t(BLUT => Z) = 98;\n\t\t(C0 => Z) = 151;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* abc9_box, lib_whitebox *)\nmodule TRELLIS_DPR16X4 (\n\tinput [3:0] DI,\n\tinput [3:0] WAD,\n\tinput WRE,\n\tinput WCK,\n\tinput [3:0] RAD,\n\toutput [3:0] DO\n);\n\tparameter WCKMUX = \"WCK\";\n\tparameter WREMUX = \"WRE\";\n\tparameter [63:0] INITVAL = 64'h0000000000000000;\n\n\treg [3:0] mem[15:0];\n\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tmem[i] <= INITVAL[4*i +: 4];\n\tend\n\n\twire muxwck = (WCKMUX == \"INV\") ? ~WCK : WCK;\n\n\treg muxwre;\n\talways @(*)\n\t\tcase (WREMUX)\n\t\t\t\"1\": muxwre = 1'b1;\n\t\t\t\"0\": muxwre = 1'b0;\n\t\t\t\"INV\": muxwre = ~WRE;\n\t\t\tdefault: muxwre = WRE;\n\t\tendcase\n\n\talways @(posedge muxwck)\n\t\tif (muxwre)\n\t\t\tmem[WAD] <= DI;\n\n\tassign DO = mem[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* abc9_box, lib_whitebox *)\nmodule DPR16X4C (\n\t\tinput [3:0] DI,\n\t\tinput WCK, WRE,\n\t\tinput [3:0] RAD,\n\t\tinput [3:0] WAD,\n\t\toutput [3:0] DO\n);\n\t// For legacy Lattice compatibility, INITIVAL is a hex\n\t// string rather than a numeric parameter\n\tparameter INITVAL = \"0x0000000000000000\";\n\n\tfunction [63:0] convert_initval;\n\t\tinput [143:0] hex_initval;\n\t\treg done;\n\t\treg [63:0] temp;\n\t\treg [7:0] char;\n\t\tinteger i;\n\t\tbegin\n\t\t\tdone = 1'b0;\n\t\t\ttemp = 0;\n\t\t\tfor (i = 0; i < 16; i = i + 1) begin\n\t\t\t\tif (!done) begin\n\t\t\t\t\tchar = hex_initval[8*i +: 8];\n\t\t\t\t\tif (char == \"x\") begin\n\t\t\t\t\t\tdone = 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (char >= \"0\" && char <= \"9\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = char - \"0\";\n\t\t\t\t\t\telse if (char >= \"A\" && char <= \"F\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"A\";\n\t\t\t\t\t\telse if (char >= \"a\" && char <= \"f\")\n\t\t\t\t\t\t\ttemp[4*i +: 4] = 10 + char - \"a\";\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tconvert_initval = temp;\n\t\tend\n\tendfunction\n\n\tlocalparam conv_initval = convert_initval(INITVAL);\n\n\treg [3:0] ram[0:15];\n\tinteger i;\n\tinitial begin\n\t\tfor (i = 0; i < 15; i = i + 1) begin\n\t\t\tram[i] <= conv_initval[4*i +: 4];\n\t\tend\n\tend\n\n\talways @(posedge WCK)\n\t\tif (WRE)\n\t\t\tram[WAD] <= DI;\n\n\tassign DO = ram[RAD];\n\n\tspecify\n\t\t// TODO\n\t\t(RAD *> DO) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n\n(* lib_whitebox *)\nmodule LUT2(input A, B, output Z);\n parameter [3:0] INIT = 4'h0;\n wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];\n assign Z = A ? s1[1] : s1[0];\nendmodule\n\n// ---------------------------------------\n\n`ifdef YOSYS\n(* abc9_flop=(SRMODE != \"ASYNC\"), abc9_box=(SRMODE == \"ASYNC\"), lib_whitebox *)\n`endif\nmodule TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);\n\tparameter GSR = \"ENABLED\";\n\tparameter [127:0] CEMUX = \"1\";\n\tparameter CLKMUX = \"CLK\";\n\tparameter LSRMUX = \"LSR\";\n\tparameter SRMODE = \"LSR_OVER_CE\";\n\tparameter REGSET = \"RESET\";\n\tparameter [127:0] LSRMODE = \"LSR\";\n\n\twire muxce;\n\tgenerate\n\t\tcase (CEMUX)\n\t\t\t\"1\": assign muxce = 1'b1;\n\t\t\t\"0\": assign muxce = 1'b0;\n\t\t\t\"INV\": assign muxce = ~CE;\n\t\t\tdefault: assign muxce = CE;\n\t\tendcase\n\tendgenerate\n\n\twire muxlsr = (LSRMUX == \"INV\") ? ~LSR : LSR;\n\twire muxclk = (CLKMUX == \"INV\") ? ~CLK : CLK;\n\twire srval;\n\tgenerate\n\t\tif (LSRMODE == \"PRLD\")\n\t\t\tassign srval = M;\n\t\telse\n\t\t\tassign srval = (REGSET == \"SET\") ? 1'b1 : 1'b0;\n\tendgenerate\n\n\tinitial Q = srval;\n\n\tgenerate\n\t\tif (SRMODE == \"ASYNC\") begin\n\t\t\talways @(posedge muxclk, posedge muxlsr)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend else begin\n\t\t\talways @(posedge muxclk)\n\t\t\t\tif (muxlsr)\n\t\t\t\t\tQ <= srval;\n\t\t\t\telse if (muxce)\n\t\t\t\t\tQ <= DI;\n\t\tend\n\tendgenerate\n\n\tspecify\n\t\t$setup(DI, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(CE, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(LSR, negedge CLK &&& CLKMUX == \"INV\", 0);\n\t\t$setup(DI, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(CE, posedge CLK &&& CLKMUX != \"INV\", 0);\n\t\t$setup(LSR, posedge CLK &&& CLKMUX != \"INV\", 0);\n`ifndef YOSYS\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX == \"INV\") (negedge CLK => (Q : srval)) = 0;\n\t\tif (SRMODE == \"ASYNC\" && muxlsr && CLKMUX != \"INV\") (posedge CLK => (Q : srval)) = 0;\n`else\n\t\tif (SRMODE == \"ASYNC\" && muxlsr) (LSR => Q) = 0; \t// Technically, this should be an edge sensitive path\n\t\t\t\t\t\t\t\t\t// but for facilitating a bypass box, let's pretend it's\n\t\t\t\t\t\t\t\t\t// a simple path\n`endif\n\t\tif (!muxlsr && muxce && CLKMUX == \"INV\") (negedge CLK => (Q : DI)) = 0;\n\t\tif (!muxlsr && muxce && CLKMUX != \"INV\") (posedge CLK => (Q : DI)) = 0;\n\tendspecify\nendmodule\n\n// ---------------------------------------\n(* keep *)\nmodule TRELLIS_IO(\n\t(* iopad_external_pin *)\n\tinout B,\n\tinput I,\n\tinput T,\n\toutput O\n);\n\tparameter DIR = \"INPUT\";\n\treg T_pd;\n\talways @(*) if (T === 1'bz) T_pd = 1'b0; else T_pd = T;\n\n\tgenerate\n\t\tif (DIR == \"INPUT\") begin\n\t\t\tassign B = 1'bz;\n\t\t\tassign O = B;\n\t\tend else if (DIR == \"OUTPUT\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = 1'bx;\n\t\tend else if (DIR == \"BIDIR\") begin\n\t\t\tassign B = T_pd ? 1'bz : I;\n\t\t\tassign O = B;\n\t\tend else begin\n\t\t\tERROR_UNKNOWN_IO_MODE error();\n\t\tend\n\tendgenerate\n\nendmodule\n\n// ---------------------------------------\n\nmodule INV(input A, output Z);\n\tassign Z = !A;\nendmodule\n\n// ---------------------------------------\n\nmodule TRELLIS_COMB(\n\tinput A, B, C, D, M,\n\tinput FCI, F1, FXA, FXB,\n\tinput WD,\n\tinput WAD0, WAD1, WAD2, WAD3,\n\tinput WRE, WCK,\n\toutput F, FCO, OFX\n);\n\tparameter MODE = \"LOGIC\";\n\tparameter INITVAL = 16'h0;\n\tparameter CCU2_INJECT1 = \"NO\";\n\tparameter WREMUX = \"WRE\";\n\tparameter IS_Z1 = 1'b0;\n\n\tgenerate\n\t\tif (MODE == \"LOGIC\") begin: mode_logic\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));\n\t\tend else if (MODE == \"CCU2\") begin: mode_ccu2\n\t\t\twire l4o, l2o;\n\t\t\tLUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));\n\t\t\tLUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));\n\t\t\twire gated_cin_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : FCI;\n\t\t\tassign F = l4o ^ gated_cin_0;\n\t\t\twire gated_lut2_0 = (CCU2_INJECT1 == \"YES\") ? 1'b0 : l2o;\n\t\t\twire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);\n\t\tend else if (MODE == \"DPRAM\") begin: mode_dpram\n\t\t\treg [15:0] ram = INITVAL;\n\t\t\talways @(posedge WCK)\n\t\t\t\tif (WRE)\n\t\t\t\t\tram[{WAD3, WAD2, WAD1, WAD0}] <= WD;\n\t\t\tassign F = ram[{A, C, B, D}];\n\t\tend else begin\n\t\t\t$error(\"unsupported COMB mode %s\", MODE);\n\t\tend\n\n \t\tif (IS_Z1)\n\t\t\tL6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));\n\t\telse\n\t\t\tPFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));\n\tendgenerate\n\nendmodule\n\n(* blackbox *)\nmodule DP16KD(\n input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,\n input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,\n input CEA, OCEA, CLKA, WEA, RSTA,\n input CSA2, CSA1, CSA0,\n output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,\n\n input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,\n input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,\n input CEB, OCEB, CLKB, WEB, RSTB,\n input CSB2, CSB1, CSB0,\n output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0\n);\n\tparameter DATA_WIDTH_A = 18;\n\tparameter DATA_WIDTH_B = 18;\n\n\tparameter REGMODE_A = \"NOREG\";\n\tparameter REGMODE_B = \"NOREG\";\n\n\tparameter RESETMODE = \"SYNC\";\n\tparameter ASYNC_RESET_RELEASE = \"SYNC\";\n\n\tparameter CSDECODE_A = \"0b000\";\n\tparameter CSDECODE_B = \"0b000\";\n\n\tparameter WRITEMODE_A = \"NORMAL\";\n\tparameter WRITEMODE_B = \"NORMAL\";\n\n\tparameter DIA17MUX = \"DIA17\";\n\tparameter DIA16MUX = \"DIA16\";\n\tparameter DIA15MUX = \"DIA15\";\n\tparameter DIA14MUX = \"DIA14\";\n\tparameter DIA13MUX = \"DIA13\";\n\tparameter DIA12MUX = \"DIA12\";\n\tparameter DIA11MUX = \"DIA11\";\n\tparameter DIA10MUX = \"DIA10\";\n\tparameter DIA9MUX = \"DIA9\";\n\tparameter DIA8MUX = \"DIA8\";\n\tparameter DIA7MUX = \"DIA7\";\n\tparameter DIA6MUX = \"DIA6\";\n\tparameter DIA5MUX = \"DIA5\";\n\tparameter DIA4MUX = \"DIA4\";\n\tparameter DIA3MUX = \"DIA3\";\n\tparameter DIA2MUX = \"DIA2\";\n\tparameter DIA1MUX = \"DIA1\";\n\tparameter DIA0MUX = \"DIA0\";\n\tparameter ADA13MUX = \"ADA13\";\n\tparameter ADA12MUX = \"ADA12\";\n\tparameter ADA11MUX = \"ADA11\";\n\tparameter ADA10MUX = \"ADA10\";\n\tparameter ADA9MUX = \"ADA9\";\n\tparameter ADA8MUX = \"ADA8\";\n\tparameter ADA7MUX = \"ADA7\";\n\tparameter ADA6MUX = \"ADA6\";\n\tparameter ADA5MUX = \"ADA5\";\n\tparameter ADA4MUX = \"ADA4\";\n\tparameter ADA3MUX = \"ADA3\";\n\tparameter ADA2MUX = \"ADA2\";\n\tparameter ADA1MUX = \"ADA1\";\n\tparameter ADA0MUX = \"ADA0\";\n\tparameter CEAMUX = \"CEA\";\n\tparameter OCEAMUX = \"OCEA\";\n\tparameter CLKAMUX = \"CLKA\";\n\tparameter WEAMUX = \"WEA\";\n\tparameter RSTAMUX = \"RSTA\";\n\tparameter CSA2MUX = \"CSA2\";\n\tparameter CSA1MUX = \"CSA1\";\n\tparameter CSA0MUX = \"CSA0\";\n\tparameter DOA17MUX = \"DOA17\";\n\tparameter DOA16MUX = \"DOA16\";\n\tparameter DOA15MUX = \"DOA15\";\n\tparameter DOA14MUX = \"DOA14\";\n\tparameter DOA13MUX = \"DOA13\";\n\tparameter DOA12MUX = \"DOA12\";\n\tparameter DOA11MUX = \"DOA11\";\n\tparameter DOA10MUX = \"DOA10\";\n\tparameter DOA9MUX = \"DOA9\";\n\tparameter DOA8MUX = \"DOA8\";\n\tparameter DOA7MUX = \"DOA7\";\n\tparameter DOA6MUX = \"DOA6\";\n\tparameter DOA5MUX = \"DOA5\";\n\tparameter DOA4MUX = \"DOA4\";\n\tparameter DOA3MUX = \"DOA3\";\n\tparameter DOA2MUX = \"DOA2\";\n\tparameter DOA1MUX = \"DOA1\";\n\tparameter DOA0MUX = \"DOA0\";\n\tparameter DIB17MUX = \"DIB17\";\n\tparameter DIB16MUX = \"DIB16\";\n\tparameter DIB15MUX = \"DIB15\";\n\tparameter DIB14MUX = \"DIB14\";\n\tparameter DIB13MUX = \"DIB13\";\n\tparameter DIB12MUX = \"DIB12\";\n\tparameter DIB11MUX = \"DIB11\";\n\tparameter DIB10MUX = \"DIB10\";\n\tparameter DIB9MUX = \"DIB9\";\n\tparameter DIB8MUX = \"DIB8\";\n\tparameter DIB7MUX = \"DIB7\";\n\tparameter DIB6MUX = \"DIB6\";\n\tparameter DIB5MUX = \"DIB5\";\n\tparameter DIB4MUX = \"DIB4\";\n\tparameter DIB3MUX = \"DIB3\";\n\tparameter DIB2MUX = \"DIB2\";\n\tparameter DIB1MUX = \"DIB1\";\n\tparameter DIB0MUX = \"DIB0\";\n\tparameter ADB13MUX = \"ADB13\";\n\tparameter ADB12MUX = \"ADB12\";\n\tparameter ADB11MUX = \"ADB11\";\n\tparameter ADB10MUX = \"ADB10\";\n\tparameter ADB9MUX = \"ADB9\";\n\tparameter ADB8MUX = \"ADB8\";\n\tparameter ADB7MUX = \"ADB7\";\n\tparameter ADB6MUX = \"ADB6\";\n\tparameter ADB5MUX = \"ADB5\";\n\tparameter ADB4MUX = \"ADB4\";\n\tparameter ADB3MUX = \"ADB3\";\n\tparameter ADB2MUX = \"ADB2\";\n\tparameter ADB1MUX = \"ADB1\";\n\tparameter ADB0MUX = \"ADB0\";\n\tparameter CEBMUX = \"CEB\";\n\tparameter OCEBMUX = \"OCEB\";\n\tparameter CLKBMUX = \"CLKB\";\n\tparameter WEBMUX = \"WEB\";\n\tparameter RSTBMUX = \"RSTB\";\n\tparameter CSB2MUX = \"CSB2\";\n\tparameter CSB1MUX = \"CSB1\";\n\tparameter CSB0MUX = \"CSB0\";\n\tparameter DOB17MUX = \"DOB17\";\n\tparameter DOB16MUX = \"DOB16\";\n\tparameter DOB15MUX = \"DOB15\";\n\tparameter DOB14MUX = \"DOB14\";\n\tparameter DOB13MUX = \"DOB13\";\n\tparameter DOB12MUX = \"DOB12\";\n\tparameter DOB11MUX = \"DOB11\";\n\tparameter DOB10MUX = \"DOB10\";\n\tparameter DOB9MUX = \"DOB9\";\n\tparameter DOB8MUX = \"DOB8\";\n\tparameter DOB7MUX = \"DOB7\";\n\tparameter DOB6MUX = \"DOB6\";\n\tparameter DOB5MUX = \"DOB5\";\n\tparameter DOB4MUX = \"DOB4\";\n\tparameter DOB3MUX = \"DOB3\";\n\tparameter DOB2MUX = \"DOB2\";\n\tparameter DOB1MUX = \"DOB1\";\n\tparameter DOB0MUX = \"DOB0\";\n\n\tparameter WID = 0;\n\n\tparameter GSR = \"ENABLED\";\n\n\tparameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_DATA = \"STATIC\";\nendmodule\n\n`ifndef NO_INCLUDES\n\n`include \"cells_ff.vh\"\n`include \"cells_io.vh\"\n\n`endif\n",
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"dsp_map.v": "module \\$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\n\tparameter A_WIDTH = 18;\n\tparameter B_WIDTH = 18;\n\tparameter Y_WIDTH = 36;\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\n\tMULT18X18D _TECHMAP_REPLACE_ (\n\t\t.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),\n\t\t.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),\n\t\t.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),\n\t\t.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),\n\n\t\t.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])\n\t);\nendmodule\n",
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"latches_map.v": "module \\$_DLATCH_N_ (E, D, Q);\n wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n input E, D;\n output Q = !E ? D : Q;\nendmodule\n\nmodule \\$_DLATCH_P_ (E, D, Q);\n wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n input E, D;\n output Q = E ? D : Q;\nendmodule\n",
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"lutrams.txt": "ram distributed $__TRELLIS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit any;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock anyedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
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@@ -78,12 +78,12 @@ export const filesystem = {
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"gate2lut.v": "(* techmap_celltype = \"$_NOT_\" *)\nmodule _90_lut_not (A, Y);\n input A;\n output Y;\n\n wire [`LUT_WIDTH-1:0] AA;\n assign AA = {A};\n\n \\$lut #(\n .WIDTH(`LUT_WIDTH),\n .LUT(4'b01)\n ) lut (\n .A(AA),\n .Y(Y)\n );\nendmodule\n\n(* techmap_celltype = \"$_OR_\" *)\nmodule _90_lut_or (A, B, Y);\n input A, B;\n output Y;\n\n wire [`LUT_WIDTH-1:0] AA;\n assign AA = {B, A};\n\n \\$lut #(\n .WIDTH(`LUT_WIDTH),\n .LUT(4'b1110)\n ) lut (\n .A(AA),\n .Y(Y)\n );\nendmodule\n\n(* techmap_celltype = \"$_AND_\" *)\nmodule _90_lut_and (A, B, Y);\n input A, B;\n output Y;\n\n wire [`LUT_WIDTH-1:0] AA;\n assign AA = {B, A};\n\n \\$lut #(\n .WIDTH(`LUT_WIDTH),\n .LUT(4'b1000)\n ) lut (\n .A(AA),\n .Y(Y)\n );\nendmodule\n\n(* techmap_celltype = \"$_XOR_\" *)\nmodule _90_lut_xor (A, B, Y);\n input A, B;\n output Y;\n\n wire [`LUT_WIDTH-1:0] AA;\n assign AA = {B, A};\n\n \\$lut #(\n .WIDTH(`LUT_WIDTH),\n .LUT(4'b0110)\n ) lut (\n .A(AA),\n .Y(Y)\n );\nendmodule\n\n(* techmap_celltype = \"$_MUX_\" *)\nmodule _90_lut_mux (A, B, S, Y);\n input A, B, S;\n output Y;\n\n wire [`LUT_WIDTH-1:0] AA;\n assign AA = {S, B, A};\n\n \\$lut #(\n .WIDTH(`LUT_WIDTH),\n // A 1010 1010\n // B 1100 1100\n // S 1111 0000\n .LUT(8'b 1100_1010)\n ) lut (\n .A(AA),\n .Y(Y)\n );\nendmodule\n",
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"arith_map.v": "/*\r\n * yosys -- Yosys Open SYnthesis Suite\r\n *\r\n * Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>\r\n *\r\n * Permission to use, copy, modify, and/or distribute this software for any\r\n * purpose with or without fee is hereby granted, provided that the above\r\n * copyright notice and this permission notice appear in all copies.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\n(* techmap_celltype = \"$alu\" *)\r\nmodule _80_gatemate_alu(A, B, CI, BI, X, Y, CO);\r\n\tparameter A_SIGNED = 0;\r\n\tparameter B_SIGNED = 0;\r\n\tparameter A_WIDTH = 1;\r\n\tparameter B_WIDTH = 1;\r\n\tparameter Y_WIDTH = 1;\r\n\r\n\t(* force_downto *)\r\n\tinput [A_WIDTH-1:0] A;\r\n\t(* force_downto *)\r\n\tinput [B_WIDTH-1:0] B;\r\n\t(* force_downto *)\r\n\toutput [Y_WIDTH-1:0] X, Y;\r\n\r\n\tinput CI, BI;\r\n\t(* force_downto *)\r\n\toutput [Y_WIDTH-1:0] CO;\r\n\r\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\r\n\r\n\t(* force_downto *)\r\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\r\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\r\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\r\n\r\n\t(* force_downto *)\r\n\twire [Y_WIDTH-1:0] AA = A_buf;\r\n\t(* force_downto *)\r\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\r\n\t(* force_downto *)\r\n\twire [Y_WIDTH-1:0] C = {CO, CI};\r\n\r\n\tgenvar i;\r\n\tgenerate\r\n\t\tfor (i = 0; i < Y_WIDTH; i = i + 1)\r\n\t\tbegin: slice\r\n\t\t\tCC_ADDF addf_i (\r\n\t\t\t\t.A(AA[i]),\r\n\t\t\t\t.B(BB[i]),\r\n\t\t\t\t.CI(C[i]),\r\n\t\t\t\t.CO(CO[i]),\r\n\t\t\t\t.S(Y[i])\r\n\t\t\t);\r\n\t\tend\r\n\tendgenerate\r\n\r\n\tassign X = AA ^ BB;\r\n\r\nendmodule\r\n",
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-
"brams.txt": "ram block $__CC_BRAM_TDP_ {\n\toption \"MODE\" \"20K\" {\n\t\tabits 14;\n\t\twidths 1 2 5 10 20 per_port;\n\t\tcost 129;\n\t}\n\toption \"MODE\" \"40K\" {\n\t\tabits 15;\n\t\twidths 1 2 5 10 20 40 per_port;\n\t\tcost 257;\n\t}\n\toption \"MODE\" \"CASCADE\" {\n\t\tabits 16;\n\t\t# hack to enforce same INIT layout as in the other modes\n\t\twidths 1 2 5 per_port;\n\t\tcost 513;\n\t}\n\tbyte 1;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\toption \"MODE\" \"20K\" {\n\t\t\twidth mix;\n\t\t}\n\t\toption \"MODE\" \"40K\" {\n\t\t\twidth mix;\n\t\t}\n\t\toption \"MODE\" \"CASCADE\" {\n\t\t\twidth mix 1;\n\t\t}\n\t\tportoption \"WR_MODE\" \"NO_CHANGE\" {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WR_MODE\" \"WRITE_THROUGH\" {\n\t\t\trdwr new;\n\t\t
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81
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+
"brams.txt": "ram block $__CC_BRAM_TDP_ {\n\toption \"MODE\" \"20K\" {\n\t\tabits 14;\n\t\twidths 1 2 5 10 20 per_port;\n\t\tcost 129;\n\t}\n\toption \"MODE\" \"40K\" {\n\t\tabits 15;\n\t\twidths 1 2 5 10 20 40 per_port;\n\t\tcost 257;\n\t}\n\toption \"MODE\" \"CASCADE\" {\n\t\tabits 16;\n\t\t# hack to enforce same INIT layout as in the other modes\n\t\twidths 1 2 5 per_port;\n\t\tcost 513;\n\t}\n\tbyte 1;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\toption \"MODE\" \"20K\" {\n\t\t\twidth mix;\n\t\t}\n\t\toption \"MODE\" \"40K\" {\n\t\t\twidth mix;\n\t\t}\n\t\toption \"MODE\" \"CASCADE\" {\n\t\t\twidth mix 1;\n\t\t}\n\t\tportoption \"WR_MODE\" \"NO_CHANGE\" {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WR_MODE\" \"WRITE_THROUGH\" {\n\t\t\trdwr new;\n\t\t}\n\t\twrbe_separate;\n\t\toptional_rw;\n\t}\n}\n\nram block $__CC_BRAM_SDP_ {\n\toption \"MODE\" \"20K\" {\n\t\tabits 14;\n\t\twidths 1 2 5 10 20 40 per_port;\n\t\tcost 129;\n\t}\n\toption \"MODE\" \"40K\" {\n\t\tabits 15;\n\t\twidths 1 2 5 10 20 40 80 per_port;\n\t\tcost 257;\n\t}\n\tbyte 1;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\toption \"MODE\" \"20K\" {\n\t\t\twidth 40;\n\t\t}\n\t\toption \"MODE\" \"40K\" {\n\t\t\twidth 80;\n\t\t}\n\t\tclock anyedge;\n\t\tclken;\n\t\toptional;\n\t}\n\tport sw \"W\" {\n\t\toption \"MODE\" \"20K\" {\n\t\t\twidth 40;\n\t\t}\n\t\toption \"MODE\" \"40K\" {\n\t\t\twidth 80;\n\t\t}\n\t\tclock anyedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\toptional;\n\t}\n}\n",
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"brams_init_20.vh": ".INIT_00(permute_init(INIT[ 0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_01(permute_init(INIT[ 1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_02(permute_init(INIT[ 2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_03(permute_init(INIT[ 3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_04(permute_init(INIT[ 4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_05(permute_init(INIT[ 5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_06(permute_init(INIT[ 6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_07(permute_init(INIT[ 7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_08(permute_init(INIT[ 8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_09(permute_init(INIT[ 9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n",
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"brams_init_40.vh": "`ifdef INIT_LOWER\n.INIT_00(permute_init(INIT[ 0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_01(permute_init(INIT[ 1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_02(permute_init(INIT[ 2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_03(permute_init(INIT[ 3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_04(permute_init(INIT[ 4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_05(permute_init(INIT[ 5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_06(permute_init(INIT[ 6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_07(permute_init(INIT[ 7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_08(permute_init(INIT[ 8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_09(permute_init(INIT[ 9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_40(permute_init(INIT[ 64*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_41(permute_init(INIT[ 65*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_42(permute_init(INIT[ 66*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_43(permute_init(INIT[ 67*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_44(permute_init(INIT[ 68*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_45(permute_init(INIT[ 69*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_46(permute_init(INIT[ 70*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_47(permute_init(INIT[ 71*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_48(permute_init(INIT[ 72*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_49(permute_init(INIT[ 73*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4A(permute_init(INIT[ 74*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4B(permute_init(INIT[ 75*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4C(permute_init(INIT[ 76*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4D(permute_init(INIT[ 77*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4E(permute_init(INIT[ 78*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4F(permute_init(INIT[ 79*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_50(permute_init(INIT[ 80*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_51(permute_init(INIT[ 81*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_52(permute_init(INIT[ 82*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_53(permute_init(INIT[ 83*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_54(permute_init(INIT[ 84*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_55(permute_init(INIT[ 85*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_56(permute_init(INIT[ 86*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_57(permute_init(INIT[ 87*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_58(permute_init(INIT[ 88*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_59(permute_init(INIT[ 89*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5A(permute_init(INIT[ 90*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5B(permute_init(INIT[ 91*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5C(permute_init(INIT[ 92*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5D(permute_init(INIT[ 93*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5E(permute_init(INIT[ 94*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5F(permute_init(INIT[ 95*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_60(permute_init(INIT[ 96*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_61(permute_init(INIT[ 97*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_62(permute_init(INIT[ 98*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_63(permute_init(INIT[ 99*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_64(permute_init(INIT[100*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_65(permute_init(INIT[101*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_66(permute_init(INIT[102*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_67(permute_init(INIT[103*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_68(permute_init(INIT[104*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_69(permute_init(INIT[105*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6A(permute_init(INIT[106*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6B(permute_init(INIT[107*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6C(permute_init(INIT[108*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6D(permute_init(INIT[109*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6E(permute_init(INIT[110*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6F(permute_init(INIT[111*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_70(permute_init(INIT[112*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_71(permute_init(INIT[113*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_72(permute_init(INIT[114*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_73(permute_init(INIT[115*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_74(permute_init(INIT[116*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_75(permute_init(INIT[117*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_76(permute_init(INIT[118*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_77(permute_init(INIT[119*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_78(permute_init(INIT[120*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_79(permute_init(INIT[121*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7A(permute_init(INIT[122*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7B(permute_init(INIT[123*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7C(permute_init(INIT[124*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7D(permute_init(INIT[125*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7E(permute_init(INIT[126*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7F(permute_init(INIT[127*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n`endif\n`ifdef INIT_UPPER\n.INIT_00(permute_init(INIT[128*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_01(permute_init(INIT[129*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_02(permute_init(INIT[130*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_03(permute_init(INIT[131*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_04(permute_init(INIT[132*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_05(permute_init(INIT[133*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_06(permute_init(INIT[134*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_07(permute_init(INIT[135*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_08(permute_init(INIT[136*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_09(permute_init(INIT[137*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0A(permute_init(INIT[138*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0B(permute_init(INIT[139*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0C(permute_init(INIT[140*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0D(permute_init(INIT[141*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0E(permute_init(INIT[142*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0F(permute_init(INIT[143*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_10(permute_init(INIT[144*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_11(permute_init(INIT[145*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_12(permute_init(INIT[146*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_13(permute_init(INIT[147*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_14(permute_init(INIT[148*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_15(permute_init(INIT[149*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_16(permute_init(INIT[150*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_17(permute_init(INIT[151*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_18(permute_init(INIT[152*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_19(permute_init(INIT[153*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1A(permute_init(INIT[154*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1B(permute_init(INIT[155*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1C(permute_init(INIT[156*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1D(permute_init(INIT[157*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1E(permute_init(INIT[158*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1F(permute_init(INIT[159*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_20(permute_init(INIT[160*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_21(permute_init(INIT[161*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_22(permute_init(INIT[162*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_23(permute_init(INIT[163*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_24(permute_init(INIT[164*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_25(permute_init(INIT[165*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_26(permute_init(INIT[166*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_27(permute_init(INIT[167*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_28(permute_init(INIT[168*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_29(permute_init(INIT[169*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2A(permute_init(INIT[170*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2B(permute_init(INIT[171*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2C(permute_init(INIT[172*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2D(permute_init(INIT[173*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2E(permute_init(INIT[174*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2F(permute_init(INIT[175*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_30(permute_init(INIT[176*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_31(permute_init(INIT[177*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_32(permute_init(INIT[178*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_33(permute_init(INIT[179*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_34(permute_init(INIT[180*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_35(permute_init(INIT[181*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_36(permute_init(INIT[182*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_37(permute_init(INIT[183*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_38(permute_init(INIT[184*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_39(permute_init(INIT[185*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3A(permute_init(INIT[186*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3B(permute_init(INIT[187*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3C(permute_init(INIT[188*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3D(permute_init(INIT[189*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3E(permute_init(INIT[190*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3F(permute_init(INIT[191*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_40(permute_init(INIT[192*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_41(permute_init(INIT[193*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_42(permute_init(INIT[194*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_43(permute_init(INIT[195*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_44(permute_init(INIT[196*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_45(permute_init(INIT[197*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_46(permute_init(INIT[198*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_47(permute_init(INIT[199*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_48(permute_init(INIT[200*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_49(permute_init(INIT[201*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4A(permute_init(INIT[202*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4B(permute_init(INIT[203*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4C(permute_init(INIT[204*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4D(permute_init(INIT[205*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4E(permute_init(INIT[206*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4F(permute_init(INIT[207*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_50(permute_init(INIT[208*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_51(permute_init(INIT[209*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_52(permute_init(INIT[210*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_53(permute_init(INIT[211*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_54(permute_init(INIT[212*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_55(permute_init(INIT[213*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_56(permute_init(INIT[214*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_57(permute_init(INIT[215*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_58(permute_init(INIT[216*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_59(permute_init(INIT[217*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5A(permute_init(INIT[218*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5B(permute_init(INIT[219*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5C(permute_init(INIT[220*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5D(permute_init(INIT[221*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5E(permute_init(INIT[222*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5F(permute_init(INIT[223*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_60(permute_init(INIT[224*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_61(permute_init(INIT[225*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_62(permute_init(INIT[226*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_63(permute_init(INIT[227*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_64(permute_init(INIT[228*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_65(permute_init(INIT[229*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_66(permute_init(INIT[230*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_67(permute_init(INIT[231*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_68(permute_init(INIT[232*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_69(permute_init(INIT[233*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6A(permute_init(INIT[234*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6B(permute_init(INIT[235*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6C(permute_init(INIT[236*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6D(permute_init(INIT[237*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6E(permute_init(INIT[238*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6F(permute_init(INIT[239*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_70(permute_init(INIT[240*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_71(permute_init(INIT[241*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_72(permute_init(INIT[242*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_73(permute_init(INIT[243*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_74(permute_init(INIT[244*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_75(permute_init(INIT[245*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_76(permute_init(INIT[246*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_77(permute_init(INIT[247*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_78(permute_init(INIT[248*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_79(permute_init(INIT[249*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7A(permute_init(INIT[250*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7B(permute_init(INIT[251*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7C(permute_init(INIT[252*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7D(permute_init(INIT[253*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7E(permute_init(INIT[254*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7F(permute_init(INIT[255*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n`endif\n",
|
|
84
|
-
"brams_map.v": "module $__CC_BRAM_TDP_(...);\r\n\r\nparameter INIT = 0;\r\nparameter OPTION_MODE = \"20K\";\r\n\r\nparameter PORT_A_CLK_POL = 1;\r\nparameter PORT_A_RD_USED = 1;\r\nparameter PORT_A_WR_USED = 1;\r\nparameter PORT_A_RD_WIDTH = 1;\r\nparameter PORT_A_WR_WIDTH = 1;\r\nparameter PORT_A_WR_BE_WIDTH = 1;\r\nparameter PORT_A_OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\nparameter PORT_B_CLK_POL = 1;\r\nparameter PORT_B_RD_USED = 1;\r\nparameter PORT_B_WR_USED = 1;\r\nparameter PORT_B_RD_WIDTH = 1;\r\nparameter PORT_B_WR_WIDTH = 1;\r\nparameter PORT_B_WR_BE_WIDTH = 1;\r\nparameter PORT_B_OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\ninput PORT_A_CLK;\r\ninput PORT_A_CLK_EN;\r\ninput PORT_A_WR_EN;\r\ninput [15:0] PORT_A_ADDR;\r\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\r\ninput [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;\r\noutput [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;\r\n\r\ninput PORT_B_CLK;\r\ninput PORT_B_CLK_EN;\r\ninput PORT_B_WR_EN;\r\ninput [15:0] PORT_B_ADDR;\r\ninput [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\r\ninput [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;\r\noutput [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;\r\n\r\ngenerate\r\n\tif (OPTION_MODE == \"20K\") begin\r\n\t\tCC_BRAM_20K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t);\r\n\tend else if (OPTION_MODE == \"40K\") begin\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], 1'b0}),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t);\r\n\tend else begin\r\n\t\twire CAS_A, CAS_B;\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t\t.CAS(\"LOWER\"),\r\n\t\t) lower (\r\n\t\t\t.A_CO(CAS_A),\r\n\t\t\t.B_CO(CAS_B),\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),\r\n\t\t);\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h80*320+:320]),\r\n\t\t\t.INIT_01(INIT['h81*320+:320]),\r\n\t\t\t.INIT_02(INIT['h82*320+:320]),\r\n\t\t\t.INIT_03(INIT['h83*320+:320]),\r\n\t\t\t.INIT_04(INIT['h84*320+:320]),\r\n\t\t\t.INIT_05(INIT['h85*320+:320]),\r\n\t\t\t.INIT_06(INIT['h86*320+:320]),\r\n\t\t\t.INIT_07(INIT['h87*320+:320]),\r\n\t\t\t.INIT_08(INIT['h88*320+:320]),\r\n\t\t\t.INIT_09(INIT['h89*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h8a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h8b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h8c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h8d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h8e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h8f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h90*320+:320]),\r\n\t\t\t.INIT_11(INIT['h91*320+:320]),\r\n\t\t\t.INIT_12(INIT['h92*320+:320]),\r\n\t\t\t.INIT_13(INIT['h93*320+:320]),\r\n\t\t\t.INIT_14(INIT['h94*320+:320]),\r\n\t\t\t.INIT_15(INIT['h95*320+:320]),\r\n\t\t\t.INIT_16(INIT['h96*320+:320]),\r\n\t\t\t.INIT_17(INIT['h97*320+:320]),\r\n\t\t\t.INIT_18(INIT['h98*320+:320]),\r\n\t\t\t.INIT_19(INIT['h99*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h9a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h9b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h9c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h9d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h9e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h9f*320+:320]),\r\n\t\t\t.INIT_20(INIT['ha0*320+:320]),\r\n\t\t\t.INIT_21(INIT['ha1*320+:320]),\r\n\t\t\t.INIT_22(INIT['ha2*320+:320]),\r\n\t\t\t.INIT_23(INIT['ha3*320+:320]),\r\n\t\t\t.INIT_24(INIT['ha4*320+:320]),\r\n\t\t\t.INIT_25(INIT['ha5*320+:320]),\r\n\t\t\t.INIT_26(INIT['ha6*320+:320]),\r\n\t\t\t.INIT_27(INIT['ha7*320+:320]),\r\n\t\t\t.INIT_28(INIT['ha8*320+:320]),\r\n\t\t\t.INIT_29(INIT['ha9*320+:320]),\r\n\t\t\t.INIT_2A(INIT['haa*320+:320]),\r\n\t\t\t.INIT_2B(INIT['hab*320+:320]),\r\n\t\t\t.INIT_2C(INIT['hac*320+:320]),\r\n\t\t\t.INIT_2D(INIT['had*320+:320]),\r\n\t\t\t.INIT_2E(INIT['hae*320+:320]),\r\n\t\t\t.INIT_2F(INIT['haf*320+:320]),\r\n\t\t\t.INIT_30(INIT['hb0*320+:320]),\r\n\t\t\t.INIT_31(INIT['hb1*320+:320]),\r\n\t\t\t.INIT_32(INIT['hb2*320+:320]),\r\n\t\t\t.INIT_33(INIT['hb3*320+:320]),\r\n\t\t\t.INIT_34(INIT['hb4*320+:320]),\r\n\t\t\t.INIT_35(INIT['hb5*320+:320]),\r\n\t\t\t.INIT_36(INIT['hb6*320+:320]),\r\n\t\t\t.INIT_37(INIT['hb7*320+:320]),\r\n\t\t\t.INIT_38(INIT['hb8*320+:320]),\r\n\t\t\t.INIT_39(INIT['hb9*320+:320]),\r\n\t\t\t.INIT_3A(INIT['hba*320+:320]),\r\n\t\t\t.INIT_3B(INIT['hbb*320+:320]),\r\n\t\t\t.INIT_3C(INIT['hbc*320+:320]),\r\n\t\t\t.INIT_3D(INIT['hbd*320+:320]),\r\n\t\t\t.INIT_3E(INIT['hbe*320+:320]),\r\n\t\t\t.INIT_3F(INIT['hbf*320+:320]),\r\n\t\t\t.INIT_40(INIT['hc0*320+:320]),\r\n\t\t\t.INIT_41(INIT['hc1*320+:320]),\r\n\t\t\t.INIT_42(INIT['hc2*320+:320]),\r\n\t\t\t.INIT_43(INIT['hc3*320+:320]),\r\n\t\t\t.INIT_44(INIT['hc4*320+:320]),\r\n\t\t\t.INIT_45(INIT['hc5*320+:320]),\r\n\t\t\t.INIT_46(INIT['hc6*320+:320]),\r\n\t\t\t.INIT_47(INIT['hc7*320+:320]),\r\n\t\t\t.INIT_48(INIT['hc8*320+:320]),\r\n\t\t\t.INIT_49(INIT['hc9*320+:320]),\r\n\t\t\t.INIT_4A(INIT['hca*320+:320]),\r\n\t\t\t.INIT_4B(INIT['hcb*320+:320]),\r\n\t\t\t.INIT_4C(INIT['hcc*320+:320]),\r\n\t\t\t.INIT_4D(INIT['hcd*320+:320]),\r\n\t\t\t.INIT_4E(INIT['hce*320+:320]),\r\n\t\t\t.INIT_4F(INIT['hcf*320+:320]),\r\n\t\t\t.INIT_50(INIT['hd0*320+:320]),\r\n\t\t\t.INIT_51(INIT['hd1*320+:320]),\r\n\t\t\t.INIT_52(INIT['hd2*320+:320]),\r\n\t\t\t.INIT_53(INIT['hd3*320+:320]),\r\n\t\t\t.INIT_54(INIT['hd4*320+:320]),\r\n\t\t\t.INIT_55(INIT['hd5*320+:320]),\r\n\t\t\t.INIT_56(INIT['hd6*320+:320]),\r\n\t\t\t.INIT_57(INIT['hd7*320+:320]),\r\n\t\t\t.INIT_58(INIT['hd8*320+:320]),\r\n\t\t\t.INIT_59(INIT['hd9*320+:320]),\r\n\t\t\t.INIT_5A(INIT['hda*320+:320]),\r\n\t\t\t.INIT_5B(INIT['hdb*320+:320]),\r\n\t\t\t.INIT_5C(INIT['hdc*320+:320]),\r\n\t\t\t.INIT_5D(INIT['hdd*320+:320]),\r\n\t\t\t.INIT_5E(INIT['hde*320+:320]),\r\n\t\t\t.INIT_5F(INIT['hdf*320+:320]),\r\n\t\t\t.INIT_60(INIT['he0*320+:320]),\r\n\t\t\t.INIT_61(INIT['he1*320+:320]),\r\n\t\t\t.INIT_62(INIT['he2*320+:320]),\r\n\t\t\t.INIT_63(INIT['he3*320+:320]),\r\n\t\t\t.INIT_64(INIT['he4*320+:320]),\r\n\t\t\t.INIT_65(INIT['he5*320+:320]),\r\n\t\t\t.INIT_66(INIT['he6*320+:320]),\r\n\t\t\t.INIT_67(INIT['he7*320+:320]),\r\n\t\t\t.INIT_68(INIT['he8*320+:320]),\r\n\t\t\t.INIT_69(INIT['he9*320+:320]),\r\n\t\t\t.INIT_6A(INIT['hea*320+:320]),\r\n\t\t\t.INIT_6B(INIT['heb*320+:320]),\r\n\t\t\t.INIT_6C(INIT['hec*320+:320]),\r\n\t\t\t.INIT_6D(INIT['hed*320+:320]),\r\n\t\t\t.INIT_6E(INIT['hee*320+:320]),\r\n\t\t\t.INIT_6F(INIT['hef*320+:320]),\r\n\t\t\t.INIT_70(INIT['hf0*320+:320]),\r\n\t\t\t.INIT_71(INIT['hf1*320+:320]),\r\n\t\t\t.INIT_72(INIT['hf2*320+:320]),\r\n\t\t\t.INIT_73(INIT['hf3*320+:320]),\r\n\t\t\t.INIT_74(INIT['hf4*320+:320]),\r\n\t\t\t.INIT_75(INIT['hf5*320+:320]),\r\n\t\t\t.INIT_76(INIT['hf6*320+:320]),\r\n\t\t\t.INIT_77(INIT['hf7*320+:320]),\r\n\t\t\t.INIT_78(INIT['hf8*320+:320]),\r\n\t\t\t.INIT_79(INIT['hf9*320+:320]),\r\n\t\t\t.INIT_7A(INIT['hfa*320+:320]),\r\n\t\t\t.INIT_7B(INIT['hfb*320+:320]),\r\n\t\t\t.INIT_7C(INIT['hfc*320+:320]),\r\n\t\t\t.INIT_7D(INIT['hfd*320+:320]),\r\n\t\t\t.INIT_7E(INIT['hfe*320+:320]),\r\n\t\t\t.INIT_7F(INIT['hff*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t\t.CAS(\"UPPER\"),\r\n\t\t) upper (\r\n\t\t\t.A_CI(CAS_A),\r\n\t\t\t.B_CI(CAS_B),\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),\r\n\t\t);\r\n\tend\r\nendgenerate\r\n\r\nendmodule\r\n\r\n\r\nmodule $__CC_BRAM_SDP_(...);\r\n\r\nparameter INIT = 0;\r\nparameter OPTION_MODE = \"20K\";\r\nparameter OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\nparameter PORT_W_CLK_POL = 1;\r\nparameter PORT_W_USED = 1;\r\nparameter PORT_W_WIDTH = 40;\r\nparameter PORT_W_WR_BE_WIDTH = 40;\r\n\r\nparameter PORT_R_CLK_POL = 1;\r\nparameter PORT_R_USED = 1;\r\nparameter PORT_R_WIDTH = 40;\r\n\r\ninput PORT_W_CLK;\r\ninput PORT_W_CLK_EN;\r\ninput PORT_W_WR_EN;\r\ninput [15:0] PORT_W_ADDR;\r\ninput [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;\r\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\r\n\r\ninput PORT_R_CLK;\r\ninput PORT_R_CLK_EN;\r\ninput [15:0] PORT_R_ADDR;\r\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\r\n\r\ngenerate\r\n\tif (OPTION_MODE == \"20K\") begin\r\n\t\tCC_BRAM_20K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(0),\r\n\t\t\t.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(0),\r\n\t\t\t.RAM_MODE(\"SDP\"),\r\n\t\t\t.A_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_W_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_R_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_W_CLK),\r\n\t\t\t.A_EN(PORT_W_CLK_EN),\r\n\t\t\t.A_WE(PORT_W_WR_EN),\r\n\t\t\t.A_BM(PORT_W_WR_BE[19:0]),\r\n\t\t\t.B_BM(PORT_W_WR_BE[39:20]),\r\n\t\t\t.A_DI(PORT_W_WR_DATA[19:0]),\r\n\t\t\t.B_DI(PORT_W_WR_DATA[39:20]),\r\n\t\t\t.A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}),\r\n\t\t\t.B_CLK(PORT_R_CLK),\r\n\t\t\t.B_EN(PORT_R_CLK_EN),\r\n\t\t\t.B_WE(1'b0),\r\n\t\t\t.B_ADDR({PORT_R_ADDR[13:5], 1'b0, PORT_R_ADDR[4:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_R_RD_DATA[19:0]),\r\n\t\t\t.B_DO(PORT_R_RD_DATA[39:20]),\r\n\t\t);\r\n\tend else if (OPTION_MODE == \"40K\") begin\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(0),\r\n\t\t\t.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(0),\r\n\t\t\t.RAM_MODE(\"SDP\"),\r\n\t\t\t.A_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_W_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_R_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_W_CLK),\r\n\t\t\t.A_EN(PORT_W_CLK_EN),\r\n\t\t\t.A_WE(PORT_W_WR_EN),\r\n\t\t\t.A_BM(PORT_W_WR_BE[39:0]),\r\n\t\t\t.B_BM(PORT_W_WR_BE[79:40]),\r\n\t\t\t.A_DI(PORT_W_WR_DATA[39:0]),\r\n\t\t\t.B_DI(PORT_W_WR_DATA[79:40]),\r\n\t\t\t.A_ADDR({PORT_W_ADDR[14:0], 1'b0}),\r\n\t\t\t.B_CLK(PORT_R_CLK),\r\n\t\t\t.B_EN(PORT_R_CLK_EN),\r\n\t\t\t.B_WE(1'b0),\r\n\t\t\t.B_ADDR({PORT_R_ADDR[14:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_R_RD_DATA[39:0]),\r\n\t\t\t.B_DO(PORT_R_RD_DATA[79:40]),\r\n\t\t);\r\n\tend\r\nendgenerate\r\n\r\nendmodule\r\n",
|
|
84
|
+
"brams_map.v": "module $__CC_BRAM_TDP_(...);\r\n\r\nparameter INIT = 0;\r\nparameter OPTION_MODE = \"20K\";\r\n\r\nparameter PORT_A_CLK_POL = 1;\r\nparameter PORT_A_RD_USED = 1;\r\nparameter PORT_A_WR_USED = 1;\r\nparameter PORT_A_RD_WIDTH = 1;\r\nparameter PORT_A_WR_WIDTH = 1;\r\nparameter PORT_A_WR_BE_WIDTH = 1;\r\nparameter PORT_A_OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\nparameter PORT_B_CLK_POL = 1;\r\nparameter PORT_B_RD_USED = 1;\r\nparameter PORT_B_WR_USED = 1;\r\nparameter PORT_B_RD_WIDTH = 1;\r\nparameter PORT_B_WR_WIDTH = 1;\r\nparameter PORT_B_WR_BE_WIDTH = 1;\r\nparameter PORT_B_OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\ninput PORT_A_CLK;\r\ninput PORT_A_CLK_EN;\r\ninput PORT_A_WR_EN;\r\ninput [15:0] PORT_A_ADDR;\r\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\r\ninput [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;\r\noutput [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;\r\n\r\ninput PORT_B_CLK;\r\ninput PORT_B_CLK_EN;\r\ninput PORT_B_WR_EN;\r\ninput [15:0] PORT_B_ADDR;\r\ninput [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\r\ninput [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;\r\noutput [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;\r\n\r\ngenerate\r\n\tif (OPTION_MODE == \"20K\") begin\r\n\t\tCC_BRAM_20K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM({{(20-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),\r\n\t\t\t.A_DI({{(20-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM({{(20-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),\r\n\t\t\t.B_DI({{(20-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t);\r\n\tend else if (OPTION_MODE == \"40K\") begin\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),\r\n\t\t\t.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),\r\n\t\t\t.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], 1'b0}),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t);\r\n\tend else begin\r\n\t\twire CAS_A, CAS_B;\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t\t.CAS(\"LOWER\"),\r\n\t\t) lower (\r\n\t\t\t.A_CO(CAS_A),\r\n\t\t\t.B_CO(CAS_B),\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),\r\n\t\t\t.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),\r\n\t\t\t.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),\r\n\t\t);\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h80*320+:320]),\r\n\t\t\t.INIT_01(INIT['h81*320+:320]),\r\n\t\t\t.INIT_02(INIT['h82*320+:320]),\r\n\t\t\t.INIT_03(INIT['h83*320+:320]),\r\n\t\t\t.INIT_04(INIT['h84*320+:320]),\r\n\t\t\t.INIT_05(INIT['h85*320+:320]),\r\n\t\t\t.INIT_06(INIT['h86*320+:320]),\r\n\t\t\t.INIT_07(INIT['h87*320+:320]),\r\n\t\t\t.INIT_08(INIT['h88*320+:320]),\r\n\t\t\t.INIT_09(INIT['h89*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h8a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h8b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h8c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h8d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h8e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h8f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h90*320+:320]),\r\n\t\t\t.INIT_11(INIT['h91*320+:320]),\r\n\t\t\t.INIT_12(INIT['h92*320+:320]),\r\n\t\t\t.INIT_13(INIT['h93*320+:320]),\r\n\t\t\t.INIT_14(INIT['h94*320+:320]),\r\n\t\t\t.INIT_15(INIT['h95*320+:320]),\r\n\t\t\t.INIT_16(INIT['h96*320+:320]),\r\n\t\t\t.INIT_17(INIT['h97*320+:320]),\r\n\t\t\t.INIT_18(INIT['h98*320+:320]),\r\n\t\t\t.INIT_19(INIT['h99*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h9a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h9b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h9c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h9d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h9e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h9f*320+:320]),\r\n\t\t\t.INIT_20(INIT['ha0*320+:320]),\r\n\t\t\t.INIT_21(INIT['ha1*320+:320]),\r\n\t\t\t.INIT_22(INIT['ha2*320+:320]),\r\n\t\t\t.INIT_23(INIT['ha3*320+:320]),\r\n\t\t\t.INIT_24(INIT['ha4*320+:320]),\r\n\t\t\t.INIT_25(INIT['ha5*320+:320]),\r\n\t\t\t.INIT_26(INIT['ha6*320+:320]),\r\n\t\t\t.INIT_27(INIT['ha7*320+:320]),\r\n\t\t\t.INIT_28(INIT['ha8*320+:320]),\r\n\t\t\t.INIT_29(INIT['ha9*320+:320]),\r\n\t\t\t.INIT_2A(INIT['haa*320+:320]),\r\n\t\t\t.INIT_2B(INIT['hab*320+:320]),\r\n\t\t\t.INIT_2C(INIT['hac*320+:320]),\r\n\t\t\t.INIT_2D(INIT['had*320+:320]),\r\n\t\t\t.INIT_2E(INIT['hae*320+:320]),\r\n\t\t\t.INIT_2F(INIT['haf*320+:320]),\r\n\t\t\t.INIT_30(INIT['hb0*320+:320]),\r\n\t\t\t.INIT_31(INIT['hb1*320+:320]),\r\n\t\t\t.INIT_32(INIT['hb2*320+:320]),\r\n\t\t\t.INIT_33(INIT['hb3*320+:320]),\r\n\t\t\t.INIT_34(INIT['hb4*320+:320]),\r\n\t\t\t.INIT_35(INIT['hb5*320+:320]),\r\n\t\t\t.INIT_36(INIT['hb6*320+:320]),\r\n\t\t\t.INIT_37(INIT['hb7*320+:320]),\r\n\t\t\t.INIT_38(INIT['hb8*320+:320]),\r\n\t\t\t.INIT_39(INIT['hb9*320+:320]),\r\n\t\t\t.INIT_3A(INIT['hba*320+:320]),\r\n\t\t\t.INIT_3B(INIT['hbb*320+:320]),\r\n\t\t\t.INIT_3C(INIT['hbc*320+:320]),\r\n\t\t\t.INIT_3D(INIT['hbd*320+:320]),\r\n\t\t\t.INIT_3E(INIT['hbe*320+:320]),\r\n\t\t\t.INIT_3F(INIT['hbf*320+:320]),\r\n\t\t\t.INIT_40(INIT['hc0*320+:320]),\r\n\t\t\t.INIT_41(INIT['hc1*320+:320]),\r\n\t\t\t.INIT_42(INIT['hc2*320+:320]),\r\n\t\t\t.INIT_43(INIT['hc3*320+:320]),\r\n\t\t\t.INIT_44(INIT['hc4*320+:320]),\r\n\t\t\t.INIT_45(INIT['hc5*320+:320]),\r\n\t\t\t.INIT_46(INIT['hc6*320+:320]),\r\n\t\t\t.INIT_47(INIT['hc7*320+:320]),\r\n\t\t\t.INIT_48(INIT['hc8*320+:320]),\r\n\t\t\t.INIT_49(INIT['hc9*320+:320]),\r\n\t\t\t.INIT_4A(INIT['hca*320+:320]),\r\n\t\t\t.INIT_4B(INIT['hcb*320+:320]),\r\n\t\t\t.INIT_4C(INIT['hcc*320+:320]),\r\n\t\t\t.INIT_4D(INIT['hcd*320+:320]),\r\n\t\t\t.INIT_4E(INIT['hce*320+:320]),\r\n\t\t\t.INIT_4F(INIT['hcf*320+:320]),\r\n\t\t\t.INIT_50(INIT['hd0*320+:320]),\r\n\t\t\t.INIT_51(INIT['hd1*320+:320]),\r\n\t\t\t.INIT_52(INIT['hd2*320+:320]),\r\n\t\t\t.INIT_53(INIT['hd3*320+:320]),\r\n\t\t\t.INIT_54(INIT['hd4*320+:320]),\r\n\t\t\t.INIT_55(INIT['hd5*320+:320]),\r\n\t\t\t.INIT_56(INIT['hd6*320+:320]),\r\n\t\t\t.INIT_57(INIT['hd7*320+:320]),\r\n\t\t\t.INIT_58(INIT['hd8*320+:320]),\r\n\t\t\t.INIT_59(INIT['hd9*320+:320]),\r\n\t\t\t.INIT_5A(INIT['hda*320+:320]),\r\n\t\t\t.INIT_5B(INIT['hdb*320+:320]),\r\n\t\t\t.INIT_5C(INIT['hdc*320+:320]),\r\n\t\t\t.INIT_5D(INIT['hdd*320+:320]),\r\n\t\t\t.INIT_5E(INIT['hde*320+:320]),\r\n\t\t\t.INIT_5F(INIT['hdf*320+:320]),\r\n\t\t\t.INIT_60(INIT['he0*320+:320]),\r\n\t\t\t.INIT_61(INIT['he1*320+:320]),\r\n\t\t\t.INIT_62(INIT['he2*320+:320]),\r\n\t\t\t.INIT_63(INIT['he3*320+:320]),\r\n\t\t\t.INIT_64(INIT['he4*320+:320]),\r\n\t\t\t.INIT_65(INIT['he5*320+:320]),\r\n\t\t\t.INIT_66(INIT['he6*320+:320]),\r\n\t\t\t.INIT_67(INIT['he7*320+:320]),\r\n\t\t\t.INIT_68(INIT['he8*320+:320]),\r\n\t\t\t.INIT_69(INIT['he9*320+:320]),\r\n\t\t\t.INIT_6A(INIT['hea*320+:320]),\r\n\t\t\t.INIT_6B(INIT['heb*320+:320]),\r\n\t\t\t.INIT_6C(INIT['hec*320+:320]),\r\n\t\t\t.INIT_6D(INIT['hed*320+:320]),\r\n\t\t\t.INIT_6E(INIT['hee*320+:320]),\r\n\t\t\t.INIT_6F(INIT['hef*320+:320]),\r\n\t\t\t.INIT_70(INIT['hf0*320+:320]),\r\n\t\t\t.INIT_71(INIT['hf1*320+:320]),\r\n\t\t\t.INIT_72(INIT['hf2*320+:320]),\r\n\t\t\t.INIT_73(INIT['hf3*320+:320]),\r\n\t\t\t.INIT_74(INIT['hf4*320+:320]),\r\n\t\t\t.INIT_75(INIT['hf5*320+:320]),\r\n\t\t\t.INIT_76(INIT['hf6*320+:320]),\r\n\t\t\t.INIT_77(INIT['hf7*320+:320]),\r\n\t\t\t.INIT_78(INIT['hf8*320+:320]),\r\n\t\t\t.INIT_79(INIT['hf9*320+:320]),\r\n\t\t\t.INIT_7A(INIT['hfa*320+:320]),\r\n\t\t\t.INIT_7B(INIT['hfb*320+:320]),\r\n\t\t\t.INIT_7C(INIT['hfc*320+:320]),\r\n\t\t\t.INIT_7D(INIT['hfd*320+:320]),\r\n\t\t\t.INIT_7E(INIT['hfe*320+:320]),\r\n\t\t\t.INIT_7F(INIT['hff*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t\t.CAS(\"UPPER\"),\r\n\t\t) upper (\r\n\t\t\t.A_CI(CAS_A),\r\n\t\t\t.B_CI(CAS_B),\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),\r\n\t\t\t.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),\r\n\t\t\t.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),\r\n\t\t);\r\n\tend\r\nendgenerate\r\n\r\nendmodule\r\n\r\n\r\nmodule $__CC_BRAM_SDP_(...);\r\n\r\nparameter INIT = 0;\r\nparameter OPTION_MODE = \"20K\";\r\nparameter OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\nparameter PORT_W_CLK_POL = 1;\r\nparameter PORT_W_USED = 1;\r\nparameter PORT_W_WIDTH = 40;\r\nparameter PORT_W_WR_BE_WIDTH = 40;\r\n\r\nparameter PORT_R_CLK_POL = 1;\r\nparameter PORT_R_USED = 1;\r\nparameter PORT_R_WIDTH = 40;\r\n\r\ninput PORT_W_CLK;\r\ninput PORT_W_CLK_EN;\r\ninput PORT_W_WR_EN;\r\ninput [15:0] PORT_W_ADDR;\r\ninput [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;\r\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\r\n\r\ninput PORT_R_CLK;\r\ninput PORT_R_CLK_EN;\r\ninput [15:0] PORT_R_ADDR;\r\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\r\n\r\ngenerate\r\n\tif (OPTION_MODE == \"20K\") begin\r\n\t\tCC_BRAM_20K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(0),\r\n\t\t\t.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(0),\r\n\t\t\t.RAM_MODE(\"SDP\"),\r\n\t\t\t.A_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_W_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_R_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_W_CLK),\r\n\t\t\t.A_EN(PORT_W_CLK_EN),\r\n\t\t\t.A_WE(PORT_W_WR_EN),\r\n\t\t\t.A_BM(PORT_W_WR_BE[19:0]),\r\n\t\t\t.B_BM({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[39:20]}),\r\n\t\t\t.A_DI(PORT_W_WR_DATA[19:0]),\r\n\t\t\t.B_DI({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[39:20]}),\r\n\t\t\t.A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}),\r\n\t\t\t.B_CLK(PORT_R_CLK),\r\n\t\t\t.B_EN(PORT_R_CLK_EN),\r\n\t\t\t.B_WE(1'b0),\r\n\t\t\t.B_ADDR({PORT_R_ADDR[13:5], 1'b0, PORT_R_ADDR[4:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_R_RD_DATA[19:0]),\r\n\t\t\t.B_DO(PORT_R_RD_DATA[39:20]),\r\n\t\t);\r\n\tend else if (OPTION_MODE == \"40K\") begin\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(0),\r\n\t\t\t.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(0),\r\n\t\t\t.RAM_MODE(\"SDP\"),\r\n\t\t\t.A_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_W_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_R_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_W_CLK),\r\n\t\t\t.A_EN(PORT_W_CLK_EN),\r\n\t\t\t.A_WE(PORT_W_WR_EN),\r\n\t\t\t.A_BM(PORT_W_WR_BE[39:0]),\r\n\t\t\t.B_BM({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[79:40]}),\r\n\t\t\t.A_DI(PORT_W_WR_DATA[39:0]),\r\n\t\t\t.B_DI({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[79:40]}),\r\n\t\t\t.A_ADDR({PORT_W_ADDR[14:0], 1'b0}),\r\n\t\t\t.B_CLK(PORT_R_CLK),\r\n\t\t\t.B_EN(PORT_R_CLK_EN),\r\n\t\t\t.B_WE(1'b0),\r\n\t\t\t.B_ADDR({PORT_R_ADDR[14:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_R_RD_DATA[39:0]),\r\n\t\t\t.B_DO(PORT_R_RD_DATA[79:40]),\r\n\t\t);\r\n\tend\r\nendgenerate\r\n\r\nendmodule\r\n",
|
|
85
85
|
"cells_bb.v": "/*\r\n * yosys -- Yosys Open SYnthesis Suite\r\n *\r\n * Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>\r\n *\r\n * Permission to use, copy, modify, and/or distribute this software for any\r\n * purpose with or without fee is hereby granted, provided that the above\r\n * copyright notice and this permission notice appear in all copies.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\n(* blackbox *)\r\nmodule CC_PLL #(\r\n\tparameter REF_CLK = \"\", // e.g. \"10.0\"\r\n\tparameter OUT_CLK = \"\", // e.g. \"50.0\"\r\n\tparameter PERF_MD = \"\", // LOWPOWER, ECONOMY, SPEED\r\n\tparameter LOCK_REQ = 1,\r\n\tparameter CLK270_DOUB = 0,\r\n\tparameter CLK180_DOUB = 0,\r\n\tparameter LOW_JITTER = 1,\r\n\tparameter CI_FILTER_CONST = 2,\r\n\tparameter CP_FILTER_CONST = 4\r\n)(\r\n\tinput CLK_REF, CLK_FEEDBACK, USR_CLK_REF,\r\n\tinput USR_LOCKED_STDY_RST,\r\n\toutput USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,\r\n\toutput CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT\r\n);\r\nendmodule\r\n\r\n(* blackbox *)\r\nmodule CC_PLL_ADV #(\r\n\tparameter [95:0] PLL_CFG_A = 96'bx,\r\n\tparameter [95:0] PLL_CFG_B = 96'bx\r\n)(\r\n\tinput CLK_REF, CLK_FEEDBACK, USR_CLK_REF,\r\n\tinput USR_LOCKED_STDY_RST, USR_SEL_A_B,\r\n\toutput USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,\r\n\toutput CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_SERDES #(\r\n\tparameter [4:0] RX_BUF_RESET_TIME = 3,\r\n\tparameter [4:0] RX_PCS_RESET_TIME = 3,\r\n\tparameter [4:0] RX_RESET_TIMER_PRESC = 0,\r\n\tparameter [0:0] RX_RESET_DONE_GATE = 0,\r\n\tparameter [4:0] RX_CDR_RESET_TIME = 3,\r\n\tparameter [4:0] RX_EQA_RESET_TIME = 3,\r\n\tparameter [4:0] RX_PMA_RESET_TIME = 3,\r\n\tparameter [0:0] RX_WAIT_CDR_LOCK = 1,\r\n\tparameter [0:0] RX_CALIB_EN = 0,\r\n\tparameter [0:0] RX_CALIB_OVR = 0,\r\n\tparameter [3:0] RX_CALIB_VAL = 0,\r\n\tparameter [2:0] RX_RTERM_VCMSEL = 4,\r\n\tparameter [0:0] RX_RTERM_PD = 0,\r\n\tparameter [7:0] RX_EQA_CKP_LF = 8'hA3,\r\n\tparameter [7:0] RX_EQA_CKP_HF = 8'hA3,\r\n\tparameter [7:0] RX_EQA_CKP_OFFSET = 8'h01,\r\n\tparameter [0:0] RX_EN_EQA = 0,\r\n\tparameter [3:0] RX_EQA_LOCK_CFG = 0,\r\n\tparameter [4:0] RX_TH_MON1 = 8,\r\n\tparameter [3:0] RX_EN_EQA_EXT_VALUE = 0,\r\n\tparameter [4:0] RX_TH_MON2 = 8,\r\n\tparameter [4:0] RX_TAPW = 8,\r\n\tparameter [4:0] RX_AFE_OFFSET = 8,\r\n\tparameter [15:0] RX_EQA_CONFIG = 16'h01C0,\r\n\tparameter [4:0] RX_AFE_PEAK = 16,\r\n\tparameter [3:0] RX_AFE_GAIN = 8,\r\n\tparameter [2:0] RX_AFE_VCMSEL = 4,\r\n\tparameter [7:0] RX_CDR_CKP = 8'hF8,\r\n\tparameter [7:0] RX_CDR_CKI = 0,\r\n\tparameter [8:0] RX_CDR_TRANS_TH = 128,\r\n\tparameter [5:0] RX_CDR_LOCK_CFG = 8'h0B,\r\n\tparameter [14:0] RX_CDR_FREQ_ACC = 0,\r\n\tparameter [15:0] RX_CDR_PHASE_ACC = 0,\r\n\tparameter [1:0] RX_CDR_SET_ACC_CONFIG = 0,\r\n\tparameter [0:0] RX_CDR_FORCE_LOCK = 0,\r\n\tparameter [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283,\r\n\tparameter [0:0] RX_MCOMMA_ALIGN_OVR = 0,\r\n\tparameter [0:0] RX_MCOMMA_ALIGN = 0,\r\n\tparameter [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C,\r\n\tparameter [0:0] RX_PCOMMA_ALIGN_OVR = 0,\r\n\tparameter [0:0] RX_PCOMMA_ALIGN = 0,\r\n\tparameter [1:0] RX_ALIGN_COMMA_WORD = 0,\r\n\tparameter [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF,\r\n\tparameter [1:0] RX_SLIDE_MODE = 0,\r\n\tparameter [0:0] RX_COMMA_DETECT_EN_OVR = 0,\r\n\tparameter [0:0] RX_COMMA_DETECT_EN = 0,\r\n\tparameter [1:0] RX_SLIDE = 0,\r\n\tparameter [0:0] RX_EYE_MEAS_EN = 0,\r\n\tparameter [14:0] RX_EYE_MEAS_CFG = 0,\r\n\tparameter [5:0] RX_MON_PH_OFFSET = 0,\r\n\tparameter [3:0] RX_EI_BIAS = 0,\r\n\tparameter [3:0] RX_EI_BW_SEL = 4,\r\n\tparameter [0:0] RX_EN_EI_DETECTOR_OVR = 0,\r\n\tparameter [0:0] RX_EN_EI_DETECTOR = 0,\r\n\tparameter [0:0] RX_DATA_SEL = 0,\r\n\tparameter [0:0] RX_BUF_BYPASS = 0,\r\n\tparameter [0:0] RX_CLKCOR_USE = 0,\r\n\tparameter [5:0] RX_CLKCOR_MIN_LAT = 32,\r\n\tparameter [5:0] RX_CLKCOR_MAX_LAT = 39,\r\n\tparameter [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7,\r\n\tparameter [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7,\r\n\tparameter [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7,\r\n\tparameter [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7,\r\n\tparameter [0:0] RX_PMA_LOOPBACK = 0,\r\n\tparameter [0:0] RX_PCS_LOOPBACK = 0,\r\n\tparameter [1:0] RX_DATAPATH_SEL = 3,\r\n\tparameter [0:0] RX_PRBS_OVR = 0,\r\n\tparameter [2:0] RX_PRBS_SEL = 0,\r\n\tparameter [0:0] RX_LOOPBACK_OVR = 0,\r\n\tparameter [0:0] RX_PRBS_CNT_RESET = 0,\r\n\tparameter [0:0] RX_POWER_DOWN_OVR = 0,\r\n\tparameter [0:0] RX_POWER_DOWN_N = 0,\r\n\tparameter [0:0] RX_RESET_OVR = 0,\r\n\tparameter [0:0] RX_RESET = 0,\r\n\tparameter [0:0] RX_PMA_RESET_OVR = 0,\r\n\tparameter [0:0] RX_PMA_RESET = 0,\r\n\tparameter [0:0] RX_EQA_RESET_OVR = 0,\r\n\tparameter [0:0] RX_EQA_RESET = 0,\r\n\tparameter [0:0] RX_CDR_RESET_OVR = 0,\r\n\tparameter [0:0] RX_CDR_RESET = 0,\r\n\tparameter [0:0] RX_PCS_RESET_OVR = 0,\r\n\tparameter [0:0] RX_PCS_RESET = 0,\r\n\tparameter [0:0] RX_BUF_RESET_OVR = 0,\r\n\tparameter [0:0] RX_BUF_RESET = 0,\r\n\tparameter [0:0] RX_POLARITY_OVR = 0,\r\n\tparameter [0:0] RX_POLARITY = 0,\r\n\tparameter [0:0] RX_8B10B_EN_OVR = 0,\r\n\tparameter [0:0] RX_8B10B_EN = 0,\r\n\tparameter [7:0] RX_8B10B_BYPASS = 0,\r\n\tparameter [0:0] RX_BYTE_REALIGN = 0,\r\n\tparameter [0:0] RX_DBG_EN = 0,\r\n\tparameter [1:0] RX_DBG_SEL = 0,\r\n\tparameter [0:0] RX_DBG_MODE = 0,\r\n\tparameter [5:0] RX_DBG_SRAM_DELAY = 6'h05,\r\n\tparameter [9:0] RX_DBG_ADDR = 0,\r\n\tparameter [0:0] RX_DBG_RE = 0,\r\n\tparameter [0:0] RX_DBG_WE = 0,\r\n\tparameter [19:0] RX_DBG_DATA = 0,\r\n\tparameter [4:0] TX_SEL_PRE = 0,\r\n\tparameter [4:0] TX_SEL_POST = 0,\r\n\tparameter [4:0] TX_AMP = 15,\r\n\tparameter [4:0] TX_BRANCH_EN_PRE = 0,\r\n\tparameter [5:0] TX_BRANCH_EN_MAIN = 6'h3F,\r\n\tparameter [4:0] TX_BRANCH_EN_POST = 0,\r\n\tparameter [2:0] TX_TAIL_CASCODE = 4,\r\n\tparameter [6:0] TX_DC_ENABLE = 63,\r\n\tparameter [4:0] TX_DC_OFFSET = 0,\r\n\tparameter [4:0] TX_CM_RAISE = 0,\r\n\tparameter [4:0] TX_CM_THRESHOLD_0 = 14,\r\n\tparameter [4:0] TX_CM_THRESHOLD_1 = 16,\r\n\tparameter [4:0] TX_SEL_PRE_EI = 0,\r\n\tparameter [4:0] TX_SEL_POST_EI = 0,\r\n\tparameter [4:0] TX_AMP_EI = 15,\r\n\tparameter [4:0] TX_BRANCH_EN_PRE_EI = 0,\r\n\tparameter [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F,\r\n\tparameter [4:0] TX_BRANCH_EN_POST_EI = 0,\r\n\tparameter [2:0] TX_TAIL_CASCODE_EI = 4,\r\n\tparameter [6:0] TX_DC_ENABLE_EI = 63,\r\n\tparameter [4:0] TX_DC_OFFSET_EI = 0,\r\n\tparameter [4:0] TX_CM_RAISE_EI = 0,\r\n\tparameter [4:0] TX_CM_THRESHOLD_0_EI = 14,\r\n\tparameter [4:0] TX_CM_THRESHOLD_1_EI = 16,\r\n\tparameter [4:0] TX_SEL_PRE_RXDET = 0,\r\n\tparameter [4:0] TX_SEL_POST_RXDET = 0,\r\n\tparameter [4:0] TX_AMP_RXDET = 15,\r\n\tparameter [4:0] TX_BRANCH_EN_PRE_RXDET = 0,\r\n\tparameter [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F,\r\n\tparameter [4:0] TX_BRANCH_EN_POST_RXDET = 0,\r\n\tparameter [2:0] TX_TAIL_CASCODE_RXDET = 4,\r\n\tparameter [6:0] TX_DC_ENABLE_RXDET = 63,\r\n\tparameter [4:0] TX_DC_OFFSET_RXDET = 0,\r\n\tparameter [4:0] TX_CM_RAISE_RXDET = 0,\r\n\tparameter [4:0] TX_CM_THRESHOLD_0_RXDET = 14,\r\n\tparameter [4:0] TX_CM_THRESHOLD_1_RXDET = 16,\r\n\tparameter [0:0] TX_CALIB_EN = 0,\r\n\tparameter [0:0] TX_CALIB_OVR = 0,\r\n\tparameter [3:0] TX_CALIB_VAL = 0,\r\n\tparameter [7:0] TX_CM_REG_KI = 8'h80,\r\n\tparameter [0:0] TX_CM_SAR_EN = 0,\r\n\tparameter [0:0] TX_CM_REG_EN = 1,\r\n\tparameter [4:0] TX_PMA_RESET_TIME = 3,\r\n\tparameter [4:0] TX_PCS_RESET_TIME = 3,\r\n\tparameter [0:0] TX_PCS_RESET_OVR = 0,\r\n\tparameter [0:0] TX_PCS_RESET = 0,\r\n\tparameter [0:0] TX_PMA_RESET_OVR = 0,\r\n\tparameter [0:0] TX_PMA_RESET = 0,\r\n\tparameter [0:0] TX_RESET_OVR = 0,\r\n\tparameter [0:0] TX_RESET = 0,\r\n\tparameter [1:0] TX_PMA_LOOPBACK = 0,\r\n\tparameter [0:0] TX_PCS_LOOPBACK = 0,\r\n\tparameter [1:0] TX_DATAPATH_SEL = 3,\r\n\tparameter [0:0] TX_PRBS_OVR = 0,\r\n\tparameter [2:0] TX_PRBS_SEL = 0,\r\n\tparameter [0:0] TX_PRBS_FORCE_ERR = 0,\r\n\tparameter [0:0] TX_LOOPBACK_OVR = 0,\r\n\tparameter [0:0] TX_POWER_DOWN_OVR = 0,\r\n\tparameter [0:0] TX_POWER_DOWN_N = 0,\r\n\tparameter [0:0] TX_ELEC_IDLE_OVR = 0,\r\n\tparameter [0:0] TX_ELEC_IDLE = 0,\r\n\tparameter [0:0] TX_DETECT_RX_OVR = 0,\r\n\tparameter [0:0] TX_DETECT_RX = 0,\r\n\tparameter [0:0] TX_POLARITY_OVR = 0,\r\n\tparameter [0:0] TX_POLARITY = 0,\r\n\tparameter [0:0] TX_8B10B_EN_OVR = 0,\r\n\tparameter [0:0] TX_8B10B_EN = 0,\r\n\tparameter [0:0] TX_DATA_OVR = 0,\r\n\tparameter [2:0] TX_DATA_CNT = 0,\r\n\tparameter [0:0] TX_DATA_VALID = 0,\r\n\tparameter [0:0] PLL_EN_ADPLL_CTRL = 0,\r\n\tparameter [0:0] PLL_CONFIG_SEL = 0,\r\n\tparameter [0:0] PLL_SET_OP_LOCK = 0,\r\n\tparameter [0:0] PLL_ENFORCE_LOCK = 0,\r\n\tparameter [0:0] PLL_DISABLE_LOCK = 0,\r\n\tparameter [0:0] PLL_LOCK_WINDOW = 1,\r\n\tparameter [0:0] PLL_FAST_LOCK = 1,\r\n\tparameter [0:0] PLL_SYNC_BYPASS = 0,\r\n\tparameter [0:0] PLL_PFD_SELECT = 0,\r\n\tparameter [0:0] PLL_REF_BYPASS = 0,\r\n\tparameter [0:0] PLL_REF_SEL = 0,\r\n\tparameter [0:0] PLL_REF_RTERM = 1,\r\n\tparameter [5:0] PLL_FCNTRL = 58,\r\n\tparameter [5:0] PLL_MAIN_DIVSEL = 27,\r\n\tparameter [1:0] PLL_OUT_DIVSEL = 0,\r\n\tparameter [4:0] PLL_CI = 3,\r\n\tparameter [9:0] PLL_CP = 80,\r\n\tparameter [3:0] PLL_AO = 0,\r\n\tparameter [2:0] PLL_SCAP = 0,\r\n\tparameter [1:0] PLL_FILTER_SHIFT = 2,\r\n\tparameter [2:0] PLL_SAR_LIMIT = 2,\r\n\tparameter [10:0] PLL_FT = 512,\r\n\tparameter [0:0] PLL_OPEN_LOOP = 0,\r\n\tparameter [0:0] PLL_SCAP_AUTO_CAL = 1,\r\n\tparameter [2:0] PLL_BISC_MODE = 4,\r\n\tparameter [3:0] PLL_BISC_TIMER_MAX = 15,\r\n\tparameter [0:0] PLL_BISC_OPT_DET_IND = 0,\r\n\tparameter [0:0] PLL_BISC_PFD_SEL = 0,\r\n\tparameter [0:0] PLL_BISC_DLY_DIR = 0,\r\n\tparameter [2:0] PLL_BISC_COR_DLY = 1,\r\n\tparameter [0:0] PLL_BISC_CAL_SIGN = 0,\r\n\tparameter [0:0] PLL_BISC_CAL_AUTO = 1,\r\n\tparameter [4:0] PLL_BISC_CP_MIN = 4,\r\n\tparameter [4:0] PLL_BISC_CP_MAX = 18,\r\n\tparameter [4:0] PLL_BISC_CP_START = 12,\r\n\tparameter [4:0] PLL_BISC_DLY_PFD_MON_REF = 0,\r\n\tparameter [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2,\r\n\tparameter [0:0] SERDES_ENABLE = 0,\r\n\tparameter [0:0] SERDES_AUTO_INIT = 0,\r\n\tparameter [0:0] SERDES_TESTMODE = 0\r\n)(\r\n\tinput [63:0] TX_DATA_I,\r\n\tinput TX_RESET_I,\r\n\tinput TX_PCS_RESET_I,\r\n\tinput TX_PMA_RESET_I,\r\n\tinput PLL_RESET_I,\r\n\tinput TX_POWER_DOWN_N_I,\r\n\tinput TX_POLARITY_I,\r\n\tinput [2:0] TX_PRBS_SEL_I,\r\n\tinput TX_PRBS_FORCE_ERR_I,\r\n\tinput TX_8B10B_EN_I,\r\n\tinput [7:0] TX_8B10B_BYPASS_I,\r\n\tinput [7:0] TX_CHAR_IS_K_I,\r\n\tinput [7:0] TX_CHAR_DISPMODE_I,\r\n\tinput [7:0] TX_CHAR_DISPVAL_I,\r\n\tinput TX_ELEC_IDLE_I,\r\n\tinput TX_DETECT_RX_I,\r\n\tinput [2:0] LOOPBACK_I,\r\n\tinput TX_CLK_I,\r\n\tinput RX_CLK_I,\r\n\tinput RX_RESET_I,\r\n\tinput RX_PMA_RESET_I,\r\n\tinput RX_EQA_RESET_I,\r\n\tinput RX_CDR_RESET_I,\r\n\tinput RX_PCS_RESET_I,\r\n\tinput RX_BUF_RESET_I,\r\n\tinput RX_POWER_DOWN_N_I,\r\n\tinput RX_POLARITY_I,\r\n\tinput [2:0] RX_PRBS_SEL_I,\r\n\tinput RX_PRBS_CNT_RESET_I,\r\n\tinput RX_8B10B_EN_I,\r\n\tinput [7:0] RX_8B10B_BYPASS_I,\r\n\tinput RX_EN_EI_DETECTOR_I,\r\n\tinput RX_COMMA_DETECT_EN_I,\r\n\tinput RX_SLIDE_I,\r\n\tinput RX_MCOMMA_ALIGN_I,\r\n\tinput RX_PCOMMA_ALIGN_I,\r\n\tinput REGFILE_CLK_I,\r\n\tinput REGFILE_WE_I,\r\n\tinput REGFILE_EN_I,\r\n\tinput [7:0] REGFILE_ADDR_I,\r\n\tinput [15:0] REGFILE_DI_I,\r\n\tinput [15:0] REGFILE_MASK_I,\r\n\toutput [63:0] RX_DATA_O,\r\n\toutput [7:0] RX_NOT_IN_TABLE_O,\r\n\toutput [7:0] RX_CHAR_IS_COMMA_O,\r\n\toutput [7:0] RX_CHAR_IS_K_O,\r\n\toutput [7:0] RX_DISP_ERR_O,\r\n\toutput TX_DETECT_RX_DONE_O,\r\n\toutput TX_DETECT_RX_PRESENT_O,\r\n\toutput TX_BUF_ERR_O,\r\n\toutput TX_RESET_DONE_O,\r\n\toutput RX_PRBS_ERR_O,\r\n\toutput RX_BUF_ERR_O,\r\n\toutput RX_BYTE_IS_ALIGNED_O,\r\n\toutput RX_BYTE_REALIGN_O,\r\n\toutput RX_RESET_DONE_O,\r\n\toutput RX_EI_EN_O,\r\n\toutput RX_CLK_O,\r\n\toutput PLL_CLK_O,\r\n\toutput [15:0] REGFILE_DO_O,\r\n\toutput REGFILE_RDY_O\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_CFG_CTRL(\r\n\tinput [7:0] DATA,\r\n\tinput CLK,\r\n\tinput EN,\r\n\tinput RECFG,\r\n\tinput VALID\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_USR_RSTN (\r\n\toutput USR_RSTN\r\n);\r\nendmodule\r\n",
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"cells_sim.v": "/*\r\n * yosys -- Yosys Open SYnthesis Suite\r\n *\r\n * Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>\r\n *\r\n * Permission to use, copy, modify, and/or distribute this software for any\r\n * purpose with or without fee is hereby granted, provided that the above\r\n * copyright notice and this permission notice appear in all copies.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\n`timescale 1ps/1ps\r\n\r\nmodule CC_IBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\tparameter [0:0] SCHMITT_TRIGGER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx\r\n)(\r\n\t(* iopad_external_pin *)\r\n\tinput I,\r\n\toutput Y\r\n);\r\n\tassign Y = I;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_OBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A,\r\n\t(* iopad_external_pin *)\r\n\toutput O\r\n);\r\n\tassign O = A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_TOBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\t(* iopad_external_pin *)\r\n\toutput O\r\n);\r\n\tassign O = T ? 1'bz : A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_IOBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\tparameter [0:0] SCHMITT_TRIGGER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\toutput Y,\r\n\t(* iopad_external_pin *)\r\n\tinout IO\r\n);\r\n\tassign IO = T ? 1'bz : A;\r\n\tassign Y = IO;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_IBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_RTERM = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx\r\n)(\r\n\t(* iopad_external_pin *)\r\n\tinput I_P, I_N,\r\n\toutput Y\r\n);\r\n\tassign Y = I_P;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_OBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A,\r\n\t(* iopad_external_pin *)\r\n\toutput O_P, O_N\r\n);\r\n\tassign O_P = A;\r\n\tassign O_N = ~A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_TOBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\t(* iopad_external_pin *)\r\n\toutput O_P, O_N\r\n);\r\n\tassign O_P = T ? 1'bz : A;\r\n\tassign O_N = T ? 1'bz : ~A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_IOBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_RTERM = 1'bx,\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\t(* iopad_external_pin *)\r\n\tinout IO_P, IO_N,\r\n\toutput Y\r\n);\r\n\tassign IO_P = T ? 1'bz : A;\r\n\tassign IO_N = T ? 1'bz : ~A;\r\n\tassign Y = IO_P;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_IDDR #(\r\n\tparameter [0:0] CLK_INV = 1'b0\r\n)(\r\n\tinput D,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\toutput reg Q0, Q1\r\n);\r\n\twire clk;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\r\n\talways @(posedge clk)\r\n\tbegin\r\n\t\tQ0 <= D;\r\n\tend\r\n\r\n\talways @(negedge clk)\r\n\tbegin\r\n\t\tQ1 <= D;\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_ODDR #(\r\n\tparameter [0:0] CLK_INV = 1'b0\r\n)(\r\n\tinput D0,\r\n\tinput D1,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput DDR,\r\n\toutput Q\r\n);\r\n\twire clk;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\r\n\treg q0, q1;\r\n\tassign Q = (DDR) ? q0 : q1;\r\n\r\n\talways @(posedge clk)\r\n\tbegin\r\n\t\tq0 <= D0;\r\n\tend\r\n\r\n\talways @(negedge clk)\r\n\tbegin\r\n\t\tq1 <= D1;\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_DFF #(\r\n\tparameter [0:0] CLK_INV = 1'b0,\r\n\tparameter [0:0] EN_INV = 1'b0,\r\n\tparameter [0:0] SR_INV = 1'b0,\r\n\tparameter [0:0] SR_VAL = 1'b0,\r\n\tparameter [0:0] INIT = 1'bx\r\n)(\r\n\tinput D,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\tinput EN,\r\n\tinput SR,\r\n\toutput reg Q\r\n);\r\n\twire clk, en, sr;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\tassign en = (EN_INV) ? ~EN : EN;\r\n\tassign sr = (SR_INV) ? ~SR : SR;\r\n\r\n\tinitial Q = INIT;\r\n\r\n\talways @(posedge clk or posedge sr)\r\n\tbegin\r\n\t\tif (sr) begin\r\n\t\t\tQ <= SR_VAL;\r\n\t\tend\r\n\t\telse if (en) begin\r\n\t\t\tQ <= D;\r\n\t\tend\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_DLT #(\r\n\tparameter [0:0] G_INV = 1'b0,\r\n\tparameter [0:0] SR_INV = 1'b0,\r\n\tparameter [0:0] SR_VAL = 1'b0,\r\n\tparameter [0:0] INIT = 1'bx\r\n)(\r\n\tinput D,\r\n\tinput G,\r\n\tinput SR,\r\n\toutput reg Q\r\n);\r\n\twire en, sr;\r\n\tassign en = (G_INV) ? ~G : G;\r\n\tassign sr = (SR_INV) ? ~SR : SR;\r\n\r\n\tinitial Q = INIT;\r\n\r\n\talways @(*)\r\n\tbegin\r\n\t\tif (sr) begin\r\n\t\t\tQ <= SR_VAL;\r\n\t\tend\r\n\t\telse if (en) begin\r\n\t\t\tQ <= D;\r\n\t\tend\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT1 (\r\n\toutput O,\r\n\tinput I0\r\n);\r\n\tparameter [1:0] INIT = 0;\r\n\r\n\tassign O = I0 ? INIT[1] : INIT[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT2 (\r\n\toutput O,\r\n\tinput I0, I1\r\n);\r\n\tparameter [3:0] INIT = 0;\r\n\r\n\twire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT3 (\r\n\toutput O,\r\n\tinput I0, I1, I2\r\n);\r\n\tparameter [7:0] INIT = 0;\r\n\r\n\twire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];\r\n\twire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT4 (\r\n\toutput O,\r\n\tinput I0, I1, I2, I3\r\n);\r\n\tparameter [15:0] INIT = 0;\r\n\r\n\twire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];\r\n\twire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];\r\n\twire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX2 (\r\n\tinput D0, D1,\r\n\tinput S0,\r\n\toutput Y\r\n);\r\n\tassign Y = S0 ? D1 : D0;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX4 (\r\n\tinput D0, D1, D2, D3,\r\n\tinput S0, S1,\r\n\toutput Y\r\n);\r\n\tassign Y = S1 ? (S0 ? D3 : D2) :\r\n\t\t\t\t\t(S0 ? D1 : D0);\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX8 (\r\n\tinput D0, D1, D2, D3,\r\n\tinput D4, D5, D6, D7,\r\n\tinput S0, S1, S2,\r\n\toutput Y\r\n);\r\n\tassign Y = S2 ? (S1 ? (S0 ? D7 : D6) :\r\n\t\t\t\t\t\t (S0 ? D5 : D4)) :\r\n\t\t\t\t\t(S1 ? (S0 ? D3 : D2) :\r\n\t\t\t\t\t\t (S0 ? D1 : D0));\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_ADDF (\r\n\tinput A, B, CI,\r\n\toutput CO, S\r\n);\r\n\tassign {CO, S} = A + B + CI;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MULT #(\r\n\tparameter A_WIDTH = 0,\r\n\tparameter B_WIDTH = 0,\r\n\tparameter P_WIDTH = 0\r\n)(\r\n\tinput signed [A_WIDTH-1:0] A,\r\n\tinput signed [B_WIDTH-1:0] B,\r\n\toutput reg signed [P_WIDTH-1:0] P\r\n);\r\n\talways @(*)\r\n\tbegin\r\n\t\tP <= A * B;\r\n\tend\r\nendmodule\r\n\r\n\r\nmodule CC_BUFG (\r\n\tinput I,\r\n\t(* clkbuf_driver *)\r\n\toutput O\r\n);\r\n\tassign O = I;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_BRAM_20K (\r\n\toutput [19:0] A_DO,\r\n\toutput [19:0] B_DO,\r\n\toutput ECC_1B_ERR,\r\n\toutput ECC_2B_ERR,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput A_EN,\r\n\tinput B_EN,\r\n\tinput A_WE,\r\n\tinput B_WE,\r\n\tinput [15:0] A_ADDR,\r\n\tinput [15:0] B_ADDR,\r\n\tinput [19:0] A_DI,\r\n\tinput [19:0] B_DI,\r\n\tinput [19:0] A_BM,\r\n\tinput [19:0] B_BM\r\n);\r\n\t// Location format: D(0..N-1)(0..N-1)X(0..3)Y(0..7)Z(0..1) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\r\n\t// Port Widths\r\n\tparameter A_RD_WIDTH = 0;\r\n\tparameter B_RD_WIDTH = 0;\r\n\tparameter A_WR_WIDTH = 0;\r\n\tparameter B_WR_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"SDP\";\r\n\tparameter A_WR_MODE = \"NO_CHANGE\";\r\n\tparameter B_WR_MODE = \"NO_CHANGE\";\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter ECC_EN = 1'b0;\r\n\r\n\t// RAM Contents\r\n\tparameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\r\n\tlocalparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH;\r\n\tlocalparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 40 bit\r\n\treg [20479:0] memory = 20480'b0;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WR_MODE != \"WRITE_THROUGH\") && (A_WR_MODE != \"NO_CHANGE\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (A_WR_MODE == \"WRITE_THROUGH\")) begin\r\n\t\t\t$display(\"ERROR: %s is not supported in %s mode.\", A_WR_MODE, RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif (ECC_EN != 1'b0) begin\r\n\t\t\t$display(\"WARNING: ECC feature not supported in simulation.\");\r\n\t\tend\r\n\t\tif ((ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (WIDTH_MODE_A != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port configuration. Must be SDP 40 bit, but is %s %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A == 40) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 40 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B == 40) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 40 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&\r\n\t\t\t(WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) &&\r\n\t\t\t(WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, WIDTH_MODE_B);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// RAM initialization\r\n\t\tmemory[320*0+319:320*0] = INIT_00;\r\n\t\tmemory[320*1+319:320*1] = INIT_01;\r\n\t\tmemory[320*2+319:320*2] = INIT_02;\r\n\t\tmemory[320*3+319:320*3] = INIT_03;\r\n\t\tmemory[320*4+319:320*4] = INIT_04;\r\n\t\tmemory[320*5+319:320*5] = INIT_05;\r\n\t\tmemory[320*6+319:320*6] = INIT_06;\r\n\t\tmemory[320*7+319:320*7] = INIT_07;\r\n\t\tmemory[320*8+319:320*8] = INIT_08;\r\n\t\tmemory[320*9+319:320*9] = INIT_09;\r\n\t\tmemory[320*10+319:320*10] = INIT_0A;\r\n\t\tmemory[320*11+319:320*11] = INIT_0B;\r\n\t\tmemory[320*12+319:320*12] = INIT_0C;\r\n\t\tmemory[320*13+319:320*13] = INIT_0D;\r\n\t\tmemory[320*14+319:320*14] = INIT_0E;\r\n\t\tmemory[320*15+319:320*15] = INIT_0F;\r\n\t\tmemory[320*16+319:320*16] = INIT_10;\r\n\t\tmemory[320*17+319:320*17] = INIT_11;\r\n\t\tmemory[320*18+319:320*18] = INIT_12;\r\n\t\tmemory[320*19+319:320*19] = INIT_13;\r\n\t\tmemory[320*20+319:320*20] = INIT_14;\r\n\t\tmemory[320*21+319:320*21] = INIT_15;\r\n\t\tmemory[320*22+319:320*22] = INIT_16;\r\n\t\tmemory[320*23+319:320*23] = INIT_17;\r\n\t\tmemory[320*24+319:320*24] = INIT_18;\r\n\t\tmemory[320*25+319:320*25] = INIT_19;\r\n\t\tmemory[320*26+319:320*26] = INIT_1A;\r\n\t\tmemory[320*27+319:320*27] = INIT_1B;\r\n\t\tmemory[320*28+319:320*28] = INIT_1C;\r\n\t\tmemory[320*29+319:320*29] = INIT_1D;\r\n\t\tmemory[320*30+319:320*30] = INIT_1E;\r\n\t\tmemory[320*31+319:320*31] = INIT_1F;\r\n\t\tmemory[320*32+319:320*32] = INIT_20;\r\n\t\tmemory[320*33+319:320*33] = INIT_21;\r\n\t\tmemory[320*34+319:320*34] = INIT_22;\r\n\t\tmemory[320*35+319:320*35] = INIT_23;\r\n\t\tmemory[320*36+319:320*36] = INIT_24;\r\n\t\tmemory[320*37+319:320*37] = INIT_25;\r\n\t\tmemory[320*38+319:320*38] = INIT_26;\r\n\t\tmemory[320*39+319:320*39] = INIT_27;\r\n\t\tmemory[320*40+319:320*40] = INIT_28;\r\n\t\tmemory[320*41+319:320*41] = INIT_29;\r\n\t\tmemory[320*42+319:320*42] = INIT_2A;\r\n\t\tmemory[320*43+319:320*43] = INIT_2B;\r\n\t\tmemory[320*44+319:320*44] = INIT_2C;\r\n\t\tmemory[320*45+319:320*45] = INIT_2D;\r\n\t\tmemory[320*46+319:320*46] = INIT_2E;\r\n\t\tmemory[320*47+319:320*47] = INIT_2F;\r\n\t\tmemory[320*48+319:320*48] = INIT_30;\r\n\t\tmemory[320*49+319:320*49] = INIT_31;\r\n\t\tmemory[320*50+319:320*50] = INIT_32;\r\n\t\tmemory[320*51+319:320*51] = INIT_33;\r\n\t\tmemory[320*52+319:320*52] = INIT_34;\r\n\t\tmemory[320*53+319:320*53] = INIT_35;\r\n\t\tmemory[320*54+319:320*54] = INIT_36;\r\n\t\tmemory[320*55+319:320*55] = INIT_37;\r\n\t\tmemory[320*56+319:320*56] = INIT_38;\r\n\t\tmemory[320*57+319:320*57] = INIT_39;\r\n\t\tmemory[320*58+319:320*58] = INIT_3A;\r\n\t\tmemory[320*59+319:320*59] = INIT_3B;\r\n\t\tmemory[320*60+319:320*60] = INIT_3C;\r\n\t\tmemory[320*61+319:320*61] = INIT_3D;\r\n\t\tmemory[320*62+319:320*62] = INIT_3E;\r\n\t\tmemory[320*63+319:320*63] = INIT_3F;\r\n\tend\r\n\r\n\t// Signal inversion\r\n\twire clka = A_CLK_INV ^ A_CLK;\r\n\twire clkb = B_CLK_INV ^ B_CLK;\r\n\twire ena = A_EN_INV ^ A_EN;\r\n\twire enb = B_EN_INV ^ B_EN;\r\n\twire wea = A_WE_INV ^ A_WE;\r\n\twire web = B_WE_INV ^ B_WE;\r\n\r\n\t// Internal signals\r\n\twire [15:0] addra;\r\n\twire [15:0] addrb;\r\n\treg [19:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg [19:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// Port A (write)\r\n\t\t\tif (A_WR_WIDTH == 40) begin\r\n\t\t\t\tassign addra = A_ADDR[15:7]*40;\r\n\t\t\tend\r\n\t\t\t// Port B (read)\r\n\t\t\tif (B_RD_WIDTH == 40) begin\r\n\t\t\t\tassign addrb = B_ADDR[15:7]*40;\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// Port A\r\n\t\t\tif (WIDTH_MODE_A <= 1) begin\r\n\t\t\t\twire [15:0] tmpa = {2'b0, A_ADDR[15:7], A_ADDR[5:1]};\r\n\t\t\t\tassign addra = tmpa + (tmpa/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 2) begin\r\n\t\t\t\twire [15:0] tmpa = {3'b0, A_ADDR[15:7], A_ADDR[5:2]};\r\n\t\t\t\tassign addra = tmpa*2 + (tmpa/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 5) begin\r\n\t\t\t\tassign addra = {4'b0, A_ADDR[15:7], A_ADDR[5:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 10) begin\r\n\t\t\t\tassign addra = {5'b0, A_ADDR[15:7], A_ADDR[5:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 20) begin\r\n\t\t\t\tassign addra = {6'b0, A_ADDR[15:7], A_ADDR[5]}*20;\r\n\t\t\tend\r\n\t\t\t// Port B\r\n\t\t\tif (WIDTH_MODE_B <= 1) begin\r\n\t\t\t\twire [15:0] tmpb = {2'b0, B_ADDR[15:7], B_ADDR[5:1]};\r\n\t\t\t\tassign addrb = tmpb + (tmpb/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 2) begin\r\n\t\t\t\twire [15:0] tmpb = {3'b0, B_ADDR[15:7], B_ADDR[5:2]};\r\n\t\t\t\tassign addrb = tmpb*2 + (tmpb/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 5) begin\r\n\t\t\t\tassign addrb = {4'b0, B_ADDR[15:7], B_ADDR[5:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 10) begin\r\n\t\t\t\tassign addrb = {5'b0, B_ADDR[15:7], B_ADDR[5:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 20) begin\r\n\t\t\t\tassign addrb = {6'b0, B_ADDR[15:7], B_ADDR[5]}*20;\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP write port\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WR_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 20) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ena && wea && B_BM[k-20]) memory[addra+k] <= B_DI[k-20];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP read port\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_RD_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 20) begin\r\n\t\t\t\t\t\tif (enb) A_DO_out[k] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (enb) B_DO_out[k-20] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// TDP port A\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_A; i=i+1) begin\r\n\t\t\t\t\tif (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i];\r\n\r\n\t\t\t\t\tif (A_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (ena && !wea) A_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (A_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (ena) begin\r\n\t\t\t\t\t\t\tif (wea && A_BM[i]) begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= A_DI[i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP port B\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_B; i=i+1) begin\r\n\t\t\t\t\tif (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i];\r\n\r\n\t\t\t\t\tif (B_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (enb && !web) B_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (B_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (enb) begin\r\n\t\t\t\t\t\t\tif (web && B_BM[i]) begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= B_DI[i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge clka) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge clkb) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\n\r\nmodule CC_BRAM_40K (\r\n\toutput [39:0] A_DO,\r\n\toutput [39:0] B_DO,\r\n\toutput A_ECC_1B_ERR,\r\n\toutput B_ECC_1B_ERR,\r\n\toutput A_ECC_2B_ERR,\r\n\toutput B_ECC_2B_ERR,\r\n\toutput reg A_CO = 0,\r\n\toutput reg B_CO = 0,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput A_EN,\r\n\tinput B_EN,\r\n\tinput A_WE,\r\n\tinput B_WE,\r\n\tinput [15:0] A_ADDR,\r\n\tinput [15:0] B_ADDR,\r\n\tinput [39:0] A_DI,\r\n\tinput [39:0] B_DI,\r\n\tinput [39:0] A_BM,\r\n\tinput [39:0] B_BM,\r\n\tinput A_CI,\r\n\tinput B_CI\r\n);\r\n\t// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\tparameter CAS = \"NONE\"; // NONE, UPPER, LOWER\r\n\r\n\t// Port Widths\r\n\tparameter A_RD_WIDTH = 0;\r\n\tparameter B_RD_WIDTH = 0;\r\n\tparameter A_WR_WIDTH = 0;\r\n\tparameter B_WR_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"SDP\";\r\n\tparameter A_WR_MODE = \"NO_CHANGE\";\r\n\tparameter B_WR_MODE = \"NO_CHANGE\";\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter A_ECC_EN = 1'b0;\r\n\tparameter B_ECC_EN = 1'b0;\r\n\r\n\tparameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_40 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_41 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_42 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_43 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_44 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_45 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_46 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_47 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_48 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_49 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_50 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_51 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_52 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_53 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_54 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_55 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_56 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_57 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_58 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_59 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_60 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_61 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_62 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_63 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_64 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_65 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_66 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_67 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_68 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_69 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_70 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_71 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_72 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_73 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_74 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_75 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_76 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_77 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_78 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_79 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\r\n\tlocalparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH;\r\n\tlocalparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 80 bit\r\n\treg [40959:0] memory = 40960'b0;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WR_MODE != \"WRITE_THROUGH\") && (A_WR_MODE != \"NO_CHANGE\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (A_WR_MODE == \"WRITE_THROUGH\")) begin\r\n\t\t\t$display(\"ERROR: %s is not supported in %s mode.\", A_WR_MODE, RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_ECC_EN != 1'b0) || (B_ECC_EN != 1'b0)) begin\r\n\t\t\t$display(\"WARNING: ECC feature not supported in simulation.\");\r\n\t\tend\r\n\t\tif ((A_ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (WIDTH_MODE_A != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port A configuration. Must be SDP 40 bit, but is %s %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&\r\n\t\t\t(WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B != 80) && (WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) &&\r\n\t\t\t(WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, WIDTH_MODE_B);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((CAS != \"NONE\") && ((WIDTH_MODE_A > 1) || (WIDTH_MODE_B > 1))) begin\r\n\t\t\t$display(\"ERROR: Cascade feature only supported in 1 bit data width mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((CAS != \"NONE\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Cascade feature only supported in TDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// RAM initialization\r\n\t\tmemory[320*0+319:320*0] = INIT_00;\r\n\t\tmemory[320*1+319:320*1] = INIT_01;\r\n\t\tmemory[320*2+319:320*2] = INIT_02;\r\n\t\tmemory[320*3+319:320*3] = INIT_03;\r\n\t\tmemory[320*4+319:320*4] = INIT_04;\r\n\t\tmemory[320*5+319:320*5] = INIT_05;\r\n\t\tmemory[320*6+319:320*6] = INIT_06;\r\n\t\tmemory[320*7+319:320*7] = INIT_07;\r\n\t\tmemory[320*8+319:320*8] = INIT_08;\r\n\t\tmemory[320*9+319:320*9] = INIT_09;\r\n\t\tmemory[320*10+319:320*10] = INIT_0A;\r\n\t\tmemory[320*11+319:320*11] = INIT_0B;\r\n\t\tmemory[320*12+319:320*12] = INIT_0C;\r\n\t\tmemory[320*13+319:320*13] = INIT_0D;\r\n\t\tmemory[320*14+319:320*14] = INIT_0E;\r\n\t\tmemory[320*15+319:320*15] = INIT_0F;\r\n\t\tmemory[320*16+319:320*16] = INIT_10;\r\n\t\tmemory[320*17+319:320*17] = INIT_11;\r\n\t\tmemory[320*18+319:320*18] = INIT_12;\r\n\t\tmemory[320*19+319:320*19] = INIT_13;\r\n\t\tmemory[320*20+319:320*20] = INIT_14;\r\n\t\tmemory[320*21+319:320*21] = INIT_15;\r\n\t\tmemory[320*22+319:320*22] = INIT_16;\r\n\t\tmemory[320*23+319:320*23] = INIT_17;\r\n\t\tmemory[320*24+319:320*24] = INIT_18;\r\n\t\tmemory[320*25+319:320*25] = INIT_19;\r\n\t\tmemory[320*26+319:320*26] = INIT_1A;\r\n\t\tmemory[320*27+319:320*27] = INIT_1B;\r\n\t\tmemory[320*28+319:320*28] = INIT_1C;\r\n\t\tmemory[320*29+319:320*29] = INIT_1D;\r\n\t\tmemory[320*30+319:320*30] = INIT_1E;\r\n\t\tmemory[320*31+319:320*31] = INIT_1F;\r\n\t\tmemory[320*32+319:320*32] = INIT_20;\r\n\t\tmemory[320*33+319:320*33] = INIT_21;\r\n\t\tmemory[320*34+319:320*34] = INIT_22;\r\n\t\tmemory[320*35+319:320*35] = INIT_23;\r\n\t\tmemory[320*36+319:320*36] = INIT_24;\r\n\t\tmemory[320*37+319:320*37] = INIT_25;\r\n\t\tmemory[320*38+319:320*38] = INIT_26;\r\n\t\tmemory[320*39+319:320*39] = INIT_27;\r\n\t\tmemory[320*40+319:320*40] = INIT_28;\r\n\t\tmemory[320*41+319:320*41] = INIT_29;\r\n\t\tmemory[320*42+319:320*42] = INIT_2A;\r\n\t\tmemory[320*43+319:320*43] = INIT_2B;\r\n\t\tmemory[320*44+319:320*44] = INIT_2C;\r\n\t\tmemory[320*45+319:320*45] = INIT_2D;\r\n\t\tmemory[320*46+319:320*46] = INIT_2E;\r\n\t\tmemory[320*47+319:320*47] = INIT_2F;\r\n\t\tmemory[320*48+319:320*48] = INIT_30;\r\n\t\tmemory[320*49+319:320*49] = INIT_31;\r\n\t\tmemory[320*50+319:320*50] = INIT_32;\r\n\t\tmemory[320*51+319:320*51] = INIT_33;\r\n\t\tmemory[320*52+319:320*52] = INIT_34;\r\n\t\tmemory[320*53+319:320*53] = INIT_35;\r\n\t\tmemory[320*54+319:320*54] = INIT_36;\r\n\t\tmemory[320*55+319:320*55] = INIT_37;\r\n\t\tmemory[320*56+319:320*56] = INIT_38;\r\n\t\tmemory[320*57+319:320*57] = INIT_39;\r\n\t\tmemory[320*58+319:320*58] = INIT_3A;\r\n\t\tmemory[320*59+319:320*59] = INIT_3B;\r\n\t\tmemory[320*60+319:320*60] = INIT_3C;\r\n\t\tmemory[320*61+319:320*61] = INIT_3D;\r\n\t\tmemory[320*62+319:320*62] = INIT_3E;\r\n\t\tmemory[320*63+319:320*63] = INIT_3F;\r\n\t\tmemory[320*64+319:320*64] = INIT_40;\r\n\t\tmemory[320*65+319:320*65] = INIT_41;\r\n\t\tmemory[320*66+319:320*66] = INIT_42;\r\n\t\tmemory[320*67+319:320*67] = INIT_43;\r\n\t\tmemory[320*68+319:320*68] = INIT_44;\r\n\t\tmemory[320*69+319:320*69] = INIT_45;\r\n\t\tmemory[320*70+319:320*70] = INIT_46;\r\n\t\tmemory[320*71+319:320*71] = INIT_47;\r\n\t\tmemory[320*72+319:320*72] = INIT_48;\r\n\t\tmemory[320*73+319:320*73] = INIT_49;\r\n\t\tmemory[320*74+319:320*74] = INIT_4A;\r\n\t\tmemory[320*75+319:320*75] = INIT_4B;\r\n\t\tmemory[320*76+319:320*76] = INIT_4C;\r\n\t\tmemory[320*77+319:320*77] = INIT_4D;\r\n\t\tmemory[320*78+319:320*78] = INIT_4E;\r\n\t\tmemory[320*79+319:320*79] = INIT_4F;\r\n\t\tmemory[320*80+319:320*80] = INIT_50;\r\n\t\tmemory[320*81+319:320*81] = INIT_51;\r\n\t\tmemory[320*82+319:320*82] = INIT_52;\r\n\t\tmemory[320*83+319:320*83] = INIT_53;\r\n\t\tmemory[320*84+319:320*84] = INIT_54;\r\n\t\tmemory[320*85+319:320*85] = INIT_55;\r\n\t\tmemory[320*86+319:320*86] = INIT_56;\r\n\t\tmemory[320*87+319:320*87] = INIT_57;\r\n\t\tmemory[320*88+319:320*88] = INIT_58;\r\n\t\tmemory[320*89+319:320*89] = INIT_59;\r\n\t\tmemory[320*90+319:320*90] = INIT_5A;\r\n\t\tmemory[320*91+319:320*91] = INIT_5B;\r\n\t\tmemory[320*92+319:320*92] = INIT_5C;\r\n\t\tmemory[320*93+319:320*93] = INIT_5D;\r\n\t\tmemory[320*94+319:320*94] = INIT_5E;\r\n\t\tmemory[320*95+319:320*95] = INIT_5F;\r\n\t\tmemory[320*96+319:320*96] = INIT_60;\r\n\t\tmemory[320*97+319:320*97] = INIT_61;\r\n\t\tmemory[320*98+319:320*98] = INIT_62;\r\n\t\tmemory[320*99+319:320*99] = INIT_63;\r\n\t\tmemory[320*100+319:320*100] = INIT_64;\r\n\t\tmemory[320*101+319:320*101] = INIT_65;\r\n\t\tmemory[320*102+319:320*102] = INIT_66;\r\n\t\tmemory[320*103+319:320*103] = INIT_67;\r\n\t\tmemory[320*104+319:320*104] = INIT_68;\r\n\t\tmemory[320*105+319:320*105] = INIT_69;\r\n\t\tmemory[320*106+319:320*106] = INIT_6A;\r\n\t\tmemory[320*107+319:320*107] = INIT_6B;\r\n\t\tmemory[320*108+319:320*108] = INIT_6C;\r\n\t\tmemory[320*109+319:320*109] = INIT_6D;\r\n\t\tmemory[320*110+319:320*110] = INIT_6E;\r\n\t\tmemory[320*111+319:320*111] = INIT_6F;\r\n\t\tmemory[320*112+319:320*112] = INIT_70;\r\n\t\tmemory[320*113+319:320*113] = INIT_71;\r\n\t\tmemory[320*114+319:320*114] = INIT_72;\r\n\t\tmemory[320*115+319:320*115] = INIT_73;\r\n\t\tmemory[320*116+319:320*116] = INIT_74;\r\n\t\tmemory[320*117+319:320*117] = INIT_75;\r\n\t\tmemory[320*118+319:320*118] = INIT_76;\r\n\t\tmemory[320*119+319:320*119] = INIT_77;\r\n\t\tmemory[320*120+319:320*120] = INIT_78;\r\n\t\tmemory[320*121+319:320*121] = INIT_79;\r\n\t\tmemory[320*122+319:320*122] = INIT_7A;\r\n\t\tmemory[320*123+319:320*123] = INIT_7B;\r\n\t\tmemory[320*124+319:320*124] = INIT_7C;\r\n\t\tmemory[320*125+319:320*125] = INIT_7D;\r\n\t\tmemory[320*126+319:320*126] = INIT_7E;\r\n\t\tmemory[320*127+319:320*127] = INIT_7F;\r\n\tend\r\n\r\n\t// Signal inversion\r\n\twire clka = A_CLK_INV ^ A_CLK;\r\n\twire clkb = B_CLK_INV ^ B_CLK;\r\n\twire ena = A_EN_INV ^ A_EN;\r\n\twire enb = B_EN_INV ^ B_EN;\r\n\twire wea = A_WE_INV ^ A_WE;\r\n\twire web = B_WE_INV ^ B_WE;\r\n\r\n\t// Internal signals\r\n\twire [15:0] addra;\r\n\twire [15:0] addrb;\r\n\treg [39:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg [39:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// Port A (write)\r\n\t\t\t if (A_WR_WIDTH == 80) begin\r\n\t\t\t\tassign addra = A_ADDR[15:7]*80;\r\n\t\t\tend\r\n\t\t\t// Port B (read)\r\n\t\t\tif (B_RD_WIDTH == 80) begin\r\n\t\t\t\tassign addrb = B_ADDR[15:7]*80;\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// Port A\r\n\t\t\tif (WIDTH_MODE_A <= 1) begin\r\n\t\t\t\twire [15:0] tmpa = {1'b0, A_ADDR[15:1]};\r\n\t\t\t\tassign addra = tmpa + (tmpa/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 2) begin\r\n\t\t\t\twire [15:0] tmpa = {2'b0, A_ADDR[15:2]};\r\n\t\t\t\tassign addra = tmpa*2 + (tmpa/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 5) begin\r\n\t\t\t\tassign addra = {3'b0, A_ADDR[15:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 10) begin\r\n\t\t\t\tassign addra = {4'b0, A_ADDR[15:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 20) begin\r\n\t\t\t\tassign addra = {5'b0, A_ADDR[15:5]}*20;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 40) begin\r\n\t\t\t\tassign addra = {6'b0, A_ADDR[15:6]}*40;\r\n\t\t\tend\r\n\t\t\t// Port B\r\n\t\t\tif (WIDTH_MODE_B <= 1) begin\r\n\t\t\t\twire [15:0] tmpb = {1'b0, B_ADDR[15:1]};\r\n\t\t\t\tassign addrb = tmpb + (tmpb/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 2) begin\r\n\t\t\t\twire [15:0] tmpb = {2'b0, B_ADDR[15:2]};\r\n\t\t\t\tassign addrb = tmpb*2 + (tmpb/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 5) begin\r\n\t\t\t\tassign addrb = {3'b0, B_ADDR[15:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 10) begin\r\n\t\t\t\tassign addrb = {4'b0, B_ADDR[15:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 20) begin\r\n\t\t\t\tassign addrb = {5'b0, B_ADDR[15:5]}*20;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 40) begin\r\n\t\t\t\tassign addrb = {6'b0, B_ADDR[15:6]}*40;\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP write port\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WR_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ena && wea && B_BM[k-40]) memory[addra+k] <= B_DI[k-40];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP read port\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_RD_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (enb) A_DO_out[k] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (enb) B_DO_out[k-40] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// {A,B}_ADDR[0]=0 selects lower, {A,B}_ADDR[0]=1 selects upper cascade memory\r\n\t\t\twire upper_sel_a = ((CAS == \"UPPER\") && (A_ADDR[0] == 1));\r\n\t\t\twire lower_sel_a = ((CAS == \"LOWER\") && (A_ADDR[0] == 0));\r\n\t\t\twire upper_sel_b = ((CAS == \"UPPER\") && (B_ADDR[0] == 1));\r\n\t\t\twire lower_sel_b = ((CAS == \"LOWER\") && (B_ADDR[0] == 0));\r\n\r\n\t\t\treg dumm;\r\n\r\n\t\t\t// Cascade output port A\r\n\t\t\talways @(*)\r\n\t\t\tbegin\r\n\t\t\t\tif ((A_WR_MODE == \"NO_CHANGE\") && lower_sel_a) begin\r\n\t\t\t\t\tA_CO = memory[addra];\r\n\t\t\t\tend\r\n\t\t\t\telse if ((A_WR_MODE == \"WRITE_THROUGH\") && lower_sel_a) begin\r\n\t\t\t\t\tA_CO = ((wea && A_BM[0]) ? (A_DI[0]) : (memory[addra]));\r\n\t\t\t\tend\r\n\t\t\tend\r\n\r\n\t\t\t// Cascade output port B\r\n\t\t\talways @(*)\r\n\t\t\tbegin\r\n\t\t\t\tif ((B_WR_MODE == \"NO_CHANGE\") && lower_sel_b) begin\r\n\t\t\t\t\tB_CO = memory[addrb];\r\n\t\t\t\tend\r\n\t\t\t\telse if ((B_WR_MODE == \"WRITE_THROUGH\") && lower_sel_b) begin\r\n\t\t\t\t\tB_CO = ((web && B_BM[0]) ? (B_DI[0]) : (memory[addrb]));\r\n\t\t\t\tend\r\n\t\t\tend\r\n\r\n\t\t\t// TDP port A\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_A; i=i+1) begin\r\n\t\t\t\t\tif (upper_sel_a || lower_sel_a || (CAS == \"NONE\")) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[i])\r\n\t\t\t\t\t\t\tmemory[addra+i] <= A_DI[i];\r\n\t\t\t\t\tend\r\n\r\n\t\t\t\t\tif (A_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (ena && !wea) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= ((A_ADDR[0] == 1) ? (memory[addra+i]) : (A_CI));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (A_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (ena) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tif (A_ADDR[0] == 1) begin\r\n\t\t\t\t\t\t\t\t\tA_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));\r\n\t\t\t\t\t\t\t\tend else begin\r\n\t\t\t\t\t\t\t\t\tA_DO_out[i] <= A_CI;\r\n\t\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP port B\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_B; i=i+1) begin\r\n\t\t\t\t\tif (upper_sel_b || lower_sel_b || (CAS == \"NONE\")) begin\r\n\t\t\t\t\t\tif (enb && web && B_BM[i])\r\n\t\t\t\t\t\t\tmemory[addrb+i] <= B_DI[i];\r\n\t\t\t\t\tend\r\n\r\n\t\t\t\t\tif (B_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (enb && !web) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= ((B_ADDR[0] == 1) ? (memory[addrb+i]) : (B_CI));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (B_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (enb) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tif (B_ADDR[0] == 1) begin\r\n\t\t\t\t\t\t\t\t\tB_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));\r\n\t\t\t\t\t\t\t\tend else begin\r\n\t\t\t\t\t\t\t\t\tB_DO_out[i] <= B_CI;\r\n\t\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge clka) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge clkb) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\nmodule CC_FIFO_40K (\r\n\toutput A_ECC_1B_ERR,\r\n\toutput B_ECC_1B_ERR,\r\n\toutput A_ECC_2B_ERR,\r\n\toutput B_ECC_2B_ERR,\r\n\t// FIFO pop port\r\n\toutput [39:0] A_DO,\r\n\toutput [39:0] B_DO,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\tinput A_EN,\r\n\t// FIFO push port\r\n\tinput [39:0] A_DI,\r\n\tinput [39:0] B_DI,\r\n\tinput [39:0] A_BM,\r\n\tinput [39:0] B_BM,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput B_EN,\r\n\tinput B_WE,\r\n\t// FIFO control\r\n\tinput F_RST_N,\r\n\tinput [14:0] F_ALMOST_FULL_OFFSET,\r\n\tinput [14:0] F_ALMOST_EMPTY_OFFSET,\r\n\t// FIFO status signals\r\n\toutput F_FULL,\r\n\toutput F_EMPTY,\r\n\toutput F_ALMOST_FULL,\r\n\toutput F_ALMOST_EMPTY,\r\n\toutput F_RD_ERROR,\r\n\toutput F_WR_ERROR,\r\n\toutput [15:0] F_RD_PTR,\r\n\toutput [15:0] F_WR_PTR\r\n);\r\n\t// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\r\n\t// Offset configuration\r\n\tparameter DYN_STAT_SELECT = 1'b0;\r\n\tparameter [14:0] ALMOST_FULL_OFFSET = 15'b0;\r\n\tparameter [14:0] ALMOST_EMPTY_OFFSET = 15'b0;\r\n\r\n\t// Port Widths\r\n\tparameter A_WIDTH = 0;\r\n\tparameter B_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"TDP\"; // \"TDP\" or \"SDP\"\r\n\tparameter FIFO_MODE = \"SYNC\"; // \"ASYNC\" or \"SYNC\"\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter A_ECC_EN = 1'b0;\r\n\tparameter B_ECC_EN = 1'b0;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 80 bit\r\n\treg [40959:0] memory = 40960'b0;\r\n\r\n\treg [15:0] counter_max;\r\n\treg [15:0] sram_depth;\r\n\tlocalparam tp = (A_WIDTH == 1) ? 15 :\r\n\t\t\t\t\t(A_WIDTH == 2) ? 14 :\r\n\t\t\t\t\t(A_WIDTH == 5) ? 13 :\r\n\t\t\t\t\t(A_WIDTH == 10) ? 12 :\r\n\t\t\t\t\t(A_WIDTH == 20) ? 11 :\r\n\t\t\t\t\t(A_WIDTH == 40) ? 10 : 9;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((FIFO_MODE != \"ASYNC\") && (FIFO_MODE != \"SYNC\")) begin\r\n\t\t\t$display(\"ERROR: Illegal FIFO MODE %d.\", FIFO_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (DYN_STAT_SELECT == 1)) begin\r\n\t\t\t$display(\"ERROR: Dynamic offset configuration is not supported in %s mode.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && ((A_WIDTH != 80) || (B_WIDTH != 80))) begin\r\n\t\t\t$display(\"ERROR: SDP is ony supported in 80 bit mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WIDTH == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((B_WIDTH == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WIDTH != 80) && (A_WIDTH != 40) && (A_WIDTH != 20) && (A_WIDTH != 10) &&\r\n\t\t\t(A_WIDTH != 5) && (A_WIDTH != 2) && (A_WIDTH != 1) && (A_WIDTH != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, A_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((B_WIDTH != 80) && (B_WIDTH != 40) && (B_WIDTH != 20) && (B_WIDTH != 10) &&\r\n\t\t\t(B_WIDTH != 5) && (B_WIDTH != 2) && (B_WIDTH != 1) && (B_WIDTH != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, B_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif (A_WIDTH != B_WIDTH) begin\r\n\t\t\t$display(\"ERROR: The values of A_WIDTH and B_WIDTH must be equal.\");\r\n\t\tend\r\n\t\tif ((A_ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (A_WIDTH != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port A configuration. ECC mode requires TDP >=40 bit or SDP 80 bit, but is %s %d.\", RAM_MODE, A_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// Set local parameters\r\n\t\tif (A_WIDTH == 1) begin // A_WIDTH=B_WIDTH\r\n\t\t\tcounter_max = 2 * 32*1024 - 1;\r\n\t\t\tsram_depth = 32*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 2) begin\r\n\t\t\tcounter_max = 2 * 16*1024 - 1;\r\n\t\t\tsram_depth = 16*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 5) begin\r\n\t\t\tcounter_max = 2 * 8*1024 - 1;\r\n\t\t\tsram_depth = 8*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 10) begin\r\n\t\t\tcounter_max = 2 * 4*1024 - 1;\r\n\t\t\tsram_depth = 4*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 20) begin\r\n\t\t\tcounter_max = 2 * 2*1024 - 1;\r\n\t\t\tsram_depth = 2*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 40) begin\r\n\t\t\tcounter_max = 2 * 1*1024 - 1;\r\n\t\t\tsram_depth = 1*1024;\r\n\t\tend\r\n\t\telse begin // 80 bit SDP\r\n\t\t\tcounter_max = 2 * 512 - 1;\r\n\t\t\tsram_depth = 512;\r\n\t\tend\r\n\tend\r\n\r\n\t// Internal signals\r\n\twire fifo_rdclk = A_CLK ^ A_CLK_INV;\r\n\twire fifo_wrclk = (FIFO_MODE == \"ASYNC\") ? (B_CLK ^ B_CLK_INV) : (A_CLK ^ A_CLK_INV);\r\n\twire [15:0] almost_full_offset = DYN_STAT_SELECT ? F_ALMOST_FULL_OFFSET : ALMOST_FULL_OFFSET;\r\n\twire [15:0] almost_empty_offset = DYN_STAT_SELECT ? F_ALMOST_EMPTY_OFFSET : ALMOST_EMPTY_OFFSET;\r\n\treg [39:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg [39:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\t// Status signals\r\n\treg fifo_full;\r\n\treg fifo_empty;\r\n\treg fifo_almost_full;\r\n\treg fifo_almost_empty;\r\n\tassign F_FULL = fifo_full;\r\n\tassign F_EMPTY = fifo_empty;\r\n\tassign F_ALMOST_FULL = fifo_almost_full;\r\n\tassign F_ALMOST_EMPTY = fifo_almost_empty;\r\n\tassign F_WR_ERROR = (F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));\r\n\tassign F_RD_ERROR = (F_EMPTY && (A_EN ^ A_EN_INV));\r\n\twire ram_we = (~F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));\r\n\twire ram_en = (~F_EMPTY && (A_EN ^ A_EN_INV));\r\n\r\n\t// Reset synchronizers\r\n\treg [1:0] aclk_reset_q, bclk_reset_q;\r\n\twire fifo_sync_rstn = aclk_reset_q;\r\n\twire fifo_async_wrrstn = bclk_reset_q;\r\n\twire fifo_async_rdrstn = aclk_reset_q;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\taclk_reset_q <= 2'b0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\taclk_reset_q[1] <= aclk_reset_q[0];\r\n\t\t\taclk_reset_q[0] <= 1'b1;\r\n\t\tend\r\n\tend\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\tbclk_reset_q <= 2'b0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tbclk_reset_q[1] <= bclk_reset_q[0];\r\n\t\t\tbclk_reset_q[0] <= 1'b1;\r\n\t\tend\r\n\tend\r\n\r\n\t// Push/pop pointers\r\n\treg [15:0] rd_pointer, rd_pointer_int;\r\n\treg [15:0] wr_pointer, wr_pointer_int;\r\n\treg [15:0] rd_pointer_cmp, wr_pointer_cmp;\r\n\twire [15:0] rd_pointer_nxt;\r\n\twire [15:0] wr_pointer_nxt;\r\n\treg [15:0] fifo_rdaddr, rdaddr;\r\n\treg [15:0] fifo_wraddr, wraddr;\r\n\tassign F_RD_PTR = fifo_rdaddr;\r\n\tassign F_WR_PTR = fifo_wraddr;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\trd_pointer <= 0;\r\n\t\t\trd_pointer_int <= 0;\r\n\t\tend\r\n\t\telse if (ram_en) begin\r\n\t\t\trd_pointer <= rd_pointer_nxt;\r\n\t\t\trd_pointer_int <= rd_pointer_nxt[15:1] ^ rd_pointer_nxt[14:0];\r\n\t\tend\r\n\tend\r\n\r\n\tassign rd_pointer_nxt = (rd_pointer == counter_max) ? (0) : (rd_pointer + 1'b1);\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\twr_pointer <= 0;\r\n\t\t\twr_pointer_int <= 0;\r\n\t\tend\r\n\t\telse if (ram_we) begin\r\n\t\t\twr_pointer <= wr_pointer_nxt;\r\n\t\t\twr_pointer_int <= wr_pointer_nxt[15:1] ^ wr_pointer_nxt[14:0];\r\n\t\tend\r\n\tend\r\n\r\n\tassign wr_pointer_nxt = (wr_pointer == counter_max) ? (0) : (wr_pointer + 1'b1);\r\n\r\n\t// Address synchronizers\r\n\treg [15:0] rd_pointer_sync, wr_pointer_sync;\r\n\treg [15:0] rd_pointer_sync_0, rd_pointer_sync_1;\r\n\treg [15:0] wr_pointer_sync_0, wr_pointer_sync_1;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\twr_pointer_sync_0 <= 0;\r\n\t\t\twr_pointer_sync_1 <= 0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\twr_pointer_sync_0 <= wraddr;\r\n\t\t\twr_pointer_sync_1 <= wr_pointer_sync_0;\r\n\t\tend\r\n\t end\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\t begin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\trd_pointer_sync_0 <= 0;\r\n\t\t\trd_pointer_sync_1 <= 0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\trd_pointer_sync_0 <= rdaddr;\r\n\t\t\trd_pointer_sync_1 <= rd_pointer_sync_0;\r\n\t\tend\r\n\t end\r\n\r\n\talways @(*) begin\r\n\t\tfifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}};\r\n\t\tfifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}};\r\n\r\n\t\trdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]};\r\n\t\twraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]};\r\n\r\n\t\tif (FIFO_MODE == \"ASYNC\")\r\n\t\t\tfifo_full = (wraddr[tp-2:0] == rd_pointer_sync_1[tp-2:0] ) && (wraddr[tp] != rd_pointer_sync_1[tp] ) && ( wraddr[tp-1] != rd_pointer_sync_1[tp-1] );\r\n\t\telse\r\n\t\t\tfifo_full = (wr_pointer[tp-1:0] == rd_pointer[tp-1:0]) && (wr_pointer[tp] ^ rd_pointer[tp]);\r\n\r\n\t\tif (FIFO_MODE == \"ASYNC\")\r\n\t\t\tfifo_empty = (wr_pointer_sync_1[tp:0] == rdaddr[tp:0]);\r\n\t\telse\r\n\t\t\tfifo_empty = (wr_pointer[tp:0] == rd_pointer[tp:0]);\r\n\r\n\t\trd_pointer_cmp = (FIFO_MODE == \"ASYNC\") ? rd_pointer_sync : rd_pointer;\r\n\t\tif (wr_pointer[tp] == rd_pointer_cmp[tp])\r\n\t\t\tfifo_almost_full = ((wr_pointer[tp-1:0] - rd_pointer_cmp[tp-1:0]) >= (sram_depth - almost_full_offset));\r\n\t\telse\r\n\t\t\tfifo_almost_full = ((rd_pointer_cmp[tp-1:0] - wr_pointer[tp-1:0]) <= almost_full_offset);\r\n\r\n\t\twr_pointer_cmp = (FIFO_MODE == \"ASYNC\") ? wr_pointer_sync : wr_pointer;\r\n\t\tif (wr_pointer_cmp[tp] == rd_pointer[tp])\r\n\t\t\tfifo_almost_empty = ((wr_pointer_cmp[tp-1:0] - rd_pointer[tp-1:0]) <= almost_empty_offset);\r\n\t\telse\r\n\t\t\tfifo_almost_empty = ((rd_pointer[tp-1:0] - wr_pointer_cmp[tp-1:0]) >= (sram_depth - almost_empty_offset));\r\n\tend\r\n\r\n\tgenerate\r\n\t\talways @(*) begin\r\n\t\t\twr_pointer_sync = 0;\r\n\t\t\trd_pointer_sync = 0;\r\n\t\t\tfor (i=tp; i >= 0; i=i-1) begin\r\n\t\t\t\tif (i == tp) begin\r\n\t\t\t\t\twr_pointer_sync[i] = wr_pointer_sync_1[i];\r\n\t\t\t\t\trd_pointer_sync[i] = rd_pointer_sync_1[i];\r\n\t\t\t\tend\r\n\t\t\t\telse begin\r\n\t\t\t\t\twr_pointer_sync[i] = wr_pointer_sync_1[i] ^ wr_pointer_sync[i+1];\r\n\t\t\t\t\trd_pointer_sync[i] = rd_pointer_sync_1[i] ^ rd_pointer_sync[i+1];\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP push ports A+B\r\n\t\t\talways @(posedge fifo_wrclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ram_we && A_BM[k]) memory[fifo_wraddr+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ram_we && B_BM[k-40]) memory[fifo_wraddr+k] <= B_DI[k-40];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP pop ports A+B\r\n\t\t\talways @(posedge fifo_rdclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ram_en) A_DO_out[k] <= memory[fifo_rdaddr+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ram_en) B_DO_out[k-40] <= memory[fifo_rdaddr+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// TDP pop port A\r\n\t\t\talways @(posedge fifo_rdclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < A_WIDTH; i=i+1) begin\r\n\t\t\t\t\tif (ram_en) begin\r\n\t\t\t\t\t\tA_DO_out[i] <= memory[fifo_rdaddr+i];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP push port B\r\n\t\t\talways @(posedge fifo_wrclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < B_WIDTH; i=i+1) begin\r\n\t\t\t\t\tif (ram_we && B_BM[i])\r\n\t\t\t\t\t\tmemory[fifo_wraddr+i] <= B_DI[i];\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge fifo_rdclk) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge fifo_rdclk) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\n// Models of the LUT2 tree primitives\r\nmodule CC_L2T4(\r\n\toutput O,\r\n\tinput I0, I1, I2, I3\r\n);\r\n\tparameter [3:0] INIT_L00 = 4'b0000;\r\n\tparameter [3:0] INIT_L01 = 4'b0000;\r\n\tparameter [3:0] INIT_L10 = 4'b0000;\r\n\r\n\twire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0];\r\n\twire l00 = I0 ? l00_s1[1] : l00_s1[0];\r\n\r\n\twire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0];\r\n\twire l01 = I2 ? l01_s1[1] : l01_s1[0];\r\n\r\n\twire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0];\r\n\tassign O = l00 ? l10_s1[1] : l10_s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_L2T5(\r\n\toutput O,\r\n\tinput I0, I1, I2, I3, I4\r\n);\r\n\tparameter [3:0] INIT_L02 = 4'b0000;\r\n\tparameter [3:0] INIT_L03 = 4'b0000;\r\n\tparameter [3:0] INIT_L11 = 4'b0000;\r\n\tparameter [3:0] INIT_L20 = 4'b0000;\r\n\r\n\twire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0];\r\n\twire l02 = I0 ? l02_s1[1] : l02_s1[0];\r\n\r\n\twire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0];\r\n\twire l03 = I2 ? l03_s1[1] : l03_s1[0];\r\n\r\n\twire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0];\r\n\twire l11 = l02 ? l11_s1[1] : l11_s1[0];\r\n\r\n\twire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0];\r\n\tassign O = I4 ? l20_s1[1] : l20_s1[0];\r\n\r\nendmodule\r\n",
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"cells_sim.v": "/*\r\n * yosys -- Yosys Open SYnthesis Suite\r\n *\r\n * Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>\r\n *\r\n * Permission to use, copy, modify, and/or distribute this software for any\r\n * purpose with or without fee is hereby granted, provided that the above\r\n * copyright notice and this permission notice appear in all copies.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\n`timescale 1ps/1ps\r\n\r\nmodule CC_IBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\tparameter [0:0] SCHMITT_TRIGGER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx\r\n)(\r\n\t(* iopad_external_pin *)\r\n\tinput I,\r\n\toutput Y\r\n);\r\n\tassign Y = I;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_OBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A,\r\n\t(* iopad_external_pin *)\r\n\toutput O\r\n);\r\n\tassign O = A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_TOBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\t(* iopad_external_pin *)\r\n\toutput O\r\n);\r\n\tassign O = T ? 1'bz : A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_IOBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\tparameter [0:0] SCHMITT_TRIGGER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\toutput Y,\r\n\t(* iopad_external_pin *)\r\n\tinout IO\r\n);\r\n\tassign IO = T ? 1'bz : A;\r\n\tassign Y = IO;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_IBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_RTERM = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx\r\n)(\r\n\t(* iopad_external_pin *)\r\n\tinput I_P, I_N,\r\n\toutput Y\r\n);\r\n\tassign Y = I_P;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_OBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A,\r\n\t(* iopad_external_pin *)\r\n\toutput O_P, O_N\r\n);\r\n\tassign O_P = A;\r\n\tassign O_N = ~A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_TOBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\t(* iopad_external_pin *)\r\n\toutput O_P, O_N\r\n);\r\n\tassign O_P = T ? 1'bz : A;\r\n\tassign O_N = T ? 1'bz : ~A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_IOBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_RTERM = 1'bx,\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput A, T,\r\n\t(* iopad_external_pin *)\r\n\tinout IO_P, IO_N,\r\n\toutput Y\r\n);\r\n\tassign IO_P = T ? 1'bz : A;\r\n\tassign IO_N = T ? 1'bz : ~A;\r\n\tassign Y = IO_P;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_IDDR #(\r\n\tparameter [0:0] CLK_INV = 1'b0\r\n)(\r\n\tinput D,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\toutput reg Q0, Q1\r\n);\r\n\twire clk;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\r\n\talways @(posedge clk)\r\n\tbegin\r\n\t\tQ0 <= D;\r\n\tend\r\n\r\n\talways @(negedge clk)\r\n\tbegin\r\n\t\tQ1 <= D;\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_ODDR #(\r\n\tparameter [0:0] CLK_INV = 1'b0\r\n)(\r\n\tinput D0,\r\n\tinput D1,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput DDR,\r\n\toutput Q\r\n);\r\n\twire clk;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\r\n\treg q0, q1;\r\n\tassign Q = (DDR) ? q0 : q1;\r\n\r\n\talways @(posedge clk)\r\n\tbegin\r\n\t\tq0 <= D0;\r\n\tend\r\n\r\n\talways @(negedge clk)\r\n\tbegin\r\n\t\tq1 <= D1;\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_DFF #(\r\n\tparameter [0:0] CLK_INV = 1'b0,\r\n\tparameter [0:0] EN_INV = 1'b0,\r\n\tparameter [0:0] SR_INV = 1'b0,\r\n\tparameter [0:0] SR_VAL = 1'b0,\r\n\tparameter [0:0] INIT = 1'bx\r\n)(\r\n\tinput D,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\tinput EN,\r\n\tinput SR,\r\n\toutput reg Q\r\n);\r\n\twire clk, en, sr;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\tassign en = (EN_INV) ? ~EN : EN;\r\n\tassign sr = (SR_INV) ? ~SR : SR;\r\n\r\n\tinitial Q = INIT;\r\n\r\n\talways @(posedge clk or posedge sr)\r\n\tbegin\r\n\t\tif (sr) begin\r\n\t\t\tQ <= SR_VAL;\r\n\t\tend\r\n\t\telse if (en) begin\r\n\t\t\tQ <= D;\r\n\t\tend\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_DLT #(\r\n\tparameter [0:0] G_INV = 1'b0,\r\n\tparameter [0:0] SR_INV = 1'b0,\r\n\tparameter [0:0] SR_VAL = 1'b0,\r\n\tparameter [0:0] INIT = 1'bx\r\n)(\r\n\tinput D,\r\n\tinput G,\r\n\tinput SR,\r\n\toutput reg Q\r\n);\r\n\twire en, sr;\r\n\tassign en = (G_INV) ? ~G : G;\r\n\tassign sr = (SR_INV) ? ~SR : SR;\r\n\r\n\tinitial Q = INIT;\r\n\r\n\talways @(*)\r\n\tbegin\r\n\t\tif (sr) begin\r\n\t\t\tQ = SR_VAL;\r\n\t\tend\r\n\t\telse if (en) begin\r\n\t\t\tQ = D;\r\n\t\tend\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT1 (\r\n\toutput O,\r\n\tinput I0\r\n);\r\n\tparameter [1:0] INIT = 0;\r\n\r\n\tassign O = I0 ? INIT[1] : INIT[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT2 (\r\n\toutput O,\r\n\tinput I0, I1\r\n);\r\n\tparameter [3:0] INIT = 0;\r\n\r\n\twire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT3 (\r\n\toutput O,\r\n\tinput I0, I1, I2\r\n);\r\n\tparameter [7:0] INIT = 0;\r\n\r\n\twire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];\r\n\twire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT4 (\r\n\toutput O,\r\n\tinput I0, I1, I2, I3\r\n);\r\n\tparameter [15:0] INIT = 0;\r\n\r\n\twire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];\r\n\twire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];\r\n\twire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX2 (\r\n\tinput D0, D1,\r\n\tinput S0,\r\n\toutput Y\r\n);\r\n\tassign Y = S0 ? D1 : D0;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX4 (\r\n\tinput D0, D1, D2, D3,\r\n\tinput S0, S1,\r\n\toutput Y\r\n);\r\n\tassign Y = S1 ? (S0 ? D3 : D2) :\r\n\t\t\t\t\t(S0 ? D1 : D0);\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX8 (\r\n\tinput D0, D1, D2, D3,\r\n\tinput D4, D5, D6, D7,\r\n\tinput S0, S1, S2,\r\n\toutput Y\r\n);\r\n\tassign Y = S2 ? (S1 ? (S0 ? D7 : D6) :\r\n\t\t\t\t\t\t (S0 ? D5 : D4)) :\r\n\t\t\t\t\t(S1 ? (S0 ? D3 : D2) :\r\n\t\t\t\t\t\t (S0 ? D1 : D0));\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_ADDF (\r\n\tinput A, B, CI,\r\n\toutput CO, S\r\n);\r\n\tassign {CO, S} = A + B + CI;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MULT #(\r\n\tparameter A_WIDTH = 0,\r\n\tparameter B_WIDTH = 0,\r\n\tparameter P_WIDTH = 0\r\n)(\r\n\tinput signed [A_WIDTH-1:0] A,\r\n\tinput signed [B_WIDTH-1:0] B,\r\n\toutput reg signed [P_WIDTH-1:0] P\r\n);\r\n\talways @(*)\r\n\tbegin\r\n\t\tP = A * B;\r\n\tend\r\nendmodule\r\n\r\n\r\nmodule CC_BUFG (\r\n\tinput I,\r\n\t(* clkbuf_driver *)\r\n\toutput O\r\n);\r\n\tassign O = I;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_BRAM_20K (\r\n\toutput [19:0] A_DO,\r\n\toutput [19:0] B_DO,\r\n\toutput ECC_1B_ERR,\r\n\toutput ECC_2B_ERR,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput A_EN,\r\n\tinput B_EN,\r\n\tinput A_WE,\r\n\tinput B_WE,\r\n\tinput [15:0] A_ADDR,\r\n\tinput [15:0] B_ADDR,\r\n\tinput [19:0] A_DI,\r\n\tinput [19:0] B_DI,\r\n\tinput [19:0] A_BM,\r\n\tinput [19:0] B_BM\r\n);\r\n\t// Location format: D(0..N-1)(0..N-1)X(0..3)Y(0..7)Z(0..1) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\r\n\t// Port Widths\r\n\tparameter A_RD_WIDTH = 0;\r\n\tparameter B_RD_WIDTH = 0;\r\n\tparameter A_WR_WIDTH = 0;\r\n\tparameter B_WR_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"SDP\";\r\n\tparameter A_WR_MODE = \"NO_CHANGE\";\r\n\tparameter B_WR_MODE = \"NO_CHANGE\";\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter ECC_EN = 1'b0;\r\n\r\n\t// RAM Contents\r\n\tparameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\r\n\tlocalparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH;\r\n\tlocalparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 40 bit\r\n\treg [20479:0] memory = 20480'b0;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WR_MODE != \"WRITE_THROUGH\") && (A_WR_MODE != \"NO_CHANGE\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (A_WR_MODE == \"WRITE_THROUGH\")) begin\r\n\t\t\t$display(\"ERROR: %s is not supported in %s mode.\", A_WR_MODE, RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif (ECC_EN != 1'b0) begin\r\n\t\t\t$display(\"WARNING: ECC feature not supported in simulation.\");\r\n\t\tend\r\n\t\tif ((ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (WIDTH_MODE_A != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port configuration. Must be SDP 40 bit, but is %s %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A == 40) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 40 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B == 40) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 40 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&\r\n\t\t\t(WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) &&\r\n\t\t\t(WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, WIDTH_MODE_B);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// RAM initialization\r\n\t\tmemory[320*0+319:320*0] = INIT_00;\r\n\t\tmemory[320*1+319:320*1] = INIT_01;\r\n\t\tmemory[320*2+319:320*2] = INIT_02;\r\n\t\tmemory[320*3+319:320*3] = INIT_03;\r\n\t\tmemory[320*4+319:320*4] = INIT_04;\r\n\t\tmemory[320*5+319:320*5] = INIT_05;\r\n\t\tmemory[320*6+319:320*6] = INIT_06;\r\n\t\tmemory[320*7+319:320*7] = INIT_07;\r\n\t\tmemory[320*8+319:320*8] = INIT_08;\r\n\t\tmemory[320*9+319:320*9] = INIT_09;\r\n\t\tmemory[320*10+319:320*10] = INIT_0A;\r\n\t\tmemory[320*11+319:320*11] = INIT_0B;\r\n\t\tmemory[320*12+319:320*12] = INIT_0C;\r\n\t\tmemory[320*13+319:320*13] = INIT_0D;\r\n\t\tmemory[320*14+319:320*14] = INIT_0E;\r\n\t\tmemory[320*15+319:320*15] = INIT_0F;\r\n\t\tmemory[320*16+319:320*16] = INIT_10;\r\n\t\tmemory[320*17+319:320*17] = INIT_11;\r\n\t\tmemory[320*18+319:320*18] = INIT_12;\r\n\t\tmemory[320*19+319:320*19] = INIT_13;\r\n\t\tmemory[320*20+319:320*20] = INIT_14;\r\n\t\tmemory[320*21+319:320*21] = INIT_15;\r\n\t\tmemory[320*22+319:320*22] = INIT_16;\r\n\t\tmemory[320*23+319:320*23] = INIT_17;\r\n\t\tmemory[320*24+319:320*24] = INIT_18;\r\n\t\tmemory[320*25+319:320*25] = INIT_19;\r\n\t\tmemory[320*26+319:320*26] = INIT_1A;\r\n\t\tmemory[320*27+319:320*27] = INIT_1B;\r\n\t\tmemory[320*28+319:320*28] = INIT_1C;\r\n\t\tmemory[320*29+319:320*29] = INIT_1D;\r\n\t\tmemory[320*30+319:320*30] = INIT_1E;\r\n\t\tmemory[320*31+319:320*31] = INIT_1F;\r\n\t\tmemory[320*32+319:320*32] = INIT_20;\r\n\t\tmemory[320*33+319:320*33] = INIT_21;\r\n\t\tmemory[320*34+319:320*34] = INIT_22;\r\n\t\tmemory[320*35+319:320*35] = INIT_23;\r\n\t\tmemory[320*36+319:320*36] = INIT_24;\r\n\t\tmemory[320*37+319:320*37] = INIT_25;\r\n\t\tmemory[320*38+319:320*38] = INIT_26;\r\n\t\tmemory[320*39+319:320*39] = INIT_27;\r\n\t\tmemory[320*40+319:320*40] = INIT_28;\r\n\t\tmemory[320*41+319:320*41] = INIT_29;\r\n\t\tmemory[320*42+319:320*42] = INIT_2A;\r\n\t\tmemory[320*43+319:320*43] = INIT_2B;\r\n\t\tmemory[320*44+319:320*44] = INIT_2C;\r\n\t\tmemory[320*45+319:320*45] = INIT_2D;\r\n\t\tmemory[320*46+319:320*46] = INIT_2E;\r\n\t\tmemory[320*47+319:320*47] = INIT_2F;\r\n\t\tmemory[320*48+319:320*48] = INIT_30;\r\n\t\tmemory[320*49+319:320*49] = INIT_31;\r\n\t\tmemory[320*50+319:320*50] = INIT_32;\r\n\t\tmemory[320*51+319:320*51] = INIT_33;\r\n\t\tmemory[320*52+319:320*52] = INIT_34;\r\n\t\tmemory[320*53+319:320*53] = INIT_35;\r\n\t\tmemory[320*54+319:320*54] = INIT_36;\r\n\t\tmemory[320*55+319:320*55] = INIT_37;\r\n\t\tmemory[320*56+319:320*56] = INIT_38;\r\n\t\tmemory[320*57+319:320*57] = INIT_39;\r\n\t\tmemory[320*58+319:320*58] = INIT_3A;\r\n\t\tmemory[320*59+319:320*59] = INIT_3B;\r\n\t\tmemory[320*60+319:320*60] = INIT_3C;\r\n\t\tmemory[320*61+319:320*61] = INIT_3D;\r\n\t\tmemory[320*62+319:320*62] = INIT_3E;\r\n\t\tmemory[320*63+319:320*63] = INIT_3F;\r\n\tend\r\n\r\n\t// Signal inversion\r\n\twire clka = A_CLK_INV ^ A_CLK;\r\n\twire clkb = B_CLK_INV ^ B_CLK;\r\n\twire ena = A_EN_INV ^ A_EN;\r\n\twire enb = B_EN_INV ^ B_EN;\r\n\twire wea = A_WE_INV ^ A_WE;\r\n\twire web = B_WE_INV ^ B_WE;\r\n\r\n\t// Internal signals\r\n\twire [15:0] addra;\r\n\twire [15:0] addrb;\r\n\treg [19:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg [19:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// Port A (write)\r\n\t\t\tif (A_WR_WIDTH == 40) begin\r\n\t\t\t\tassign addra = A_ADDR[15:7]*40;\r\n\t\t\tend\r\n\t\t\t// Port B (read)\r\n\t\t\tif (B_RD_WIDTH == 40) begin\r\n\t\t\t\tassign addrb = B_ADDR[15:7]*40;\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// Port A\r\n\t\t\tif (WIDTH_MODE_A <= 1) begin\r\n\t\t\t\twire [15:0] tmpa = {2'b0, A_ADDR[15:7], A_ADDR[5:1]};\r\n\t\t\t\tassign addra = tmpa + (tmpa/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 2) begin\r\n\t\t\t\twire [15:0] tmpa = {3'b0, A_ADDR[15:7], A_ADDR[5:2]};\r\n\t\t\t\tassign addra = tmpa*2 + (tmpa/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 5) begin\r\n\t\t\t\tassign addra = {4'b0, A_ADDR[15:7], A_ADDR[5:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 10) begin\r\n\t\t\t\tassign addra = {5'b0, A_ADDR[15:7], A_ADDR[5:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 20) begin\r\n\t\t\t\tassign addra = {6'b0, A_ADDR[15:7], A_ADDR[5]}*20;\r\n\t\t\tend\r\n\t\t\t// Port B\r\n\t\t\tif (WIDTH_MODE_B <= 1) begin\r\n\t\t\t\twire [15:0] tmpb = {2'b0, B_ADDR[15:7], B_ADDR[5:1]};\r\n\t\t\t\tassign addrb = tmpb + (tmpb/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 2) begin\r\n\t\t\t\twire [15:0] tmpb = {3'b0, B_ADDR[15:7], B_ADDR[5:2]};\r\n\t\t\t\tassign addrb = tmpb*2 + (tmpb/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 5) begin\r\n\t\t\t\tassign addrb = {4'b0, B_ADDR[15:7], B_ADDR[5:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 10) begin\r\n\t\t\t\tassign addrb = {5'b0, B_ADDR[15:7], B_ADDR[5:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 20) begin\r\n\t\t\t\tassign addrb = {6'b0, B_ADDR[15:7], B_ADDR[5]}*20;\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP write port\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WR_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 20) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ena && wea && B_BM[k-20]) memory[addra+k] <= B_DI[k-20];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP read port\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_RD_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 20) begin\r\n\t\t\t\t\t\tif (enb) A_DO_out[k] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (enb) B_DO_out[k-20] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// TDP port A\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_A; i=i+1) begin\r\n\t\t\t\t\tif (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i];\r\n\r\n\t\t\t\t\tif (A_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (ena && !wea) A_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (A_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (ena) begin\r\n\t\t\t\t\t\t\tif (wea && A_BM[i]) begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= A_DI[i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP port B\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_B; i=i+1) begin\r\n\t\t\t\t\tif (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i];\r\n\r\n\t\t\t\t\tif (B_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (enb && !web) B_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (B_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (enb) begin\r\n\t\t\t\t\t\t\tif (web && B_BM[i]) begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= B_DI[i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge clka) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge clkb) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\n\r\nmodule CC_BRAM_40K (\r\n\toutput [39:0] A_DO,\r\n\toutput [39:0] B_DO,\r\n\toutput A_ECC_1B_ERR,\r\n\toutput B_ECC_1B_ERR,\r\n\toutput A_ECC_2B_ERR,\r\n\toutput B_ECC_2B_ERR,\r\n\toutput reg A_CO = 0,\r\n\toutput reg B_CO = 0,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput A_EN,\r\n\tinput B_EN,\r\n\tinput A_WE,\r\n\tinput B_WE,\r\n\tinput [15:0] A_ADDR,\r\n\tinput [15:0] B_ADDR,\r\n\tinput [39:0] A_DI,\r\n\tinput [39:0] B_DI,\r\n\tinput [39:0] A_BM,\r\n\tinput [39:0] B_BM,\r\n\tinput A_CI,\r\n\tinput B_CI\r\n);\r\n\t// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\tparameter CAS = \"NONE\"; // NONE, UPPER, LOWER\r\n\r\n\t// Port Widths\r\n\tparameter A_RD_WIDTH = 0;\r\n\tparameter B_RD_WIDTH = 0;\r\n\tparameter A_WR_WIDTH = 0;\r\n\tparameter B_WR_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"SDP\";\r\n\tparameter A_WR_MODE = \"NO_CHANGE\";\r\n\tparameter B_WR_MODE = \"NO_CHANGE\";\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter A_ECC_EN = 1'b0;\r\n\tparameter B_ECC_EN = 1'b0;\r\n\r\n\tparameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_40 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_41 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_42 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_43 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_44 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_45 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_46 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_47 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_48 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_49 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_50 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_51 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_52 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_53 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_54 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_55 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_56 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_57 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_58 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_59 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_60 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_61 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_62 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_63 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_64 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_65 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_66 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_67 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_68 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_69 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_70 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_71 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_72 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_73 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_74 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_75 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_76 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_77 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_78 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_79 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\r\n\tlocalparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH;\r\n\tlocalparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 80 bit\r\n\treg [40959:0] memory = 40960'b0;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WR_MODE != \"WRITE_THROUGH\") && (A_WR_MODE != \"NO_CHANGE\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (A_WR_MODE == \"WRITE_THROUGH\")) begin\r\n\t\t\t$display(\"ERROR: %s is not supported in %s mode.\", A_WR_MODE, RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_ECC_EN != 1'b0) || (B_ECC_EN != 1'b0)) begin\r\n\t\t\t$display(\"WARNING: ECC feature not supported in simulation.\");\r\n\t\tend\r\n\t\tif ((A_ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (WIDTH_MODE_A != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port A configuration. Must be SDP 40 bit, but is %s %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&\r\n\t\t\t(WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B != 80) && (WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) &&\r\n\t\t\t(WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, WIDTH_MODE_B);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((CAS != \"NONE\") && ((WIDTH_MODE_A > 1) || (WIDTH_MODE_B > 1))) begin\r\n\t\t\t$display(\"ERROR: Cascade feature only supported in 1 bit data width mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((CAS != \"NONE\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Cascade feature only supported in TDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// RAM initialization\r\n\t\tmemory[320*0+319:320*0] = INIT_00;\r\n\t\tmemory[320*1+319:320*1] = INIT_01;\r\n\t\tmemory[320*2+319:320*2] = INIT_02;\r\n\t\tmemory[320*3+319:320*3] = INIT_03;\r\n\t\tmemory[320*4+319:320*4] = INIT_04;\r\n\t\tmemory[320*5+319:320*5] = INIT_05;\r\n\t\tmemory[320*6+319:320*6] = INIT_06;\r\n\t\tmemory[320*7+319:320*7] = INIT_07;\r\n\t\tmemory[320*8+319:320*8] = INIT_08;\r\n\t\tmemory[320*9+319:320*9] = INIT_09;\r\n\t\tmemory[320*10+319:320*10] = INIT_0A;\r\n\t\tmemory[320*11+319:320*11] = INIT_0B;\r\n\t\tmemory[320*12+319:320*12] = INIT_0C;\r\n\t\tmemory[320*13+319:320*13] = INIT_0D;\r\n\t\tmemory[320*14+319:320*14] = INIT_0E;\r\n\t\tmemory[320*15+319:320*15] = INIT_0F;\r\n\t\tmemory[320*16+319:320*16] = INIT_10;\r\n\t\tmemory[320*17+319:320*17] = INIT_11;\r\n\t\tmemory[320*18+319:320*18] = INIT_12;\r\n\t\tmemory[320*19+319:320*19] = INIT_13;\r\n\t\tmemory[320*20+319:320*20] = INIT_14;\r\n\t\tmemory[320*21+319:320*21] = INIT_15;\r\n\t\tmemory[320*22+319:320*22] = INIT_16;\r\n\t\tmemory[320*23+319:320*23] = INIT_17;\r\n\t\tmemory[320*24+319:320*24] = INIT_18;\r\n\t\tmemory[320*25+319:320*25] = INIT_19;\r\n\t\tmemory[320*26+319:320*26] = INIT_1A;\r\n\t\tmemory[320*27+319:320*27] = INIT_1B;\r\n\t\tmemory[320*28+319:320*28] = INIT_1C;\r\n\t\tmemory[320*29+319:320*29] = INIT_1D;\r\n\t\tmemory[320*30+319:320*30] = INIT_1E;\r\n\t\tmemory[320*31+319:320*31] = INIT_1F;\r\n\t\tmemory[320*32+319:320*32] = INIT_20;\r\n\t\tmemory[320*33+319:320*33] = INIT_21;\r\n\t\tmemory[320*34+319:320*34] = INIT_22;\r\n\t\tmemory[320*35+319:320*35] = INIT_23;\r\n\t\tmemory[320*36+319:320*36] = INIT_24;\r\n\t\tmemory[320*37+319:320*37] = INIT_25;\r\n\t\tmemory[320*38+319:320*38] = INIT_26;\r\n\t\tmemory[320*39+319:320*39] = INIT_27;\r\n\t\tmemory[320*40+319:320*40] = INIT_28;\r\n\t\tmemory[320*41+319:320*41] = INIT_29;\r\n\t\tmemory[320*42+319:320*42] = INIT_2A;\r\n\t\tmemory[320*43+319:320*43] = INIT_2B;\r\n\t\tmemory[320*44+319:320*44] = INIT_2C;\r\n\t\tmemory[320*45+319:320*45] = INIT_2D;\r\n\t\tmemory[320*46+319:320*46] = INIT_2E;\r\n\t\tmemory[320*47+319:320*47] = INIT_2F;\r\n\t\tmemory[320*48+319:320*48] = INIT_30;\r\n\t\tmemory[320*49+319:320*49] = INIT_31;\r\n\t\tmemory[320*50+319:320*50] = INIT_32;\r\n\t\tmemory[320*51+319:320*51] = INIT_33;\r\n\t\tmemory[320*52+319:320*52] = INIT_34;\r\n\t\tmemory[320*53+319:320*53] = INIT_35;\r\n\t\tmemory[320*54+319:320*54] = INIT_36;\r\n\t\tmemory[320*55+319:320*55] = INIT_37;\r\n\t\tmemory[320*56+319:320*56] = INIT_38;\r\n\t\tmemory[320*57+319:320*57] = INIT_39;\r\n\t\tmemory[320*58+319:320*58] = INIT_3A;\r\n\t\tmemory[320*59+319:320*59] = INIT_3B;\r\n\t\tmemory[320*60+319:320*60] = INIT_3C;\r\n\t\tmemory[320*61+319:320*61] = INIT_3D;\r\n\t\tmemory[320*62+319:320*62] = INIT_3E;\r\n\t\tmemory[320*63+319:320*63] = INIT_3F;\r\n\t\tmemory[320*64+319:320*64] = INIT_40;\r\n\t\tmemory[320*65+319:320*65] = INIT_41;\r\n\t\tmemory[320*66+319:320*66] = INIT_42;\r\n\t\tmemory[320*67+319:320*67] = INIT_43;\r\n\t\tmemory[320*68+319:320*68] = INIT_44;\r\n\t\tmemory[320*69+319:320*69] = INIT_45;\r\n\t\tmemory[320*70+319:320*70] = INIT_46;\r\n\t\tmemory[320*71+319:320*71] = INIT_47;\r\n\t\tmemory[320*72+319:320*72] = INIT_48;\r\n\t\tmemory[320*73+319:320*73] = INIT_49;\r\n\t\tmemory[320*74+319:320*74] = INIT_4A;\r\n\t\tmemory[320*75+319:320*75] = INIT_4B;\r\n\t\tmemory[320*76+319:320*76] = INIT_4C;\r\n\t\tmemory[320*77+319:320*77] = INIT_4D;\r\n\t\tmemory[320*78+319:320*78] = INIT_4E;\r\n\t\tmemory[320*79+319:320*79] = INIT_4F;\r\n\t\tmemory[320*80+319:320*80] = INIT_50;\r\n\t\tmemory[320*81+319:320*81] = INIT_51;\r\n\t\tmemory[320*82+319:320*82] = INIT_52;\r\n\t\tmemory[320*83+319:320*83] = INIT_53;\r\n\t\tmemory[320*84+319:320*84] = INIT_54;\r\n\t\tmemory[320*85+319:320*85] = INIT_55;\r\n\t\tmemory[320*86+319:320*86] = INIT_56;\r\n\t\tmemory[320*87+319:320*87] = INIT_57;\r\n\t\tmemory[320*88+319:320*88] = INIT_58;\r\n\t\tmemory[320*89+319:320*89] = INIT_59;\r\n\t\tmemory[320*90+319:320*90] = INIT_5A;\r\n\t\tmemory[320*91+319:320*91] = INIT_5B;\r\n\t\tmemory[320*92+319:320*92] = INIT_5C;\r\n\t\tmemory[320*93+319:320*93] = INIT_5D;\r\n\t\tmemory[320*94+319:320*94] = INIT_5E;\r\n\t\tmemory[320*95+319:320*95] = INIT_5F;\r\n\t\tmemory[320*96+319:320*96] = INIT_60;\r\n\t\tmemory[320*97+319:320*97] = INIT_61;\r\n\t\tmemory[320*98+319:320*98] = INIT_62;\r\n\t\tmemory[320*99+319:320*99] = INIT_63;\r\n\t\tmemory[320*100+319:320*100] = INIT_64;\r\n\t\tmemory[320*101+319:320*101] = INIT_65;\r\n\t\tmemory[320*102+319:320*102] = INIT_66;\r\n\t\tmemory[320*103+319:320*103] = INIT_67;\r\n\t\tmemory[320*104+319:320*104] = INIT_68;\r\n\t\tmemory[320*105+319:320*105] = INIT_69;\r\n\t\tmemory[320*106+319:320*106] = INIT_6A;\r\n\t\tmemory[320*107+319:320*107] = INIT_6B;\r\n\t\tmemory[320*108+319:320*108] = INIT_6C;\r\n\t\tmemory[320*109+319:320*109] = INIT_6D;\r\n\t\tmemory[320*110+319:320*110] = INIT_6E;\r\n\t\tmemory[320*111+319:320*111] = INIT_6F;\r\n\t\tmemory[320*112+319:320*112] = INIT_70;\r\n\t\tmemory[320*113+319:320*113] = INIT_71;\r\n\t\tmemory[320*114+319:320*114] = INIT_72;\r\n\t\tmemory[320*115+319:320*115] = INIT_73;\r\n\t\tmemory[320*116+319:320*116] = INIT_74;\r\n\t\tmemory[320*117+319:320*117] = INIT_75;\r\n\t\tmemory[320*118+319:320*118] = INIT_76;\r\n\t\tmemory[320*119+319:320*119] = INIT_77;\r\n\t\tmemory[320*120+319:320*120] = INIT_78;\r\n\t\tmemory[320*121+319:320*121] = INIT_79;\r\n\t\tmemory[320*122+319:320*122] = INIT_7A;\r\n\t\tmemory[320*123+319:320*123] = INIT_7B;\r\n\t\tmemory[320*124+319:320*124] = INIT_7C;\r\n\t\tmemory[320*125+319:320*125] = INIT_7D;\r\n\t\tmemory[320*126+319:320*126] = INIT_7E;\r\n\t\tmemory[320*127+319:320*127] = INIT_7F;\r\n\tend\r\n\r\n\t// Signal inversion\r\n\twire clka = A_CLK_INV ^ A_CLK;\r\n\twire clkb = B_CLK_INV ^ B_CLK;\r\n\twire ena = A_EN_INV ^ A_EN;\r\n\twire enb = B_EN_INV ^ B_EN;\r\n\twire wea = A_WE_INV ^ A_WE;\r\n\twire web = B_WE_INV ^ B_WE;\r\n\r\n\t// Internal signals\r\n\twire [15:0] addra;\r\n\twire [15:0] addrb;\r\n\treg [39:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg [39:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// Port A (write)\r\n\t\t\t if (A_WR_WIDTH == 80) begin\r\n\t\t\t\tassign addra = A_ADDR[15:7]*80;\r\n\t\t\tend\r\n\t\t\t// Port B (read)\r\n\t\t\tif (B_RD_WIDTH == 80) begin\r\n\t\t\t\tassign addrb = B_ADDR[15:7]*80;\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// Port A\r\n\t\t\tif (WIDTH_MODE_A <= 1) begin\r\n\t\t\t\twire [15:0] tmpa = {1'b0, A_ADDR[15:1]};\r\n\t\t\t\tassign addra = tmpa + (tmpa/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 2) begin\r\n\t\t\t\twire [15:0] tmpa = {2'b0, A_ADDR[15:2]};\r\n\t\t\t\tassign addra = tmpa*2 + (tmpa/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 5) begin\r\n\t\t\t\tassign addra = {3'b0, A_ADDR[15:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 10) begin\r\n\t\t\t\tassign addra = {4'b0, A_ADDR[15:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 20) begin\r\n\t\t\t\tassign addra = {5'b0, A_ADDR[15:5]}*20;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 40) begin\r\n\t\t\t\tassign addra = {6'b0, A_ADDR[15:6]}*40;\r\n\t\t\tend\r\n\t\t\t// Port B\r\n\t\t\tif (WIDTH_MODE_B <= 1) begin\r\n\t\t\t\twire [15:0] tmpb = {1'b0, B_ADDR[15:1]};\r\n\t\t\t\tassign addrb = tmpb + (tmpb/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 2) begin\r\n\t\t\t\twire [15:0] tmpb = {2'b0, B_ADDR[15:2]};\r\n\t\t\t\tassign addrb = tmpb*2 + (tmpb/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 5) begin\r\n\t\t\t\tassign addrb = {3'b0, B_ADDR[15:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 10) begin\r\n\t\t\t\tassign addrb = {4'b0, B_ADDR[15:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 20) begin\r\n\t\t\t\tassign addrb = {5'b0, B_ADDR[15:5]}*20;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 40) begin\r\n\t\t\t\tassign addrb = {6'b0, B_ADDR[15:6]}*40;\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP write port\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WR_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ena && wea && B_BM[k-40]) memory[addra+k] <= B_DI[k-40];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP read port\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_RD_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (enb) A_DO_out[k] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (enb) B_DO_out[k-40] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// {A,B}_ADDR[0]=0 selects lower, {A,B}_ADDR[0]=1 selects upper cascade memory\r\n\t\t\twire upper_sel_a = ((CAS == \"UPPER\") && (A_ADDR[0] == 1));\r\n\t\t\twire lower_sel_a = ((CAS == \"LOWER\") && (A_ADDR[0] == 0));\r\n\t\t\twire upper_sel_b = ((CAS == \"UPPER\") && (B_ADDR[0] == 1));\r\n\t\t\twire lower_sel_b = ((CAS == \"LOWER\") && (B_ADDR[0] == 0));\r\n\r\n\t\t\treg dumm;\r\n\r\n\t\t\t// Cascade output port A\r\n\t\t\talways @(*)\r\n\t\t\tbegin\r\n\t\t\t\tif ((A_WR_MODE == \"NO_CHANGE\") && lower_sel_a) begin\r\n\t\t\t\t\tA_CO = memory[addra];\r\n\t\t\t\tend\r\n\t\t\t\telse if ((A_WR_MODE == \"WRITE_THROUGH\") && lower_sel_a) begin\r\n\t\t\t\t\tA_CO = ((wea && A_BM[0]) ? (A_DI[0]) : (memory[addra]));\r\n\t\t\t\tend\r\n\t\t\tend\r\n\r\n\t\t\t// Cascade output port B\r\n\t\t\talways @(*)\r\n\t\t\tbegin\r\n\t\t\t\tif ((B_WR_MODE == \"NO_CHANGE\") && lower_sel_b) begin\r\n\t\t\t\t\tB_CO = memory[addrb];\r\n\t\t\t\tend\r\n\t\t\t\telse if ((B_WR_MODE == \"WRITE_THROUGH\") && lower_sel_b) begin\r\n\t\t\t\t\tB_CO = ((web && B_BM[0]) ? (B_DI[0]) : (memory[addrb]));\r\n\t\t\t\tend\r\n\t\t\tend\r\n\r\n\t\t\t// TDP port A\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_A; i=i+1) begin\r\n\t\t\t\t\tif (upper_sel_a || lower_sel_a || (CAS == \"NONE\")) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[i])\r\n\t\t\t\t\t\t\tmemory[addra+i] <= A_DI[i];\r\n\t\t\t\t\tend\r\n\r\n\t\t\t\t\tif (A_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (ena && !wea) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= ((A_ADDR[0] == 1) ? (memory[addra+i]) : (A_CI));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (A_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (ena) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tif (A_ADDR[0] == 1) begin\r\n\t\t\t\t\t\t\t\t\tA_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));\r\n\t\t\t\t\t\t\t\tend else begin\r\n\t\t\t\t\t\t\t\t\tA_DO_out[i] <= A_CI;\r\n\t\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP port B\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_B; i=i+1) begin\r\n\t\t\t\t\tif (upper_sel_b || lower_sel_b || (CAS == \"NONE\")) begin\r\n\t\t\t\t\t\tif (enb && web && B_BM[i])\r\n\t\t\t\t\t\t\tmemory[addrb+i] <= B_DI[i];\r\n\t\t\t\t\tend\r\n\r\n\t\t\t\t\tif (B_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (enb && !web) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= ((B_ADDR[0] == 1) ? (memory[addrb+i]) : (B_CI));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (B_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (enb) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tif (B_ADDR[0] == 1) begin\r\n\t\t\t\t\t\t\t\t\tB_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));\r\n\t\t\t\t\t\t\t\tend else begin\r\n\t\t\t\t\t\t\t\t\tB_DO_out[i] <= B_CI;\r\n\t\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge clka) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge clkb) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\nmodule CC_FIFO_40K (\r\n\toutput A_ECC_1B_ERR,\r\n\toutput B_ECC_1B_ERR,\r\n\toutput A_ECC_2B_ERR,\r\n\toutput B_ECC_2B_ERR,\r\n\t// FIFO pop port\r\n\toutput [39:0] A_DO,\r\n\toutput [39:0] B_DO,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\tinput A_EN,\r\n\t// FIFO push port\r\n\tinput [39:0] A_DI,\r\n\tinput [39:0] B_DI,\r\n\tinput [39:0] A_BM,\r\n\tinput [39:0] B_BM,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput B_EN,\r\n\tinput B_WE,\r\n\t// FIFO control\r\n\tinput F_RST_N,\r\n\tinput [14:0] F_ALMOST_FULL_OFFSET,\r\n\tinput [14:0] F_ALMOST_EMPTY_OFFSET,\r\n\t// FIFO status signals\r\n\toutput F_FULL,\r\n\toutput F_EMPTY,\r\n\toutput F_ALMOST_FULL,\r\n\toutput F_ALMOST_EMPTY,\r\n\toutput F_RD_ERROR,\r\n\toutput F_WR_ERROR,\r\n\toutput [15:0] F_RD_PTR,\r\n\toutput [15:0] F_WR_PTR\r\n);\r\n\t// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\r\n\t// Offset configuration\r\n\tparameter DYN_STAT_SELECT = 1'b0;\r\n\tparameter [14:0] ALMOST_FULL_OFFSET = 15'b0;\r\n\tparameter [14:0] ALMOST_EMPTY_OFFSET = 15'b0;\r\n\r\n\t// Port Widths\r\n\tparameter A_WIDTH = 0;\r\n\tparameter B_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"TDP\"; // \"TDP\" or \"SDP\"\r\n\tparameter FIFO_MODE = \"SYNC\"; // \"ASYNC\" or \"SYNC\"\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter A_ECC_EN = 1'b0;\r\n\tparameter B_ECC_EN = 1'b0;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 80 bit\r\n\treg [40959:0] memory = 40960'b0;\r\n\r\n\treg [15:0] counter_max;\r\n\treg [15:0] sram_depth;\r\n\tlocalparam tp = (A_WIDTH == 1) ? 15 :\r\n\t\t\t\t\t(A_WIDTH == 2) ? 14 :\r\n\t\t\t\t\t(A_WIDTH == 5) ? 13 :\r\n\t\t\t\t\t(A_WIDTH == 10) ? 12 :\r\n\t\t\t\t\t(A_WIDTH == 20) ? 11 :\r\n\t\t\t\t\t(A_WIDTH == 40) ? 10 : 9;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((FIFO_MODE != \"ASYNC\") && (FIFO_MODE != \"SYNC\")) begin\r\n\t\t\t$display(\"ERROR: Illegal FIFO MODE %d.\", FIFO_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (DYN_STAT_SELECT == 1)) begin\r\n\t\t\t$display(\"ERROR: Dynamic offset configuration is not supported in %s mode.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && ((A_WIDTH != 80) || (B_WIDTH != 80))) begin\r\n\t\t\t$display(\"ERROR: SDP is ony supported in 80 bit mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WIDTH == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((B_WIDTH == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WIDTH != 80) && (A_WIDTH != 40) && (A_WIDTH != 20) && (A_WIDTH != 10) &&\r\n\t\t\t(A_WIDTH != 5) && (A_WIDTH != 2) && (A_WIDTH != 1) && (A_WIDTH != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, A_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((B_WIDTH != 80) && (B_WIDTH != 40) && (B_WIDTH != 20) && (B_WIDTH != 10) &&\r\n\t\t\t(B_WIDTH != 5) && (B_WIDTH != 2) && (B_WIDTH != 1) && (B_WIDTH != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, B_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif (A_WIDTH != B_WIDTH) begin\r\n\t\t\t$display(\"ERROR: The values of A_WIDTH and B_WIDTH must be equal.\");\r\n\t\tend\r\n\t\tif ((A_ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (A_WIDTH != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port A configuration. ECC mode requires TDP >=40 bit or SDP 80 bit, but is %s %d.\", RAM_MODE, A_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// Set local parameters\r\n\t\tif (A_WIDTH == 1) begin // A_WIDTH=B_WIDTH\r\n\t\t\tcounter_max = 2 * 32*1024 - 1;\r\n\t\t\tsram_depth = 32*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 2) begin\r\n\t\t\tcounter_max = 2 * 16*1024 - 1;\r\n\t\t\tsram_depth = 16*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 5) begin\r\n\t\t\tcounter_max = 2 * 8*1024 - 1;\r\n\t\t\tsram_depth = 8*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 10) begin\r\n\t\t\tcounter_max = 2 * 4*1024 - 1;\r\n\t\t\tsram_depth = 4*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 20) begin\r\n\t\t\tcounter_max = 2 * 2*1024 - 1;\r\n\t\t\tsram_depth = 2*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 40) begin\r\n\t\t\tcounter_max = 2 * 1*1024 - 1;\r\n\t\t\tsram_depth = 1*1024;\r\n\t\tend\r\n\t\telse begin // 80 bit SDP\r\n\t\t\tcounter_max = 2 * 512 - 1;\r\n\t\t\tsram_depth = 512;\r\n\t\tend\r\n\tend\r\n\r\n\t// Internal signals\r\n\twire fifo_rdclk = A_CLK ^ A_CLK_INV;\r\n\twire fifo_wrclk = (FIFO_MODE == \"ASYNC\") ? (B_CLK ^ B_CLK_INV) : (A_CLK ^ A_CLK_INV);\r\n\twire [15:0] almost_full_offset = DYN_STAT_SELECT ? F_ALMOST_FULL_OFFSET : ALMOST_FULL_OFFSET;\r\n\twire [15:0] almost_empty_offset = DYN_STAT_SELECT ? F_ALMOST_EMPTY_OFFSET : ALMOST_EMPTY_OFFSET;\r\n\treg [39:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg [39:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\t// Status signals\r\n\treg fifo_full;\r\n\treg fifo_empty;\r\n\treg fifo_almost_full;\r\n\treg fifo_almost_empty;\r\n\tassign F_FULL = fifo_full;\r\n\tassign F_EMPTY = fifo_empty;\r\n\tassign F_ALMOST_FULL = fifo_almost_full;\r\n\tassign F_ALMOST_EMPTY = fifo_almost_empty;\r\n\tassign F_WR_ERROR = (F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));\r\n\tassign F_RD_ERROR = (F_EMPTY && (A_EN ^ A_EN_INV));\r\n\twire ram_we = (~F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));\r\n\twire ram_en = (~F_EMPTY && (A_EN ^ A_EN_INV));\r\n\r\n\t// Reset synchronizers\r\n\treg [1:0] aclk_reset_q, bclk_reset_q;\r\n\twire fifo_sync_rstn = aclk_reset_q;\r\n\twire fifo_async_wrrstn = bclk_reset_q;\r\n\twire fifo_async_rdrstn = aclk_reset_q;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\taclk_reset_q <= 2'b0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\taclk_reset_q[1] <= aclk_reset_q[0];\r\n\t\t\taclk_reset_q[0] <= 1'b1;\r\n\t\tend\r\n\tend\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\tbclk_reset_q <= 2'b0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tbclk_reset_q[1] <= bclk_reset_q[0];\r\n\t\t\tbclk_reset_q[0] <= 1'b1;\r\n\t\tend\r\n\tend\r\n\r\n\t// Push/pop pointers\r\n\treg [15:0] rd_pointer, rd_pointer_int;\r\n\treg [15:0] wr_pointer, wr_pointer_int;\r\n\treg [15:0] rd_pointer_cmp, wr_pointer_cmp;\r\n\twire [15:0] rd_pointer_nxt;\r\n\twire [15:0] wr_pointer_nxt;\r\n\treg [15:0] fifo_rdaddr, rdaddr;\r\n\treg [15:0] fifo_wraddr, wraddr;\r\n\tassign F_RD_PTR = fifo_rdaddr;\r\n\tassign F_WR_PTR = fifo_wraddr;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\trd_pointer <= 0;\r\n\t\t\trd_pointer_int <= 0;\r\n\t\tend\r\n\t\telse if (ram_en) begin\r\n\t\t\trd_pointer <= rd_pointer_nxt;\r\n\t\t\trd_pointer_int <= rd_pointer_nxt[15:1] ^ rd_pointer_nxt[14:0];\r\n\t\tend\r\n\tend\r\n\r\n\tassign rd_pointer_nxt = (rd_pointer == counter_max) ? (0) : (rd_pointer + 1'b1);\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\twr_pointer <= 0;\r\n\t\t\twr_pointer_int <= 0;\r\n\t\tend\r\n\t\telse if (ram_we) begin\r\n\t\t\twr_pointer <= wr_pointer_nxt;\r\n\t\t\twr_pointer_int <= wr_pointer_nxt[15:1] ^ wr_pointer_nxt[14:0];\r\n\t\tend\r\n\tend\r\n\r\n\tassign wr_pointer_nxt = (wr_pointer == counter_max) ? (0) : (wr_pointer + 1'b1);\r\n\r\n\t// Address synchronizers\r\n\treg [15:0] rd_pointer_sync, wr_pointer_sync;\r\n\treg [15:0] rd_pointer_sync_0, rd_pointer_sync_1;\r\n\treg [15:0] wr_pointer_sync_0, wr_pointer_sync_1;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\twr_pointer_sync_0 <= 0;\r\n\t\t\twr_pointer_sync_1 <= 0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\twr_pointer_sync_0 <= wraddr;\r\n\t\t\twr_pointer_sync_1 <= wr_pointer_sync_0;\r\n\t\tend\r\n\t end\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\t begin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\trd_pointer_sync_0 <= 0;\r\n\t\t\trd_pointer_sync_1 <= 0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\trd_pointer_sync_0 <= rdaddr;\r\n\t\t\trd_pointer_sync_1 <= rd_pointer_sync_0;\r\n\t\tend\r\n\t end\r\n\r\n\talways @(*) begin\r\n\t\tfifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}};\r\n\t\tfifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}};\r\n\r\n\t\trdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]};\r\n\t\twraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]};\r\n\r\n\t\tif (FIFO_MODE == \"ASYNC\")\r\n\t\t\tfifo_full = (wraddr[tp-2:0] == rd_pointer_sync_1[tp-2:0] ) && (wraddr[tp] != rd_pointer_sync_1[tp] ) && ( wraddr[tp-1] != rd_pointer_sync_1[tp-1] );\r\n\t\telse\r\n\t\t\tfifo_full = (wr_pointer[tp-1:0] == rd_pointer[tp-1:0]) && (wr_pointer[tp] ^ rd_pointer[tp]);\r\n\r\n\t\tif (FIFO_MODE == \"ASYNC\")\r\n\t\t\tfifo_empty = (wr_pointer_sync_1[tp:0] == rdaddr[tp:0]);\r\n\t\telse\r\n\t\t\tfifo_empty = (wr_pointer[tp:0] == rd_pointer[tp:0]);\r\n\r\n\t\trd_pointer_cmp = (FIFO_MODE == \"ASYNC\") ? rd_pointer_sync : rd_pointer;\r\n\t\tif (wr_pointer[tp] == rd_pointer_cmp[tp])\r\n\t\t\tfifo_almost_full = ((wr_pointer[tp-1:0] - rd_pointer_cmp[tp-1:0]) >= (sram_depth - almost_full_offset));\r\n\t\telse\r\n\t\t\tfifo_almost_full = ((rd_pointer_cmp[tp-1:0] - wr_pointer[tp-1:0]) <= almost_full_offset);\r\n\r\n\t\twr_pointer_cmp = (FIFO_MODE == \"ASYNC\") ? wr_pointer_sync : wr_pointer;\r\n\t\tif (wr_pointer_cmp[tp] == rd_pointer[tp])\r\n\t\t\tfifo_almost_empty = ((wr_pointer_cmp[tp-1:0] - rd_pointer[tp-1:0]) <= almost_empty_offset);\r\n\t\telse\r\n\t\t\tfifo_almost_empty = ((rd_pointer[tp-1:0] - wr_pointer_cmp[tp-1:0]) >= (sram_depth - almost_empty_offset));\r\n\tend\r\n\r\n\tgenerate\r\n\t\talways @(*) begin\r\n\t\t\twr_pointer_sync = 0;\r\n\t\t\trd_pointer_sync = 0;\r\n\t\t\tfor (i=tp; i >= 0; i=i-1) begin\r\n\t\t\t\tif (i == tp) begin\r\n\t\t\t\t\twr_pointer_sync[i] = wr_pointer_sync_1[i];\r\n\t\t\t\t\trd_pointer_sync[i] = rd_pointer_sync_1[i];\r\n\t\t\t\tend\r\n\t\t\t\telse begin\r\n\t\t\t\t\twr_pointer_sync[i] = wr_pointer_sync_1[i] ^ wr_pointer_sync[i+1];\r\n\t\t\t\t\trd_pointer_sync[i] = rd_pointer_sync_1[i] ^ rd_pointer_sync[i+1];\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP push ports A+B\r\n\t\t\talways @(posedge fifo_wrclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ram_we && A_BM[k]) memory[fifo_wraddr+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ram_we && B_BM[k-40]) memory[fifo_wraddr+k] <= B_DI[k-40];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP pop ports A+B\r\n\t\t\talways @(posedge fifo_rdclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ram_en) A_DO_out[k] <= memory[fifo_rdaddr+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ram_en) B_DO_out[k-40] <= memory[fifo_rdaddr+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// TDP pop port A\r\n\t\t\talways @(posedge fifo_rdclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < A_WIDTH; i=i+1) begin\r\n\t\t\t\t\tif (ram_en) begin\r\n\t\t\t\t\t\tA_DO_out[i] <= memory[fifo_rdaddr+i];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP push port B\r\n\t\t\talways @(posedge fifo_wrclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < B_WIDTH; i=i+1) begin\r\n\t\t\t\t\tif (ram_we && B_BM[i])\r\n\t\t\t\t\t\tmemory[fifo_wraddr+i] <= B_DI[i];\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge fifo_rdclk) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge fifo_rdclk) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\n// Models of the LUT2 tree primitives\r\nmodule CC_L2T4(\r\n\toutput O,\r\n\tinput I0, I1, I2, I3\r\n);\r\n\tparameter [3:0] INIT_L00 = 4'b0000;\r\n\tparameter [3:0] INIT_L01 = 4'b0000;\r\n\tparameter [3:0] INIT_L10 = 4'b0000;\r\n\r\n\twire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0];\r\n\twire l00 = I0 ? l00_s1[1] : l00_s1[0];\r\n\r\n\twire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0];\r\n\twire l01 = I2 ? l01_s1[1] : l01_s1[0];\r\n\r\n\twire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0];\r\n\tassign O = l00 ? l10_s1[1] : l10_s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_L2T5(\r\n\toutput O,\r\n\tinput I0, I1, I2, I3, I4\r\n);\r\n\tparameter [3:0] INIT_L02 = 4'b0000;\r\n\tparameter [3:0] INIT_L03 = 4'b0000;\r\n\tparameter [3:0] INIT_L11 = 4'b0000;\r\n\tparameter [3:0] INIT_L20 = 4'b0000;\r\n\r\n\twire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0];\r\n\twire l02 = I0 ? l02_s1[1] : l02_s1[0];\r\n\r\n\twire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0];\r\n\twire l03 = I2 ? l03_s1[1] : l03_s1[0];\r\n\r\n\twire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0];\r\n\twire l11 = l02 ? l11_s1[1] : l11_s1[0];\r\n\r\n\twire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0];\r\n\tassign O = I4 ? l20_s1[1] : l20_s1[0];\r\n\r\nendmodule\r\n",
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87
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"inv_map.v": "// Any inverters not folded into LUTs are mapped to a LUT of their own\nmodule \\$__CC_NOT (input A, output Y);\n\tCC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y));\nendmodule\n",
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88
88
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"lut_map.v": "/*\r\n * yosys -- Yosys Open SYnthesis Suite\r\n *\r\n * Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>\r\n *\r\n * Permission to use, copy, modify, and/or distribute this software for any\r\n * purpose with or without fee is hereby granted, provided that the above\r\n * copyright notice and this permission notice appear in all copies.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\nmodule \\$lut (A, Y);\r\n\tparameter WIDTH = 0;\r\n\tparameter LUT = 0;\r\n\r\n\t(* force_downto *)\r\n\tinput [WIDTH-1:0] A;\r\n\toutput Y;\r\n\r\n\tgenerate\r\n\t\tif (WIDTH == 1) begin\r\n\t\t\tCC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));\r\n\t\tend\r\n\t\telse if (WIDTH == 2) begin\r\n\t\t\tCC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));\r\n\t\tend\r\n\t\telse if (WIDTH == 3) begin\r\n\t\t\tCC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));\r\n\t\tend\r\n\t\telse if (WIDTH == 4) begin\r\n\t\t\tCC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\r\n\t\tend\r\n\t\telse begin\r\n\t\t\twire _TECHMAP_FAIL_ = 1;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n",
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"lut_tree_cells.genlib": "GATE $__ZERO 0 Y=CONST0;\nGATE $__ONE 0 Y=CONST1;\n\nGATE $__CC_BUF 5 Y=A;\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC_NOT 0 Y=!A;\nPIN * INV 1 9999 10 5 10 5\n\nGATE $__CC_MUX 5 Y=((A*!C)+(B*C));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC2_A 10 Y=(A*B);\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC3_A_O 12 Y=(E+(A*B));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC3_A_X 12 Y=((E*(!A+!B))+(!E*(A*B)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC2_O 10 Y=(A+B);\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC3_O_A 12 Y=(E*(A+B));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC3_O_X 12 Y=((E*(!A*!B))+(!E*(A+B)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC2_X 10 Y=((A*!B)+(!A*B));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_X_A 12 Y=(E*((A*!B)+(!A*B)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_X_O 12 Y=(E+((A*!B)+(!A*B)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_AA 10 Y=((A*B)*C);\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_AA_O 12 Y=(E+((A*B)*C));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_AA_X 12 Y=((E*((!A+!B)+!C))+(!E*((A*B)*C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_OO 10 Y=((A+B)+C);\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_OO_A 12 Y=(E*((A+B)+C));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_OO_X 12 Y=((E*((!A*!B)*!C))+(!E*((A+B)+C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_XX 10 Y=((((A*!B)+(!A*B))*!C)+(((!A+B)*(A+!B))*C));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_XX_A 12 Y=(E*((((A*!B)+(!A*B))*!C)+(((!A+B)*(A+!B))*C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_XX_O 12 Y=(E+((((A*!B)+(!A*B))*!C)+(((!A+B)*(A+!B))*C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_AO 10 Y=((A*B)+C);\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_AO_A 12 Y=(E*((A*B)+C));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_AO_O 12 Y=(E+((A*B)+C));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_AO_X 12 Y=((E*((!A+!B)*!C))+(!E*((A*B)+C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_OA 10 Y=((A+B)*C);\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_OA_A 12 Y=(E*((A+B)*C));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_OA_O 12 Y=(E+((A+B)*C));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC4_OA_X 12 Y=((E*((!A*!B)+!C))+(!E*((A+B)*C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_AX 10 Y=(((A*B)*!C)+((!A+!B)*C));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AX_A 12 Y=(E*(((A*B)*!C)+((!A+!B)*C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AX_O 12 Y=(E+(((A*B)*!C)+((!A+!B)*C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AX_X 12 Y=((E*(((!A+!B)+C)*((A*B)+!C)))+(!E*(((A*B)*!C)+((!A+!B)*C))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC3_XA 10 Y=(((A*!B)+(!A*B))*C);\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_XA_A 12 Y=(E*(((A*!B)+(!A*B))*C));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_XA_O 12 Y=(E+(((A*!B)+(!A*B))*C));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_XA_X 12 Y=((E*(((!A+B)*(A+!B))+!C))+(!E*(((A*!B)+(!A*B))*C)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AAA 10 Y=((A*B)*(C*D));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AAA_A 12 Y=(E*((A*B)*(C*D)));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AAA_O 12 Y=(E+((A*B)*(C*D)));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AAA_X 12 Y=((E*((!A+!B)+(!C+!D)))+(!E*((A*B)*(C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AXA 10 Y=(((A*B)*(!C+!D))+((!A+!B)*(C*D)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AXA_A 12 Y=(E*(((A*B)*(!C+!D))+((!A+!B)*(C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AXA_O 12 Y=(E+(((A*B)*(!C+!D))+((!A+!B)*(C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AXA_X 12 Y=((E*(((!A+!B)+(C*D))*((A*B)+(!C+!D))))+(!E*(((A*B)*(!C+!D))+((!A+!B)*(C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_XAX 10 Y=(((A*!B)+(!A*B))*((C*!D)+(!C*D)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_XAX_A 12 Y=(E*(((A*!B)+(!A*B))*((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_XAX_O 12 Y=(E+(((A*!B)+(!A*B))*((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_XAX_X 12 Y=((E*(((!A+B)*(A+!B))+((!C+D)*(C+!D))))+(!E*(((A*!B)+(!A*B))*((C*!D)+(!C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AAX 10 Y=((A*B)*((C*!D)+(!C*D)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AAX_A 12 Y=(E*((A*B)*((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AAX_O 12 Y=(E+((A*B)*((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AAX_X 12 Y=((E*((!A+!B)+((!C+D)*(C+!D))))+(!E*((A*B)*((C*!D)+(!C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AXX 10 Y=(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AXX_A 12 Y=(E*(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AXX_O 12 Y=(E+(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AXX_X 12 Y=((E*(((!A+!B)+((C*!D)+(!C*D)))*((A*B)+((!C+D)*(C+!D)))))+(!E*(((A*B)*((!C+D)*(C+!D)))+((!A+!B)*((C*!D)+(!C*D))))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_XXX 10 Y=((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_XXX_A 12 Y=(E*((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_XXX_O 12 Y=(E+((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_XXX_X 12 Y=((E*((((!A+B)*(A+!B))+((C*!D)+(!C*D)))*(((A*!B)+(!A*B))+((!C+D)*(C+!D)))))+(!E*((((A*!B)+(!A*B))*((!C+D)*(C+!D)))+(((!A+B)*(A+!B))*((C*!D)+(!C*D))))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AAO 10 Y=((A*B)*(C+D));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AAO_A 12 Y=(E*((A*B)*(C+D)));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AAO_O 12 Y=(E+((A*B)*(C+D)));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AAO_X 12 Y=((E*((!A+!B)+(!C*!D)))+(!E*((A*B)*(C+D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AOA 10 Y=((A*B)+(C*D));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AOA_A 12 Y=(E*((A*B)+(C*D)));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AOA_O 12 Y=(E+((A*B)+(C*D)));\nPIN * NONINV 1 9999 10 5 10 5\n\nGATE $__CC5_AOA_X 12 Y=((E*((!A+!B)*(!C+!D)))+(!E*((A*B)+(C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC4_AOX 10 Y=((A*B)+((C*!D)+(!C*D)));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AOX_A 12 Y=(E*((A*B)+((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AOX_O 12 Y=(E+((A*B)+((C*!D)+(!C*D))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n\nGATE $__CC5_AOX_X 12 Y=((E*((!A+!B)*((!C+D)*(C+!D))))+(!E*((A*B)+((C*!D)+(!C*D)))));\nPIN * UNKNOWN 1 9999 10 5 10 5\n",
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@@ -110,7 +110,7 @@ export const filesystem = {
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"cells_map.v": "module GP_DFFS(input D, CLK, nSET, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DFFSR #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b1),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.CLK(CLK),\n\t\t.nSR(nSET),\n\t\t.Q(Q)\n\t);\nendmodule\n\nmodule GP_DFFR(input D, CLK, nRST, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DFFSR #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b0),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.CLK(CLK),\n\t\t.nSR(nRST),\n\t\t.Q(Q)\n\t);\nendmodule\n\nmodule GP_DFFSI(input D, CLK, nSET, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DFFSRI #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b1),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.CLK(CLK),\n\t\t.nSR(nSET),\n\t\t.nQ(nQ)\n\t);\nendmodule\n\nmodule GP_DFFRI(input D, CLK, nRST, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DFFSRI #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b0),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.CLK(CLK),\n\t\t.nSR(nRST),\n\t\t.nQ(nQ)\n\t);\nendmodule\n\nmodule GP_DLATCHS(input D, nCLK, nSET, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DLATCHSR #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b1),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.nCLK(nCLK),\n\t\t.nSR(nSET),\n\t\t.Q(Q)\n\t);\nendmodule\n\nmodule GP_DLATCHR(input D, nCLK, nRST, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DLATCHSR #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b0),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.nCLK(nCLK),\n\t\t.nSR(nRST),\n\t\t.Q(Q)\n\t);\nendmodule\n\nmodule GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DLATCHSRI #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b1),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.nCLK(nCLK),\n\t\t.nSR(nSET),\n\t\t.nQ(nQ)\n\t);\nendmodule\n\nmodule GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tGP_DLATCHSRI #(\n\t\t.INIT(INIT),\n\t\t.SRMODE(1'b0),\n\t) _TECHMAP_REPLACE_ (\n\t\t.D(D),\n\t\t.nCLK(nCLK),\n\t\t.nSR(nRST),\n\t\t.nQ(nQ)\n\t);\nendmodule\n\nmodule GP_OBUFT(input IN, input OE, output OUT);\n\tGP_IOBUF _TECHMAP_REPLACE_ (\n\t\t.IN(IN),\n\t\t.OE(OE),\n\t\t.IO(OUT),\n\t\t.OUT()\n\t);\nendmodule\n\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\tif(LUT == 2'b01) begin\n\t\t\tGP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );\n\t\tend\n\t\telse begin\n\t\t\tGP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),\n\t\t\t\t.IN0(A[0]), .IN1(1'b0));\n\t\tend\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tGP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),\n\t\t\t\t.IN0(A[0]), .IN1(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tGP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),\n\t\t\t\t.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tGP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),\n\t\t\t\t.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));\n\t\tend else begin\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\tend\n\tendgenerate\nendmodule\n\nmodule \\$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);\n\n\tinput wire CE;\n\tinput wire CLK;\n\toutput reg OUT;\n\t(* force_downto *)\n\toutput reg[WIDTH-1:0] POUT;\n\tinput wire RST;\n\tinput wire UP;\n\n\tparameter COUNT_TO = 1;\n\tparameter RESET_MODE = \"RISING\";\n\tparameter RESET_TO_MAX = 0;\n\tparameter HAS_POUT = 0;\n\tparameter HAS_CE = 0;\n\tparameter WIDTH = 8;\n\tparameter DIRECTION = \"DOWN\";\n\n\t//If we have a DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet\n\tif(DIRECTION != \"DOWN\") begin\n\t\tinitial begin\n\t\t\t$display(\"ERROR: \\$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\t//If counter is more than 14 bits wide, complain (also shouldn't happen)\n\telse if(WIDTH > 14) begin\n\t\tinitial begin\n\t\t\t$display(\"ERROR: \\$__COUNT_ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\t//If counter is more than 8 bits wide and has parallel output, we have a problem\n\telse if(WIDTH > 8 && HAS_POUT) begin\n\t\tinitial begin\n\t\t\t$display(\"ERROR: \\$__COUNT_ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\t//Looks like a legal counter! Do something with it\n\telse if(WIDTH <= 8) begin\n\t\tif(HAS_CE) begin\n\t\t\twire ce_not;\n\t\t\tGP_INV ceinv(\n\t\t\t\t.IN(CE),\n\t\t\t\t.OUT(ce_not)\n\t\t\t);\n\t\t\tGP_COUNT8_ADV #(\n\t\t\t\t.COUNT_TO(COUNT_TO),\n\t\t\t\t.RESET_MODE(RESET_MODE),\n\t\t\t\t.RESET_VALUE(RESET_TO_MAX ? \"COUNT_TO\" : \"ZERO\"),\n\t\t\t\t.CLKIN_DIVIDE(1)\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.CLK(CLK),\n\t\t\t\t.RST(RST),\n\t\t\t\t.OUT(OUT),\n\t\t\t\t.UP(1'b0),\t\t//always count down for now\n\t\t\t\t.KEEP(ce_not),\n\t\t\t\t.POUT(POUT)\n\t\t\t);\n\t\tend\n\t\telse begin\n\t\t\tGP_COUNT8 #(\n\t\t\t\t.COUNT_TO(COUNT_TO),\n\t\t\t\t.RESET_MODE(RESET_MODE),\n\t\t\t\t.CLKIN_DIVIDE(1)\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.CLK(CLK),\n\t\t\t\t.RST(RST),\n\t\t\t\t.OUT(OUT),\n\t\t\t\t.POUT(POUT)\n\t\t\t);\n\t\tend\n\tend\n\n\telse begin\n\t\tif(HAS_CE) begin\n\t\t\twire ce_not;\n\t\t\tGP_INV ceinv(\n\t\t\t\t.IN(CE),\n\t\t\t\t.OUT(ce_not)\n\t\t\t);\n\t\t\tGP_COUNT14_ADV #(\n\t\t\t\t.COUNT_TO(COUNT_TO),\n\t\t\t\t.RESET_MODE(RESET_TO_MAX ? \"COUNT_TO\" : \"ZERO\"),\n\t\t\t\t.RESET_VALUE(\"COUNT_TO\"),\n\t\t\t\t.CLKIN_DIVIDE(1)\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.CLK(CLK),\n\t\t\t\t.RST(RST),\n\t\t\t\t.OUT(OUT),\n\t\t\t\t.UP(1'b0),\t\t//always count down for now\n\t\t\t\t.KEEP(ce_not),\n\t\t\t\t.POUT(POUT)\n\t\t\t);\n\t\tend\n\t\telse begin\n\t\t\tGP_COUNT14 #(\n\t\t\t\t.COUNT_TO(COUNT_TO),\n\t\t\t\t.RESET_MODE(RESET_MODE),\n\t\t\t\t.CLKIN_DIVIDE(1)\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.CLK(CLK),\n\t\t\t\t.RST(RST),\n\t\t\t\t.OUT(OUT)\n\t\t\t);\n\t\tend\n\tend\n\nendmodule\n",
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"cells_sim.v": "`timescale 1ns/1ps\n\n`include \"cells_sim_ams.v\"\n`include \"cells_sim_digital.v\"\n`include \"cells_sim_wip.v\"\n",
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"cells_sim_ams.v": "`timescale 1ns/1ps\n\n/*\n This file contains analog / mixed signal cells, or other things that are not possible to fully model\n in behavioral Verilog.\n\n It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.\n TODO: do we want a third file for those cells?\n */\n\nmodule GP_ABUF(input wire IN, output wire OUT);\n\n\tassign OUT = IN;\n\n\t//must be 1, 5, 20, 50\n\t//values >1 only available with Vdd > 2.7V\n\tparameter BANDWIDTH_KHZ = 1;\n\nendmodule\n\nmodule GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);\n\n\tparameter BANDWIDTH = \"HIGH\";\n\tparameter VIN_ATTEN = 1;\n\tparameter VIN_ISRC_EN = 0;\n\tparameter HYSTERESIS = 0;\n\n\tinitial OUT = 0;\n\nendmodule\n\nmodule GP_BANDGAP(output reg OK);\n\tparameter AUTO_PWRDN = 1;\n\tparameter CHOPPER_EN = 1;\n\tparameter OUT_DELAY = 100;\n\nendmodule\n\nmodule GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);\n\n\tinitial VOUT = 0;\n\n\t//analog hard IP is not supported for simulation\n\nendmodule\n\nmodule GP_LFOSC(input PWRDN, output reg CLKOUT);\n\n\tparameter PWRDN_EN = 0;\n\tparameter AUTO_PWRDN = 0;\n\tparameter OUT_DIV = 1;\n\n\tinitial CLKOUT = 0;\n\n\t//auto powerdown not implemented for simulation\n\t//output dividers not implemented for simulation\n\n\talways begin\n\t\tif(PWRDN)\n\t\t\tCLKOUT = 0;\n\t\telse begin\n\t\t\t//half period of 1730 Hz\n\t\t\t#289017;\n\t\t\tCLKOUT = ~CLKOUT;\n\t\tend\n\tend\n\nendmodule\n\nmodule GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);\n\n\tparameter GAIN = 1;\n\tparameter INPUT_MODE = \"SINGLE\";\n\n\tinitial VOUT = 0;\n\n\t//cannot simulate mixed signal IP\n\nendmodule\n\nmodule GP_PWRDET(output reg VDD_LOW);\n\tinitial VDD_LOW = 0;\nendmodule\n\nmodule GP_VREF(input VIN, output reg VOUT);\n\tparameter VIN_DIV = 1;\n\tparameter VREF = 0;\n\t//cannot simulate mixed signal IP\nendmodule\n\nmodule GP_POR(output reg RST_DONE);\n\tparameter POR_TIME = 500;\n\n\tinitial begin\n\t\tRST_DONE = 0;\n\n\t\tif(POR_TIME == 4)\n\t\t\t#4000;\n\t\telse if(POR_TIME == 500)\n\t\t\t#500000;\n\t\telse begin\n\t\t\t$display(\"ERROR: bad POR_TIME for GP_POR cell\");\n\t\t\t$finish;\n\t\tend\n\n\t\tRST_DONE = 1;\n\n\tend\n\nendmodule\n",
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"cells_sim_digital.v": "`timescale 1ns/1ps\n\n/*\n This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable\n behavioral Verilog constructs only.\n */\n\nmodule GP_2LUT(input IN0, IN1, output OUT);\n\tparameter [3:0] INIT = 0;\n\tassign OUT = INIT[{IN1, IN0}];\nendmodule\n\nmodule GP_3LUT(input IN0, IN1, IN2, output OUT);\n\tparameter [7:0] INIT = 0;\n\tassign OUT = INIT[{IN2, IN1, IN0}];\nendmodule\n\nmodule GP_4LUT(\n\tinput wire IN0,\n\tinput wire IN1,\n\tinput wire IN2,\n\tinput wire IN3,\n\toutput wire OUT);\n\n\tparameter [15:0] INIT = 0;\n\tassign OUT = INIT[{IN3, IN2, IN1, IN0}];\nendmodule\n\nmodule GP_CLKBUF(input wire IN, output wire OUT);\n\tassign OUT = IN;\nendmodule\n\nmodule GP_COUNT14(input CLK, input wire RST, output reg OUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\n\tparameter COUNT_TO\t\t= 14'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\treg[13:0] count = COUNT_TO;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tOUT <= (count == 14'h0);\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\t\t\t\t\tif(!RST)\n\t\t\t\t\t\tcount\t\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT14 not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t\t<= 0;\n\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT14\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_COUNT14_ADV(input CLK, input RST, output reg OUT,\n input UP, input KEEP, output reg[7:0] POUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\tparameter RESET_VALUE = \"ZERO\";\n\n\tparameter COUNT_TO\t\t= 14'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\treg[13:0] count = COUNT_TO;\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tif(UP)\n\t\t\tOUT <= (count == 14'h3fff);\n\t\telse\n\t\t\tOUT <= (count == 14'h0);\n\t\tPOUT <= count[7:0];\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 14'h3fff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(!RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 14'h3fff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT14_ADV not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse begin\n\n\t\t\t\t\t\tif(KEEP) begin\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\t\tif(count == 14'h3fff)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse begin\n\t\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT14_ADV\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_COUNT8_ADV(input CLK, input RST, output reg OUT,\n input UP, input KEEP, output reg[7:0] POUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\tparameter RESET_VALUE = \"ZERO\";\n\n\tparameter COUNT_TO\t\t= 8'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\treg[7:0] count = COUNT_TO;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tif(UP)\n\t\t\tOUT <= (count == 8'hff);\n\t\telse\n\t\t\tOUT <= (count == 8'h0);\n\t\tPOUT <= count;\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\t//Main counter\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 8'hff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(!RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\t//Main counter\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 8'hff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT8_ADV not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse begin\n\n\t\t\t\t\t\tif(KEEP) begin\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\t\tif(count == 8'hff)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse begin\n\t\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT8_ADV\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_COUNT8(\n\tinput wire CLK,\n\tinput wire RST,\n\toutput reg OUT,\n\toutput reg[7:0] POUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\n\tparameter COUNT_TO\t\t= 8'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\treg[7:0] count = COUNT_TO;\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tOUT <= (count == 8'h0);\n\t\tPOUT <= count;\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\t\t\t\t\tif(!RST)\n\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT8 not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t<= 0;\n\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT8\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_DCMPREF(output reg[7:0]OUT);\n\tparameter[7:0] REF_VAL = 8'h00;\n\tinitial OUT = REF_VAL;\nendmodule\n\nmodule GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);\n\n\talways @(*) begin\n\t\tcase(SEL)\n\t\t\t2'd00: begin\n\t\t\t\tOUTA <= IN0;\n\t\t\t\tOUTB <= IN3;\n\t\t\tend\n\n\t\t\t2'd01: begin\n\t\t\t\tOUTA <= IN1;\n\t\t\t\tOUTB <= IN2;\n\t\t\tend\n\n\t\t\t2'd02: begin\n\t\t\t\tOUTA <= IN2;\n\t\t\t\tOUTB <= IN1;\n\t\t\tend\n\n\t\t\t2'd03: begin\n\t\t\t\tOUTA <= IN3;\n\t\t\t\tOUTB <= IN0;\n\t\t\tend\n\n\t\tendcase\n\tend\nendmodule\n\nmodule GP_DELAY(input IN, output reg OUT);\n\n\tparameter DELAY_STEPS = 1;\n\tparameter GLITCH_FILTER = 0;\n\n\tinitial OUT = 0;\n\n\tgenerate\n\n\t\tif(GLITCH_FILTER) begin\n\t\t\tinitial begin\n\t\t\t\t$display(\"ERROR: GP_DELAY glitch filter mode not implemented\");\n\t\t\t\t$finish;\n\t\t\tend\n\t\tend\n\n\t\t//TODO: These delays are PTV dependent! For now, hard code 3v3 timing\n\t\t//Change simulation-mode delay depending on global Vdd range (how to specify this?)\n\t\talways @(*) begin\n\t\t\tcase(DELAY_STEPS)\n\t\t\t\t1: #166 OUT = IN;\n\t\t\t\t2: #318 OUT = IN;\n\t\t\t\t2: #471 OUT = IN;\n\t\t\t\t3: #622 OUT = IN;\n\t\t\t\tdefault: begin\n\t\t\t\t\t$display(\"ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\tendgenerate\n\nendmodule\n\nmodule GP_DFF(input D, CLK, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK) begin\n\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFI(input D, CLK, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK) begin\n\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DFFR(input D, CLK, nRST, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK, negedge nRST) begin\n\t\tif (!nRST)\n\t\t\tQ <= 1'b0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFRI(input D, CLK, nRST, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK, negedge nRST) begin\n\t\tif (!nRST)\n\t\t\tnQ <= 1'b1;\n\t\telse\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DFFS(input D, CLK, nSET, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK, negedge nSET) begin\n\t\tif (!nSET)\n\t\t\tQ <= 1'b1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFSI(input D, CLK, nSET, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK, negedge nSET) begin\n\t\tif (!nSET)\n\t\t\tnQ <= 1'b0;\n\t\telse\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DFFSR(input D, CLK, nSR, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter [0:0] SRMODE = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK, negedge nSR) begin\n\t\tif (!nSR)\n\t\t\tQ <= SRMODE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFSRI(input D, CLK, nSR, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter [0:0] SRMODE = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK, negedge nSR) begin\n\t\tif (!nSR)\n\t\t\tnQ <= ~SRMODE;\n\t\telse\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DLATCH(input D, input nCLK, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nCLK)\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DLATCHI(input D, input nCLK, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nCLK)\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nRST)\n\t\t\tQ <= 1'b0;\n\t\telse if(!nCLK)\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nRST)\n\t\t\tnQ <= 1'b1;\n\t\telse if(!nCLK)\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nSET)\n\t\t\tQ <= 1'b1;\n\t\telse if(!nCLK)\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nSET)\n\t\t\tnQ <= 1'b0;\n\t\telse if(!nCLK)\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter[0:0] SRMODE = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nSR)\n\t\t\tQ <= SRMODE;\n\t\telse if(!nCLK)\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter[0:0] SRMODE = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nSR)\n\t\t\tnQ <= ~SRMODE;\n\t\telse if(!nCLK)\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_IBUF(input IN, output OUT);\n\tassign OUT = IN;\nendmodule\n\nmodule GP_IOBUF(input IN, input OE, output OUT, inout IO);\n\tassign OUT = IO;\n\tassign IO = OE ? IN : 1'bz;\nendmodule\n\nmodule GP_INV(input IN, output OUT);\n\tassign OUT = ~IN;\nendmodule\n\nmodule GP_OBUF(input IN, output OUT);\n\tassign OUT = IN;\nendmodule\n\nmodule GP_OBUFT(input IN, input OE, output OUT);\n\tassign OUT = OE ? IN : 1'bz;\nendmodule\n\nmodule GP_PGEN(input wire nRST, input wire CLK, output reg OUT);\n\tinitial OUT = 0;\n\tparameter PATTERN_DATA = 16'h0;\n\tparameter PATTERN_LEN = 5'd16;\n\n\tlocalparam COUNT_MAX = PATTERN_LEN - 1'h1;\n\n\treg[3:0] count = 0;\n\talways @(posedge CLK, negedge nRST) begin\n\n\t\tif(!nRST)\n\t\t\tcount\t<= 0;\n\n\t\telse begin\n\t\t\tcount\t<= count - 1'h1;\n\t\t\tif(count == 0)\n\t\t\t\tcount <= COUNT_MAX;\n\t\tend\n\tend\n\n\talways @(*)\n\t\tOUT\t= PATTERN_DATA[count];\n\nendmodule\n\nmodule GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);\n\n\tparameter OUTA_TAP = 1;\n\tparameter OUTA_INVERT = 0;\n\tparameter OUTB_TAP = 1;\n\n\treg[15:0] shreg = 0;\n\n\talways @(posedge CLK, negedge nRST) begin\n\n\t\tif(!nRST)\n\t\t\tshreg = 0;\n\n\t\telse\n\t\t\tshreg <= {shreg[14:0], IN};\n\n\tend\n\n\tassign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];\n\tassign OUTB = shreg[OUTB_TAP - 1];\n\nendmodule\n\nmodule GP_VDD(output OUT);\n assign OUT = 1;\nendmodule\n\nmodule GP_VSS(output OUT);\n assign OUT = 0;\nendmodule\n",
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"cells_sim_digital.v": "`timescale 1ns/1ps\n\n/*\n This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable\n behavioral Verilog constructs only.\n */\n\nmodule GP_2LUT(input IN0, IN1, output OUT);\n\tparameter [3:0] INIT = 0;\n\tassign OUT = INIT[{IN1, IN0}];\nendmodule\n\nmodule GP_3LUT(input IN0, IN1, IN2, output OUT);\n\tparameter [7:0] INIT = 0;\n\tassign OUT = INIT[{IN2, IN1, IN0}];\nendmodule\n\nmodule GP_4LUT(\n\tinput wire IN0,\n\tinput wire IN1,\n\tinput wire IN2,\n\tinput wire IN3,\n\toutput wire OUT);\n\n\tparameter [15:0] INIT = 0;\n\tassign OUT = INIT[{IN3, IN2, IN1, IN0}];\nendmodule\n\nmodule GP_CLKBUF(input wire IN, output wire OUT);\n\tassign OUT = IN;\nendmodule\n\nmodule GP_COUNT14(input CLK, input wire RST, output reg OUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\n\tparameter COUNT_TO\t\t= 14'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\treg[13:0] count = COUNT_TO;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tOUT = (count == 14'h0);\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\t\t\t\t\tif(!RST)\n\t\t\t\t\t\tcount\t\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT14 not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t\t<= 0;\n\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT14\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_COUNT14_ADV(input CLK, input RST, output reg OUT,\n input UP, input KEEP, output reg[7:0] POUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\tparameter RESET_VALUE = \"ZERO\";\n\n\tparameter COUNT_TO\t\t= 14'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\treg[13:0] count = COUNT_TO;\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tif(UP)\n\t\t\tOUT = (count == 14'h3fff);\n\t\telse\n\t\t\tOUT = (count == 14'h0);\n\t\tPOUT = count[7:0];\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 14'h3fff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(!RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 14'h3fff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT14_ADV not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse begin\n\n\t\t\t\t\t\tif(KEEP) begin\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\t\tif(count == 14'h3fff)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse begin\n\t\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT14_ADV\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_COUNT8_ADV(input CLK, input RST, output reg OUT,\n input UP, input KEEP, output reg[7:0] POUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\tparameter RESET_VALUE = \"ZERO\";\n\n\tparameter COUNT_TO\t\t= 8'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\treg[7:0] count = COUNT_TO;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tif(UP)\n\t\t\tOUT = (count == 8'hff);\n\t\telse\n\t\t\tOUT = (count == 8'h0);\n\t\tPOUT = count;\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\t//Main counter\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 8'hff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(!RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\t//Main counter\n\t\t\t\t\telse if(KEEP) begin\n\t\t\t\t\tend\n\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\tif(count == 8'hff)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT8_ADV not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\n\t\t\t\t\t//Resets\n\t\t\t\t\tif(RST) begin\n\t\t\t\t\t\tif(RESET_VALUE == \"ZERO\")\n\t\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\n\t\t\t\t\telse begin\n\n\t\t\t\t\t\tif(KEEP) begin\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse if(UP) begin\n\t\t\t\t\t\t\tcount\t\t<= count + 1'd1;\n\t\t\t\t\t\t\tif(count == 8'hff)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\t\t\t\t\t\telse begin\n\t\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\n\t\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT8_ADV\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_COUNT8(\n\tinput wire CLK,\n\tinput wire RST,\n\toutput reg OUT,\n\toutput reg[7:0] POUT);\n\n\tparameter RESET_MODE \t= \"RISING\";\n\n\tparameter COUNT_TO\t\t= 8'h1;\n\tparameter CLKIN_DIVIDE\t= 1;\n\n\tinitial begin\n\t\tif(CLKIN_DIVIDE != 1) begin\n\t\t\t$display(\"ERROR: CLKIN_DIVIDE values other than 1 not implemented\");\n\t\t\t$finish;\n\t\tend\n\tend\n\n\treg[7:0] count = COUNT_TO;\n\n\t//Combinatorially output underflow flag whenever we wrap low\n\talways @(*) begin\n\t\tOUT = (count == 8'h0);\n\t\tPOUT = count;\n\tend\n\n\t//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.\n\t//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.\n\tgenerate\n\t\tcase(RESET_MODE)\n\n\t\t\t\"RISING\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"FALLING\": begin\n\t\t\t\talways @(posedge CLK, negedge RST) begin\n\t\t\t\t\tif(!RST)\n\t\t\t\t\t\tcount\t<= 0;\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"BOTH\": begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Both-edge reset mode for GP_COUNT8 not implemented\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t\"LEVEL\": begin\n\t\t\t\talways @(posedge CLK, posedge RST) begin\n\t\t\t\t\tif(RST)\n\t\t\t\t\t\tcount\t<= 0;\n\n\t\t\t\t\telse begin\n\t\t\t\t\t\tcount\t\t<= count - 1'd1;\n\t\t\t\t\t\tif(count == 0)\n\t\t\t\t\t\t\tcount\t<= COUNT_TO;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tdefault: begin\n\t\t\t\tinitial begin\n\t\t\t\t\t$display(\"Invalid RESET_MODE on GP_COUNT8\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendcase\n\tendgenerate\n\nendmodule\n\nmodule GP_DCMPREF(output reg[7:0]OUT);\n\tparameter[7:0] REF_VAL = 8'h00;\n\tinitial OUT = REF_VAL;\nendmodule\n\nmodule GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);\n\n\talways @(*) begin\n\t\tcase(SEL)\n\t\t\t2'd00: begin\n\t\t\t\tOUTA = IN0;\n\t\t\t\tOUTB = IN3;\n\t\t\tend\n\n\t\t\t2'd01: begin\n\t\t\t\tOUTA = IN1;\n\t\t\t\tOUTB = IN2;\n\t\t\tend\n\n\t\t\t2'd02: begin\n\t\t\t\tOUTA = IN2;\n\t\t\t\tOUTB = IN1;\n\t\t\tend\n\n\t\t\t2'd03: begin\n\t\t\t\tOUTA = IN3;\n\t\t\t\tOUTB = IN0;\n\t\t\tend\n\n\t\tendcase\n\tend\nendmodule\n\nmodule GP_DELAY(input IN, output reg OUT);\n\n\tparameter DELAY_STEPS = 1;\n\tparameter GLITCH_FILTER = 0;\n\n\tinitial OUT = 0;\n\n\tgenerate\n\n\t\tif(GLITCH_FILTER) begin\n\t\t\tinitial begin\n\t\t\t\t$display(\"ERROR: GP_DELAY glitch filter mode not implemented\");\n\t\t\t\t$finish;\n\t\t\tend\n\t\tend\n\n\t\t//TODO: These delays are PTV dependent! For now, hard code 3v3 timing\n\t\t//Change simulation-mode delay depending on global Vdd range (how to specify this?)\n\t\talways @(*) begin\n\t\t\tcase(DELAY_STEPS)\n\t\t\t\t1: #166 OUT = IN;\n\t\t\t\t2: #318 OUT = IN;\n\t\t\t\t2: #471 OUT = IN;\n\t\t\t\t3: #622 OUT = IN;\n\t\t\t\tdefault: begin\n\t\t\t\t\t$display(\"ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]\");\n\t\t\t\t\t$finish;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\tendgenerate\n\nendmodule\n\nmodule GP_DFF(input D, CLK, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK) begin\n\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFI(input D, CLK, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK) begin\n\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DFFR(input D, CLK, nRST, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK, negedge nRST) begin\n\t\tif (!nRST)\n\t\t\tQ <= 1'b0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFRI(input D, CLK, nRST, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK, negedge nRST) begin\n\t\tif (!nRST)\n\t\t\tnQ <= 1'b1;\n\t\telse\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DFFS(input D, CLK, nSET, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK, negedge nSET) begin\n\t\tif (!nSET)\n\t\t\tQ <= 1'b1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFSI(input D, CLK, nSET, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK, negedge nSET) begin\n\t\tif (!nSET)\n\t\t\tnQ <= 1'b0;\n\t\telse\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DFFSR(input D, CLK, nSR, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter [0:0] SRMODE = 1'bx;\n\tinitial Q = INIT;\n\talways @(posedge CLK, negedge nSR) begin\n\t\tif (!nSR)\n\t\t\tQ <= SRMODE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nendmodule\n\nmodule GP_DFFSRI(input D, CLK, nSR, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter [0:0] SRMODE = 1'bx;\n\tinitial nQ = INIT;\n\talways @(posedge CLK, negedge nSR) begin\n\t\tif (!nSR)\n\t\t\tnQ <= ~SRMODE;\n\t\telse\n\t\t\tnQ <= ~D;\n\tend\nendmodule\n\nmodule GP_DLATCH(input D, input nCLK, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nCLK)\n\t\t\tQ = D;\n\tend\nendmodule\n\nmodule GP_DLATCHI(input D, input nCLK, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nCLK)\n\t\t\tnQ = ~D;\n\tend\nendmodule\n\nmodule GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nRST)\n\t\t\tQ = 1'b0;\n\t\telse if(!nCLK)\n\t\t\tQ = D;\n\tend\nendmodule\n\nmodule GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nRST)\n\t\t\tnQ = 1'b1;\n\t\telse if(!nCLK)\n\t\t\tnQ = ~D;\n\tend\nendmodule\n\nmodule GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nSET)\n\t\t\tQ = 1'b1;\n\t\telse if(!nCLK)\n\t\t\tQ = D;\n\tend\nendmodule\n\nmodule GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nSET)\n\t\t\tnQ = 1'b0;\n\t\telse if(!nCLK)\n\t\t\tnQ = ~D;\n\tend\nendmodule\n\nmodule GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter[0:0] SRMODE = 1'bx;\n\tinitial Q = INIT;\n\talways @(*) begin\n\t\tif(!nSR)\n\t\t\tQ = SRMODE;\n\t\telse if(!nCLK)\n\t\t\tQ = D;\n\tend\nendmodule\n\nmodule GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);\n\tparameter [0:0] INIT = 1'bx;\n\tparameter[0:0] SRMODE = 1'bx;\n\tinitial nQ = INIT;\n\talways @(*) begin\n\t\tif(!nSR)\n\t\t\tnQ = ~SRMODE;\n\t\telse if(!nCLK)\n\t\t\tnQ = ~D;\n\tend\nendmodule\n\nmodule GP_IBUF(input IN, output OUT);\n\tassign OUT = IN;\nendmodule\n\nmodule GP_IOBUF(input IN, input OE, output OUT, inout IO);\n\tassign OUT = IO;\n\tassign IO = OE ? IN : 1'bz;\nendmodule\n\nmodule GP_INV(input IN, output OUT);\n\tassign OUT = ~IN;\nendmodule\n\nmodule GP_OBUF(input IN, output OUT);\n\tassign OUT = IN;\nendmodule\n\nmodule GP_OBUFT(input IN, input OE, output OUT);\n\tassign OUT = OE ? IN : 1'bz;\nendmodule\n\nmodule GP_PGEN(input wire nRST, input wire CLK, output reg OUT);\n\tinitial OUT = 0;\n\tparameter PATTERN_DATA = 16'h0;\n\tparameter PATTERN_LEN = 5'd16;\n\n\tlocalparam COUNT_MAX = PATTERN_LEN - 1'h1;\n\n\treg[3:0] count = 0;\n\talways @(posedge CLK, negedge nRST) begin\n\n\t\tif(!nRST)\n\t\t\tcount\t<= 0;\n\n\t\telse begin\n\t\t\tcount\t<= count - 1'h1;\n\t\t\tif(count == 0)\n\t\t\t\tcount <= COUNT_MAX;\n\t\tend\n\tend\n\n\talways @(*)\n\t\tOUT\t= PATTERN_DATA[count];\n\nendmodule\n\nmodule GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);\n\n\tparameter OUTA_TAP = 1;\n\tparameter OUTA_INVERT = 0;\n\tparameter OUTB_TAP = 1;\n\n\treg[15:0] shreg = 0;\n\n\talways @(posedge CLK, negedge nRST) begin\n\n\t\tif(!nRST)\n\t\t\tshreg = 0;\n\n\t\telse\n\t\t\tshreg <= {shreg[14:0], IN};\n\n\tend\n\n\tassign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];\n\tassign OUTB = shreg[OUTB_TAP - 1];\n\nendmodule\n\nmodule GP_VDD(output OUT);\n assign OUT = 1;\nendmodule\n\nmodule GP_VSS(output OUT);\n assign OUT = 0;\nendmodule\n",
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"cells_sim_wip.v": "\n//Cells still in this file have INCOMPLETE simulation models, need to finish them\n\nmodule GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);\n\tparameter PWRDN_SYNC = 1'b0;\n\tparameter CLK_EDGE = \"RISING\";\n\tparameter GREATER_OR_EQUAL = 1'b0;\n\n\t//TODO implement power-down mode\n\n\tinitial GREATER = 0;\n\tinitial EQUAL = 0;\n\n\twire clk_minv = (CLK_EDGE == \"RISING\") ? CLK : ~CLK;\n\talways @(posedge clk_minv) begin\n\t\tif(GREATER_OR_EQUAL)\n\t\t\tGREATER <= (INP >= INN);\n\t\telse\n\t\t\tGREATER <= (INP > INN);\n\n\t\tEQUAL <= (INP == INN);\n\tend\n\nendmodule\n\nmodule GP_EDGEDET(input IN, output reg OUT);\n\n\tparameter EDGE_DIRECTION = \"RISING\";\n\tparameter DELAY_STEPS = 1;\n\tparameter GLITCH_FILTER = 0;\n\n\t//not implemented for simulation\n\nendmodule\n\nmodule GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);\n\n\tparameter PWRDN_EN = 0;\n\tparameter AUTO_PWRDN = 0;\n\tparameter HARDIP_DIV = 1;\n\tparameter FABRIC_DIV = 1;\n\tparameter OSC_FREQ = \"25k\";\n\n\tinitial CLKOUT_HARDIP = 0;\n\tinitial CLKOUT_FABRIC = 0;\n\n\t//output dividers not implemented for simulation\n\t//auto powerdown not implemented for simulation\n\n\talways begin\n\t\tif(PWRDN) begin\n\t\t\tCLKOUT_HARDIP = 0;\n\t\t\tCLKOUT_FABRIC = 0;\n\t\tend\n\t\telse begin\n\n\t\t\tif(OSC_FREQ == \"25k\") begin\n\t\t\t\t//half period of 25 kHz\n\t\t\t\t#20000;\n\t\t\tend\n\n\t\t\telse begin\n\t\t\t\t//half period of 2 MHz\n\t\t\t\t#250;\n\t\t\tend\n\n\t\t\tCLKOUT_HARDIP = ~CLKOUT_HARDIP;\n\t\t\tCLKOUT_FABRIC = ~CLKOUT_FABRIC;\n\t\tend\n\tend\n\nendmodule\n\nmodule GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);\n\n\tparameter PWRDN_EN = 0;\n\tparameter AUTO_PWRDN = 0;\n\tparameter HARDIP_DIV = 1;\n\tparameter FABRIC_DIV = 1;\n\n\tinitial CLKOUT_HARDIP = 0;\n\tinitial CLKOUT_FABRIC = 0;\n\n\t//output dividers not implemented for simulation\n\t//auto powerdown not implemented for simulation\n\n\talways begin\n\t\tif(PWRDN) begin\n\t\t\tCLKOUT_HARDIP = 0;\n\t\t\tCLKOUT_FABRIC = 0;\n\t\tend\n\t\telse begin\n\t\t\t//half period of 27 MHz\n\t\t\t#18.518;\n\t\t\tCLKOUT_HARDIP = ~CLKOUT_HARDIP;\n\t\t\tCLKOUT_FABRIC = ~CLKOUT_FABRIC;\n\t\tend\n\tend\n\nendmodule\n\nmodule GP_SPI(\n\tinput SCK,\n\tinout SDAT,\n\tinput CSN,\n\tinput[7:0] TXD_HIGH,\n\tinput[7:0] TXD_LOW,\n\toutput reg[7:0] RXD_HIGH,\n\toutput reg[7:0] RXD_LOW,\n\toutput reg INT);\n\n\tinitial RXD_HIGH = 0;\n\tinitial RXD_LOW = 0;\n\tinitial INT = 0;\n\n\tparameter DATA_WIDTH = 8;\t\t//byte or word width\n\tparameter SPI_CPHA = 0;\t\t\t//SPI clock phase\n\tparameter SPI_CPOL = 0;\t\t\t//SPI clock polarity\n\tparameter DIRECTION = \"INPUT\";\t//SPI data direction (either input to chip or output to host)\n\t//parallel output to fabric not yet implemented\n\n\t//TODO: write sim model\n\t//TODO: SPI SDIO control... can we use ADC output while SPI is input??\n\t//TODO: clock sync\n\nendmodule\n\n//keep constraint needed to prevent optimization since we have no outputs\n(* keep *)\nmodule GP_SYSRESET(input RST);\n\tparameter RESET_MODE = \"EDGE\";\n\tparameter EDGE_SPEED = 4;\n\n\t//cannot simulate whole system reset\n\nendmodule\n",
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"gp_dff.lib": "library(gp_dff) {\n cell(GP_DFF) {\n area: 1;\n ff(\"IQ\", \"IQN\") { clocked_on: CLK;\n next_state: D; }\n pin(CLK) { direction: input;\n clock: true; }\n pin(D) { direction: input; }\n pin(Q) { direction: output;\n function: \"IQ\"; }\n }\n cell(GP_DFFS) {\n area: 1;\n ff(\"IQ\", \"IQN\") { clocked_on: CLK;\n next_state: D;\n preset: \"nSET'\"; }\n pin(CLK) { direction: input;\n clock: true; }\n pin(D) { direction: input; }\n pin(Q) { direction: output;\n function: \"IQ\"; }\n pin(nSET) { direction: input; }\n }\n cell(GP_DFFR) {\n area: 1;\n ff(\"IQ\", \"IQN\") { clocked_on: CLK;\n next_state: D;\n clear: \"nRST'\"; }\n pin(CLK) { direction: input;\n clock: true; }\n pin(D) { direction: input; }\n pin(Q) { direction: output;\n function: \"IQ\"; }\n pin(nRST) { direction: input; }\n }\n}\n",
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"cxxrtl_capi.cc": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi.h`.\n\n#include <cxxrtl/capi/cxxrtl_capi.h>\n#include <cxxrtl/cxxrtl.h>\n\nstruct _cxxrtl_handle {\n\tstd::unique_ptr<cxxrtl::module> module;\n\tcxxrtl::debug_items objects;\n};\n\n// Private function for use by other units of the C API.\nconst cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle) {\n\treturn handle->objects;\n}\n\ncxxrtl_handle cxxrtl_create(cxxrtl_toplevel design) {\n\treturn cxxrtl_create_at(design, \"\");\n}\n\ncxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path_) {\n\tstd::string top_path = top_path_;\n\tif (!top_path.empty()) {\n\t\t// module::debug_info() accepts either an empty path, or a path ending in space to simplify\n\t\t// the logic in generated code. While this is sketchy at best to expose in the C++ API, this\n\t\t// would be a lot worse in the C API, so don't expose it here.\n\t\tassert(top_path.back() != ' ');\n\t\ttop_path += ' ';\n\t}\n\n\tcxxrtl_handle handle = new _cxxrtl_handle;\n\thandle->module = std::move(design->module);\n\thandle->module->debug_info(&handle->objects, nullptr, top_path);\n\tdelete design;\n\treturn handle;\n}\n\nvoid cxxrtl_destroy(cxxrtl_handle handle) {\n\tdelete handle;\n}\n\nvoid cxxrtl_reset(cxxrtl_handle handle) {\n\thandle->module->reset();\n}\n\nint cxxrtl_eval(cxxrtl_handle handle) {\n\treturn handle->module->eval();\n}\n\nint cxxrtl_commit(cxxrtl_handle handle) {\n\treturn handle->module->commit();\n}\n\nsize_t cxxrtl_step(cxxrtl_handle handle) {\n\treturn handle->module->step();\n}\n\nstruct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, size_t *parts) {\n\tauto it = handle->objects.table.find(name);\n\tif (it == handle->objects.table.end())\n\t\treturn nullptr;\n\t*parts = it->second.size();\n\treturn static_cast<cxxrtl_object*>(&it->second[0]);\n}\n\nvoid cxxrtl_enum(cxxrtl_handle handle, void *data,\n void (*callback)(void *data, const char *name,\n cxxrtl_object *object, size_t parts)) {\n\tfor (auto &it : handle->objects.table)\n\t\tcallback(data, it.first.c_str(), static_cast<cxxrtl_object*>(&it.second[0]), it.second.size());\n}\n\nvoid cxxrtl_outline_eval(cxxrtl_outline outline) {\n\toutline->eval();\n}\n\nint cxxrtl_attr_type(cxxrtl_attr_set attrs_, const char *name) {\n\tauto attrs = (cxxrtl::metadata_map*)attrs_;\n\tif (!attrs->count(name))\n\t\treturn CXXRTL_ATTR_NONE;\n\tswitch (attrs->at(name).value_type) {\n\t\tcase cxxrtl::metadata::UINT:\n\t\t\treturn CXXRTL_ATTR_UNSIGNED_INT;\n\t\tcase cxxrtl::metadata::SINT:\n\t\t\treturn CXXRTL_ATTR_SIGNED_INT;\n\t\tcase cxxrtl::metadata::STRING:\n\t\t\treturn CXXRTL_ATTR_STRING;\n\t\tcase cxxrtl::metadata::DOUBLE:\n\t\t\treturn CXXRTL_ATTR_DOUBLE;\n\t\tdefault:\n\t\t\t// Present unsupported attribute type the same way as no attribute at all.\n\t\t\treturn CXXRTL_ATTR_NONE;\n\t}\n}\n\nuint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs_, const char *name) {\n\tauto &attrs = *(cxxrtl::metadata_map*)attrs_;\n\tassert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::UINT);\n\treturn attrs[name].as_uint();\n}\n\nint64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs_, const char *name) {\n\tauto &attrs = *(cxxrtl::metadata_map*)attrs_;\n\tassert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::SINT);\n\treturn attrs[name].as_sint();\n}\n\nconst char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs_, const char *name) {\n\tauto &attrs = *(cxxrtl::metadata_map*)attrs_;\n\tassert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::STRING);\n\treturn attrs[name].as_string().c_str();\n}\n\ndouble cxxrtl_attr_get_double(cxxrtl_attr_set attrs_, const char *name) {\n\tauto &attrs = *(cxxrtl::metadata_map*)attrs_;\n\tassert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::DOUBLE);\n\treturn attrs[name].as_double();\n}\n",
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"cxxrtl_capi.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_CAPI_H\n#define CXXRTL_CAPI_H\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.cc`.\n//\n// The CXXRTL C API makes it possible to drive CXXRTL designs using C or any other language that\n// supports the C ABI, for example, Python. It does not provide a way to implement black boxes.\n\n#include <stddef.h>\n#include <stdint.h>\n#include <assert.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// Opaque reference to a design toplevel.\n//\n// A design toplevel can only be used to create a design handle.\ntypedef struct _cxxrtl_toplevel *cxxrtl_toplevel;\n\n// The constructor for a design toplevel is provided as a part of generated code for that design.\n// Its prototype matches:\n//\n// cxxrtl_toplevel <design-name>_create();\n\n// Opaque reference to a design handle.\n//\n// A design handle is required by all operations in the C API.\ntypedef struct _cxxrtl_handle *cxxrtl_handle;\n\n// Create a design handle from a design toplevel.\n//\n// The `design` is consumed by this operation and cannot be used afterwards.\ncxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);\n\n// Create a design handle at a given hierarchy position from a design toplevel.\n//\n// This operation is similar to `cxxrtl_create`, except the full hierarchical name of every object\n// is prepended with `top_path`.\ncxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path);\n\n// Release all resources used by a design and its handle.\nvoid cxxrtl_destroy(cxxrtl_handle handle);\n\n// Reinitialize the design, replacing the internal state with the reset values while preserving\n// black boxes.\n//\n// This operation is essentially equivalent to a power-on reset. Values, wires, and memories are\n// returned to their reset state while preserving the state of black boxes and keeping all of\n// the interior pointers obtained with e.g. `cxxrtl_get` valid.\nvoid cxxrtl_reset(cxxrtl_handle handle);\n\n// Evaluate the design, propagating changes on inputs to the `next` value of internal state and\n// output wires.\n//\n// Returns 1 if the design is known to immediately converge, 0 otherwise.\nint cxxrtl_eval(cxxrtl_handle handle);\n\n// Commit the design, replacing the `curr` value of internal state and output wires with the `next`\n// value.\n//\n// Return 1 if any of the `curr` values were updated, 0 otherwise.\nint cxxrtl_commit(cxxrtl_handle handle);\n\n// Simulate the design to a fixed point.\n//\n// Returns the number of delta cycles.\nsize_t cxxrtl_step(cxxrtl_handle handle);\n\n// Type of a simulated object.\n//\n// The type of a simulated object indicates the way it is stored and the operations that are legal\n// to perform on it (i.e. won't crash the simulation). It says very little about object semantics,\n// which is specified through flags.\nenum cxxrtl_type {\n\t// Values correspond to singly buffered netlist nodes, i.e. nodes driven exclusively by\n\t// combinatorial cells, or toplevel input nodes.\n\t//\n\t// Values can be inspected via the `curr` pointer. If the `next` pointer is NULL, the value is\n\t// driven by a constant and can never be modified. Otherwise, the value can be modified through\n\t// the `next` pointer (which is equal to `curr` if not NULL). Note that changes to the bits\n\t// driven by combinatorial cells will be ignored.\n\t//\n\t// Values always have depth 1.\n\tCXXRTL_VALUE = 0,\n\n\t// Wires correspond to doubly buffered netlist nodes, i.e. nodes driven, at least in part, by\n\t// storage cells, or by combinatorial cells that are a part of a feedback path. They are also\n\t// present in non-optimized builds.\n\t//\n\t// Wires can be inspected via the `curr` pointer and modified via the `next` pointer (which are\n\t// distinct for wires). Note that changes to the bits driven by combinatorial cells will be\n\t// ignored.\n\t//\n\t// Wires always have depth 1.\n\tCXXRTL_WIRE = 1,\n\n\t// Memories correspond to memory cells.\n\t//\n\t// Memories can be inspected and modified via the `curr` pointer. Due to a limitation of this\n\t// API, memories cannot yet be modified in a guaranteed race-free way, and the `next` pointer is\n\t// always NULL.\n\tCXXRTL_MEMORY = 2,\n\n\t// Aliases correspond to netlist nodes driven by another node such that their value is always\n\t// exactly equal.\n\t//\n\t// Aliases can be inspected via the `curr` pointer. They cannot be modified, and the `next`\n\t// pointer is always NULL.\n\tCXXRTL_ALIAS = 3,\n\n\t// Outlines correspond to netlist nodes that were optimized in a way that makes them inaccessible\n\t// outside of a module's `eval()` function. At the highest debug information level, every inlined\n\t// node has a corresponding outline object.\n\t//\n\t// Outlines can be inspected via the `curr` pointer and can never be modified; the `next` pointer\n\t// is always NULL. Unlike all other objects, the bits of an outline object are meaningful only\n\t// after a call to `cxxrtl_outline_eval` and until any subsequent modification to the netlist.\n\t// Observing this requirement is the responsibility of the caller; it is not enforced.\n\t//\n\t// Outlines always correspond to combinatorial netlist nodes that are not ports.\n\tCXXRTL_OUTLINE = 4,\n\n\t// More object types may be added in the future, but the existing ones will never change.\n};\n\n// Flags of a simulated object.\n//\n// The flags of a simulated object indicate its role in the netlist:\n// * The flags `CXXRTL_INPUT` and `CXXRTL_OUTPUT` designate module ports.\n// * The flags `CXXRTL_DRIVEN_SYNC`, `CXXRTL_DRIVEN_COMB`, and `CXXRTL_UNDRIVEN` specify\n// the semantics of node state. An object with several of these flags set has different bits\n// follow different semantics.\nenum cxxrtl_flag {\n\t// Node is a module input port.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined\n\t// with `CXXRTL_OUTPUT`, as well as other flags.\n\tCXXRTL_INPUT = 1 << 0,\n\n\t// Node is a module output port.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with `CXXRTL_INPUT`,\n\t// as well as other flags.\n\tCXXRTL_OUTPUT = 1 << 1,\n\n\t// Node is a module inout port.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with other flags.\n\tCXXRTL_INOUT = (CXXRTL_INPUT|CXXRTL_OUTPUT),\n\n\t// Node has bits that are driven by a storage cell.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with\n\t// `CXXRTL_DRIVEN_COMB` and `CXXRTL_UNDRIVEN`, as well as other flags.\n\t//\n\t// This flag is set on wires that have bits connected directly to the output of a flip-flop or\n\t// a latch, and hold its state. Many `CXXRTL_WIRE` objects may not have the `CXXRTL_DRIVEN_SYNC`\n\t// flag set; for example, output ports and feedback wires generally won't. Writing to the `next`\n\t// pointer of these wires updates stored state, and for designs without combinatorial loops,\n\t// capturing the value from every of these wires through the `curr` pointer creates a complete\n\t// snapshot of the design state.\n\tCXXRTL_DRIVEN_SYNC = 1 << 2,\n\n\t// Node has bits that are driven by a combinatorial cell or another node.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_VALUE`, `CXXRTL_WIRE`, and `CXXRTL_OUTLINE`.\n\t// It may be combined with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_UNDRIVEN`, as well as other flags.\n\t//\n\t// This flag is set on objects that have bits connected to the output of a combinatorial cell,\n\t// or directly to another node. For designs without combinatorial loops, writing to such bits\n\t// through the `next` pointer (if it is not NULL) has no effect.\n\tCXXRTL_DRIVEN_COMB = 1 << 3,\n\n\t// Node has bits that are not driven.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined\n\t// with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_DRIVEN_COMB`, as well as other flags.\n\t//\n\t// This flag is set on objects that have bits not driven by an output of any cell or by another\n\t// node, such as inputs and dangling wires.\n\tCXXRTL_UNDRIVEN = 1 << 4,\n\n\t// More object flags may be added in the future, but the existing ones will never change.\n};\n\n// Description of a simulated object.\n//\n// The `curr` and `next` arrays can be accessed directly to inspect and, if applicable, modify\n// the bits stored in the object.\nstruct cxxrtl_object {\n\t// Type of the object.\n\t//\n\t// All objects have the same memory layout determined by `width` and `depth`, but the type\n\t// determines all other properties of the object.\n\tuint32_t type; // actually `enum cxxrtl_type`\n\n\t// Flags of the object.\n\tuint32_t flags; // actually bit mask of `enum cxxrtl_flags`\n\n\t// Width of the object in bits.\n\tsize_t width;\n\n\t// Index of the least significant bit.\n\tsize_t lsb_at;\n\n\t// Depth of the object. Only meaningful for memories; for other objects, always 1.\n\tsize_t depth;\n\n\t// Index of the first word. Only meaningful for memories; for other objects, always 0;\n\tsize_t zero_at;\n\n\t// Bits stored in the object, as 32-bit chunks, least significant bits first.\n\t//\n\t// The width is rounded up to a multiple of 32; the padding bits are always set to 0 by\n\t// the simulation code, and must be always written as 0 when modified by user code.\n\t// In memories, every element is stored contiguously. Therefore, the total number of chunks\n\t// in any object is `((width + 31) / 32) * depth`.\n\t//\n\t// To allow the simulation to be partitioned into multiple independent units communicating\n\t// through wires, the bits are double buffered. To avoid race conditions, user code should\n\t// always read from `curr` and write to `next`. The `curr` pointer is always valid; for objects\n\t// that cannot be modified, or cannot be modified in a race-free way, `next` is NULL.\n\t//\n\t// In case where `width == 0`, `curr` is a non-NULL pointer unique for the wire. That is,\n\t// there is a 1-to-1 correspondence between simulation objects and `curr` pointers, regardless\n\t// of whether they have storage or not. (Aliases' `curr` pointer equals that of some other\n\t// simulated object.)\n\tuint32_t *curr;\n\tuint32_t *next;\n\n\t// Opaque reference to an outline. Only meaningful for outline objects.\n\t//\n\t// See the documentation of `cxxrtl_outline` for details. When creating a `cxxrtl_object`, set\n\t// this field to NULL.\n\tstruct _cxxrtl_outline *outline;\n\n\t// Opaque reference to an attribute set.\n\t//\n\t// See the documentation of `cxxrtl_attr_set` for details. When creating a `cxxrtl_object`, set\n\t// this field to NULL.\n\t//\n\t// The lifetime of the pointers returned by `cxxrtl_attr_*` family of functions is the same as\n\t// the lifetime of this structure.\n\tstruct _cxxrtl_attr_set *attrs;\n\n\t// More description fields may be added in the future, but the existing ones will never change.\n};\n\n// Retrieve description of a simulated object.\n//\n// The `name` is the full hierarchical name of the object in the Yosys notation, where public names\n// have a `\\` prefix and hierarchy levels are separated by single spaces. For example, if\n// the top-level module instantiates a module `foo`, which in turn contains a wire `bar`, the full\n// hierarchical name is `\\foo \\bar`.\n//\n// The storage of a single abstract object may be split (usually with the `splitnets` pass) into\n// many physical parts, all of which correspond to the same hierarchical name. To handle such cases,\n// this function returns an array and writes its length to `parts`. The array is sorted by `lsb_at`.\n//\n// Returns the object parts if it was found, NULL otherwise. The returned parts are valid until\n// the design is destroyed.\nstruct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, size_t *parts);\n\n// Retrieve description of a single part simulated object.\n//\n// This function is a shortcut for the most common use of `cxxrtl_get_parts`. It asserts that,\n// if the object exists, it consists of a single part. If assertions are disabled, it returns NULL\n// for multi-part objects.\nstatic inline struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) {\n\tsize_t parts = 0;\n\tstruct cxxrtl_object *object = cxxrtl_get_parts(handle, name, &parts);\n\tassert(object == NULL || parts == 1);\n\tif (object == NULL || parts == 1)\n\t\treturn object;\n\treturn NULL;\n}\n\n// Enumerate simulated objects.\n//\n// For every object in the simulation, `callback` is called with the provided `data`, the full\n// hierarchical name of the object (see `cxxrtl_get` for details), and the object parts.\n// The provided `name` and `object` values are valid until the design is destroyed.\nvoid cxxrtl_enum(cxxrtl_handle handle, void *data,\n void (*callback)(void *data, const char *name,\n struct cxxrtl_object *object, size_t parts));\n\n// Opaque reference to an outline.\n//\n// An outline is a group of outline objects that are evaluated simultaneously. The identity of\n// an outline can be compared to determine whether any two objects belong to the same outline.\ntypedef struct _cxxrtl_outline *cxxrtl_outline;\n\n// Evaluate an outline.\n//\n// After evaluating an outline, the bits of every outline object contained in it are consistent\n// with the current state of the netlist. In general, any further modification to the netlist\n// causes every outline object to become stale, after which the corresponding outline must be\n// re-evaluated, otherwise the bits read from that object are meaningless.\nvoid cxxrtl_outline_eval(cxxrtl_outline outline);\n\n// Opaque reference to an attribute set.\n//\n// An attribute set is a map between attribute names (always strings) and values (which may have\n// several different types). To find out the type of an attribute, use `cxxrtl_attr_type`, and\n// to retrieve the value of an attribute, use `cxxrtl_attr_as_string`.\ntypedef struct _cxxrtl_attr_set *cxxrtl_attr_set;\n\n// Type of an attribute.\nenum cxxrtl_attr_type {\n\t// Attribute is not present.\n\tCXXRTL_ATTR_NONE = 0,\n\n\t// Attribute has an unsigned integer value.\n\tCXXRTL_ATTR_UNSIGNED_INT = 1,\n\n\t// Attribute has an unsigned integer value.\n\tCXXRTL_ATTR_SIGNED_INT = 2,\n\n\t// Attribute has a string value.\n\tCXXRTL_ATTR_STRING = 3,\n\n\t// Attribute has a double precision floating point value.\n\tCXXRTL_ATTR_DOUBLE = 4,\n\n\t// More attribute types may be defined in the future, but the existing values will never change.\n};\n\n// Determine the presence and type of an attribute in an attribute set.\n//\n// This function returns one of the possible `cxxrtl_attr_type` values.\nint cxxrtl_attr_type(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve an unsigned integer valued attribute from an attribute set.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_UNSIGNED_INT`.\n// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type.\nuint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve a signed integer valued attribute from an attribute set.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_SIGNED_INT`.\n// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type.\nint64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve a string valued attribute from an attribute set. The returned string is zero-terminated.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_STRING`. If assertions\n// are disabled, returns NULL if the attribute is missing or has an incorrect type.\nconst char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve a double precision floating point valued attribute from an attribute set.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_DOUBLE`. If assertions\n// are disabled, returns NULL if the attribute is missing or has an incorrect type.\ndouble cxxrtl_attr_get_double(cxxrtl_attr_set attrs, const char *name);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n",
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"cxxrtl_capi.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_CAPI_H\n#define CXXRTL_CAPI_H\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.cc`.\n//\n// The CXXRTL C API makes it possible to drive CXXRTL designs using C or any other language that\n// supports the C ABI, for example, Python. It does not provide a way to implement black boxes.\n\n#include <stddef.h>\n#include <stdint.h>\n#include <assert.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// Opaque reference to a design toplevel.\n//\n// A design toplevel can only be used to create a design handle.\ntypedef struct _cxxrtl_toplevel *cxxrtl_toplevel;\n\n// The constructor for a design toplevel is provided as a part of generated code for that design.\n// Its prototype matches:\n//\n// cxxrtl_toplevel <design-name>_create();\n\n// Opaque reference to a design handle.\n//\n// A design handle is required by all operations in the C API.\ntypedef struct _cxxrtl_handle *cxxrtl_handle;\n\n// Create a design handle from a design toplevel.\n//\n// The `design` is consumed by this operation and cannot be used afterwards.\ncxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);\n\n// Create a design handle at a given hierarchy position from a design toplevel.\n//\n// This operation is similar to `cxxrtl_create`, except the full hierarchical name of every object\n// is prepended with `top_path`.\ncxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path);\n\n// Release all resources used by a design and its handle.\nvoid cxxrtl_destroy(cxxrtl_handle handle);\n\n// Reinitialize the design, replacing the internal state with the reset values while preserving\n// black boxes.\n//\n// This operation is essentially equivalent to a power-on reset. Values, wires, and memories are\n// returned to their reset state while preserving the state of black boxes and keeping all of\n// the interior pointers obtained with e.g. `cxxrtl_get` valid.\nvoid cxxrtl_reset(cxxrtl_handle handle);\n\n// Evaluate the design, propagating changes on inputs to the `next` value of internal state and\n// output wires.\n//\n// Returns 1 if the design is known to immediately converge, 0 otherwise.\nint cxxrtl_eval(cxxrtl_handle handle);\n\n// Commit the design, replacing the `curr` value of internal state and output wires with the `next`\n// value.\n//\n// Return 1 if any of the `curr` values were updated, 0 otherwise.\nint cxxrtl_commit(cxxrtl_handle handle);\n\n// Simulate the design to a fixed point.\n//\n// Returns the number of delta cycles.\nsize_t cxxrtl_step(cxxrtl_handle handle);\n\n// Type of a simulated object.\n//\n// The type of a simulated object indicates the way it is stored and the operations that are legal\n// to perform on it (i.e. won't crash the simulation). It says very little about object semantics,\n// which is specified through flags.\nenum cxxrtl_type {\n\t// Values correspond to singly buffered netlist nodes, i.e. nodes driven exclusively by\n\t// combinatorial cells, or toplevel input nodes.\n\t//\n\t// Values can be inspected via the `curr` pointer. If the `next` pointer is NULL, the value is\n\t// driven by a constant and can never be modified. Otherwise, the value can be modified through\n\t// the `next` pointer (which is equal to `curr` if not NULL). Note that changes to the bits\n\t// driven by combinatorial cells will be ignored.\n\t//\n\t// Values always have depth 1.\n\tCXXRTL_VALUE = 0,\n\n\t// Wires correspond to doubly buffered netlist nodes, i.e. nodes driven, at least in part, by\n\t// storage cells, or by combinatorial cells that are a part of a feedback path. They are also\n\t// present in non-optimized builds.\n\t//\n\t// Wires can be inspected via the `curr` pointer and modified via the `next` pointer (which are\n\t// distinct for wires). Note that changes to the bits driven by combinatorial cells will be\n\t// ignored.\n\t//\n\t// Wires always have depth 1.\n\tCXXRTL_WIRE = 1,\n\n\t// Memories correspond to memory cells.\n\t//\n\t// Memories can be inspected and modified via the `curr` pointer. Due to a limitation of this\n\t// API, memories cannot yet be modified in a guaranteed race-free way, and the `next` pointer is\n\t// always NULL.\n\tCXXRTL_MEMORY = 2,\n\n\t// Aliases correspond to netlist nodes driven by another node such that their value is always\n\t// exactly equal.\n\t//\n\t// Aliases can be inspected via the `curr` pointer. They cannot be modified, and the `next`\n\t// pointer is always NULL.\n\tCXXRTL_ALIAS = 3,\n\n\t// Outlines correspond to netlist nodes that were optimized in a way that makes them inaccessible\n\t// outside of a module's `eval()` function. At the highest debug information level, every inlined\n\t// node has a corresponding outline object.\n\t//\n\t// Outlines can be inspected via the `curr` pointer and can never be modified; the `next` pointer\n\t// is always NULL. Unlike all other objects, the bits of an outline object are meaningful only\n\t// after a call to `cxxrtl_outline_eval` and until any subsequent modification to the netlist.\n\t// Observing this requirement is the responsibility of the caller; it is not enforced.\n\t//\n\t// Outlines always correspond to combinatorial netlist nodes that are not ports.\n\tCXXRTL_OUTLINE = 4,\n\n\t// More object types may be added in the future, but the existing ones will never change.\n};\n\n// Flags of a simulated object.\n//\n// The flags of a simulated object indicate its role in the netlist:\n// * The flags `CXXRTL_INPUT` and `CXXRTL_OUTPUT` designate module ports.\n// * The flags `CXXRTL_DRIVEN_SYNC`, `CXXRTL_DRIVEN_COMB`, and `CXXRTL_UNDRIVEN` specify\n// the semantics of node state. An object with several of these flags set has different bits\n// follow different semantics.\nenum cxxrtl_flag {\n\t// Node is a module input port.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined\n\t// with `CXXRTL_OUTPUT`, as well as other flags.\n\tCXXRTL_INPUT = 1 << 0,\n\n\t// Node is a module output port.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with `CXXRTL_INPUT`,\n\t// as well as other flags.\n\tCXXRTL_OUTPUT = 1 << 1,\n\n\t// Node is a module inout port.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with other flags.\n\tCXXRTL_INOUT = (CXXRTL_INPUT|CXXRTL_OUTPUT),\n\n\t// Node has bits that are driven by a storage cell.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with\n\t// `CXXRTL_DRIVEN_COMB` and `CXXRTL_UNDRIVEN`, as well as other flags.\n\t//\n\t// This flag is set on wires that have bits connected directly to the output of a flip-flop or\n\t// a latch, and hold its state. Many `CXXRTL_WIRE` objects may not have the `CXXRTL_DRIVEN_SYNC`\n\t// flag set; for example, output ports and feedback wires generally won't. Writing to the `next`\n\t// pointer of these wires updates stored state, and for designs without combinatorial loops,\n\t// capturing the value from every of these wires through the `curr` pointer creates a complete\n\t// snapshot of the design state.\n\tCXXRTL_DRIVEN_SYNC = 1 << 2,\n\n\t// Node has bits that are driven by a combinatorial cell or another node.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_VALUE`, `CXXRTL_WIRE`, and `CXXRTL_OUTLINE`.\n\t// It may be combined with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_UNDRIVEN`, as well as other flags.\n\t//\n\t// This flag is set on objects that have bits connected to the output of a combinatorial cell,\n\t// or directly to another node. For designs without combinatorial loops, writing to such bits\n\t// through the `next` pointer (if it is not NULL) has no effect.\n\tCXXRTL_DRIVEN_COMB = 1 << 3,\n\n\t// Node has bits that are not driven.\n\t//\n\t// This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined\n\t// with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_DRIVEN_COMB`, as well as other flags.\n\t//\n\t// This flag is set on objects that have bits not driven by an output of any cell or by another\n\t// node, such as inputs and dangling wires.\n\tCXXRTL_UNDRIVEN = 1 << 4,\n\n\t// Generated correspond to netlist nodes that correspond to state with an internal name, that\n\t// need to be saved, but wouldn't otherwise have a debug item generated.\n\tCXXRTL_GENERATED = 1 << 5,\n\n\t// More object flags may be added in the future, but the existing ones will never change.\n};\n\n// Description of a simulated object.\n//\n// The `curr` and `next` arrays can be accessed directly to inspect and, if applicable, modify\n// the bits stored in the object.\nstruct cxxrtl_object {\n\t// Type of the object.\n\t//\n\t// All objects have the same memory layout determined by `width` and `depth`, but the type\n\t// determines all other properties of the object.\n\tuint32_t type; // actually `enum cxxrtl_type`\n\n\t// Flags of the object.\n\tuint32_t flags; // actually bit mask of `enum cxxrtl_flags`\n\n\t// Width of the object in bits.\n\tsize_t width;\n\n\t// Index of the least significant bit.\n\tsize_t lsb_at;\n\n\t// Depth of the object. Only meaningful for memories; for other objects, always 1.\n\tsize_t depth;\n\n\t// Index of the first word. Only meaningful for memories; for other objects, always 0;\n\tsize_t zero_at;\n\n\t// Bits stored in the object, as 32-bit chunks, least significant bits first.\n\t//\n\t// The width is rounded up to a multiple of 32; the padding bits are always set to 0 by\n\t// the simulation code, and must be always written as 0 when modified by user code.\n\t// In memories, every element is stored contiguously. Therefore, the total number of chunks\n\t// in any object is `((width + 31) / 32) * depth`.\n\t//\n\t// To allow the simulation to be partitioned into multiple independent units communicating\n\t// through wires, the bits are double buffered. To avoid race conditions, user code should\n\t// always read from `curr` and write to `next`. The `curr` pointer is always valid; for objects\n\t// that cannot be modified, or cannot be modified in a race-free way, `next` is NULL.\n\t//\n\t// In case where `width == 0`, `curr` is a non-NULL pointer unique for the wire. That is,\n\t// there is a 1-to-1 correspondence between simulation objects and `curr` pointers, regardless\n\t// of whether they have storage or not. (Aliases' `curr` pointer equals that of some other\n\t// simulated object.)\n\tuint32_t *curr;\n\tuint32_t *next;\n\n\t// Opaque reference to an outline. Only meaningful for outline objects.\n\t//\n\t// See the documentation of `cxxrtl_outline` for details. When creating a `cxxrtl_object`, set\n\t// this field to NULL.\n\tstruct _cxxrtl_outline *outline;\n\n\t// Opaque reference to an attribute set.\n\t//\n\t// See the documentation of `cxxrtl_attr_set` for details. When creating a `cxxrtl_object`, set\n\t// this field to NULL.\n\t//\n\t// The lifetime of the pointers returned by `cxxrtl_attr_*` family of functions is the same as\n\t// the lifetime of this structure.\n\tstruct _cxxrtl_attr_set *attrs;\n\n\t// More description fields may be added in the future, but the existing ones will never change.\n};\n\n// Retrieve description of a simulated object.\n//\n// The `name` is the full hierarchical name of the object in the Yosys notation, where public names\n// have a `\\` prefix and hierarchy levels are separated by single spaces. For example, if\n// the top-level module instantiates a module `foo`, which in turn contains a wire `bar`, the full\n// hierarchical name is `\\foo \\bar`.\n//\n// The storage of a single abstract object may be split (usually with the `splitnets` pass) into\n// many physical parts, all of which correspond to the same hierarchical name. To handle such cases,\n// this function returns an array and writes its length to `parts`. The array is sorted by `lsb_at`.\n//\n// Returns the object parts if it was found, NULL otherwise. The returned parts are valid until\n// the design is destroyed.\nstruct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, size_t *parts);\n\n// Retrieve description of a single part simulated object.\n//\n// This function is a shortcut for the most common use of `cxxrtl_get_parts`. It asserts that,\n// if the object exists, it consists of a single part. If assertions are disabled, it returns NULL\n// for multi-part objects.\nstatic inline struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) {\n\tsize_t parts = 0;\n\tstruct cxxrtl_object *object = cxxrtl_get_parts(handle, name, &parts);\n\tassert(object == NULL || parts == 1);\n\tif (object == NULL || parts == 1)\n\t\treturn object;\n\treturn NULL;\n}\n\n// Enumerate simulated objects.\n//\n// For every object in the simulation, `callback` is called with the provided `data`, the full\n// hierarchical name of the object (see `cxxrtl_get` for details), and the object parts.\n// The provided `name` and `object` values are valid until the design is destroyed.\nvoid cxxrtl_enum(cxxrtl_handle handle, void *data,\n void (*callback)(void *data, const char *name,\n struct cxxrtl_object *object, size_t parts));\n\n// Opaque reference to an outline.\n//\n// An outline is a group of outline objects that are evaluated simultaneously. The identity of\n// an outline can be compared to determine whether any two objects belong to the same outline.\ntypedef struct _cxxrtl_outline *cxxrtl_outline;\n\n// Evaluate an outline.\n//\n// After evaluating an outline, the bits of every outline object contained in it are consistent\n// with the current state of the netlist. In general, any further modification to the netlist\n// causes every outline object to become stale, after which the corresponding outline must be\n// re-evaluated, otherwise the bits read from that object are meaningless.\nvoid cxxrtl_outline_eval(cxxrtl_outline outline);\n\n// Opaque reference to an attribute set.\n//\n// An attribute set is a map between attribute names (always strings) and values (which may have\n// several different types). To find out the type of an attribute, use `cxxrtl_attr_type`, and\n// to retrieve the value of an attribute, use `cxxrtl_attr_as_string`.\ntypedef struct _cxxrtl_attr_set *cxxrtl_attr_set;\n\n// Type of an attribute.\nenum cxxrtl_attr_type {\n\t// Attribute is not present.\n\tCXXRTL_ATTR_NONE = 0,\n\n\t// Attribute has an unsigned integer value.\n\tCXXRTL_ATTR_UNSIGNED_INT = 1,\n\n\t// Attribute has an unsigned integer value.\n\tCXXRTL_ATTR_SIGNED_INT = 2,\n\n\t// Attribute has a string value.\n\tCXXRTL_ATTR_STRING = 3,\n\n\t// Attribute has a double precision floating point value.\n\tCXXRTL_ATTR_DOUBLE = 4,\n\n\t// More attribute types may be defined in the future, but the existing values will never change.\n};\n\n// Determine the presence and type of an attribute in an attribute set.\n//\n// This function returns one of the possible `cxxrtl_attr_type` values.\nint cxxrtl_attr_type(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve an unsigned integer valued attribute from an attribute set.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_UNSIGNED_INT`.\n// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type.\nuint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve a signed integer valued attribute from an attribute set.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_SIGNED_INT`.\n// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type.\nint64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve a string valued attribute from an attribute set. The returned string is zero-terminated.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_STRING`. If assertions\n// are disabled, returns NULL if the attribute is missing or has an incorrect type.\nconst char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs, const char *name);\n\n// Retrieve a double precision floating point valued attribute from an attribute set.\n//\n// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_DOUBLE`. If assertions\n// are disabled, returns NULL if the attribute is missing or has an incorrect type.\ndouble cxxrtl_attr_get_double(cxxrtl_attr_set attrs, const char *name);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n",
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"cxxrtl_capi_vcd.cc": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi_vcd.h`.\n\n#include <cxxrtl/capi/cxxrtl_capi_vcd.h>\n#include <cxxrtl/cxxrtl_vcd.h>\n\nextern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle);\n\nstruct _cxxrtl_vcd {\n\tcxxrtl::vcd_writer writer;\n\tbool flush = false;\n};\n\ncxxrtl_vcd cxxrtl_vcd_create() {\n\treturn new _cxxrtl_vcd;\n}\n\nvoid cxxrtl_vcd_destroy(cxxrtl_vcd vcd) {\n\tdelete vcd;\n}\n\nvoid cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit) {\n\tvcd->writer.timescale(number, unit);\n}\n\nvoid cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, cxxrtl_object *object) {\n\t// Note the copy. We don't know whether `object` came from a design (in which case it is\n\t// an instance of `debug_item`), or from user code (in which case it is an instance of\n\t// `cxxrtl_object`), so casting the pointer wouldn't be safe.\n\tvcd->writer.add(name, cxxrtl::debug_item(*object));\n}\n\nvoid cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle) {\n\tvcd->writer.add(cxxrtl_debug_items_from_handle(handle));\n}\n\nvoid cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tint (*filter)(void *data, const char *name,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t const cxxrtl_object *object)) {\n\tvcd->writer.add(cxxrtl_debug_items_from_handle(handle),\n\t\t[=](const std::string &name, const cxxrtl::debug_item &item) {\n\t\t\treturn filter(data, name.c_str(), static_cast<const cxxrtl_object*>(&item));\n\t\t});\n}\n\nvoid cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle) {\n\tvcd->writer.add_without_memories(cxxrtl_debug_items_from_handle(handle));\n}\n\nvoid cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time) {\n\tif (vcd->flush) {\n\t\tvcd->writer.buffer.clear();\n\t\tvcd->flush = false;\n\t}\n\tvcd->writer.sample(time);\n}\n\nvoid cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size) {\n\tif (vcd->flush) {\n\t\tvcd->writer.buffer.clear();\n\t\tvcd->flush = false;\n\t}\n\t*data = vcd->writer.buffer.c_str();\n\t*size = vcd->writer.buffer.size();\n\tvcd->flush = true;\n}\n",
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"cxxrtl_capi_vcd.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_CAPI_VCD_H\n#define CXXRTL_CAPI_VCD_H\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`.\n//\n// The CXXRTL C API for VCD writing makes it possible to insert virtual probes into designs and\n// dump waveforms to Value Change Dump files.\n\n#include <stddef.h>\n#include <stdint.h>\n\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// Opaque reference to a VCD writer.\ntypedef struct _cxxrtl_vcd *cxxrtl_vcd;\n\n// Create a VCD writer.\ncxxrtl_vcd cxxrtl_vcd_create();\n\n// Release all resources used by a VCD writer.\nvoid cxxrtl_vcd_destroy(cxxrtl_vcd vcd);\n\n// Set VCD timescale.\n//\n// The `number` must be 1, 10, or 100, and the `unit` must be one of `\"s\"`, `\"ms\"`, `\"us\"`, `\"ns\"`,\n// `\"ps\"`, or `\"fs\"`.\n//\n// Timescale can only be set before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit);\n\n// Schedule a specific CXXRTL object to be sampled.\n//\n// The `name` is a full hierarchical name as described for `cxxrtl_get`; it does not need to match\n// the original name of `object`, if any. The `object` must outlive the VCD writer, but there are\n// no other requirements; if desired, it can be provided by user code, rather than come from\n// a design.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, struct cxxrtl_object *object);\n\n// Schedule all CXXRTL objects in a simulation.\n//\n// The design `handle` must outlive the VCD writer.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle);\n\n// Schedule CXXRTL objects in a simulation that match a given predicate.\n//\n// For every object in the simulation, `filter` is called with the provided `data`, the full\n// hierarchical name of the object (see `cxxrtl_get` for details), and the object description.\n// The object will be sampled if the predicate returns a non-zero value.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,\n int (*filter)(void *data, const char *name,\n const struct cxxrtl_object *object));\n\n// Schedule all CXXRTL objects in a simulation except for memories.\n//\n// The design `handle` must outlive the VCD writer.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle);\n\n// Sample all scheduled objects.\n//\n// First, `time` is written to the internal buffer. Second, the values of every signal changed since\n// the previous call to `cxxrtl_vcd_sample` (all values if this is the first call) are written to\n// the internal buffer. The contents of the buffer can be retrieved with `cxxrtl_vcd_read`.\nvoid cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time);\n\n// Retrieve buffered VCD data.\n//\n// The pointer to the start of the next chunk of VCD data is assigned to `*data`, and the length\n// of that chunk is assigned to `*size`. The pointer to the data is valid until the next call to\n// `cxxrtl_vcd_sample` or `cxxrtl_vcd_read`. Once all of the buffered data has been retrieved,\n// this function will always return zero sized chunks.\nvoid cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n",
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"cxxrtl.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.\n//\n// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides\n// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass\n// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler\n// to unwrap the abstraction and generate efficient code.\n\n#ifndef CXXRTL_H\n#define CXXRTL_H\n\n#include <cstddef>\n#include <cstdint>\n#include <cstring>\n#include <cassert>\n#include <limits>\n#include <type_traits>\n#include <tuple>\n#include <vector>\n#include <map>\n#include <algorithm>\n#include <memory>\n#include <functional>\n#include <sstream>\n#include <iostream>\n\n// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifndef __has_attribute\n#\tdefine __has_attribute(x) 0\n#endif\n\n// CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.\n// It generates a lot of specialized template functions with relatively large bodies that, when inlined\n// into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.\n// Because of this, most of the CXXRTL runtime must be always inlined for best performance.\n#if __has_attribute(always_inline)\n#define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))\n#else\n#define CXXRTL_ALWAYS_INLINE inline\n#endif\n// Conversely, some functions in the generated code are extremely large yet very cold, with both of these\n// properties being extreme enough to confuse C++ compilers into spending pathological amounts of time\n// on a futile (the code becomes worse) attempt to optimize the least important parts of code.\n#if __has_attribute(optnone)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))\n#elif __has_attribute(optimize)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))\n#else\n#define CXXRTL_EXTREMELY_COLD\n#endif\n\n// CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior\n// of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at\n// most result in undefined simulation results).\n//\n// Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating\n// the simulation into another process that should survive violating RTL contracts.\n#ifndef CXXRTL_ASSERT\n#ifndef CXXRTL_NDEBUG\n#define CXXRTL_ASSERT(x) assert(x)\n#else\n#define CXXRTL_ASSERT(x)\n#endif\n#endif\n\nnamespace cxxrtl {\n\n// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size\n// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving\n// and introspecting the simulation in Python.\n//\n// It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on\n// narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.\n// However, (a) most of our operations do not change those bits in the first place because of invariants that are\n// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.\n// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be\n// clobbered results in simpler generated code.\ntypedef uint32_t chunk_t;\ntypedef uint64_t wide_chunk_t;\n\ntemplate<typename T>\nstruct chunk_traits {\n\tstatic_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,\n\t \"chunk type must be an unsigned integral type\");\n\tusing type = T;\n\tstatic constexpr size_t bits = std::numeric_limits<T>::digits;\n\tstatic constexpr T mask = std::numeric_limits<T>::max();\n};\n\ntemplate<class T>\nstruct expr_base;\n\ntemplate<size_t Bits>\nstruct value : public expr_base<value<Bits>> {\n\tstatic constexpr size_t bits = Bits;\n\n\tusing chunk = chunk_traits<chunk_t>;\n\tstatic constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask\n\t\t: chunk::mask >> (chunk::bits - (Bits % chunk::bits));\n\n\tstatic constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;\n\tchunk::type data[chunks] = {};\n\n\tvalue() = default;\n\ttemplate<typename... Init>\n\texplicit constexpr value(Init ...init) : data{init...} {}\n\n\tvalue(const value<Bits> &) = default;\n\tvalue<Bits> &operator=(const value<Bits> &) = default;\n\n\tvalue(value<Bits> &&) = default;\n\tvalue<Bits> &operator=(value<Bits> &&) = default;\n\n\t// A (no-op) helper that forces the cast to value<>.\n\tCXXRTL_ALWAYS_INLINE\n\tconst value<Bits> &val() const {\n\t\treturn *this;\n\t}\n\n\tstd::string str() const {\n\t\tstd::stringstream ss;\n\t\tss << *this;\n\t\treturn ss.str();\n\t}\n\n\t// Conversion operations.\n\t//\n\t// These functions ensure that a conversion is never out of range, and should be always used, if at all\n\t// possible, instead of direct manipulation of the `data` member. For very large types, .slice() and\n\t// .concat() can be used to split them into more manageable parts.\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"get<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"get<T>() requires T to be at least as wide as the value is\");\n\t\tIntegerT result = 0;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult |= IntegerT(data[n]) << (n * chunk::bits);\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tauto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();\n\t\tIntegerT result;\n\t\tmemcpy(&result, &unsigned_result, sizeof(IntegerT));\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"set<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"set<T>() requires the value to be at least as wide as T is\");\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tdata[n] = (value >> (n * chunk::bits)) & chunk::mask;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\ttypename std::make_unsigned<IntegerT>::type unsigned_value;\n\t\tmemcpy(&unsigned_value, &value, sizeof(IntegerT));\n\t\tset(unsigned_value);\n\t}\n\n\t// Operations with compile-time parameters.\n\t//\n\t// These operations are used to implement slicing, concatenation, and blitting.\n\t// The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);\n\t// the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> trunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"trunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < result.chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zext() const {\n\t\tstatic_assert(NewBits >= Bits, \"zext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> sext() const {\n\t\tstatic_assert(NewBits >= Bits, \"sext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tif (is_neg()) {\n\t\t\tresult.data[chunks - 1] |= ~msb_mask;\n\t\t\tfor (size_t n = chunks; n < result.chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rtrunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"rtrunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (Bits - NewBits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tif (shift_chunks + result.chunks < chunks) {\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);\n\t\t}\n\t\tfor (size_t n = result.chunks; n > 0; n--) {\n\t\t\tresult.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + n - 1] << (chunk::bits - shift_bits);\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rzext() const {\n\t\tstatic_assert(NewBits >= Bits, \"rzext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (NewBits - Bits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (shift_chunks + chunks < result.chunks)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\t// Bit blit operation, i.e. a partial read-modify-write.\n\ttemplate<size_t Stop, size_t Start>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits> blit(const value<Stop - Start + 1> &source) const {\n\t\tstatic_assert(Stop >= Start, \"blit() may not reverse bit order\");\n\t\tconstexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));\n\t\tconstexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0\n\t\t\t: (chunk::mask << (Stop % chunk::bits + 1));\n\t\tvalue<Bits> masked = *this;\n\t\tif (Start / chunk::bits == Stop / chunk::bits) {\n\t\t\tmasked.data[Start / chunk::bits] &= stop_mask | start_mask;\n\t\t} else {\n\t\t\tmasked.data[Start / chunk::bits] &= start_mask;\n\t\t\tfor (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)\n\t\t\t\tmasked.data[n] = 0;\n\t\t\tmasked.data[Stop / chunk::bits] &= stop_mask;\n\t\t}\n\t\tvalue<Bits> shifted = source\n\t\t\t.template rzext<Stop + 1>()\n\t\t\t.template zext<Bits>();\n\t\treturn masked.bit_or(shifted);\n\t}\n\n\t// Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower\n\t// than the operand. In C++17 these can be replaced with `if constexpr`.\n\ttemplate<size_t NewBits, typename = void>\n\tstruct zext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template zext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits, typename = void>\n\tstruct sext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template sext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zcast() const {\n\t\treturn zext_cast<NewBits>()(*this);\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> scast() const {\n\t\treturn sext_cast<NewBits>()(*this);\n\t}\n\n\t// Bit replication is far more efficient than the equivalent concatenation.\n\ttemplate<size_t Count>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits * Count> repeat() const {\n\t\tstatic_assert(Bits == 1, \"repeat() is implemented only for 1-bit values\");\n\t\treturn *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();\n\t}\n\n\t// Operations with run-time parameters (offsets, amounts, etc).\n\t//\n\t// These operations are used for computations.\n\tbool bit(size_t offset) const {\n\t\treturn data[offset / chunk::bits] & (1 << (offset % chunk::bits));\n\t}\n\n\tvoid set_bit(size_t offset, bool value = true) {\n\t\tsize_t offset_chunks = offset / chunk::bits;\n\t\tsize_t offset_bits = offset % chunk::bits;\n\t\tdata[offset_chunks] &= ~(1 << offset_bits);\n\t\tdata[offset_chunks] |= value ? 1 << offset_bits : 0;\n\t}\n\n\texplicit operator bool() const {\n\t\treturn !is_zero();\n\t}\n\n\tbool is_zero() const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool is_neg() const {\n\t\treturn data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));\n\t}\n\n\tbool operator ==(const value<Bits> &other) const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != other.data[n])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator !=(const value<Bits> &other) const {\n\t\treturn !(*this == other);\n\t}\n\n\tvalue<Bits> bit_not() const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = ~data[n];\n\t\tresult.data[chunks - 1] &= msb_mask;\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_and(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] & other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_or(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] | other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_xor(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] ^ other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {\n\t\treturn bit_and(mask.bit_not()).bit_or(val.bit_and(mask));\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> shl(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shl() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn {};\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn {};\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits, bool Signed = false>\n\tvalue<Bits> shr(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shr() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Signed && is_neg()) {\n\t\t\tsize_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;\n\t\t\tsize_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;\n\t\t\tfor (size_t n = top_chunk_idx + 1; n < chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tif (amount.data[0] != 0)\n\t\t\t\tresult.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> sshr(const value<AmountBits> &amount) const {\n\t\treturn shr<AmountBits, /*Signed=*/true>(amount);\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> bmux(const value<SelBits> &sel) const {\n\t\tstatic_assert(ResultBits << SelBits == Bits, \"invalid sizes used in bmux()\");\n\t\tsize_t amount = sel.data[0] * ResultBits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tif (ResultBits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tcarry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> demux(const value<SelBits> &sel) const {\n\t\tstatic_assert(Bits << SelBits == ResultBits, \"invalid sizes used in demux()\");\n\t\tsize_t amount = sel.data[0] * Bits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Bits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\tsize_t ctpop() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\t// This loop implements the population count idiom as recognized by LLVM and GCC.\n\t\t\tfor (chunk::type x = data[n]; x != 0; count++)\n\t\t\t\tx = x & (x - 1);\n\t\t}\n\t\treturn count;\n\t}\n\n\tsize_t ctlz() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tchunk::type x = data[chunks - 1 - n];\n\t\t\t// First add to `count` as if the chunk is zero\n\t\t\tconstexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;\n\t\t\tcount += (n == 0 ? msb_chunk_bits : chunk::bits);\n\t\t\t// If the chunk isn't zero, correct the `count` value and return\n\t\t\tif (x != 0) {\n\t\t\t\tfor (; x != 0; count--)\n\t\t\t\t\tx >>= 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\treturn count;\n\t}\n\n\ttemplate<bool Invert, bool CarryIn>\n\tstd::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry = CarryIn;\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;\n\t\t\tif (result.chunks - 1 == n)\n\t\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t\tcarry = (result.data[n] < data[n]) ||\n\t\t\t (result.data[n] == data[n] && carry);\n\t\t}\n\t\treturn {result, carry};\n\t}\n\n\tvalue<Bits> add(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/false, /*CarryIn=*/false>(other).first;\n\t}\n\n\tvalue<Bits> sub(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/true, /*CarryIn=*/true>(other).first;\n\t}\n\n\tvalue<Bits> neg() const {\n\t\treturn value<Bits>().sub(*this);\n\t}\n\n\tbool ucmp(const value<Bits> &other) const {\n\t\tbool carry;\n\t\tstd::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\treturn !carry; // a.ucmp(b) ≡ a u< b\n\t}\n\n\tbool scmp(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry;\n\t\tstd::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\tbool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());\n\t\treturn result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b\n\t}\n\n\ttemplate<size_t ResultBits>\n\tvalue<ResultBits> mul(const value<Bits> &other) const {\n\t\tvalue<ResultBits> result;\n\t\twide_chunk_t wide_result[result.chunks + 1] = {};\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tfor (size_t m = 0; m < chunks && n + m < result.chunks; m++) {\n\t\t\t\twide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);\n\t\t\t\twide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;\n\t\t\t\twide_result[n + m] &= chunk::mask;\n\t\t\t}\n\t\t}\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = wide_result[n];\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {\n\t\tvalue<Bits> quotient;\n\t\tvalue<Bits> dividend = *this;\n\t\tif (dividend.ucmp(divisor))\n\t\t\treturn {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};\n\t\tint64_t divisor_shift = divisor.ctlz() - dividend.ctlz();\n\t\tassert(divisor_shift >= 0);\n\t\tdivisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});\n\t\tfor (size_t step = 0; step <= divisor_shift; step++) {\n\t\t\tquotient = quotient.shl(value<Bits>{1u});\n\t\t\tif (!dividend.ucmp(divisor)) {\n\t\t\t\tdividend = dividend.sub(divisor);\n\t\t\t\tquotient.set_bit(0, true);\n\t\t\t}\n\t\t\tdivisor = divisor.shr(value<Bits>{1u});\n\t\t}\n\t\treturn {quotient, /*remainder=*/dividend};\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {\n\t\tvalue<Bits + 1> quotient;\n\t\tvalue<Bits + 1> remainder;\n\t\tvalue<Bits + 1> dividend = sext<Bits + 1>();\n\t\tvalue<Bits + 1> divisor = other.template sext<Bits + 1>();\n\t\tif (is_neg()) dividend = dividend.neg();\n\t\tif (other.is_neg()) divisor = divisor.neg();\n\t\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\t\tif (is_neg() != other.is_neg()) quotient = quotient.neg();\n\t\tif (is_neg()) remainder = remainder.neg();\n\t\treturn {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};\n\t}\n};\n\n// Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, size_t Stop, size_t Start>\nstruct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {\n\tstatic_assert(Stop >= Start, \"slice_expr() may not reverse bit order\");\n\tstatic_assert(Start < T::bits && Stop < T::bits, \"slice_expr() must be within bounds\");\n\tstatic constexpr size_t bits = Stop - Start + 1;\n\n\tT &expr;\n\n\tslice_expr(T &expr) : expr(expr) {}\n\tslice_expr(const slice_expr<T, Stop, Start> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\treturn static_cast<const value<T::bits> &>(expr)\n\t\t\t.template rtrunc<T::bits - Start>()\n\t\t\t.template trunc<bits>();\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {\n\t\t// Generic partial assignment implemented using a read-modify-write operation on the sliced expression.\n\t\texpr = static_cast<const value<T::bits> &>(expr)\n\t\t\t.template blit<Stop, Start>(rhs);\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, class U>\nstruct concat_expr : public expr_base<concat_expr<T, U>> {\n\tstatic constexpr size_t bits = T::bits + U::bits;\n\n\tT &ms_expr;\n\tU &ls_expr;\n\n\tconcat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}\n\tconcat_expr(const concat_expr<T, U> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\tvalue<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)\n\t\t\t.template rzext<bits>();\n\t\tvalue<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)\n\t\t\t.template zext<bits>();\n\t\treturn ms_shifted.bit_or(ls_extended);\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, U> &operator=(const value<bits> &rhs) {\n\t\tms_expr = rhs.template rtrunc<T::bits>();\n\t\tls_expr = rhs.template trunc<U::bits>();\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.\n//\n// Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because\n// they refer to temporaries that will, in general, only live until the end of the statement. For example, both of\n// these snippets perform use-after-free:\n//\n// const auto &a = val.slice<7,0>().slice<1>();\n// value<1> b = a;\n//\n// auto &&c = val.slice<7,0>().slice<1>();\n// c = value<1>{1u};\n//\n// An easy way to write code using slices and concatenations safely is to follow two simple rules:\n// * Never explicitly name any type except `value<W>` or `const value<W> &`.\n// * Never use a `const auto &` or `auto &&` in any such expression.\n// Then, any code that compiles will be well-defined.\ntemplate<class T>\nstruct expr_base {\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<const T, Stop, Start> slice() const {\n\t\treturn {*static_cast<const T *>(this)};\n\t}\n\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> slice() {\n\t\treturn {*static_cast<T *>(this)};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {\n\t\treturn {*static_cast<const T *>(this), other};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {\n\t\treturn {*static_cast<T *>(this), other};\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const value<Bits> &val) {\n\tauto old_flags = os.flags(std::ios::right);\n\tauto old_width = os.width(0);\n\tauto old_fill = os.fill('0');\n\tos << val.bits << '\\'' << std::hex;\n\tfor (size_t n = val.chunks - 1; n != (size_t)-1; n--) {\n\t\tif (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)\n\t\t\tos.width((Bits % value<Bits>::chunk::bits + 3) / 4);\n\t\telse\n\t\t\tos.width((value<Bits>::chunk::bits + 3) / 4);\n\t\tos << val.data[n];\n\t}\n\tos.fill(old_fill);\n\tos.width(old_width);\n\tos.flags(old_flags);\n\treturn os;\n}\n\ntemplate<size_t Bits>\nstruct wire {\n\tstatic constexpr size_t bits = Bits;\n\n\tvalue<Bits> curr;\n\tvalue<Bits> next;\n\n\twire() = default;\n\texplicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}\n\ttemplate<typename... Init>\n\texplicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}\n\n\t// Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,\n\t// e.g. because a module is built with a different optimization level, then existing code could\n\t// unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure\n\t// this doesn't happen, prohibit copying and copy-assigning wires.\n\twire(const wire<Bits> &) = delete;\n\twire<Bits> &operator=(const wire<Bits> &) = delete;\n\n\twire(wire<Bits> &&) = default;\n\twire<Bits> &operator=(wire<Bits> &&) = default;\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\treturn curr.template get<IntegerT>();\n\t}\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT other) {\n\t\tnext.template set<IntegerT>(other);\n\t}\n\n\t// This method intentionally takes a mandatory argument (to make it more difficult to misuse in\n\t// black box implementations, leading to missed observer events). It is generic over its argument\n\t// to allow the `on_update` method to be non-virtual.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tif (curr != next) {\n\t\t\tobserver.on_update(curr.chunks, curr.data, next.data);\n\t\t\tcurr = next;\n\t\t\treturn true;\n\t\t}\n\t\treturn false;\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {\n\tos << val.curr;\n\treturn os;\n}\n\ntemplate<size_t Width>\nstruct memory {\n\tconst size_t depth;\n\tstd::unique_ptr<value<Width>[]> data;\n\n\texplicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}\n\n\tmemory(const memory<Width> &) = delete;\n\tmemory<Width> &operator=(const memory<Width> &) = delete;\n\n\tmemory(memory<Width> &&) = default;\n\tmemory<Width> &operator=(memory<Width> &&other) {\n\t\tassert(depth == other.depth);\n\t\tdata = std::move(other.data);\n\t\twrite_queue = std::move(other.write_queue);\n\t\treturn *this;\n\t}\n\n\t// An operator for direct memory reads. May be used at any time during the simulation.\n\tconst value<Width> &operator [](size_t index) const {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// An operator for direct memory writes. May only be used before the simulation is started. If used\n\t// after the simulation is started, the design may malfunction.\n\tvalue<Width> &operator [](size_t index) {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// A simple way to make a writable memory would be to use an array of wires instead of an array of values.\n\t// However, there are two significant downsides to this approach: first, it has large overhead (2× space\n\t// overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port\n\t// priorities. Although in principle write ports could be ordered or conditionally enabled in generated\n\t// code based on their priorities and selected addresses, the feedback arc set problem is computationally\n\t// expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)\n\t// a particular write port evaluation order.\n\t//\n\t// The approach used here instead is to queue writes into a buffer during the eval phase, then perform\n\t// the writes during the commit phase in the priority order. This approach has low overhead, with both space\n\t// and time proportional to the amount of write ports. Because virtually every memory in a practical design\n\t// has at most two write ports, linear search is used on every write, being the fastest and simplest approach.\n\tstruct write {\n\t\tsize_t index;\n\t\tvalue<Width> val;\n\t\tvalue<Width> mask;\n\t\tint priority;\n\t};\n\tstd::vector<write> write_queue;\n\n\tvoid update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {\n\t\tassert(index < depth);\n\t\t// Queue up the write while keeping the queue sorted by priority.\n\t\twrite_queue.insert(\n\t\t\tstd::upper_bound(write_queue.begin(), write_queue.end(), priority,\n\t\t\t\t[](const int a, const write& b) { return a < b.priority; }),\n\t\t\twrite { index, val, mask, priority });\n\t}\n\n\t// See the note for `wire::commit()`.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tbool changed = false;\n\t\tfor (const write &entry : write_queue) {\n\t\t\tvalue<Width> elem = data[entry.index];\n\t\t\telem = elem.update(entry.val, entry.mask);\n\t\t\tif (data[entry.index] != elem) {\n\t\t\t\tobserver.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);\n\t\t\t\tchanged |= true;\n\t\t\t}\n\t\t\tdata[entry.index] = elem;\n\t\t}\n\t\twrite_queue.clear();\n\t\treturn changed;\n\t}\n};\n\nstruct metadata {\n\tconst enum {\n\t\tMISSING = 0,\n\t\tUINT \t= 1,\n\t\tSINT \t= 2,\n\t\tSTRING \t= 3,\n\t\tDOUBLE \t= 4,\n\t} value_type;\n\n\t// In debug mode, using the wrong .as_*() function will assert.\n\t// In release mode, using the wrong .as_*() function will safely return a default value.\n\tconst uint64_t uint_value = 0;\n\tconst int64_t sint_value = 0;\n\tconst std::string string_value = \"\";\n\tconst double double_value = 0.0;\n\n\tmetadata() : value_type(MISSING) {}\n\tmetadata(uint64_t value) : value_type(UINT), uint_value(value) {}\n\tmetadata(int64_t value) : value_type(SINT), sint_value(value) {}\n\tmetadata(const std::string &value) : value_type(STRING), string_value(value) {}\n\tmetadata(const char *value) : value_type(STRING), string_value(value) {}\n\tmetadata(double value) : value_type(DOUBLE), double_value(value) {}\n\n\tmetadata(const metadata &) = default;\n\tmetadata &operator=(const metadata &) = delete;\n\n\tuint64_t as_uint() const {\n\t\tassert(value_type == UINT);\n\t\treturn uint_value;\n\t}\n\n\tint64_t as_sint() const {\n\t\tassert(value_type == SINT);\n\t\treturn sint_value;\n\t}\n\n\tconst std::string &as_string() const {\n\t\tassert(value_type == STRING);\n\t\treturn string_value;\n\t}\n\n\tdouble as_double() const {\n\t\tassert(value_type == DOUBLE);\n\t\treturn double_value;\n\t}\n\n\t// Internal CXXRTL use only.\n\tstatic std::map<std::string, metadata> deserialize(const char *ptr) {\n\t\tstd::map<std::string, metadata> result;\n\t\tstd::string name;\n\t\t// Grammar:\n\t\t// string ::= [^\\0]+ \\0\n\t\t// metadata ::= [uid] .{8} | s <string>\n\t\t// map ::= ( <string> <metadata> )* \\0\n\t\tfor (;;) {\n\t\t\tif (*ptr) {\n\t\t\t\tname += *ptr++;\n\t\t\t} else if (!name.empty()) {\n\t\t\t\tptr++;\n\t\t\t\tauto get_u64 = [&]() {\n\t\t\t\t\tuint64_t result = 0;\n\t\t\t\t\tfor (size_t count = 0; count < 8; count++)\n\t\t\t\t\t\tresult = (result << 8) | *ptr++;\n\t\t\t\t\treturn result;\n\t\t\t\t};\n\t\t\t\tchar type = *ptr++;\n\t\t\t\tif (type == 'u') {\n\t\t\t\t\tuint64_t value = get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'i') {\n\t\t\t\t\tint64_t value = (int64_t)get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'd') {\n\t\t\t\t\tdouble dvalue;\n\t\t\t\t\tuint64_t uvalue = get_u64();\n\t\t\t\t\tstatic_assert(sizeof(dvalue) == sizeof(uvalue), \"double must be 64 bits in size\");\n\t\t\t\t\tmemcpy(&dvalue, &uvalue, sizeof(dvalue));\n\t\t\t\t\tresult.emplace(name, dvalue);\n\t\t\t\t} else if (type == 's') {\n\t\t\t\t\tstd::string value;\n\t\t\t\t\twhile (*ptr)\n\t\t\t\t\t\tvalue += *ptr++;\n\t\t\t\t\tptr++;\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else {\n\t\t\t\t\tassert(false && \"Unknown type specifier\");\n\t\t\t\t\treturn result;\n\t\t\t\t}\n\t\t\t\tname.clear();\n\t\t\t} else {\n\t\t\t\treturn result;\n\t\t\t}\n\t\t}\n\t}\n};\n\ntypedef std::map<std::string, metadata> metadata_map;\n\nstruct performer;\n\n// An object that allows formatting a string lazily.\nstruct lazy_fmt {\n\tvirtual std::string operator() () const = 0;\n};\n\n// Flavor of a `$check` cell.\nenum class flavor {\n\t// Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement.\n\tASSERT,\n\t// Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement.\n\tASSUME,\n\t// Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement.\n\tASSERT_EVENTUALLY,\n\t// Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement.\n\tASSUME_EVENTUALLY,\n\t// Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement.\n\tCOVER,\n};\n\n// An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented\n// below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not\n// taken into account.\nstruct performer {\n\t// Called by generated formatting code to evaluate a Verilog `$time` expression.\n\tvirtual int64_t vlog_time() const { return 0; }\n\n\t// Called by generated formatting code to evaluate a Verilog `$realtime` expression.\n\tvirtual double vlog_realtime() const { return vlog_time(); }\n\n\t// Called when a `$print` cell is triggered.\n\tvirtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tstd::cout << formatter();\n\t}\n\n\t// Called when a `$check` cell is triggered.\n\tvirtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tif (type == flavor::ASSERT || type == flavor::ASSUME) {\n\t\t\tif (!condition)\n\t\t\t\tstd::cerr << formatter();\n\t\t\tCXXRTL_ASSERT(condition && \"Check failed\");\n\t\t}\n\t}\n};\n\n// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in\n// the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and\n// a comparatively heavyweight template-based solution is justified.\nstruct observer {\n\t// Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks\n\t// at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and\n\t// `base` points to the first chunk.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}\n\n\t// Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`\n\t// with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to\n\t// the memory element chunk count and `base` points to the first chunk of the first element of the memory.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}\n};\n\n// Must be kept in sync with `struct FmtPart` in kernel/fmt.h!\n// Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.\nstruct fmt_part {\n\tenum {\n\t\tLITERAL = 0,\n\t\tINTEGER = 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\t// + value<Bits> val;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify; // = RIGHT;\n\tchar padding; // = '\\0';\n\tsize_t width; // = 0;\n\n\t// INTEGER type\n\tunsigned base; // = 10;\n\tbool signed_; // = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign; // = MINUS;\n\tbool hex_upper; // = false;\n\tbool show_base; // = false;\n\tbool group; // = false;\n\n\t// VLOG_TIME type\n\tbool realtime; // = false;\n\t// + int64_t itime;\n\t// + double ftime;\n\n\t// Format the part as a string.\n\t//\n\t// The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.\n\ttemplate<size_t Bits>\n\tstd::string render(value<Bits> val, performer *performer = nullptr)\n\t{\n\t\t// We might want to replace some of these bit() calls with direct\n\t\t// chunk access if it turns out to be slow enough to matter.\n\t\tstd::string buf;\n\t\tstd::string prefix;\n\t\tswitch (type) {\n\t\t\tcase LITERAL:\n\t\t\t\treturn str;\n\n\t\t\tcase STRING: {\n\t\t\t\tbuf.reserve(Bits/8);\n\t\t\t\tfor (int i = 0; i < Bits; i += 8) {\n\t\t\t\t\tchar ch = 0;\n\t\t\t\t\tfor (int j = 0; j < 8 && i + j < int(Bits); j++)\n\t\t\t\t\t\tif (val.bit(i + j))\n\t\t\t\t\t\t\tch |= 1 << j;\n\t\t\t\t\tif (ch != 0)\n\t\t\t\t\t\tbuf.append({ch});\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase UNICHAR: {\n\t\t\t\tuint32_t codepoint = val.template zcast<32>().template get<uint32_t>();\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0xf0 | (codepoint >> 18));\n\t\t\t\telse if (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0xe0 | (codepoint >> 12));\n\t\t\t\telse if (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0xc0 | (codepoint >> 6));\n\t\t\t\telse\n\t\t\t\t\tbuf += (char)codepoint;\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 12) & 0x3f));\n\t\t\t\tif (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 6) & 0x3f));\n\t\t\t\tif (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 0) & 0x3f));\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase INTEGER: {\n\t\t\t\tbool negative = signed_ && val.is_neg();\n\t\t\t\tif (negative) {\n\t\t\t\t\tprefix = \"-\";\n\t\t\t\t\tval = val.neg();\n\t\t\t\t} else {\n\t\t\t\t\tswitch (sign) {\n\t\t\t\t\t\tcase MINUS: break;\n\t\t\t\t\t\tcase PLUS_MINUS: prefix = \"+\"; break;\n\t\t\t\t\t\tcase SPACE_MINUS: prefix = \" \"; break;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tsize_t val_width = Bits;\n\t\t\t\tif (base != 10) {\n\t\t\t\t\tval_width = 1;\n\t\t\t\t\tfor (size_t index = 0; index < Bits; index++)\n\t\t\t\t\t\tif (val.bit(index))\n\t\t\t\t\t\t\tval_width = index + 1;\n\t\t\t\t}\n\n\t\t\t\tif (base == 2) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0b\";\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index++) {\n\t\t\t\t\t\tif (group && index > 0 && index % 4 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += (val.bit(index) ? '1' : '0');\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 8 || base == 16) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += (base == 16) ? (hex_upper ? \"0X\" : \"0x\") : \"0o\";\n\t\t\t\t\tsize_t step = (base == 16) ? 4 : 3;\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index += step) {\n\t\t\t\t\t\tif (group && index > 0 && index % (4 * step) == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tuint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);\n\t\t\t\t\t\tif (step == 4)\n\t\t\t\t\t\t\tvalue |= val.bit(index + 3) << 3;\n\t\t\t\t\t\tbuf += (hex_upper ? \"0123456789ABCDEF\" : \"0123456789abcdef\")[value];\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 10) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0d\";\n\t\t\t\t\tif (val.is_zero())\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();\n\t\t\t\t\tsize_t index = 0;\n\t\t\t\t\twhile (!xval.is_zero()) {\n\t\t\t\t\t\tif (group && index > 0 && index % 3 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> quotient, remainder;\n\t\t\t\t\t\tif (Bits >= 4)\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);\n\t\t\t\t\t\tbuf += '0' + remainder.template trunc<4>().template get<uint8_t>();\n\t\t\t\t\t\txval = quotient;\n\t\t\t\t\t\tindex++;\n\t\t\t\t\t}\n\t\t\t\t} else assert(false && \"Unsupported base for fmt_part\");\n\t\t\t\tif (justify == NUMERIC && group && padding == '0') {\n\t\t\t\t\tint group_size = base == 10 ? 3 : 4;\n\t\t\t\t\twhile (prefix.size() + buf.size() < width) {\n\t\t\t\t\t\tif (buf.size() % (group_size + 1) == group_size)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase VLOG_TIME: {\n\t\t\t\tif (performer) {\n\t\t\t\t\tbuf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());\n\t\t\t\t} else {\n\t\t\t\t\tbuf = realtime ? std::to_string(0.0) : std::to_string(0);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tstd::string str;\n\t\tassert(width == 0 || padding != '\\0');\n\t\tif (prefix.size() + buf.size() < width) {\n\t\t\tsize_t pad_width = width - prefix.size() - buf.size();\n\t\t\tswitch (justify) {\n\t\t\t\tcase LEFT:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tbreak;\n\t\t\t\tcase RIGHT:\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\tcase NUMERIC:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t} else {\n\t\t\tstr += prefix;\n\t\t\tstr += buf;\n\t\t}\n\t\treturn str;\n\t}\n};\n\n// Tag class to disambiguate values/wires and their aliases.\nstruct debug_alias {};\n\n// Tag declaration to disambiguate values and debug outlines.\nusing debug_outline = ::_cxxrtl_outline;\n\n// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.\n// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.\n//\n// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used\n// in the C API, or it would not be possible to cast between the pointers to these.\n//\n// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created\n// from external C code.\nstruct debug_item : ::cxxrtl_object {\n\t// Object types.\n\tenum : uint32_t {\n\t\tVALUE = CXXRTL_VALUE,\n\t\tWIRE = CXXRTL_WIRE,\n\t\tMEMORY = CXXRTL_MEMORY,\n\t\tALIAS = CXXRTL_ALIAS,\n\t\tOUTLINE = CXXRTL_OUTLINE,\n\t};\n\n\t// Object flags.\n\tenum : uint32_t {\n\t\tINPUT = CXXRTL_INPUT,\n\t\tOUTPUT = CXXRTL_OUTPUT,\n\t\tINOUT = CXXRTL_INOUT,\n\t\tDRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,\n\t\tDRIVEN_COMB = CXXRTL_DRIVEN_COMB,\n\t\tUNDRIVEN = CXXRTL_UNDRIVEN,\n\t};\n\n\tdebug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}\n\n\ttemplate<size_t Bits>\n\tdebug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.data;\n\t\tnext = item.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = WIRE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.curr.data;\n\t\tnext = item.next.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Width>\n\tdebug_item(memory<Width> &item, size_t zero_offset = 0) {\n\t\tstatic_assert(Width == 0 || sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),\n\t\t \"memory<Width> is not compatible with C layout\");\n\t\ttype = MEMORY;\n\t\tflags = 0;\n\t\twidth = Width;\n\t\tlsb_at = 0;\n\t\tdepth = item.depth;\n\t\tzero_at = zero_offset;\n\t\tcurr = item.data ? item.data[0].data : nullptr;\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.curr.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = OUTLINE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = &group;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tIntegerT get() const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\tstd::copy(curr, curr + value<Bits>::chunks, item.data);\n\t\treturn item.template get<IntegerT>();\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tvoid set(IntegerT other) const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\titem.template set<IntegerT>(other);\n\t\tstd::copy(item.data, item.data + value<Bits>::chunks, next);\n\t}\n};\nstatic_assert(std::is_standard_layout<debug_item>::value, \"debug_item is not compatible with C layout\");\n\n} // namespace cxxrtl\n\ntypedef struct _cxxrtl_attr_set {\n\tcxxrtl::metadata_map map;\n} *cxxrtl_attr_set;\n\nnamespace cxxrtl {\n\n// Representation of an attribute set in the C++ interface.\nusing debug_attrs = ::_cxxrtl_attr_set;\n\nstruct debug_items {\n\t// Debug items may be composed of multiple parts, but the attributes are shared between all of them.\n\t// There are additional invariants, not all of which are not checked by this code:\n\t// - Memories and non-memories cannot be mixed together.\n\t// - Bit indices (considering `lsb_at` and `width`) must not overlap.\n\t// - Row indices (considering `depth` and `zero_at`) must be the same.\n\t// - The `INPUT` and `OUTPUT` flags must be the same for all parts.\n\t// Other than that, the parts can be quite different, e.g. it is OK to mix a value, a wire, an alias,\n\t// and an outline, in the debug information for a single name in four parts.\n\tstd::map<std::string, std::vector<debug_item>> table;\n\tstd::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;\n\n\tvoid add(const std::string &path, debug_item &&item, metadata_map &&item_attrs = {}) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tstd::unique_ptr<debug_attrs> &attrs = attrs_table[path];\n\t\tif (attrs.get() == nullptr)\n\t\t\tattrs = std::unique_ptr<debug_attrs>(new debug_attrs);\n\t\tfor (auto attr : item_attrs)\n\t\t\tattrs->map.insert(attr);\n\t\titem.attrs = attrs.get();\n\t\tstd::vector<debug_item> &parts = table[path];\n\t\tparts.emplace_back(item);\n\t\tstd::sort(parts.begin(), parts.end(),\n\t\t\t[](const debug_item &a, const debug_item &b) {\n\t\t\t\treturn a.lsb_at < b.lsb_at;\n\t\t\t});\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\ttemplate<class... T>\n\tvoid add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {\n\t\tadd(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));\n\t}\n\n\tsize_t count(const std::string &path) const {\n\t\tif (table.count(path) == 0)\n\t\t\treturn 0;\n\t\treturn table.at(path).size();\n\t}\n\n\tconst std::vector<debug_item> &at(const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n\n\t// Like `at()`, but operates only on single-part debug items.\n\tconst debug_item &operator [](const std::string &path) const {\n\t\tconst std::vector<debug_item> &parts = table.at(path);\n\t\tassert(parts.size() == 1);\n\t\treturn parts.at(0);\n\t}\n\n\tbool is_memory(const std::string &path) const {\n\t\treturn at(path).at(0).type == debug_item::MEMORY;\n\t}\n\n\tconst metadata_map &attrs(const std::string &path) const {\n\t\treturn attrs_table.at(path)->map;\n\t}\n};\n\n// Only `module` scopes are defined. The type is implicit, since Yosys does not currently support\n// any other scope types.\nstruct debug_scope {\n\tstd::string module_name;\n\tstd::unique_ptr<debug_attrs> module_attrs;\n\tstd::unique_ptr<debug_attrs> cell_attrs;\n};\n\nstruct debug_scopes {\n\tstd::map<std::string, debug_scope> table;\n\n\tvoid add(const std::string &path, const std::string &module_name, metadata_map &&module_attrs, metadata_map &&cell_attrs) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tassert(table.count(path) == 0);\n\t\tdebug_scope &scope = table[path];\n\t\tscope.module_name = module_name;\n\t\tscope.module_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { module_attrs });\n\t\tscope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\tvoid add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {\n\t\tadd(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));\n\t}\n\n\tsize_t contains(const std::string &path) const {\n\t\treturn table.count(path);\n\t}\n\n\tconst debug_scope &operator [](const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n};\n\n// Tag class to disambiguate the default constructor used by the toplevel module that calls `reset()`,\n// and the constructor of interior modules that should not call it.\nstruct interior {};\n\n// The core API of the `module` class consists of only four virtual methods: `reset()`, `eval()`,\n// `commit`, and `debug_info()`. (The virtual destructor is made necessary by C++.) Every other method\n// is a convenience method, and exists solely to simplify some common pattern for C++ API consumers.\n// No behavior may be added to such convenience methods that other parts of CXXRTL can rely on, since\n// there is no guarantee they will be called (and, for example, other CXXRTL libraries will often call\n// the `eval()` and `commit()` directly instead, as well as being exposed in the C API).\nstruct module {\n\tmodule() {}\n\tvirtual ~module() {}\n\n\t// Modules with black boxes cannot be copied. Although not all designs include black boxes,\n\t// delete the copy constructor and copy assignment operator to make sure that any downstream\n\t// code that manipulates modules doesn't accidentally depend on their availability.\n\tmodule(const module &) = delete;\n\tmodule &operator=(const module &) = delete;\n\n\tmodule(module &&) = default;\n\tmodule &operator=(module &&) = default;\n\n\tvirtual void reset() = 0;\n\n\t// The `eval()` callback object, `performer`, is included in the virtual call signature since\n\t// the generated code has broadly identical performance properties.\n\tvirtual bool eval(performer *performer = nullptr) = 0;\n\n\t// The `commit()` callback object, `observer`, is not included in the virtual call signature since\n\t// the generated code is severely pessimized by it. To observe commit events, the non-virtual\n\t// `commit(observer *)` overload must be called directly on a `module` subclass.\n\tvirtual bool commit() = 0;\n\n\tsize_t step(performer *performer = nullptr) {\n\t\tsize_t deltas = 0;\n\t\tbool converged = false;\n\t\tdo {\n\t\t\tconverged = eval(performer);\n\t\t\tdeltas++;\n\t\t} while (commit() && !converged);\n\t\treturn deltas;\n\t}\n\n\tvirtual void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) {\n\t\t(void)items, (void)scopes, (void)path, (void)cell_attrs;\n\t}\n\n\t// Compatibility method.\n#if __has_attribute(deprecated)\n\t__attribute__((deprecated(\"Use `debug_info(&items, /*scopes=*/nullptr, path);` instead.\")))\n#endif\n\tvoid debug_info(debug_items &items, std::string path) {\n\t\tdebug_info(&items, /*scopes=*/nullptr, path);\n\t}\n};\n\n} // namespace cxxrtl\n\n// Internal structures used to communicate with the implementation of the C interface.\n\ntypedef struct _cxxrtl_toplevel {\n\tstd::unique_ptr<cxxrtl::module> module;\n} *cxxrtl_toplevel;\n\ntypedef struct _cxxrtl_outline {\n\tstd::function<void()> eval;\n} *cxxrtl_outline;\n\n// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic\n// and indepenent of Yosys implementation details.\n//\n// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these\n// functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,\n// whereas basic operations on arbitrary width values require operands to be of the same width. These functions\n// bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`\n// if the corresponding operand is unsigned, and `s` if it is signed.\nnamespace cxxrtl_yosys {\n\nusing namespace cxxrtl;\n\n// std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.\ntemplate<class T>\nCXXRTL_ALWAYS_INLINE\nconstexpr T max(const T &a, const T &b) {\n\treturn a > b ? a : b;\n}\n\n// Logic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_not(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };\n}\n\n// Reduction operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_and(const value<BitsA> &a) {\n\treturn value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_or(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xnor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_bool(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\n// Bitwise operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_and(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_or(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.sshr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_us<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_ss<BitsY>(a, b);\n}\n\n// Comparison operations\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\n// Arithmetic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().add(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().add(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().sub(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().sub(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;\n\treturn a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template zext<Bits>();\n\tvalue<Bits> divisor = b.template zext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template sext<Bits>();\n\tvalue<Bits> divisor = b.template sext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.sdivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\n// GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and\n// a=b*N+r where N is some integer\n// In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0\n// then return the remainder + b\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> r;\n\tr = divmod_ss<BitsY>(a, b).second;\n\tif((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn add_ss<BitsY>(b, r);\n\treturn r;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\n// Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.\n// In other words, returns (truncating) a/b, except if a and b have different signs\n// and there's non-zero remainder, subtract one more towards floor.\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> q, r;\n\tstd::tie(q, r) = divmod_ss<BitsY>(a, b);\n\tif ((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn sub_uu<BitsY>(q, value<1> { 1u });\n\treturn q;\n\n}\n\n// Memory helper\nstruct memory_index {\n\tbool valid;\n\tsize_t index;\n\n\ttemplate<size_t BitsAddr>\n\tmemory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {\n\t\tstatic_assert(value<BitsAddr>::chunks <= 1, \"memory address is too wide\");\n\t\tsize_t offset_index = addr.data[0];\n\n\t\tvalid = (offset_index >= offset && offset_index < offset + depth);\n\t\tindex = offset_index - offset;\n\t}\n};\n\n} // namespace cxxrtl_yosys\n\n#endif\n",
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"cxxrtl.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.\n//\n// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides\n// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass\n// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler\n// to unwrap the abstraction and generate efficient code.\n\n#ifndef CXXRTL_H\n#define CXXRTL_H\n\n#include <cstddef>\n#include <cstdint>\n#include <cstring>\n#include <cassert>\n#include <limits>\n#include <type_traits>\n#include <tuple>\n#include <vector>\n#include <map>\n#include <algorithm>\n#include <memory>\n#include <functional>\n#include <sstream>\n#include <iostream>\n\n// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifndef __has_attribute\n#\tdefine __has_attribute(x) 0\n#endif\n\n// CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.\n// It generates a lot of specialized template functions with relatively large bodies that, when inlined\n// into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.\n// Because of this, most of the CXXRTL runtime must be always inlined for best performance.\n#if __has_attribute(always_inline)\n#define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))\n#else\n#define CXXRTL_ALWAYS_INLINE inline\n#endif\n// Conversely, some functions in the generated code are extremely large yet very cold, with both of these\n// properties being extreme enough to confuse C++ compilers into spending pathological amounts of time\n// on a futile (the code becomes worse) attempt to optimize the least important parts of code.\n#if __has_attribute(optnone)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))\n#elif __has_attribute(optimize)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))\n#else\n#define CXXRTL_EXTREMELY_COLD\n#endif\n\n// CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior\n// of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at\n// most result in undefined simulation results).\n//\n// Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating\n// the simulation into another process that should survive violating RTL contracts.\n#ifndef CXXRTL_ASSERT\n#ifndef CXXRTL_NDEBUG\n#define CXXRTL_ASSERT(x) assert(x)\n#else\n#define CXXRTL_ASSERT(x)\n#endif\n#endif\n\nnamespace cxxrtl {\n\n// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size\n// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving\n// and introspecting the simulation in Python.\n//\n// It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on\n// narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.\n// However, (a) most of our operations do not change those bits in the first place because of invariants that are\n// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.\n// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be\n// clobbered results in simpler generated code.\ntypedef uint32_t chunk_t;\ntypedef uint64_t wide_chunk_t;\n\ntemplate<typename T>\nstruct chunk_traits {\n\tstatic_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,\n\t \"chunk type must be an unsigned integral type\");\n\tusing type = T;\n\tstatic constexpr size_t bits = std::numeric_limits<T>::digits;\n\tstatic constexpr T mask = std::numeric_limits<T>::max();\n};\n\ntemplate<class T>\nstruct expr_base;\n\ntemplate<size_t Bits>\nstruct value : public expr_base<value<Bits>> {\n\tstatic constexpr size_t bits = Bits;\n\n\tusing chunk = chunk_traits<chunk_t>;\n\tstatic constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask\n\t\t: chunk::mask >> (chunk::bits - (Bits % chunk::bits));\n\n\tstatic constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;\n\tchunk::type data[chunks] = {};\n\n\tvalue() = default;\n\ttemplate<typename... Init>\n\texplicit constexpr value(Init ...init) : data{init...} {}\n\n\tvalue(const value<Bits> &) = default;\n\tvalue<Bits> &operator=(const value<Bits> &) = default;\n\n\tvalue(value<Bits> &&) = default;\n\tvalue<Bits> &operator=(value<Bits> &&) = default;\n\n\t// A (no-op) helper that forces the cast to value<>.\n\tCXXRTL_ALWAYS_INLINE\n\tconst value<Bits> &val() const {\n\t\treturn *this;\n\t}\n\n\tstd::string str() const {\n\t\tstd::stringstream ss;\n\t\tss << *this;\n\t\treturn ss.str();\n\t}\n\n\t// Conversion operations.\n\t//\n\t// These functions ensure that a conversion is never out of range, and should be always used, if at all\n\t// possible, instead of direct manipulation of the `data` member. For very large types, .slice() and\n\t// .concat() can be used to split them into more manageable parts.\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"get<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"get<T>() requires T to be at least as wide as the value is\");\n\t\tIntegerT result = 0;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult |= IntegerT(data[n]) << (n * chunk::bits);\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tauto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();\n\t\tIntegerT result;\n\t\tmemcpy(&result, &unsigned_result, sizeof(IntegerT));\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"set<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"set<T>() requires the value to be at least as wide as T is\");\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tdata[n] = (value >> (n * chunk::bits)) & chunk::mask;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\ttypename std::make_unsigned<IntegerT>::type unsigned_value;\n\t\tmemcpy(&unsigned_value, &value, sizeof(IntegerT));\n\t\tset(unsigned_value);\n\t}\n\n\t// Operations with compile-time parameters.\n\t//\n\t// These operations are used to implement slicing, concatenation, and blitting.\n\t// The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);\n\t// the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> trunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"trunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < result.chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zext() const {\n\t\tstatic_assert(NewBits >= Bits, \"zext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> sext() const {\n\t\tstatic_assert(NewBits >= Bits, \"sext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tif (is_neg()) {\n\t\t\tresult.data[chunks - 1] |= ~msb_mask;\n\t\t\tfor (size_t n = chunks; n < result.chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rtrunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"rtrunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (Bits - NewBits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tif (shift_chunks + result.chunks < chunks) {\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);\n\t\t}\n\t\tfor (size_t n = result.chunks; n > 0; n--) {\n\t\t\tresult.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + n - 1] << (chunk::bits - shift_bits);\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rzext() const {\n\t\tstatic_assert(NewBits >= Bits, \"rzext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (NewBits - Bits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (shift_chunks + chunks < result.chunks)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\t// Bit blit operation, i.e. a partial read-modify-write.\n\ttemplate<size_t Stop, size_t Start>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits> blit(const value<Stop - Start + 1> &source) const {\n\t\tstatic_assert(Stop >= Start, \"blit() may not reverse bit order\");\n\t\tconstexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));\n\t\tconstexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0\n\t\t\t: (chunk::mask << (Stop % chunk::bits + 1));\n\t\tvalue<Bits> masked = *this;\n\t\tif (Start / chunk::bits == Stop / chunk::bits) {\n\t\t\tmasked.data[Start / chunk::bits] &= stop_mask | start_mask;\n\t\t} else {\n\t\t\tmasked.data[Start / chunk::bits] &= start_mask;\n\t\t\tfor (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)\n\t\t\t\tmasked.data[n] = 0;\n\t\t\tmasked.data[Stop / chunk::bits] &= stop_mask;\n\t\t}\n\t\tvalue<Bits> shifted = source\n\t\t\t.template rzext<Stop + 1>()\n\t\t\t.template zext<Bits>();\n\t\treturn masked.bit_or(shifted);\n\t}\n\n\t// Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower\n\t// than the operand. In C++17 these can be replaced with `if constexpr`.\n\ttemplate<size_t NewBits, typename = void>\n\tstruct zext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template zext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits, typename = void>\n\tstruct sext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template sext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zcast() const {\n\t\treturn zext_cast<NewBits>()(*this);\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> scast() const {\n\t\treturn sext_cast<NewBits>()(*this);\n\t}\n\n\t// Bit replication is far more efficient than the equivalent concatenation.\n\ttemplate<size_t Count>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits * Count> repeat() const {\n\t\tstatic_assert(Bits == 1, \"repeat() is implemented only for 1-bit values\");\n\t\treturn *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();\n\t}\n\n\t// Operations with run-time parameters (offsets, amounts, etc).\n\t//\n\t// These operations are used for computations.\n\tbool bit(size_t offset) const {\n\t\treturn data[offset / chunk::bits] & (1 << (offset % chunk::bits));\n\t}\n\n\tvoid set_bit(size_t offset, bool value = true) {\n\t\tsize_t offset_chunks = offset / chunk::bits;\n\t\tsize_t offset_bits = offset % chunk::bits;\n\t\tdata[offset_chunks] &= ~(1 << offset_bits);\n\t\tdata[offset_chunks] |= value ? 1 << offset_bits : 0;\n\t}\n\n\texplicit operator bool() const {\n\t\treturn !is_zero();\n\t}\n\n\tbool is_zero() const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool is_neg() const {\n\t\treturn data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));\n\t}\n\n\tbool operator ==(const value<Bits> &other) const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != other.data[n])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator !=(const value<Bits> &other) const {\n\t\treturn !(*this == other);\n\t}\n\n\tvalue<Bits> bit_not() const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = ~data[n];\n\t\tresult.data[chunks - 1] &= msb_mask;\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_and(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] & other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_or(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] | other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_xor(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] ^ other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {\n\t\treturn bit_and(mask.bit_not()).bit_or(val.bit_and(mask));\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> shl(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shl() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn {};\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn {};\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits, bool Signed = false>\n\tvalue<Bits> shr(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shr() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Signed && is_neg()) {\n\t\t\tsize_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;\n\t\t\tsize_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;\n\t\t\tfor (size_t n = top_chunk_idx + 1; n < chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tif (amount.data[0] != 0)\n\t\t\t\tresult.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> sshr(const value<AmountBits> &amount) const {\n\t\treturn shr<AmountBits, /*Signed=*/true>(amount);\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> bmux(const value<SelBits> &sel) const {\n\t\tstatic_assert(ResultBits << SelBits == Bits, \"invalid sizes used in bmux()\");\n\t\tsize_t amount = sel.data[0] * ResultBits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tif (ResultBits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tcarry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits> bwmux(const value<Bits> &b, const value<Bits> &s) const {\n\t\treturn (bit_and(s.bit_not())).bit_or(b.bit_and(s));\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> demux(const value<SelBits> &sel) const {\n\t\tstatic_assert(Bits << SelBits == ResultBits, \"invalid sizes used in demux()\");\n\t\tsize_t amount = sel.data[0] * Bits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Bits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\tsize_t ctpop() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\t// This loop implements the population count idiom as recognized by LLVM and GCC.\n\t\t\tfor (chunk::type x = data[n]; x != 0; count++)\n\t\t\t\tx = x & (x - 1);\n\t\t}\n\t\treturn count;\n\t}\n\n\tsize_t ctlz() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tchunk::type x = data[chunks - 1 - n];\n\t\t\t// First add to `count` as if the chunk is zero\n\t\t\tconstexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;\n\t\t\tcount += (n == 0 ? msb_chunk_bits : chunk::bits);\n\t\t\t// If the chunk isn't zero, correct the `count` value and return\n\t\t\tif (x != 0) {\n\t\t\t\tfor (; x != 0; count--)\n\t\t\t\t\tx >>= 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\treturn count;\n\t}\n\n\ttemplate<bool Invert, bool CarryIn>\n\tstd::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry = CarryIn;\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;\n\t\t\tif (result.chunks - 1 == n)\n\t\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t\tcarry = (result.data[n] < data[n]) ||\n\t\t\t (result.data[n] == data[n] && carry);\n\t\t}\n\t\treturn {result, carry};\n\t}\n\n\tvalue<Bits> add(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/false, /*CarryIn=*/false>(other).first;\n\t}\n\n\tvalue<Bits> sub(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/true, /*CarryIn=*/true>(other).first;\n\t}\n\n\tvalue<Bits> neg() const {\n\t\treturn value<Bits>().sub(*this);\n\t}\n\n\tbool ucmp(const value<Bits> &other) const {\n\t\tbool carry;\n\t\tstd::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\treturn !carry; // a.ucmp(b) ≡ a u< b\n\t}\n\n\tbool scmp(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry;\n\t\tstd::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\tbool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());\n\t\treturn result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b\n\t}\n\n\ttemplate<size_t ResultBits>\n\tvalue<ResultBits> mul(const value<Bits> &other) const {\n\t\tvalue<ResultBits> result;\n\t\twide_chunk_t wide_result[result.chunks + 1] = {};\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tfor (size_t m = 0; m < chunks && n + m < result.chunks; m++) {\n\t\t\t\twide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);\n\t\t\t\twide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;\n\t\t\t\twide_result[n + m] &= chunk::mask;\n\t\t\t}\n\t\t}\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = wide_result[n];\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {\n\t\tvalue<Bits> quotient;\n\t\tvalue<Bits> dividend = *this;\n\t\tif (dividend.ucmp(divisor))\n\t\t\treturn {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};\n\t\tint64_t divisor_shift = divisor.ctlz() - dividend.ctlz();\n\t\tassert(divisor_shift >= 0);\n\t\tdivisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});\n\t\tfor (size_t step = 0; step <= divisor_shift; step++) {\n\t\t\tquotient = quotient.shl(value<Bits>{1u});\n\t\t\tif (!dividend.ucmp(divisor)) {\n\t\t\t\tdividend = dividend.sub(divisor);\n\t\t\t\tquotient.set_bit(0, true);\n\t\t\t}\n\t\t\tdivisor = divisor.shr(value<Bits>{1u});\n\t\t}\n\t\treturn {quotient, /*remainder=*/dividend};\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {\n\t\tvalue<Bits + 1> quotient;\n\t\tvalue<Bits + 1> remainder;\n\t\tvalue<Bits + 1> dividend = sext<Bits + 1>();\n\t\tvalue<Bits + 1> divisor = other.template sext<Bits + 1>();\n\t\tif (is_neg()) dividend = dividend.neg();\n\t\tif (other.is_neg()) divisor = divisor.neg();\n\t\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\t\tif (is_neg() != other.is_neg()) quotient = quotient.neg();\n\t\tif (is_neg()) remainder = remainder.neg();\n\t\treturn {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};\n\t}\n};\n\n// Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, size_t Stop, size_t Start>\nstruct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {\n\tstatic_assert(Stop >= Start, \"slice_expr() may not reverse bit order\");\n\tstatic_assert(Start < T::bits && Stop < T::bits, \"slice_expr() must be within bounds\");\n\tstatic constexpr size_t bits = Stop - Start + 1;\n\n\tT &expr;\n\n\tslice_expr(T &expr) : expr(expr) {}\n\tslice_expr(const slice_expr<T, Stop, Start> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\treturn static_cast<const value<T::bits> &>(expr)\n\t\t\t.template rtrunc<T::bits - Start>()\n\t\t\t.template trunc<bits>();\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {\n\t\t// Generic partial assignment implemented using a read-modify-write operation on the sliced expression.\n\t\texpr = static_cast<const value<T::bits> &>(expr)\n\t\t\t.template blit<Stop, Start>(rhs);\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, class U>\nstruct concat_expr : public expr_base<concat_expr<T, U>> {\n\tstatic constexpr size_t bits = T::bits + U::bits;\n\n\tT &ms_expr;\n\tU &ls_expr;\n\n\tconcat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}\n\tconcat_expr(const concat_expr<T, U> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\tvalue<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)\n\t\t\t.template rzext<bits>();\n\t\tvalue<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)\n\t\t\t.template zext<bits>();\n\t\treturn ms_shifted.bit_or(ls_extended);\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, U> &operator=(const value<bits> &rhs) {\n\t\tms_expr = rhs.template rtrunc<T::bits>();\n\t\tls_expr = rhs.template trunc<U::bits>();\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.\n//\n// Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because\n// they refer to temporaries that will, in general, only live until the end of the statement. For example, both of\n// these snippets perform use-after-free:\n//\n// const auto &a = val.slice<7,0>().slice<1>();\n// value<1> b = a;\n//\n// auto &&c = val.slice<7,0>().slice<1>();\n// c = value<1>{1u};\n//\n// An easy way to write code using slices and concatenations safely is to follow two simple rules:\n// * Never explicitly name any type except `value<W>` or `const value<W> &`.\n// * Never use a `const auto &` or `auto &&` in any such expression.\n// Then, any code that compiles will be well-defined.\ntemplate<class T>\nstruct expr_base {\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<const T, Stop, Start> slice() const {\n\t\treturn {*static_cast<const T *>(this)};\n\t}\n\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> slice() {\n\t\treturn {*static_cast<T *>(this)};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {\n\t\treturn {*static_cast<const T *>(this), other};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {\n\t\treturn {*static_cast<T *>(this), other};\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const value<Bits> &val) {\n\tauto old_flags = os.flags(std::ios::right);\n\tauto old_width = os.width(0);\n\tauto old_fill = os.fill('0');\n\tos << val.bits << '\\'' << std::hex;\n\tfor (size_t n = val.chunks - 1; n != (size_t)-1; n--) {\n\t\tif (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)\n\t\t\tos.width((Bits % value<Bits>::chunk::bits + 3) / 4);\n\t\telse\n\t\t\tos.width((value<Bits>::chunk::bits + 3) / 4);\n\t\tos << val.data[n];\n\t}\n\tos.fill(old_fill);\n\tos.width(old_width);\n\tos.flags(old_flags);\n\treturn os;\n}\n\ntemplate<size_t Bits>\nstruct wire {\n\tstatic constexpr size_t bits = Bits;\n\n\tvalue<Bits> curr;\n\tvalue<Bits> next;\n\n\twire() = default;\n\texplicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}\n\ttemplate<typename... Init>\n\texplicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}\n\n\t// Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,\n\t// e.g. because a module is built with a different optimization level, then existing code could\n\t// unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure\n\t// this doesn't happen, prohibit copying and copy-assigning wires.\n\twire(const wire<Bits> &) = delete;\n\twire<Bits> &operator=(const wire<Bits> &) = delete;\n\n\twire(wire<Bits> &&) = default;\n\twire<Bits> &operator=(wire<Bits> &&) = default;\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\treturn curr.template get<IntegerT>();\n\t}\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT other) {\n\t\tnext.template set<IntegerT>(other);\n\t}\n\n\t// This method intentionally takes a mandatory argument (to make it more difficult to misuse in\n\t// black box implementations, leading to missed observer events). It is generic over its argument\n\t// to allow the `on_update` method to be non-virtual.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tif (curr != next) {\n\t\t\tobserver.on_update(curr.chunks, curr.data, next.data);\n\t\t\tcurr = next;\n\t\t\treturn true;\n\t\t}\n\t\treturn false;\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {\n\tos << val.curr;\n\treturn os;\n}\n\ntemplate<size_t Width>\nstruct memory {\n\tconst size_t depth;\n\tstd::unique_ptr<value<Width>[]> data;\n\n\texplicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}\n\n\tmemory(const memory<Width> &) = delete;\n\tmemory<Width> &operator=(const memory<Width> &) = delete;\n\n\tmemory(memory<Width> &&) = default;\n\tmemory<Width> &operator=(memory<Width> &&other) {\n\t\tassert(depth == other.depth);\n\t\tdata = std::move(other.data);\n\t\twrite_queue = std::move(other.write_queue);\n\t\treturn *this;\n\t}\n\n\t// An operator for direct memory reads. May be used at any time during the simulation.\n\tconst value<Width> &operator [](size_t index) const {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// An operator for direct memory writes. May only be used before the simulation is started. If used\n\t// after the simulation is started, the design may malfunction.\n\tvalue<Width> &operator [](size_t index) {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// A simple way to make a writable memory would be to use an array of wires instead of an array of values.\n\t// However, there are two significant downsides to this approach: first, it has large overhead (2× space\n\t// overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port\n\t// priorities. Although in principle write ports could be ordered or conditionally enabled in generated\n\t// code based on their priorities and selected addresses, the feedback arc set problem is computationally\n\t// expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)\n\t// a particular write port evaluation order.\n\t//\n\t// The approach used here instead is to queue writes into a buffer during the eval phase, then perform\n\t// the writes during the commit phase in the priority order. This approach has low overhead, with both space\n\t// and time proportional to the amount of write ports. Because virtually every memory in a practical design\n\t// has at most two write ports, linear search is used on every write, being the fastest and simplest approach.\n\tstruct write {\n\t\tsize_t index;\n\t\tvalue<Width> val;\n\t\tvalue<Width> mask;\n\t\tint priority;\n\t};\n\tstd::vector<write> write_queue;\n\n\tvoid update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {\n\t\tassert(index < depth);\n\t\t// Queue up the write while keeping the queue sorted by priority.\n\t\twrite_queue.insert(\n\t\t\tstd::upper_bound(write_queue.begin(), write_queue.end(), priority,\n\t\t\t\t[](const int a, const write& b) { return a < b.priority; }),\n\t\t\twrite { index, val, mask, priority });\n\t}\n\n\t// See the note for `wire::commit()`.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tbool changed = false;\n\t\tfor (const write &entry : write_queue) {\n\t\t\tvalue<Width> elem = data[entry.index];\n\t\t\telem = elem.update(entry.val, entry.mask);\n\t\t\tif (data[entry.index] != elem) {\n\t\t\t\tobserver.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);\n\t\t\t\tchanged |= true;\n\t\t\t}\n\t\t\tdata[entry.index] = elem;\n\t\t}\n\t\twrite_queue.clear();\n\t\treturn changed;\n\t}\n};\n\nstruct metadata {\n\tconst enum {\n\t\tMISSING = 0,\n\t\tUINT \t= 1,\n\t\tSINT \t= 2,\n\t\tSTRING \t= 3,\n\t\tDOUBLE \t= 4,\n\t} value_type;\n\n\t// In debug mode, using the wrong .as_*() function will assert.\n\t// In release mode, using the wrong .as_*() function will safely return a default value.\n\tconst uint64_t uint_value = 0;\n\tconst int64_t sint_value = 0;\n\tconst std::string string_value = \"\";\n\tconst double double_value = 0.0;\n\n\tmetadata() : value_type(MISSING) {}\n\tmetadata(uint64_t value) : value_type(UINT), uint_value(value) {}\n\tmetadata(int64_t value) : value_type(SINT), sint_value(value) {}\n\tmetadata(const std::string &value) : value_type(STRING), string_value(value) {}\n\tmetadata(const char *value) : value_type(STRING), string_value(value) {}\n\tmetadata(double value) : value_type(DOUBLE), double_value(value) {}\n\n\tmetadata(const metadata &) = default;\n\tmetadata &operator=(const metadata &) = delete;\n\n\tuint64_t as_uint() const {\n\t\tassert(value_type == UINT);\n\t\treturn uint_value;\n\t}\n\n\tint64_t as_sint() const {\n\t\tassert(value_type == SINT);\n\t\treturn sint_value;\n\t}\n\n\tconst std::string &as_string() const {\n\t\tassert(value_type == STRING);\n\t\treturn string_value;\n\t}\n\n\tdouble as_double() const {\n\t\tassert(value_type == DOUBLE);\n\t\treturn double_value;\n\t}\n\n\t// Internal CXXRTL use only.\n\tstatic std::map<std::string, metadata> deserialize(const char *ptr) {\n\t\tstd::map<std::string, metadata> result;\n\t\tstd::string name;\n\t\t// Grammar:\n\t\t// string ::= [^\\0]+ \\0\n\t\t// metadata ::= [uid] .{8} | s <string>\n\t\t// map ::= ( <string> <metadata> )* \\0\n\t\tfor (;;) {\n\t\t\tif (*ptr) {\n\t\t\t\tname += *ptr++;\n\t\t\t} else if (!name.empty()) {\n\t\t\t\tptr++;\n\t\t\t\tauto get_u64 = [&]() {\n\t\t\t\t\tuint64_t result = 0;\n\t\t\t\t\tfor (size_t count = 0; count < 8; count++)\n\t\t\t\t\t\tresult = (result << 8) | *ptr++;\n\t\t\t\t\treturn result;\n\t\t\t\t};\n\t\t\t\tchar type = *ptr++;\n\t\t\t\tif (type == 'u') {\n\t\t\t\t\tuint64_t value = get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'i') {\n\t\t\t\t\tint64_t value = (int64_t)get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'd') {\n\t\t\t\t\tdouble dvalue;\n\t\t\t\t\tuint64_t uvalue = get_u64();\n\t\t\t\t\tstatic_assert(sizeof(dvalue) == sizeof(uvalue), \"double must be 64 bits in size\");\n\t\t\t\t\tmemcpy(&dvalue, &uvalue, sizeof(dvalue));\n\t\t\t\t\tresult.emplace(name, dvalue);\n\t\t\t\t} else if (type == 's') {\n\t\t\t\t\tstd::string value;\n\t\t\t\t\twhile (*ptr)\n\t\t\t\t\t\tvalue += *ptr++;\n\t\t\t\t\tptr++;\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else {\n\t\t\t\t\tassert(false && \"Unknown type specifier\");\n\t\t\t\t\treturn result;\n\t\t\t\t}\n\t\t\t\tname.clear();\n\t\t\t} else {\n\t\t\t\treturn result;\n\t\t\t}\n\t\t}\n\t}\n};\n\ntypedef std::map<std::string, metadata> metadata_map;\n\nstruct performer;\n\n// An object that allows formatting a string lazily.\nstruct lazy_fmt {\n\tvirtual std::string operator() () const = 0;\n};\n\n// Flavor of a `$check` cell.\nenum class flavor {\n\t// Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement.\n\tASSERT,\n\t// Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement.\n\tASSUME,\n\t// Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement.\n\tASSERT_EVENTUALLY,\n\t// Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement.\n\tASSUME_EVENTUALLY,\n\t// Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement.\n\tCOVER,\n};\n\n// An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented\n// below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not\n// taken into account.\nstruct performer {\n\t// Called by generated formatting code to evaluate a Verilog `$time` expression.\n\tvirtual int64_t vlog_time() const { return 0; }\n\n\t// Called by generated formatting code to evaluate a Verilog `$realtime` expression.\n\tvirtual double vlog_realtime() const { return vlog_time(); }\n\n\t// Called when a `$print` cell is triggered.\n\tvirtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tstd::cout << formatter();\n\t}\n\n\t// Called when a `$check` cell is triggered.\n\tvirtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tif (type == flavor::ASSERT || type == flavor::ASSUME) {\n\t\t\tif (!condition)\n\t\t\t\tstd::cerr << formatter();\n\t\t\tCXXRTL_ASSERT(condition && \"Check failed\");\n\t\t}\n\t}\n};\n\n// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in\n// the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and\n// a comparatively heavyweight template-based solution is justified.\nstruct observer {\n\t// Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks\n\t// at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and\n\t// `base` points to the first chunk.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}\n\n\t// Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`\n\t// with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to\n\t// the memory element chunk count and `base` points to the first chunk of the first element of the memory.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}\n};\n\n// Must be kept in sync with `struct FmtPart` in kernel/fmt.h!\n// Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.\nstruct fmt_part {\n\tenum {\n\t\tLITERAL = 0,\n\t\tINTEGER = 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\t// + value<Bits> val;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify; // = RIGHT;\n\tchar padding; // = '\\0';\n\tsize_t width; // = 0;\n\n\t// INTEGER type\n\tunsigned base; // = 10;\n\tbool signed_; // = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign; // = MINUS;\n\tbool hex_upper; // = false;\n\tbool show_base; // = false;\n\tbool group; // = false;\n\n\t// VLOG_TIME type\n\tbool realtime; // = false;\n\t// + int64_t itime;\n\t// + double ftime;\n\n\t// Format the part as a string.\n\t//\n\t// The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.\n\ttemplate<size_t Bits>\n\tstd::string render(value<Bits> val, performer *performer = nullptr)\n\t{\n\t\t// We might want to replace some of these bit() calls with direct\n\t\t// chunk access if it turns out to be slow enough to matter.\n\t\tstd::string buf;\n\t\tstd::string prefix;\n\t\tswitch (type) {\n\t\t\tcase LITERAL:\n\t\t\t\treturn str;\n\n\t\t\tcase STRING: {\n\t\t\t\tbuf.reserve(Bits/8);\n\t\t\t\tfor (int i = 0; i < Bits; i += 8) {\n\t\t\t\t\tchar ch = 0;\n\t\t\t\t\tfor (int j = 0; j < 8 && i + j < int(Bits); j++)\n\t\t\t\t\t\tif (val.bit(i + j))\n\t\t\t\t\t\t\tch |= 1 << j;\n\t\t\t\t\tif (ch != 0)\n\t\t\t\t\t\tbuf.append({ch});\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase UNICHAR: {\n\t\t\t\tuint32_t codepoint = val.template zcast<32>().template get<uint32_t>();\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0xf0 | (codepoint >> 18));\n\t\t\t\telse if (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0xe0 | (codepoint >> 12));\n\t\t\t\telse if (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0xc0 | (codepoint >> 6));\n\t\t\t\telse\n\t\t\t\t\tbuf += (char)codepoint;\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 12) & 0x3f));\n\t\t\t\tif (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 6) & 0x3f));\n\t\t\t\tif (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 0) & 0x3f));\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase INTEGER: {\n\t\t\t\tbool negative = signed_ && val.is_neg();\n\t\t\t\tif (negative) {\n\t\t\t\t\tprefix = \"-\";\n\t\t\t\t\tval = val.neg();\n\t\t\t\t} else {\n\t\t\t\t\tswitch (sign) {\n\t\t\t\t\t\tcase MINUS: break;\n\t\t\t\t\t\tcase PLUS_MINUS: prefix = \"+\"; break;\n\t\t\t\t\t\tcase SPACE_MINUS: prefix = \" \"; break;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tsize_t val_width = Bits;\n\t\t\t\tif (base != 10) {\n\t\t\t\t\tval_width = 1;\n\t\t\t\t\tfor (size_t index = 0; index < Bits; index++)\n\t\t\t\t\t\tif (val.bit(index))\n\t\t\t\t\t\t\tval_width = index + 1;\n\t\t\t\t}\n\n\t\t\t\tif (base == 2) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0b\";\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index++) {\n\t\t\t\t\t\tif (group && index > 0 && index % 4 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += (val.bit(index) ? '1' : '0');\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 8 || base == 16) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += (base == 16) ? (hex_upper ? \"0X\" : \"0x\") : \"0o\";\n\t\t\t\t\tsize_t step = (base == 16) ? 4 : 3;\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index += step) {\n\t\t\t\t\t\tif (group && index > 0 && index % (4 * step) == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tuint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);\n\t\t\t\t\t\tif (step == 4)\n\t\t\t\t\t\t\tvalue |= val.bit(index + 3) << 3;\n\t\t\t\t\t\tbuf += (hex_upper ? \"0123456789ABCDEF\" : \"0123456789abcdef\")[value];\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 10) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0d\";\n\t\t\t\t\tif (val.is_zero())\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();\n\t\t\t\t\tsize_t index = 0;\n\t\t\t\t\twhile (!xval.is_zero()) {\n\t\t\t\t\t\tif (group && index > 0 && index % 3 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> quotient, remainder;\n\t\t\t\t\t\tif (Bits >= 4)\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);\n\t\t\t\t\t\tbuf += '0' + remainder.template trunc<4>().template get<uint8_t>();\n\t\t\t\t\t\txval = quotient;\n\t\t\t\t\t\tindex++;\n\t\t\t\t\t}\n\t\t\t\t} else assert(false && \"Unsupported base for fmt_part\");\n\t\t\t\tif (justify == NUMERIC && group && padding == '0') {\n\t\t\t\t\tint group_size = base == 10 ? 3 : 4;\n\t\t\t\t\twhile (prefix.size() + buf.size() < width) {\n\t\t\t\t\t\tif (buf.size() % (group_size + 1) == group_size)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase VLOG_TIME: {\n\t\t\t\tif (performer) {\n\t\t\t\t\tbuf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());\n\t\t\t\t} else {\n\t\t\t\t\tbuf = realtime ? std::to_string(0.0) : std::to_string(0);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tstd::string str;\n\t\tassert(width == 0 || padding != '\\0');\n\t\tif (prefix.size() + buf.size() < width) {\n\t\t\tsize_t pad_width = width - prefix.size() - buf.size();\n\t\t\tswitch (justify) {\n\t\t\t\tcase LEFT:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tbreak;\n\t\t\t\tcase RIGHT:\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\tcase NUMERIC:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t} else {\n\t\t\tstr += prefix;\n\t\t\tstr += buf;\n\t\t}\n\t\treturn str;\n\t}\n};\n\n// Tag class to disambiguate values/wires and their aliases.\nstruct debug_alias {};\n\n// Tag declaration to disambiguate values and debug outlines.\nusing debug_outline = ::_cxxrtl_outline;\n\n// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.\n// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.\n//\n// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used\n// in the C API, or it would not be possible to cast between the pointers to these.\n//\n// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created\n// from external C code.\nstruct debug_item : ::cxxrtl_object {\n\t// Object types.\n\tenum : uint32_t {\n\t\tVALUE = CXXRTL_VALUE,\n\t\tWIRE = CXXRTL_WIRE,\n\t\tMEMORY = CXXRTL_MEMORY,\n\t\tALIAS = CXXRTL_ALIAS,\n\t\tOUTLINE = CXXRTL_OUTLINE,\n\t};\n\n\t// Object flags.\n\tenum : uint32_t {\n\t\tINPUT = CXXRTL_INPUT,\n\t\tOUTPUT = CXXRTL_OUTPUT,\n\t\tINOUT = CXXRTL_INOUT,\n\t\tDRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,\n\t\tDRIVEN_COMB = CXXRTL_DRIVEN_COMB,\n\t\tUNDRIVEN = CXXRTL_UNDRIVEN,\n\t\tGENERATED = CXXRTL_GENERATED,\n\t};\n\n\tdebug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}\n\n\ttemplate<size_t Bits>\n\tdebug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.data;\n\t\tnext = item.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = WIRE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.curr.data;\n\t\tnext = item.next.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Width>\n\tdebug_item(memory<Width> &item, size_t zero_offset = 0) {\n\t\tstatic_assert(Width == 0 || sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),\n\t\t \"memory<Width> is not compatible with C layout\");\n\t\ttype = MEMORY;\n\t\tflags = 0;\n\t\twidth = Width;\n\t\tlsb_at = 0;\n\t\tdepth = item.depth;\n\t\tzero_at = zero_offset;\n\t\tcurr = item.data ? item.data[0].data : nullptr;\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.curr.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = OUTLINE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = &group;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tIntegerT get() const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\tstd::copy(curr, curr + value<Bits>::chunks, item.data);\n\t\treturn item.template get<IntegerT>();\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tvoid set(IntegerT other) const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\titem.template set<IntegerT>(other);\n\t\tstd::copy(item.data, item.data + value<Bits>::chunks, next);\n\t}\n};\nstatic_assert(std::is_standard_layout<debug_item>::value, \"debug_item is not compatible with C layout\");\n\n} // namespace cxxrtl\n\ntypedef struct _cxxrtl_attr_set {\n\tcxxrtl::metadata_map map;\n} *cxxrtl_attr_set;\n\nnamespace cxxrtl {\n\n// Representation of an attribute set in the C++ interface.\nusing debug_attrs = ::_cxxrtl_attr_set;\n\nstruct debug_items {\n\t// Debug items may be composed of multiple parts, but the attributes are shared between all of them.\n\t// There are additional invariants, not all of which are not checked by this code:\n\t// - Memories and non-memories cannot be mixed together.\n\t// - Bit indices (considering `lsb_at` and `width`) must not overlap.\n\t// - Row indices (considering `depth` and `zero_at`) must be the same.\n\t// - The `INPUT` and `OUTPUT` flags must be the same for all parts.\n\t// Other than that, the parts can be quite different, e.g. it is OK to mix a value, a wire, an alias,\n\t// and an outline, in the debug information for a single name in four parts.\n\tstd::map<std::string, std::vector<debug_item>> table;\n\tstd::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;\n\n\tvoid add(const std::string &path, debug_item &&item, metadata_map &&item_attrs = {}) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tstd::unique_ptr<debug_attrs> &attrs = attrs_table[path];\n\t\tif (attrs.get() == nullptr)\n\t\t\tattrs = std::unique_ptr<debug_attrs>(new debug_attrs);\n\t\tfor (auto attr : item_attrs)\n\t\t\tattrs->map.insert(attr);\n\t\titem.attrs = attrs.get();\n\t\tstd::vector<debug_item> &parts = table[path];\n\t\tparts.emplace_back(item);\n\t\tstd::sort(parts.begin(), parts.end(),\n\t\t\t[](const debug_item &a, const debug_item &b) {\n\t\t\t\treturn a.lsb_at < b.lsb_at;\n\t\t\t});\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\ttemplate<class... T>\n\tvoid add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {\n\t\tadd(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));\n\t}\n\n\tsize_t count(const std::string &path) const {\n\t\tif (table.count(path) == 0)\n\t\t\treturn 0;\n\t\treturn table.at(path).size();\n\t}\n\n\tconst std::vector<debug_item> &at(const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n\n\t// Like `at()`, but operates only on single-part debug items.\n\tconst debug_item &operator [](const std::string &path) const {\n\t\tconst std::vector<debug_item> &parts = table.at(path);\n\t\tassert(parts.size() == 1);\n\t\treturn parts.at(0);\n\t}\n\n\tbool is_memory(const std::string &path) const {\n\t\treturn at(path).at(0).type == debug_item::MEMORY;\n\t}\n\n\tconst metadata_map &attrs(const std::string &path) const {\n\t\treturn attrs_table.at(path)->map;\n\t}\n};\n\n// Only `module` scopes are defined. The type is implicit, since Yosys does not currently support\n// any other scope types.\nstruct debug_scope {\n\tstd::string module_name;\n\tstd::unique_ptr<debug_attrs> module_attrs;\n\tstd::unique_ptr<debug_attrs> cell_attrs;\n};\n\nstruct debug_scopes {\n\tstd::map<std::string, debug_scope> table;\n\n\tvoid add(const std::string &path, const std::string &module_name, metadata_map &&module_attrs, metadata_map &&cell_attrs) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tassert(table.count(path) == 0);\n\t\tdebug_scope &scope = table[path];\n\t\tscope.module_name = module_name;\n\t\tscope.module_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { module_attrs });\n\t\tscope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\tvoid add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {\n\t\tadd(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));\n\t}\n\n\tsize_t contains(const std::string &path) const {\n\t\treturn table.count(path);\n\t}\n\n\tconst debug_scope &operator [](const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n};\n\n// Tag class to disambiguate the default constructor used by the toplevel module that calls `reset()`,\n// and the constructor of interior modules that should not call it.\nstruct interior {};\n\n// The core API of the `module` class consists of only four virtual methods: `reset()`, `eval()`,\n// `commit`, and `debug_info()`. (The virtual destructor is made necessary by C++.) Every other method\n// is a convenience method, and exists solely to simplify some common pattern for C++ API consumers.\n// No behavior may be added to such convenience methods that other parts of CXXRTL can rely on, since\n// there is no guarantee they will be called (and, for example, other CXXRTL libraries will often call\n// the `eval()` and `commit()` directly instead, as well as being exposed in the C API).\nstruct module {\n\tmodule() {}\n\tvirtual ~module() {}\n\n\t// Modules with black boxes cannot be copied. Although not all designs include black boxes,\n\t// delete the copy constructor and copy assignment operator to make sure that any downstream\n\t// code that manipulates modules doesn't accidentally depend on their availability.\n\tmodule(const module &) = delete;\n\tmodule &operator=(const module &) = delete;\n\n\tmodule(module &&) = default;\n\tmodule &operator=(module &&) = default;\n\n\tvirtual void reset() = 0;\n\n\t// The `eval()` callback object, `performer`, is included in the virtual call signature since\n\t// the generated code has broadly identical performance properties.\n\tvirtual bool eval(performer *performer = nullptr) = 0;\n\n\t// The `commit()` callback object, `observer`, is not included in the virtual call signature since\n\t// the generated code is severely pessimized by it. To observe commit events, the non-virtual\n\t// `commit(observer *)` overload must be called directly on a `module` subclass.\n\tvirtual bool commit() = 0;\n\n\tsize_t step(performer *performer = nullptr) {\n\t\tsize_t deltas = 0;\n\t\tbool converged = false;\n\t\tdo {\n\t\t\tconverged = eval(performer);\n\t\t\tdeltas++;\n\t\t} while (commit() && !converged);\n\t\treturn deltas;\n\t}\n\n\tvirtual void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) {\n\t\t(void)items, (void)scopes, (void)path, (void)cell_attrs;\n\t}\n\n\t// Compatibility method.\n#if __has_attribute(deprecated)\n\t__attribute__((deprecated(\"Use `debug_info(&items, /*scopes=*/nullptr, path);` instead.\")))\n#endif\n\tvoid debug_info(debug_items &items, std::string path) {\n\t\tdebug_info(&items, /*scopes=*/nullptr, path);\n\t}\n};\n\n} // namespace cxxrtl\n\n// Internal structures used to communicate with the implementation of the C interface.\n\ntypedef struct _cxxrtl_toplevel {\n\tstd::unique_ptr<cxxrtl::module> module;\n} *cxxrtl_toplevel;\n\ntypedef struct _cxxrtl_outline {\n\tstd::function<void()> eval;\n} *cxxrtl_outline;\n\n// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic\n// and indepenent of Yosys implementation details.\n//\n// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these\n// functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,\n// whereas basic operations on arbitrary width values require operands to be of the same width. These functions\n// bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`\n// if the corresponding operand is unsigned, and `s` if it is signed.\nnamespace cxxrtl_yosys {\n\nusing namespace cxxrtl;\n\n// std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.\ntemplate<class T>\nCXXRTL_ALWAYS_INLINE\nconstexpr T max(const T &a, const T &b) {\n\treturn a > b ? a : b;\n}\n\n// Logic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_not(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };\n}\n\n// Reduction operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_and(const value<BitsA> &a) {\n\treturn value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_or(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xnor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_bool(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\n// Bitwise operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_and(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_or(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shr(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.sshr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_us<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_ss<BitsY>(a, b);\n}\n\n// Comparison operations\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\n// Arithmetic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().add(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().add(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().sub(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().sub(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;\n\treturn a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template zext<Bits>();\n\tvalue<Bits> divisor = b.template trunc<BitsB>().template zext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template sext<Bits>();\n\tvalue<Bits> divisor = b.template sext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.sdivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\n// GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and\n// a=b*N+r where N is some integer\n// In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0\n// then return the remainder + b\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> r;\n\tr = divmod_ss<BitsY>(a, b).second;\n\tif((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn add_ss<BitsY>(b, r);\n\treturn r;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\n// Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.\n// In other words, returns (truncating) a/b, except if a and b have different signs\n// and there's non-zero remainder, subtract one more towards floor.\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> q, r;\n\tstd::tie(q, r) = divmod_ss<BitsY>(a, b);\n\tif ((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn sub_uu<BitsY>(q, value<1> { 1u });\n\treturn q;\n\n}\n\n// Memory helper\nstruct memory_index {\n\tbool valid;\n\tsize_t index;\n\n\ttemplate<size_t BitsAddr>\n\tmemory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {\n\t\tstatic_assert(value<BitsAddr>::chunks <= 1, \"memory address is too wide\");\n\t\tsize_t offset_index = addr.data[0];\n\n\t\tvalid = (offset_index >= offset && offset_index < offset + depth);\n\t\tindex = offset_index - offset;\n\t}\n};\n\n} // namespace cxxrtl_yosys\n\n#endif\n",
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"cxxrtl_replay.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2023 Catherine <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_REPLAY_H\n#define CXXRTL_REPLAY_H\n\n#if !defined(WIN32)\n#include <unistd.h>\n#define O_BINARY 0\n#else\n#include <io.h>\n#endif\n\n#include <fcntl.h>\n#include <cstring>\n#include <cstdio>\n#include <atomic>\n#include <unordered_map>\n\n#include <cxxrtl/cxxrtl.h>\n#include <cxxrtl/cxxrtl_time.h>\n\n// Theory of operation\n// ===================\n//\n// Log format\n// ----------\n//\n// The replay log is a simple data format based on a sequence of 32-bit words. The following BNF-like grammar describes\n// enough detail to understand the overall structure of the log data and be able to read hex dumps. For a greater\n// degree of detail see the source code. The format is considered fully internal to CXXRTL and is subject to change\n// without notice.\n//\n// <file> ::= <file-header> <definitions> <sample>+\n// <file-header> ::= 0x52585843 0x00004c54\n// <definitions> ::= <packet-define>* <packet-end>\n// <sample> ::= <packet-sample> (<packet-change> | <packet-diag>)* <packet-end>\n// <packet-define> ::= 0xc0000000 ...\n// <packet-sample> ::= 0xc0000001 ...\n// <packet-change> ::= 0x0??????? <chunk>+ | 0x1??????? <index> <chunk>+ | 0x2??????? | 0x3???????\n// <chunk>, <index> ::= 0x????????\n// <packet-diag> ::= <packet-break> | <packet-print> | <packet-assert> | <packet-assume>\n// <packet-break> ::= 0xc0000010 <message> <source-location>\n// <packet-print> ::= 0xc0000011 <message> <source-location>\n// <packet-assert> ::= 0xc0000012 <message> <source-location>\n// <packet-assume> ::= 0xc0000013 <message> <source-location>\n// <packet-end> ::= 0xFFFFFFFF\n//\n// The replay log contains sample data, however, it does not cover the entire design. Rather, it only contains sample\n// data for the subset of debug items containing _design state_: inputs and registers/latches. This keeps its size to\n// a minimum, and recording speed to a maximum. The player samples any missing data by setting the design state items\n// to the same values they had during recording, and re-evaluating the design.\n//\n// Packets for diagnostics (prints, breakpoints, assertions, and assumptions) are used solely for diagnostics emitted\n// by the C++ testbench driving the simulation, and are not recorded while evaluating the design. (Diagnostics emitted\n// by the RTL can be reconstructed at replay time, so recording them would be a waste of space.)\n//\n// Limits\n// ------\n//\n// The log may contain:\n//\n// * Up to 2**28-1 debug items containing design state.\n// * Up to 2**32 chunks per debug item.\n// * Up to 2**32 rows per memory.\n// * Up to 2**32 samples.\n//\n// Of these limits, the last two are most likely to be eventually exceeded by practical recordings. However, other\n// performance considerations will likely limit the size of such practical recordings first, so the log data format\n// will undergo a breaking change at that point.\n//\n// Operations\n// ----------\n//\n// As suggested by the name \"replay log\", this format is designed for recording (writing) once and playing (reading)\n// many times afterwards, such that reading the format can be done linearly and quickly. The log format is designed to\n// support three primary read operations:\n//\n// 1. Initialization\n// 2. Rewinding (to time T)\n// 3. Replaying (for N samples)\n//\n// During initialization, the player establishes the mapping between debug item names and their 28-bit identifiers in\n// the log. It is done once.\n//\n// During rewinding, the player begins reading at the latest non-incremental sample that still lies before the requested\n// sample time. It continues reading incremental samples after that point until it reaches the requested sample time.\n// This process is very cheap as the design is not evaluated; it is essentially a (convoluted) memory copy operation.\n//\n// During replaying, the player evaluates the design at the current time, which causes all debug items to assume\n// the values they had before recording. This process is expensive. Once done, the player advances to the next state\n// by reading the next (complete or incremental) sample, as above. Since a range of samples is replayed, this process\n// is repeated several times in a row.\n//\n// In principle, when replaying, the player could only read the state of the inputs and the time delta and use a normal\n// eval/commit loop to progress the simulation, which is fully deterministic so its calculated design state should be\n// exactly the same as the recorded design state. In practice, it is both faster and more reliable (in presence of e.g.\n// user-defined black boxes) to read the recorded values instead of calculating them.\n//\n// Note: The operations described above are conceptual and do not correspond exactly to methods on `cxxrtl::player`.\n// The `cxxrtl::player::replay()` method does not evaluate the design. This is so that delta cycles could be ignored\n// if they are not of interest while replaying.\n\nnamespace cxxrtl {\n\n// A single diagnostic that can be manipulated as an object (including being written to and read from a file).\n// This differs from the base CXXRTL interface, where diagnostics can only be emitted via a procedure call, and are\n// not materialized as objects.\nstruct diagnostic {\n\t// The `BREAK` flavor corresponds to a breakpoint, which is a diagnostic type that can currently only be emitted\n\t// by the C++ testbench code.\n\tenum flavor {\n\t\tBREAK = 0,\n\t\tPRINT = 1,\n\t\tASSERT = 2,\n\t\tASSUME = 3,\n\t};\n\n\tflavor type;\n\tstd::string message;\n\tstd::string location; // same format as the `src` attribute of `$print` or `$check` cell\n\n\tdiagnostic()\n\t: type(BREAK) {}\n\n\tdiagnostic(flavor type, const std::string &message, const std::string &location)\n\t: type(type), message(message), location(location) {}\n\n\tdiagnostic(flavor type, const std::string &message, const char *file, unsigned line)\n\t: type(type), message(message), location(std::string(file) + ':' + std::to_string(line)) {}\n};\n\n// A spool stores CXXRTL design state changes in a file.\nclass spool {\npublic:\n\t// Unique pointer to a specific sample within a replay log. (Timestamps are not unique.)\n\ttypedef uint32_t pointer_t;\n\n\t// Numeric identifier assigned to a debug item within a replay log. Range limited to [1, MAXIMUM_IDENT].\n\ttypedef uint32_t ident_t;\n\n\tstatic constexpr uint16_t VERSION = 0x0400;\n\n\tstatic constexpr uint64_t HEADER_MAGIC = 0x00004c5452585843;\n\tstatic constexpr uint64_t VERSION_MASK = 0xffff000000000000;\n\n\tstatic constexpr uint32_t PACKET_DEFINE = 0xc0000000;\n\n\tstatic constexpr uint32_t PACKET_SAMPLE = 0xc0000001;\n\tenum sample_flag : uint32_t {\n\t\tEMPTY = 0,\n\t\tINCREMENTAL = 1,\n\t};\n\n\tstatic constexpr uint32_t MAXIMUM_IDENT = 0x0fffffff;\n\tstatic constexpr uint32_t CHANGE_MASK = 0x30000000;\n\n\tstatic constexpr uint32_t PACKET_CHANGE = 0x00000000/* | ident */;\n\tstatic constexpr uint32_t PACKET_CHANGEI = 0x10000000/* | ident */;\n\tstatic constexpr uint32_t PACKET_CHANGEL = 0x20000000/* | ident */;\n\tstatic constexpr uint32_t PACKET_CHANGEH = 0x30000000/* | ident */;\n\n\tstatic constexpr uint32_t PACKET_DIAGNOSTIC = 0xc0000010/* | diagnostic::flavor */;\n\tstatic constexpr uint32_t DIAGNOSTIC_MASK = 0x0000000f;\n\n\tstatic constexpr uint32_t PACKET_END = 0xffffffff;\n\n\t// Writing spools.\n\n\tclass writer {\n\t\tint fd;\n\t\tsize_t position;\n\t\tstd::vector<uint32_t> buffer;\n\n\t\t// These functions aren't overloaded because of implicit numeric conversions.\n\n\t\tvoid emit_word(uint32_t word) {\n\t\t\tif (position + 1 == buffer.size())\n\t\t\t\tflush();\n\t\t\tbuffer[position++] = word;\n\t\t}\n\n\t\tvoid emit_dword(uint64_t dword) {\n\t\t\temit_word(dword >> 0);\n\t\t\temit_word(dword >> 32);\n\t\t}\n\n\t\tvoid emit_ident(ident_t ident) {\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\t\t\temit_word(ident);\n\t\t}\n\n\t\tvoid emit_size(size_t size) {\n\t\t\tassert(size <= std::numeric_limits<uint32_t>::max());\n\t\t\temit_word(size);\n\t\t}\n\n\t\t// Same implementation as `emit_size()`, different declared intent.\n\t\tvoid emit_index(size_t index) {\n\t\t\tassert(index <= std::numeric_limits<uint32_t>::max());\n\t\t\temit_word(index);\n\t\t}\n\n\t\tvoid emit_string(std::string str) {\n\t\t\t// Align to a word boundary, and add at least one terminating \\0.\n\t\t\tstr.resize(str.size() + (sizeof(uint32_t) - (str.size() + sizeof(uint32_t)) % sizeof(uint32_t)));\n\t\t\tfor (size_t index = 0; index < str.size(); index += sizeof(uint32_t)) {\n\t\t\t\tuint32_t word;\n\t\t\t\tmemcpy(&word, &str[index], sizeof(uint32_t));\n\t\t\t\temit_word(word);\n\t\t\t}\n\t\t}\n\n\t\tvoid emit_time(const time ×tamp) {\n\t\t\tconst value<time::bits> &raw_timestamp(timestamp);\n\t\t\temit_word(raw_timestamp.data[0]);\n\t\t\temit_word(raw_timestamp.data[1]);\n\t\t\temit_word(raw_timestamp.data[2]);\n\t\t}\n\n\tpublic:\n\t\t// Creates a writer, and transfers ownership of `fd`, which must be open for appending.\n\t\t//\n\t\t// The buffer size is currently fixed to a \"reasonably large\" size, determined empirically by measuring writer\n\t\t// performance on a representative design; large but not so large it would e.g. cause address space exhaustion\n\t\t// on 32-bit platforms.\n\t\twriter(spool &spool) : fd(spool.take_write()), position(0), buffer(32 * 1024 * 1024) {\n\t\t\tassert(fd != -1);\n#if !defined(WIN32)\n\t\t\tint result = ftruncate(fd, 0);\n#else\n\t\t\tint result = _chsize_s(fd, 0);\n#endif\n\t\t\tassert(result == 0);\n\t\t}\n\n\t\twriter(writer &&moved) : fd(moved.fd), position(moved.position), buffer(moved.buffer) {\n\t\t\tmoved.fd = -1;\n\t\t\tmoved.position = 0;\n\t\t}\n\n\t\twriter(const writer &) = delete;\n\t\twriter &operator=(const writer &) = delete;\n\n\t\t// Both write() calls and fwrite() calls are too expensive to perform implicitly. The API consumer must determine\n\t\t// the optimal time to flush the writer and do that explicitly for best performance.\n\t\tvoid flush() {\n\t\t\tassert(fd != -1);\n\t\t\tsize_t data_size = position * sizeof(uint32_t);\n\t\t\tsize_t data_written = write(fd, buffer.data(), data_size);\n\t\t\tassert(data_size == data_written);\n\t\t\tposition = 0;\n\t\t}\n\n\t\t~writer() {\n\t\t\tif (fd != -1) {\n\t\t\t\tflush();\n\t\t\t\tclose(fd);\n\t\t\t}\n\t\t}\n\n\t\tvoid write_magic() {\n\t\t\t// `CXXRTL` followed by version in binary. This header will read backwards on big-endian machines, which allows\n\t\t\t// detection of this case, both visually and programmatically.\n\t\t\temit_dword(((uint64_t)VERSION << 48) | HEADER_MAGIC);\n\t\t}\n\n\t\tvoid write_define(ident_t ident, const std::string &name, size_t part_index, size_t chunks, size_t depth) {\n\t\t\temit_word(PACKET_DEFINE);\n\t\t\temit_ident(ident);\n\t\t\temit_string(name);\n\t\t\temit_index(part_index);\n\t\t\temit_size(chunks);\n\t\t\temit_size(depth);\n\t\t}\n\n\t\tvoid write_sample(bool incremental, pointer_t pointer, const time ×tamp) {\n\t\t\tuint32_t flags = (incremental ? sample_flag::INCREMENTAL : 0);\n\t\t\temit_word(PACKET_SAMPLE);\n\t\t\temit_word(flags);\n\t\t\temit_word(pointer);\n\t\t\temit_time(timestamp);\n\t\t}\n\n\t\tvoid write_change(ident_t ident, size_t chunks, const chunk_t *data) {\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\n\t\t\tif (chunks == 1 && *data == 0) {\n\t\t\t\temit_word(PACKET_CHANGEL | ident);\n\t\t\t} else if (chunks == 1 && *data == 1) {\n\t\t\t\temit_word(PACKET_CHANGEH | ident);\n\t\t\t} else {\n\t\t\t\temit_word(PACKET_CHANGE | ident);\n\t\t\t\tfor (size_t offset = 0; offset < chunks; offset++)\n\t\t\t\t\temit_word(data[offset]);\n\t\t\t}\n\t\t}\n\n\t\tvoid write_change(ident_t ident, size_t chunks, const chunk_t *data, size_t index) {\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\n\t\t\temit_word(PACKET_CHANGEI | ident);\n\t\t\temit_index(index);\n\t\t\tfor (size_t offset = 0; offset < chunks; offset++)\n\t\t\t\temit_word(data[offset]);\n\t\t}\n\n\t\tvoid write_diagnostic(const diagnostic &diagnostic) {\n\t\t\temit_word(PACKET_DIAGNOSTIC | diagnostic.type);\n\t\t\temit_string(diagnostic.message);\n\t\t\temit_string(diagnostic.location);\n\t\t}\n\n\t\tvoid write_end() {\n\t\t\temit_word(PACKET_END);\n\t\t}\n\t};\n\n\t// Reading spools.\n\n\tclass reader {\n\t\tFILE *f;\n\n\t\tuint32_t absorb_word() {\n\t\t\t// If we're at end of file, `fread` will not write to `word`, and `PACKET_END` will be returned.\n\t\t\tuint32_t word = PACKET_END;\n\t\t\tfread(&word, sizeof(word), 1, f);\n\t\t\treturn word;\n\t\t}\n\n\t\tuint64_t absorb_dword() {\n\t\t\tuint32_t lo = absorb_word();\n\t\t\tuint32_t hi = absorb_word();\n\t\t\treturn ((uint64_t)hi << 32) | lo;\n\t\t}\n\n\t\tident_t absorb_ident() {\n\t\t\tident_t ident = absorb_word();\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\t\t\treturn ident;\n\t\t}\n\n\t\tsize_t absorb_size() {\n\t\t\treturn absorb_word();\n\t\t}\n\n\t\tsize_t absorb_index() {\n\t\t\treturn absorb_word();\n\t\t}\n\n\t\tstd::string absorb_string() {\n\t\t\tstd::string str;\n\t\t\tdo {\n\t\t\t\tsize_t end = str.size();\n\t\t\t\tstr.resize(end + 4);\n\t\t\t\tuint32_t word = absorb_word();\n\t\t\t\tmemcpy(&str[end], &word, sizeof(uint32_t));\n\t\t\t} while (str.back() != '\\0');\n\t\t\t// Strings have no embedded zeroes besides the terminating one(s).\n\t\t\treturn str.substr(0, str.find('\\0'));\n\t\t}\n\n\t\ttime absorb_time() {\n\t\t\tvalue<time::bits> raw_timestamp;\n\t\t\traw_timestamp.data[0] = absorb_word();\n\t\t\traw_timestamp.data[1] = absorb_word();\n\t\t\traw_timestamp.data[2] = absorb_word();\n\t\t\treturn time(raw_timestamp);\n\t\t}\n\n\tpublic:\n\t\ttypedef uint64_t pos_t;\n\n\t\t// Creates a reader, and transfers ownership of `fd`, which must be open for reading.\n\t\treader(spool &spool) : f(fdopen(spool.take_read(), \"r\")) {\n\t\t\tassert(f != nullptr);\n\t\t}\n\n\t\treader(reader &&moved) : f(moved.f) {\n\t\t\tmoved.f = nullptr;\n\t\t}\n\n\t\treader(const reader &) = delete;\n\t\treader &operator=(const reader &) = delete;\n\n\t\t~reader() {\n\t\t\tif (f != nullptr)\n\t\t\t\tfclose(f);\n\t\t}\n\n\t\tpos_t position() {\n\t\t\treturn ftell(f);\n\t\t}\n\n\t\tvoid rewind(pos_t position) {\n\t\t\tfseek(f, position, SEEK_SET);\n\t\t}\n\n\t\tvoid read_magic() {\n\t\t\tuint64_t magic = absorb_dword();\n\t\t\tassert((magic & ~VERSION_MASK) == HEADER_MAGIC);\n\t\t\tassert((magic >> 48) == VERSION);\n\t\t}\n\n\t\tbool read_define(ident_t &ident, std::string &name, size_t &part_index, size_t &chunks, size_t &depth) {\n\t\t\tuint32_t header = absorb_word();\n\t\t\tif (header == PACKET_END)\n\t\t\t\treturn false;\n\t\t\tassert(header == PACKET_DEFINE);\n\t\t\tident = absorb_ident();\n\t\t\tname = absorb_string();\n\t\t\tpart_index = absorb_index();\n\t\t\tchunks = absorb_size();\n\t\t\tdepth = absorb_size();\n\t\t\treturn true;\n\t\t}\n\n\t\tbool read_sample(bool &incremental, pointer_t &pointer, time ×tamp) {\n\t\t\tuint32_t header = absorb_word();\n\t\t\tif (header == PACKET_END)\n\t\t\t\treturn false;\n\t\t\tassert(header == PACKET_SAMPLE);\n\t\t\tuint32_t flags = absorb_word();\n\t\t\tincremental = (flags & sample_flag::INCREMENTAL);\n\t\t\tpointer = absorb_word();\n\t\t\ttimestamp = absorb_time();\n\t\t\treturn true;\n\t\t}\n\n\t\tbool read_header(uint32_t &header) {\n\t\t\theader = absorb_word();\n\t\t\treturn header != PACKET_END;\n\t\t}\n\n\t\t// This method must be separate from `read_change_data` because `chunks` and `depth` can only be looked up\n\t\t// if `ident` is known.\n\t\tbool read_change_ident(uint32_t header, ident_t &ident) {\n\t\t\tif ((header & ~(CHANGE_MASK | MAXIMUM_IDENT)) != 0)\n\t\t\t\treturn false; // some other packet\n\t\t\tident = header & MAXIMUM_IDENT;\n\t\t\treturn true;\n\t\t}\n\n\t\tvoid read_change_data(uint32_t header, size_t chunks, size_t depth, chunk_t *data) {\n\t\t\tuint32_t index = 0;\n\t\t\tswitch (header & CHANGE_MASK) {\n\t\t\t\tcase PACKET_CHANGEL:\n\t\t\t\t\t*data = 0;\n\t\t\t\t\treturn;\n\t\t\t\tcase PACKET_CHANGEH:\n\t\t\t\t\t*data = 1;\n\t\t\t\t\treturn;\n\t\t\t\tcase PACKET_CHANGE:\n\t\t\t\t\tbreak;\n\t\t\t\tcase PACKET_CHANGEI:\n\t\t\t\t\tindex = absorb_word();\n\t\t\t\t\tassert(index < depth);\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tassert(false && \"Unrecognized change packet\");\n\t\t\t}\n\t\t\tfor (size_t offset = 0; offset < chunks; offset++)\n\t\t\t\tdata[chunks * index + offset] = absorb_word();\n\t\t}\n\n\t\tbool read_diagnostic(uint32_t header, diagnostic &diagnostic) {\n\t\t\tif ((header & ~DIAGNOSTIC_MASK) != PACKET_DIAGNOSTIC)\n\t\t\t\treturn false; // some other packet\n\t\t\tuint32_t type = header & DIAGNOSTIC_MASK;\n\t\t\tassert(type == diagnostic::BREAK || type == diagnostic::PRINT ||\n\t\t\t type == diagnostic::ASSERT || type == diagnostic::ASSUME);\n\t\t\tdiagnostic.type = (diagnostic::flavor)type;\n\t\t\tdiagnostic.message = absorb_string();\n\t\t\tdiagnostic.location = absorb_string();\n\t\t\treturn true;\n\t\t}\n\t};\n\n\t// Opening spools. For certain uses of the record/replay mechanism, two distinct open files (two open files, i.e.\n\t// two distinct file pointers, and not just file descriptors, which share the file pointer if duplicated) are used,\n\t// for a reader and writer thread. This class manages the lifetime of the descriptors for these files. When only\n\t// one of them is used, the other is closed harmlessly when the spool is destroyed.\nprivate:\n\tstd::atomic<int> writefd;\n\tstd::atomic<int> readfd;\n\npublic:\n\tspool(const std::string &filename)\n\t\t: writefd(open(filename.c_str(), O_CREAT|O_BINARY|O_WRONLY|O_APPEND, 0644)),\n\t\t readfd(open(filename.c_str(), O_BINARY|O_RDONLY)) {\n\t\tassert(writefd.load() != -1 && readfd.load() != -1);\n\t}\n\n\tspool(spool &&moved) : writefd(moved.writefd.exchange(-1)), readfd(moved.readfd.exchange(-1)) {}\n\n\tspool(const spool &) = delete;\n\tspool &operator=(const spool &) = delete;\n\n\t~spool() {\n\t\tint fd;\n\t\tif ((fd = writefd.exchange(-1)) != -1)\n\t\t\tclose(fd);\n\t\tif ((fd = readfd.exchange(-1)) != -1)\n\t\t\tclose(fd);\n\t}\n\n\t// Atomically acquire a write file descriptor for the spool. Can be called once, and will return -1 the next time\n\t// it is called. Thread-safe.\n\tint take_write() {\n\t\treturn writefd.exchange(-1);\n\t}\n\n\t// Atomically acquire a read file descriptor for the spool. Can be called once, and will return -1 the next time\n\t// it is called. Thread-safe.\n\tint take_read() {\n\t\treturn readfd.exchange(-1);\n\t}\n};\n\n// A CXXRTL recorder samples design state, producing complete or incremental updates, and writes them to a spool.\nclass recorder {\n\tstruct variable {\n\t\tspool::ident_t ident; /* <= spool::MAXIMUM_IDENT */\n\t\tsize_t chunks;\n\t\tsize_t depth; /* == 1 for wires */\n\t\tchunk_t *curr;\n\t\tbool memory;\n\t};\n\n\tspool::writer writer;\n\tstd::vector<variable> variables;\n\tstd::vector<size_t> inputs; // values of inputs must be recorded explicitly, as their changes are not observed\n\tstd::unordered_map<const chunk_t*, spool::ident_t> ident_lookup;\n\tbool streaming = false; // whether variable definitions have been written\n\tspool::pointer_t pointer = 0;\n\ttime timestamp;\n\npublic:\n\ttemplate<typename ...Args>\n\trecorder(Args &&...args) : writer(std::forward<Args>(args)...) {}\n\n\tvoid start(module &module, std::string top_path = \"\") {\n\t\tdebug_items items;\n\t\tmodule.debug_info(&items, /*scopes=*/nullptr, top_path);\n\t\tstart(items);\n\t}\n\n\tvoid start(const debug_items &items) {\n\t\tassert(!streaming);\n\n\t\twriter.write_magic();\n\t\tfor (auto item : items.table)\n\t\t\tfor (size_t part_index = 0; part_index < item.second.size(); part_index++) {\n\t\t\t\tauto &part = item.second[part_index];\n\t\t\t\tif ((part.flags & debug_item::INPUT) || (part.flags & debug_item::DRIVEN_SYNC) ||\n\t\t\t\t\t\t(part.type == debug_item::MEMORY)) {\n\t\t\t\t\tvariable var;\n\t\t\t\t\tvar.ident = variables.size() + 1;\n\t\t\t\t\tvar.chunks = (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8);\n\t\t\t\t\tvar.depth = part.depth;\n\t\t\t\t\tvar.curr = part.curr;\n\t\t\t\t\tvar.memory = (part.type == debug_item::MEMORY);\n\t\t\t\t\tident_lookup[var.curr] = var.ident;\n\n\t\t\t\t\tassert(variables.size() < spool::MAXIMUM_IDENT);\n\t\t\t\t\tif (part.flags & debug_item::INPUT)\n\t\t\t\t\t\tinputs.push_back(variables.size());\n\t\t\t\t\tvariables.push_back(var);\n\n\t\t\t\t\twriter.write_define(var.ident, item.first, part_index, var.chunks, var.depth);\n\t\t\t\t}\n\t\t\t}\n\t\twriter.write_end();\n\t\tstreaming = true;\n\t}\n\n\tconst time &latest_time() {\n\t\treturn timestamp;\n\t}\n\n\tconst time &advance_time(const time &delta) {\n\t\tassert(!delta.is_negative());\n\t\ttimestamp += delta;\n\t\treturn timestamp;\n\t}\n\n\tvoid record_complete() {\n\t\tassert(streaming);\n\n\t\twriter.write_sample(/*incremental=*/false, pointer++, timestamp);\n\t\tfor (auto var : variables) {\n\t\t\tassert(var.ident != 0);\n\t\t\tif (!var.memory)\n\t\t\t\twriter.write_change(var.ident, var.chunks, var.curr);\n\t\t\telse\n\t\t\t\tfor (size_t index = 0; index < var.depth; index++)\n\t\t\t\t\twriter.write_change(var.ident, var.chunks, &var.curr[var.chunks * index], index);\n\t\t}\n\t\twriter.write_end();\n\t}\n\n\t// This function is generic over ModuleT to encourage observer callbacks to be inlined into the commit function.\n\ttemplate<class ModuleT>\n\tbool record_incremental(ModuleT &module) {\n\t\tassert(streaming);\n\n\t\tstruct : observer {\n\t\t\tstd::unordered_map<const chunk_t*, spool::ident_t> *ident_lookup;\n\t\t\tspool::writer *writer;\n\n\t\t\tCXXRTL_ALWAYS_INLINE\n\t\t\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {\n\t\t\t\twriter->write_change(ident_lookup->at(base), chunks, value);\n\t\t\t}\n\n\t\t\tCXXRTL_ALWAYS_INLINE\n\t\t\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {\n\t\t\t\twriter->write_change(ident_lookup->at(base), chunks, value, index);\n\t\t\t}\n\t\t} record_observer;\n\t\trecord_observer.ident_lookup = &ident_lookup;\n\t\trecord_observer.writer = &writer;\n\n\t\twriter.write_sample(/*incremental=*/true, pointer++, timestamp);\n\t\tfor (auto input_index : inputs) {\n\t\t\tvariable &var = variables.at(input_index);\n\t\t\tassert(!var.memory);\n\t\t\twriter.write_change(var.ident, var.chunks, var.curr);\n\t\t}\n\t\tbool changed = module.commit(record_observer);\n\t\twriter.write_end();\n\t\treturn changed;\n\t}\n\n\tvoid record_diagnostic(const diagnostic &diagnostic) {\n\t\tassert(streaming);\n\n\t\t// Emit an incremental delta cycle per diagnostic to simplify the logic of the recorder. This is inefficient, but\n\t\t// diagnostics should be rare enough that this inefficiency does not matter. If it turns out to be an issue, this\n\t\t// code should be changed to accumulate diagnostics to a buffer that is flushed in `record_{complete,incremental}`\n\t\t// and also in `advance_time` before the timestamp is changed. (Right now `advance_time` never writes to the spool.)\n\t\twriter.write_sample(/*incremental=*/true, pointer++, timestamp);\n\t\twriter.write_diagnostic(diagnostic);\n\t\twriter.write_end();\n\t}\n\n\tvoid flush() {\n\t\twriter.flush();\n\t}\n};\n\n// A CXXRTL player reads samples from a spool, and changes the design state accordingly. To start reading samples,\n// a spool must have been initialized: the recorder must have been started and an initial complete sample must have\n// been written.\nclass player {\n\tstruct variable {\n\t\tsize_t chunks;\n\t\tsize_t depth; /* == 1 for wires */\n\t\tchunk_t *curr;\n\t};\n\n\tspool::reader reader;\n\tstd::unordered_map<spool::ident_t, variable> variables;\n\tbool streaming = false; // whether variable definitions have been read\n\tbool initialized = false; // whether a sample has ever been read\n\tspool::pointer_t pointer = 0;\n\ttime timestamp;\n\n\tstd::map<spool::pointer_t, spool::reader::pos_t, std::greater<spool::pointer_t>> index_by_pointer;\n\tstd::map<time, spool::reader::pos_t, std::greater<time>> index_by_timestamp;\n\n\tbool peek_sample(spool::pointer_t &pointer, time ×tamp) {\n\t\tbool incremental;\n\t\tauto position = reader.position();\n\t\tbool success = reader.read_sample(incremental, pointer, timestamp);\n\t\treader.rewind(position);\n\t\treturn success;\n\t}\n\npublic:\n\ttemplate<typename ...Args>\n\tplayer(Args &&...args) : reader(std::forward<Args>(args)...) {}\n\n\t// The `top_path` must match the one given to the recorder.\n\tvoid start(module &module, std::string top_path = \"\") {\n\t\tdebug_items items;\n\t\tmodule.debug_info(&items, /*scopes=*/nullptr, top_path);\n\t\tstart(items);\n\t}\n\n\tvoid start(const debug_items &items) {\n\t\tassert(!streaming);\n\n\t\treader.read_magic();\n\t\twhile (true) {\n\t\t\tspool::ident_t ident;\n\t\t\tstd::string name;\n\t\t\tsize_t part_index;\n\t\t\tsize_t chunks;\n\t\t\tsize_t depth;\n\t\t\tif (!reader.read_define(ident, name, part_index, chunks, depth))\n\t\t\t\tbreak;\n\t\t\tassert(variables.count(ident) == 0);\n\t\t\tassert(items.count(name) != 0);\n\t\t\tassert(part_index < items.count(name));\n\n\t\t\tconst debug_item &part = items.at(name).at(part_index);\n\t\t\tassert(chunks == (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8));\n\t\t\tassert(depth == part.depth);\n\n\t\t\tvariable &var = variables[ident];\n\t\t\tvar.chunks = chunks;\n\t\t\tvar.depth = depth;\n\t\t\tvar.curr = part.curr;\n\t\t}\n\t\tassert(variables.size() > 0);\n\t\tstreaming = true;\n\n\t\t// Establish the initial state of the design.\n\t\tstd::vector<diagnostic> diagnostics;\n\t\tinitialized = replay(&diagnostics);\n\t\tassert(initialized && diagnostics.empty());\n\t}\n\n\t// Returns the pointer of the current sample.\n\tspool::pointer_t current_pointer() {\n\t\tassert(initialized);\n\t\treturn pointer;\n\t}\n\n\t// Returns the time of the current sample.\n\tconst time ¤t_time() {\n\t\tassert(initialized);\n\t\treturn timestamp;\n\t}\n\n\t// Returns `true` if there is a next sample to read, and sets `pointer` to its pointer if there is.\n\tbool get_next_pointer(spool::pointer_t &pointer) {\n\t\tassert(streaming);\n\t\ttime timestamp;\n\t\treturn peek_sample(pointer, timestamp);\n\t}\n\n\t// Returns `true` if there is a next sample to read, and sets `timestamp` to its time if there is.\n\tbool get_next_time(time ×tamp) {\n\t\tassert(streaming);\n\t\tuint32_t pointer;\n\t\treturn peek_sample(pointer, timestamp);\n\t}\n\n\t// If this function returns `true`, then `current_pointer() == at_pointer`, and the module contains values that\n\t// correspond to this pointer in the replay log. To obtain a valid pointer, call `current_pointer()`; while pointers\n\t// are monotonically increasing for each consecutive sample, using arithmetic operations to create a new pointer is\n\t// not allowed. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in this sample.\n\tbool rewind_to(spool::pointer_t at_pointer, std::vector<diagnostic> *diagnostics) {\n\t\tassert(initialized);\n\n\t\t// The pointers in the replay log start from one that is greater than `at_pointer`. In this case the pointer will\n\t\t// never be reached.\n\t\tassert(index_by_pointer.size() > 0);\n\t\tif (at_pointer < index_by_pointer.rbegin()->first)\n\t\t\treturn false;\n\n\t\t// Find the last complete sample whose pointer is less than or equal to `at_pointer`. Note that the comparison\n\t\t// function used here is `std::greater`, inverting the direction of `lower_bound`.\n\t\tauto position_it = index_by_pointer.lower_bound(at_pointer);\n\t\tassert(position_it != index_by_pointer.end());\n\t\treader.rewind(position_it->second);\n\n\t\t// Replay samples until eventually arriving to `at_pointer` or encountering end of file.\n\t\twhile(replay(diagnostics)) {\n\t\t\tif (pointer == at_pointer)\n\t\t\t\treturn true;\n\n\t\t\tif (diagnostics)\n\t\t\t\tdiagnostics->clear();\n\t\t}\n\t\treturn false;\n\t}\n\n\t// If this function returns `true`, then `current_time() <= at_or_before_timestamp`, and the module contains values\n\t// that correspond to `current_time()` in the replay log. If `current_time() == at_or_before_timestamp` and there\n\t// are several consecutive samples with the same time, the module contains values that correspond to the first of\n\t// these samples. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in this sample.\n\tbool rewind_to_or_before(const time &at_or_before_timestamp, std::vector<diagnostic> *diagnostics) {\n\t\tassert(initialized);\n\n\t\t// The timestamps in the replay log start from one that is greater than `at_or_before_timestamp`. In this case\n\t\t// the timestamp will never be reached. Otherwise, this function will always succeed.\n\t\tassert(index_by_timestamp.size() > 0);\n\t\tif (at_or_before_timestamp < index_by_timestamp.rbegin()->first)\n\t\t\treturn false;\n\n\t\t// Find the last complete sample whose timestamp is less than or equal to `at_or_before_timestamp`. Note that\n\t\t// the comparison function used here is `std::greater`, inverting the direction of `lower_bound`.\n\t\tauto position_it = index_by_timestamp.lower_bound(at_or_before_timestamp);\n\t\tassert(position_it != index_by_timestamp.end());\n\t\treader.rewind(position_it->second);\n\n\t\t// Replay samples until eventually arriving to or past `at_or_before_timestamp` or encountering end of file.\n\t\twhile (replay(diagnostics)) {\n\t\t\tif (timestamp == at_or_before_timestamp)\n\t\t\t\tbreak;\n\n\t\t\ttime next_timestamp;\n\t\t\tif (!get_next_time(next_timestamp))\n\t\t\t\tbreak;\n\t\t\tif (next_timestamp > at_or_before_timestamp)\n\t\t\t\tbreak;\n\n\t\t\tif (diagnostics)\n\t\t\t\tdiagnostics->clear();\n\t\t}\n\t\treturn true;\n\t}\n\n\t// If this function returns `true`, then `current_pointer()` and `current_time()` are updated for the next sample\n\t// and the module now contains values that correspond to that sample. If it returns `false`, there was no next sample\n\t// to read. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in the next sample.\n\tbool replay(std::vector<diagnostic> *diagnostics) {\n\t\tassert(streaming);\n\n\t\tbool incremental;\n\t\tauto position = reader.position();\n\t\tif (!reader.read_sample(incremental, pointer, timestamp))\n\t\t\treturn false;\n\n\t\t// The very first sample that is read must be a complete sample. This is required for the rewind functions to work.\n\t\tassert(initialized || !incremental);\n\n\t\t// It is possible (though not very useful) to have several complete samples with the same timestamp in a row.\n\t\t// Ensure that we associate the timestamp with the position of the first such complete sample. (This condition\n\t\t// works because the player never jumps over a sample.)\n\t\tif (!incremental && !index_by_pointer.count(pointer)) {\n\t\t\tassert(!index_by_timestamp.count(timestamp));\n\t\t\tindex_by_pointer[pointer] = position;\n\t\t\tindex_by_timestamp[timestamp] = position;\n\t\t}\n\n\t\tuint32_t header;\n\t\twhile (reader.read_header(header)) {\n\t\t\tspool::ident_t ident;\n\t\t\tdiagnostic diag;\n\t\t\tif (reader.read_change_ident(header, ident)) {\n\t\t\t\tvariable &var = variables.at(ident);\n\t\t\t\treader.read_change_data(header, var.chunks, var.depth, var.curr);\n\t\t\t} else if (reader.read_diagnostic(header, diag)) {\n\t\t\t\tif (diagnostics)\n\t\t\t\t\tdiagnostics->push_back(diag);\n\t\t\t} else assert(false && \"Unrecognized packet header\");\n\t\t}\n\t\treturn true;\n\t}\n};\n\n}\n\n#endif\n",
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"cxxrtl_time.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2023 Catherine <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_TIME_H\n#define CXXRTL_TIME_H\n\n#include <cinttypes>\n#include <string>\n\n#include <cxxrtl/cxxrtl.h>\n\nnamespace cxxrtl {\n\n// A timestamp or a difference in time, stored as a 96-bit number of femtoseconds (10e-15 s). The range and resolution\n// of this format can represent any VCD timestamp within approx. ±1255321.2 years, without the need for a timescale.\nclass time {\npublic:\n\tstatic constexpr size_t bits = 96; // 3 chunks\n\nprivate:\n\tstatic constexpr size_t resolution_digits = 15;\n\n\tstatic_assert(sizeof(chunk_t) == 4, \"a chunk is expected to be 32-bit\");\n\tstatic constexpr value<bits> resolution = value<bits> {\n\t\tchunk_t(1000000000000000ull & 0xffffffffull), chunk_t(1000000000000000ull >> 32), 0u\n\t};\n\n\t// Signed number of femtoseconds from the beginning of time.\n\tvalue<bits> raw;\n\npublic:\n\tconstexpr time() {}\n\n\texplicit constexpr time(const value<bits> &raw) : raw(raw) {}\n\texplicit operator const value<bits> &() const { return raw; }\n\n\tstatic constexpr time maximum() {\n\t\treturn time(value<bits> { 0xffffffffu, 0xffffffffu, 0x7fffffffu });\n\t}\n\n\ttime(int64_t secs, int64_t femtos) {\n\t\tvalue<64> secs_val;\n\t\tsecs_val.set(secs);\n\t\tvalue<64> femtos_val;\n\t\tfemtos_val.set(femtos);\n\t\traw = secs_val.sext<bits>().mul<bits>(resolution).add(femtos_val.sext<bits>());\n\t}\n\n\tbool is_zero() const {\n\t\treturn raw.is_zero();\n\t}\n\n\t// Extracts the sign of the value.\n\tbool is_negative() const {\n\t\treturn raw.is_neg();\n\t}\n\n\t// Extracts the number of whole seconds. Negative if the value is negative.\n\tint64_t secs() const {\n\t\treturn raw.sdivmod(resolution).first.trunc<64>().get<int64_t>();\n\t}\n\n\t// Extracts the number of femtoseconds in the fractional second. Negative if the value is negative.\n\tint64_t femtos() const {\n\t\treturn raw.sdivmod(resolution).second.trunc<64>().get<int64_t>();\n\t}\n\n\tbool operator==(const time &other) const {\n\t\treturn raw == other.raw;\n\t}\n\n\tbool operator!=(const time &other) const {\n\t\treturn raw != other.raw;\n\t}\n\n\tbool operator>(const time &other) const {\n\t\treturn other.raw.scmp(raw);\n\t}\n\n\tbool operator>=(const time &other) const {\n\t\treturn !raw.scmp(other.raw);\n\t}\n\n\tbool operator<(const time &other) const {\n\t\treturn raw.scmp(other.raw);\n\t}\n\n\tbool operator<=(const time &other) const {\n\t\treturn !other.raw.scmp(raw);\n\t}\n\n\ttime operator+(const time &other) const {\n\t\treturn time(raw.add(other.raw));\n\t}\n\n\ttime &operator+=(const time &other) {\n\t\t*this = *this + other;\n\t\treturn *this;\n\t}\n\n\ttime operator-() const {\n\t\treturn time(raw.neg());\n\t}\n\n\ttime operator-(const time &other) const {\n\t\treturn *this + (-other);\n\t}\n\n\ttime &operator-=(const time &other) {\n\t\t*this = *this - other;\n\t\treturn *this;\n\t}\n\n\toperator std::string() const {\n\t\tchar buf[48]; // x=2**95; len(f\"-{x/1_000_000_000_000_000}.{x^1_000_000_000_000_000}\") == 48\n\t\tint64_t secs = this->secs();\n\t\tint64_t femtos = this->femtos();\n\t\tsnprintf(buf, sizeof(buf), \"%s%\" PRIi64 \".%015\" PRIi64,\n\t\t\tis_negative() ? \"-\" : \"\", secs >= 0 ? secs : -secs, femtos >= 0 ? femtos : -femtos);\n\t\treturn buf;\n\t}\n\n#if __cplusplus >= 201603L\n\t[[nodiscard(\"ignoring parse errors\")]]\n#endif\n\tbool parse(const std::string &str) {\n\t\tenum {\n\t\t\tparse_sign_opt,\n\t\t\tparse_integral,\n\t\t\tparse_fractional,\n\t\t} state = parse_sign_opt;\n\t\tbool negative = false;\n\t\tint64_t integral = 0;\n\t\tint64_t fractional = 0;\n\t\tsize_t frac_digits = 0;\n\t\tfor (auto chr : str) {\n\t\t\tswitch (state) {\n\t\t\t\tcase parse_sign_opt:\n\t\t\t\t\tstate = parse_integral;\n\t\t\t\t\tif (chr == '+' || chr == '-') {\n\t\t\t\t\t\tnegative = (chr == '-');\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\t/* fallthrough */\n\t\t\t\tcase parse_integral:\n\t\t\t\t\tif (chr >= '0' && chr <= '9') {\n\t\t\t\t\t\tintegral *= 10;\n\t\t\t\t\t\tintegral += chr - '0';\n\t\t\t\t\t} else if (chr == '.') {\n\t\t\t\t\t\tstate = parse_fractional;\n\t\t\t\t\t} else {\n\t\t\t\t\t\treturn false;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase parse_fractional:\n\t\t\t\t\tif (chr >= '0' && chr <= '9' && frac_digits < resolution_digits) {\n\t\t\t\t\t\tfractional *= 10;\n\t\t\t\t\t\tfractional += chr - '0';\n\t\t\t\t\t\tfrac_digits++;\n\t\t\t\t\t} else {\n\t\t\t\t\t\treturn false;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (frac_digits == 0)\n\t\t\treturn false;\n\t\twhile (frac_digits++ < resolution_digits)\n\t\t\tfractional *= 10;\n\t\t*this = negative ? -time { integral, fractional} : time { integral, fractional };\n\t\treturn true;\n\t}\n};\n\n// Out-of-line definition required until C++17.\nconstexpr value<time::bits> time::resolution;\n\nstd::ostream &operator<<(std::ostream &os, const time &val) {\n\tos << (std::string)val;\n\treturn os;\n}\n\n// These literals are (confusingly) compatible with the ones from `std::chrono`: the `std::chrono` literals do not\n// have an underscore (e.g. 1ms) and the `cxxrtl::time` literals do (e.g. 1_ms). This syntactic difference is\n// a requirement of the C++ standard. Despite being compatible the literals should not be mixed in the same namespace.\nnamespace time_literals {\n\ntime operator\"\"_s(unsigned long long seconds) {\n\treturn time { (int64_t)seconds, 0 };\n}\n\ntime operator\"\"_ms(unsigned long long milliseconds) {\n\treturn time { 0, (int64_t)milliseconds * 1000000000000 };\n}\n\ntime operator\"\"_us(unsigned long long microseconds) {\n\treturn time { 0, (int64_t)microseconds * 1000000000 };\n}\n\ntime operator\"\"_ns(unsigned long long nanoseconds) {\n\treturn time { 0, (int64_t)nanoseconds * 1000000 };\n}\n\ntime operator\"\"_ps(unsigned long long picoseconds) {\n\treturn time { 0, (int64_t)picoseconds * 1000 };\n}\n\ntime operator\"\"_fs(unsigned long long femtoseconds) {\n\treturn time { 0, (int64_t)femtoseconds };\n}\n\n};\n\n};\n\n#endif\n",
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"cxxrtl_vcd.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_VCD_H\n#define CXXRTL_VCD_H\n\n#include <cxxrtl/cxxrtl.h>\n\nnamespace cxxrtl {\n\nclass vcd_writer {\n\tstruct variable {\n\t\tsize_t ident;\n\t\tsize_t width;\n\t\tchunk_t *curr;\n\t\tsize_t cache_offset;\n\t\tdebug_outline *outline;\n\t\tbool *outline_warm;\n\t};\n\n\tstd::vector<std::string> current_scope;\n\tstd::map<debug_outline*, bool> outlines;\n\tstd::vector<variable> variables;\n\tstd::vector<chunk_t> cache;\n\tstd::map<chunk_t*, size_t> aliases;\n\tbool streaming = false;\n\n\tvoid emit_timescale(unsigned number, const std::string &unit) {\n\t\tassert(!streaming);\n\t\tassert(number == 1 || number == 10 || number == 100);\n\t\tassert(unit == \"s\" || unit == \"ms\" || unit == \"us\" ||\n\t\t unit == \"ns\" || unit == \"ps\" || unit == \"fs\");\n\t\tbuffer += \"$timescale \" + std::to_string(number) + \" \" + unit + \" $end\\n\";\n\t}\n\n\tvoid emit_scope(const std::vector<std::string> &scope) {\n\t\tassert(!streaming);\n\t\tsize_t same_scope_count = 0;\n\t\twhile ((same_scope_count < current_scope.size()) &&\n\t\t\t (same_scope_count < scope.size()) &&\n\t\t\t (current_scope[same_scope_count] == scope[same_scope_count])) {\n\t\t\tsame_scope_count++;\n\t\t}\n\t\twhile (current_scope.size() > same_scope_count) {\n\t\t\tbuffer += \"$upscope $end\\n\";\n\t\t\tcurrent_scope.pop_back();\n\t\t}\n\t\twhile (current_scope.size() < scope.size()) {\n\t\t\tbuffer += \"$scope module \" + scope[current_scope.size()] + \" $end\\n\";\n\t\t\tcurrent_scope.push_back(scope[current_scope.size()]);\n\t\t}\n\t}\n\n\tvoid emit_ident(size_t ident) {\n\t\tdo {\n\t\t\tbuffer += '!' + ident % 94; // \"base94\"\n\t\t\tident /= 94;\n\t\t} while (ident != 0);\n\t}\n\n\tvoid emit_name(const std::string &name) {\n\t\tfor (char c : name) {\n\t\t\tif (c == ':') {\n\t\t\t\t// Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file\n\t\t\t\t// to be unreadable. It cannot be escaped either, so replace it with the sideways colon.\n\t\t\t\tbuffer += \"..\";\n\t\t\t} else {\n\t\t\t\tbuffer += c;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid emit_var(const variable &var, const std::string &type, const std::string &name,\n\t size_t lsb_at, bool multipart) {\n\t\tassert(!streaming);\n\t\tbuffer += \"$var \" + type + \" \" + std::to_string(var.width) + \" \";\n\t\temit_ident(var.ident);\n\t\tbuffer += \" \";\n\t\temit_name(name);\n\t\tif (multipart || name.back() == ']' || lsb_at != 0) {\n\t\t\tif (var.width == 1)\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at) + \"]\";\n\t\t\telse\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at + var.width - 1) + \":\" + std::to_string(lsb_at) + \"]\";\n\t\t}\n\t\tbuffer += \" $end\\n\";\n\t}\n\n\tvoid emit_enddefinitions() {\n\t\tassert(!streaming);\n\t\tbuffer += \"$enddefinitions $end\\n\";\n\t\tstreaming = true;\n\t}\n\n\tvoid emit_time(uint64_t timestamp) {\n\t\tassert(streaming);\n\t\tbuffer += \"#\" + std::to_string(timestamp) + \"\\n\";\n\t}\n\n\tvoid emit_scalar(const variable &var) {\n\t\tassert(streaming);\n\t\tassert(var.width == 1);\n\t\tbuffer += (*var.curr ? '1' : '0');\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid emit_vector(const variable &var) {\n\t\tassert(streaming);\n\t\tbuffer += 'b';\n\t\tfor (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {\n\t\t\tbool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));\n\t\t\tbuffer += (bit_curr ? '1' : '0');\n\t\t}\n\t\tif (var.width == 0)\n\t\t\tbuffer += '0';\n\t\tbuffer += ' ';\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid reset_outlines() {\n\t\tfor (auto &outline_it : outlines)\n\t\t\toutline_it.second = /*warm=*/(outline_it.first == nullptr);\n\t}\n\n\tvariable ®ister_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) {\n\t\tif (aliases.count(curr)) {\n\t\t\treturn variables[aliases[curr]];\n\t\t} else {\n\t\t\tauto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first;\n\t\t\tconst size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\taliases[curr] = variables.size();\n\t\t\tif (constant) {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second });\n\t\t\t} else {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second });\n\t\t\t\tcache.insert(cache.end(), &curr[0], &curr[chunks]);\n\t\t\t}\n\t\t\treturn variables.back();\n\t\t}\n\t}\n\n\tbool test_variable(const variable &var) {\n\t\tif (var.cache_offset == (size_t)-1)\n\t\t\treturn false; // constant\n\t\tif (!*var.outline_warm) {\n\t\t\tvar.outline->eval();\n\t\t\t*var.outline_warm = true;\n\t\t}\n\t\tconst size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\tif (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) {\n\t\t\treturn false;\n\t\t} else {\n\t\t\tstd::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]);\n\t\t\treturn true;\n\t\t}\n\t}\n\n\tstatic std::vector<std::string> split_hierarchy(const std::string &hier_name) {\n\t\tstd::vector<std::string> hierarchy;\n\t\tsize_t prev = 0;\n\t\twhile (true) {\n\t\t\tsize_t curr = hier_name.find_first_of(' ', prev);\n\t\t\tif (curr == std::string::npos) {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev));\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev, curr - prev));\n\t\t\t\tprev = curr + 1;\n\t\t\t}\n\t\t}\n\t\treturn hierarchy;\n\t}\n\npublic:\n\tstd::string buffer;\n\n\tvoid timescale(unsigned number, const std::string &unit) {\n\t\temit_timescale(number, unit);\n\t}\n\n\tvoid add(const std::string &hier_name, const debug_item &item, bool multipart = false) {\n\t\tstd::vector<std::string> scope = split_hierarchy(hier_name);\n\t\tstd::string name = scope.back();\n\t\tscope.pop_back();\n\n\t\temit_scope(scope);\n\t\tswitch (item.type) {\n\t\t\t// Not the best naming but oh well...\n\t\t\tcase debug_item::VALUE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::WIRE:\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"reg\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::MEMORY: {\n\t\t\t\tconst size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\t\tfor (size_t index = 0; index < item.depth; index++) {\n\t\t\t\t\tchunk_t *nth_curr = &item.curr[stride * index];\n\t\t\t\t\tstd::string nth_name = name + '[' + std::to_string(index) + ']';\n\t\t\t\t\temit_var(register_variable(item.width, nth_curr),\n\t\t\t\t\t \"reg\", nth_name, item.lsb_at, multipart);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase debug_item::ALIAS:\n\t\t\t\t// Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value\n\t\t\t\t// can actually change, and must be tracked. In most cases the VCD identifier will be\n\t\t\t\t// unified with the aliased reg, but we should handle the case where only the alias is\n\t\t\t\t// added to the VCD writer, too.\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::OUTLINE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\ttemplate<class Filter>\n\tvoid add(const debug_items &items, const Filter &filter) {\n\t\t// `debug_items` is a map, so the items are already sorted in an order optimal for emitting\n\t\t// VCD scope sections.\n\t\tfor (auto &it : items.table)\n\t\t\tfor (auto &part : it.second)\n\t\t\t\tif (filter(it.first, part))\n\t\t\t\t\tadd(it.first, part, it.second.size() > 1);\n\t}\n\n\tvoid add(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &) {\n\t\t\treturn true;\n\t\t});\n\t}\n\n\tvoid add_without_memories(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &item) {\n\t\t\treturn item.type != debug_item::MEMORY;\n\t\t});\n\t}\n\n\tvoid sample(uint64_t timestamp) {\n\t\tbool first_sample = !streaming;\n\t\tif (first_sample) {\n\t\t\temit_scope({});\n\t\t\temit_enddefinitions();\n\t\t}\n\t\treset_outlines();\n\t\temit_time(timestamp);\n\t\tfor (auto var : variables)\n\t\t\tif (test_variable(var) || first_sample) {\n\t\t\t\tif (var.width == 1)\n\t\t\t\t\temit_scalar(var);\n\t\t\t\telse\n\t\t\t\t\temit_vector(var);\n\t\t\t}\n\t}\n};\n\n}\n\n#endif\n",
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@@ -164,8 +164,8 @@ export const filesystem = {
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"cellaigs.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLAIGS_H\n#define CELLAIGS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AigNode\n{\n\tIdString portname;\n\tint portbit;\n\tbool inverter;\n\tint left_parent, right_parent;\n\tvector<pair<IdString, int>> outports;\n\n\tAigNode();\n\tbool operator==(const AigNode &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct Aig\n{\n\tstring name;\n\tvector<AigNode> nodes;\n\tAig(Cell *cell);\n\n\tbool operator==(const Aig &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"celledges.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLEDGES_H\n#define CELLEDGES_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AbstractCellEdgesDatabase\n{\n\tvirtual ~AbstractCellEdgesDatabase() { }\n\tvirtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;\n\tbool add_edges_from_cell(RTLIL::Cell *cell);\n};\n\nstruct FwdCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tFwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[from_sigbit].insert(to_sigbit);\n\t}\n};\n\nstruct RevCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tRevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[to_sigbit].insert(from_sigbit);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"celltypes.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n\tbool is_combinatorial;\n\tbool is_synthesizable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($buf), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits())\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type.in(ID($_BUF_), ID($buf)))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"consteval.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits()[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).to_bits();\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> slave_bits = y_values.at(i).to_bits();\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits()[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type.in(ID($macc), ID($macc_v2)))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tfor (auto &port : macc.ports) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(chain)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\nX(area)\nX(capacitance)\nX(NPRODUCTS)\nX(NADDENDS)\nX(PRODUCT_NEGATED)\nX(ADDEND_NEGATED)\nX(A_WIDTHS)\nX(B_WIDTHS)\nX(C_WIDTHS)\nX(C_SIGNED)\n",
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"consteval.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits()[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).to_bits();\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> slave_bits = y_values.at(i).to_bits();\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits()[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type.in(ID($macc), ID($macc_v2)))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tfor (auto &port : macc.terms) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(chain)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(promoted_if)\nX(Q)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(single_bit_vector)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\nX(area)\nX(capacitance)\nX(NPRODUCTS)\nX(NADDENDS)\nX(PRODUCT_NEGATED)\nX(ADDEND_NEGATED)\nX(A_WIDTHS)\nX(B_WIDTHS)\nX(C_WIDTHS)\nX(C_SIGNED)\n",
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"cost.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef COST_H\n#define COST_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellCosts\n{\n\n\tprivate:\n\tdict<RTLIL::IdString, int> mod_cost_cache_;\n\tDesign *design_ = nullptr;\n\n\tpublic:\n\tCellCosts(RTLIL::Design *design) : design_(design) { }\n\n\tstatic const dict<RTLIL::IdString, int>& default_gate_cost() {\n\t\t// Default size heuristics for several common PDK standard cells\n\t\t// used by abc and stat\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 4 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 4 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 4 },\n\t\t\t{ ID($_ORNOT_), 4 },\n\t\t\t{ ID($_XOR_), 5 },\n\t\t\t{ ID($_XNOR_), 5 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 7 },\n\t\t\t{ ID($_OAI4_), 7 },\n\t\t\t{ ID($_MUX_), 4 },\n\t\t\t{ ID($_NMUX_), 4 },\n\t\t};\n\t\treturn db;\n\t}\n\n\tstatic const dict<RTLIL::IdString, int>& cmos_gate_cost() {\n\t\t// Estimated CMOS transistor counts for several common PDK standard cells\n\t\t// used by stat and optionally by abc\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 6 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 6 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 6 },\n\t\t\t{ ID($_ORNOT_), 6 },\n\t\t\t{ ID($_XOR_), 12 },\n\t\t\t{ ID($_XNOR_), 12 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 8 },\n\t\t\t{ ID($_OAI4_), 8 },\n\t\t\t{ ID($_MUX_), 12 },\n\t\t\t{ ID($_NMUX_), 10 },\n\t\t\t{ ID($_DFF_P_), 16 },\n\t\t\t{ ID($_DFF_N_), 16 },\n\t\t};\n\t\treturn db;\n\t}\n\n\t// Get the cell cost for a cell based on its parameters.\n\t// This cost is an *approximate* upper bound for the number of gates that\n\t// the cell will get mapped to with \"opt -fast; techmap\"\n\t// The intended usage is for flattening heuristics and similar situations\n\tunsigned int get(RTLIL::Cell *cell);\n\t// Sum up the cell costs of all cells in the module\n\t// and all its submodules recursively\n\tunsigned int get(RTLIL::Module *mod);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"drivertools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef DRIVERTOOLS_H\n#define DRIVERTOOLS_H\n\n#include <type_traits>\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// TODO move implementation into a .cc file\n\nstruct DriveBit;\n\nstruct DriveChunkWire;\nstruct DriveChunkPort;\nstruct DriveChunkMarker;\nstruct DriveChunk;\n\nstruct DriveSpec;\n\nconst char *log_signal(DriveChunkWire const &chunk);\nconst char *log_signal(DriveChunkPort const &chunk);\nconst char *log_signal(DriveChunkMarker const &chunk);\nconst char *log_signal(DriveChunk const &chunk);\nconst char *log_signal(DriveSpec const &chunk);\n\nenum class DriveType : unsigned char\n{\n\tNONE,\n\tCONSTANT,\n\tWIRE,\n\tPORT,\n\tMULTIPLE,\n\tMARKER,\n};\n\nstruct DriveBitWire\n{\n\tWire *wire;\n\tint offset;\n\n\tDriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {}\n\n\tbool operator==(const DriveBitWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\n\toperator SigBit() const\n\t{\n\t\treturn SigBit(wire, offset);\n\t}\n};\n\nstruct DriveBitPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\n\tDriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {}\n\n\tbool operator==(const DriveBitPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n};\n\n\nstruct DriveBitMarker\n{\n\tint marker;\n\tint offset;\n\n\tDriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {}\n\n\tbool operator==(const DriveBitMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n};\n\nstruct DriveBitMultiple\n{\nprivate:\n\tpool<DriveBit> multiple_;\n\npublic:\n\tDriveBitMultiple();\n\tDriveBitMultiple(DriveBit const &single);\n\n\tpool<DriveBit> const &multiple() const { return multiple_; }\n\n\tvoid merge(DriveBitMultiple const &other)\n\t{\n\t\tfor (DriveBit const &single : other.multiple_)\n\t\t\tmerge(single);\n\t}\n\n\tvoid merge(DriveBitMultiple &&other)\n\t{\n\t\tfor (DriveBit &single : other.multiple_)\n\t\t\tmerge(std::move(single));\n\t}\n\n\tvoid merge(DriveBit const &single);\n\tvoid merge(DriveBit &&single);\n\n\tbool operator==(const DriveBitMultiple &other) const\n\t{\n\t\treturn multiple_ == other.multiple_;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct DriveBit\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tState constant_;\n\t\tDriveBitWire wire_;\n\t\tDriveBitPort port_;\n\t\tDriveBitMarker marker_;\n\t\tDriveBitMultiple multiple_;\n\t};\npublic:\n\tDriveBit() {}\n\n\tDriveBit(SigBit const &bit);\n\n\tDriveBit(DriveBit const &other) { *this = other; }\n\tDriveBit(DriveBit &&other) { *this = other; }\n\n\n\tDriveBit(State constant) { *this = constant; }\n\tDriveBit(DriveBitWire const &wire) { *this = wire; }\n\tDriveBit(DriveBitWire &&wire) { *this = wire; }\n\tDriveBit(DriveBitPort const &port) { *this = port; }\n\tDriveBit(DriveBitPort &&port) { *this = port; }\n\tDriveBit(DriveBitMarker const &marker) { *this = marker; }\n\tDriveBit(DriveBitMarker &&marker) { *this = marker; }\n\tDriveBit(DriveBitMultiple const &multiple) { *this = multiple; }\n\tDriveBit(DriveBitMultiple &&multiple) { *this = multiple; }\n\n\t~DriveBit() { set_none(); }\n\n\tvoid set_none()\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveBitWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveBitPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveBitMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveBitMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t}\n\n\tDriveBit &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBit &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(State constant)\n\t{\n\t\tset_none();\n\t\tconstant_ = constant;\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple const &multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple &&multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\tbool operator==(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveBit &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tlog_assert(!\"TODO\");\n\t\t}\n\t\tlog_abort();\n\t}\n\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tState &constant() { log_assert(is_constant()); return constant_; }\n\tState const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveBitWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveBitWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveBitPort &port() { log_assert(is_port()); return port_; }\n\tDriveBitPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveBitMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\tvoid merge(DriveBit const &other);\n\n};\n\ninline DriveBitMultiple::DriveBitMultiple() {}\ninline DriveBitMultiple::DriveBitMultiple(DriveBit const &single)\n{\n\tmultiple_.emplace(single);\n}\n\nstruct DriveChunkWire\n{\n\tWire *wire;\n\tint offset;\n\tint width;\n\n\tDriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {}\n\tDriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitWire operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitWire(wire, offset + i);\n\t}\n\n\tbool can_append(DriveBitWire const &bit) const;\n\tbool try_append(DriveBitWire const &bit);\n\tbool try_append(DriveChunkWire const &chunk);\n\n\t// Whether this chunk is a whole wire\n\tbool is_whole() const { return offset == 0 && width == wire->width; }\n\n\tbool operator==(const DriveChunkWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\texplicit operator SigChunk() const\n\t{\n\t\treturn SigChunk(wire, offset, width);\n\t}\n};\n\nstruct DriveChunkPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\tint width;\n\n\tDriveChunkPort(Cell *cell, IdString port, int offset, int width) :\n\t\tcell(cell), port(port), offset(offset), width(width) { }\n\tDriveChunkPort(Cell *cell, IdString port) :\n\t\tcell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { }\n\tDriveChunkPort(Cell *cell, std::pair<IdString, SigSpec> const &conn) :\n\t\tcell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { }\n\tDriveChunkPort(DriveBitPort const &bit) :\n\t\tcell(bit.cell), port(bit.port), offset(bit.offset), width(1) { }\n\n\tint size() const { return width; }\n\n\tDriveBitPort operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitPort(cell, port, offset + i);\n\t}\n\n\tbool can_append(DriveBitPort const &bit) const;\n\tbool try_append(DriveBitPort const &bit);\n\tbool try_append(DriveChunkPort const &chunk);\n\n\t// Whether this chunk is a whole port\n\tbool is_whole() const\n\t{\n\t\treturn offset == 0 && width == cell->connections().at(port).size();\n\t}\n\n\tbool operator==(const DriveChunkPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\n\nstruct DriveChunkMarker\n{\n\tint marker;\n\tint offset;\n\tint width;\n\n\tDriveChunkMarker(int marker, int offset, int width) :\n\t\tmarker(marker), offset(offset), width(width) {}\n\tDriveChunkMarker(DriveBitMarker const &bit) :\n\t\tmarker(bit.marker), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitMarker operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitMarker(marker, offset + i);\n\t}\n\n\tbool can_append(DriveBitMarker const &bit) const;\n\tbool try_append(DriveBitMarker const &bit);\n\tbool try_append(DriveChunkMarker const &chunk);\n\n\tbool operator==(const DriveChunkMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct DriveChunkMultiple\n{\nprivate:\n\tmutable pool<DriveChunk> multiple_;\n\tint width_;\n\npublic:\n\tpool<DriveChunk> const &multiple() const { return multiple_; }\n\n\tDriveChunkMultiple(DriveBitMultiple const &bit);\n\n\tint size() const { return width_; }\n\n\tDriveBitMultiple operator[](int i) const;\n\n\tbool can_append(DriveBitMultiple const &bit) const;\n\n\tbool try_append(DriveBitMultiple const &bit);\n\n\n\tbool can_append(DriveChunkMultiple const &bit) const;\n\n\tbool try_append(DriveChunkMultiple const &bit);\n\n\tbool operator==(const DriveChunkMultiple &other) const\n\t{\n\t\treturn width_ == other.width_ && multiple_ == other.multiple_;\n\t}\n\n\tbool operator<(const DriveChunkMultiple &other) const\n\t{\n\t\tif (multiple_.size() < other.multiple_.size())\n\n\t\tmultiple_.sort();\n\t\treturn false; // TODO implement, canonicalize order\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct DriveChunk\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tint none_;\n\t\tConst constant_;\n\t\tDriveChunkWire wire_;\n\t\tDriveChunkPort port_;\n\t\tDriveChunkMarker marker_;\n\t\tDriveChunkMultiple multiple_;\n\t};\n\npublic:\n\tDriveChunk() { set_none(); }\n\n\tDriveChunk(DriveChunk const &other) { *this = other; }\n\tDriveChunk(DriveChunk &&other) { *this = other; }\n\n\tDriveChunk(DriveBit const &other) { *this = other; }\n\n\tDriveChunk(Const const &constant) { *this = constant; }\n\tDriveChunk(Const &&constant) { *this = constant; }\n\tDriveChunk(DriveChunkWire const &wire) { *this = wire; }\n\tDriveChunk(DriveChunkWire &&wire) { *this = wire; }\n\tDriveChunk(DriveChunkPort const &port) { *this = port; }\n\tDriveChunk(DriveChunkPort &&port) { *this = port; }\n\tDriveChunk(DriveChunkMarker const &marker) { *this = marker; }\n\tDriveChunk(DriveChunkMarker &&marker) { *this = marker; }\n\tDriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; }\n\tDriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; }\n\n\t~DriveChunk() { set_none(); }\n\n\tDriveBit operator[](int i) const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn DriveBit();\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_[i];\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_[i];\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_[i];\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_[i];\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_[i];\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tvoid set_none(int width = 0)\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tnone_ = width;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tconstant_.~Const();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveChunkWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveChunkPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveChunkMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveChunkMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t\tnone_ = width;\n\t}\n\n\tDriveChunk &operator=(DriveChunk const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunk &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const const &constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(constant);\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const &&constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(std::move(constant));\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple const &multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple &&multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type())\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(1);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = Const(other.constant());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = DriveChunkWire(other.wire());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = DriveChunkPort(other.port());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = DriveChunkMarker(other.marker());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = DriveChunkMultiple(other.multiple());\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tbool can_append(DriveBit const &bit) const;\n\tbool try_append(DriveBit const &bit);\n\tbool try_append(DriveChunk const &chunk);\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\tbool operator==(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveChunk &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ < other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tConst &constant() { log_assert(is_constant()); return constant_; }\n\tConst const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveChunkWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveChunkPort &port() { log_assert(is_port()); return port_; }\n\tDriveChunkPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveChunkMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\n\tint size() const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn none_;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_.size();\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_.size();\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_.size();\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_.size();\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_.size();\n\t\t}\n\t\tlog_abort();\n\t}\n};\n\ninline DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit)\n\t: width_(1)\n{\n\tfor (auto const &bit : bit.multiple())\n\t\tmultiple_.emplace(bit);\n}\n\nstruct DriveSpec\n{\nprivate:\n\tint width_ = 0;\n\tmutable std::vector<DriveChunk> chunks_;\n\tmutable std::vector<DriveBit> bits_;\n\tmutable unsigned int hash_ = 0;\npublic:\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tDriveSpec() {}\n\n\tDriveSpec(DriveChunk const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkWire const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkPort const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMarker const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; }\n\n\tDriveSpec(DriveBit const &bit) { *this = bit; }\n\tDriveSpec(DriveBitWire const &bit) { *this = bit; }\n\tDriveSpec(DriveBitPort const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMarker const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMultiple const &bit) { *this = bit; }\n\n\tDriveSpec(std::vector<DriveChunk> const &chunks) : chunks_(chunks) { compute_width(); }\n\n\tDriveSpec(std::vector<DriveBit> const &bits)\n\t{\n\t\tfor (auto const &bit : bits)\n\t\t\tappend(bit);\n\t}\n\n\tDriveSpec(SigSpec const &sig)\n\t{\n\t\t// TODO: converting one chunk at a time would be faster\n\t\tfor (auto const &bit : sig.bits())\n\t\t\tappend(bit);\n\t}\n\n\tstd::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }\n\tstd::vector<DriveBit> const &bits() const { unpack(); return bits_; }\n\n\tint size() const { return width_; }\n\n\tvoid append(DriveBit const &bit);\n\n\tvoid append(DriveChunk const &chunk);\n\n\tvoid pack() const;\n\n\tvoid unpack() const;\n\n\tDriveBit &operator[](int index)\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tconst DriveBit &operator[](int index) const\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tvoid clear()\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\twidth_ = 0;\n\t}\n\n\tDriveSpec &operator=(DriveChunk const &chunk)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(chunk);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); }\n\n\tDriveSpec &operator=(DriveBit const &bit)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(bit);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); }\n\n\tvoid updhash() const {\n\t\tif (hash_ != 0)\n\t\t\treturn;\n\t\tpack();\n\t\thash_ = run_hash(chunks_);\n\t\thash_ |= (hash_ == 0);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\tbool operator==(DriveSpec const &other) const {\n\t\tupdhash();\n\t\tother.updhash();\n\t\tif (size() != other.size() || hash_ != other.hash_)\n\t\t\treturn false;\n\t\treturn chunks() == other.chunks();\n\t}\n\nprivate:\n\tvoid compute_width();\n};\n\n\n\nstruct DriverMap\n{\n\tCellTypes celltypes;\n\n\tDriverMap() { celltypes.setup(); }\n\tDriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); }\n\nprivate:\n\n\t// Internally we represent all DriveBits by mapping them to DriveBitIds\n\t// which use less memory and are cheaper to compare.\n\tstruct DriveBitId\n\t{\n\t\tint id = -1;\n\n\t\tDriveBitId() {};\n\n\t\tDriveBitId(int id) : id(id) { }\n\n\t\tbool operator==(const DriveBitId &other) const { return id == other.id; }\n\t\tbool operator!=(const DriveBitId &other) const { return id != other.id; }\n\t\tbool operator<(const DriveBitId &other) const { return id < other.id; }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t};\n\t// Essentially a dict<DriveBitId, pool<DriveBitId>> but using less memory\n\t// and fewer allocations\n\tstruct DriveBitGraph {\n\t\tdict<DriveBitId, DriveBitId> first_edges;\n\t\tdict<DriveBitId, DriveBitId> second_edges;\n\t\tdict<DriveBitId, pool<DriveBitId>> more_edges;\n\n\t\tvoid add_edge(DriveBitId src, DriveBitId dst);\n\t\tDriveBitId pop_edge(DriveBitId src);\n\t\tvoid clear(DriveBitId src);\n\t\tbool contains(DriveBitId src);\n\t\tint count(DriveBitId src);\n\n\t\tDriveBitId at(DriveBitId src, int index);\n\t};\n\n\t// The following two maps maintain a sparse DriveBit to DriveBitId mapping.\n\t// This saves a lot of memory compared to a `dict<DriveBit, DriveBitId>` or\n\t// `idict<DriveBit>`.\n\n\t// Maps wires to the first DriveBitId of the consecutive range used for\n\t// that wire.\n\tdict<Wire *, DriveBitId> wire_offsets;\n\n\t// Maps cell ports to a the first DriveBitId of the consecutive range used\n\t// for that cell port.\n\tdict<pair<Cell *, IdString>, DriveBitId> port_offsets;\n\n\t// For the inverse map that maps DriveBitIds back to DriveBits we use a\n\t// sorted map containing only the first DriveBit for each wire and cell\n\t// port.\n\tstd::map<DriveBitId, DriveBit> drive_bits;\n\n\t// As a memory optimization for gate level net lists we store single-bit\n\t// wires and cell ports in a `dict` which requires less memory and fewer\n\t// allocations than `std::map` but doesn't support the kind of lookups we\n\t// need for a sparse coarse grained mapping.\n\tdict<DriveBitId, DriveBit> isolated_drive_bits;\n\n\t// Used for allocating DriveBitIds, none and constant states use a fixewd\n\t// mapping to the first few ids, which we need to skip.\n\tint next_offset = 1 + (int)State::Sm;\n\n\t// Union-Find over directly connected bits that share the same single\n\t// driver or are undriven. We never merge connections between drivers\n\t// and/or kept wires.\n\tmfp<DriveBitId> same_driver;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally unambiguous (one side only drives or requires a driven value).\n\tDriveBitGraph connected_drivers;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally ambiguous. Every such ambiguous connection is also present in\n\t// the reverse direction and has to be resolved when querying drivers.\n\tDriveBitGraph connected_undirected;\n\n\t// Subset of `connected_undirected` for caching the resolved driving\n\t// direction. In case multiple drivers are present this can still contain\n\t// both orientations of a single connection, but for a single driver only\n\t// one will be present.\n\tDriveBitGraph connected_oriented;\n\n\t// Stores for which bits we already resolved the orientation (cached in\n\t// `connected_oriented`).\n\tpool<DriveBitId> oriented_present;\n\n\n\tenum class BitMode {\n\t\tNONE = 0, // Not driven, no need to keep wire\n\t\tDRIVEN = 1, // Not driven, uses a value driven elsewhere\n\t\tDRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection\n\t\tKEEP = 3, // Wire that should be kept\n\t\tTRISTATE = 4, // Can drive a value but can also use a value driven elsewhere\n\t\tDRIVER = 5, // Drives a value\n\t};\n\n\tBitMode bit_mode(DriveBit const &bit);\n\tDriveBitId id_from_drive_bit(DriveBit const &bit);\n\tDriveBit drive_bit_from_id(DriveBitId id);\n\n\tvoid connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_undirected(DriveBitId a_id, DriveBitId b_id);\n\npublic:\n\n\tvoid add(Module *module);\n\n\t// Add a single bit connection to the driver map.\n\tvoid add(DriveBit const &a, DriveBit const &b);\n\n\ttemplate<typename T>\n\tstatic constexpr bool is_sig_type() {\n\t\treturn\n\t\t\tstd::is_same<T, SigSpec>::value ||\n\t\t\tstd::is_same<T, SigChunk>::value ||\n\t\t\tstd::is_same<T, DriveSpec>::value ||\n\t\t\tstd::is_same<T, DriveChunk>::value ||\n\t\t\tstd::is_same<T, DriveChunkPort>::value ||\n\t\t\tstd::is_same<T, DriveChunkWire>::value ||\n\t\t\tstd::is_same<T, Const>::value;\n\t}\n\n\t// We use the enable_if to produce better compiler errors when unsupported\n\t// types are used\n\ttemplate<typename T, typename U>\n\ttypename std::enable_if<is_sig_type<T>() && is_sig_type<U>()>::type\n\tadd(T const &a, U const &b)\n\t{\n\t\tlog_assert(a.size() == b.size());\n\t\tfor (int i = 0; i != GetSize(a); ++i)\n\t\t\tadd(DriveBit(a[i]), DriveBit(b[i]));\n\t}\n\n\n\t// Specialized version that avoids unpacking\n\tvoid add(SigSpec const &a, SigSpec const &b);\n\nprivate:\n\tvoid add_port(Cell *cell, IdString const &port, SigSpec const &b);\n\n\t// Only used a local variables in `orient_undirected`, always cleared, only\n\t// stored to reduce allocations.\n\tpool<DriveBitId> orient_undirected_seen;\n\tpool<DriveBitId> orient_undirected_drivers;\n\tdict<DriveBitId, int> orient_undirected_distance;\n\n\tvoid orient_undirected(DriveBitId id);\n\npublic:\n\tDriveBit operator()(DriveBit const &bit);\n\n\tDriveSpec operator()(DriveSpec spec);\n\nprivate:\n\tbool keep_wire(Wire *wire) {\n\t\t// TODO configurable\n\t\treturn wire->has_attribute(ID(keep));\n\t}\n};\n\ninline Hasher DriveBitWire::hash_into(Hasher h) const\n{\n\th.eat(wire->name);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveBitPort::hash_into(Hasher h) const\n{\n\th.eat(cell->name);\n\th.eat(port);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveBitMarker::hash_into(Hasher h) const\n{\n\th.eat(marker);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveBitMultiple::hash_into(Hasher h) const\n{\n\th.eat(multiple_);\n\treturn h;\n}\n\ninline Hasher DriveBit::hash_into(Hasher h) const\n{\n\tswitch (type_) {\n\tcase DriveType::NONE:\n\t\th.eat(0);\n\t\tbreak;\n\tcase DriveType::CONSTANT:\n\t\th.eat(constant_);\n\t\tbreak;\n\tcase DriveType::WIRE:\n\t\th.eat(wire_);\n\t\tbreak;\n\tcase DriveType::PORT:\n\t\th.eat(port_);\n\t\tbreak;\n\tcase DriveType::MARKER:\n\t\th.eat(marker_);\n\t\tbreak;\n\tcase DriveType::MULTIPLE:\n\t\th.eat(multiple_);\n\t\tbreak;\n\t}\n\th.eat(type_);\n\treturn h;\n}\n\ninline Hasher DriveChunkWire::hash_into(Hasher h) const\n{\n\th.eat(wire->name);\n\th.eat(width);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveChunkPort::hash_into(Hasher h) const\n{\n\th.eat(cell->name);\n\th.eat(port);\n\th.eat(width);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveChunkMarker::hash_into(Hasher h) const\n{\n\th.eat(marker);\n\th.eat(width);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveChunkMultiple::hash_into(Hasher h) const\n{\n\th.eat(width_);\n\th.eat(multiple_);\n\treturn h;\n}\n\ninline Hasher DriveChunk::hash_into(Hasher h) const\n{\n\tswitch (type_) {\n\tcase DriveType::NONE:\n\t\th.eat(0);\n\t\tbreak;\n\tcase DriveType::CONSTANT:\n\t\th.eat(constant_);\n\t\tbreak;\n\tcase DriveType::WIRE:\n\t\th.eat(wire_);\n\t\tbreak;\n\tcase DriveType::PORT:\n\t\th.eat(port_);\n\t\tbreak;\n\tcase DriveType::MARKER:\n\t\th.eat(marker_);\n\t\tbreak;\n\tcase DriveType::MULTIPLE:\n\t\th.eat(multiple_);\n\t\tbreak;\n\t}\n\th.eat(type_);\n\treturn h;\n}\n\ninline Hasher DriveSpec::hash_into(Hasher h) const\n{\n\tupdhash();\n\th.eat(hash_);\n\treturn h;\n}\n\ninline Hasher DriverMap::DriveBitId::hash_into(Hasher h) const\n{\n\th.eat(id);\n\treturn h;\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"ff.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FF_H\n#define FF_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Describes a flip-flop or a latch.\n//\n// If has_gclk, this is a formal verification FF with implicit global clock:\n// Q is simply previous cycle's D. Additionally if is_anyinit is true, this is\n// an $anyinit cell which always has an undefined initialization value. Note\n// that $anyinit is not considered to be among the FF celltypes, so a pass has\n// to explicitly opt-in to process $anyinit cells with FfData.\n//\n// Otherwise, the FF/latch can have any number of features selected by has_*\n// attributes that determine Q's value (in order of decreasing priority):\n//\n// - on start, register is initialized to val_init\n// - if has_sr is present:\n// - sig_clr is per-bit async clear, and sets the corresponding bit to 0\n// if active\n// - sig_set is per-bit async set, and sets the corresponding bit to 1\n// if active\n// - if has_arst is present:\n// - sig_arst is whole-reg async reset, and sets the whole register to val_arst\n// - if has_aload is present:\n// - sig_aload is whole-reg async load (aka latch gate enable), and sets the whole\n// register to sig_ad\n// - if has_clk is present, and we're currently on a clock edge:\n// - if has_ce is present and ce_over_srst is true:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - if has_srst is present:\n// - sig_srst is whole-reg sync reset and sets the register to val_srst\n// - if has_ce is present and ce_over_srst is false:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - set whole reg to sig_d\n// - if nothing of the above applies, the reg value remains unchanged\n//\n// Since the yosys FF cell library isn't fully generic, not all combinations\n// of the features above can be supported:\n//\n// - only one of has_srst, has_arst, has_sr can be used\n// - if has_clk is used together with has_aload, then has_srst, has_arst,\n// has_sr cannot be used\n//\n// The valid feature combinations are thus:\n//\n// - has_clk + optional has_ce [dff/dffe]\n// - has_clk + optional has_ce + has_arst [adff/adffe]\n// - has_clk + optional has_ce + has_aload [aldff/aldffe]\n// - has_clk + optional has_ce + has_sr [dffsr/dffsre]\n// - has_clk + optional has_ce + has_srst [sdff/sdffe/sdffce]\n// - has_aload [dlatch]\n// - has_aload + has_arst [adlatch]\n// - has_aload + has_sr [dlatchsr]\n// - has_sr [sr]\n// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]\n// - empty set [not a cell — will be emitted as a simple direct connection]\n\nstruct FfData {\n\tModule *module;\n\tFfInitVals *initvals;\n\tCell *cell;\n\tIdString name;\n\t// The FF output.\n\tSigSpec sig_q;\n\t// The sync data input, present if has_clk or has_gclk.\n\tSigSpec sig_d;\n\t// The async data input, present if has_aload.\n\tSigSpec sig_ad;\n\t// The sync clock, present if has_clk.\n\tSigSpec sig_clk;\n\t// The clock enable, present if has_ce.\n\tSigSpec sig_ce;\n\t// The async load enable, present if has_aload.\n\tSigSpec sig_aload;\n\t// The async reset, preset if has_arst.\n\tSigSpec sig_arst;\n\t// The sync reset, preset if has_srst.\n\tSigSpec sig_srst;\n\t// The async clear (per-lane), present if has_sr.\n\tSigSpec sig_clr;\n\t// The async set (per-lane), present if has_sr.\n\tSigSpec sig_set;\n\t// True if this is a clocked (edge-sensitive) flip-flop.\n\tbool has_clk;\n\t// True if this is a $ff, exclusive with every other has_*.\n\tbool has_gclk;\n\t// True if this FF has a clock enable. Depends on has_clk.\n\tbool has_ce;\n\t// True if this FF has async load function — this includes D latches.\n\t// If this and has_clk are both set, has_arst and has_sr cannot be set.\n\tbool has_aload;\n\t// True if this FF has sync set/reset. Depends on has_clk, exclusive\n\t// with has_arst, has_sr, has_aload.\n\tbool has_srst;\n\t// True if this FF has async set/reset. Exclusive with has_srst,\n\t// has_sr. If this and has_clk are both set, has_aload cannot be set.\n\tbool has_arst;\n\t// True if this FF has per-bit async set + clear. Exclusive with\n\t// has_srst, has_arst. If this and has_clk are both set, has_aload\n\t// cannot be set.\n\tbool has_sr;\n\t// If has_ce and has_srst are both set, determines their relative\n\t// priorities: if true, inactive ce disables srst; if false, srst\n\t// operates independent of ce.\n\tbool ce_over_srst;\n\t// True if this FF is a fine cell, false if it is a coarse cell.\n\t// If true, width must be 1.\n\tbool is_fine;\n\t// True if this FF is an $anyinit cell. Depends on has_gclk.\n\tbool is_anyinit;\n\t// Polarities, corresponding to sig_*.\n\t// True means rising edge, false means falling edge.\n\tbool pol_clk;\n\t// True means active-high, false\n\t// means active-low.\n\tbool pol_ce;\n\tbool pol_aload;\n\tbool pol_arst;\n\tbool pol_srst;\n\tbool pol_clr;\n\tbool pol_set;\n\t// The value loaded by sig_arst.\n\tConst val_arst;\n\t// The value loaded by sig_srst.\n\tConst val_srst;\n\t// The initial value at power-up.\n\tConst val_init;\n\t// The FF data width in bits.\n\tint width;\n\tdict<IdString, Const> attributes;\n\n\tFfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {\n\t\twidth = 0;\n\t\thas_clk = false;\n\t\thas_gclk = false;\n\t\thas_ce = false;\n\t\thas_aload = false;\n\t\thas_srst = false;\n\t\thas_arst = false;\n\t\thas_sr = false;\n\t\tce_over_srst = false;\n\t\tis_fine = false;\n\t\tis_anyinit = false;\n\t\tpol_clk = false;\n\t\tpol_aload = false;\n\t\tpol_ce = false;\n\t\tpol_arst = false;\n\t\tpol_srst = false;\n\t\tpol_clr = false;\n\t\tpol_set = false;\n\t}\n\n\tFfData(FfInitVals *initvals, Cell *cell_);\n\n\t// Returns a FF identical to this one, but only keeping bit indices from the argument.\n\tFfData slice(const std::vector<int> &bits);\n\n\tvoid add_dummy_ce();\n\tvoid add_dummy_srst();\n\tvoid add_dummy_arst();\n\tvoid add_dummy_aload();\n\tvoid add_dummy_sr();\n\tvoid add_dummy_clk();\n\n\tvoid arst_to_aload();\n\tvoid arst_to_sr();\n\n\tvoid aload_to_sr();\n\n\t// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and\n\t// fixes up control signals appropriately to preserve semantics.\n\tvoid convert_ce_over_srst(bool val);\n\n\tvoid unmap_ce();\n\tvoid unmap_srst();\n\n\tvoid unmap_ce_srst() {\n\t\tunmap_ce();\n\t\tunmap_srst();\n\t}\n\n\tCell *emit();\n\n\t// Removes init attribute from the Q output, but keeps val_init unchanged.\n\t// It will be automatically reattached on emit. Use this before changing sig_q.\n\tvoid remove_init() {\n\t\tif (initvals)\n\t\t\tinitvals->remove_init(sig_q);\n\t}\n\n\tvoid remove();\n\n\t// Flip the sense of the given bit slices of the FF: insert inverters on data\n\t// inputs and output, flip the corresponding init/reset bits, swap clr/set\n\t// inputs with proper priority fix.\n\tvoid flip_bits(const pool<int> &bits);\n\n\tvoid flip_rst_bits(const pool<int> &bits);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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@@ -173,24 +173,24 @@ export const filesystem = {
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"ffmerge.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFMERGE_H\n#define FFMERGE_H\n\n#include \"kernel/ffinit.h\"\n#include \"kernel/ff.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// A helper class for passes that want to merge FFs on the input or output\n// of a cell into the cell itself.\n//\n// The procedure is:\n//\n// 1. Construct this class (at beginning of processing for a given module).\n// 2. For every considered cell:\n//\n// a. Call find_output_ff for every considered output.\n// b. Call find_input_ff for every considered input.\n// c. Look at the FF description returned (if any) from each call, reject\n// results that cannot be merged into given cell for any reason.\n// If both inputs and outputs are being merged, take care of FF bits that\n// are returned in both input and output results (a FF bit cannot be\n// merged to both). Decide on the final set of FF bits to merge.\n// d. Call remove_output_ff for every find_output_ff result that will be used\n// for merging. This removes the actual FF bits from design and from index.\n// e. Call mark_input_ff for every find_input_ff result that will be used\n// for merging. This updates the index disallowing further usage of these\n// FF bits for output FF merging, if they were eligible before. The actual\n// FF bits are still left in the design and can be merged into other inputs.\n// If the FF bits are not otherwise used, they will be removed by later\n// opt passes.\n// f. Merge the FFs into the cell.\n//\n// Note that, if both inputs and outputs are being considered for merging in\n// a single pass, the result may be nondeterministic (depending on cell iteration\n// order) because a given FF bit could be eligible for both input and output merge,\n// perhaps in different cells. For this reason, it may be a good idea to separate\n// input and output merging.\n\nstruct FfMergeHelper\n{\n\tconst SigMap *sigmap;\n\tRTLIL::Module *module;\n\tFfInitVals *initvals;\n\n\tdict<SigBit, std::pair<Cell*, int>> dff_driver;\n\tdict<SigBit, pool<std::pair<Cell*, int>>> dff_sink;\n\tdict<SigBit, int> sigbit_users_count;\n\n\t// Returns true if all bits in sig are completely unused.\n\tbool is_output_unused(RTLIL::SigSpec sig);\n\n\t// Finds the FF to merge into a given cell output. Takes sig, which\n\t// is the current cell output — it will be the sig_d of the found FF.\n\t// If found, returns true, and fills the two output arguments.\n\t//\n\t// For every bit of sig, this function finds a FF bit that has\n\t// the same sig_d, and fills the output FfData according to the FF\n\t// bits found. This function will only consider FF bits that are\n\t// the only user of the given sig bits — if any bit in sig is used\n\t// by anything other than a single FF, this function will return false.\n\t//\n\t// The returned FfData structure does not correspond to any actual FF\n\t// cell in the design — it is the amalgamation of extracted FF bits,\n\t// possibly coming from several FF cells.\n\t//\n\t// If some of the bits in sig have no users at all, this function\n\t// will accept them as well (and fill returned FfData with dummy values\n\t// for the given bit, effectively synthesizing an unused FF bit of the\n\t// appropriate type). However, if all bits in sig are completely\n\t// unused, this function will fail and return false (having no idea\n\t// what kind of FF to produce) — use the above helper if that case\n\t// is important to handle.\n\t//\n\t// Note that this function does not remove the FF bits returned from\n\t// the design — this is so that the caller can decide whether to accept\n\t// this FF for merging or not. If the result is accepted,\n\t// remove_output_ff should be called on the second output argument.\n\tbool find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// Like above, but returns a FF to merge into a given cell input. Takes\n\t// sig_q, which is the current cell input — it will search for FFs with\n\t// matching sig_q.\n\t//\n\t// As opposed to find_output_ff, this function doesn't care about usage\n\t// counts, and may return FF bits that also have other fanout. This\n\t// should not be a problem for input FF merging.\n\t//\n\t// As a special case, if some of the bits in sig_q are constant, this\n\t// function will accept them as well, by synthesizing in-place\n\t// a constant-input FF bit (with matching initial value and reset value).\n\t// However, this will not work if the input is all-constant — if the caller\n\t// cares about this case, it needs to check for it explicitely.\n\tbool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_output_ff result that will be merged. This\n\t// marks the given FF bits as used up (and not to be considered for\n\t// further merging as inputs), and reconnects their Q ports to a dummy\n\t// wire (since the wire previously connected there will now be driven\n\t// by the merged-to cell instead).\n\tvoid remove_output_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_input_ff result that will be merged. This\n\t// marks the given FF bits as used, and disallows merging them as\n\t// outputs. They can, however, still be merged as inputs again\n\t// (perhaps for another cell).\n\tvoid mark_input_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\tvoid set(FfInitVals *initvals_, RTLIL::Module *module_);\n\n\tvoid clear();\n\n\tFfMergeHelper(FfInitVals *initvals, RTLIL::Module *module) {\n\t\tset(initvals, module);\n\t}\n\n\tFfMergeHelper() {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"fmt.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n// $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tTIME = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n// \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tLITERAL \t= 0,\n\t\tINTEGER \t= 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign = MINUS;\n\tbool hex_upper = false;\n\tbool show_base = false;\n\tbool group = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_literal(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"gzip.h": "#include <string>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_GZIP_H\n#define YOSYS_GZIP_H\n\nYOSYS_NAMESPACE_BEGIN\n\n#ifdef YOSYS_ENABLE_ZLIB\n\nnamespace Zlib {\n#include <zlib.h>\n}\n\n/*\nAn output stream that uses a stringbuf to buffer data internally,\nusing zlib to write gzip-compressed data every time the stream is flushed.\n*/\nclass gzip_ostream : public std::ostream {\npublic:\n\tgzip_ostream(): std::ostream(nullptr) {\n\t\trdbuf(&outbuf);\n\t}\n\tbool open(const std::string &filename) {\n\t\treturn outbuf.open(filename);\n\t}\nprivate:\n\tclass obuf : public std::stringbuf {\n\tpublic:\n\t\tobuf();\n\t\tbool open(const std::string &filename);\n\t\tvirtual int sync() override;\n\t\tvirtual ~obuf();\n\tprivate:\n\t\tstatic const int buffer_size = 4096;\n\t\tchar buffer[buffer_size]; // Internal buffer for compressed data\n\t\tZlib::gzFile gzf = nullptr; // Handle to the gzip file\n\t};\n\n\tobuf outbuf; // The stream buffer instance\n};\n\n/*\nAn input stream that uses zlib to read gzip-compressed data from a file,\nbuffering the decompressed data internally using its own buffer.\n*/\nclass gzip_istream final : public std::istream {\npublic:\n\tgzip_istream() : std::istream(&inbuf) {}\n\tbool open(const std::string& filename) {\n\t\treturn inbuf.open(filename);\n\t}\nprivate:\n\tclass ibuf final : public std::streambuf {\n\tpublic:\n\t\tibuf() : gzf(nullptr) {}\n\t\tbool open(const std::string& filename);\n\t\tvirtual ~ibuf();\n\n\tprotected:\n\t\t// Called when the buffer is empty and more input is needed\n\t\tvirtual int_type underflow() override;\n\tprivate:\n\t\tstatic const int buffer_size = 8192;\n\t\tchar buffer[buffer_size];\n\t\tZlib::gzFile gzf;\n\t};\n\n\tibuf inbuf; // The stream buffer instance\n};\n\n#endif // YOSYS_ENABLE_ZLIB\n\nstd::istream* uncompressed(const std::string filename, std::ios_base::openmode mode = std::ios_base::in);\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_GZIP_H\n",
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"hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <variant>\n#include <vector>\n#include <type_traits>\n#include <stdint.h>\n\n#define YS_HASHING_VERSION 1\n\nnamespace hashlib {\n\n/**\n * HASHING\n *\n * Also refer to docs/source/yosys_internals/hashing.rst\n *\n * The Hasher knows how to hash 32 and 64-bit integers. That's it.\n * In the future, it could be expanded to do vectors with SIMD.\n *\n * The Hasher doesn't know how to hash common standard containers\n * and compositions. However, hashlib provides centralized wrappers.\n *\n * Hashlib doesn't know how to hash silly Yosys-specific types.\n * Hashlib doesn't depend on Yosys and can be used standalone.\n * Please don't use hashlib standalone for new projects.\n * Never directly include kernel/hashlib.h in Yosys code.\n * Instead include kernel/yosys_common.h\n *\n * The hash_ops type is now always left to its default value, derived\n * from templated functions through SFINAE. Providing custom ops is\n * still supported.\n *\n * HASH TABLES\n *\n * We implement associative data structures with separate chaining.\n * Linked lists use integers into the indirection hashtable array\n * instead of pointers.\n */\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\nnamespace legacy {\n\tinline uint32_t djb2_add(uint32_t a, uint32_t b) {\n\t\treturn ((a << 5) + a) + b;\n\t}\n};\n\ntemplate<typename T>\nstruct hash_ops;\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\nclass HasherDJB32 {\npublic:\n\tusing hash_t = uint32_t;\n\n\tHasherDJB32() {\n\t\t// traditionally 5381 is used as starting value for the djb2 hash\n\t\tstate = 5381;\n\t}\n\tstatic void set_fudge(hash_t f) {\n\t\tfudge = f;\n\t}\n\nprivate:\n\tuint32_t state;\n\tstatic uint32_t fudge;\n\t// The XOR version of DJB2\n\t[[nodiscard]]\n\tstatic uint32_t djb2_xor(uint32_t a, uint32_t b) {\n\t\tuint32_t hash = ((a << 5) + a) ^ b;\n\t\treturn hash;\n\t}\n\tpublic:\n\tvoid hash32(uint32_t i) {\n\t\tstate = djb2_xor(i, state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\tvoid hash64(uint64_t i) {\n\t\tstate = djb2_xor((uint32_t)(i & 0xFFFFFFFFULL), state);\n\t\tstate = djb2_xor((uint32_t)(i >> 32ULL), state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\t[[nodiscard]]\n\thash_t yield() {\n\t\treturn (hash_t)state;\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(T&& t) {\n\t\t*this = hash_ops<std::remove_cv_t<std::remove_reference_t<T>>>::hash_into(std::forward<T>(t), *this);\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(const T& t) {\n\t\t*this = hash_ops<T>::hash_into(t, *this);\n\t}\n\n\tvoid commutative_eat(hash_t t) {\n\t\tstate ^= t;\n\t}\n\n\tvoid force(hash_t new_state) {\n\t\tstate = new_state;\n\t}\n};\n\nusing Hasher = HasherDJB32;\n\n// Boilerplate compressor for trivially implementing\n// top-level hash method with hash_into\n#define HASH_TOP_LOOP_FST [[nodiscard]] static inline Hasher hash\n#define HASH_TOP_LOOP_SND { \\\n\tHasher h; \\\n\th = hash_into(a, h); \\\n\treturn h; \\\n}\n\ntemplate<typename T>\nstruct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const T &a, Hasher h) {\n\t\tif constexpr (std::is_integral_v<T>) {\n\t\t\tstatic_assert(sizeof(T) <= sizeof(uint64_t));\n\t\t\tif (sizeof(T) == sizeof(uint64_t))\n\t\t\t\th.hash64(a);\n\t\t\telse\n\t\t\t\th.hash32(a);\n\t\t\treturn h;\n\t\t} else if constexpr (std::is_enum_v<T>) {\n\t\t\tusing u_type = std::underlying_type_t<T>;\n\t\t\treturn hash_ops<u_type>::hash_into((u_type) a, h);\n\t\t} else if constexpr (std::is_pointer_v<T>) {\n\t\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t) a, h);\n\t\t} else if constexpr (std::is_same_v<T, std::string>) {\n\t\t\tfor (auto c : a)\n\t\t\t\th.hash32(c);\n\t\t\treturn h;\n\t\t} else {\n\t\t\treturn a.hash_into(h);\n\t\t}\n\t}\n\tHASH_TOP_LOOP_FST (const T &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::pair<P, Q> a, Hasher h) {\n\t\th = hash_ops<P>::hash_into(a.first, h);\n\t\th = hash_ops<Q>::hash_into(a.second, h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::pair<P, Q> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), Hasher>::type hash_into(std::tuple<T...>, Hasher h) {\n\t\treturn h;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), Hasher>::type hash_into(std::tuple<T...> a, Hasher h) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\th = hash_into<I+1>(a, h);\n\t\th = element_ops_t::hash_into(std::get<I>(a), h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::tuple<T...> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::vector<T> a, Hasher h) {\n\t\th.eat((uint32_t)a.size());\n\t\tfor (auto k : a)\n\t\t\th.eat(k);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::vector<T> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T, size_t N> struct hash_ops<std::array<T, N>> {\n static inline bool cmp(std::array<T, N> a, std::array<T, N> b) {\n return a == b;\n }\n [[nodiscard]] static inline Hasher hash_into(std::array<T, N> a, Hasher h) {\n for (const auto& k : a)\n h = hash_ops<T>::hash_into(k, h);\n return h;\n }\n\tHASH_TOP_LOOP_FST (std::array<T, N> a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\treturn strcmp(a, b) == 0;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const char *a, Hasher h) {\n\t\twhile (*a)\n\t\t\th.hash32(*(a++));\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const char *a) HASH_TOP_LOOP_SND\n};\n\ntemplate <> struct hash_ops<char*> : hash_cstr_ops {};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const void *a, Hasher h) {\n\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t)a, h);\n\t}\n\tHASH_TOP_LOOP_FST (const void *a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\t[[nodiscard]] static inline Hasher hash_into(const T *a, Hasher h) {\n\t\tif (a)\n\t\t\th = a->hash_into(h);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n\ttemplate<typename T>\n\tHASH_TOP_LOOP_FST (const T *a) HASH_TOP_LOOP_SND\n};\n/**\n * If you find yourself using this function, think hard\n * about if it's the right thing to do. Mixing finalized\n * hashes together with XORs or worse can destroy\n * desirable qualities of the hash function\n */\ntemplate<typename T>\n[[nodiscard]]\nHasher::hash_t run_hash(const T& obj) {\n\treturn hash_ops<T>::hash(obj).yield();\n}\n\n/** Refer to docs/source/yosys_internals/hashing.rst */\ntemplate<typename T>\n[[nodiscard]]\n[[deprecated]]\ninline unsigned int mkhash(const T &v) {\n\treturn (unsigned int) run_hash<T>(v);\n}\n\ntemplate<> struct hash_ops<std::monostate> {\n\tstatic inline bool cmp(std::monostate a, std::monostate b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::monostate, Hasher h) {\n\t\treturn h;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::variant<T...>> {\n\tstatic inline bool cmp(std::variant<T...> a, std::variant<T...> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::variant<T...> a, Hasher h) {\n\t\tstd::visit([& h](const auto &v) { h.eat(v); }, a);\n\t\th.eat(a.index());\n\t\treturn h;\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::optional<T>> {\n\tstatic inline bool cmp(std::optional<T> a, std::optional<T> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::optional<T> a, Hasher h) {\n\t\tif(a.has_value())\n\t\t\th.eat(*a);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n};\n\ninline unsigned int hashtable_size(unsigned int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<unsigned int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713, 2211715897, 2764644887, 3455806139\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(unsigned int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict {\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto &it : entries) {\n\t\t\tHasher entry_hash;\n\t\t\tentry_hash.eat(it.udata.first);\n\t\t\tentry_hash.eat(it.udata.second);\n\t\t\th.commutative_eat(entry_hash.yield());\n\t\t}\n\t\th.eat(entries.size());\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto &it : entries) {\n\t\t\th.commutative_eat(ops.hash(it.udata).yield());\n\t\t}\n\t\th.eat(entries.size());\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
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"io.h": "#include <string>\n#include <stdarg.h>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_IO_H\n#define YOSYS_IO_H\n\nYOSYS_NAMESPACE_BEGIN\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n\t// For the common case of strings shorter than 128, save a heap\n\t// allocation by using a stack allocated buffer.\n\tconst int kBufSize = 128;\n\tchar buf[kBufSize];\n\tbuf[0] = '\\0';\n\tva_list apc;\n\tva_copy(apc, ap);\n\tint n = vsnprintf(buf, kBufSize, fmt, apc);\n\tva_end(apc);\n\tif (n < kBufSize)\n\t\treturn std::string(buf);\n\n\tstd::string string;\n\tchar *str = NULL;\n#if defined(_WIN32) || defined(__CYGWIN__)\n\tint sz = 2 * kBufSize, rc;\n\twhile (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char *)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n\tif (vasprintf(&str, fmt, ap) < 0)\n\t\tstr = NULL;\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_IO_H\n",
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"hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <optional>\n#include <string>\n#include <variant>\n#include <vector>\n#include <type_traits>\n#include <stdint.h>\n\n#define YS_HASHING_VERSION 1\n\nnamespace hashlib {\n\n/**\n * HASHING\n *\n * Also refer to docs/source/yosys_internals/hashing.rst\n *\n * The Hasher knows how to hash 32 and 64-bit integers. That's it.\n * In the future, it could be expanded to do vectors with SIMD.\n *\n * The Hasher doesn't know how to hash common standard containers\n * and compositions. However, hashlib provides centralized wrappers.\n *\n * Hashlib doesn't know how to hash silly Yosys-specific types.\n * Hashlib doesn't depend on Yosys and can be used standalone.\n * Please don't use hashlib standalone for new projects.\n * Never directly include kernel/hashlib.h in Yosys code.\n * Instead include kernel/yosys_common.h\n *\n * The hash_ops type is now always left to its default value, derived\n * from templated functions through SFINAE. Providing custom ops is\n * still supported.\n *\n * HASH TABLES\n *\n * We implement associative data structures with separate chaining.\n * Linked lists use integers into the indirection hashtable array\n * instead of pointers.\n */\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\nnamespace legacy {\n\tinline uint32_t djb2_add(uint32_t a, uint32_t b) {\n\t\treturn ((a << 5) + a) + b;\n\t}\n};\n\ntemplate<typename T>\nstruct hash_ops;\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\nclass HasherDJB32 {\npublic:\n\tusing hash_t = uint32_t;\n\n\tHasherDJB32() {\n\t\t// traditionally 5381 is used as starting value for the djb2 hash\n\t\tstate = 5381;\n\t}\n\tstatic void set_fudge(hash_t f) {\n\t\tfudge = f;\n\t}\n\nprivate:\n\tuint32_t state;\n\tstatic uint32_t fudge;\n\t// The XOR version of DJB2\n\t[[nodiscard]]\n\tstatic uint32_t djb2_xor(uint32_t a, uint32_t b) {\n\t\tuint32_t hash = ((a << 5) + a) ^ b;\n\t\treturn hash;\n\t}\n\tpublic:\n\tvoid hash32(uint32_t i) {\n\t\tstate = djb2_xor(i, state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\tvoid hash64(uint64_t i) {\n\t\tstate = djb2_xor((uint32_t)(i & 0xFFFFFFFFULL), state);\n\t\tstate = djb2_xor((uint32_t)(i >> 32ULL), state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\t[[nodiscard]]\n\thash_t yield() {\n\t\treturn (hash_t)state;\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(T&& t) {\n\t\t*this = hash_ops<std::remove_cv_t<std::remove_reference_t<T>>>::hash_into(std::forward<T>(t), *this);\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(const T& t) {\n\t\t*this = hash_ops<T>::hash_into(t, *this);\n\t}\n\n\tvoid commutative_eat(hash_t t) {\n\t\tstate ^= t;\n\t}\n\n\tvoid force(hash_t new_state) {\n\t\tstate = new_state;\n\t}\n};\n\nusing Hasher = HasherDJB32;\n\n// Boilerplate compressor for trivially implementing\n// top-level hash method with hash_into\n#define HASH_TOP_LOOP_FST [[nodiscard]] static inline Hasher hash\n#define HASH_TOP_LOOP_SND { \\\n\tHasher h; \\\n\th = hash_into(a, h); \\\n\treturn h; \\\n}\n\ntemplate<typename T>\nstruct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const T &a, Hasher h) {\n\t\tif constexpr (std::is_integral_v<T>) {\n\t\t\tstatic_assert(sizeof(T) <= sizeof(uint64_t));\n\t\t\tif (sizeof(T) == sizeof(uint64_t))\n\t\t\t\th.hash64(a);\n\t\t\telse\n\t\t\t\th.hash32(a);\n\t\t\treturn h;\n\t\t} else if constexpr (std::is_enum_v<T>) {\n\t\t\tusing u_type = std::underlying_type_t<T>;\n\t\t\treturn hash_ops<u_type>::hash_into((u_type) a, h);\n\t\t} else if constexpr (std::is_pointer_v<T>) {\n\t\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t) a, h);\n\t\t} else if constexpr (std::is_same_v<T, std::string>) {\n\t\t\tfor (auto c : a)\n\t\t\t\th.hash32(c);\n\t\t\treturn h;\n\t\t} else {\n\t\t\treturn a.hash_into(h);\n\t\t}\n\t}\n\tHASH_TOP_LOOP_FST (const T &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::pair<P, Q> a, Hasher h) {\n\t\th = hash_ops<P>::hash_into(a.first, h);\n\t\th = hash_ops<Q>::hash_into(a.second, h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::pair<P, Q> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), Hasher>::type hash_into(std::tuple<T...>, Hasher h) {\n\t\treturn h;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), Hasher>::type hash_into(std::tuple<T...> a, Hasher h) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\th = hash_into<I+1>(a, h);\n\t\th = element_ops_t::hash_into(std::get<I>(a), h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::tuple<T...> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::vector<T> a, Hasher h) {\n\t\th.eat((uint32_t)a.size());\n\t\tfor (auto k : a)\n\t\t\th.eat(k);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::vector<T> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T, size_t N> struct hash_ops<std::array<T, N>> {\n static inline bool cmp(std::array<T, N> a, std::array<T, N> b) {\n return a == b;\n }\n [[nodiscard]] static inline Hasher hash_into(std::array<T, N> a, Hasher h) {\n for (const auto& k : a)\n h = hash_ops<T>::hash_into(k, h);\n return h;\n }\n\tHASH_TOP_LOOP_FST (std::array<T, N> a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\treturn strcmp(a, b) == 0;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const char *a, Hasher h) {\n\t\twhile (*a)\n\t\t\th.hash32(*(a++));\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const char *a) HASH_TOP_LOOP_SND\n};\n\ntemplate <> struct hash_ops<char*> : hash_cstr_ops {};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const void *a, Hasher h) {\n\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t)a, h);\n\t}\n\tHASH_TOP_LOOP_FST (const void *a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\t[[nodiscard]] static inline Hasher hash_into(const T *a, Hasher h) {\n\t\tif (a)\n\t\t\th = a->hash_into(h);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n\ttemplate<typename T>\n\tHASH_TOP_LOOP_FST (const T *a) HASH_TOP_LOOP_SND\n};\n/**\n * If you find yourself using this function, think hard\n * about if it's the right thing to do. Mixing finalized\n * hashes together with XORs or worse can destroy\n * desirable qualities of the hash function\n */\ntemplate<typename T>\n[[nodiscard]]\nHasher::hash_t run_hash(const T& obj) {\n\treturn hash_ops<T>::hash(obj).yield();\n}\n\n/** Refer to docs/source/yosys_internals/hashing.rst */\ntemplate<typename T>\n[[nodiscard]]\n[[deprecated]]\ninline unsigned int mkhash(const T &v) {\n\treturn (unsigned int) run_hash<T>(v);\n}\n\ntemplate<> struct hash_ops<std::monostate> {\n\tstatic inline bool cmp(std::monostate a, std::monostate b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::monostate, Hasher h) {\n\t\treturn h;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::variant<T...>> {\n\tstatic inline bool cmp(std::variant<T...> a, std::variant<T...> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::variant<T...> a, Hasher h) {\n\t\tstd::visit([& h](const auto &v) { h.eat(v); }, a);\n\t\th.eat(a.index());\n\t\treturn h;\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::optional<T>> {\n\tstatic inline bool cmp(std::optional<T> a, std::optional<T> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::optional<T> a, Hasher h) {\n\t\tif(a.has_value())\n\t\t\th.eat(*a);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n};\n\ninline unsigned int hashtable_size(unsigned int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<unsigned int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713, 2211715897, 2764644887, 3455806139\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(unsigned int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict {\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto &it : entries) {\n\t\t\tHasher entry_hash;\n\t\t\tentry_hash.eat(it.udata.first);\n\t\t\tentry_hash.eat(it.udata.second);\n\t\t\th.commutative_eat(entry_hash.yield());\n\t\t}\n\t\th.eat(entries.size());\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto &it : entries) {\n\t\t\th.commutative_eat(ops.hash(it.udata).yield());\n\t\t}\n\t\th.eat(entries.size());\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
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"io.h": "#include <string>\n#include <stdarg.h>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_IO_H\n#define YOSYS_IO_H\n\nYOSYS_NAMESPACE_BEGIN\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n\t// For the common case of strings shorter than 128, save a heap\n\t// allocation by using a stack allocated buffer.\n\tconst int kBufSize = 128;\n\tchar buf[kBufSize];\n\tbuf[0] = '\\0';\n\tva_list apc;\n\tva_copy(apc, ap);\n\tint n = vsnprintf(buf, kBufSize, fmt, apc);\n\tva_end(apc);\n\tif (n < kBufSize)\n\t\treturn std::string(buf);\n\n\tstd::string string;\n\tchar *str = NULL;\n#if defined(_WIN32) || defined(__CYGWIN__)\n\tint sz = 2 * kBufSize, rc;\n\twhile (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char *)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n\tif (vasprintf(&str, fmt, ap) < 0)\n\t\tstr = NULL;\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(const std::string& filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname, bool is_exec = false);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_IO_H\n",
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"json.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n enum Scope {\n VALUE,\n OBJECT_FIRST,\n OBJECT,\n ARRAY_FIRST,\n ARRAY,\n };\n\n struct Target {\n virtual void emit(const char *data) = 0;\n virtual void flush() {};\n virtual ~Target() {};\n };\n\n std::string newline_indent = \"\\n\";\n std::vector<std::unique_ptr<Target>> targets;\n std::vector<Scope> state = {VALUE};\n int compact_depth = INT_MAX;\npublic:\n\n void emit_to_log();\n void append_to_string(std::string &target);\n bool write_to_file(const std::string &path);\n\n bool active() { return !targets.empty(); }\n\n void compact() { compact_depth = GetSize(state); }\n\n void line(bool space_if_inline = true);\n void raw(const char *raw_json);\n void flush();\n void begin_object();\n void begin_array();\n void end_object();\n void end_array();\n void name(const char *name);\n void begin_value();\n void end_value();\n void value_json(const Json &value);\n void value(unsigned int value) { value_json(Json((int)value)); }\n template<typename T>\n void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n void entry_json(const char *name, const Json &value);\n void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n template<typename T>\n void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n template<typename T>\n void object(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n entry(item.first, item.second);\n end_object();\n }\n\n template<typename T>\n void array(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n value(item);\n end_object();\n }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\nconst char *log_str(const char *str);\nconst char *log_str(std::string const &str);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T> static inline void log_dump_val_worker(dict<K, T> &v);\ntemplate<typename K> static inline void log_dump_val_worker(pool<K> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T>\nstatic inline void log_dump_val_worker(dict<K, T> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(pool<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
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"macc.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct
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"macc.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct term_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\tstd::vector<term_t> terms;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<term_t> new_terms;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : terms)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_terms.push_back(port);\n\t\t}\n\n\t\tif (off.as_bool()) {\n\t\t\tterm_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_terms.push_back(port);\n\t\t}\n\n\t\tnew_terms.swap(terms);\n\t}\n\n\tvoid from_cell_v1(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tterms.clear();\n\n\t\tauto config_bits = cell->getParam(ID::CONFIG);\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tterm_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tterms.push_back(this_port);\n\t\t}\n\n\t\tfor (auto bit : cell->getPort(ID::B))\n\t\t\tterms.push_back(term_t{{bit}, {}, false, false});\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (cell->type == ID($macc)) {\n\t\t\tfrom_cell_v1(cell);\n\t\t\treturn;\n\t\t}\n\t\tlog_assert(cell->type == ID($macc_v2));\n\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\t\tRTLIL::SigSpec port_b = cell->getPort(ID::B);\n\t\tRTLIL::SigSpec port_c = cell->getPort(ID::C);\n\n\t\tterms.clear();\n\n\t\tint nproducts = cell->getParam(ID::NPRODUCTS).as_int();\n\t\tconst Const &product_neg = cell->getParam(ID::PRODUCT_NEGATED);\n\t\tconst Const &a_widths = cell->getParam(ID::A_WIDTHS);\n\t\tconst Const &b_widths = cell->getParam(ID::B_WIDTHS);\n\t\tconst Const &a_signed = cell->getParam(ID::A_SIGNED);\n\t\tconst Const &b_signed = cell->getParam(ID::B_SIGNED);\n\t\tint ai = 0, bi = 0;\n\t\tfor (int i = 0; i < nproducts; i++) {\n\t\t\tterm_t term;\n\n\t\t\tlog_assert(a_signed[i] == b_signed[i]);\n\t\t\tterm.is_signed = (a_signed[i] == State::S1);\n\t\t\tint a_width = a_widths.extract(16 * i, 16).as_int(false);\n\t\t\tint b_width = b_widths.extract(16 * i, 16).as_int(false);\n\n\t\t\tterm.in_a = port_a.extract(ai, a_width);\n\t\t\tai += a_width;\n\t\t\tterm.in_b = port_b.extract(bi, b_width);\n\t\t\tbi += b_width;\n\t\t\tterm.do_subtract = (product_neg[i] == State::S1);\n\n\t\t\tterms.push_back(term);\n\t\t}\n\t\tlog_assert(port_a.size() == ai);\n\t\tlog_assert(port_b.size() == bi);\n\n\t\tint naddends = cell->getParam(ID::NADDENDS).as_int();\n\t\tconst Const &addend_neg = cell->getParam(ID::ADDEND_NEGATED);\n\t\tconst Const &c_widths = cell->getParam(ID::C_WIDTHS);\n\t\tconst Const &c_signed = cell->getParam(ID::C_SIGNED);\n\t\tint ci = 0;\n\t\tfor (int i = 0; i < naddends; i++) {\n\t\t\tterm_t term;\n\n\t\t\tterm.is_signed = (c_signed[i] == State::S1);\n\t\t\tint c_width = c_widths.extract(16 * i, 16).as_int(false);\n\n\t\t\tterm.in_a = port_c.extract(ci, c_width);\n\t\t\tci += c_width;\n\t\t\tterm.do_subtract = (addend_neg[i] == State::S1);\n\n\t\t\tterms.push_back(term);\n\t\t}\n\t\tlog_assert(port_c.size() == ci);\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell)\n\t{\n\t\tcell->type = ID($macc_v2);\n\n\t\tint nproducts = 0, naddends = 0;\n\t\tConst a_signed, b_signed, a_widths, b_widths, product_negated;\n\t\tConst c_signed, c_widths, addend_negated;\n\t\tSigSpec a, b, c;\n\n\t\tfor (int i = 0; i < (int) terms.size(); i++) {\n\t\t\tSigSpec term_a = terms[i].in_a, term_b = terms[i].in_b;\n\n\t\t\tif (term_b.empty()) {\n\t\t\t\t// addend\n\t\t\t\tc_widths.append(Const(term_a.size(), 16));\n\t\t\t\tc_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\taddend_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tc.append(term_a);\n\t\t\t\tnaddends++;\n\t\t\t} else {\n\t\t\t\t// product\n\t\t\t\ta_widths.append(Const(term_a.size(), 16));\n\t\t\t\tb_widths.append(Const(term_b.size(), 16));\n\t\t\t\ta_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tb_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tproduct_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\ta.append(term_a);\n\t\t\t\tb.append(term_b);\n\t\t\t\tnproducts++;\n\t\t\t}\n\t\t}\n\n\t\tif (a_signed.empty())\n\t\t\ta_signed = {RTLIL::Sx};\n\t\tif (b_signed.empty())\n\t\t\tb_signed = {RTLIL::Sx};\n\t\tif (c_signed.empty())\n\t\t\tc_signed = {RTLIL::Sx};\n\t\tif (a_widths.empty())\n\t\t\ta_widths = {RTLIL::Sx};\n\t\tif (b_widths.empty())\n\t\t\tb_widths = {RTLIL::Sx};\n\t\tif (c_widths.empty())\n\t\t\tc_widths = {RTLIL::Sx};\n\t\tif (product_negated.empty())\n\t\t\tproduct_negated = {RTLIL::Sx};\n\t\tif (addend_negated.empty())\n\t\t\taddend_negated = {RTLIL::Sx};\n\n\t\tcell->setParam(ID::NPRODUCTS, nproducts);\n\t\tcell->setParam(ID::PRODUCT_NEGATED, product_negated);\n\t\tcell->setParam(ID::NADDENDS, naddends);\n\t\tcell->setParam(ID::ADDEND_NEGATED, addend_negated);\n\t\tcell->setParam(ID::A_SIGNED, a_signed);\n\t\tcell->setParam(ID::B_SIGNED, b_signed);\n\t\tcell->setParam(ID::C_SIGNED, c_signed);\n\t\tcell->setParam(ID::A_WIDTHS, a_widths);\n\t\tcell->setParam(ID::B_WIDTHS, b_widths);\n\t\tcell->setParam(ID::C_WIDTHS, c_widths);\n\t\tcell->setPort(ID::A, a);\n\t\tcell->setPort(ID::B, b);\n\t\tcell->setPort(ID::C, c);\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits())\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : terms)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool is_simple_product()\n\t{\n\t\treturn terms.size() == 1 &&\n\t\t\t\t!terms[0].in_b.empty() &&\n\t\t\t\t!terms[0].do_subtract;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"mem.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MEM_H\n#define MEM_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n#include \"kernel/utils.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct MemRd : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity, ce_over_srst;\n\tConst arst_value, srst_value, init_value;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will bypass the written data\n\t// to this port's output (default behavior is to read old value).\n\t// Can only be set for write ports that have the same clock domain.\n\tstd::vector<bool> transparency_mask;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will return an all-X (don't care)\n\t// value. Mutually exclusive with transparency_mask.\n\t// Can only be set for write ports that have the same clock domain.\n\t// For optimization purposes, this will also be set if we can\n\t// determine that the two ports can never be active simultanously\n\t// (making the above vacuously true).\n\tstd::vector<bool> collision_x_mask;\n\tSigSpec clk, en, arst, srst, addr, data;\n\n\tMemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n};\n\nstruct MemWr : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity;\n\tstd::vector<bool> priority_mask;\n\tSigSpec clk, en, addr, data;\n\n\tMemWr() : removed(false), cell(nullptr) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n\n\tstd::pair<SigSpec, std::vector<int>> compress_en();\n\tSigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig);\n};\n\nstruct MemInit : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tConst addr;\n\tConst data;\n\tConst en;\n\tMemInit() : removed(false), cell(nullptr) {}\n};\n\nstruct Mem : RTLIL::AttrObject {\n\tModule *module;\n\tIdString memid;\n\tbool packed;\n\tRTLIL::Memory *mem;\n\tCell *cell;\n\tint width, start_offset, size;\n\tstd::vector<MemInit> inits;\n\tstd::vector<MemRd> rd_ports;\n\tstd::vector<MemWr> wr_ports;\n\n\t// Removes this memory from the module. The data in helper structures\n\t// is unaffected except for the cell/mem fields.\n\tvoid remove();\n\n\t// Commits all changes in helper structures into the module — ports and\n\t// inits marked as removed are actually removed, new ports/inits create\n\t// new cells, modified port/inits are commited into their existing\n\t// cells. Note that this reindexes the ports and inits array (actually\n\t// removing the ports/inits marked as removed).\n\tvoid emit();\n\n\t// Marks all inits as removed.\n\tvoid clear_inits();\n\n\t// Coalesces inits: whenever two inits have overlapping or touching\n\t// address ranges, they are combined into one, with the higher-priority\n\t// one's data overwriting the other. Running this results in\n\t// an inits list equivalent to the original, in which all entries\n\t// cover disjoint (and non-touching) address ranges, and all enable\n\t// masks are all-1.\n\tvoid coalesce_inits();\n\n\t// Checks consistency of this memory and all its ports/inits, using\n\t// log_assert.\n\tvoid check();\n\n\t// Gathers all initialization data into a single big const covering\n\t// the whole memory. For all non-initialized bits, Sx will be returned.\n\tConst get_init_data() const;\n\n\t// Constructs and returns the helper structures for all memories\n\t// in a module.\n\tstatic std::vector<Mem> get_all_memories(Module *module);\n\n\t// Constructs and returns the helper structures for all selected\n\t// memories in a module.\n\tstatic std::vector<Mem> get_selected_memories(Module *module);\n\n\t// Converts a synchronous read port into an asynchronous one by\n\t// extracting the data (or, in some rare cases, address) register\n\t// into a separate cell, together with any soft-transparency\n\t// logic necessary to preserve its semantics. Returns the created\n\t// register cell, if any. Note that in some rare cases this function\n\t// may succeed and perform a conversion without creating a new\n\t// register — a nullptr result doesn't imply nothing was done.\n\tCell *extract_rdff(int idx, FfInitVals *initvals);\n\n\t// Splits all wide ports in this memory into equivalent narrow ones.\n\t// This function performs no modifications at all to the actual\n\t// netlist unless and until emit() is called.\n\tvoid narrow();\n\n\t// If write port idx2 currently has priority over write port idx1,\n\t// inserts extra logic on idx1's enable signal to disable writes\n\t// when idx2 is writing to the same address, then removes the priority\n\t// from the priority mask. If there is a memory port that is\n\t// transparent with idx1, but not with idx2, that port is converted\n\t// to use soft transparency logic.\n\tvoid emulate_priority(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Creates soft-transparency logic on read port ridx, bypassing the\n\t// data from write port widx. Should only be called when ridx is\n\t// transparent wrt widx in the first place. Once we're done, the\n\t// transparency_mask bit will be cleared, and the collision_x_mask\n\t// bit will be set instead (since whatever value is read will be\n\t// replaced by the soft transparency logic).\n\tvoid emulate_transparency(int widx, int ridx, FfInitVals *initvals);\n\n\t// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).\n\t// Specifically, takes care of priority masks: any priority relations\n\t// that idx2 had are replicated onto idx1, unless they conflict with\n\t// priorities already present on idx1, in which case emulate_priority\n\t// is called. Likewise, ensures transparency and undefined collision\n\t// masks of all read ports have the same values for both ports,\n\t// calling emulate_transparency if necessary.\n\tvoid prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares for merging read port idx2 into idx1.\n\t// Specifically, makes sure the transparency and undefined collision\n\t// masks of both ports are equal, by changing undefined behavior\n\t// of one port to the other's defined behavior, or by calling\n\t// emulate_transparency if necessary.\n\tvoid prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares the memory for widening a port to a given width. This\n\t// involves ensuring that start_offset and size are aligned to the\n\t// target width.\n\tvoid widen_prep(int wide_log2);\n\n\t// Widens a write port up to a given width. The newly port is\n\t// equivalent to the original, made by replicating enable/data bits\n\t// and masking enable bits with decoders on the low part of the\n\t// original address.\n\tvoid widen_wr_port(int idx, int wide_log2);\n\n\t// Emulates a sync read port's enable functionality in soft logic,\n\t// changing the actual read port's enable to be always-on.\n\tvoid emulate_rden(int idx, FfInitVals *initvals);\n\n\t// Emulates a sync read port's initial/reset value functionality in\n\t// soft logic, removing it from the actual read port.\n\tvoid emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals);\n\n\t// Given a read port with ce_over_srst set, converts it to a port\n\t// with ce_over_srst unset without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_ce_over_srst(int idx);\n\n\t// Given a read port with ce_over_srst unset, converts it to a port\n\t// with ce_over_srst set without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_srst_over_ce(int idx);\n\n\t// Returns true iff emulate_read_first makes sense to call.\n\tbool emulate_read_first_ok();\n\n\t// Emulates all read-first read-write port relationships in terms of\n\t// all-transparent ports, by delaying all write ports by one cycle.\n\t// This can only be used when all read ports and all write ports are\n\t// in the same clock domain.\n\tvoid emulate_read_first(FfInitVals *initvals);\n\n\tMem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}\n};\n\n// MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined\nclass MemContents {\npublic:\n\tclass range; class iterator;\n\tusing addr_t = uint32_t;\nprivate:\n\t// we ban _addr_width == sizeof(addr_t) * 8 because it adds too many cornercases\n\tint _addr_width;\n\tint _data_width;\n\tRTLIL::Const _default_value;\n\t// for each range, store the concatenation of the words at the start address\n\t// invariants:\n\t// - no overlapping or adjacent ranges\n\t// - no empty ranges\n\t// - all Consts are a multiple of the word size\n\tstd::map<addr_t, RTLIL::Const> _values;\n\t// returns an iterator to the range containing addr, if it exists, or the first range past addr\n\tstd::map<addr_t, RTLIL::Const>::iterator _range_at(addr_t addr) const;\n\taddr_t _range_size(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->second.size() / _data_width; }\n\taddr_t _range_begin(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->first; }\n\taddr_t _range_end(std::map<addr_t, RTLIL::Const>::iterator it) const { return _range_begin(it) + _range_size(it); }\n\t// check if the iterator points to a range containing addr\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const;\n\t// check if the iterator points to a range containing [begin_addr, end_addr). assumes end_addr >= begin_addr.\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// check if the iterator points to a range overlapping with [begin_addr, end_addr)\n\tbool _range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// return the offset the addr would have in the range at `it`\n\tsize_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }\n\t// assuming _range_contains(it, addr), return an iterator pointing to the data at addr\n\tstd::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits().begin() + _range_offset(it, addr); }\n\t// internal version of reserve_range that returns an iterator to the range\n\tstd::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);\n\t// write a single word at addr, return iterator to next word\n\tstd::vector<State>::iterator _range_write(std::vector<State>::iterator it, RTLIL::Const const &data);\npublic:\n\tclass range {\n\t\tint _data_width;\n\t\taddr_t _base;\n\t\tRTLIL::Const const &_values;\n\t\tfriend class iterator;\n\t\trange(int data_width, addr_t base, RTLIL::Const const &values)\n\t\t: _data_width(data_width), _base(base), _values(values) {}\n\tpublic:\n\t\taddr_t base() const { return _base; }\n\t\taddr_t size() const { return ((addr_t) _values.size()) / _data_width; }\n\t\taddr_t limit() const { return _base + size(); }\n\t\tRTLIL::Const const &concatenated() const { return _values; }\n\t\tRTLIL::Const operator[](addr_t addr) const {\n\t\t\tlog_assert(addr - _base < size());\n\t\t\treturn _values.extract((addr - _base) * _data_width, _data_width);\n\t\t}\n\t\tRTLIL::Const at_offset(addr_t offset) const { return (*this)[_base + offset]; }\n\t};\n\tclass iterator {\n\t\tMemContents const *_memory;\n\t\t// storing addr instead of an iterator gives more well-defined behaviour under insertions/deletions\n\t\t// use ~0 for end so that all end iterators compare the same\n\t\taddr_t _addr;\n\t\tfriend class MemContents;\n\t\titerator(MemContents const *memory, addr_t addr) : _memory(memory), _addr(addr) {}\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = range;\n\t\tusing pointer = arrow_proxy<range>;\n\t\tusing reference = range;\n\t\tusing difference_type = addr_t;\n\t\treference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); }\n\t\tpointer operator->() const { return arrow_proxy<range>(**this); }\n\t\tbool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; }\n\t\tbool operator ==(iterator const &other) const { return !(*this != other); }\n\t\titerator &operator++();\n\t};\n\tMemContents(int addr_width, int data_width, RTLIL::Const default_value)\n\t\t: _addr_width(addr_width), _data_width(data_width)\n\t\t, _default_value((default_value.extu(data_width), std::move(default_value)))\n\t{ log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); log_assert(_data_width > 0); }\n\tMemContents(int addr_width, int data_width) : MemContents(addr_width, data_width, RTLIL::Const(State::Sx, data_width)) {}\n\texplicit MemContents(Mem *mem);\n\tint addr_width() const { return _addr_width; }\n\tint data_width() const { return _data_width; }\n\tRTLIL::Const const &default_value() const { return _default_value; }\n\t// return the value at the address if it exists, the default_value of the memory otherwise. address must not exceed 2**addr_width.\n\tRTLIL::Const operator [](addr_t addr) const;\n\t// return the number of defined words in the range [begin_addr, end_addr)\n\taddr_t count_range(addr_t begin_addr, addr_t end_addr) const;\n\t// allocate memory for the range [begin_addr, end_addr), but leave the contents undefined.\n\tvoid reserve_range(addr_t begin_addr, addr_t end_addr) { _reserve_range(begin_addr, end_addr); }\n\t// insert multiple words (provided as a single concatenated RTLIL::Const) at the given address, overriding any previous assignment.\n\tvoid insert_concatenated(addr_t addr, RTLIL::Const const &values);\n\t// insert multiple words at the given address, overriding any previous assignment.\n\ttemplate<typename Iterator> void insert_range(addr_t addr, Iterator begin, Iterator end) {\n\t\tauto words = end - begin;\n\t\tlog_assert(addr < (addr_t)(1<<_addr_width)); log_assert(words <= (addr_t)(1<<_addr_width) - addr);\n\t\tauto range = _reserve_range(addr, addr + words);\n\t\tauto it = _range_data(range, addr);\n\t\tfor(; begin != end; ++begin)\n\t\t\tit = _range_write(it, *begin);\n\t}\n\t// undefine all words in the range [begin_addr, end_addr)\n\tvoid clear_range(addr_t begin_addr, addr_t end_addr);\n\t// check invariants, abort if invariants failed\n\tvoid check();\n\titerator end() const { return iterator(nullptr, ~(addr_t) 0); }\n\titerator begin() const { return _values.empty() ? end() : iterator(this, _values.begin()->first); }\n\tbool empty() const { return _values.empty(); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"modtools.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MODTOOLS_H\n#define MODTOOLS_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ModIndex : public RTLIL::Monitor\n{\n\tstruct PortInfo {\n\t\tRTLIL::Cell* cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tPortInfo() : cell(), port(), offset() { }\n\t\tPortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }\n\n\t\tbool operator<(const PortInfo &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (offset != other.offset)\n\t\t\t\treturn offset < other.offset;\n\t\t\treturn port < other.port;\n\t\t}\n\n\t\tbool operator==(const PortInfo &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tstruct SigBitInfo\n\t{\n\t\tbool is_input, is_output;\n\t\tpool<PortInfo> ports;\n\n\t\tSigBitInfo() : is_input(false), is_output(false) { }\n\n\t\tbool operator==(const SigBitInfo &other) const {\n\t\t\treturn is_input == other.is_input && is_output == other.is_output && ports == other.ports;\n\t\t}\n\n\t\tvoid merge(const SigBitInfo &other)\n\t\t{\n\t\t\tis_input = is_input || other.is_input;\n\t\t\tis_output = is_output || other.is_output;\n\t\t\tports.insert(other.ports.begin(), other.ports.end());\n\t\t}\n\t};\n\n\tSigMap sigmap;\n\tRTLIL::Module *module;\n\tstd::map<RTLIL::SigBit, SigBitInfo> database;\n\tint auto_reload_counter;\n\tbool auto_reload_module;\n\n\tvoid port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.insert(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tvoid port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.erase(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tconst SigBitInfo &info(RTLIL::SigBit bit)\n\t{\n\t\treturn database[sigmap(bit)];\n\t}\n\n\tvoid reload_module(bool reset_sigmap = true)\n\t{\n\t\tif (reset_sigmap) {\n\t\t\tsigmap.clear();\n\t\t\tsigmap.set(module);\n\t\t}\n\n\t\tdatabase.clear();\n\t\tfor (auto wire : module->wires())\n\t\t\tif (wire->port_input || wire->port_output)\n\t\t\t\tfor (int i = 0; i < GetSize(wire); i++) {\n\t\t\t\t\tRTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));\n\t\t\t\t\tif (bit.wire && wire->port_input)\n\t\t\t\t\t\tdatabase[bit].is_input = true;\n\t\t\t\t\tif (bit.wire && wire->port_output)\n\t\t\t\t\t\tdatabase[bit].is_output = true;\n\t\t\t\t}\n\t\tfor (auto cell : module->cells())\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tport_add(cell, conn.first, conn.second);\n\n\t\tif (auto_reload_module) {\n\t\t\tif (++auto_reload_counter > 2)\n\t\t\t\tlog_warning(\"Auto-reload in ModIndex -- possible performance bug!\\n\");\n\t\t\tauto_reload_module = false;\n\t\t}\n\t}\n\n\tvoid check()\n\t{\n#ifndef NDEBUG\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (auto it : database)\n\t\t\tlog_assert(it.first == sigmap(it.first));\n\n\t\tauto database_bak = std::move(database);\n\t\treload_module(false);\n\n\t\tif (!(database == database_bak))\n\t\t{\n\t\t\tfor (auto &it : database_bak)\n\t\t\t\tif (!database.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database_bak, not database: %s\\n\", log_signal(it.first));\n\n\t\t\tfor (auto &it : database)\n\t\t\t\tif (!database_bak.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database, not database_bak: %s\\n\", log_signal(it.first));\n\t\t\t\telse if (!(it.second == database_bak.at(it.first)))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Different content for database[%s].\\n\", log_signal(it.first));\n\n\t\t\tlog_assert(database == database_bak);\n\t\t}\n#endif\n\t}\n\n\tvoid notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override\n\t{\n\t\tlog_assert(module == cell->module);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tport_del(cell, port, old_sig);\n\t\tport_add(cell, port, sig);\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override\n\t{\n\t\tlog_assert(module == mod);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (int i = 0; i < GetSize(sigsig.first); i++)\n\t\t{\n\t\t\tRTLIL::SigBit lhs = sigmap(sigsig.first[i]);\n\t\t\tRTLIL::SigBit rhs = sigmap(sigsig.second[i]);\n\t\t\tbool has_lhs = database.count(lhs) != 0;\n\t\t\tbool has_rhs = database.count(rhs) != 0;\n\n\t\t\tif (!has_lhs && !has_rhs) {\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t} else\n\t\t\tif (!has_rhs) {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\tlhs = sigmap(lhs);\n\t\t\t\tif (lhs.wire)\n\t\t\t\t\tdatabase[lhs] = new_info;\n\t\t\t} else\n\t\t\tif (!has_lhs) {\n\t\t\t\tSigBitInfo new_info = database.at(rhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t} else {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tnew_info.merge(database.at(rhs));\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tvoid notify_blackout(RTLIL::Module *mod) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)\n\t{\n\t\tauto_reload_counter = 0;\n\t\tauto_reload_module = true;\n\t\tmodule->monitors.insert(this);\n\t}\n\n\t~ModIndex()\n\t{\n\t\tmodule->monitors.erase(this);\n\t}\n\n\tSigBitInfo *query(RTLIL::SigBit bit)\n\t{\n\t\tif (auto_reload_module)\n\t\t\treload_module();\n\n\t\tauto it = database.find(sigmap(bit));\n\t\tif (it == database.end())\n\t\t\treturn nullptr;\n\t\telse\n\t\t\treturn &it->second;\n\t}\n\n\tbool query_is_input(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_input;\n\t}\n\n\tbool query_is_output(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_output;\n\t}\n\n\tpool<PortInfo> &query_ports(RTLIL::SigBit bit)\n\t{\n\t\tstatic pool<PortInfo> empty_result_set;\n\t\tSigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn empty_result_set;\n\t\treturn info->ports;\n\t}\n\n\tvoid dump_db()\n\t{\n\t\tlog(\"--- ModIndex Dump ---\\n\");\n\n\t\tif (auto_reload_module) {\n\t\t\tlog(\"AUTO-RELOAD\\n\");\n\t\t\treload_module();\n\t\t}\n\n\t\tfor (auto &it : database) {\n\t\t\tlog(\"BIT %s:\\n\", log_signal(it.first));\n\t\t\tif (it.second.is_input)\n\t\t\t\tlog(\" PRIMARY INPUT\\n\");\n\t\t\tif (it.second.is_output)\n\t\t\t\tlog(\" PRIMARY OUTPUT\\n\");\n\t\t\tfor (auto &port : it.second.ports)\n\t\t\t\tlog(\" PORT: %s.%s[%d] (%s)\\n\", log_id(port.cell),\n\t\t\t\t\t\tlog_id(port.port), port.offset, log_id(port.cell->type));\n\t\t}\n\t}\n};\n\nstruct ModWalker\n{\n\tstruct PortBit\n\t{\n\t\tRTLIL::Cell *cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\t\tPortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}\n\n\t\tbool operator<(const PortBit &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (port != other.port)\n\t\t\t\treturn port < other.port;\n\t\t\treturn offset < other.offset;\n\t\t}\n\n\t\tbool operator==(const PortBit &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tRTLIL::Design *design;\n\tRTLIL::Module *module;\n\n\tCellTypes ct;\n\tSigMap sigmap;\n\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_drivers;\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_consumers;\n\tpool<RTLIL::SigBit> signal_inputs, signal_outputs;\n\n\tdict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;\n\n\tvoid add_wire(RTLIL::Wire *wire)\n\t{\n\t\tif (wire->port_input) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_inputs.insert(bit);\n\t\t}\n\n\t\tif (wire->port_output) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_outputs.insert(bit);\n\t\t}\n\t}\n\n\tvoid add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)\n\t{\n\t\tfor (int i = 0; i < int(bits.size()); i++)\n\t\t\tif (bits[i].wire != NULL) {\n\t\t\t\tPortBit pbit {cell, port, i};\n\t\t\t\tif (is_output) {\n\t\t\t\t\tsignal_drivers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_outputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t\tif (is_input) {\n\t\t\t\t\tsignal_consumers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_inputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\tvoid add_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (ct.cell_known(cell->type)) {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second),\n\t\t\t\t\t\tct.cell_output(cell->type, conn.first),\n\t\t\t\t\t\tct.cell_input(cell->type, conn.first));\n\t\t} else {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second), true, true);\n\t\t}\n\t}\n\n\tModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)\n\t{\n\t\tct.setup(design);\n\t\tif (module)\n\t\t\tsetup(module);\n\t}\n\n\tvoid setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)\n\t{\n\t\tthis->module = module;\n\n\t\tsigmap.set(module);\n\n\t\tsignal_drivers.clear();\n\t\tsignal_consumers.clear();\n\t\tsignal_inputs.clear();\n\t\tsignal_outputs.clear();\n\t\tcell_inputs.clear();\n\t\tcell_outputs.clear();\n\n\t\tfor (auto &it : module->wires_)\n\t\t\tadd_wire(it.second);\n\t\tfor (auto &it : module->cells_)\n\t\t\tif (filter_ct == NULL || filter_ct->cell_known(it.second->type))\n\t\t\t\tadd_cell(it.second);\n\t}\n\n\t// get_* methods -- single RTLIL::SigBit\n\n\tinline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_drivers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_consumers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_inputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_outputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- container of RTLIL::SigBit's (always by reference)\n\n\ttemplate<typename T>\n\tinline bool get_drivers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_drivers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_consumers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_consumers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_inputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_outputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- call by RTLIL::SigSpec (always by value)\n\n\tbool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_drivers(result, bits);\n\t}\n\n\tbool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_consumers(result, bits);\n\t}\n\n\tbool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_inputs(result, bits);\n\t}\n\n\tbool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_outputs(result, bits);\n\t}\n\n\t// has_* methods -- call by reference\n\n\ttemplate<typename T>\n\tinline bool has_drivers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_consumers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_inputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_outputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n\n\t// has_* methods -- call by value\n\n\tinline bool has_drivers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\tinline bool has_consumers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\tinline bool has_inputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\tinline bool has_outputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"qcsat.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef QCSAT_H\n#define QCSAT_H\n\n#include \"kernel/satgen.h\"\n#include \"kernel/modtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// This is a helper class meant for easy construction of quick SAT queries\n// to a combinatorial input cone of some set of signals, meant for SAT-based\n// optimizations. Various knobs are provided to set just how much of the\n// cone should be included in the model — since this class is meant for\n// optimization, it should not be a correctness problem when some cells are\n// skipped and the solver spuriously returns SAT with a solution that\n// cannot exist in reality due to skipped constraints (ie. only UNSAT results\n// from this class should be considered binding).\nstruct QuickConeSat {\n\tModWalker &modwalker;\n\tezSatPtr ez;\n\tSatGen satgen;\n\n\t// The effort level knobs.\n\n\t// The maximum \"complexity level\" of cells that will be imported.\n\t// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa\n\t// - 2: addition, subtraction, greater/less than comparisons, lcu\n\t// - 3: shifts\n\t// - 4: multiplication, division, power\n\tint max_cell_complexity = 2;\n\t// The maximum number of cells to import, or 0 for no limit.\n\tint max_cell_count = 0;\n\t// If non-0, skip importing cells with more than this number of output bits.\n\tint max_cell_outs = 0;\n\n\t// Internal state.\n\tpool<RTLIL::Cell*> imported_cells;\n\tpool<RTLIL::Wire*> imported_onehot;\n\tpool<RTLIL::SigBit> bits_queue;\n\n\tQuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}\n\n\t// Imports a signal into the SAT solver, queues its input cone to be\n\t// imported in the next prepare() call.\n\tstd::vector<int> importSig(SigSpec sig);\n\tint importSigBit(SigBit bit);\n\n\t// Imports the input cones of all previously importSig'd signals into\n\t// the SAT solver.\n\tvoid prepare();\n\n\t// Returns the \"complexity level\" of a given cell.\n\tstatic int cell_complexity(RTLIL::Cell *cell);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"register.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic dict<char*, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic std::vector<int> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t\tif (idx) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\t}\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tif (!p[0])\n\t\t\treturn 0;\n\n\t\tauto it = global_id_index_.find((char*)p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tlog_assert(p[1] != 0);\n\t\tfor (const char *c = p; *c; c++)\n\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tif (global_id_storage_.empty()) {\n\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t}\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (!destruct_guard_ok || !idx)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tlog_assert(refcount == 0);\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn c_str()[0] == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(Args... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\nnamespace RTLIL {\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tmutable backing_tag tag;\n\tunion {\n\t\tmutable bitvectype bits_;\n\t\tmutable std::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits() const;\n\tstd::string& get_str() const;\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tstd::vector<RTLIL::State>& bits();\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\tvoid bitvectorize() const;\n\n\tvoid append(const RTLIL::Const &other);\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const& parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator& operator++(int) { ++idx; return *this; }\n\t\tconst_iterator& operator--(int) { --idx; return *this; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tbits().resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbitvectype& bv = bits();\n\t\tbv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(size());\n\t\tfor (auto b : *this)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n\tint from_hdl_index(int hdl_index) {\n\t\tint zero_index = hdl_index - start_offset;\n\t\tint rtlil_index = upto ? width - 1 - zero_index : zero_index;\n\t\treturn rtlil_index >= 0 && rtlil_index < width ? rtlil_index : INT_MIN;\n\t}\n\n\tint to_hdl_index(int rtlil_index) {\n\t\tif (rtlil_index < 0 || rtlil_index >= width)\n\t\t\treturn INT_MIN;\n\t\tint zero_index = upto ? width - 1 - rtlil_index : rtlil_index;\n\t\treturn zero_index + start_offset;\n\t}\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString ¶mname) const;\n\tvoid unsetParam(const RTLIL::IdString ¶mname);\n\tvoid setParam(const RTLIL::IdString ¶mname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString ¶mname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"register.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\t// Prefer overriding 'Pass::on_shutdown()' if possible\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tenum SelectPartials : unsigned char {\n\t\tSELECT_ALL = 0, // include partial modules\n\t\tSELECT_WHOLE_ONLY = 1, // ignore partial modules\n\t\tSELECT_WHOLE_WARN = 2, // call log_warning on partial module\n\t\tSELECT_WHOLE_ERR = 3, // call log_error on partial module\n\t\tSELECT_WHOLE_CMDERR = 4 // call log_cmd_error on partial module\n\t};\n\n\tenum SelectBoxes : unsigned char {\n\t\tSB_ALL = 0, // include boxed modules\n\t\tSB_WARN = 1, // helper for log_warning (not for direct use)\n\t\tSB_ERR = 2, // helper for log_error (not for direct use)\n\t\tSB_CMDERR = 3, // helper for log_cmd_error (not for direct use)\n\t\tSB_UNBOXED_ONLY = 4, // ignore boxed modules\n\t\tSB_UNBOXED_WARN = 5, // call log_warning on boxed module\n\t\tSB_UNBOXED_ERR = 6, // call log_error on boxed module\n\t\tSB_UNBOXED_CMDERR = 7, // call log_cmd_error on boxed module\n\t\tSB_INCL_WB = 8, // helper for white boxes (not for direct use)\n\t\tSB_EXCL_BB_ONLY = 12, // ignore black boxes, but not white boxes\n\t\tSB_EXCL_BB_WARN = 13, // call log_warning on black boxed module\n\t\tSB_EXCL_BB_ERR = 14, // call log_error on black boxed module\n\t\tSB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct NamedObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic dict<char*, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic std::vector<int> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t\tif (idx) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\t}\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tif (!p[0])\n\t\t\treturn 0;\n\n\t\tauto it = global_id_index_.find((char*)p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tlog_assert(p[1] != 0);\n\t\tfor (const char *c = p; *c; c++)\n\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tif (global_id_storage_.empty()) {\n\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t}\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (!destruct_guard_ok || !idx)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tlog_assert(refcount == 0);\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn c_str()[0] == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(Args... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\nnamespace RTLIL {\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tmutable backing_tag tag;\n\tunion {\n\t\tmutable bitvectype bits_;\n\t\tmutable std::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits() const;\n\tstd::string& get_str() const;\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tstd::vector<RTLIL::State>& bits();\n\tbool as_bool() const;\n\n\t// Convert the constant value to a C++ int.\n\t// NOTE: If the constant is too wide to fit in int (32 bits) this will\n\t// truncate any higher bits, potentially over/underflowing. Consider using\n\t// try_as_int, as_int_saturating, or guarding behind convertible_to_int\n\t// instead.\n\tint as_int(bool is_signed = false) const;\n\n\t// Returns true iff the constant can be converted to an int without\n\t// over/underflow.\n\tbool convertible_to_int(bool is_signed = false) const;\n\n\t// Returns the constant's value as an int if it can be represented without\n\t// over/underflow, or std::nullopt otherwise.\n\tstd::optional<int> try_as_int(bool is_signed = false) const;\n\n\t// Returns the constant's value as an int if it can be represented without\n\t// over/underflow, otherwise the max/min value for int depending on the sign.\n\tint as_int_saturating(bool is_signed = false) const;\n\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\tvoid bitvectorize() const;\n\n\tvoid append(const RTLIL::Const &other);\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const& parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator& operator++(int) { ++idx; return *this; }\n\t\tconst_iterator& operator--(int) { --idx; return *this; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tbits().resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbitvectype& bv = bits();\n\t\tbv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(size());\n\t\tfor (auto b : *this)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::NamedObject : public RTLIL::AttrObject\n{\n\tRTLIL::IdString name;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\n\t// Convert the SigSpec to a C++ int, assuming all bits are constant.\n\t// NOTE: If the value is too wide to fit in int (32 bits) this will\n\t// truncate any higher bits, potentially over/underflowing. Consider using\n\t// try_as_int, as_int_saturating, or guarding behind convertible_to_int\n\t// instead.\n\tint as_int(bool is_signed = false) const;\n\n\t// Returns true iff the SigSpec is constant and can be converted to an int\n\t// without over/underflow.\n\tbool convertible_to_int(bool is_signed = false) const;\n\n\t// Returns the SigSpec's value as an int if it is a constant and can be\n\t// represented without over/underflow, or std::nullopt otherwise.\n\tstd::optional<int> try_as_int(bool is_signed = false) const;\n\n\t// Returns an all constant SigSpec's value as an int if it can be represented\n\t// without over/underflow, otherwise the max/min value for int depending on\n\t// the sign.\n\tint as_int_saturating(bool is_signed = false) const;\n\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\t// selection includes boxed modules\n\tbool selects_boxes;\n\t// selection covers full design, including boxed modules\n\tbool complete_selection;\n\t// selection covers full design, not including boxed modules\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\tRTLIL::Design *current_design;\n\n\t// create a new selection\n\tSelection(\n\t\t// should the selection cover the full design\n\t\tbool full = true,\n\t\t// should the selection include boxed modules\n\t\tbool boxes = false,\n\t\t// the design to select from\n\t\tRTLIL::Design *design = nullptr\n\t) :\n\t\tselects_boxes(boxes), complete_selection(full && boxes), full_selection(full && !boxes), current_design(design) { }\n\n\t// checks if the given module exists in the current design and is a\n\t// boxed module, warning the user if the current design is not set\n\tbool boxed_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is included in this selection\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is wholly included in this selection,\n\t// i.e. not partially selected\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given member from the given module is included in this\n\t// selection\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\t// optimizes this selection for the given design by:\n\t// - removing non-existent modules and members, any boxed modules and\n\t// their members (if selection does not include boxes), and any\n\t// partially selected modules with no selected members;\n\t// - marking partially selected modules as wholly selected if all\n\t// members of that module are selected; and\n\t// - marking selection as a complete_selection if all modules in the\n\t// given design are selected, or a full_selection if it does not\n\t// include boxes.\n\tvoid optimize(RTLIL::Design *design);\n\n\t// checks if selection covers full design (may or may not include\n\t// boxed-modules)\n\tbool selects_all() const {\n\t\treturn full_selection || complete_selection;\n\t}\n\n\t// add whole module to this selection\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!selects_all() && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t\tif (module->get_blackbox_attribute())\n\t\t\t\tselects_boxes = true;\n\t\t}\n\t}\n\n\t// add member of module to this selection\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!selects_all() && selected_modules.count(module->name) == 0) {\n\t\t\tselected_members[module->name].insert(member->name);\n\t\t\tif (module->get_blackbox_attribute())\n\t\t\t\tselects_boxes = true;\n\t\t}\n\t}\n\n\t// checks if selection is empty\n\tbool empty() const {\n\t\treturn !selects_all() && selected_modules.empty() && selected_members.empty();\n\t}\n\n\t// clear this selection, leaving it empty\n\tvoid clear();\n\n\t// create a new selection which is empty\n\tstatic Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };\n\n\t// create a new selection with all non-boxed modules\n\tstatic Selection FullSelection(RTLIL::Design *design = nullptr) { return Selection(true, false, design); };\n\n\t// create a new selection with all modules, including boxes\n\tstatic Selection CompleteSelection(RTLIL::Design *design = nullptr) { return Selection(true, true, design); };\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module() const;\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\t// checks if the given module is included in the current selection\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given module is wholly included in the current\n\t// selection, i.e. not partially selected\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\n\t// checks if the given member from the given module is included in the\n\t// current selection\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\t// checks if the given module is included in the current selection\n\tbool selected_module(RTLIL::Module *mod) const;\n\n\t// checks if the given module is wholly included in the current\n\t// selection, i.e. not partially selected\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\t// push the given selection to the selection stack\n\tvoid push_selection(RTLIL::Selection sel);\n\t// push a new selection to the selection stack, with nothing selected\n\tvoid push_empty_selection();\n\t// push a new selection to the selection stack, with all non-boxed\n\t// modules selected\n\tvoid push_full_selection();\n\t// push a new selection to the selection stack, with all modules\n\t// selected including boxes\n\tvoid push_complete_selection();\n\t// pop the current selection from the stack, returning to a full\n\t// selection (no boxes) if the stack is empty\n\tvoid pop_selection();\n\n\t// get the current selection\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\t// get the current selection\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\t// is the current selection a full selection (no boxes)\n\tbool full_selection() const {\n\t\treturn selection().full_selection;\n\t}\n\n\t// is the given module in the current selection\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\t// is the given member of the given module in the current selection\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\t// add whole module to the current selection\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tRTLIL::Selection &sel = selection();\n\t\tsel.select(module);\n\t}\n\n\t// add member of module to the current selection\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tRTLIL::Selection &sel = selection();\n\t\tsel.select(module, member);\n\t}\n\n\n\t// returns all selected modules\n\tstd::vector<RTLIL::Module*> selected_modules(\n\t\t// controls if partially selected modules are included\n\t\tRTLIL::SelectPartials partials = SELECT_ALL,\n\t\t// controls if boxed modules are included\n\t\tRTLIL::SelectBoxes boxes = SB_UNBOXED_WARN\n\t) const;\n\n\t// returns all selected modules, and may include boxes\n\tstd::vector<RTLIL::Module*> all_selected_modules() const { return selected_modules(SELECT_ALL, SB_ALL); }\n\t// returns all selected unboxed modules, silently ignoring any boxed\n\t// modules in the selection\n\tstd::vector<RTLIL::Module*> selected_unboxed_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_ONLY); }\n\t// returns all selected unboxed modules, warning the user if any boxed\n\t// modules have been ignored\n\tstd::vector<RTLIL::Module*> selected_unboxed_modules_warn() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }\n\n\t[[deprecated(\"Use select_unboxed_whole_modules() to maintain prior behaviour, or consider one of the other selected whole module helpers.\")]]\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_WARN); }\n\t// returns all selected whole modules, silently ignoring partially\n\t// selected modules, and may include boxes\n\tstd::vector<RTLIL::Module*> all_selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_ALL); }\n\t// returns all selected whole modules, warning the user if any partially\n\t// selected or boxed modules have been ignored; optionally includes\n\t// selected whole modules with the 'whitebox' attribute\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(\n\t\t// should whole modules with the 'whitebox' attribute be\n\t\t// included\n\t\tbool include_wb = false\n\t) const { return selected_modules(SELECT_WHOLE_WARN, include_wb ? SB_EXCL_BB_WARN : SB_UNBOXED_WARN); }\n\t// returns all selected unboxed whole modules, silently ignoring\n\t// partially selected or boxed modules\n\tstd::vector<RTLIL::Module*> selected_unboxed_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_ONLY); }\n\t// returns all selected unboxed whole modules, warning the user if any\n\t// partially selected or boxed modules have been ignored\n\tstd::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tbool is_selected() const;\n\tbool is_selected_whole() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\tstd::vector<RTLIL::Memory*> selected_memories() const;\n\tstd::vector<RTLIL::Process*> selected_processes() const;\n\tstd::vector<RTLIL::NamedObject*> selected_members() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n\tint from_hdl_index(int hdl_index) {\n\t\tint zero_index = hdl_index - start_offset;\n\t\tint rtlil_index = upto ? width - 1 - zero_index : zero_index;\n\t\treturn rtlil_index >= 0 && rtlil_index < width ? rtlil_index : INT_MIN;\n\t}\n\n\tint to_hdl_index(int rtlil_index) {\n\t\tif (rtlil_index < 0 || rtlil_index >= width)\n\t\t\treturn INT_MIN;\n\t\tint zero_index = upto ? width - 1 - rtlil_index : rtlil_index;\n\t\treturn zero_index + start_offset;\n\t}\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString ¶mname) const;\n\tvoid unsetParam(const RTLIL::IdString ¶mname);\n\tvoid setParam(const RTLIL::IdString ¶mname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString ¶mname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::NamedObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"satgen.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tSigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string name = pf + (bit.wire->width == 1 ? stringf(\"%s\", log_id(bit.wire)) : stringf(\"%s [%d]\", log_id(bit.wire->name), bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"scopeinfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const\n\t\t{\n\t\t\th.eat(scope_name);\n\t\t\th.eat(target);\n\t\t\treturn h;\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(ptr); return h; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty() && object->name.isPublic())\n\t\tpath.push_back(object->name);\n\tif (!path.empty() && !(object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\"))) {\n\t\tpath.pop_back();\n\t\tpath.push_back(object->name);\n\t}\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\")) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else if (object->has_attribute(ID::hdlname)) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"sexpr.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Emily Schmidt <emily@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SEXPR_H\n#define SEXPR_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nclass SExpr {\npublic:\n\tstd::variant<std::vector<SExpr>, std::string> _v;\npublic:\n\tSExpr(std::string a) : _v(std::move(a)) {}\n SExpr(const char *a) : _v(a) {}\n // FIXME: should maybe be defined for all integral types\n\tSExpr(int n) : _v(std::to_string(n)) {}\n\tSExpr(std::vector<SExpr> const &l) : _v(l) {}\n\tSExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}\n // It would be nicer to have an std::initializer_list constructor,\n // but that causes confusing issues with overload resolution sometimes.\n template<typename... Args> static SExpr list(Args&&... args) {\n\t return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n }\n bool is_atom() const { return std::holds_alternative<std::string>(_v); }\n std::string const &atom() const { return std::get<std::string>(_v); }\n bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }\n std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }\n\tstd::string to_string() const;\n};\n\nstd::ostream &operator<<(std::ostream &os, SExpr const &sexpr);\n\nnamespace SExprUtil {\n // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list`\n template<typename... Args> SExpr list(Args&&... args) {\n\t return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n }\n}\n\n// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout.\nclass SExprWriter {\n std::ostream &os;\n int _max_line_width;\n int _indent = 0;\n int _pos = 0;\n // If _pending_nl is set, print a newline before the next character.\n // This lets us \"undo\" the last newline so we can put\n // closing parentheses or a hanging comment on the same line.\n bool _pending_nl = false;\n // Unclosed parentheses (boolean stored is indent_rest)\n\tvector<bool> _unclosed;\n // Used only for push() and pop() (stores _unclosed.size())\n\tvector<size_t> _unclosed_stack;\n\tvoid nl_if_pending();\n void puts(std::string_view s);\n int check_fit(SExpr const &sexpr, int space);\n void print(SExpr const &sexpr, bool close = true, bool indent_rest = true);\npublic:\n SExprWriter(std::ostream &os, int max_line_width = 80)\n : os(os)\n , _max_line_width(max_line_width)\n {}\n // Print an s-expr.\n SExprWriter &operator <<(SExpr const &sexpr) {\n print(sexpr);\n _pending_nl = true;\n return *this;\n }\n // Print an s-expr (which must be a list), but leave room for extra elements\n // which may be printed using either << or further calls to open.\n // If indent_rest = false, the remaining elements are not intended\n // (for avoiding unreasonable indentation on deeply nested structures).\n void open(SExpr const &sexpr, bool indent_rest = true) {\n log_assert(sexpr.is_list());\n print(sexpr, false, indent_rest);\n }\n // Close the s-expr opened with the last call to open\n // (if an argument is given, close that many s-exprs).\n void close(size_t n = 1);\n // push() remembers how many s-exprs are currently open\n\tvoid push() {\n\t\t_unclosed_stack.push_back(_unclosed.size());\n\t}\n // pop() closes all s-expr opened since the corresponding call to push()\n\tvoid pop() {\n\t\tauto t = _unclosed_stack.back();\n\t\tlog_assert(_unclosed.size() >= t);\n\t\tclose(_unclosed.size() - t);\n\t\t_unclosed_stack.pop_back();\n\t}\n // Print a comment.\n // If hanging = true, append it to the end of the last printed s-expr.\n\tvoid comment(std::string const &str, bool hanging = false);\n // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses.\n void flush() {\n nl_if_pending();\n }\n // Destructor closes any unclosed parentheses and flushes.\n ~SExprWriter();\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"sigtools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SIGTOOLS_H\n#define SIGTOOLS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct SigPool\n{\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(first->name);\n\t\t\th.eat(second);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tpool<bitDef_t> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.insert(bit);\n\t}\n\n\tvoid add(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.insert(bit);\n\t}\n\n\tvoid del(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.erase(bit);\n\t}\n\n\tvoid del(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.erase(bit);\n\t}\n\n\tvoid expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\t\tfor (int i = 0; i < GetSize(from); i++) {\n\t\t\tbitDef_t bit_from(from[i]), bit_to(to[i]);\n\t\t\tif (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)\n\t\t\t\tbits.insert(bit_to);\n\t\t}\n\t}\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tRTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tbool check(const RTLIL::SigBit &bit) const\n\t{\n\t\treturn bit.wire != NULL && bits.count(bit);\n\t}\n\n\tbool check_any(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool check_all(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tRTLIL::SigSpec export_one() const\n\t{\n\t\tfor (auto &bit : bits)\n\t\t\treturn RTLIL::SigSpec(bit.first, bit.second);\n\t\treturn RTLIL::SigSpec();\n\t}\n\n\tRTLIL::SigSpec export_all() const\n\t{\n\t\tpool<RTLIL::SigBit> sig;\n\t\tfor (auto &bit : bits)\n\t\t\tsig.insert(RTLIL::SigBit(bit.first, bit.second));\n\t\treturn sig;\n\t}\n\n\tsize_t size() const\n\t{\n\t\treturn bits.size();\n\t}\n};\n\ntemplate <typename T, class Compare = void>\nstruct SigSet\n{\n\tstatic_assert(!std::is_same<Compare,void>::value, \"Default value for `Compare' class not found for SigSet<T>. Please specify.\");\n\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(first->name);\n\t\t\th.eat(second);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tdict<bitDef_t, std::set<T, Compare>> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid insert(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data);\n\t}\n\n\tvoid insert(const RTLIL::SigSpec& sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data.begin(), data.end());\n\t}\n\n\tvoid erase(const RTLIL::SigSpec& sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].clear();\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data);\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data.begin(), data.end());\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, std::set<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, pool<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tstd::set<T> find(const RTLIL::SigSpec &sig)\n\t{\n\t\tstd::set<T> result;\n\t\tfind(sig, result);\n\t\treturn result;\n\t}\n\n\tbool has(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n};\n\ntemplate<typename T>\nclass SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};\ntemplate<typename T>\nusing sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;\ntemplate<typename T>\nclass SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};\n\n/**\n * SigMap wraps a union-find \"database\"\n * to map SigBits of a module to canonical representative SigBits.\n * SigBits that are connected share a set in the underlying database.\n * If a SigBit has a const state (impl: bit.wire is nullptr),\n * it's promoted to a representative.\n */\nstruct SigMap\n{\n\tmfp<SigBit> database;\n\n\tSigMap(RTLIL::Module *module = NULL)\n\t{\n\t\tif (module != NULL)\n\t\t\tset(module);\n\t}\n\n\tvoid swap(SigMap &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid clear()\n\t{\n\t\tdatabase.clear();\n\t}\n\n\t// Rebuild SigMap for all connections in module\n\tvoid set(RTLIL::Module *module)\n\t{\n\t\tint bitcount = 0;\n\t\tfor (auto &it : module->connections())\n\t\t\tbitcount += it.first.size();\n\n\t\tdatabase.clear();\n\t\tdatabase.reserve(bitcount);\n\n\t\tfor (auto &it : module->connections())\n\t\t\tadd(it.first, it.second);\n\t}\n\n\t// Add connections from \"from\" to \"to\", bit-by-bit\n\tvoid add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\n\t\tfor (int i = 0; i < GetSize(from); i++)\n\t\t{\n\t\t\tint bfi = database.lookup(from[i]);\n\t\t\tint bti = database.lookup(to[i]);\n\n\t\t\tconst RTLIL::SigBit &bf = database[bfi];\n\t\t\tconst RTLIL::SigBit &bt = database[bti];\n\n\t\t\tif (bf.wire || bt.wire)\n\t\t\t{\n\t\t\t\tdatabase.imerge(bfi, bti);\n\n\t\t\t\tif (bf.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bfi);\n\n\t\t\t\tif (bt.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bti);\n\t\t\t}\n\t\t}\n\t}\n\n\t// Add sig as disconnected from anything\n\tvoid add(const RTLIL::SigBit &bit)\n\t{\n\t\tconst auto &b = database.find(bit);\n\t\tif (b.wire != nullptr)\n\t\t\tdatabase.promote(bit);\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tadd(bit);\n\t}\n\n\tinline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }\n\n\t// Modify bit to its representative\n\tvoid apply(RTLIL::SigBit &bit) const\n\t{\n\t\tbit = database.find(bit);\n\t}\n\n\tvoid apply(RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tapply(bit);\n\t}\n\n\tRTLIL::SigBit operator()(RTLIL::SigBit bit) const\n\t{\n\t\tapply(bit);\n\t\treturn bit;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::SigSpec sig) const\n\t{\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::Wire *wire) const\n\t{\n\t\tSigSpec sig(wire);\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\t// All non-const bits\n\tRTLIL::SigSpec allbits() const\n\t{\n\t\tRTLIL::SigSpec sig;\n\t\tfor (const auto &bit : database)\n\t\t\tif (bit.wire != nullptr)\n\t\t\t\tsig.append(bit);\n\t\treturn sig;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif /* SIGTOOLS_H */\n",
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"timinginfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * (C) 2020 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tstd::optional<SigBit> get_connection(RTLIL::Cell *cell) {\n\t\t\tif (!cell->hasPort(name))\n\t\t\t\treturn {};\n\t\t\tauto &port = cell->getPort(name);\n\t\t\tif (offset >= port.size())\n\t\t\t\treturn {};\n\t\t\treturn port[offset];\n\t\t}\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(name);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(first);\n\t\t\th.eat(second);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"utils.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*>> backup_state;\n\tdict<Key, T> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>> class TopoSort\n{\n public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n if (rv.second) {\n \t nodes.push_back(n);\n\t\t edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\n// this class is used for implementing operator-> on iterators that return values rather than references\n// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained\ntemplate<class T>\nstruct arrow_proxy {\n\tT v;\n\texplicit arrow_proxy(T const & v) : v(v) {}\n\tT* operator->() { return &v; }\n};\n\ninline int ceil_log2(int x)\n{\n#if defined(__GNUC__)\n return x > 1 ? (8*sizeof(int)) - __builtin_clz(x-1) : 0;\n#else\n\tif (x <= 0)\n\t\treturn 0;\n\tfor (int i = 0; i < 32; i++)\n\t\tif (((x-1) >> i) == 0)\n\t\t\treturn i;\n\tlog_abort();\n#endif\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\n#ifdef YOSYS_ENABLE_TCL\nstruct Tcl_Interp;\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"yosys_common.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#define FRIEND_TEST(test_case_name, test_name) \\\n friend class test_case_name##_##test_name##_Test\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#else\n# error \"C++17 or later compatible compiler is required\"\n#endif\n\n#if defined(__has_cpp_attribute) && __has_cpp_attribute(gnu::cold)\n# define YS_COLD [[gnu::cold]]\n#else\n# define YS_COLD\n#endif\n\n#include \"kernel/io.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# error \"You've probably included hashlib.h under two namespace paths. Bad idea.\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\nusing hashlib::Hasher;\nusing hashlib::run_hash;\nusing hashlib::hash_ops;\nusing hashlib::mkhash_xorshift;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(*content);\n\t\treturn h;\n\t}\n};\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\
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"yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\n#ifdef YOSYS_ENABLE_TCL\nstruct Tcl_Interp;\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\nconst char* yosys_maybe_version();\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"yosys_common.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#define FRIEND_TEST(test_case_name, test_name) \\\n friend class test_case_name##_##test_name##_Test\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#else\n# error \"C++17 or later compatible compiler is required\"\n#endif\n\n#if defined(__has_cpp_attribute) && __has_cpp_attribute(gnu::cold)\n# define YS_COLD [[gnu::cold]]\n#else\n# define YS_COLD\n#endif\n\n#include \"kernel/io.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# error \"You've probably included hashlib.h under two namespace paths. Bad idea.\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\nusing hashlib::Hasher;\nusing hashlib::run_hash;\nusing hashlib::hash_ops;\nusing hashlib::mkhash_xorshift;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(*content);\n\t\treturn h;\n\t}\n};\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\nextern bool yosys_write_versions;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n// sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"yw.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YW_H\n#define YW_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/mem.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct IdPath : public std::vector<RTLIL::IdString>\n{\n\ttemplate<typename... T>\n\tIdPath(T&&... args) : std::vector<RTLIL::IdString>(std::forward<T>(args)...) { }\n\tIdPath prefix() const { return {begin(), end() - !empty()}; }\n\tstd::string str() const;\n\n\tbool has_address() const { int tmp; return get_address(tmp); };\n\tbool get_address(int &addr) const;\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(static_cast<const std::vector<RTLIL::IdString>&&>(*this));\n\t\treturn h;\n\t}\n};\n\nstruct WitnessHierarchyItem {\n\tRTLIL::Module *module;\n\tRTLIL::Wire *wire = nullptr;\n\tRTLIL::Cell *cell = nullptr;\n\tMem *mem = nullptr;\n\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Wire *wire) : module(module), wire(wire) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, Mem *mem) : module(module), mem(mem) {}\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback);\n\ntemplate<class T> static std::vector<std::string> witness_path(T *obj) {\n\tstd::vector<std::string> path;\n\tif (obj->name.isPublic()) {\n\t\tauto hdlname = obj->get_string_attribute(ID::hdlname);\n\t\tfor (auto token : split_tokens(hdlname))\n\t\t\tpath.push_back(\"\\\\\" + token);\n\t}\n\tif (path.empty())\n\t\tpath.push_back(obj->name.str());\n\treturn path;\n}\n\nstruct ReadWitness\n{\n\tstruct Clock {\n\t\tIdPath path;\n\t\tint offset;\n\t\tbool is_posedge = false;\n\t\tbool is_negedge = false;\n\t};\n\n\tstruct Signal {\n\t\tIdPath path;\n\t\tint offset;\n\t\tint width;\n\t\tbool init_only;\n\n\t\tint bits_offset;\n\t};\n\n\tstruct Step {\n\t\tstd::string bits;\n\t};\n\n\tstd::string filename;\n\tstd::vector<Clock> clocks;\n\tstd::vector<Signal> signals;\n\tstd::vector<Step> steps;\n\n\tReadWitness(const std::string &filename);\n\n\tRTLIL::Const get_bits(int t, int bits_offset, int width) const;\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *module, D data, T &callback)\n{\n\tauto const &const_path = path;\n\tsize_t path_size = path.size();\n\tfor (auto wire : module->wires())\n\t{\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : wire->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == wire->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty())\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(wire->name);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto cell : module->cells())\n\t{\n\t\tModule *child = module->design->module(cell->type);\n\t\tif (child == nullptr)\n\t\t\tcontinue;\n\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, 1, child, child_data, callback);\n\t\t}\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(cell->name);\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, hdlname.empty() ? hdlname_mode : -1, child, child_data, callback);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto mem : Mem::get_all_memories(module)) {\n\t\tstd::vector<std::string> hdlname;\n\n\t\tif (hdlname_mode >= 0 && mem.cell != nullptr)\n\t\t\thdlname = mem.cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == mem.cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t}\n\t\tpath.resize(path_size);\n\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(mem.memid);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\tpath.pop_back();\n\n\t\t\tif (mem.cell != nullptr && mem.cell->name != mem.memid) {\n\t\t\t\tpath.push_back(mem.cell->name);\n\t\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\t\tpath.pop_back();\n\t\t\t}\n\t\t}\n\t}\n}\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback)\n{\n\tIdPath path;\n\twitness_hierarchy_recursion<D, T>(path, 0, module, data, callback);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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"lutrams_xcv.txt": "# LUT RAMs for Virtex, Virtex 2, Spartan 3, Virtex 4.\n# The corresponding mapping file is lutrams_xcv_map.v\n\nram distributed $__XILINX_LUTRAM_SP_ {\n\twidth 1;\n\toption \"ABITS\" 4 {\n\t\tabits 4;\n\t\tcost 3;\n\t}\n\toption \"ABITS\" 5 {\n\t\tabits 5;\n\t\tcost 5;\n\t}\n\tifndef IS_VIRTEX {\n\t\toption \"ABITS\" 6 {\n\t\t\tabits 6;\n\t\t\tcost 9;\n\t\t}\n\t}\n\tifdef IS_VIRTEX2 {\n\t\t# RAM128X1S\n\t\toption \"ABITS\" 7 {\n\t\t\tabits 7;\n\t\t\tcost 17;\n\t\t}\n\t}\n\tinit no_undef;\n\tprune_rom;\n\tport arsw \"RW\" {\n\t\tclock posedge;\n\t}\n}\n\nram distributed $__XILINX_LUTRAM_DP_ {\n\twidth 1;\n\toption \"ABITS\" 4 {\n\t\tabits 4;\n\t\tcost 5;\n\t}\n\tifdef IS_VIRTEX2 {\n\t\t# RAM32X1D\n\t\toption \"ABITS\" 5 {\n\t\t\tabits 5;\n\t\t\tcost 9;\n\t\t}\n\t\t# RAM64X1D\n\t\toption \"ABITS\" 6 {\n\t\t\tabits 6;\n\t\t\tcost 17;\n\t\t}\n\t}\n\tinit no_undef;\n\tprune_rom;\n\tport arsw \"RW\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
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"lutrams_xcv_map.v": "// LUT RAMs for Virtex, Virtex 2, Spartan 3, Virtex 4.\n// The corresponding definition file is lutrams_xcv.txt\n\nmodule $__XILINX_LUTRAM_SP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_ABITS = 4;\n\noutput PORT_RW_RD_DATA;\ninput PORT_RW_WR_DATA;\ninput [OPTION_ABITS-1:0] PORT_RW_ADDR;\ninput PORT_RW_WR_EN;\ninput PORT_RW_CLK;\n\ngenerate\ncase(OPTION_ABITS)\n4: RAM16X1S\n\t#(\n\t\t.INIT(INIT),\n\t)\n\t_TECHMAP_REPLACE_\n\t(\n\t\t.A0(PORT_RW_ADDR[0]),\n\t\t.A1(PORT_RW_ADDR[1]),\n\t\t.A2(PORT_RW_ADDR[2]),\n\t\t.A3(PORT_RW_ADDR[3]),\n\t\t.D(PORT_RW_WR_DATA),\n\t\t.O(PORT_RW_RD_DATA),\n\t\t.WE(PORT_RW_WR_EN),\n\t\t.WCLK(PORT_RW_CLK),\n\t);\n5: RAM32X1S\n\t#(\n\t\t.INIT(INIT),\n\t)\n\t_TECHMAP_REPLACE_\n\t(\n\t\t.A0(PORT_RW_ADDR[0]),\n\t\t.A1(PORT_RW_ADDR[1]),\n\t\t.A2(PORT_RW_ADDR[2]),\n\t\t.A3(PORT_RW_ADDR[3]),\n\t\t.A4(PORT_RW_ADDR[4]),\n\t\t.D(PORT_RW_WR_DATA),\n\t\t.O(PORT_RW_RD_DATA),\n\t\t.WE(PORT_RW_WR_EN),\n\t\t.WCLK(PORT_RW_CLK),\n\t);\n6: RAM64X1S\n\t#(\n\t\t.INIT(INIT),\n\t)\n\t_TECHMAP_REPLACE_\n\t(\n\t\t.A0(PORT_RW_ADDR[0]),\n\t\t.A1(PORT_RW_ADDR[1]),\n\t\t.A2(PORT_RW_ADDR[2]),\n\t\t.A3(PORT_RW_ADDR[3]),\n\t\t.A4(PORT_RW_ADDR[4]),\n\t\t.A5(PORT_RW_ADDR[5]),\n\t\t.D(PORT_RW_WR_DATA),\n\t\t.O(PORT_RW_RD_DATA),\n\t\t.WE(PORT_RW_WR_EN),\n\t\t.WCLK(PORT_RW_CLK),\n\t);\n7: RAM128X1S\n\t#(\n\t\t.INIT(INIT),\n\t)\n\t_TECHMAP_REPLACE_\n\t(\n\t\t.A0(PORT_RW_ADDR[0]),\n\t\t.A1(PORT_RW_ADDR[1]),\n\t\t.A2(PORT_RW_ADDR[2]),\n\t\t.A3(PORT_RW_ADDR[3]),\n\t\t.A4(PORT_RW_ADDR[4]),\n\t\t.A5(PORT_RW_ADDR[5]),\n\t\t.A6(PORT_RW_ADDR[6]),\n\t\t.D(PORT_RW_WR_DATA),\n\t\t.O(PORT_RW_RD_DATA),\n\t\t.WE(PORT_RW_WR_EN),\n\t\t.WCLK(PORT_RW_CLK),\n\t);\ndefault:\n\t$error(\"invalid OPTION_ABITS\");\nendcase\nendgenerate\n\nendmodule\n\nmodule $__XILINX_LUTRAM_DP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_ABITS = 4;\n\noutput PORT_RW_RD_DATA;\ninput PORT_RW_WR_DATA;\ninput [OPTION_ABITS-1:0] PORT_RW_ADDR;\ninput PORT_RW_WR_EN;\ninput PORT_RW_CLK;\n\noutput PORT_R_RD_DATA;\ninput [OPTION_ABITS-1:0] PORT_R_ADDR;\n\ngenerate\ncase (OPTION_ABITS)\n4: RAM16X1D\n\t#(\n\t\t.INIT(INIT),\n\t)\n\t_TECHMAP_REPLACE_\n\t(\n\t\t.A0(PORT_RW_ADDR[0]),\n\t\t.A1(PORT_RW_ADDR[1]),\n\t\t.A2(PORT_RW_ADDR[2]),\n\t\t.A3(PORT_RW_ADDR[3]),\n\t\t.D(PORT_RW_WR_DATA),\n\t\t.SPO(PORT_RW_RD_DATA),\n\t\t.WE(PORT_RW_WR_EN),\n\t\t.WCLK(PORT_RW_CLK),\n\t\t.DPRA0(PORT_R_ADDR[0]),\n\t\t.DPRA1(PORT_R_ADDR[1]),\n\t\t.DPRA2(PORT_R_ADDR[2]),\n\t\t.DPRA3(PORT_R_ADDR[3]),\n\t\t.DPO(PORT_R_RD_DATA),\n\t);\n5: RAM32X1D\n\t#(\n\t\t.INIT(INIT),\n\t)\n\t_TECHMAP_REPLACE_\n\t(\n\t\t.A0(PORT_RW_ADDR[0]),\n\t\t.A1(PORT_RW_ADDR[1]),\n\t\t.A2(PORT_RW_ADDR[2]),\n\t\t.A3(PORT_RW_ADDR[3]),\n\t\t.A4(PORT_RW_ADDR[4]),\n\t\t.D(PORT_RW_WR_DATA),\n\t\t.SPO(PORT_RW_RD_DATA),\n\t\t.WE(PORT_RW_WR_EN),\n\t\t.WCLK(PORT_RW_CLK),\n\t\t.DPRA0(PORT_R_ADDR[0]),\n\t\t.DPRA1(PORT_R_ADDR[1]),\n\t\t.DPRA2(PORT_R_ADDR[2]),\n\t\t.DPRA3(PORT_R_ADDR[3]),\n\t\t.DPRA4(PORT_R_ADDR[4]),\n\t\t.DPO(PORT_R_RD_DATA),\n\t);\n6: RAM64X1D\n\t#(\n\t\t.INIT(INIT),\n\t)\n\t_TECHMAP_REPLACE_\n\t(\n\t\t.A0(PORT_RW_ADDR[0]),\n\t\t.A1(PORT_RW_ADDR[1]),\n\t\t.A2(PORT_RW_ADDR[2]),\n\t\t.A3(PORT_RW_ADDR[3]),\n\t\t.A4(PORT_RW_ADDR[4]),\n\t\t.A5(PORT_RW_ADDR[5]),\n\t\t.D(PORT_RW_WR_DATA),\n\t\t.SPO(PORT_RW_RD_DATA),\n\t\t.WE(PORT_RW_WR_EN),\n\t\t.WCLK(PORT_RW_CLK),\n\t\t.DPRA0(PORT_R_ADDR[0]),\n\t\t.DPRA1(PORT_R_ADDR[1]),\n\t\t.DPRA2(PORT_R_ADDR[2]),\n\t\t.DPRA3(PORT_R_ADDR[3]),\n\t\t.DPRA4(PORT_R_ADDR[4]),\n\t\t.DPRA5(PORT_R_ADDR[5]),\n\t\t.DPO(PORT_R_RD_DATA),\n\t);\ndefault:\n\t$error(\"invalid OPTION_ABITS\");\nendcase\nendgenerate\n\nendmodule\n",
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"mux_map.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * 2019 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// The purpose of these mapping rules is to allow preserve all (sufficiently\n// wide) $shiftx cells during 'techmap' so that they can be mapped to hard\n// resources, rather than being bit-blasted to gates during 'techmap'\n// execution\n\nmodule \\$shiftx (A, B, Y);\n parameter A_SIGNED = 0;\n parameter B_SIGNED = 0;\n parameter A_WIDTH = 1;\n parameter B_WIDTH = 1;\n parameter Y_WIDTH = 1;\n\n (* force_downto *)\n input [A_WIDTH-1:0] A;\n (* force_downto *)\n input [B_WIDTH-1:0] B;\n (* force_downto *)\n output [Y_WIDTH-1:0] Y;\n\n parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n generate\n if (B_SIGNED) begin\n if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))\n // Optimisation to remove B_SIGNED if sign bit of B is constant-0\n \\$shiftx #(\n .A_SIGNED(A_SIGNED),\n .B_SIGNED(0),\n .A_WIDTH(A_WIDTH),\n .B_WIDTH(B_WIDTH-1'd1),\n .Y_WIDTH(Y_WIDTH)\n ) _TECHMAP_REPLACE_ (\n .A(A), .B(B[B_WIDTH-2:0]), .Y(Y)\n );\n else\n wire _TECHMAP_FAIL_ = 1;\n end\n else begin\n if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)\n wire _TECHMAP_FAIL_ = 1;\n else\n \\$__XILINX_SHIFTX #(\n .A_SIGNED(A_SIGNED),\n .B_SIGNED(B_SIGNED),\n .A_WIDTH(A_WIDTH),\n .B_WIDTH(B_WIDTH),\n .Y_WIDTH(Y_WIDTH)\n ) _TECHMAP_REPLACE_ (\n .A(A), .B(B), .Y(Y)\n );\n end\n endgenerate\nendmodule\n",
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414
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"urams.txt": "ram huge $__XILINX_URAM_ {\n\tabits 12;\n\twidth 72;\n\tcost 1024;\n\toption \"BYTEWIDTH\" 8 byte 8;\n\toption \"BYTEWIDTH\" 9 byte 9;\n\tinit zero;\n\tport srsw \"A\" {\n\t\tclock anyedge \"C\";\n\t\tclken;\n\t\trdwr no_change;\n\t\trdinit zero;\n\t\tportoption \"RST_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\tportoption \"RST_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\twrtrans all new;\n\t\twrbe_separate;\n\t}\n\tport srsw \"B\" {\n\t\tclock anyedge \"C\";\n\t\tclken;\n\t\trdwr no_change;\n\t\trdinit zero;\n\t\tportoption \"RST_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\tportoption \"RST_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\twrtrans all old;\n\t\twrprio \"A\";\n\t\twrbe_separate;\n\t}\n}\n",
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415
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"urams_map.v": "module $__XILINX_URAM_ (...);\n\tparameter OPTION_BYTEWIDTH = 8;\n\tlocalparam WR_BE_WIDTH = 72 / OPTION_BYTEWIDTH;\n\n\tparameter CLK_C_POL = 1;\n\tparameter PORT_A_CLK_POL = 1;\n\tparameter PORT_A_OPTION_RST_MODE = \"SYNC\";\n\tparameter PORT_B_CLK_POL = 1;\n\tparameter PORT_B_OPTION_RST_MODE = \"SYNC\";\n\n\tinput CLK_C;\n\n\tinput PORT_A_CLK;\n\tinput PORT_A_CLK_EN;\n\tinput PORT_A_RD_SRST;\n\tinput PORT_A_RD_ARST;\n\tinput PORT_A_WR_EN;\n\tinput [WR_BE_WIDTH-1:0] PORT_A_WR_BE;\n\tinput [11:0] PORT_A_ADDR;\n\tinput [71:0] PORT_A_WR_DATA;\n\toutput [71:0] PORT_A_RD_DATA;\n\n\tinput PORT_B_CLK;\n\tinput PORT_B_CLK_EN;\n\tinput PORT_B_RD_SRST;\n\tinput PORT_B_RD_ARST;\n\tinput PORT_B_WR_EN;\n\tinput [WR_BE_WIDTH-1:0] PORT_B_WR_BE;\n\tinput [11:0] PORT_B_ADDR;\n\tinput [71:0] PORT_B_WR_DATA;\n\toutput [71:0] PORT_B_RD_DATA;\n\n\twire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;\n\n\tgenerate\n\t\tif (OPTION_BYTEWIDTH == 8) begin\n\t\t\tassign DIN_A = PORT_A_WR_DATA;\n\t\t\tassign DIN_B = PORT_B_WR_DATA;\n\t\t\tassign PORT_A_RD_DATA = DOUT_A;\n\t\t\tassign PORT_B_RD_DATA = DOUT_B;\n\t\tend else begin\n\t\t\tassign DIN_A = {\n\t\t\t\tPORT_A_WR_DATA[71],\n\t\t\t\tPORT_A_WR_DATA[62],\n\t\t\t\tPORT_A_WR_DATA[53],\n\t\t\t\tPORT_A_WR_DATA[44],\n\t\t\t\tPORT_A_WR_DATA[35],\n\t\t\t\tPORT_A_WR_DATA[26],\n\t\t\t\tPORT_A_WR_DATA[17],\n\t\t\t\tPORT_A_WR_DATA[8],\n\t\t\t\tPORT_A_WR_DATA[70:63],\n\t\t\t\tPORT_A_WR_DATA[61:54],\n\t\t\t\tPORT_A_WR_DATA[52:45],\n\t\t\t\tPORT_A_WR_DATA[43:36],\n\t\t\t\tPORT_A_WR_DATA[34:27],\n\t\t\t\tPORT_A_WR_DATA[25:18],\n\t\t\t\tPORT_A_WR_DATA[16:9],\n\t\t\t\tPORT_A_WR_DATA[7:0]\n\t\t\t};\n\t\t\tassign DIN_B = {\n\t\t\t\tPORT_B_WR_DATA[71],\n\t\t\t\tPORT_B_WR_DATA[62],\n\t\t\t\tPORT_B_WR_DATA[53],\n\t\t\t\tPORT_B_WR_DATA[44],\n\t\t\t\tPORT_B_WR_DATA[35],\n\t\t\t\tPORT_B_WR_DATA[26],\n\t\t\t\tPORT_B_WR_DATA[17],\n\t\t\t\tPORT_B_WR_DATA[8],\n\t\t\t\tPORT_B_WR_DATA[70:63],\n\t\t\t\tPORT_B_WR_DATA[61:54],\n\t\t\t\tPORT_B_WR_DATA[52:45],\n\t\t\t\tPORT_B_WR_DATA[43:36],\n\t\t\t\tPORT_B_WR_DATA[34:27],\n\t\t\t\tPORT_B_WR_DATA[25:18],\n\t\t\t\tPORT_B_WR_DATA[16:9],\n\t\t\t\tPORT_B_WR_DATA[7:0]\n\t\t\t};\n\t\t\tassign PORT_A_RD_DATA = {\n\t\t\t\tDOUT_A[71],\n\t\t\t\tDOUT_A[63:56],\n\t\t\t\tDOUT_A[70],\n\t\t\t\tDOUT_A[55:48],\n\t\t\t\tDOUT_A[69],\n\t\t\t\tDOUT_A[47:40],\n\t\t\t\tDOUT_A[68],\n\t\t\t\tDOUT_A[39:32],\n\t\t\t\tDOUT_A[67],\n\t\t\t\tDOUT_A[31:24],\n\t\t\t\tDOUT_A[66],\n\t\t\t\tDOUT_A[23:16],\n\t\t\t\tDOUT_A[65],\n\t\t\t\tDOUT_A[15:8],\n\t\t\t\tDOUT_A[64],\n\t\t\t\tDOUT_A[7:0]\n\t\t\t};\n\t\t\tassign PORT_B_RD_DATA = {\n\t\t\t\tDOUT_B[71],\n\t\t\t\tDOUT_B[63:56],\n\t\t\t\tDOUT_B[70],\n\t\t\t\tDOUT_B[55:48],\n\t\t\t\tDOUT_B[69],\n\t\t\t\tDOUT_B[47:40],\n\t\t\t\tDOUT_B[68],\n\t\t\t\tDOUT_B[39:32],\n\t\t\t\tDOUT_B[67],\n\t\t\t\tDOUT_B[31:24],\n\t\t\t\tDOUT_B[66],\n\t\t\t\tDOUT_B[23:16],\n\t\t\t\tDOUT_B[65],\n\t\t\t\tDOUT_B[15:8],\n\t\t\t\tDOUT_B[64],\n\t\t\t\tDOUT_B[7:0]\n\t\t\t};\n\t\tend\n\tendgenerate\n\n\tURAM288 #(\n\t\t.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? \"PARITY_INDEPENDENT\" : \"PARITY_INTERLEAVED\"),\n\t\t.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? \"PARITY_INDEPENDENT\" : \"PARITY_INTERLEAVED\"),\n\t\t.EN_AUTO_SLEEP_MODE(\"FALSE\"),\n\t\t.IREG_PRE_A(\"FALSE\"),\n\t\t.IREG_PRE_B(\"FALSE\"),\n\t\t.IS_CLK_INVERTED(!CLK_C_POL),\n\t\t.OREG_A(\"FALSE\"),\n\t\t.OREG_B(\"FALSE\"),\n\t\t.RST_MODE_A(PORT_A_OPTION_RST_MODE),\n\t\t.RST_MODE_B(PORT_B_OPTION_RST_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.ADDR_A({11'b0, PORT_A_ADDR}),\n\t\t.BWE_A(PORT_A_WR_BE),\n\t\t.EN_A(PORT_A_CLK_EN),\n\t\t.RDB_WR_A(PORT_A_WR_EN),\n\t\t.INJECT_DBITERR_A(1'b0),\n\t\t.INJECT_SBITERR_A(1'b0),\n\t\t.RST_A(PORT_A_OPTION_RST_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t\t.DIN_A(DIN_A),\n\t\t.DOUT_A(DOUT_A),\n\n\t\t.ADDR_B({11'b0, PORT_B_ADDR}),\n\t\t.BWE_B(PORT_B_WR_BE),\n\t\t.EN_B(PORT_B_CLK_EN),\n\t\t.RDB_WR_B(PORT_B_WR_EN),\n\t\t.INJECT_DBITERR_B(1'b0),\n\t\t.INJECT_SBITERR_B(1'b0),\n\t\t.RST_B(PORT_B_OPTION_RST_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t\t.DIN_B(DIN_B),\n\t\t.DOUT_B(DOUT_B),\n\n\t\t.CLK(CLK_C),\n\t\t.SLEEP(1'b0)\n\t);\nendmodule\n",
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414
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+
"urams.txt": "ram huge $__XILINX_URAM_ {\n\tabits 12;\n\twidth 72;\n\tcost 1024;\n\toption \"BYTEWIDTH\" 8 byte 8;\n\toption \"BYTEWIDTH\" 9 byte 9;\n\tinit zero;\n\tport srsw \"A\" {\n\t\tclock anyedge \"C\";\n\t\tclken;\n\t\trdwr no_change;\n\t\trdinit zero;\n\t\tportoption \"RST_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\tportoption \"RST_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\twrtrans all new;\n\t\twrbe_separate;\n\t}\n\tport srsw \"B\" {\n\t\tclock anyedge \"C\";\n\t\tclken;\n\t\trdwr no_change;\n\t\trdinit zero;\n\t\tportoption \"RST_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\tportoption \"RST_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\twrtrans all old;\n\t\twrprio \"A\";\n\t\twrbe_separate;\n\t}\n}\n\nram huge $__XILINX_URAM_SP_ {\n\tabits 11;\n\twidth 144;\n\tcost 1024;\n\toption \"BYTEWIDTH\" 8 byte 8;\n\toption \"BYTEWIDTH\" 9 byte 9;\n\tinit zero;\n\tport srsw \"A\" {\n\t\tclock anyedge \"C\";\n\t\tclken;\n\t\trdwr no_change;\n\t\trdinit zero;\n\t\tportoption \"RST_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\tportoption \"RST_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\twrbe_separate;\n\t}\n}\n",
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415
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"urams_map.v": "module $__XILINX_URAM_ (...);\n\tparameter OPTION_BYTEWIDTH = 8;\n\tlocalparam WR_BE_WIDTH = 72 / OPTION_BYTEWIDTH;\n\n\tparameter CLK_C_POL = 1;\n\tparameter PORT_A_CLK_POL = 1;\n\tparameter PORT_A_OPTION_RST_MODE = \"SYNC\";\n\tparameter PORT_B_CLK_POL = 1;\n\tparameter PORT_B_OPTION_RST_MODE = \"SYNC\";\n\n\tinput CLK_C;\n\n\tinput PORT_A_CLK;\n\tinput PORT_A_CLK_EN;\n\tinput PORT_A_RD_SRST;\n\tinput PORT_A_RD_ARST;\n\tinput PORT_A_WR_EN;\n\tinput [WR_BE_WIDTH-1:0] PORT_A_WR_BE;\n\tinput [11:0] PORT_A_ADDR;\n\tinput [71:0] PORT_A_WR_DATA;\n\toutput [71:0] PORT_A_RD_DATA;\n\n\tinput PORT_B_CLK;\n\tinput PORT_B_CLK_EN;\n\tinput PORT_B_RD_SRST;\n\tinput PORT_B_RD_ARST;\n\tinput PORT_B_WR_EN;\n\tinput [WR_BE_WIDTH-1:0] PORT_B_WR_BE;\n\tinput [11:0] PORT_B_ADDR;\n\tinput [71:0] PORT_B_WR_DATA;\n\toutput [71:0] PORT_B_RD_DATA;\n\n\twire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;\n\n\tgenerate\n\t\tif (OPTION_BYTEWIDTH == 8) begin\n\t\t\tassign DIN_A = PORT_A_WR_DATA;\n\t\t\tassign DIN_B = PORT_B_WR_DATA;\n\t\t\tassign PORT_A_RD_DATA = DOUT_A;\n\t\t\tassign PORT_B_RD_DATA = DOUT_B;\n\t\tend else begin\n\t\t\tassign DIN_A = {\n\t\t\t\tPORT_A_WR_DATA[71],\n\t\t\t\tPORT_A_WR_DATA[62],\n\t\t\t\tPORT_A_WR_DATA[53],\n\t\t\t\tPORT_A_WR_DATA[44],\n\t\t\t\tPORT_A_WR_DATA[35],\n\t\t\t\tPORT_A_WR_DATA[26],\n\t\t\t\tPORT_A_WR_DATA[17],\n\t\t\t\tPORT_A_WR_DATA[8],\n\t\t\t\tPORT_A_WR_DATA[70:63],\n\t\t\t\tPORT_A_WR_DATA[61:54],\n\t\t\t\tPORT_A_WR_DATA[52:45],\n\t\t\t\tPORT_A_WR_DATA[43:36],\n\t\t\t\tPORT_A_WR_DATA[34:27],\n\t\t\t\tPORT_A_WR_DATA[25:18],\n\t\t\t\tPORT_A_WR_DATA[16:9],\n\t\t\t\tPORT_A_WR_DATA[7:0]\n\t\t\t};\n\t\t\tassign DIN_B = {\n\t\t\t\tPORT_B_WR_DATA[71],\n\t\t\t\tPORT_B_WR_DATA[62],\n\t\t\t\tPORT_B_WR_DATA[53],\n\t\t\t\tPORT_B_WR_DATA[44],\n\t\t\t\tPORT_B_WR_DATA[35],\n\t\t\t\tPORT_B_WR_DATA[26],\n\t\t\t\tPORT_B_WR_DATA[17],\n\t\t\t\tPORT_B_WR_DATA[8],\n\t\t\t\tPORT_B_WR_DATA[70:63],\n\t\t\t\tPORT_B_WR_DATA[61:54],\n\t\t\t\tPORT_B_WR_DATA[52:45],\n\t\t\t\tPORT_B_WR_DATA[43:36],\n\t\t\t\tPORT_B_WR_DATA[34:27],\n\t\t\t\tPORT_B_WR_DATA[25:18],\n\t\t\t\tPORT_B_WR_DATA[16:9],\n\t\t\t\tPORT_B_WR_DATA[7:0]\n\t\t\t};\n\t\t\tassign PORT_A_RD_DATA = {\n\t\t\t\tDOUT_A[71],\n\t\t\t\tDOUT_A[63:56],\n\t\t\t\tDOUT_A[70],\n\t\t\t\tDOUT_A[55:48],\n\t\t\t\tDOUT_A[69],\n\t\t\t\tDOUT_A[47:40],\n\t\t\t\tDOUT_A[68],\n\t\t\t\tDOUT_A[39:32],\n\t\t\t\tDOUT_A[67],\n\t\t\t\tDOUT_A[31:24],\n\t\t\t\tDOUT_A[66],\n\t\t\t\tDOUT_A[23:16],\n\t\t\t\tDOUT_A[65],\n\t\t\t\tDOUT_A[15:8],\n\t\t\t\tDOUT_A[64],\n\t\t\t\tDOUT_A[7:0]\n\t\t\t};\n\t\t\tassign PORT_B_RD_DATA = {\n\t\t\t\tDOUT_B[71],\n\t\t\t\tDOUT_B[63:56],\n\t\t\t\tDOUT_B[70],\n\t\t\t\tDOUT_B[55:48],\n\t\t\t\tDOUT_B[69],\n\t\t\t\tDOUT_B[47:40],\n\t\t\t\tDOUT_B[68],\n\t\t\t\tDOUT_B[39:32],\n\t\t\t\tDOUT_B[67],\n\t\t\t\tDOUT_B[31:24],\n\t\t\t\tDOUT_B[66],\n\t\t\t\tDOUT_B[23:16],\n\t\t\t\tDOUT_B[65],\n\t\t\t\tDOUT_B[15:8],\n\t\t\t\tDOUT_B[64],\n\t\t\t\tDOUT_B[7:0]\n\t\t\t};\n\t\tend\n\tendgenerate\n\n\tURAM288 #(\n\t\t.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? \"PARITY_INDEPENDENT\" : \"PARITY_INTERLEAVED\"),\n\t\t.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? \"PARITY_INDEPENDENT\" : \"PARITY_INTERLEAVED\"),\n\t\t.EN_AUTO_SLEEP_MODE(\"FALSE\"),\n\t\t.IREG_PRE_A(\"FALSE\"),\n\t\t.IREG_PRE_B(\"FALSE\"),\n\t\t.IS_CLK_INVERTED(!CLK_C_POL),\n\t\t.OREG_A(\"FALSE\"),\n\t\t.OREG_B(\"FALSE\"),\n\t\t.RST_MODE_A(PORT_A_OPTION_RST_MODE),\n\t\t.RST_MODE_B(PORT_B_OPTION_RST_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.ADDR_A({11'b0, PORT_A_ADDR}),\n\t\t.BWE_A(PORT_A_WR_BE),\n\t\t.EN_A(PORT_A_CLK_EN),\n\t\t.RDB_WR_A(PORT_A_WR_EN),\n\t\t.INJECT_DBITERR_A(1'b0),\n\t\t.INJECT_SBITERR_A(1'b0),\n\t\t.RST_A(PORT_A_OPTION_RST_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t\t.DIN_A(DIN_A),\n\t\t.DOUT_A(DOUT_A),\n\n\t\t.ADDR_B({11'b0, PORT_B_ADDR}),\n\t\t.BWE_B(PORT_B_WR_BE),\n\t\t.EN_B(PORT_B_CLK_EN),\n\t\t.RDB_WR_B(PORT_B_WR_EN),\n\t\t.INJECT_DBITERR_B(1'b0),\n\t\t.INJECT_SBITERR_B(1'b0),\n\t\t.RST_B(PORT_B_OPTION_RST_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST),\n\t\t.DIN_B(DIN_B),\n\t\t.DOUT_B(DOUT_B),\n\n\t\t.CLK(CLK_C),\n\t\t.SLEEP(1'b0)\n\t);\nendmodule\n\nmodule $__XILINX_URAM_SP_ (...);\n\tparameter OPTION_BYTEWIDTH = 8;\n\tlocalparam WR_BE_WIDTH = 144 / OPTION_BYTEWIDTH;\n\n\tparameter CLK_C_POL = 1;\n\tparameter PORT_A_CLK_POL = 1;\n\tparameter PORT_A_OPTION_RST_MODE = \"SYNC\";\n\n\tinput CLK_C;\n\n\tinput PORT_A_CLK;\n\tinput PORT_A_CLK_EN;\n\tinput PORT_A_RD_SRST;\n\tinput PORT_A_RD_ARST;\n\tinput PORT_A_WR_EN;\n\tinput [WR_BE_WIDTH-1:0] PORT_A_WR_BE;\n\tinput [10:0] PORT_A_ADDR;\n\tinput [143:0] PORT_A_WR_DATA;\n\toutput [143:0] PORT_A_RD_DATA;\n\n\twire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;\n\n\tgenerate\n\t\tif (OPTION_BYTEWIDTH == 8) begin\n\t\t\tassign DIN_A = PORT_A_WR_DATA[71:0];\n\t\t\tassign DIN_B = PORT_A_WR_DATA[143:72];\n\t\t\tassign PORT_A_RD_DATA = {DOUT_B, DOUT_A};\n\t\tend else begin\n\t\t\tassign DIN_A = {\n\t\t\t\tPORT_A_WR_DATA[71],\n\t\t\t\tPORT_A_WR_DATA[62],\n\t\t\t\tPORT_A_WR_DATA[53],\n\t\t\t\tPORT_A_WR_DATA[44],\n\t\t\t\tPORT_A_WR_DATA[35],\n\t\t\t\tPORT_A_WR_DATA[26],\n\t\t\t\tPORT_A_WR_DATA[17],\n\t\t\t\tPORT_A_WR_DATA[8],\n\t\t\t\tPORT_A_WR_DATA[70:63],\n\t\t\t\tPORT_A_WR_DATA[61:54],\n\t\t\t\tPORT_A_WR_DATA[52:45],\n\t\t\t\tPORT_A_WR_DATA[43:36],\n\t\t\t\tPORT_A_WR_DATA[34:27],\n\t\t\t\tPORT_A_WR_DATA[25:18],\n\t\t\t\tPORT_A_WR_DATA[16:9],\n\t\t\t\tPORT_A_WR_DATA[7:0]\n\t\t\t};\n\t\t\tassign DIN_B = {\n\t\t\t\tPORT_A_WR_DATA[72+71],\n\t\t\t\tPORT_A_WR_DATA[72+62],\n\t\t\t\tPORT_A_WR_DATA[72+53],\n\t\t\t\tPORT_A_WR_DATA[72+44],\n\t\t\t\tPORT_A_WR_DATA[72+35],\n\t\t\t\tPORT_A_WR_DATA[72+26],\n\t\t\t\tPORT_A_WR_DATA[72+17],\n\t\t\t\tPORT_A_WR_DATA[72+8],\n\t\t\t\tPORT_A_WR_DATA[72+70:72+63],\n\t\t\t\tPORT_A_WR_DATA[72+61:72+54],\n\t\t\t\tPORT_A_WR_DATA[72+52:72+45],\n\t\t\t\tPORT_A_WR_DATA[72+43:72+36],\n\t\t\t\tPORT_A_WR_DATA[72+34:72+27],\n\t\t\t\tPORT_A_WR_DATA[72+25:72+18],\n\t\t\t\tPORT_A_WR_DATA[72+16:72+ 9],\n\t\t\t\tPORT_A_WR_DATA[72+ 7:72+ 0]\n\t\t\t};\n\t\t\tassign PORT_A_RD_DATA = {\n\t\t\t\tDOUT_B[71],\n\t\t\t\tDOUT_B[63:56],\n\t\t\t\tDOUT_B[70],\n\t\t\t\tDOUT_B[55:48],\n\t\t\t\tDOUT_B[69],\n\t\t\t\tDOUT_B[47:40],\n\t\t\t\tDOUT_B[68],\n\t\t\t\tDOUT_B[39:32],\n\t\t\t\tDOUT_B[67],\n\t\t\t\tDOUT_B[31:24],\n\t\t\t\tDOUT_B[66],\n\t\t\t\tDOUT_B[23:16],\n\t\t\t\tDOUT_B[65],\n\t\t\t\tDOUT_B[15:8],\n\t\t\t\tDOUT_B[64],\n\t\t\t\tDOUT_B[7:0],\n\t\t\t\tDOUT_A[71],\n\t\t\t\tDOUT_A[63:56],\n\t\t\t\tDOUT_A[70],\n\t\t\t\tDOUT_A[55:48],\n\t\t\t\tDOUT_A[69],\n\t\t\t\tDOUT_A[47:40],\n\t\t\t\tDOUT_A[68],\n\t\t\t\tDOUT_A[39:32],\n\t\t\t\tDOUT_A[67],\n\t\t\t\tDOUT_A[31:24],\n\t\t\t\tDOUT_A[66],\n\t\t\t\tDOUT_A[23:16],\n\t\t\t\tDOUT_A[65],\n\t\t\t\tDOUT_A[15:8],\n\t\t\t\tDOUT_A[64],\n\t\t\t\tDOUT_A[7:0]\n\t\t\t};\n\t\tend\n\tendgenerate\n\n\tURAM288 #(\n\t\t.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? \"PARITY_INDEPENDENT\" : \"PARITY_INTERLEAVED\"),\n\t\t.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? \"PARITY_INDEPENDENT\" : \"PARITY_INTERLEAVED\"),\n\t\t.EN_AUTO_SLEEP_MODE(\"FALSE\"),\n\t\t.IREG_PRE_A(\"FALSE\"),\n\t\t.IREG_PRE_B(\"FALSE\"),\n\t\t.IS_CLK_INVERTED(!CLK_C_POL),\n\t\t.OREG_A(\"FALSE\"),\n\t\t.OREG_B(\"FALSE\"),\n\t\t.RST_MODE_A(PORT_A_OPTION_RST_MODE),\n\t\t.RST_MODE_B(PORT_A_OPTION_RST_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.ADDR_A({11'b0, PORT_A_ADDR, 1'b0}),\n\t\t.BWE_A(PORT_A_WR_BE[WR_BE_WIDTH/2-1:0]),\n\t\t.EN_A(PORT_A_CLK_EN),\n\t\t.RDB_WR_A(PORT_A_WR_EN),\n\t\t.INJECT_DBITERR_A(1'b0),\n\t\t.INJECT_SBITERR_A(1'b0),\n\t\t.RST_A(PORT_A_OPTION_RST_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t\t.DIN_A(DIN_A),\n\t\t.DOUT_A(DOUT_A),\n\n\t\t.ADDR_B({11'b0, PORT_A_ADDR, 1'b1}),\n\t\t.BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH/2]),\n\t\t.EN_B(PORT_A_CLK_EN),\n\t\t.RDB_WR_B(PORT_A_WR_EN),\n\t\t.INJECT_DBITERR_B(1'b0),\n\t\t.INJECT_SBITERR_B(1'b0),\n\t\t.RST_B(PORT_A_OPTION_RST_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST),\n\t\t.DIN_B(DIN_B),\n\t\t.DOUT_B(DOUT_B),\n\n\t\t.CLK(CLK_C),\n\t\t.SLEEP(1'b0)\n\t);\nendmodule\n",
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416
416
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"xc3s_mult_map.v": "module \\$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 0;\n\tparameter B_WIDTH = 0;\n\tparameter Y_WIDTH = 0;\n\n\tMULT18X18 _TECHMAP_REPLACE_ (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.P(Y)\n\t);\nendmodule\n\n",
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417
417
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"xc3sda_dsp_map.v": "module \\$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 0;\n\tparameter B_WIDTH = 0;\n\tparameter Y_WIDTH = 0;\n\n\twire [47:0] P_48;\n\tDSP48A #(\n\t\t// Disable all registers\n\t\t.A0REG(0),\n\t\t.A1REG(0),\n\t\t.B0REG(0),\n\t\t.B1REG(0),\n\t\t.CARRYINREG(0),\n\t\t.CARRYINSEL(\"OPMODE5\"),\n\t\t.CREG(0),\n\t\t.DREG(0),\n\t\t.MREG(0),\n\t\t.OPMODEREG(0),\n\t\t.PREG(0)\n\t) _TECHMAP_REPLACE_ (\n\t\t//Data path\n\t\t.A(A),\n\t\t.B(B),\n\t\t.C(48'b0),\n\t\t.D(18'b0),\n\t\t.P(P_48),\n\n\t\t.OPMODE(8'b0000001)\n\t);\n\tassign Y = P_48;\nendmodule\n\n",
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418
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"xc4v_dsp_map.v": "module \\$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 0;\n\tparameter B_WIDTH = 0;\n\tparameter Y_WIDTH = 0;\n\n\twire [47:0] P_48;\n\tDSP48 #(\n\t\t// Disable all registers\n\t\t.AREG(0),\n\t\t.BREG(0),\n\t\t.B_INPUT(\"DIRECT\"),\n\t\t.CARRYINREG(0),\n\t\t.CARRYINSELREG(0),\n\t\t.CREG(0),\n\t\t.MREG(0),\n\t\t.OPMODEREG(0),\n\t\t.PREG(0),\n\t\t.SUBTRACTREG(0),\n\t\t.LEGACY_MODE(\"MULT18X18\")\n\t) _TECHMAP_REPLACE_ (\n\t\t//Data path\n\t\t.A(A),\n\t\t.B(B),\n\t\t.C(48'b0),\n\t\t.P(P_48),\n\n\t\t.SUBTRACT(1'b0),\n\t\t.OPMODE(7'b000101),\n\t\t.CARRYINSEL(2'b00),\n\n\t\t.BCIN(18'b0),\n\t\t.PCIN(48'b0),\n\t\t.CARRYIN(1'b0)\n\t);\n\tassign Y = P_48;\nendmodule\n",
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