npm - @yowasp/yosys - Versions diffs - 0.50.857 → 0.52.893 - Mend

@yowasp/yosys 0.50.857 → 0.52.893

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.

Files changed (7) hide show

package/gen/resources-yosys.js CHANGED Viewed

@@ -82,7 +82,7 @@ export const filesystem = {
             "brams_init_20.vh": ".INIT_00(permute_init(INIT[  0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_01(permute_init(INIT[  1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_02(permute_init(INIT[  2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_03(permute_init(INIT[  3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_04(permute_init(INIT[  4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_05(permute_init(INIT[  5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_06(permute_init(INIT[  6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_07(permute_init(INIT[  7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_08(permute_init(INIT[  8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_09(permute_init(INIT[  9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n",
             "brams_init_40.vh": "`ifdef INIT_LOWER\n.INIT_00(permute_init(INIT[  0*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_01(permute_init(INIT[  1*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_02(permute_init(INIT[  2*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_03(permute_init(INIT[  3*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_04(permute_init(INIT[  4*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_05(permute_init(INIT[  5*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_06(permute_init(INIT[  6*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_07(permute_init(INIT[  7*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_08(permute_init(INIT[  8*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_09(permute_init(INIT[  9*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0A(permute_init(INIT[ 10*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0B(permute_init(INIT[ 11*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0C(permute_init(INIT[ 12*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0D(permute_init(INIT[ 13*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0E(permute_init(INIT[ 14*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0F(permute_init(INIT[ 15*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_10(permute_init(INIT[ 16*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_11(permute_init(INIT[ 17*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_12(permute_init(INIT[ 18*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_13(permute_init(INIT[ 19*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_14(permute_init(INIT[ 20*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_15(permute_init(INIT[ 21*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_16(permute_init(INIT[ 22*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_17(permute_init(INIT[ 23*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_18(permute_init(INIT[ 24*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_19(permute_init(INIT[ 25*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1A(permute_init(INIT[ 26*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1B(permute_init(INIT[ 27*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1C(permute_init(INIT[ 28*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1D(permute_init(INIT[ 29*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1E(permute_init(INIT[ 30*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1F(permute_init(INIT[ 31*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_20(permute_init(INIT[ 32*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_21(permute_init(INIT[ 33*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_22(permute_init(INIT[ 34*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_23(permute_init(INIT[ 35*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_24(permute_init(INIT[ 36*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_25(permute_init(INIT[ 37*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_26(permute_init(INIT[ 38*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_27(permute_init(INIT[ 39*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_28(permute_init(INIT[ 40*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_29(permute_init(INIT[ 41*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2A(permute_init(INIT[ 42*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2B(permute_init(INIT[ 43*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2C(permute_init(INIT[ 44*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2D(permute_init(INIT[ 45*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2E(permute_init(INIT[ 46*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2F(permute_init(INIT[ 47*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_30(permute_init(INIT[ 48*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_31(permute_init(INIT[ 49*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_32(permute_init(INIT[ 50*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_33(permute_init(INIT[ 51*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_34(permute_init(INIT[ 52*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_35(permute_init(INIT[ 53*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_36(permute_init(INIT[ 54*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_37(permute_init(INIT[ 55*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_38(permute_init(INIT[ 56*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_39(permute_init(INIT[ 57*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3A(permute_init(INIT[ 58*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3B(permute_init(INIT[ 59*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3C(permute_init(INIT[ 60*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3D(permute_init(INIT[ 61*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3E(permute_init(INIT[ 62*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3F(permute_init(INIT[ 63*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_40(permute_init(INIT[ 64*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_41(permute_init(INIT[ 65*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_42(permute_init(INIT[ 66*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_43(permute_init(INIT[ 67*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_44(permute_init(INIT[ 68*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_45(permute_init(INIT[ 69*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_46(permute_init(INIT[ 70*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_47(permute_init(INIT[ 71*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_48(permute_init(INIT[ 72*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_49(permute_init(INIT[ 73*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4A(permute_init(INIT[ 74*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4B(permute_init(INIT[ 75*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4C(permute_init(INIT[ 76*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4D(permute_init(INIT[ 77*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4E(permute_init(INIT[ 78*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4F(permute_init(INIT[ 79*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_50(permute_init(INIT[ 80*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_51(permute_init(INIT[ 81*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_52(permute_init(INIT[ 82*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_53(permute_init(INIT[ 83*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_54(permute_init(INIT[ 84*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_55(permute_init(INIT[ 85*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_56(permute_init(INIT[ 86*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_57(permute_init(INIT[ 87*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_58(permute_init(INIT[ 88*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_59(permute_init(INIT[ 89*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5A(permute_init(INIT[ 90*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5B(permute_init(INIT[ 91*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5C(permute_init(INIT[ 92*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5D(permute_init(INIT[ 93*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5E(permute_init(INIT[ 94*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5F(permute_init(INIT[ 95*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_60(permute_init(INIT[ 96*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_61(permute_init(INIT[ 97*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_62(permute_init(INIT[ 98*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_63(permute_init(INIT[ 99*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_64(permute_init(INIT[100*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_65(permute_init(INIT[101*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_66(permute_init(INIT[102*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_67(permute_init(INIT[103*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_68(permute_init(INIT[104*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_69(permute_init(INIT[105*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6A(permute_init(INIT[106*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6B(permute_init(INIT[107*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6C(permute_init(INIT[108*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6D(permute_init(INIT[109*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6E(permute_init(INIT[110*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6F(permute_init(INIT[111*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_70(permute_init(INIT[112*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_71(permute_init(INIT[113*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_72(permute_init(INIT[114*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_73(permute_init(INIT[115*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_74(permute_init(INIT[116*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_75(permute_init(INIT[117*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_76(permute_init(INIT[118*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_77(permute_init(INIT[119*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_78(permute_init(INIT[120*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_79(permute_init(INIT[121*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7A(permute_init(INIT[122*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7B(permute_init(INIT[123*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7C(permute_init(INIT[124*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7D(permute_init(INIT[125*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7E(permute_init(INIT[126*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7F(permute_init(INIT[127*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n`endif\n`ifdef INIT_UPPER\n.INIT_00(permute_init(INIT[128*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_01(permute_init(INIT[129*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_02(permute_init(INIT[130*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_03(permute_init(INIT[131*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_04(permute_init(INIT[132*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_05(permute_init(INIT[133*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_06(permute_init(INIT[134*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_07(permute_init(INIT[135*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_08(permute_init(INIT[136*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_09(permute_init(INIT[137*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0A(permute_init(INIT[138*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0B(permute_init(INIT[139*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0C(permute_init(INIT[140*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0D(permute_init(INIT[141*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0E(permute_init(INIT[142*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_0F(permute_init(INIT[143*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_10(permute_init(INIT[144*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_11(permute_init(INIT[145*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_12(permute_init(INIT[146*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_13(permute_init(INIT[147*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_14(permute_init(INIT[148*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_15(permute_init(INIT[149*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_16(permute_init(INIT[150*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_17(permute_init(INIT[151*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_18(permute_init(INIT[152*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_19(permute_init(INIT[153*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1A(permute_init(INIT[154*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1B(permute_init(INIT[155*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1C(permute_init(INIT[156*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1D(permute_init(INIT[157*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1E(permute_init(INIT[158*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_1F(permute_init(INIT[159*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_20(permute_init(INIT[160*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_21(permute_init(INIT[161*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_22(permute_init(INIT[162*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_23(permute_init(INIT[163*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_24(permute_init(INIT[164*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_25(permute_init(INIT[165*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_26(permute_init(INIT[166*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_27(permute_init(INIT[167*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_28(permute_init(INIT[168*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_29(permute_init(INIT[169*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2A(permute_init(INIT[170*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2B(permute_init(INIT[171*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2C(permute_init(INIT[172*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2D(permute_init(INIT[173*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2E(permute_init(INIT[174*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_2F(permute_init(INIT[175*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_30(permute_init(INIT[176*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_31(permute_init(INIT[177*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_32(permute_init(INIT[178*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_33(permute_init(INIT[179*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_34(permute_init(INIT[180*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_35(permute_init(INIT[181*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_36(permute_init(INIT[182*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_37(permute_init(INIT[183*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_38(permute_init(INIT[184*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_39(permute_init(INIT[185*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3A(permute_init(INIT[186*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3B(permute_init(INIT[187*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3C(permute_init(INIT[188*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3D(permute_init(INIT[189*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3E(permute_init(INIT[190*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_3F(permute_init(INIT[191*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_40(permute_init(INIT[192*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_41(permute_init(INIT[193*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_42(permute_init(INIT[194*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_43(permute_init(INIT[195*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_44(permute_init(INIT[196*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_45(permute_init(INIT[197*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_46(permute_init(INIT[198*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_47(permute_init(INIT[199*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_48(permute_init(INIT[200*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_49(permute_init(INIT[201*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4A(permute_init(INIT[202*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4B(permute_init(INIT[203*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4C(permute_init(INIT[204*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4D(permute_init(INIT[205*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4E(permute_init(INIT[206*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_4F(permute_init(INIT[207*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_50(permute_init(INIT[208*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_51(permute_init(INIT[209*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_52(permute_init(INIT[210*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_53(permute_init(INIT[211*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_54(permute_init(INIT[212*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_55(permute_init(INIT[213*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_56(permute_init(INIT[214*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_57(permute_init(INIT[215*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_58(permute_init(INIT[216*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_59(permute_init(INIT[217*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5A(permute_init(INIT[218*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5B(permute_init(INIT[219*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5C(permute_init(INIT[220*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5D(permute_init(INIT[221*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5E(permute_init(INIT[222*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_5F(permute_init(INIT[223*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_60(permute_init(INIT[224*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_61(permute_init(INIT[225*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_62(permute_init(INIT[226*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_63(permute_init(INIT[227*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_64(permute_init(INIT[228*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_65(permute_init(INIT[229*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_66(permute_init(INIT[230*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_67(permute_init(INIT[231*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_68(permute_init(INIT[232*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_69(permute_init(INIT[233*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6A(permute_init(INIT[234*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6B(permute_init(INIT[235*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6C(permute_init(INIT[236*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6D(permute_init(INIT[237*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6E(permute_init(INIT[238*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_6F(permute_init(INIT[239*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_70(permute_init(INIT[240*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_71(permute_init(INIT[241*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_72(permute_init(INIT[242*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_73(permute_init(INIT[243*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_74(permute_init(INIT[244*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_75(permute_init(INIT[245*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_76(permute_init(INIT[246*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_77(permute_init(INIT[247*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_78(permute_init(INIT[248*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_79(permute_init(INIT[249*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7A(permute_init(INIT[250*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7B(permute_init(INIT[251*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7C(permute_init(INIT[252*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7D(permute_init(INIT[253*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7E(permute_init(INIT[254*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n.INIT_7F(permute_init(INIT[255*INIT_CHUNK_SIZE +: INIT_CHUNK_SIZE])),\n`endif\n",
             "brams_map.v": "module $__CC_BRAM_TDP_(...);\r\n\r\nparameter INIT = 0;\r\nparameter OPTION_MODE = \"20K\";\r\n\r\nparameter PORT_A_CLK_POL = 1;\r\nparameter PORT_A_RD_USED = 1;\r\nparameter PORT_A_WR_USED = 1;\r\nparameter PORT_A_RD_WIDTH = 1;\r\nparameter PORT_A_WR_WIDTH = 1;\r\nparameter PORT_A_WR_BE_WIDTH = 1;\r\nparameter PORT_A_OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\nparameter PORT_B_CLK_POL = 1;\r\nparameter PORT_B_RD_USED = 1;\r\nparameter PORT_B_WR_USED = 1;\r\nparameter PORT_B_RD_WIDTH = 1;\r\nparameter PORT_B_WR_WIDTH = 1;\r\nparameter PORT_B_WR_BE_WIDTH = 1;\r\nparameter PORT_B_OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\ninput PORT_A_CLK;\r\ninput PORT_A_CLK_EN;\r\ninput PORT_A_WR_EN;\r\ninput [15:0] PORT_A_ADDR;\r\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\r\ninput [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;\r\noutput [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;\r\n\r\ninput PORT_B_CLK;\r\ninput PORT_B_CLK_EN;\r\ninput PORT_B_WR_EN;\r\ninput [15:0] PORT_B_ADDR;\r\ninput [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\r\ninput [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;\r\noutput [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;\r\n\r\ngenerate\r\n\tif (OPTION_MODE == \"20K\") begin\r\n\t\tCC_BRAM_20K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t);\r\n\tend else if (OPTION_MODE == \"40K\") begin\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], 1'b0}),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t);\r\n\tend else begin\r\n\t\twire CAS_A, CAS_B;\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t\t.CAS(\"LOWER\"),\r\n\t\t) lower (\r\n\t\t\t.A_CO(CAS_A),\r\n\t\t\t.B_CO(CAS_B),\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),\r\n\t\t);\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h80*320+:320]),\r\n\t\t\t.INIT_01(INIT['h81*320+:320]),\r\n\t\t\t.INIT_02(INIT['h82*320+:320]),\r\n\t\t\t.INIT_03(INIT['h83*320+:320]),\r\n\t\t\t.INIT_04(INIT['h84*320+:320]),\r\n\t\t\t.INIT_05(INIT['h85*320+:320]),\r\n\t\t\t.INIT_06(INIT['h86*320+:320]),\r\n\t\t\t.INIT_07(INIT['h87*320+:320]),\r\n\t\t\t.INIT_08(INIT['h88*320+:320]),\r\n\t\t\t.INIT_09(INIT['h89*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h8a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h8b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h8c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h8d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h8e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h8f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h90*320+:320]),\r\n\t\t\t.INIT_11(INIT['h91*320+:320]),\r\n\t\t\t.INIT_12(INIT['h92*320+:320]),\r\n\t\t\t.INIT_13(INIT['h93*320+:320]),\r\n\t\t\t.INIT_14(INIT['h94*320+:320]),\r\n\t\t\t.INIT_15(INIT['h95*320+:320]),\r\n\t\t\t.INIT_16(INIT['h96*320+:320]),\r\n\t\t\t.INIT_17(INIT['h97*320+:320]),\r\n\t\t\t.INIT_18(INIT['h98*320+:320]),\r\n\t\t\t.INIT_19(INIT['h99*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h9a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h9b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h9c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h9d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h9e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h9f*320+:320]),\r\n\t\t\t.INIT_20(INIT['ha0*320+:320]),\r\n\t\t\t.INIT_21(INIT['ha1*320+:320]),\r\n\t\t\t.INIT_22(INIT['ha2*320+:320]),\r\n\t\t\t.INIT_23(INIT['ha3*320+:320]),\r\n\t\t\t.INIT_24(INIT['ha4*320+:320]),\r\n\t\t\t.INIT_25(INIT['ha5*320+:320]),\r\n\t\t\t.INIT_26(INIT['ha6*320+:320]),\r\n\t\t\t.INIT_27(INIT['ha7*320+:320]),\r\n\t\t\t.INIT_28(INIT['ha8*320+:320]),\r\n\t\t\t.INIT_29(INIT['ha9*320+:320]),\r\n\t\t\t.INIT_2A(INIT['haa*320+:320]),\r\n\t\t\t.INIT_2B(INIT['hab*320+:320]),\r\n\t\t\t.INIT_2C(INIT['hac*320+:320]),\r\n\t\t\t.INIT_2D(INIT['had*320+:320]),\r\n\t\t\t.INIT_2E(INIT['hae*320+:320]),\r\n\t\t\t.INIT_2F(INIT['haf*320+:320]),\r\n\t\t\t.INIT_30(INIT['hb0*320+:320]),\r\n\t\t\t.INIT_31(INIT['hb1*320+:320]),\r\n\t\t\t.INIT_32(INIT['hb2*320+:320]),\r\n\t\t\t.INIT_33(INIT['hb3*320+:320]),\r\n\t\t\t.INIT_34(INIT['hb4*320+:320]),\r\n\t\t\t.INIT_35(INIT['hb5*320+:320]),\r\n\t\t\t.INIT_36(INIT['hb6*320+:320]),\r\n\t\t\t.INIT_37(INIT['hb7*320+:320]),\r\n\t\t\t.INIT_38(INIT['hb8*320+:320]),\r\n\t\t\t.INIT_39(INIT['hb9*320+:320]),\r\n\t\t\t.INIT_3A(INIT['hba*320+:320]),\r\n\t\t\t.INIT_3B(INIT['hbb*320+:320]),\r\n\t\t\t.INIT_3C(INIT['hbc*320+:320]),\r\n\t\t\t.INIT_3D(INIT['hbd*320+:320]),\r\n\t\t\t.INIT_3E(INIT['hbe*320+:320]),\r\n\t\t\t.INIT_3F(INIT['hbf*320+:320]),\r\n\t\t\t.INIT_40(INIT['hc0*320+:320]),\r\n\t\t\t.INIT_41(INIT['hc1*320+:320]),\r\n\t\t\t.INIT_42(INIT['hc2*320+:320]),\r\n\t\t\t.INIT_43(INIT['hc3*320+:320]),\r\n\t\t\t.INIT_44(INIT['hc4*320+:320]),\r\n\t\t\t.INIT_45(INIT['hc5*320+:320]),\r\n\t\t\t.INIT_46(INIT['hc6*320+:320]),\r\n\t\t\t.INIT_47(INIT['hc7*320+:320]),\r\n\t\t\t.INIT_48(INIT['hc8*320+:320]),\r\n\t\t\t.INIT_49(INIT['hc9*320+:320]),\r\n\t\t\t.INIT_4A(INIT['hca*320+:320]),\r\n\t\t\t.INIT_4B(INIT['hcb*320+:320]),\r\n\t\t\t.INIT_4C(INIT['hcc*320+:320]),\r\n\t\t\t.INIT_4D(INIT['hcd*320+:320]),\r\n\t\t\t.INIT_4E(INIT['hce*320+:320]),\r\n\t\t\t.INIT_4F(INIT['hcf*320+:320]),\r\n\t\t\t.INIT_50(INIT['hd0*320+:320]),\r\n\t\t\t.INIT_51(INIT['hd1*320+:320]),\r\n\t\t\t.INIT_52(INIT['hd2*320+:320]),\r\n\t\t\t.INIT_53(INIT['hd3*320+:320]),\r\n\t\t\t.INIT_54(INIT['hd4*320+:320]),\r\n\t\t\t.INIT_55(INIT['hd5*320+:320]),\r\n\t\t\t.INIT_56(INIT['hd6*320+:320]),\r\n\t\t\t.INIT_57(INIT['hd7*320+:320]),\r\n\t\t\t.INIT_58(INIT['hd8*320+:320]),\r\n\t\t\t.INIT_59(INIT['hd9*320+:320]),\r\n\t\t\t.INIT_5A(INIT['hda*320+:320]),\r\n\t\t\t.INIT_5B(INIT['hdb*320+:320]),\r\n\t\t\t.INIT_5C(INIT['hdc*320+:320]),\r\n\t\t\t.INIT_5D(INIT['hdd*320+:320]),\r\n\t\t\t.INIT_5E(INIT['hde*320+:320]),\r\n\t\t\t.INIT_5F(INIT['hdf*320+:320]),\r\n\t\t\t.INIT_60(INIT['he0*320+:320]),\r\n\t\t\t.INIT_61(INIT['he1*320+:320]),\r\n\t\t\t.INIT_62(INIT['he2*320+:320]),\r\n\t\t\t.INIT_63(INIT['he3*320+:320]),\r\n\t\t\t.INIT_64(INIT['he4*320+:320]),\r\n\t\t\t.INIT_65(INIT['he5*320+:320]),\r\n\t\t\t.INIT_66(INIT['he6*320+:320]),\r\n\t\t\t.INIT_67(INIT['he7*320+:320]),\r\n\t\t\t.INIT_68(INIT['he8*320+:320]),\r\n\t\t\t.INIT_69(INIT['he9*320+:320]),\r\n\t\t\t.INIT_6A(INIT['hea*320+:320]),\r\n\t\t\t.INIT_6B(INIT['heb*320+:320]),\r\n\t\t\t.INIT_6C(INIT['hec*320+:320]),\r\n\t\t\t.INIT_6D(INIT['hed*320+:320]),\r\n\t\t\t.INIT_6E(INIT['hee*320+:320]),\r\n\t\t\t.INIT_6F(INIT['hef*320+:320]),\r\n\t\t\t.INIT_70(INIT['hf0*320+:320]),\r\n\t\t\t.INIT_71(INIT['hf1*320+:320]),\r\n\t\t\t.INIT_72(INIT['hf2*320+:320]),\r\n\t\t\t.INIT_73(INIT['hf3*320+:320]),\r\n\t\t\t.INIT_74(INIT['hf4*320+:320]),\r\n\t\t\t.INIT_75(INIT['hf5*320+:320]),\r\n\t\t\t.INIT_76(INIT['hf6*320+:320]),\r\n\t\t\t.INIT_77(INIT['hf7*320+:320]),\r\n\t\t\t.INIT_78(INIT['hf8*320+:320]),\r\n\t\t\t.INIT_79(INIT['hf9*320+:320]),\r\n\t\t\t.INIT_7A(INIT['hfa*320+:320]),\r\n\t\t\t.INIT_7B(INIT['hfb*320+:320]),\r\n\t\t\t.INIT_7C(INIT['hfc*320+:320]),\r\n\t\t\t.INIT_7D(INIT['hfd*320+:320]),\r\n\t\t\t.INIT_7E(INIT['hfe*320+:320]),\r\n\t\t\t.INIT_7F(INIT['hff*320+:320]),\r\n\t\t\t.A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0),\r\n\t\t\t.A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0),\r\n\t\t\t.RAM_MODE(\"TDP\"),\r\n\t\t\t.A_WR_MODE(PORT_A_OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(PORT_B_OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_A_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_B_CLK_POL),\r\n\t\t\t.CAS(\"UPPER\"),\r\n\t\t) upper (\r\n\t\t\t.A_CI(CAS_A),\r\n\t\t\t.B_CI(CAS_B),\r\n\t\t\t.A_CLK(PORT_A_CLK),\r\n\t\t\t.A_EN(PORT_A_CLK_EN),\r\n\t\t\t.A_WE(PORT_A_WR_EN),\r\n\t\t\t.A_BM(PORT_A_WR_BE),\r\n\t\t\t.A_DI(PORT_A_WR_DATA),\r\n\t\t\t.A_DO(PORT_A_RD_DATA),\r\n\t\t\t.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),\r\n\t\t\t.B_CLK(PORT_B_CLK),\r\n\t\t\t.B_EN(PORT_B_CLK_EN),\r\n\t\t\t.B_WE(PORT_B_WR_EN),\r\n\t\t\t.B_BM(PORT_B_WR_BE),\r\n\t\t\t.B_DI(PORT_B_WR_DATA),\r\n\t\t\t.B_DO(PORT_B_RD_DATA),\r\n\t\t\t.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),\r\n\t\t);\r\n\tend\r\nendgenerate\r\n\r\nendmodule\r\n\r\n\r\nmodule $__CC_BRAM_SDP_(...);\r\n\r\nparameter INIT = 0;\r\nparameter OPTION_MODE = \"20K\";\r\nparameter OPTION_WR_MODE = \"NO_CHANGE\";\r\n\r\nparameter PORT_W_CLK_POL = 1;\r\nparameter PORT_W_USED = 1;\r\nparameter PORT_W_WIDTH = 40;\r\nparameter PORT_W_WR_BE_WIDTH = 40;\r\n\r\nparameter PORT_R_CLK_POL = 1;\r\nparameter PORT_R_USED = 1;\r\nparameter PORT_R_WIDTH = 40;\r\n\r\ninput PORT_W_CLK;\r\ninput PORT_W_CLK_EN;\r\ninput PORT_W_WR_EN;\r\ninput [15:0] PORT_W_ADDR;\r\ninput [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;\r\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\r\n\r\ninput PORT_R_CLK;\r\ninput PORT_R_CLK_EN;\r\ninput [15:0] PORT_R_ADDR;\r\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\r\n\r\ngenerate\r\n\tif (OPTION_MODE == \"20K\") begin\r\n\t\tCC_BRAM_20K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(0),\r\n\t\t\t.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(0),\r\n\t\t\t.RAM_MODE(\"SDP\"),\r\n\t\t\t.A_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_W_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_R_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_W_CLK),\r\n\t\t\t.A_EN(PORT_W_CLK_EN),\r\n\t\t\t.A_WE(PORT_W_WR_EN),\r\n\t\t\t.A_BM(PORT_W_WR_BE[19:0]),\r\n\t\t\t.B_BM(PORT_W_WR_BE[39:20]),\r\n\t\t\t.A_DI(PORT_W_WR_DATA[19:0]),\r\n\t\t\t.B_DI(PORT_W_WR_DATA[39:20]),\r\n\t\t\t.A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}),\r\n\t\t\t.B_CLK(PORT_R_CLK),\r\n\t\t\t.B_EN(PORT_R_CLK_EN),\r\n\t\t\t.B_WE(1'b0),\r\n\t\t\t.B_ADDR({PORT_R_ADDR[13:5], 1'b0, PORT_R_ADDR[4:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_R_RD_DATA[19:0]),\r\n\t\t\t.B_DO(PORT_R_RD_DATA[39:20]),\r\n\t\t);\r\n\tend else if (OPTION_MODE == \"40K\") begin\r\n\t\tCC_BRAM_40K #(\r\n\t\t\t.INIT_00(INIT['h00*320+:320]),\r\n\t\t\t.INIT_01(INIT['h01*320+:320]),\r\n\t\t\t.INIT_02(INIT['h02*320+:320]),\r\n\t\t\t.INIT_03(INIT['h03*320+:320]),\r\n\t\t\t.INIT_04(INIT['h04*320+:320]),\r\n\t\t\t.INIT_05(INIT['h05*320+:320]),\r\n\t\t\t.INIT_06(INIT['h06*320+:320]),\r\n\t\t\t.INIT_07(INIT['h07*320+:320]),\r\n\t\t\t.INIT_08(INIT['h08*320+:320]),\r\n\t\t\t.INIT_09(INIT['h09*320+:320]),\r\n\t\t\t.INIT_0A(INIT['h0a*320+:320]),\r\n\t\t\t.INIT_0B(INIT['h0b*320+:320]),\r\n\t\t\t.INIT_0C(INIT['h0c*320+:320]),\r\n\t\t\t.INIT_0D(INIT['h0d*320+:320]),\r\n\t\t\t.INIT_0E(INIT['h0e*320+:320]),\r\n\t\t\t.INIT_0F(INIT['h0f*320+:320]),\r\n\t\t\t.INIT_10(INIT['h10*320+:320]),\r\n\t\t\t.INIT_11(INIT['h11*320+:320]),\r\n\t\t\t.INIT_12(INIT['h12*320+:320]),\r\n\t\t\t.INIT_13(INIT['h13*320+:320]),\r\n\t\t\t.INIT_14(INIT['h14*320+:320]),\r\n\t\t\t.INIT_15(INIT['h15*320+:320]),\r\n\t\t\t.INIT_16(INIT['h16*320+:320]),\r\n\t\t\t.INIT_17(INIT['h17*320+:320]),\r\n\t\t\t.INIT_18(INIT['h18*320+:320]),\r\n\t\t\t.INIT_19(INIT['h19*320+:320]),\r\n\t\t\t.INIT_1A(INIT['h1a*320+:320]),\r\n\t\t\t.INIT_1B(INIT['h1b*320+:320]),\r\n\t\t\t.INIT_1C(INIT['h1c*320+:320]),\r\n\t\t\t.INIT_1D(INIT['h1d*320+:320]),\r\n\t\t\t.INIT_1E(INIT['h1e*320+:320]),\r\n\t\t\t.INIT_1F(INIT['h1f*320+:320]),\r\n\t\t\t.INIT_20(INIT['h20*320+:320]),\r\n\t\t\t.INIT_21(INIT['h21*320+:320]),\r\n\t\t\t.INIT_22(INIT['h22*320+:320]),\r\n\t\t\t.INIT_23(INIT['h23*320+:320]),\r\n\t\t\t.INIT_24(INIT['h24*320+:320]),\r\n\t\t\t.INIT_25(INIT['h25*320+:320]),\r\n\t\t\t.INIT_26(INIT['h26*320+:320]),\r\n\t\t\t.INIT_27(INIT['h27*320+:320]),\r\n\t\t\t.INIT_28(INIT['h28*320+:320]),\r\n\t\t\t.INIT_29(INIT['h29*320+:320]),\r\n\t\t\t.INIT_2A(INIT['h2a*320+:320]),\r\n\t\t\t.INIT_2B(INIT['h2b*320+:320]),\r\n\t\t\t.INIT_2C(INIT['h2c*320+:320]),\r\n\t\t\t.INIT_2D(INIT['h2d*320+:320]),\r\n\t\t\t.INIT_2E(INIT['h2e*320+:320]),\r\n\t\t\t.INIT_2F(INIT['h2f*320+:320]),\r\n\t\t\t.INIT_30(INIT['h30*320+:320]),\r\n\t\t\t.INIT_31(INIT['h31*320+:320]),\r\n\t\t\t.INIT_32(INIT['h32*320+:320]),\r\n\t\t\t.INIT_33(INIT['h33*320+:320]),\r\n\t\t\t.INIT_34(INIT['h34*320+:320]),\r\n\t\t\t.INIT_35(INIT['h35*320+:320]),\r\n\t\t\t.INIT_36(INIT['h36*320+:320]),\r\n\t\t\t.INIT_37(INIT['h37*320+:320]),\r\n\t\t\t.INIT_38(INIT['h38*320+:320]),\r\n\t\t\t.INIT_39(INIT['h39*320+:320]),\r\n\t\t\t.INIT_3A(INIT['h3a*320+:320]),\r\n\t\t\t.INIT_3B(INIT['h3b*320+:320]),\r\n\t\t\t.INIT_3C(INIT['h3c*320+:320]),\r\n\t\t\t.INIT_3D(INIT['h3d*320+:320]),\r\n\t\t\t.INIT_3E(INIT['h3e*320+:320]),\r\n\t\t\t.INIT_3F(INIT['h3f*320+:320]),\r\n\t\t\t.INIT_40(INIT['h40*320+:320]),\r\n\t\t\t.INIT_41(INIT['h41*320+:320]),\r\n\t\t\t.INIT_42(INIT['h42*320+:320]),\r\n\t\t\t.INIT_43(INIT['h43*320+:320]),\r\n\t\t\t.INIT_44(INIT['h44*320+:320]),\r\n\t\t\t.INIT_45(INIT['h45*320+:320]),\r\n\t\t\t.INIT_46(INIT['h46*320+:320]),\r\n\t\t\t.INIT_47(INIT['h47*320+:320]),\r\n\t\t\t.INIT_48(INIT['h48*320+:320]),\r\n\t\t\t.INIT_49(INIT['h49*320+:320]),\r\n\t\t\t.INIT_4A(INIT['h4a*320+:320]),\r\n\t\t\t.INIT_4B(INIT['h4b*320+:320]),\r\n\t\t\t.INIT_4C(INIT['h4c*320+:320]),\r\n\t\t\t.INIT_4D(INIT['h4d*320+:320]),\r\n\t\t\t.INIT_4E(INIT['h4e*320+:320]),\r\n\t\t\t.INIT_4F(INIT['h4f*320+:320]),\r\n\t\t\t.INIT_50(INIT['h50*320+:320]),\r\n\t\t\t.INIT_51(INIT['h51*320+:320]),\r\n\t\t\t.INIT_52(INIT['h52*320+:320]),\r\n\t\t\t.INIT_53(INIT['h53*320+:320]),\r\n\t\t\t.INIT_54(INIT['h54*320+:320]),\r\n\t\t\t.INIT_55(INIT['h55*320+:320]),\r\n\t\t\t.INIT_56(INIT['h56*320+:320]),\r\n\t\t\t.INIT_57(INIT['h57*320+:320]),\r\n\t\t\t.INIT_58(INIT['h58*320+:320]),\r\n\t\t\t.INIT_59(INIT['h59*320+:320]),\r\n\t\t\t.INIT_5A(INIT['h5a*320+:320]),\r\n\t\t\t.INIT_5B(INIT['h5b*320+:320]),\r\n\t\t\t.INIT_5C(INIT['h5c*320+:320]),\r\n\t\t\t.INIT_5D(INIT['h5d*320+:320]),\r\n\t\t\t.INIT_5E(INIT['h5e*320+:320]),\r\n\t\t\t.INIT_5F(INIT['h5f*320+:320]),\r\n\t\t\t.INIT_60(INIT['h60*320+:320]),\r\n\t\t\t.INIT_61(INIT['h61*320+:320]),\r\n\t\t\t.INIT_62(INIT['h62*320+:320]),\r\n\t\t\t.INIT_63(INIT['h63*320+:320]),\r\n\t\t\t.INIT_64(INIT['h64*320+:320]),\r\n\t\t\t.INIT_65(INIT['h65*320+:320]),\r\n\t\t\t.INIT_66(INIT['h66*320+:320]),\r\n\t\t\t.INIT_67(INIT['h67*320+:320]),\r\n\t\t\t.INIT_68(INIT['h68*320+:320]),\r\n\t\t\t.INIT_69(INIT['h69*320+:320]),\r\n\t\t\t.INIT_6A(INIT['h6a*320+:320]),\r\n\t\t\t.INIT_6B(INIT['h6b*320+:320]),\r\n\t\t\t.INIT_6C(INIT['h6c*320+:320]),\r\n\t\t\t.INIT_6D(INIT['h6d*320+:320]),\r\n\t\t\t.INIT_6E(INIT['h6e*320+:320]),\r\n\t\t\t.INIT_6F(INIT['h6f*320+:320]),\r\n\t\t\t.INIT_70(INIT['h70*320+:320]),\r\n\t\t\t.INIT_71(INIT['h71*320+:320]),\r\n\t\t\t.INIT_72(INIT['h72*320+:320]),\r\n\t\t\t.INIT_73(INIT['h73*320+:320]),\r\n\t\t\t.INIT_74(INIT['h74*320+:320]),\r\n\t\t\t.INIT_75(INIT['h75*320+:320]),\r\n\t\t\t.INIT_76(INIT['h76*320+:320]),\r\n\t\t\t.INIT_77(INIT['h77*320+:320]),\r\n\t\t\t.INIT_78(INIT['h78*320+:320]),\r\n\t\t\t.INIT_79(INIT['h79*320+:320]),\r\n\t\t\t.INIT_7A(INIT['h7a*320+:320]),\r\n\t\t\t.INIT_7B(INIT['h7b*320+:320]),\r\n\t\t\t.INIT_7C(INIT['h7c*320+:320]),\r\n\t\t\t.INIT_7D(INIT['h7d*320+:320]),\r\n\t\t\t.INIT_7E(INIT['h7e*320+:320]),\r\n\t\t\t.INIT_7F(INIT['h7f*320+:320]),\r\n\t\t\t.A_RD_WIDTH(0),\r\n\t\t\t.A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0),\r\n\t\t\t.B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0),\r\n\t\t\t.B_WR_WIDTH(0),\r\n\t\t\t.RAM_MODE(\"SDP\"),\r\n\t\t\t.A_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.B_WR_MODE(OPTION_WR_MODE),\r\n\t\t\t.A_CLK_INV(!PORT_W_CLK_POL),\r\n\t\t\t.B_CLK_INV(!PORT_R_CLK_POL),\r\n\t\t) _TECHMAP_REPLACE_ (\r\n\t\t\t.A_CLK(PORT_W_CLK),\r\n\t\t\t.A_EN(PORT_W_CLK_EN),\r\n\t\t\t.A_WE(PORT_W_WR_EN),\r\n\t\t\t.A_BM(PORT_W_WR_BE[39:0]),\r\n\t\t\t.B_BM(PORT_W_WR_BE[79:40]),\r\n\t\t\t.A_DI(PORT_W_WR_DATA[39:0]),\r\n\t\t\t.B_DI(PORT_W_WR_DATA[79:40]),\r\n\t\t\t.A_ADDR({PORT_W_ADDR[14:0], 1'b0}),\r\n\t\t\t.B_CLK(PORT_R_CLK),\r\n\t\t\t.B_EN(PORT_R_CLK_EN),\r\n\t\t\t.B_WE(1'b0),\r\n\t\t\t.B_ADDR({PORT_R_ADDR[14:0], 1'b0}),\r\n\t\t\t.A_DO(PORT_R_RD_DATA[39:0]),\r\n\t\t\t.B_DO(PORT_R_RD_DATA[79:40]),\r\n\t\t);\r\n\tend\r\nendgenerate\r\n\r\nendmodule\r\n",
-            "cells_bb.v": "/*\r\n *  yosys -- Yosys Open SYnthesis Suite\r\n *\r\n *  Copyright (C) 2021  Cologne Chip AG <support@colognechip.com>\r\n *\r\n *  Permission to use, copy, modify, and/or distribute this software for any\r\n *  purpose with or without fee is hereby granted, provided that the above\r\n *  copyright notice and this permission notice appear in all copies.\r\n *\r\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\n(* blackbox *)\r\nmodule CC_PLL #(\r\n\tparameter REF_CLK = \"\", // e.g. \"10.0\"\r\n\tparameter OUT_CLK = \"\", // e.g. \"50.0\"\r\n\tparameter PERF_MD = \"\", // LOWPOWER, ECONOMY, SPEED\r\n\tparameter LOCK_REQ = 1,\r\n\tparameter CLK270_DOUB = 0,\r\n\tparameter CLK180_DOUB = 0,\r\n\tparameter LOW_JITTER = 1,\r\n\tparameter CI_FILTER_CONST = 2,\r\n\tparameter CP_FILTER_CONST = 4\r\n)(\r\n\tinput  CLK_REF, CLK_FEEDBACK, USR_CLK_REF,\r\n\tinput  USR_LOCKED_STDY_RST,\r\n\toutput USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,\r\n\toutput CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT\r\n);\r\nendmodule\r\n\r\n(* blackbox *)\r\nmodule CC_PLL_ADV #(\r\n\tparameter [95:0] PLL_CFG_A = 96'bx,\r\n\tparameter [95:0] PLL_CFG_B = 96'bx\r\n)(\r\n\tinput  CLK_REF, CLK_FEEDBACK, USR_CLK_REF,\r\n\tinput  USR_LOCKED_STDY_RST, USR_SEL_A_B,\r\n\toutput USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,\r\n\toutput CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_SERDES #(\r\n\tparameter SERDES_CFG = \"\"\r\n)(\r\n\tinput [63:0] TX_DATA_I,\r\n\tinput TX_RESET_I,\r\n\tinput TX_PCS_RESET_I,\r\n\tinput TX_PMA_RESET_I,\r\n\tinput PLL_RESET_I,\r\n\tinput TX_POWERDOWN_N_I,\r\n\tinput TX_POLARITY_I,\r\n\tinput [2:0] TX_PRBS_SEL_I,\r\n\tinput TX_PRBS_FORCE_ERR_I,\r\n\tinput TX_8B10B_EN_I,\r\n\tinput [7:0] TX_8B10B_BYPASS_I,\r\n\tinput [7:0] TX_CHAR_IS_K_I,\r\n\tinput [7:0] TX_CHAR_DISPMODE_I,\r\n\tinput [7:0] TX_CHAR_DISPVAL_I,\r\n\tinput TX_ELEC_IDLE_I,\r\n\tinput TX_DETECT_RX_I,\r\n\tinput [2:0] LOOPBACK_I,\r\n\tinput CLK_CORE_TX_I,\r\n\tinput CLK_CORE_RX_I,\r\n\tinput RX_RESET_I,\r\n\tinput RX_PMA_RESET_I,\r\n\tinput RX_EQA_RESET_I,\r\n\tinput RX_CDR_RESET_I,\r\n\tinput RX_PCS_RESET_I,\r\n\tinput RX_BUF_RESET_I,\r\n\tinput RX_POWERDOWN_N_I,\r\n\tinput RX_POLARITY_I,\r\n\tinput [2:0] RX_PRBS_SEL_I,\r\n\tinput RX_PRBS_CNT_RESET_I,\r\n\tinput RX_8B10B_EN_I,\r\n\tinput [7:0] RX_8B10B_BYPASS_I,\r\n\tinput RX_EN_EI_DETECTOR_I,\r\n\tinput RX_COMMA_DETECT_EN_I,\r\n\tinput RX_SLIDE_I,\r\n\tinput RX_MCOMMA_ALIGN_I,\r\n\tinput RX_PCOMMA_ALIGN_I,\r\n\tinput CLK_REG_I,\r\n\tinput REGFILE_WE_I,\r\n\tinput REGFILE_EN_I,\r\n\tinput [7:0] REGFILE_ADDR_I,\r\n\tinput [15:0] REGFILE_DI_I,\r\n\tinput [15:0] REGFILE_MASK_I,\r\n\toutput [63:0] RX_DATA_O,\r\n\toutput [7:0] RX_NOT_IN_TABLE_O,\r\n\toutput [7:0] RX_CHAR_IS_COMMA_O,\r\n\toutput [7:0] RX_CHAR_IS_K_O,\r\n\toutput [7:0] RX_DISP_ERR_O,\r\n\toutput RX_DETECT_DONE_O,\r\n\toutput RX_PRESENT_O,\r\n\toutput TX_BUF_ERR_O,\r\n\toutput TX_RESETDONE_O,\r\n\toutput RX_PRBS_ERR_O,\r\n\toutput RX_BUF_ERR_O,\r\n\toutput RX_BYTE_IS_ALIGNED_O,\r\n\toutput RX_BYTE_REALIGN_O,\r\n\toutput RX_RESETDONE_O,\r\n\toutput RX_EI_EN_O,\r\n\toutput CLK_CORE_RX_O,\r\n\toutput CLK_CORE_PLL_O,\r\n\toutput [15:0] REGFILE_DO_O,\r\n\toutput REGFILE_RDY_O\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_CFG_CTRL(\r\n\tinput [7:0] DATA,\r\n\tinput CLK,\r\n\tinput EN,\r\n\tinput RECFG,\r\n\tinput VALID\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_USR_RSTN (\r\n\toutput USR_RSTN\r\n);\r\nendmodule\r\n",
+            "cells_bb.v": "/*\r\n *  yosys -- Yosys Open SYnthesis Suite\r\n *\r\n *  Copyright (C) 2021  Cologne Chip AG <support@colognechip.com>\r\n *\r\n *  Permission to use, copy, modify, and/or distribute this software for any\r\n *  purpose with or without fee is hereby granted, provided that the above\r\n *  copyright notice and this permission notice appear in all copies.\r\n *\r\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\n(* blackbox *)\r\nmodule CC_PLL #(\r\n\tparameter REF_CLK = \"\", // e.g. \"10.0\"\r\n\tparameter OUT_CLK = \"\", // e.g. \"50.0\"\r\n\tparameter PERF_MD = \"\", // LOWPOWER, ECONOMY, SPEED\r\n\tparameter LOCK_REQ = 1,\r\n\tparameter CLK270_DOUB = 0,\r\n\tparameter CLK180_DOUB = 0,\r\n\tparameter LOW_JITTER = 1,\r\n\tparameter CI_FILTER_CONST = 2,\r\n\tparameter CP_FILTER_CONST = 4\r\n)(\r\n\tinput  CLK_REF, CLK_FEEDBACK, USR_CLK_REF,\r\n\tinput  USR_LOCKED_STDY_RST,\r\n\toutput USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,\r\n\toutput CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT\r\n);\r\nendmodule\r\n\r\n(* blackbox *)\r\nmodule CC_PLL_ADV #(\r\n\tparameter [95:0] PLL_CFG_A = 96'bx,\r\n\tparameter [95:0] PLL_CFG_B = 96'bx\r\n)(\r\n\tinput  CLK_REF, CLK_FEEDBACK, USR_CLK_REF,\r\n\tinput  USR_LOCKED_STDY_RST, USR_SEL_A_B,\r\n\toutput USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,\r\n\toutput CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_SERDES #(\r\n\tparameter  [4:0] RX_BUF_RESET_TIME = 3,\r\n\tparameter  [4:0] RX_PCS_RESET_TIME = 3,\r\n\tparameter  [4:0] RX_RESET_TIMER_PRESC = 0,\r\n\tparameter  [0:0] RX_RESET_DONE_GATE = 0,\r\n\tparameter  [4:0] RX_CDR_RESET_TIME = 3,\r\n\tparameter  [4:0] RX_EQA_RESET_TIME = 3,\r\n\tparameter  [4:0] RX_PMA_RESET_TIME = 3,\r\n\tparameter  [0:0] RX_WAIT_CDR_LOCK = 1,\r\n\tparameter  [0:0] RX_CALIB_EN = 0,\r\n\tparameter  [0:0] RX_CALIB_OVR = 0,\r\n\tparameter  [3:0] RX_CALIB_VAL = 0,\r\n\tparameter  [2:0] RX_RTERM_VCMSEL = 4,\r\n\tparameter  [0:0] RX_RTERM_PD = 0,\r\n\tparameter  [7:0] RX_EQA_CKP_LF = 8'hA3,\r\n\tparameter  [7:0] RX_EQA_CKP_HF = 8'hA3,\r\n\tparameter  [7:0] RX_EQA_CKP_OFFSET = 8'h01,\r\n\tparameter  [0:0] RX_EN_EQA = 0,\r\n\tparameter  [3:0] RX_EQA_LOCK_CFG = 0,\r\n\tparameter  [4:0] RX_TH_MON1 = 8,\r\n\tparameter  [3:0] RX_EN_EQA_EXT_VALUE = 0,\r\n\tparameter  [4:0] RX_TH_MON2 = 8,\r\n\tparameter  [4:0] RX_TAPW = 8,\r\n\tparameter  [4:0] RX_AFE_OFFSET = 8,\r\n\tparameter [15:0] RX_EQA_CONFIG = 16'h01C0,\r\n\tparameter  [4:0] RX_AFE_PEAK = 16,\r\n\tparameter  [3:0] RX_AFE_GAIN = 8,\r\n\tparameter  [2:0] RX_AFE_VCMSEL = 4,\r\n\tparameter  [7:0] RX_CDR_CKP = 8'hF8,\r\n\tparameter  [7:0] RX_CDR_CKI = 0,\r\n\tparameter  [8:0] RX_CDR_TRANS_TH = 128,\r\n\tparameter  [5:0] RX_CDR_LOCK_CFG = 8'h0B,\r\n\tparameter [14:0] RX_CDR_FREQ_ACC = 0,\r\n\tparameter [15:0] RX_CDR_PHASE_ACC = 0,\r\n\tparameter  [1:0] RX_CDR_SET_ACC_CONFIG = 0,\r\n\tparameter  [0:0] RX_CDR_FORCE_LOCK = 0,\r\n\tparameter  [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283,\r\n\tparameter  [0:0] RX_MCOMMA_ALIGN_OVR = 0,\r\n\tparameter  [0:0] RX_MCOMMA_ALIGN = 0,\r\n\tparameter  [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C,\r\n\tparameter  [0:0] RX_PCOMMA_ALIGN_OVR = 0,\r\n\tparameter  [0:0] RX_PCOMMA_ALIGN = 0,\r\n\tparameter  [1:0] RX_ALIGN_COMMA_WORD = 0,\r\n\tparameter  [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF,\r\n\tparameter  [1:0] RX_SLIDE_MODE = 0,\r\n\tparameter  [0:0] RX_COMMA_DETECT_EN_OVR = 0,\r\n\tparameter  [0:0] RX_COMMA_DETECT_EN = 0,\r\n\tparameter  [1:0] RX_SLIDE = 0,\r\n\tparameter  [0:0] RX_EYE_MEAS_EN = 0,\r\n\tparameter [14:0] RX_EYE_MEAS_CFG = 0,\r\n\tparameter  [5:0] RX_MON_PH_OFFSET = 0,\r\n\tparameter  [3:0] RX_EI_BIAS = 0,\r\n\tparameter  [3:0] RX_EI_BW_SEL = 4,\r\n\tparameter  [0:0] RX_EN_EI_DETECTOR_OVR = 0,\r\n\tparameter  [0:0] RX_EN_EI_DETECTOR = 0,\r\n\tparameter  [0:0] RX_DATA_SEL = 0,\r\n\tparameter  [0:0] RX_BUF_BYPASS = 0,\r\n\tparameter  [0:0] RX_CLKCOR_USE = 0,\r\n\tparameter  [5:0] RX_CLKCOR_MIN_LAT = 32,\r\n\tparameter  [5:0] RX_CLKCOR_MAX_LAT = 39,\r\n\tparameter  [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7,\r\n\tparameter  [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7,\r\n\tparameter  [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7,\r\n\tparameter  [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7,\r\n\tparameter  [0:0] RX_PMA_LOOPBACK = 0,\r\n\tparameter  [0:0] RX_PCS_LOOPBACK = 0,\r\n\tparameter  [1:0] RX_DATAPATH_SEL = 3,\r\n\tparameter  [0:0] RX_PRBS_OVR = 0,\r\n\tparameter  [2:0] RX_PRBS_SEL = 0,\r\n\tparameter  [0:0] RX_LOOPBACK_OVR = 0,\r\n\tparameter  [0:0] RX_PRBS_CNT_RESET = 0,\r\n\tparameter  [0:0] RX_POWER_DOWN_OVR = 0,\r\n\tparameter  [0:0] RX_POWER_DOWN_N = 0,\r\n\tparameter  [0:0] RX_RESET_OVR = 0,\r\n\tparameter  [0:0] RX_RESET = 0,\r\n\tparameter  [0:0] RX_PMA_RESET_OVR = 0,\r\n\tparameter  [0:0] RX_PMA_RESET = 0,\r\n\tparameter  [0:0] RX_EQA_RESET_OVR = 0,\r\n\tparameter  [0:0] RX_EQA_RESET = 0,\r\n\tparameter  [0:0] RX_CDR_RESET_OVR = 0,\r\n\tparameter  [0:0] RX_CDR_RESET = 0,\r\n\tparameter  [0:0] RX_PCS_RESET_OVR = 0,\r\n\tparameter  [0:0] RX_PCS_RESET = 0,\r\n\tparameter  [0:0] RX_BUF_RESET_OVR = 0,\r\n\tparameter  [0:0] RX_BUF_RESET = 0,\r\n\tparameter  [0:0] RX_POLARITY_OVR = 0,\r\n\tparameter  [0:0] RX_POLARITY = 0,\r\n\tparameter  [0:0] RX_8B10B_EN_OVR = 0,\r\n\tparameter  [0:0] RX_8B10B_EN = 0,\r\n\tparameter  [7:0] RX_8B10B_BYPASS = 0,\r\n\tparameter  [0:0] RX_BYTE_REALIGN = 0,\r\n\tparameter  [0:0] RX_DBG_EN = 0,\r\n\tparameter  [1:0] RX_DBG_SEL = 0,\r\n\tparameter  [0:0] RX_DBG_MODE = 0,\r\n\tparameter  [5:0] RX_DBG_SRAM_DELAY = 6'h05,\r\n\tparameter  [9:0] RX_DBG_ADDR = 0,\r\n\tparameter  [0:0] RX_DBG_RE = 0,\r\n\tparameter  [0:0] RX_DBG_WE = 0,\r\n\tparameter [19:0] RX_DBG_DATA = 0,\r\n\tparameter  [4:0] TX_SEL_PRE = 0,\r\n\tparameter  [4:0] TX_SEL_POST = 0,\r\n\tparameter  [4:0] TX_AMP = 15,\r\n\tparameter  [4:0] TX_BRANCH_EN_PRE = 0,\r\n\tparameter  [5:0] TX_BRANCH_EN_MAIN = 6'h3F,\r\n\tparameter  [4:0] TX_BRANCH_EN_POST = 0,\r\n\tparameter  [2:0] TX_TAIL_CASCODE = 4,\r\n\tparameter  [6:0] TX_DC_ENABLE = 63,\r\n\tparameter  [4:0] TX_DC_OFFSET = 0,\r\n\tparameter  [4:0] TX_CM_RAISE = 0,\r\n\tparameter  [4:0] TX_CM_THRESHOLD_0 = 14,\r\n\tparameter  [4:0] TX_CM_THRESHOLD_1 = 16,\r\n\tparameter  [4:0] TX_SEL_PRE_EI = 0,\r\n\tparameter  [4:0] TX_SEL_POST_EI = 0,\r\n\tparameter  [4:0] TX_AMP_EI = 15,\r\n\tparameter  [4:0] TX_BRANCH_EN_PRE_EI = 0,\r\n\tparameter  [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F,\r\n\tparameter  [4:0] TX_BRANCH_EN_POST_EI = 0,\r\n\tparameter  [2:0] TX_TAIL_CASCODE_EI = 4,\r\n\tparameter  [6:0] TX_DC_ENABLE_EI = 63,\r\n\tparameter  [4:0] TX_DC_OFFSET_EI = 0,\r\n\tparameter  [4:0] TX_CM_RAISE_EI = 0,\r\n\tparameter  [4:0] TX_CM_THRESHOLD_0_EI = 14,\r\n\tparameter  [4:0] TX_CM_THRESHOLD_1_EI = 16,\r\n\tparameter  [4:0] TX_SEL_PRE_RXDET = 0,\r\n\tparameter  [4:0] TX_SEL_POST_RXDET = 0,\r\n\tparameter  [4:0] TX_AMP_RXDET = 15,\r\n\tparameter  [4:0] TX_BRANCH_EN_PRE_RXDET = 0,\r\n\tparameter  [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F,\r\n\tparameter  [4:0] TX_BRANCH_EN_POST_RXDET = 0,\r\n\tparameter  [2:0] TX_TAIL_CASCODE_RXDET = 4,\r\n\tparameter  [6:0] TX_DC_ENABLE_RXDET = 63,\r\n\tparameter  [4:0] TX_DC_OFFSET_RXDET = 0,\r\n\tparameter  [4:0] TX_CM_RAISE_RXDET = 0,\r\n\tparameter  [4:0] TX_CM_THRESHOLD_0_RXDET = 14,\r\n\tparameter  [4:0] TX_CM_THRESHOLD_1_RXDET = 16,\r\n\tparameter  [0:0] TX_CALIB_EN = 0,\r\n\tparameter  [0:0] TX_CALIB_OVR = 0,\r\n\tparameter  [3:0] TX_CALIB_VAL = 0,\r\n\tparameter  [7:0] TX_CM_REG_KI = 8'h80,\r\n\tparameter  [0:0] TX_CM_SAR_EN = 0,\r\n\tparameter  [0:0] TX_CM_REG_EN = 1,\r\n\tparameter  [4:0] TX_PMA_RESET_TIME = 3,\r\n\tparameter  [4:0] TX_PCS_RESET_TIME = 3,\r\n\tparameter  [0:0] TX_PCS_RESET_OVR = 0,\r\n\tparameter  [0:0] TX_PCS_RESET = 0,\r\n\tparameter  [0:0] TX_PMA_RESET_OVR = 0,\r\n\tparameter  [0:0] TX_PMA_RESET = 0,\r\n\tparameter  [0:0] TX_RESET_OVR = 0,\r\n\tparameter  [0:0] TX_RESET = 0,\r\n\tparameter  [1:0] TX_PMA_LOOPBACK = 0,\r\n\tparameter  [0:0] TX_PCS_LOOPBACK = 0,\r\n\tparameter  [1:0] TX_DATAPATH_SEL = 3,\r\n\tparameter  [0:0] TX_PRBS_OVR = 0,\r\n\tparameter  [2:0] TX_PRBS_SEL = 0,\r\n\tparameter  [0:0] TX_PRBS_FORCE_ERR = 0,\r\n\tparameter  [0:0] TX_LOOPBACK_OVR = 0,\r\n\tparameter  [0:0] TX_POWER_DOWN_OVR = 0,\r\n\tparameter  [0:0] TX_POWER_DOWN_N = 0,\r\n\tparameter  [0:0] TX_ELEC_IDLE_OVR = 0,\r\n\tparameter  [0:0] TX_ELEC_IDLE = 0,\r\n\tparameter  [0:0] TX_DETECT_RX_OVR = 0,\r\n\tparameter  [0:0] TX_DETECT_RX = 0,\r\n\tparameter  [0:0] TX_POLARITY_OVR = 0,\r\n\tparameter  [0:0] TX_POLARITY = 0,\r\n\tparameter  [0:0] TX_8B10B_EN_OVR = 0,\r\n\tparameter  [0:0] TX_8B10B_EN = 0,\r\n\tparameter  [0:0] TX_DATA_OVR = 0,\r\n\tparameter  [2:0] TX_DATA_CNT = 0,\r\n\tparameter  [0:0] TX_DATA_VALID = 0,\r\n\tparameter  [0:0] PLL_EN_ADPLL_CTRL = 0,\r\n\tparameter  [0:0] PLL_CONFIG_SEL = 0,\r\n\tparameter  [0:0] PLL_SET_OP_LOCK = 0,\r\n\tparameter  [0:0] PLL_ENFORCE_LOCK = 0,\r\n\tparameter  [0:0] PLL_DISABLE_LOCK = 0,\r\n\tparameter  [0:0] PLL_LOCK_WINDOW = 1,\r\n\tparameter  [0:0] PLL_FAST_LOCK = 1,\r\n\tparameter  [0:0] PLL_SYNC_BYPASS = 0,\r\n\tparameter  [0:0] PLL_PFD_SELECT = 0,\r\n\tparameter  [0:0] PLL_REF_BYPASS = 0,\r\n\tparameter  [0:0] PLL_REF_SEL = 0,\r\n\tparameter  [0:0] PLL_REF_RTERM = 1,\r\n\tparameter  [5:0] PLL_FCNTRL = 58,\r\n\tparameter  [5:0] PLL_MAIN_DIVSEL = 27,\r\n\tparameter  [1:0] PLL_OUT_DIVSEL = 0,\r\n\tparameter  [4:0] PLL_CI = 3,\r\n\tparameter  [9:0] PLL_CP = 80,\r\n\tparameter  [3:0] PLL_AO = 0,\r\n\tparameter  [2:0] PLL_SCAP = 0,\r\n\tparameter  [1:0] PLL_FILTER_SHIFT = 2,\r\n\tparameter  [2:0] PLL_SAR_LIMIT = 2,\r\n\tparameter [10:0] PLL_FT = 512,\r\n\tparameter  [0:0] PLL_OPEN_LOOP = 0,\r\n\tparameter  [0:0] PLL_SCAP_AUTO_CAL = 1,\r\n\tparameter  [2:0] PLL_BISC_MODE = 4,\r\n\tparameter  [3:0] PLL_BISC_TIMER_MAX = 15,\r\n\tparameter  [0:0] PLL_BISC_OPT_DET_IND = 0,\r\n\tparameter  [0:0] PLL_BISC_PFD_SEL = 0,\r\n\tparameter  [0:0] PLL_BISC_DLY_DIR = 0,\r\n\tparameter  [2:0] PLL_BISC_COR_DLY = 1,\r\n\tparameter  [0:0] PLL_BISC_CAL_SIGN = 0,\r\n\tparameter  [0:0] PLL_BISC_CAL_AUTO = 1,\r\n\tparameter  [4:0] PLL_BISC_CP_MIN = 4,\r\n\tparameter  [4:0] PLL_BISC_CP_MAX = 18,\r\n\tparameter  [4:0] PLL_BISC_CP_START = 12,\r\n\tparameter  [4:0] PLL_BISC_DLY_PFD_MON_REF = 0,\r\n\tparameter  [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2,\r\n\tparameter  [0:0] SERDES_ENABLE = 0,\r\n\tparameter  [0:0] SERDES_AUTO_INIT = 0,\r\n\tparameter  [0:0] SERDES_TESTMODE = 0\r\n)(\r\n\tinput [63:0] TX_DATA_I,\r\n\tinput TX_RESET_I,\r\n\tinput TX_PCS_RESET_I,\r\n\tinput TX_PMA_RESET_I,\r\n\tinput PLL_RESET_I,\r\n\tinput TX_POWER_DOWN_N_I,\r\n\tinput TX_POLARITY_I,\r\n\tinput [2:0] TX_PRBS_SEL_I,\r\n\tinput TX_PRBS_FORCE_ERR_I,\r\n\tinput TX_8B10B_EN_I,\r\n\tinput [7:0] TX_8B10B_BYPASS_I,\r\n\tinput [7:0] TX_CHAR_IS_K_I,\r\n\tinput [7:0] TX_CHAR_DISPMODE_I,\r\n\tinput [7:0] TX_CHAR_DISPVAL_I,\r\n\tinput TX_ELEC_IDLE_I,\r\n\tinput TX_DETECT_RX_I,\r\n\tinput [2:0] LOOPBACK_I,\r\n\tinput TX_CLK_I,\r\n\tinput RX_CLK_I,\r\n\tinput RX_RESET_I,\r\n\tinput RX_PMA_RESET_I,\r\n\tinput RX_EQA_RESET_I,\r\n\tinput RX_CDR_RESET_I,\r\n\tinput RX_PCS_RESET_I,\r\n\tinput RX_BUF_RESET_I,\r\n\tinput RX_POWER_DOWN_N_I,\r\n\tinput RX_POLARITY_I,\r\n\tinput [2:0] RX_PRBS_SEL_I,\r\n\tinput RX_PRBS_CNT_RESET_I,\r\n\tinput RX_8B10B_EN_I,\r\n\tinput [7:0] RX_8B10B_BYPASS_I,\r\n\tinput RX_EN_EI_DETECTOR_I,\r\n\tinput RX_COMMA_DETECT_EN_I,\r\n\tinput RX_SLIDE_I,\r\n\tinput RX_MCOMMA_ALIGN_I,\r\n\tinput RX_PCOMMA_ALIGN_I,\r\n\tinput REGFILE_CLK_I,\r\n\tinput REGFILE_WE_I,\r\n\tinput REGFILE_EN_I,\r\n\tinput [7:0] REGFILE_ADDR_I,\r\n\tinput [15:0] REGFILE_DI_I,\r\n\tinput [15:0] REGFILE_MASK_I,\r\n\toutput [63:0] RX_DATA_O,\r\n\toutput [7:0] RX_NOT_IN_TABLE_O,\r\n\toutput [7:0] RX_CHAR_IS_COMMA_O,\r\n\toutput [7:0] RX_CHAR_IS_K_O,\r\n\toutput [7:0] RX_DISP_ERR_O,\r\n\toutput TX_DETECT_RX_DONE_O,\r\n\toutput TX_DETECT_RX_PRESENT_O,\r\n\toutput TX_BUF_ERR_O,\r\n\toutput TX_RESET_DONE_O,\r\n\toutput RX_PRBS_ERR_O,\r\n\toutput RX_BUF_ERR_O,\r\n\toutput RX_BYTE_IS_ALIGNED_O,\r\n\toutput RX_BYTE_REALIGN_O,\r\n\toutput RX_RESET_DONE_O,\r\n\toutput RX_EI_EN_O,\r\n\toutput RX_CLK_O,\r\n\toutput PLL_CLK_O,\r\n\toutput [15:0] REGFILE_DO_O,\r\n\toutput REGFILE_RDY_O\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_CFG_CTRL(\r\n\tinput [7:0] DATA,\r\n\tinput CLK,\r\n\tinput EN,\r\n\tinput RECFG,\r\n\tinput VALID\r\n);\r\nendmodule\r\n\r\n(* blackbox *) (* keep *)\r\nmodule CC_USR_RSTN (\r\n\toutput USR_RSTN\r\n);\r\nendmodule\r\n",
             "cells_sim.v": "/*\r\n *  yosys -- Yosys Open SYnthesis Suite\r\n *\r\n *  Copyright (C) 2021  Cologne Chip AG <support@colognechip.com>\r\n *\r\n *  Permission to use, copy, modify, and/or distribute this software for any\r\n *  purpose with or without fee is hereby granted, provided that the above\r\n *  copyright notice and this permission notice appear in all copies.\r\n *\r\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\n`timescale 1ps/1ps\r\n\r\nmodule CC_IBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\tparameter [0:0] SCHMITT_TRIGGER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx\r\n)(\r\n\t(* iopad_external_pin *)\r\n\tinput  I,\r\n\toutput Y\r\n);\r\n\tassign Y = I;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_OBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput  A,\r\n\t(* iopad_external_pin *)\r\n\toutput O\r\n);\r\n\tassign O = A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_TOBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput  A, T,\r\n\t(* iopad_external_pin *)\r\n\toutput O\r\n);\r\n\tassign O = T ? 1'bz : A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_IOBUF #(\r\n\tparameter PIN_NAME = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter DRIVE = \"UNDEFINED\",\r\n\tparameter SLEW = \"UNDEFINED\",\r\n\tparameter [0:0] PULLUP = 1'bx,\r\n\tparameter [0:0] PULLDOWN = 1'bx,\r\n\tparameter [0:0] KEEPER = 1'bx,\r\n\tparameter [0:0] SCHMITT_TRIGGER = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput  A, T,\r\n\toutput Y,\r\n\t(* iopad_external_pin *)\r\n\tinout  IO\r\n);\r\n\tassign IO = T ? 1'bz : A;\r\n\tassign Y = IO;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_IBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_RTERM = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx\r\n)(\r\n\t(* iopad_external_pin *)\r\n\tinput  I_P, I_N,\r\n\toutput Y\r\n);\r\n\tassign Y = I_P;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_OBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput  A,\r\n\t(* iopad_external_pin *)\r\n\toutput O_P, O_N\r\n);\r\n\tassign O_P = A;\r\n\tassign O_N = ~A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_TOBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput  A, T,\r\n\t(* iopad_external_pin *)\r\n\toutput O_P, O_N\r\n);\r\n\tassign O_P = T ? 1'bz :  A;\r\n\tassign O_N = T ? 1'bz : ~A;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LVDS_IOBUF #(\r\n\tparameter PIN_NAME_P = \"UNPLACED\",\r\n\tparameter PIN_NAME_N = \"UNPLACED\",\r\n\tparameter V_IO = \"UNDEFINED\",\r\n\tparameter [0:0] LVDS_RTERM = 1'bx,\r\n\tparameter [0:0] LVDS_BOOST = 1'bx,\r\n\t// IOSEL\r\n\tparameter [3:0] DELAY_IBF = 1'bx,\r\n\tparameter [3:0] DELAY_OBF = 1'bx,\r\n\tparameter [0:0] FF_IBF = 1'bx,\r\n\tparameter [0:0] FF_OBF = 1'bx\r\n)(\r\n\tinput  A, T,\r\n\t(* iopad_external_pin *)\r\n\tinout  IO_P, IO_N,\r\n\toutput Y\r\n);\r\n\tassign IO_P = T ? 1'bz :  A;\r\n\tassign IO_N = T ? 1'bz : ~A;\r\n\tassign Y = IO_P;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_IDDR #(\r\n\tparameter [0:0] CLK_INV = 1'b0\r\n)(\r\n\tinput D,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\toutput reg Q0, Q1\r\n);\r\n\twire clk;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\r\n\talways @(posedge clk)\r\n\tbegin\r\n\t\tQ0 <= D;\r\n\tend\r\n\r\n\talways @(negedge clk)\r\n\tbegin\r\n\t\tQ1 <= D;\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_ODDR #(\r\n\tparameter [0:0] CLK_INV = 1'b0\r\n)(\r\n\tinput D0,\r\n\tinput D1,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput DDR,\r\n\toutput Q\r\n);\r\n\twire clk;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\r\n\treg q0, q1;\r\n\tassign Q = (DDR) ? q0 : q1;\r\n\r\n\talways @(posedge clk)\r\n\tbegin\r\n\t\tq0 <= D0;\r\n\tend\r\n\r\n\talways @(negedge clk)\r\n\tbegin\r\n\t\tq1 <= D1;\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_DFF #(\r\n\tparameter [0:0] CLK_INV = 1'b0,\r\n\tparameter [0:0] EN_INV  = 1'b0,\r\n\tparameter [0:0] SR_INV  = 1'b0,\r\n\tparameter [0:0] SR_VAL  = 1'b0,\r\n\tparameter [0:0] INIT    = 1'bx\r\n)(\r\n\tinput D,\r\n\t(* clkbuf_sink *)\r\n\tinput CLK,\r\n\tinput EN,\r\n\tinput SR,\r\n\toutput reg Q\r\n);\r\n\twire clk, en, sr;\r\n\tassign clk = (CLK_INV) ? ~CLK : CLK;\r\n\tassign en  = (EN_INV)  ?  ~EN :  EN;\r\n\tassign sr  = (SR_INV)  ?  ~SR :  SR;\r\n\r\n\tinitial Q = INIT;\r\n\r\n\talways @(posedge clk or posedge sr)\r\n\tbegin\r\n\t\tif (sr) begin\r\n\t\t\tQ <= SR_VAL;\r\n\t\tend\r\n\t\telse if (en) begin\r\n\t\t\tQ <= D;\r\n\t\tend\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_DLT #(\r\n\tparameter [0:0] G_INV  = 1'b0,\r\n\tparameter [0:0] SR_INV = 1'b0,\r\n\tparameter [0:0] SR_VAL = 1'b0,\r\n\tparameter [0:0] INIT   = 1'bx\r\n)(\r\n\tinput D,\r\n\tinput G,\r\n\tinput SR,\r\n\toutput reg Q\r\n);\r\n\twire en, sr;\r\n\tassign en  = (G_INV) ? ~G : G;\r\n\tassign sr  = (SR_INV) ? ~SR : SR;\r\n\r\n\tinitial Q = INIT;\r\n\r\n\talways @(*)\r\n\tbegin\r\n\t\tif (sr) begin\r\n\t\t\tQ <= SR_VAL;\r\n\t\tend\r\n\t\telse if (en) begin\r\n\t\t\tQ <= D;\r\n\t\tend\r\n\tend\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT1 (\r\n\toutput O,\r\n\tinput  I0\r\n);\r\n\tparameter [1:0] INIT = 0;\r\n\r\n\tassign O = I0 ? INIT[1] : INIT[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT2 (\r\n\toutput O,\r\n\tinput  I0, I1\r\n);\r\n\tparameter [3:0] INIT = 0;\r\n\r\n\twire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT3 (\r\n\toutput O,\r\n\tinput  I0, I1, I2\r\n);\r\n\tparameter [7:0] INIT = 0;\r\n\r\n\twire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];\r\n\twire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_LUT4 (\r\n\toutput O,\r\n\tinput  I0, I1, I2, I3\r\n);\r\n\tparameter [15:0] INIT = 0;\r\n\r\n\twire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];\r\n\twire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];\r\n\twire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];\r\n\tassign O = I0 ? s1[1] : s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX2 (\r\n\tinput  D0, D1,\r\n\tinput  S0,\r\n\toutput Y\r\n);\r\n\tassign Y = S0 ? D1 : D0;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX4 (\r\n\tinput  D0, D1, D2, D3,\r\n\tinput  S0, S1,\r\n\toutput Y\r\n);\r\n\tassign Y = S1 ? (S0 ? D3 : D2) :\r\n\t\t\t\t\t(S0 ? D1 : D0);\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MX8 (\r\n\tinput  D0, D1, D2, D3,\r\n\tinput  D4, D5, D6, D7,\r\n\tinput  S0, S1, S2,\r\n\toutput Y\r\n);\r\n\tassign Y = S2 ? (S1 ? (S0 ? D7 : D6) :\r\n\t\t\t\t\t\t  (S0 ? D5 : D4)) :\r\n\t\t\t\t\t(S1 ? (S0 ? D3 : D2) :\r\n\t\t\t\t\t\t  (S0 ? D1 : D0));\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_ADDF (\r\n\tinput  A, B, CI,\r\n\toutput CO, S\r\n);\r\n\tassign {CO, S} = A + B + CI;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_MULT #(\r\n\tparameter A_WIDTH = 0,\r\n\tparameter B_WIDTH = 0,\r\n\tparameter P_WIDTH = 0\r\n)(\r\n\tinput signed [A_WIDTH-1:0] A,\r\n\tinput signed [B_WIDTH-1:0] B,\r\n\toutput reg signed [P_WIDTH-1:0] P\r\n);\r\n\talways @(*)\r\n\tbegin\r\n\t\tP <= A * B;\r\n\tend\r\nendmodule\r\n\r\n\r\nmodule CC_BUFG (\r\n\tinput  I,\r\n\t(* clkbuf_driver *)\r\n\toutput O\r\n);\r\n\tassign O = I;\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_BRAM_20K (\r\n\toutput [19:0] A_DO,\r\n\toutput [19:0] B_DO,\r\n\toutput ECC_1B_ERR,\r\n\toutput ECC_2B_ERR,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput A_EN,\r\n\tinput B_EN,\r\n\tinput A_WE,\r\n\tinput B_WE,\r\n\tinput [15:0] A_ADDR,\r\n\tinput [15:0] B_ADDR,\r\n\tinput [19:0] A_DI,\r\n\tinput [19:0] B_DI,\r\n\tinput [19:0] A_BM,\r\n\tinput [19:0] B_BM\r\n);\r\n\t// Location format: D(0..N-1)(0..N-1)X(0..3)Y(0..7)Z(0..1) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\r\n\t// Port Widths\r\n\tparameter A_RD_WIDTH = 0;\r\n\tparameter B_RD_WIDTH = 0;\r\n\tparameter A_WR_WIDTH = 0;\r\n\tparameter B_WR_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"SDP\";\r\n\tparameter A_WR_MODE = \"NO_CHANGE\";\r\n\tparameter B_WR_MODE = \"NO_CHANGE\";\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter ECC_EN = 1'b0;\r\n\r\n\t// RAM Contents\r\n\tparameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\r\n\tlocalparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH;\r\n\tlocalparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 40 bit\r\n\treg [20479:0] memory = 20480'b0;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WR_MODE != \"WRITE_THROUGH\") && (A_WR_MODE != \"NO_CHANGE\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (A_WR_MODE == \"WRITE_THROUGH\")) begin\r\n\t\t\t$display(\"ERROR: %s is not supported in %s mode.\", A_WR_MODE, RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif (ECC_EN != 1'b0) begin\r\n\t\t\t$display(\"WARNING: ECC feature not supported in simulation.\");\r\n\t\tend\r\n\t\tif ((ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (WIDTH_MODE_A != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port configuration. Must be SDP 40 bit, but is %s %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A == 40) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 40 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B == 40) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 40 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&\r\n\t\t\t(WIDTH_MODE_A != 5)  && (WIDTH_MODE_A != 2)  && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) &&\r\n\t\t\t(WIDTH_MODE_B != 5)  && (WIDTH_MODE_B != 2)  && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, WIDTH_MODE_B);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// RAM initialization\r\n\t\tmemory[320*0+319:320*0]   = INIT_00;\r\n\t\tmemory[320*1+319:320*1]   = INIT_01;\r\n\t\tmemory[320*2+319:320*2]   = INIT_02;\r\n\t\tmemory[320*3+319:320*3]   = INIT_03;\r\n\t\tmemory[320*4+319:320*4]   = INIT_04;\r\n\t\tmemory[320*5+319:320*5]   = INIT_05;\r\n\t\tmemory[320*6+319:320*6]   = INIT_06;\r\n\t\tmemory[320*7+319:320*7]   = INIT_07;\r\n\t\tmemory[320*8+319:320*8]   = INIT_08;\r\n\t\tmemory[320*9+319:320*9]   = INIT_09;\r\n\t\tmemory[320*10+319:320*10] = INIT_0A;\r\n\t\tmemory[320*11+319:320*11] = INIT_0B;\r\n\t\tmemory[320*12+319:320*12] = INIT_0C;\r\n\t\tmemory[320*13+319:320*13] = INIT_0D;\r\n\t\tmemory[320*14+319:320*14] = INIT_0E;\r\n\t\tmemory[320*15+319:320*15] = INIT_0F;\r\n\t\tmemory[320*16+319:320*16] = INIT_10;\r\n\t\tmemory[320*17+319:320*17] = INIT_11;\r\n\t\tmemory[320*18+319:320*18] = INIT_12;\r\n\t\tmemory[320*19+319:320*19] = INIT_13;\r\n\t\tmemory[320*20+319:320*20] = INIT_14;\r\n\t\tmemory[320*21+319:320*21] = INIT_15;\r\n\t\tmemory[320*22+319:320*22] = INIT_16;\r\n\t\tmemory[320*23+319:320*23] = INIT_17;\r\n\t\tmemory[320*24+319:320*24] = INIT_18;\r\n\t\tmemory[320*25+319:320*25] = INIT_19;\r\n\t\tmemory[320*26+319:320*26] = INIT_1A;\r\n\t\tmemory[320*27+319:320*27] = INIT_1B;\r\n\t\tmemory[320*28+319:320*28] = INIT_1C;\r\n\t\tmemory[320*29+319:320*29] = INIT_1D;\r\n\t\tmemory[320*30+319:320*30] = INIT_1E;\r\n\t\tmemory[320*31+319:320*31] = INIT_1F;\r\n\t\tmemory[320*32+319:320*32] = INIT_20;\r\n\t\tmemory[320*33+319:320*33] = INIT_21;\r\n\t\tmemory[320*34+319:320*34] = INIT_22;\r\n\t\tmemory[320*35+319:320*35] = INIT_23;\r\n\t\tmemory[320*36+319:320*36] = INIT_24;\r\n\t\tmemory[320*37+319:320*37] = INIT_25;\r\n\t\tmemory[320*38+319:320*38] = INIT_26;\r\n\t\tmemory[320*39+319:320*39] = INIT_27;\r\n\t\tmemory[320*40+319:320*40] = INIT_28;\r\n\t\tmemory[320*41+319:320*41] = INIT_29;\r\n\t\tmemory[320*42+319:320*42] = INIT_2A;\r\n\t\tmemory[320*43+319:320*43] = INIT_2B;\r\n\t\tmemory[320*44+319:320*44] = INIT_2C;\r\n\t\tmemory[320*45+319:320*45] = INIT_2D;\r\n\t\tmemory[320*46+319:320*46] = INIT_2E;\r\n\t\tmemory[320*47+319:320*47] = INIT_2F;\r\n\t\tmemory[320*48+319:320*48] = INIT_30;\r\n\t\tmemory[320*49+319:320*49] = INIT_31;\r\n\t\tmemory[320*50+319:320*50] = INIT_32;\r\n\t\tmemory[320*51+319:320*51] = INIT_33;\r\n\t\tmemory[320*52+319:320*52] = INIT_34;\r\n\t\tmemory[320*53+319:320*53] = INIT_35;\r\n\t\tmemory[320*54+319:320*54] = INIT_36;\r\n\t\tmemory[320*55+319:320*55] = INIT_37;\r\n\t\tmemory[320*56+319:320*56] = INIT_38;\r\n\t\tmemory[320*57+319:320*57] = INIT_39;\r\n\t\tmemory[320*58+319:320*58] = INIT_3A;\r\n\t\tmemory[320*59+319:320*59] = INIT_3B;\r\n\t\tmemory[320*60+319:320*60] = INIT_3C;\r\n\t\tmemory[320*61+319:320*61] = INIT_3D;\r\n\t\tmemory[320*62+319:320*62] = INIT_3E;\r\n\t\tmemory[320*63+319:320*63] = INIT_3F;\r\n\tend\r\n\r\n\t// Signal inversion\r\n\twire clka = A_CLK_INV ^ A_CLK;\r\n\twire clkb = B_CLK_INV ^ B_CLK;\r\n\twire ena  = A_EN_INV ^ A_EN;\r\n\twire enb  = B_EN_INV ^ B_EN;\r\n\twire wea  = A_WE_INV ^ A_WE;\r\n\twire web  = B_WE_INV ^ B_WE;\r\n\r\n\t// Internal signals\r\n\twire [15:0] addra;\r\n\twire [15:0] addrb;\r\n\treg  [19:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg  [19:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// Port A (write)\r\n\t\t\tif (A_WR_WIDTH == 40) begin\r\n\t\t\t\tassign addra = A_ADDR[15:7]*40;\r\n\t\t\tend\r\n\t\t\t// Port B (read)\r\n\t\t\tif (B_RD_WIDTH == 40) begin\r\n\t\t\t\tassign addrb = B_ADDR[15:7]*40;\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// Port A\r\n\t\t\tif (WIDTH_MODE_A <= 1) begin\r\n\t\t\t\twire [15:0] tmpa = {2'b0, A_ADDR[15:7], A_ADDR[5:1]};\r\n\t\t\t\tassign addra = tmpa + (tmpa/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 2) begin\r\n\t\t\t\twire [15:0] tmpa = {3'b0, A_ADDR[15:7], A_ADDR[5:2]};\r\n\t\t\t\tassign addra = tmpa*2 + (tmpa/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 5) begin\r\n\t\t\t\tassign addra = {4'b0, A_ADDR[15:7], A_ADDR[5:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 10) begin\r\n\t\t\t\tassign addra = {5'b0, A_ADDR[15:7], A_ADDR[5:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 20) begin\r\n\t\t\t\tassign addra = {6'b0, A_ADDR[15:7], A_ADDR[5]}*20;\r\n\t\t\tend\r\n\t\t\t// Port B\r\n\t\t\tif (WIDTH_MODE_B <= 1) begin\r\n\t\t\t\twire [15:0] tmpb = {2'b0, B_ADDR[15:7], B_ADDR[5:1]};\r\n\t\t\t\tassign addrb = tmpb + (tmpb/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 2) begin\r\n\t\t\t\twire [15:0] tmpb = {3'b0, B_ADDR[15:7], B_ADDR[5:2]};\r\n\t\t\t\tassign addrb = tmpb*2 + (tmpb/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 5) begin\r\n\t\t\t\tassign addrb = {4'b0, B_ADDR[15:7], B_ADDR[5:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 10) begin\r\n\t\t\t\tassign addrb = {5'b0, B_ADDR[15:7], B_ADDR[5:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 20) begin\r\n\t\t\t\tassign addrb = {6'b0, B_ADDR[15:7], B_ADDR[5]}*20;\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP write port\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WR_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 20) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ena && wea && B_BM[k-20]) memory[addra+k] <= B_DI[k-20];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP read port\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_RD_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 20) begin\r\n\t\t\t\t\t\tif (enb) A_DO_out[k] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (enb) B_DO_out[k-20] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// TDP port A\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_A; i=i+1) begin\r\n\t\t\t\t\tif (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i];\r\n\r\n\t\t\t\t\tif (A_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (ena && !wea) A_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (A_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (ena) begin\r\n\t\t\t\t\t\t\tif (wea && A_BM[i]) begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= A_DI[i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP port B\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_B; i=i+1) begin\r\n\t\t\t\t\tif (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i];\r\n\r\n\t\t\t\t\tif (B_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (enb && !web) B_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (B_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (enb) begin\r\n\t\t\t\t\t\t\tif (web && B_BM[i]) begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= B_DI[i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge clka) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge clkb) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\n\r\nmodule CC_BRAM_40K (\r\n\toutput [39:0] A_DO,\r\n\toutput [39:0] B_DO,\r\n\toutput A_ECC_1B_ERR,\r\n\toutput B_ECC_1B_ERR,\r\n\toutput A_ECC_2B_ERR,\r\n\toutput B_ECC_2B_ERR,\r\n\toutput reg A_CO = 0,\r\n\toutput reg B_CO = 0,\r\n\t(* clkbuf_sink *)\r\n\tinput A_CLK,\r\n\t(* clkbuf_sink *)\r\n\tinput B_CLK,\r\n\tinput A_EN,\r\n\tinput B_EN,\r\n\tinput A_WE,\r\n\tinput B_WE,\r\n\tinput [15:0] A_ADDR,\r\n\tinput [15:0] B_ADDR,\r\n\tinput [39:0] A_DI,\r\n\tinput [39:0] B_DI,\r\n\tinput [39:0] A_BM,\r\n\tinput [39:0] B_BM,\r\n\tinput A_CI,\r\n\tinput B_CI\r\n);\r\n\t// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\tparameter CAS = \"NONE\"; // NONE, UPPER, LOWER\r\n\r\n\t// Port Widths\r\n\tparameter A_RD_WIDTH = 0;\r\n\tparameter B_RD_WIDTH = 0;\r\n\tparameter A_WR_WIDTH = 0;\r\n\tparameter B_WR_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"SDP\";\r\n\tparameter A_WR_MODE = \"NO_CHANGE\";\r\n\tparameter B_WR_MODE = \"NO_CHANGE\";\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter A_ECC_EN  = 1'b0;\r\n\tparameter B_ECC_EN  = 1'b0;\r\n\r\n\tparameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_40 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_41 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_42 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_43 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_44 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_45 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_46 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_47 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_48 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_49 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_4F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_50 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_51 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_52 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_53 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_54 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_55 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_56 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_57 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_58 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_59 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_5F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_60 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_61 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_62 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_63 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_64 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_65 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_66 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_67 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_68 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_69 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_6F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_70 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_71 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_72 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_73 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_74 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_75 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_76 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_77 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_78 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_79 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\tparameter INIT_7F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;\r\n\r\n\tlocalparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH;\r\n\tlocalparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 80 bit\r\n\treg [40959:0] memory = 40960'b0;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WR_MODE != \"WRITE_THROUGH\") && (A_WR_MODE != \"NO_CHANGE\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (A_WR_MODE == \"WRITE_THROUGH\")) begin\r\n\t\t\t$display(\"ERROR: %s is not supported in %s mode.\", A_WR_MODE, RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_ECC_EN != 1'b0) || (B_ECC_EN != 1'b0)) begin\r\n\t\t\t$display(\"WARNING: ECC feature not supported in simulation.\");\r\n\t\tend\r\n\t\tif ((A_ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (WIDTH_MODE_A != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port A configuration. Must be SDP 40 bit, but is %s %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&\r\n\t\t\t(WIDTH_MODE_A != 5)  && (WIDTH_MODE_A != 2)  && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, WIDTH_MODE_A);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((WIDTH_MODE_B != 80) && (WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) &&\r\n\t\t\t(WIDTH_MODE_B != 5)  && (WIDTH_MODE_B != 2)  && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, WIDTH_MODE_B);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((CAS != \"NONE\") && ((WIDTH_MODE_A > 1) || (WIDTH_MODE_B > 1))) begin\r\n\t\t\t$display(\"ERROR: Cascade feature only supported in 1 bit data width mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((CAS != \"NONE\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Cascade feature only supported in TDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// RAM initialization\r\n\t\tmemory[320*0+319:320*0]     = INIT_00;\r\n\t\tmemory[320*1+319:320*1]     = INIT_01;\r\n\t\tmemory[320*2+319:320*2]     = INIT_02;\r\n\t\tmemory[320*3+319:320*3]     = INIT_03;\r\n\t\tmemory[320*4+319:320*4]     = INIT_04;\r\n\t\tmemory[320*5+319:320*5]     = INIT_05;\r\n\t\tmemory[320*6+319:320*6]     = INIT_06;\r\n\t\tmemory[320*7+319:320*7]     = INIT_07;\r\n\t\tmemory[320*8+319:320*8]     = INIT_08;\r\n\t\tmemory[320*9+319:320*9]     = INIT_09;\r\n\t\tmemory[320*10+319:320*10]   = INIT_0A;\r\n\t\tmemory[320*11+319:320*11]   = INIT_0B;\r\n\t\tmemory[320*12+319:320*12]   = INIT_0C;\r\n\t\tmemory[320*13+319:320*13]   = INIT_0D;\r\n\t\tmemory[320*14+319:320*14]   = INIT_0E;\r\n\t\tmemory[320*15+319:320*15]   = INIT_0F;\r\n\t\tmemory[320*16+319:320*16]   = INIT_10;\r\n\t\tmemory[320*17+319:320*17]   = INIT_11;\r\n\t\tmemory[320*18+319:320*18]   = INIT_12;\r\n\t\tmemory[320*19+319:320*19]   = INIT_13;\r\n\t\tmemory[320*20+319:320*20]   = INIT_14;\r\n\t\tmemory[320*21+319:320*21]   = INIT_15;\r\n\t\tmemory[320*22+319:320*22]   = INIT_16;\r\n\t\tmemory[320*23+319:320*23]   = INIT_17;\r\n\t\tmemory[320*24+319:320*24]   = INIT_18;\r\n\t\tmemory[320*25+319:320*25]   = INIT_19;\r\n\t\tmemory[320*26+319:320*26]   = INIT_1A;\r\n\t\tmemory[320*27+319:320*27]   = INIT_1B;\r\n\t\tmemory[320*28+319:320*28]   = INIT_1C;\r\n\t\tmemory[320*29+319:320*29]   = INIT_1D;\r\n\t\tmemory[320*30+319:320*30]   = INIT_1E;\r\n\t\tmemory[320*31+319:320*31]   = INIT_1F;\r\n\t\tmemory[320*32+319:320*32]   = INIT_20;\r\n\t\tmemory[320*33+319:320*33]   = INIT_21;\r\n\t\tmemory[320*34+319:320*34]   = INIT_22;\r\n\t\tmemory[320*35+319:320*35]   = INIT_23;\r\n\t\tmemory[320*36+319:320*36]   = INIT_24;\r\n\t\tmemory[320*37+319:320*37]   = INIT_25;\r\n\t\tmemory[320*38+319:320*38]   = INIT_26;\r\n\t\tmemory[320*39+319:320*39]   = INIT_27;\r\n\t\tmemory[320*40+319:320*40]   = INIT_28;\r\n\t\tmemory[320*41+319:320*41]   = INIT_29;\r\n\t\tmemory[320*42+319:320*42]   = INIT_2A;\r\n\t\tmemory[320*43+319:320*43]   = INIT_2B;\r\n\t\tmemory[320*44+319:320*44]   = INIT_2C;\r\n\t\tmemory[320*45+319:320*45]   = INIT_2D;\r\n\t\tmemory[320*46+319:320*46]   = INIT_2E;\r\n\t\tmemory[320*47+319:320*47]   = INIT_2F;\r\n\t\tmemory[320*48+319:320*48]   = INIT_30;\r\n\t\tmemory[320*49+319:320*49]   = INIT_31;\r\n\t\tmemory[320*50+319:320*50]   = INIT_32;\r\n\t\tmemory[320*51+319:320*51]   = INIT_33;\r\n\t\tmemory[320*52+319:320*52]   = INIT_34;\r\n\t\tmemory[320*53+319:320*53]   = INIT_35;\r\n\t\tmemory[320*54+319:320*54]   = INIT_36;\r\n\t\tmemory[320*55+319:320*55]   = INIT_37;\r\n\t\tmemory[320*56+319:320*56]   = INIT_38;\r\n\t\tmemory[320*57+319:320*57]   = INIT_39;\r\n\t\tmemory[320*58+319:320*58]   = INIT_3A;\r\n\t\tmemory[320*59+319:320*59]   = INIT_3B;\r\n\t\tmemory[320*60+319:320*60]   = INIT_3C;\r\n\t\tmemory[320*61+319:320*61]   = INIT_3D;\r\n\t\tmemory[320*62+319:320*62]   = INIT_3E;\r\n\t\tmemory[320*63+319:320*63]   = INIT_3F;\r\n\t\tmemory[320*64+319:320*64]   = INIT_40;\r\n\t\tmemory[320*65+319:320*65]   = INIT_41;\r\n\t\tmemory[320*66+319:320*66]   = INIT_42;\r\n\t\tmemory[320*67+319:320*67]   = INIT_43;\r\n\t\tmemory[320*68+319:320*68]   = INIT_44;\r\n\t\tmemory[320*69+319:320*69]   = INIT_45;\r\n\t\tmemory[320*70+319:320*70]   = INIT_46;\r\n\t\tmemory[320*71+319:320*71]   = INIT_47;\r\n\t\tmemory[320*72+319:320*72]   = INIT_48;\r\n\t\tmemory[320*73+319:320*73]   = INIT_49;\r\n\t\tmemory[320*74+319:320*74]   = INIT_4A;\r\n\t\tmemory[320*75+319:320*75]   = INIT_4B;\r\n\t\tmemory[320*76+319:320*76]   = INIT_4C;\r\n\t\tmemory[320*77+319:320*77]   = INIT_4D;\r\n\t\tmemory[320*78+319:320*78]   = INIT_4E;\r\n\t\tmemory[320*79+319:320*79]   = INIT_4F;\r\n\t\tmemory[320*80+319:320*80]   = INIT_50;\r\n\t\tmemory[320*81+319:320*81]   = INIT_51;\r\n\t\tmemory[320*82+319:320*82]   = INIT_52;\r\n\t\tmemory[320*83+319:320*83]   = INIT_53;\r\n\t\tmemory[320*84+319:320*84]   = INIT_54;\r\n\t\tmemory[320*85+319:320*85]   = INIT_55;\r\n\t\tmemory[320*86+319:320*86]   = INIT_56;\r\n\t\tmemory[320*87+319:320*87]   = INIT_57;\r\n\t\tmemory[320*88+319:320*88]   = INIT_58;\r\n\t\tmemory[320*89+319:320*89]   = INIT_59;\r\n\t\tmemory[320*90+319:320*90]   = INIT_5A;\r\n\t\tmemory[320*91+319:320*91]   = INIT_5B;\r\n\t\tmemory[320*92+319:320*92]   = INIT_5C;\r\n\t\tmemory[320*93+319:320*93]   = INIT_5D;\r\n\t\tmemory[320*94+319:320*94]   = INIT_5E;\r\n\t\tmemory[320*95+319:320*95]   = INIT_5F;\r\n\t\tmemory[320*96+319:320*96]   = INIT_60;\r\n\t\tmemory[320*97+319:320*97]   = INIT_61;\r\n\t\tmemory[320*98+319:320*98]   = INIT_62;\r\n\t\tmemory[320*99+319:320*99]   = INIT_63;\r\n\t\tmemory[320*100+319:320*100] = INIT_64;\r\n\t\tmemory[320*101+319:320*101] = INIT_65;\r\n\t\tmemory[320*102+319:320*102] = INIT_66;\r\n\t\tmemory[320*103+319:320*103] = INIT_67;\r\n\t\tmemory[320*104+319:320*104] = INIT_68;\r\n\t\tmemory[320*105+319:320*105] = INIT_69;\r\n\t\tmemory[320*106+319:320*106] = INIT_6A;\r\n\t\tmemory[320*107+319:320*107] = INIT_6B;\r\n\t\tmemory[320*108+319:320*108] = INIT_6C;\r\n\t\tmemory[320*109+319:320*109] = INIT_6D;\r\n\t\tmemory[320*110+319:320*110] = INIT_6E;\r\n\t\tmemory[320*111+319:320*111] = INIT_6F;\r\n\t\tmemory[320*112+319:320*112] = INIT_70;\r\n\t\tmemory[320*113+319:320*113] = INIT_71;\r\n\t\tmemory[320*114+319:320*114] = INIT_72;\r\n\t\tmemory[320*115+319:320*115] = INIT_73;\r\n\t\tmemory[320*116+319:320*116] = INIT_74;\r\n\t\tmemory[320*117+319:320*117] = INIT_75;\r\n\t\tmemory[320*118+319:320*118] = INIT_76;\r\n\t\tmemory[320*119+319:320*119] = INIT_77;\r\n\t\tmemory[320*120+319:320*120] = INIT_78;\r\n\t\tmemory[320*121+319:320*121] = INIT_79;\r\n\t\tmemory[320*122+319:320*122] = INIT_7A;\r\n\t\tmemory[320*123+319:320*123] = INIT_7B;\r\n\t\tmemory[320*124+319:320*124] = INIT_7C;\r\n\t\tmemory[320*125+319:320*125] = INIT_7D;\r\n\t\tmemory[320*126+319:320*126] = INIT_7E;\r\n\t\tmemory[320*127+319:320*127] = INIT_7F;\r\n\tend\r\n\r\n\t// Signal inversion\r\n\twire clka = A_CLK_INV ^ A_CLK;\r\n\twire clkb = B_CLK_INV ^ B_CLK;\r\n\twire ena  = A_EN_INV ^ A_EN;\r\n\twire enb  = B_EN_INV ^ B_EN;\r\n\twire wea  = A_WE_INV ^ A_WE;\r\n\twire web  = B_WE_INV ^ B_WE;\r\n\r\n\t// Internal signals\r\n\twire [15:0] addra;\r\n\twire [15:0] addrb;\r\n\treg  [39:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg  [39:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// Port A (write)\r\n\t\t\t if (A_WR_WIDTH == 80) begin\r\n\t\t\t\tassign addra = A_ADDR[15:7]*80;\r\n\t\t\tend\r\n\t\t\t// Port B (read)\r\n\t\t\tif (B_RD_WIDTH == 80) begin\r\n\t\t\t\tassign addrb = B_ADDR[15:7]*80;\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// Port A\r\n\t\t\tif (WIDTH_MODE_A <= 1) begin\r\n\t\t\t\twire [15:0] tmpa = {1'b0, A_ADDR[15:1]};\r\n\t\t\t\tassign addra = tmpa + (tmpa/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 2) begin\r\n\t\t\t\twire [15:0] tmpa = {2'b0, A_ADDR[15:2]};\r\n\t\t\t\tassign addra = tmpa*2 + (tmpa/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 5) begin\r\n\t\t\t\tassign addra = {3'b0, A_ADDR[15:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 10) begin\r\n\t\t\t\tassign addra = {4'b0, A_ADDR[15:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 20) begin\r\n\t\t\t\tassign addra = {5'b0, A_ADDR[15:5]}*20;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_A <= 40) begin\r\n\t\t\t\tassign addra = {6'b0, A_ADDR[15:6]}*40;\r\n\t\t\tend\r\n\t\t\t// Port B\r\n\t\t\tif (WIDTH_MODE_B <= 1) begin\r\n\t\t\t\twire [15:0] tmpb = {1'b0, B_ADDR[15:1]};\r\n\t\t\t\tassign addrb = tmpb + (tmpb/4);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 2) begin\r\n\t\t\t\twire [15:0] tmpb = {2'b0, B_ADDR[15:2]};\r\n\t\t\t\tassign addrb = tmpb*2 + (tmpb/2);\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 5) begin\r\n\t\t\t\tassign addrb = {3'b0, B_ADDR[15:3]}*5;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 10) begin\r\n\t\t\t\tassign addrb = {4'b0, B_ADDR[15:4]}*10;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 20) begin\r\n\t\t\t\tassign addrb = {5'b0, B_ADDR[15:5]}*20;\r\n\t\t\tend\r\n\t\t\telse if (WIDTH_MODE_B <= 40) begin\r\n\t\t\t\tassign addrb = {6'b0, B_ADDR[15:6]}*40;\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\tgenerate\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP write port\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WR_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ena && wea && B_BM[k-40]) memory[addra+k] <= B_DI[k-40];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP read port\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_RD_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (enb) A_DO_out[k] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (enb) B_DO_out[k-40] <= memory[addrb+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// {A,B}_ADDR[0]=0 selects lower, {A,B}_ADDR[0]=1 selects upper cascade memory\r\n\t\t\twire upper_sel_a = ((CAS == \"UPPER\") && (A_ADDR[0] == 1));\r\n\t\t\twire lower_sel_a = ((CAS == \"LOWER\") && (A_ADDR[0] == 0));\r\n\t\t\twire upper_sel_b = ((CAS == \"UPPER\") && (B_ADDR[0] == 1));\r\n\t\t\twire lower_sel_b = ((CAS == \"LOWER\") && (B_ADDR[0] == 0));\r\n\r\n\t\t\treg dumm;\r\n\r\n\t\t\t// Cascade output port A\r\n\t\t\talways @(*)\r\n\t\t\tbegin\r\n\t\t\t\tif ((A_WR_MODE == \"NO_CHANGE\") && lower_sel_a) begin\r\n\t\t\t\t\tA_CO = memory[addra];\r\n\t\t\t\tend\r\n\t\t\t\telse if ((A_WR_MODE == \"WRITE_THROUGH\") && lower_sel_a) begin\r\n\t\t\t\t\tA_CO = ((wea && A_BM[0]) ? (A_DI[0]) : (memory[addra]));\r\n\t\t\t\tend\r\n\t\t\tend\r\n\r\n\t\t\t// Cascade output port B\r\n\t\t\talways @(*)\r\n\t\t\tbegin\r\n\t\t\t\tif ((B_WR_MODE == \"NO_CHANGE\") && lower_sel_b) begin\r\n\t\t\t\t\tB_CO = memory[addrb];\r\n\t\t\t\tend\r\n\t\t\t\telse if ((B_WR_MODE == \"WRITE_THROUGH\") && lower_sel_b) begin\r\n\t\t\t\t\tB_CO = ((web && B_BM[0]) ? (B_DI[0]) : (memory[addrb]));\r\n\t\t\t\tend\r\n\t\t\tend\r\n\r\n\t\t\t// TDP port A\r\n\t\t\talways @(posedge clka)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_A; i=i+1) begin\r\n\t\t\t\t\tif (upper_sel_a || lower_sel_a || (CAS == \"NONE\")) begin\r\n\t\t\t\t\t\tif (ena && wea && A_BM[i])\r\n\t\t\t\t\t\t\tmemory[addra+i] <= A_DI[i];\r\n\t\t\t\t\tend\r\n\r\n\t\t\t\t\tif (A_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (ena && !wea) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= ((A_ADDR[0] == 1) ? (memory[addra+i]) : (A_CI));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= memory[addra+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (A_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (ena) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tif (A_ADDR[0] == 1) begin\r\n\t\t\t\t\t\t\t\t\tA_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));\r\n\t\t\t\t\t\t\t\tend else begin\r\n\t\t\t\t\t\t\t\t\tA_DO_out[i] <= A_CI;\r\n\t\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tA_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP port B\r\n\t\t\talways @(posedge clkb)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < WIDTH_MODE_B; i=i+1) begin\r\n\t\t\t\t\tif (upper_sel_b || lower_sel_b || (CAS == \"NONE\")) begin\r\n\t\t\t\t\t\tif (enb && web && B_BM[i])\r\n\t\t\t\t\t\t\tmemory[addrb+i] <= B_DI[i];\r\n\t\t\t\t\tend\r\n\r\n\t\t\t\t\tif (B_WR_MODE == \"NO_CHANGE\") begin\r\n\t\t\t\t\t\tif (enb && !web) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= ((B_ADDR[0] == 1) ? (memory[addrb+i]) : (B_CI));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= memory[addrb+i];\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse if (B_WR_MODE == \"WRITE_THROUGH\") begin\r\n\t\t\t\t\t\tif (enb) begin\r\n\t\t\t\t\t\t\tif (CAS == \"UPPER\") begin\r\n\t\t\t\t\t\t\t\tif (B_ADDR[0] == 1) begin\r\n\t\t\t\t\t\t\t\t\tB_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));\r\n\t\t\t\t\t\t\t\tend else begin\r\n\t\t\t\t\t\t\t\t\tB_DO_out[i] <= B_CI;\r\n\t\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\t\telse if (CAS == \"NONE\") begin\r\n\t\t\t\t\t\t\t\tB_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));\r\n\t\t\t\t\t\t\tend\r\n\t\t\t\t\t\tend\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge clka) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge clkb) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\nmodule CC_FIFO_40K (\r\n\toutput A_ECC_1B_ERR,\r\n\toutput B_ECC_1B_ERR,\r\n\toutput A_ECC_2B_ERR,\r\n\toutput B_ECC_2B_ERR,\r\n\t// FIFO pop port\r\n\toutput [39:0] A_DO,\r\n\toutput [39:0] B_DO,\r\n\t(* clkbuf_sink *)\r\n\tinput  A_CLK,\r\n\tinput  A_EN,\r\n\t// FIFO push port\r\n\tinput  [39:0] A_DI,\r\n\tinput  [39:0] B_DI,\r\n\tinput  [39:0] A_BM,\r\n\tinput  [39:0] B_BM,\r\n\t(* clkbuf_sink *)\r\n\tinput  B_CLK,\r\n\tinput  B_EN,\r\n\tinput  B_WE,\r\n\t// FIFO control\r\n\tinput  F_RST_N,\r\n\tinput  [14:0] F_ALMOST_FULL_OFFSET,\r\n\tinput  [14:0] F_ALMOST_EMPTY_OFFSET,\r\n\t// FIFO status signals\r\n\toutput F_FULL,\r\n\toutput F_EMPTY,\r\n\toutput F_ALMOST_FULL,\r\n\toutput F_ALMOST_EMPTY,\r\n\toutput F_RD_ERROR,\r\n\toutput F_WR_ERROR,\r\n\toutput [15:0] F_RD_PTR,\r\n\toutput [15:0] F_WR_PTR\r\n);\r\n\t// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r\n\tparameter LOC = \"UNPLACED\";\r\n\r\n\t// Offset configuration\r\n\tparameter DYN_STAT_SELECT = 1'b0;\r\n\tparameter [14:0] ALMOST_FULL_OFFSET = 15'b0;\r\n\tparameter [14:0] ALMOST_EMPTY_OFFSET = 15'b0;\r\n\r\n\t// Port Widths\r\n\tparameter A_WIDTH = 0;\r\n\tparameter B_WIDTH = 0;\r\n\r\n\t// RAM and Write Modes\r\n\tparameter RAM_MODE = \"TDP\"; // \"TDP\" or \"SDP\"\r\n\tparameter FIFO_MODE = \"SYNC\"; // \"ASYNC\" or \"SYNC\"\r\n\r\n\t// Inverting Control Pins\r\n\tparameter A_CLK_INV = 1'b0;\r\n\tparameter B_CLK_INV = 1'b0;\r\n\tparameter A_EN_INV = 1'b0;\r\n\tparameter B_EN_INV = 1'b0;\r\n\tparameter A_WE_INV = 1'b0;\r\n\tparameter B_WE_INV = 1'b0;\r\n\r\n\t// Output Register\r\n\tparameter A_DO_REG = 1'b0;\r\n\tparameter B_DO_REG = 1'b0;\r\n\r\n\t// Error Checking and Correction\r\n\tparameter A_ECC_EN  = 1'b0;\r\n\tparameter B_ECC_EN  = 1'b0;\r\n\r\n\tinteger i, k;\r\n\r\n\t// 512 x 80 bit\r\n\treg [40959:0] memory = 40960'b0;\r\n\r\n\treg [15:0] counter_max;\r\n\treg [15:0] sram_depth;\r\n\tlocalparam tp = (A_WIDTH ==  1) ? 15 :\r\n\t\t\t\t\t(A_WIDTH ==  2) ? 14 :\r\n\t\t\t\t\t(A_WIDTH ==  5) ? 13 :\r\n\t\t\t\t\t(A_WIDTH == 10) ? 12 :\r\n\t\t\t\t\t(A_WIDTH == 20) ? 11 :\r\n\t\t\t\t\t(A_WIDTH == 40) ? 10 : 9;\r\n\r\n\tinitial begin\r\n\t\t// Check parameters\r\n\t\tif ((RAM_MODE != \"SDP\") && (RAM_MODE != \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Illegal RAM MODE %d.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((FIFO_MODE != \"ASYNC\") && (FIFO_MODE != \"SYNC\")) begin\r\n\t\t\t$display(\"ERROR: Illegal FIFO MODE %d.\", FIFO_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && (DYN_STAT_SELECT == 1)) begin\r\n\t\t\t$display(\"ERROR: Dynamic offset configuration is not supported in %s mode.\", RAM_MODE);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((RAM_MODE == \"SDP\") && ((A_WIDTH != 80) || (B_WIDTH != 80))) begin\r\n\t\t\t$display(\"ERROR: SDP is ony supported in 80 bit mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WIDTH == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port A width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((B_WIDTH == 80) && (RAM_MODE == \"TDP\")) begin\r\n\t\t\t$display(\"ERROR: Port B width of 80 bits is only supported in SDP mode.\");\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((A_WIDTH != 80) && (A_WIDTH != 40) && (A_WIDTH != 20) && (A_WIDTH != 10) &&\r\n\t\t\t(A_WIDTH != 5)  && (A_WIDTH != 2)  && (A_WIDTH != 1) && (A_WIDTH != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port A width configuration %d.\", RAM_MODE, A_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif ((B_WIDTH != 80) && (B_WIDTH != 40) && (B_WIDTH != 20) && (B_WIDTH != 10) &&\r\n\t\t\t(B_WIDTH != 5)  && (B_WIDTH != 2)  && (B_WIDTH != 1) && (B_WIDTH != 0)) begin\r\n\t\t\t$display(\"ERROR: Illegal %s Port B width configuration %d.\", RAM_MODE, B_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\tif (A_WIDTH != B_WIDTH) begin\r\n\t\t\t$display(\"ERROR: The values of A_WIDTH and B_WIDTH must be equal.\");\r\n\t\tend\r\n\t\tif ((A_ECC_EN == 1'b1) && (RAM_MODE != \"SDP\") && (A_WIDTH != 40)) begin\r\n\t\t\t$display(\"ERROR: Illegal ECC Port A configuration. ECC mode requires TDP >=40 bit or SDP 80 bit, but is %s %d.\", RAM_MODE, A_WIDTH);\r\n\t\t\t$finish();\r\n\t\tend\r\n\t\t// Set local parameters\r\n\t\tif (A_WIDTH == 1) begin // A_WIDTH=B_WIDTH\r\n\t\t\tcounter_max = 2 * 32*1024 - 1;\r\n\t\t\tsram_depth  =     32*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 2) begin\r\n\t\t\tcounter_max = 2 * 16*1024 - 1;\r\n\t\t\tsram_depth  =     16*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 5) begin\r\n\t\t\tcounter_max = 2 * 8*1024 - 1;\r\n\t\t\tsram_depth  =     8*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 10) begin\r\n\t\t\tcounter_max = 2 * 4*1024 - 1;\r\n\t\t\tsram_depth  =     4*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 20) begin\r\n\t\t\tcounter_max = 2 * 2*1024 - 1;\r\n\t\t\tsram_depth  =     2*1024;\r\n\t\tend\r\n\t\telse if (A_WIDTH == 40) begin\r\n\t\t\tcounter_max = 2 * 1*1024 - 1;\r\n\t\t\tsram_depth  =     1*1024;\r\n\t\tend\r\n\t\telse begin // 80 bit SDP\r\n\t\t\tcounter_max = 2 * 512 - 1;\r\n\t\t\tsram_depth  =     512;\r\n\t\tend\r\n\tend\r\n\r\n\t// Internal signals\r\n\twire fifo_rdclk = A_CLK ^ A_CLK_INV;\r\n\twire fifo_wrclk = (FIFO_MODE == \"ASYNC\") ? (B_CLK ^ B_CLK_INV) : (A_CLK ^ A_CLK_INV);\r\n\twire [15:0] almost_full_offset  = DYN_STAT_SELECT ? F_ALMOST_FULL_OFFSET  : ALMOST_FULL_OFFSET;\r\n\twire [15:0] almost_empty_offset = DYN_STAT_SELECT ? F_ALMOST_EMPTY_OFFSET : ALMOST_EMPTY_OFFSET;\r\n\treg  [39:0] A_DO_out = 0, A_DO_reg = 0;\r\n\treg  [39:0] B_DO_out = 0, B_DO_reg = 0;\r\n\r\n\t// Status signals\r\n\treg fifo_full;\r\n\treg fifo_empty;\r\n\treg fifo_almost_full;\r\n\treg fifo_almost_empty;\r\n\tassign F_FULL         = fifo_full;\r\n\tassign F_EMPTY        = fifo_empty;\r\n\tassign F_ALMOST_FULL  = fifo_almost_full;\r\n\tassign F_ALMOST_EMPTY = fifo_almost_empty;\r\n\tassign F_WR_ERROR     = (F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));\r\n\tassign F_RD_ERROR     = (F_EMPTY && (A_EN ^ A_EN_INV));\r\n\twire ram_we = (~F_FULL  && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));\r\n\twire ram_en = (~F_EMPTY && (A_EN ^ A_EN_INV));\r\n\r\n\t// Reset synchronizers\r\n\treg  [1:0] aclk_reset_q, bclk_reset_q;\r\n\twire fifo_sync_rstn    = aclk_reset_q;\r\n\twire fifo_async_wrrstn = bclk_reset_q;\r\n\twire fifo_async_rdrstn = aclk_reset_q;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\taclk_reset_q <= 2'b0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\taclk_reset_q[1] <= aclk_reset_q[0];\r\n\t\t\taclk_reset_q[0] <= 1'b1;\r\n\t\tend\r\n\tend\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\tbclk_reset_q <= 2'b0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tbclk_reset_q[1] <= bclk_reset_q[0];\r\n\t\t\tbclk_reset_q[0] <= 1'b1;\r\n\t\tend\r\n\tend\r\n\r\n\t// Push/pop pointers\r\n\treg  [15:0] rd_pointer, rd_pointer_int;\r\n\treg  [15:0] wr_pointer, wr_pointer_int;\r\n\treg  [15:0] rd_pointer_cmp, wr_pointer_cmp;\r\n\twire [15:0] rd_pointer_nxt;\r\n\twire [15:0] wr_pointer_nxt;\r\n\treg  [15:0] fifo_rdaddr, rdaddr;\r\n\treg  [15:0] fifo_wraddr, wraddr;\r\n\tassign F_RD_PTR = fifo_rdaddr;\r\n\tassign F_WR_PTR = fifo_wraddr;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\trd_pointer <= 0;\r\n\t\t\trd_pointer_int <= 0;\r\n\t\tend\r\n\t\telse if (ram_en) begin\r\n\t\t\trd_pointer <= rd_pointer_nxt;\r\n\t\t\trd_pointer_int <= rd_pointer_nxt[15:1] ^ rd_pointer_nxt[14:0];\r\n\t\tend\r\n\tend\r\n\r\n\tassign rd_pointer_nxt = (rd_pointer == counter_max) ? (0) : (rd_pointer + 1'b1);\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\twr_pointer <= 0;\r\n\t\t\twr_pointer_int <= 0;\r\n\t\tend\r\n\t\telse if (ram_we) begin\r\n\t\t\twr_pointer <= wr_pointer_nxt;\r\n\t\t\twr_pointer_int <= wr_pointer_nxt[15:1] ^ wr_pointer_nxt[14:0];\r\n\t\tend\r\n\tend\r\n\r\n\tassign wr_pointer_nxt = (wr_pointer == counter_max) ? (0) : (wr_pointer + 1'b1);\r\n\r\n\t// Address synchronizers\r\n\treg [15:0] rd_pointer_sync, wr_pointer_sync;\r\n\treg [15:0] rd_pointer_sync_0, rd_pointer_sync_1;\r\n\treg [15:0] wr_pointer_sync_0, wr_pointer_sync_1;\r\n\r\n\talways @(posedge fifo_rdclk or negedge F_RST_N)\r\n\tbegin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\twr_pointer_sync_0 <= 0;\r\n\t\t\twr_pointer_sync_1 <= 0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\twr_pointer_sync_0 <= wraddr;\r\n\t\t\twr_pointer_sync_1 <= wr_pointer_sync_0;\r\n\t\tend\r\n\t end\r\n\r\n\talways @(posedge fifo_wrclk or negedge F_RST_N)\r\n\t begin\r\n\t\tif (F_RST_N == 1'b0) begin\r\n\t\t\trd_pointer_sync_0 <= 0;\r\n\t\t\trd_pointer_sync_1 <= 0;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\trd_pointer_sync_0 <= rdaddr;\r\n\t\t\trd_pointer_sync_1 <= rd_pointer_sync_0;\r\n\t\tend\r\n\t end\r\n\r\n\talways @(*) begin\r\n\t\tfifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}};\r\n\t\tfifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}};\r\n\r\n\t\trdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]};\r\n\t\twraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]};\r\n\r\n\t\tif (FIFO_MODE == \"ASYNC\")\r\n\t\t\tfifo_full = (wraddr[tp-2:0] == rd_pointer_sync_1[tp-2:0] ) && (wraddr[tp] != rd_pointer_sync_1[tp] ) && ( wraddr[tp-1] != rd_pointer_sync_1[tp-1] );\r\n\t\telse\r\n\t\t\tfifo_full = (wr_pointer[tp-1:0] == rd_pointer[tp-1:0]) && (wr_pointer[tp] ^ rd_pointer[tp]);\r\n\r\n\t\tif (FIFO_MODE == \"ASYNC\")\r\n\t\t\tfifo_empty = (wr_pointer_sync_1[tp:0] == rdaddr[tp:0]);\r\n\t\telse\r\n\t\t\tfifo_empty = (wr_pointer[tp:0] == rd_pointer[tp:0]);\r\n\r\n\t\trd_pointer_cmp = (FIFO_MODE == \"ASYNC\") ? rd_pointer_sync : rd_pointer;\r\n\t\tif (wr_pointer[tp] == rd_pointer_cmp[tp])\r\n\t\t\tfifo_almost_full = ((wr_pointer[tp-1:0] - rd_pointer_cmp[tp-1:0]) >= (sram_depth - almost_full_offset));\r\n\t\telse\r\n\t\t\tfifo_almost_full = ((rd_pointer_cmp[tp-1:0] - wr_pointer[tp-1:0]) <= almost_full_offset);\r\n\r\n\t\twr_pointer_cmp = (FIFO_MODE == \"ASYNC\") ? wr_pointer_sync : wr_pointer;\r\n\t\tif (wr_pointer_cmp[tp] == rd_pointer[tp])\r\n\t\t\tfifo_almost_empty = ((wr_pointer_cmp[tp-1:0] - rd_pointer[tp-1:0]) <= almost_empty_offset);\r\n\t\telse\r\n\t\t\tfifo_almost_empty = ((rd_pointer[tp-1:0] - wr_pointer_cmp[tp-1:0]) >= (sram_depth - almost_empty_offset));\r\n\tend\r\n\r\n\tgenerate\r\n\t\talways @(*) begin\r\n\t\t\twr_pointer_sync = 0;\r\n\t\t\trd_pointer_sync = 0;\r\n\t\t\tfor (i=tp; i >= 0; i=i-1) begin\r\n\t\t\t\tif (i == tp) begin\r\n\t\t\t\t\twr_pointer_sync[i] = wr_pointer_sync_1[i];\r\n\t\t\t\t\trd_pointer_sync[i] = rd_pointer_sync_1[i];\r\n\t\t\t\tend\r\n\t\t\t\telse begin\r\n\t\t\t\t\twr_pointer_sync[i] = wr_pointer_sync_1[i] ^ wr_pointer_sync[i+1];\r\n\t\t\t\t\trd_pointer_sync[i] = rd_pointer_sync_1[i] ^ rd_pointer_sync[i+1];\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\tif (RAM_MODE == \"SDP\") begin\r\n\t\t\t// SDP push ports A+B\r\n\t\t\talways @(posedge fifo_wrclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < A_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ram_we && A_BM[k]) memory[fifo_wraddr+k] <= A_DI[k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ram_we && B_BM[k-40]) memory[fifo_wraddr+k] <= B_DI[k-40];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// SDP pop ports A+B\r\n\t\t\talways @(posedge fifo_rdclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (k=0; k < B_WIDTH; k=k+1) begin\r\n\t\t\t\t\tif (k < 40) begin\r\n\t\t\t\t\t\tif (ram_en) A_DO_out[k] <= memory[fifo_rdaddr+k];\r\n\t\t\t\t\tend\r\n\t\t\t\t\telse begin // use both ports\r\n\t\t\t\t\t\tif (ram_en) B_DO_out[k-40] <= memory[fifo_rdaddr+k];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\t\telse if (RAM_MODE == \"TDP\") begin\r\n\t\t\t// TDP pop port A\r\n\t\t\talways @(posedge fifo_rdclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < A_WIDTH; i=i+1) begin\r\n\t\t\t\t\tif (ram_en) begin\r\n\t\t\t\t\t\tA_DO_out[i] <= memory[fifo_rdaddr+i];\r\n\t\t\t\t\tend\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\t\t// TDP push port B\r\n\t\t\talways @(posedge fifo_wrclk)\r\n\t\t\tbegin\r\n\t\t\t\tfor (i=0; i < B_WIDTH; i=i+1) begin\r\n\t\t\t\t\tif (ram_we && B_BM[i])\r\n\t\t\t\t\t\tmemory[fifo_wraddr+i] <= B_DI[i];\r\n\t\t\t\tend\r\n\t\t\tend\r\n\t\tend\r\n\tendgenerate\r\n\r\n\t// Optional output register\r\n\tgenerate\r\n\t\tif (A_DO_REG) begin\r\n\t\t\talways @(posedge fifo_rdclk) begin\r\n\t\t\t\tA_DO_reg <= A_DO_out;\r\n\t\t\tend\r\n\t\t\tassign A_DO = A_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign A_DO = A_DO_out;\r\n\t\tend\r\n\t\tif (B_DO_REG) begin\r\n\t\t\talways @(posedge fifo_rdclk) begin\r\n\t\t\t\tB_DO_reg <= B_DO_out;\r\n\t\t\tend\r\n\t\t\tassign B_DO = B_DO_reg;\r\n\t\tend\r\n\t\telse begin\r\n\t\t\tassign B_DO = B_DO_out;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n\r\n// Models of the LUT2 tree primitives\r\nmodule CC_L2T4(\r\n\toutput O,\r\n\tinput I0, I1, I2, I3\r\n);\r\n\tparameter [3:0] INIT_L00 = 4'b0000;\r\n\tparameter [3:0] INIT_L01 = 4'b0000;\r\n\tparameter [3:0] INIT_L10 = 4'b0000;\r\n\r\n\twire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0];\r\n\twire l00 = I0 ? l00_s1[1] : l00_s1[0];\r\n\r\n\twire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0];\r\n\twire l01 = I2 ? l01_s1[1] : l01_s1[0];\r\n\r\n\twire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0];\r\n\tassign O = l00 ? l10_s1[1] : l10_s1[0];\r\n\r\nendmodule\r\n\r\n\r\nmodule CC_L2T5(\r\n\toutput O,\r\n\tinput I0, I1, I2, I3, I4\r\n);\r\n\tparameter [3:0] INIT_L02 = 4'b0000;\r\n\tparameter [3:0] INIT_L03 = 4'b0000;\r\n\tparameter [3:0] INIT_L11 = 4'b0000;\r\n\tparameter [3:0] INIT_L20 = 4'b0000;\r\n\r\n\twire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0];\r\n\twire l02 = I0 ? l02_s1[1] : l02_s1[0];\r\n\r\n\twire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0];\r\n\twire l03 = I2 ? l03_s1[1] : l03_s1[0];\r\n\r\n\twire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0];\r\n\twire l11 = l02 ? l11_s1[1] : l11_s1[0];\r\n\r\n\twire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0];\r\n\tassign O = I4 ? l20_s1[1] : l20_s1[0];\r\n\r\nendmodule\r\n",
             "inv_map.v": "// Any inverters not folded into LUTs are mapped to a LUT of their own\nmodule \\$__CC_NOT (input A, output Y);\n\tCC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y));\nendmodule\n",
             "lut_map.v": "/*\r\n *  yosys -- Yosys Open SYnthesis Suite\r\n *\r\n *  Copyright (C) 2021  Cologne Chip AG <support@colognechip.com>\r\n *\r\n *  Permission to use, copy, modify, and/or distribute this software for any\r\n *  purpose with or without fee is hereby granted, provided that the above\r\n *  copyright notice and this permission notice appear in all copies.\r\n *\r\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r\n *\r\n */\r\n\r\nmodule \\$lut (A, Y);\r\n\tparameter WIDTH = 0;\r\n\tparameter LUT = 0;\r\n\r\n\t(* force_downto *)\r\n\tinput [WIDTH-1:0] A;\r\n\toutput Y;\r\n\r\n\tgenerate\r\n\t\tif (WIDTH == 1) begin\r\n\t\t\tCC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));\r\n\t\tend\r\n\t\telse if (WIDTH == 2) begin\r\n\t\t\tCC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));\r\n\t\tend\r\n\t\telse if (WIDTH == 3) begin\r\n\t\t\tCC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));\r\n\t\tend\r\n\t\telse if (WIDTH == 4) begin\r\n\t\t\tCC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\r\n\t\tend\r\n\t\telse begin\r\n\t\t\twire _TECHMAP_FAIL_ = 1;\r\n\t\tend\r\n\tendgenerate\r\nendmodule\r\n",
@@ -97,10 +97,10 @@ export const filesystem = {
             "brams.txt": "ram block $__GOWIN_SP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_DP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_SDP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\tclock posedge;\n\t\tclken;\n\t}\n}\n",
             "brams_map.v": "`define DEF_FUNCS \\\n\tfunction [255:0] init_slice_x8; \\\n\t\tinput integer idx; \\\n\t\tinteger i; \\\n\t\tfor (i = 0; i < 32; i = i + 1) begin \\\n\t\t\tinit_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \\\n\t\tend \\\n\tendfunction \\\n\tfunction [287:0] init_slice_x9; \\\n\t\tinput integer idx; \\\n\t\tinit_slice_x9 = INIT[idx * 288+:288]; \\\n\tendfunction \\\n\n`define x8_width(width) (width / 9 * 8 + width % 9)\n`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}\n`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}\n`define addrbe_always(width, addr) (width < 18 ? addr :  width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})\n\n\n`define INIT(func) \\\n\t.INIT_RAM_00(func('h00)), \\\n\t.INIT_RAM_01(func('h01)), \\\n\t.INIT_RAM_02(func('h02)), \\\n\t.INIT_RAM_03(func('h03)), \\\n\t.INIT_RAM_04(func('h04)), \\\n\t.INIT_RAM_05(func('h05)), \\\n\t.INIT_RAM_06(func('h06)), \\\n\t.INIT_RAM_07(func('h07)), \\\n\t.INIT_RAM_08(func('h08)), \\\n\t.INIT_RAM_09(func('h09)), \\\n\t.INIT_RAM_0A(func('h0a)), \\\n\t.INIT_RAM_0B(func('h0b)), \\\n\t.INIT_RAM_0C(func('h0c)), \\\n\t.INIT_RAM_0D(func('h0d)), \\\n\t.INIT_RAM_0E(func('h0e)), \\\n\t.INIT_RAM_0F(func('h0f)), \\\n\t.INIT_RAM_10(func('h10)), \\\n\t.INIT_RAM_11(func('h11)), \\\n\t.INIT_RAM_12(func('h12)), \\\n\t.INIT_RAM_13(func('h13)), \\\n\t.INIT_RAM_14(func('h14)), \\\n\t.INIT_RAM_15(func('h15)), \\\n\t.INIT_RAM_16(func('h16)), \\\n\t.INIT_RAM_17(func('h17)), \\\n\t.INIT_RAM_18(func('h18)), \\\n\t.INIT_RAM_19(func('h19)), \\\n\t.INIT_RAM_1A(func('h1a)), \\\n\t.INIT_RAM_1B(func('h1b)), \\\n\t.INIT_RAM_1C(func('h1c)), \\\n\t.INIT_RAM_1D(func('h1d)), \\\n\t.INIT_RAM_1E(func('h1e)), \\\n\t.INIT_RAM_1F(func('h1f)), \\\n\t.INIT_RAM_20(func('h20)), \\\n\t.INIT_RAM_21(func('h21)), \\\n\t.INIT_RAM_22(func('h22)), \\\n\t.INIT_RAM_23(func('h23)), \\\n\t.INIT_RAM_24(func('h24)), \\\n\t.INIT_RAM_25(func('h25)), \\\n\t.INIT_RAM_26(func('h26)), \\\n\t.INIT_RAM_27(func('h27)), \\\n\t.INIT_RAM_28(func('h28)), \\\n\t.INIT_RAM_29(func('h29)), \\\n\t.INIT_RAM_2A(func('h2a)), \\\n\t.INIT_RAM_2B(func('h2b)), \\\n\t.INIT_RAM_2C(func('h2c)), \\\n\t.INIT_RAM_2D(func('h2d)), \\\n\t.INIT_RAM_2E(func('h2e)), \\\n\t.INIT_RAM_2F(func('h2f)), \\\n\t.INIT_RAM_30(func('h30)), \\\n\t.INIT_RAM_31(func('h31)), \\\n\t.INIT_RAM_32(func('h32)), \\\n\t.INIT_RAM_33(func('h33)), \\\n\t.INIT_RAM_34(func('h34)), \\\n\t.INIT_RAM_35(func('h35)), \\\n\t.INIT_RAM_36(func('h36)), \\\n\t.INIT_RAM_37(func('h37)), \\\n\t.INIT_RAM_38(func('h38)), \\\n\t.INIT_RAM_39(func('h39)), \\\n\t.INIT_RAM_3A(func('h3a)), \\\n\t.INIT_RAM_3B(func('h3b)), \\\n\t.INIT_RAM_3C(func('h3c)), \\\n\t.INIT_RAM_3D(func('h3d)), \\\n\t.INIT_RAM_3E(func('h3e)), \\\n\t.INIT_RAM_3F(func('h3f)),\n\nmodule $__GOWIN_SP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 36;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DO);\n\n\tSP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_A_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_A_RD_DATA = DO;\n\n\tSPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(PORT_A_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_DP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;\n\n`DEF_FUNCS\n\nwire RSTA = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire RSTB = OPTION_RESET_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST;\nwire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\nwire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin\n\n\twire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);\n\twire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);\n\twire [15:0] DOA;\n\twire [15:0] DOB;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DOA);\n\tassign PORT_B_RD_DATA = `x8_rd_data(DOB);\n\n\tDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend else begin\n\n\twire [17:0] DIA = PORT_A_WR_DATA;\n\twire [17:0] DIB = PORT_B_WR_DATA;\n\twire [17:0] DOA;\n\twire [17:0] DOB;\n\n\tassign PORT_A_RD_DATA = DOA;\n\tassign PORT_B_RD_DATA = DOB;\n\n\tDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(PORT_A_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_B_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 18;\nparameter PORT_W_WIDTH = 18;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput PORT_W_WR_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST;\nwire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);\nwire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;\n\ngenerate\n\nif (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_R_RD_DATA = `x8_rd_data(DO);\n\n\tSDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_W_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_R_RD_DATA = DO;\n\n\tSDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(PORT_W_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_R_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n",
             "cells_map.v": "`default_nettype none\n//All DFF* have INIT, but the hardware is always initialised to the reset\n//value regardless. The parameter is ignored.\n\n// DFFN\t\t\t D Flip-Flop with Negative-Edge Clock\nmodule\t\\$_DFF_N_ (input D, C, output Q);\n\tDFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFF\t\t\t D Flip-Flop\nmodule\t\\$_DFF_P_ (input D, C, output Q);\n\tDFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFE\t\t\t D Flip-Flop with Clock Enable\nmodule\t\\$_DFFE_PP_ (input D, C, E, output Q);\n\tDFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNE\t\t D Flip-Flop with Negative-Edge Clock and Clock Enable\nmodule\t\\$_DFFE_NP_ (input D, C, E, output Q);\n\tDFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFR\t\t\t D Flip-Flop with Synchronous Reset\nmodule\t\\$_SDFF_PP0_ (input D, C, R, output Q);\n\tDFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNR\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Reset\nmodule\t\\$_SDFF_NP0_ (input D, C, R, output Q);\n\tDFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFRE\t\t D Flip-Flop with Clock Enable and Synchronous Reset\nmodule\t\\$_SDFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNRE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset\nmodule\t\\$_SDFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFS\t\t\t D Flip-Flop with Synchronous Set\nmodule\t\\$_SDFF_PP1_ (input D, C, R, output Q);\n\tDFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNS\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Set\nmodule\t\\$_SDFF_NP1_ (input D, C, R, output Q);\n\tDFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFSE\t\t D Flip-Flop with Clock Enable and Synchronous Set\nmodule\t\\$_SDFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNSE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set\nmodule\t\\$_SDFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFP\t\t\t D Flip-Flop with Asynchronous Preset\nmodule\t\\$_DFF_PP1_ (input D, C, R, output Q);\n\tDFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNP\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Preset\nmodule\t\\$_DFF_NP1_ (input D, C, R, output Q);\n\tDFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFC\t\t\t D Flip-Flop with Asynchronous Clear\nmodule\t\\$_DFF_PP0_ (input D, C, R, output Q);\n\tDFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNC\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Clear\nmodule\t\\$_DFF_NP0_ (input D, C, R, output Q);\n\tDFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFPE\t\t D Flip-Flop with Clock Enable and Asynchronous Preset\nmodule\t\\$_DFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNPE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset\nmodule\t\\$_DFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFCE\t\t D Flip-Flop with Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNCE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\t\tLUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]));\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tLUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tLUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tLUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\n\t\tend else\n\t\tif (WIDTH == 5) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));\n\t\t\tMUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 6) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));\n\t\t\tMUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 7) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));\n\t\t\tMUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 8) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));\n\t\t\tMUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));\n\t\tend else begin\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\tend\n\tendgenerate\nendmodule\n",
-            "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n  assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n  MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n  MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n  MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n  MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (CE)\n      Q <= D;\n  end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else\n      Q <= D;\t\n  end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n  always @(posedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else\n      Q <= D;\n  end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n  always @(posedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n  specify\n    (negedge CLK => (Q : D)) = (480, 660);\n    $setup(D, negedge CLK, 576);\n  endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (CE)\n      Q <= D;\n  end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n  \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else\n      Q <= D;\t\n  end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n  always @(negedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else\n      Q <= D;\n  end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n  \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n  always @(negedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n  input I, OEN;\n  output O;\n  assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n  input I,OEN;\n  output O;\n  inout IO;\n  assign IO = OEN ? 1'bz : I;\n  assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n  input I;\n  output O;\n  output OB;\n  assign O = I;\n  assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n  input I;\n  output O;\n  output OB;\n  assign O = I;\n  assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET)  ;\n    parameter GSREN = \"\";\n    parameter LSREN = \"\";\n    parameter HWL = \"\";\n    parameter TCLK_SOURCE = \"\";\n    parameter TXCLK_POL = \"\";\n\n    input D0, D1, D2, D3;\n    input TX0, TX1;\n    input PCLK, FCLK, TCLK, RESET;\n    output  Q0,  Q1;\n\n    parameter ID = \"\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR,\nRADDR, CALIB, PCLK, FCLK, ICLK, RESET)  ;\nparameter GSREN = \"\";\nparameter LSREN = \"\";\n\ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput CALIB, RESET;\n\noutput Q0,Q1,Q2,Q3;\n\nparameter ID = \"\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG,\nWFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR,\nHOLD, RCLKSEL, PCLK, FCLK, RESET) ;\n    input DQSIN,PCLK,FCLK,RESET;\n    input [3:0] READ;\n    input [2:0] RCLKSEL;\n    input [7:0] DLLSTEP;\n    input [7:0] WSTEP;\n    input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\n\n    output DQSR90, DQSW0, DQSW270;\n    output [2:0] RPOINT, WPOINT;\n    output RVALID,RBURST, RFLAG, WFLAG;\n\n    parameter FIFO_MODE_SEL = \"\";\n    parameter RD_PNTR = \"\";\n    parameter DQS_MODE = \"\";\n    parameter HWL = \"\";\n    parameter GSREN = \"\";\n    parameter ID = \"\";\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox, keep *)\nmodule GSR (input GSRI);\nendmodule\n\n(* blackbox, keep *)\nmodule BANDGAP (input BGEN);\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0  => COUT) = (1010, 1380);\n\t(I1  => COUT) = (1021, 1505);\n\t(I3  => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = I0 & I1;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\";         // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\";    // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0;             // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\";   // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0;            // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\";    // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8;             // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";      // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1;     // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1;    // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0;      // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0;     // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\";   // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\";  // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2;         // 2~128, only even numbers\nparameter CLKOUTD_SRC =  \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\";        // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\";         // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\";    // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0;             // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\";   // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0;            // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\";    // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8;             // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";      // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1;     // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1;    // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0;      // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0;     // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\";   // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\";  // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2;         // 2~128, only even numbers\nparameter CLKOUTD_SRC =  \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\";       // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nparameter DCS_MODE = \"RISING\";\nendmodule\n\n(* blackbox *)\nmodule EMCU (\n  input          FCLK,\n  input          PORESETN,\n  input          SYSRESETN,\n  input          RTCSRCCLK,\n  output  [15:0] IOEXPOUTPUTO,\n  output  [15:0] IOEXPOUTPUTENO,\n  input   [15:0] IOEXPINPUTI,\n  output         UART0TXDO,\n  output         UART1TXDO,\n  output         UART0BAUDTICK,\n  output         UART1BAUDTICK,\n  input          UART0RXDI,\n  input          UART1RXDI,\n  output         INTMONITOR,\n  output         MTXHRESETN,\n  output  [12:0] SRAM0ADDR,\n  output   [3:0] SRAM0WREN,\n  output  [31:0] SRAM0WDATA,\n  output         SRAM0CS,\n  input   [31:0] SRAM0RDATA,\n  output         TARGFLASH0HSEL,\n  output  [28:0] TARGFLASH0HADDR,\n  output   [1:0] TARGFLASH0HTRANS,\n  output   [2:0] TARGFLASH0HSIZE,\n  output   [2:0] TARGFLASH0HBURST,\n  output         TARGFLASH0HREADYMUX,\n  input   [31:0] TARGFLASH0HRDATA,\n  input    [2:0] TARGFLASH0HRUSER,\n  input          TARGFLASH0HRESP,\n  input          TARGFLASH0EXRESP,\n  input          TARGFLASH0HREADYOUT,\n  output         TARGEXP0HSEL,\n  output  [31:0] TARGEXP0HADDR,\n  output   [1:0] TARGEXP0HTRANS,\n  output         TARGEXP0HWRITE,\n  output   [2:0] TARGEXP0HSIZE,\n  output   [2:0] TARGEXP0HBURST,\n  output   [3:0] TARGEXP0HPROT,\n  output   [1:0] TARGEXP0MEMATTR,\n  output         TARGEXP0EXREQ,\n  output   [3:0] TARGEXP0HMASTER,\n  output  [31:0] TARGEXP0HWDATA,\n  output         TARGEXP0HMASTLOCK,\n  output         TARGEXP0HREADYMUX,\n  output         TARGEXP0HAUSER,\n  output   [3:0] TARGEXP0HWUSER,\n  input   [31:0] TARGEXP0HRDATA,\n  input          TARGEXP0HREADYOUT,\n  input          TARGEXP0HRESP,\n  input          TARGEXP0EXRESP,\n  input    [2:0] TARGEXP0HRUSER,\n  output  [31:0] INITEXP0HRDATA,\n  output         INITEXP0HREADY,\n  output         INITEXP0HRESP,\n  output         INITEXP0EXRESP,\n  output   [2:0] INITEXP0HRUSER,\n  input          INITEXP0HSEL,\n  input   [31:0] INITEXP0HADDR,\n  input    [1:0] INITEXP0HTRANS,\n  input          INITEXP0HWRITE,\n  input    [2:0] INITEXP0HSIZE,\n  input    [2:0] INITEXP0HBURST,\n  input    [3:0] INITEXP0HPROT,\n  input    [1:0] INITEXP0MEMATTR,\n  input          INITEXP0EXREQ,\n  input    [3:0] INITEXP0HMASTER,\n  input   [31:0] INITEXP0HWDATA,\n  input          INITEXP0HMASTLOCK,\n  input          INITEXP0HAUSER,\n  input    [3:0] INITEXP0HWUSER,\n  output   [3:0] APBTARGEXP2PSTRB,\n  output   [2:0] APBTARGEXP2PPROT,\n  output         APBTARGEXP2PSEL,\n  output         APBTARGEXP2PENABLE,\n  output  [11:0] APBTARGEXP2PADDR,\n  output         APBTARGEXP2PWRITE,\n  output  [31:0] APBTARGEXP2PWDATA,\n  input   [31:0] APBTARGEXP2PRDATA,\n  input          APBTARGEXP2PREADY,\n  input          APBTARGEXP2PSLVERR,\n  input    [3:0] MTXREMAP,\n  output         DAPTDO,\n  output         DAPJTAGNSW,\n  output         DAPNTDOEN,\n  input          DAPSWDITMS,\n  input          DAPTDI,\n  input          DAPNTRST,\n  input          DAPSWCLKTCK,\n  output   [3:0] TPIUTRACEDATA,\n  output         TPIUTRACECLK,\n  input    [4:0] GPINT,\n  input          FLASHERR,\n  input          FLASHINT\n\n );\nendmodule\n\n\n",
-            "cells_xtra_gw1n.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput  I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput  [17:0] A;\ninput  [17:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput  [8:0] A;\ninput  [8:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput  [8:0] A,SIA;\ninput  [8:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput  [17:0] A,SIA;\ninput  [17:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput  [35:0] A;\ninput  [35:0] B;\ninput  ASIGN,BSIGN;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput  [17:0] A;\ninput  [35:0] B;\ninput  [53:0] C;\ninput  ASIGN,BSIGN,ACCLOAD;\ninput  CE;\ninput  CLK;\ninput  RESET;\ninput  [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\";  \nparameter CLKOUTP_BYPASS = \"false\";   \nparameter CLKOUTD_BYPASS = \"false\";  \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC =  \"CLKOUT\";  \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput  I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput  I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput  I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput  I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput  I, IB, IL, MODESEL;\nendmodule\n\nmodule ELVDS_IBUF_MIPI (...);\noutput OH, OL;\ninput  I, IB;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput  I, MODESEL;\nendmodule\n\nmodule TLVDS_OEN_BK (...);\ninput OEN;\nparameter OEN_BANK = \"0\"; \nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n\t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\t\t  \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n   \t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n\t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\t\t  \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n\t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\t\t  \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN =  \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n\t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\t\t  \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O;          \noutput DESKEW_ERROR;      \ninout  CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0,  HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN,  D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK;         \ninput HS_8BIT_MODE;       \ninput RX_CLK_1X;          \ninput RX_INVERT;          \ninput LALIGN_EN;          \ninput WALIGN_BY;          \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN;       \ninput HSRX_STOP;          \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON;              \ninput RESET;              \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH;   \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ;         \ninput DRST_N;             \ninput ONE_BYTE0_MATCH;    \ninput WORD_LENDIAN;       \ninput [2:0] FIFO_RD_STD;  \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b0;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule PWRGRD (...);\ninput PDEN; \nendmodule\n",
-            "cells_xtra_gw2a.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput  I;\noutput O;\nendmodule\n\n\nmodule IDDR_MEM (...);\nparameter GSREN = \"false\";  \nparameter LSREN = \"true\";    \ninput D, ICLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET;\noutput  Q0,Q1;\nendmodule\n\n\nmodule ODDR_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1;\ninput TX, PCLK, TCLK, RESET;\noutput  Q0, Q1;\nendmodule\n\n\nmodule IDES4_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET,CALIB;\noutput Q0,Q1,Q2,Q3;\nendmodule\n\n\nmodule IDES8_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET,CALIB;\noutput  Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7;\nendmodule\n\n\nmodule OSER4_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \nparameter HWL = \"false\";     \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3;\ninput TX0, TX1;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule OSER8_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \nparameter HWL = \"false\";    \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3, D4, D5, D6, D7;\ninput TX0, TX1, TX2, TX3;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput  [17:0] A;\ninput  [17:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput  [8:0] A;\ninput  [8:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput  [8:0] A,SIA;\ninput  [8:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput  [17:0] A,SIA;\ninput  [17:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput  [35:0] A;\ninput  [35:0] B;\ninput  ASIGN,BSIGN;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput  [17:0] A;\ninput  [35:0] B;\ninput  [53:0] C;\ninput  ASIGN,BSIGN,ACCLOAD;\ninput  CE;\ninput  CLK;\ninput  RESET;\ninput  [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\";  \nparameter CLKOUTP_BYPASS = \"false\";   \nparameter CLKOUTD_BYPASS = \"false\";  \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC =  \"CLKOUT\";  \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW2A-18\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DQS (...);\ninput DQSIN,PCLK,FCLK,RESET;\ninput [3:0] READ;\ninput [2:0] RCLKSEL;\ninput [7:0] DLLSTEP;\ninput [7:0] WSTEP;\ninput RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\noutput DQSR90, DQSW0, DQSW270; \noutput [2:0] RPOINT, WPOINT;\noutput RVALID,RBURST, RFLAG, WFLAG;\nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IBUF_R (...);\ninput  I;\ninput RTEN;\noutput O;\nendmodule\n\nmodule IOBUF_R (...);\ninput I,OEN;\ninput RTEN;\noutput O;\ninout IO;\nendmodule\n\nmodule ELVDS_IBUF_R (...);\noutput O;\ninput I, IB;\ninput RTEN;\nendmodule\n\nmodule ELVDS_IOBUF_R (...);\noutput  O;\ninout IO, IOB;\ninput I, OEN;\ninput RTEN;\nendmodule\n\nmodule OTP (...);\ninput CSB, SCLK;\noutput DOUT;\nendmodule\n\nmodule SAMB (...);\ninput [23:0] SPIAD;\ninput LOADN_SPIAD;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN =  \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule ELVDS_IBUF_MIPI (...);\noutput OH, OL;\ninput  I, IB;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput  I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput  I, MODESEL;\nendmodule\n",
-            "cells_xtra_gw5a.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, GE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, GE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule INV (...);\ninput  I;\noutput O;\nendmodule\n\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput  I, IB;\ninput OEN, OENB;\ninput HSEN, HSREN;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput  I, IB, IL, MODESEL;\ninout IO, IOB;\ninput OEN, OENB;\nendmodule\n\nmodule ELVDS_IOBUF_R (...);\noutput  O;\ninout IO, IOB;\ninput I, OEN;\ninput RTEN;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput  I, MODESEL;\nendmodule\n\nmodule TLVDS_IBUF_ADC (...);\ninput I, IB;\ninput ADCEN;\nendmodule\n\nmodule MIPI_CPHY_IBUF (...);\noutput OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2;\ninout IO0, IOB0, IO1, IOB1, IO2, IOB2;\ninput  I0, IB0, I1, IB1, I2, IB2;\ninput OEN, OENB;\ninput HSEN;\nendmodule\n\nmodule MIPI_CPHY_OBUF (...);\noutput O0, OB0, O1, OB1, O2, OB2;\ninput  I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2;\ninout IO0, IOB0, IO1, IOB1, IO2, IOB2;\ninput OEN, OENB, MODESEL, VCOME;\nendmodule\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDP36KE (...);\nparameter ECC_WRITE_EN=\"TRUE\"; \nparameter ECC_READ_EN=\"TRUE\"; \nparameter READ_MODE = 1'b0; \nparameter BLK_SEL_A = 3'b000;\nparameter BLK_SEL_B = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_FILE = \"NONE\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [8:0] ADA, ADB;\ninput [63:0] DI;\ninput [7:0] DIP;\ninput [2:0] BLKSELA, BLKSELB;\ninput DECCI, SECCI;\noutput [63:0] DO;\noutput [7:0] DOP;\noutput DECCO, SECCO;\noutput [7:0] ECCP;\nendmodule\n\n\nmodule SDP136K (...);\ninput CLKA, CLKB;\ninput WE, RE;\ninput [10:0] ADA, ADB;\ninput [67:0] DI;\noutput [67:0] DO;\nendmodule\n\nmodule MULTADDALU12X12 (...);\nparameter A0REG_CLK = \"BYPASS\"; \nparameter A0REG_CE = \"CE0\"; \nparameter A0REG_RESET = \"RESET0\"; \nparameter A1REG_CLK = \"BYPASS\"; \nparameter A1REG_CE = \"CE0\"; \nparameter A1REG_RESET = \"RESET0\"; \nparameter B0REG_CLK = \"BYPASS\"; \nparameter B0REG_CE = \"CE0\"; \nparameter B0REG_RESET = \"RESET0\"; \nparameter B1REG_CLK = \"BYPASS\"; \nparameter B1REG_CE = \"CE0\"; \nparameter B1REG_RESET = \"RESET0\"; \nparameter ACCSEL_IREG_CLK = \"BYPASS\"; \nparameter ACCSEL_IREG_CE = \"CE0\"; \nparameter ACCSEL_IREG_RESET = \"RESET0\"; \nparameter CASISEL_IREG_CLK = \"BYPASS\"; \nparameter CASISEL_IREG_CE = \"CE0\"; \nparameter CASISEL_IREG_RESET = \"RESET0\"; \nparameter ADDSUB0_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_IREG_CE = \"CE0\"; \nparameter ADDSUB0_IREG_RESET = \"RESET0\"; \nparameter ADDSUB1_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_IREG_CE = \"CE0\"; \nparameter ADDSUB1_IREG_RESET = \"RESET0\"; \nparameter PREG0_CLK = \"BYPASS\"; \nparameter PREG0_CE = \"CE0\"; \nparameter PREG0_RESET = \"RESET0\"; \nparameter PREG1_CLK = \"BYPASS\"; \nparameter PREG1_CE = \"CE0\"; \nparameter PREG1_RESET = \"RESET0\"; \nparameter FB_PREG_EN = \"FALSE\"; \nparameter ACCSEL_PREG_CLK = \"BYPASS\"; \nparameter ACCSEL_PREG_CE = \"CE0\"; \nparameter ACCSEL_PREG_RESET = \"RESET0\"; \nparameter CASISEL_PREG_CLK = \"BYPASS\"; \nparameter CASISEL_PREG_CE = \"CE0\"; \nparameter CASISEL_PREG_RESET = \"RESET0\"; \nparameter ADDSUB0_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_PREG_CE = \"CE0\"; \nparameter ADDSUB0_PREG_RESET = \"RESET0\"; \nparameter ADDSUB1_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_PREG_CE = \"CE0\"; \nparameter ADDSUB1_PREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter PRE_LOAD = 48'h000000000000;\nparameter DYN_ADD_SUB_0 = \"FALSE\";\nparameter ADD_SUB_0 = 1'b0;\nparameter DYN_ADD_SUB_1 = \"FALSE\";\nparameter ADD_SUB_1 = 1'b0;\nparameter DYN_CASI_SEL = \"FALSE\";\nparameter CASI_SEL = 1'b0;\nparameter DYN_ACC_SEL = \"FALSE\";\nparameter ACC_SEL = 1'b0;\noutput [47:0] DOUT, CASO;\ninput  [11:0] A0, B0, A1, B1;\ninput  [47:0] CASI;\ninput  ACCSEL;\ninput  CASISEL;\ninput  [1:0] ADDSUB;\ninput  [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULTALU27X18 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter DREG_CLK = \"BYPASS\"; \nparameter DREG_CE = \"CE0\"; \nparameter DREG_RESET = \"RESET0\"; \nparameter C_IREG_CLK = \"BYPASS\"; \nparameter C_IREG_CE = \"CE0\"; \nparameter C_IREG_RESET = \"RESET0\"; \nparameter PSEL_IREG_CLK = \"BYPASS\"; \nparameter PSEL_IREG_CE = \"CE0\"; \nparameter PSEL_IREG_RESET = \"RESET0\"; \nparameter PADDSUB_IREG_CLK = \"BYPASS\"; \nparameter PADDSUB_IREG_CE = \"CE0\"; \nparameter PADDSUB_IREG_RESET = \"RESET0\"; \nparameter ADDSUB0_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_IREG_CE = \"CE0\"; \nparameter ADDSUB0_IREG_RESET = \"RESET0\"; \nparameter ADDSUB1_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_IREG_CE = \"CE0\"; \nparameter ADDSUB1_IREG_RESET = \"RESET0\"; \nparameter CSEL_IREG_CLK = \"BYPASS\"; \nparameter CSEL_IREG_CE = \"CE0\"; \nparameter CSEL_IREG_RESET = \"RESET0\"; \nparameter CASISEL_IREG_CLK = \"BYPASS\"; \nparameter CASISEL_IREG_CE = \"CE0\"; \nparameter CASISEL_IREG_RESET = \"RESET0\"; \nparameter ACCSEL_IREG_CLK = \"BYPASS\"; \nparameter ACCSEL_IREG_CE = \"CE0\"; \nparameter ACCSEL_IREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter ADDSUB0_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_PREG_CE = \"CE0\"; \nparameter ADDSUB0_PREG_RESET = \"RESET0\"; \nparameter ADDSUB1_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_PREG_CE = \"CE0\"; \nparameter ADDSUB1_PREG_RESET = \"RESET0\"; \nparameter CSEL_PREG_CLK = \"BYPASS\"; \nparameter CSEL_PREG_CE = \"CE0\"; \nparameter CSEL_PREG_RESET = \"RESET0\"; \nparameter CASISEL_PREG_CLK = \"BYPASS\"; \nparameter CASISEL_PREG_CE = \"CE0\"; \nparameter CASISEL_PREG_RESET = \"RESET0\"; \nparameter ACCSEL_PREG_CLK = \"BYPASS\"; \nparameter ACCSEL_PREG_CE = \"CE0\"; \nparameter ACCSEL_PREG_RESET = \"RESET0\"; \nparameter C_PREG_CLK = \"BYPASS\"; \nparameter C_PREG_CE = \"CE0\"; \nparameter C_PREG_RESET = \"RESET0\"; \nparameter FB_PREG_EN = \"FALSE\"; \nparameter SOA_PREG_EN = \"FALSE\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter PRE_LOAD = 48'h000000000000;\nparameter DYN_P_SEL = \"FALSE\";\nparameter P_SEL = 1'b0;\nparameter DYN_P_ADDSUB = \"FALSE\";\nparameter P_ADDSUB = 1'b0;\nparameter DYN_A_SEL = \"FALSE\";\nparameter A_SEL = 1'b0;\nparameter DYN_ADD_SUB_0 = \"FALSE\";\nparameter ADD_SUB_0 = 1'b0;\nparameter DYN_ADD_SUB_1 = \"FALSE\";\nparameter ADD_SUB_1 = 1'b0;\nparameter DYN_C_SEL = \"FALSE\";\nparameter C_SEL = 1'b1;\nparameter DYN_CASI_SEL = \"FALSE\";\nparameter CASI_SEL = 1'b0;\nparameter DYN_ACC_SEL = \"FALSE\";\nparameter ACC_SEL = 1'b0;\nparameter MULT12X12_EN = \"FALSE\";\noutput [47:0] DOUT, CASO;\noutput [26:0] SOA;\ninput  [26:0] A, SIA;\ninput  [17:0] B;\ninput  [47:0] C;\ninput  [25:0] D;\ninput  [47:0] CASI;\ninput  ACCSEL;\ninput  PSEL;\ninput  ASEL;\ninput  PADDSUB;\ninput  CSEL, CASISEL;\ninput  [1:0] ADDSUB;\ninput  [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULT12X12 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\noutput [23:0] DOUT;\ninput  [11:0] A, B;\ninput  [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULT27X36 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter DREG_CLK = \"BYPASS\"; \nparameter DREG_CE = \"CE0\"; \nparameter DREG_RESET = \"RESET0\"; \nparameter PADDSUB_IREG_CLK = \"BYPASS\"; \nparameter PADDSUB_IREG_CE = \"CE0\"; \nparameter PADDSUB_IREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter PSEL_IREG_CLK = \"BYPASS\"; \nparameter PSEL_IREG_CE = \"CE0\"; \nparameter PSEL_IREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter DYN_P_SEL = \"FALSE\";\nparameter P_SEL = 1'b0;\nparameter DYN_P_ADDSUB = \"FALSE\";\nparameter P_ADDSUB = 1'b0;\noutput [62:0] DOUT;\ninput  [26:0] A;\ninput  [35:0] B;\ninput  [25:0] D;\ninput  [1:0] CLK, CE, RESET;\ninput  PSEL;\ninput  PADDSUB;\nendmodule\n\nmodule MULTACC (...);\noutput  [23:0] DATAO, CASO;\ninput CE, CLK;\ninput [5:0] COFFIN0, COFFIN1, COFFIN2;\ninput [9:0] DATAIN0, DATAIN1;\ninput [9:0] DATAIN2;\ninput RSTN;\ninput [23:0] CASI;\nparameter COFFIN_WIDTH = 4; \nparameter DATAIN_WIDTH = 8; \nparameter IREG = 1'b0; \nparameter OREG = 1'b0; \nparameter PREG = 1'b0; \nparameter ACC_EN = \"FALSE\";  \nparameter CASI_EN = \"FALSE\"; \nparameter CASO_EN = \"FALSE\"; \nendmodule\n\nmodule IDDR_MEM (...);\ninput D, ICLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET;\noutput  Q0,Q1;\nendmodule\n\n\nmodule ODDR_MEM (...);\nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1;\ninput TX, PCLK, TCLK, RESET;\noutput  Q0, Q1;\nendmodule\n\n\nmodule IDES4_MEM (...);\ninput PCLK, D, ICLK, FCLK, RESET, CALIB;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\noutput Q0,Q1,Q2,Q3;\nendmodule\n\n\nmodule IDES8_MEM (...);\ninput PCLK, D, ICLK, FCLK, RESET, CALIB;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\noutput Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;\nendmodule\n\n\nmodule IDES14 (...);\ninput D, FCLK, PCLK, CALIB,RESET;\noutput Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13;\nendmodule\n\n\nmodule IDES32 (...);\ninput D, FCLK, PCLK, CALIB,RESET;\noutput Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31;\nendmodule\n\n\nmodule OSER4_MEM (...);\nparameter HWL = \"false\";     \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3;\ninput TX0, TX1;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule OSER8_MEM (...);\nparameter HWL = \"false\";    \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3, D4, D5, D6, D7;\ninput TX0, TX1, TX2, TX3;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DLY_EN = \"FALSE\";\nparameter ADAPT_EN = \"FALSE\";\ninput  DI;\ninput  SDTAP;\ninput  VALUE;\ninput  [7:0] DLYSTEP;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule OSIDES32 (...);\noutput [31:0] Q;\ninput D;\ninput PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;\ninput RESET;\noutput DF0, DF1;\ninput  SDTAP0, SDTAP1;\ninput  VALUE0,VALUE1;\ninput  [7:0] DLYSTEP0,DLYSTEP1;\nparameter C_STATIC_DLY_0 = 0; \nparameter DYN_DLY_EN_0 = \"FALSE\";\nparameter ADAPT_EN_0 = \"FALSE\";\nparameter C_STATIC_DLY_1 = 0; \nparameter DYN_DLY_EN_1 = \"FALSE\";\nparameter ADAPT_EN_1 = \"FALSE\";\nendmodule\n\nmodule OSIDES64 (...);\noutput [63:0] Q;\ninput D;\ninput PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;\ninput RESET;\noutput DF0, DF1, DF2, DF3;\ninput  SDTAP0, SDTAP1, SDTAP2, SDTAP3;\ninput  VALUE0, VALUE1, VALUE2, VALUE3;\ninput  [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3;\nparameter C_STATIC_DLY_0 = 0; \nparameter DYN_DLY_EN_0 = \"FALSE\";\nparameter ADAPT_EN_0 = \"FALSE\";\nparameter C_STATIC_DLY_1 = 0; \nparameter DYN_DLY_EN_1 = \"FALSE\";\nparameter ADAPT_EN_1 = \"FALSE\";\nparameter C_STATIC_DLY_2 = 0; \nparameter DYN_DLY_EN_2 = \"FALSE\";\nparameter ADAPT_EN_2 = \"FALSE\";\nparameter C_STATIC_DLY_3 = 0; \nparameter DYN_DLY_EN_3 = \"FALSE\";\nparameter ADAPT_EN_3 = \"FALSE\";\nendmodule\n\nmodule DCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule DDRDLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = \"FALSE\";\nparameter CODESCAL = \"000\";\nparameter SCAL_EN = \"TRUE\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP, CSTEP;\ninput LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nparameter DYN_DLY_EN = \"FALSE\";\nparameter ADAPT_EN = \"FALSE\";\nparameter STEP_SEL = 1'b0;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nendmodule\n\nmodule CLKDIV2 (...);\ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DHCE (...);\ninput CLKIN;\ninput CEN;\noutput CLKOUT;\nendmodule\n\nmodule OSCA (...);\nparameter  FREQ_DIV = 100; \noutput OSCOUT;\ninput OSCEN;\nendmodule\n\nmodule OSCB (...);\nparameter FREQ_MODE = \"25\"; \nparameter FREQ_DIV = 10; \nparameter DYN_TRIM_EN = \"FALSE\"; \noutput OSCOUT;\noutput OSCREF;\ninput OSCEN, FMODE;\ninput [7:0] RTRIM;\ninput [5:0] RTCTRIM; \nendmodule\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput PLLPWD;\ninput RESET_I;\ninput RESET_O;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] MDSEL;\ninput [2:0] MDSEL_FRAC;\ninput [6:0] ODSEL0;\ninput [2:0] ODSEL0_FRAC;\ninput [6:0] ODSEL1;\ninput [6:0] ODSEL2;\ninput [6:0] ODSEL3;\ninput [6:0] ODSEL4;\ninput [6:0] ODSEL5;\ninput [6:0] ODSEL6;\ninput [3:0] DT0,DT1,DT2,DT3;\ninput [5:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] LPFCAP;\ninput [2:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLK0;\ninput ENCLK1;\ninput ENCLK2;\ninput ENCLK3;\ninput ENCLK4;\ninput ENCLK5;\ninput ENCLK6;\ninput SSCPOL;\ninput SSCON;\ninput [6:0] SSCMDSEL;\ninput [2:0] SSCMDSEL_FRAC;\noutput LOCK;\noutput CLKOUT0;\noutput CLKOUT1;\noutput CLKOUT2;\noutput CLKOUT3;\noutput CLKOUT4;\noutput CLKOUT5;\noutput CLKOUT6;\noutput CLKFBOUT;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 1; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 1; \nparameter DYN_ODIV0_SEL= \"FALSE\";\nparameter ODIV0_SEL = 8; \nparameter DYN_ODIV1_SEL= \"FALSE\";\nparameter ODIV1_SEL = 8; \nparameter DYN_ODIV2_SEL= \"FALSE\";\nparameter ODIV2_SEL = 8; \nparameter DYN_ODIV3_SEL= \"FALSE\";\nparameter ODIV3_SEL = 8; \nparameter DYN_ODIV4_SEL= \"FALSE\";\nparameter ODIV4_SEL = 8; \nparameter DYN_ODIV5_SEL= \"FALSE\";\nparameter ODIV5_SEL = 8; \nparameter DYN_ODIV6_SEL= \"FALSE\";\nparameter ODIV6_SEL = 8; \nparameter DYN_MDIV_SEL= \"FALSE\";\nparameter MDIV_SEL = 8; \nparameter MDIV_FRAC_SEL = 0; \nparameter ODIV0_FRAC_SEL = 0; \nparameter CLKOUT0_EN = \"TRUE\";\nparameter CLKOUT1_EN = \"FALSE\";\nparameter CLKOUT2_EN = \"FALSE\";\nparameter CLKOUT3_EN = \"FALSE\";\nparameter CLKOUT4_EN = \"FALSE\";\nparameter CLKOUT5_EN = \"FALSE\";\nparameter CLKOUT6_EN = \"FALSE\";\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DT0_SEL = \"FALSE\"; \nparameter DYN_DT1_SEL = \"FALSE\"; \nparameter DYN_DT2_SEL = \"FALSE\"; \nparameter DYN_DT3_SEL = \"FALSE\"; \nparameter CLKOUT0_DT_DIR = 1'b1; \nparameter CLKOUT1_DT_DIR = 1'b1; \nparameter CLKOUT2_DT_DIR = 1'b1; \nparameter CLKOUT3_DT_DIR = 1'b1; \nparameter CLKOUT0_DT_STEP = 0; \nparameter CLKOUT1_DT_STEP = 0; \nparameter CLKOUT2_DT_STEP = 0; \nparameter CLKOUT3_DT_STEP = 0; \nparameter CLK0_IN_SEL = 1'b0;\nparameter CLK0_OUT_SEL = 1'b0;\nparameter CLK1_IN_SEL = 1'b0;\nparameter CLK1_OUT_SEL = 1'b0;\nparameter CLK2_IN_SEL = 1'b0;\nparameter CLK2_OUT_SEL = 1'b0;\nparameter CLK3_IN_SEL = 1'b0;\nparameter CLK3_OUT_SEL = 1'b0;\nparameter CLK4_IN_SEL = 2'b00;\nparameter CLK4_OUT_SEL = 1'b0;\nparameter CLK5_IN_SEL = 1'b0;\nparameter CLK5_OUT_SEL = 1'b0;\nparameter CLK6_IN_SEL = 1'b0;\nparameter CLK6_OUT_SEL = 1'b0;\nparameter DYN_DPA_EN = \"FALSE\";\nparameter CLKOUT0_PE_COARSE = 0;\nparameter CLKOUT0_PE_FINE = 0;\nparameter CLKOUT1_PE_COARSE = 0;\nparameter CLKOUT1_PE_FINE = 0;\nparameter CLKOUT2_PE_COARSE = 0;\nparameter CLKOUT2_PE_FINE = 0;\nparameter CLKOUT3_PE_COARSE = 0;\nparameter CLKOUT3_PE_FINE = 0;\nparameter CLKOUT4_PE_COARSE = 0;\nparameter CLKOUT4_PE_FINE = 0;\nparameter CLKOUT5_PE_COARSE = 0;\nparameter CLKOUT5_PE_FINE = 0;\nparameter CLKOUT6_PE_COARSE = 0;\nparameter CLKOUT6_PE_FINE = 0;\nparameter DYN_PE0_SEL = \"FALSE\";\nparameter DYN_PE1_SEL = \"FALSE\";\nparameter DYN_PE2_SEL = \"FALSE\";\nparameter DYN_PE3_SEL = \"FALSE\";\nparameter DYN_PE4_SEL = \"FALSE\";\nparameter DYN_PE5_SEL = \"FALSE\";\nparameter DYN_PE6_SEL = \"FALSE\";\nparameter DE0_EN = \"FALSE\";\nparameter DE1_EN = \"FALSE\";\nparameter DE2_EN = \"FALSE\";\nparameter DE3_EN = \"FALSE\";\nparameter DE4_EN = \"FALSE\";\nparameter DE5_EN = \"FALSE\";\nparameter DE6_EN = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_O_EN =  \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 6'bXXXXXX;\nparameter DYN_LPF_SEL= \"FALSE\";\nparameter LPF_RES = 3'bXXX;\nparameter LPF_CAP = 2'b00;\nparameter SSC_EN = \"FALSE\";\nendmodule\n\nmodule PLLA (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput PLLPWD;\ninput RESET_I;\ninput RESET_O;\ninput [2:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput SSCPOL;\ninput SSCON;\ninput [6:0] SSCMDSEL;\ninput [2:0] SSCMDSEL_FRAC;\ninput MDCLK;\ninput [1:0] MDOPC;\ninput MDAINC;\ninput [7:0] MDWDI;\noutput [7:0] MDRDO;\noutput LOCK;\noutput CLKOUT0;\noutput CLKOUT1;\noutput CLKOUT2;\noutput CLKOUT3;\noutput CLKOUT4;\noutput CLKOUT5;\noutput CLKOUT6;\noutput CLKFBOUT;\nparameter FCLKIN = \"100.0\"; \nparameter IDIV_SEL = 1; \nparameter FBDIV_SEL = 1; \nparameter ODIV0_SEL = 8; \nparameter ODIV1_SEL = 8; \nparameter ODIV2_SEL = 8; \nparameter ODIV3_SEL = 8; \nparameter ODIV4_SEL = 8; \nparameter ODIV5_SEL = 8; \nparameter ODIV6_SEL = 8; \nparameter MDIV_SEL = 8; \nparameter MDIV_FRAC_SEL = 0; \nparameter ODIV0_FRAC_SEL = 0; \nparameter CLKOUT0_EN = \"TRUE\";\nparameter CLKOUT1_EN = \"FALSE\";\nparameter CLKOUT2_EN = \"FALSE\";\nparameter CLKOUT3_EN = \"FALSE\";\nparameter CLKOUT4_EN = \"FALSE\";\nparameter CLKOUT5_EN = \"FALSE\";\nparameter CLKOUT6_EN = \"FALSE\";\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter CLKOUT0_DT_DIR = 1'b1; \nparameter CLKOUT1_DT_DIR = 1'b1; \nparameter CLKOUT2_DT_DIR = 1'b1; \nparameter CLKOUT3_DT_DIR = 1'b1; \nparameter CLKOUT0_DT_STEP = 0; \nparameter CLKOUT1_DT_STEP = 0; \nparameter CLKOUT2_DT_STEP = 0; \nparameter CLKOUT3_DT_STEP = 0; \nparameter CLK0_IN_SEL = 1'b0;\nparameter CLK0_OUT_SEL = 1'b0;\nparameter CLK1_IN_SEL = 1'b0;\nparameter CLK1_OUT_SEL = 1'b0;\nparameter CLK2_IN_SEL = 1'b0;\nparameter CLK2_OUT_SEL = 1'b0;\nparameter CLK3_IN_SEL = 1'b0;\nparameter CLK3_OUT_SEL = 1'b0;\nparameter CLK4_IN_SEL = 2'b00;\nparameter CLK4_OUT_SEL = 1'b0;\nparameter CLK5_IN_SEL = 1'b0;\nparameter CLK5_OUT_SEL = 1'b0;\nparameter CLK6_IN_SEL = 1'b0;\nparameter CLK6_OUT_SEL = 1'b0;\nparameter DYN_DPA_EN = \"FALSE\";\nparameter CLKOUT0_PE_COARSE = 0;\nparameter CLKOUT0_PE_FINE = 0;\nparameter CLKOUT1_PE_COARSE = 0;\nparameter CLKOUT1_PE_FINE = 0;\nparameter CLKOUT2_PE_COARSE = 0;\nparameter CLKOUT2_PE_FINE = 0;\nparameter CLKOUT3_PE_COARSE = 0;\nparameter CLKOUT3_PE_FINE = 0;\nparameter CLKOUT4_PE_COARSE = 0;\nparameter CLKOUT4_PE_FINE = 0;\nparameter CLKOUT5_PE_COARSE = 0;\nparameter CLKOUT5_PE_FINE = 0;\nparameter CLKOUT6_PE_COARSE = 0;\nparameter CLKOUT6_PE_FINE = 0;\nparameter DYN_PE0_SEL = \"FALSE\";\nparameter DYN_PE1_SEL = \"FALSE\";\nparameter DYN_PE2_SEL = \"FALSE\";\nparameter DYN_PE3_SEL = \"FALSE\";\nparameter DYN_PE4_SEL = \"FALSE\";\nparameter DYN_PE5_SEL = \"FALSE\";\nparameter DYN_PE6_SEL = \"FALSE\";\nparameter DE0_EN = \"FALSE\";\nparameter DE1_EN = \"FALSE\";\nparameter DE2_EN = \"FALSE\";\nparameter DE3_EN = \"FALSE\";\nparameter DE4_EN = \"FALSE\";\nparameter DE5_EN = \"FALSE\";\nparameter DE6_EN = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_O_EN =  \"FALSE\";\nparameter ICP_SEL = 6'bXXXXXX;\nparameter LPF_RES = 3'bXXX;\nparameter LPF_CAP = 2'b00;\nparameter SSC_EN = \"FALSE\";\nendmodule\n\nmodule AE350_SOC (...);\ninput               POR_N;\ninput               HW_RSTN;\ninput               CORE_CLK;\ninput               DDR_CLK;\ninput               AHB_CLK;\ninput               APB_CLK;\ninput               DBG_TCK;\ninput               RTC_CLK;\ninput               CORE_CE;\ninput               AXI_CE;\ninput               DDR_CE;\ninput               AHB_CE;\ninput     [7:0]     APB_CE;\ninput               APB2AHB_CE;\ninput               SCAN_TEST;\ninput               SCAN_EN;\noutput              PRESETN;\noutput              HRESETN;\noutput              DDR_RSTN;\ninput       [15:0]  GP_INT;\ninput       [ 7:0]  DMA_REQ;\noutput      [ 7:0]  DMA_ACK;\noutput              CORE0_WFI_MODE;\ninput               WAKEUP_IN;           \noutput              RTC_WAKEUP;           \ninput               TEST_CLK;\ninput               TEST_MODE;\ninput               TEST_RSTN;\noutput  [31:0]      ROM_HADDR;\ninput   [31:0]      ROM_HRDATA;\ninput               ROM_HREADY;\ninput               ROM_HRESP;\noutput   [1:0]      ROM_HTRANS;\noutput              ROM_HWRITE;\noutput  [31:0]      APB_PADDR;\noutput              APB_PENABLE;\ninput   [31:0]      APB_PRDATA;\ninput               APB_PREADY;\noutput              APB_PSEL;\noutput  [31:0]      APB_PWDATA;\noutput              APB_PWRITE;\ninput               APB_PSLVERR;\noutput   [2:0]      APB_PPROT;\noutput   [3:0]      APB_PSTRB;\ninput   [31:0]      EXTS_HRDATA;\ninput               EXTS_HREADYIN;\ninput               EXTS_HRESP;\noutput  [31:0]      EXTS_HADDR;\noutput   [2:0]      EXTS_HBURST;\noutput   [3:0]      EXTS_HPROT;\noutput              EXTS_HSEL;\noutput   [2:0]      EXTS_HSIZE;\noutput   [1:0]      EXTS_HTRANS;\noutput  [31:0]      EXTS_HWDATA;\noutput              EXTS_HWRITE;\ninput   [31:0]      EXTM_HADDR;\ninput    [2:0]      EXTM_HBURST;\ninput    [3:0]      EXTM_HPROT;\noutput  [63:0]      EXTM_HRDATA;\ninput               EXTM_HREADY;\noutput              EXTM_HREADYOUT;\noutput              EXTM_HRESP;\ninput               EXTM_HSEL;\ninput    [2:0]      EXTM_HSIZE;\ninput    [1:0]      EXTM_HTRANS;\ninput   [63:0]      EXTM_HWDATA;\ninput               EXTM_HWRITE;\noutput  [31:0]      DDR_HADDR;\noutput   [2:0]      DDR_HBURST;\noutput   [3:0]      DDR_HPROT;\ninput   [63:0]      DDR_HRDATA;\ninput               DDR_HREADY;\ninput               DDR_HRESP;\noutput   [2:0]      DDR_HSIZE;\noutput   [1:0]      DDR_HTRANS;\noutput  [63:0]      DDR_HWDATA;\noutput              DDR_HWRITE;\ninput               TMS_IN;           \ninput               TRST_IN;\ninput               TDI_IN;\noutput              TDO_OUT;\noutput              TDO_OE;\ninput               SPI2_HOLDN_IN;\ninput               SPI2_WPN_IN;\ninput               SPI2_CLK_IN;\ninput               SPI2_CSN_IN;\ninput               SPI2_MISO_IN;\ninput               SPI2_MOSI_IN;\noutput              SPI2_HOLDN_OUT;\noutput              SPI2_HOLDN_OE;\noutput              SPI2_WPN_OUT;\noutput              SPI2_WPN_OE;\noutput              SPI2_CLK_OUT;\noutput              SPI2_CLK_OE;\noutput              SPI2_CSN_OUT;\noutput              SPI2_CSN_OE;\noutput              SPI2_MISO_OUT;\noutput              SPI2_MISO_OE;\noutput              SPI2_MOSI_OUT;\noutput              SPI2_MOSI_OE;\ninput               I2C_SCL_IN;\ninput               I2C_SDA_IN;\noutput              I2C_SCL;\noutput              I2C_SDA;\noutput              UART1_TXD;\noutput              UART1_RTSN;\ninput               UART1_RXD;\ninput               UART1_CTSN;\ninput               UART1_DSRN;\ninput               UART1_DCDN;\ninput               UART1_RIN;\noutput              UART1_DTRN;\noutput              UART1_OUT1N;\noutput              UART1_OUT2N;\noutput              UART2_TXD;\noutput              UART2_RTSN;\ninput               UART2_RXD;\ninput               UART2_CTSN;\ninput               UART2_DCDN;\ninput               UART2_DSRN;\ninput               UART2_RIN;\noutput              UART2_DTRN;\noutput              UART2_OUT1N;\noutput              UART2_OUT2N;\noutput              CH0_PWM;\noutput              CH0_PWMOE;\noutput              CH1_PWM;\noutput              CH1_PWMOE;\noutput              CH2_PWM;\noutput              CH2_PWMOE;\noutput              CH3_PWM;\noutput              CH3_PWMOE;\ninput     [31:0]    GPIO_IN;\noutput    [31:0]    GPIO_OE;\noutput    [31:0]    GPIO_OUT;\ninput\t [19:0]\tSCAN_IN;\ninput\t\tINTEG_TCK;\ninput\t\tINTEG_TDI;\ninput\t\tINTEG_TMS;\ninput\t\tINTEG_TRST;\noutput\t\tINTEG_TDO;\noutput   [19:0]\tSCAN_OUT;\ninput\t\tPGEN_CHAIN_I;\noutput\t\tPRDYN_CHAIN_O;\ninput\t[2:0]\tEMA;\ninput\t[1:0]\tEMAW;\ninput\t\tEMAS;\ninput\t\tRET1N;\ninput\t\tRET2N;\nendmodule\n\nmodule AE350_RAM (...);\ninput               POR_N;\ninput               HW_RSTN;\ninput               CORE_CLK;\ninput               AHB_CLK;\ninput               APB_CLK;\ninput               RTC_CLK;\ninput               CORE_CE;\ninput               AXI_CE;\ninput               AHB_CE;\ninput   [31:0]      EXTM_HADDR;\ninput    [2:0]      EXTM_HBURST;\ninput    [3:0]      EXTM_HPROT;\noutput  [63:0]      EXTM_HRDATA;\ninput               EXTM_HREADY;\noutput              EXTM_HREADYOUT;\noutput              EXTM_HRESP;\ninput               EXTM_HSEL;\ninput    [2:0]      EXTM_HSIZE;\ninput    [1:0]      EXTM_HTRANS;\ninput   [63:0]      EXTM_HWDATA;\ninput               EXTM_HWRITE;\ninput\t[2:0]\tEMA;\ninput\t[1:0]\tEMAW;\ninput\t\tEMAS;\ninput\t\tRET1N;\ninput\t\tRET2N;\nendmodule\n\nmodule SAMB (...);\nparameter MODE = 2'b00; \ninput [23:0] SPIAD;\ninput LOAD;\ninput ADWSEL; \nendmodule\n\nmodule OTP (...);\nparameter MODE = 2'b01; \ninput CLK, READ, SHIFT;\noutput DOUT;\nendmodule\n\nmodule CMSER (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [27:0] ERRLOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERRINJECT;\ninput [6:0] ERRINJLOC;\nendmodule\n\nmodule CMSERA (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [26:0] ERR0LOC;\noutput [26:0] ERR1LOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERR0INJECT,ERR1INJECT;\ninput [6:0] ERRINJ0LOC,ERRINJ1LOC;\nendmodule\n\nmodule CMSERB (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [12:0] ERRLOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERR0INJECT,ERR1INJECT;\ninput [6:0] ERRINJ0LOC,ERRINJ1LOC;\nendmodule\n\nmodule SAMBA (...);\nparameter MODE = 2'b00; \ninput SPIAD;\ninput LOAD;\nendmodule\n\nmodule ADCLRC (...);\nendmodule\n\nmodule ADCULC (...);\nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput D0LN_DESKEW_DONE,D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE;\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O;          \noutput DESKEW_ERROR;      \ninout  CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput BYTE_LENDIAN;       \ninput [2:0] FIFO_RD_STD;  \ninput HSRX_STOP;          \ninput PWRON;              \ninput RESET;              \ninput D0LN_HSRX_DREN,  D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput DESKEW_BY,DESKEW_EN_OEDGE;\ninput [5:0] DESKEW_HALF_OPENING;\ninput [2:0] DESKEW_LNSEL; \ninput [1:0] DESKEW_LSB_MODE;\ninput [2:0] DESKEW_M;\ninput [12:0] DESKEW_MTH;   \ninput [6:0] DESKEW_MSET;\ninput DESKEW_OCLKEDG_EN;\ninput [6:0] DESKEW_OWVAL;\ninput DESKEW_REQ;         \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput DRST_N;             \ninput [2:0] EQCS_LANE0,EQCS_LANE1,EQCS_LANE2,EQCS_LANE3,EQCS_CK;\ninput [2:0] EQRS_LANE0,EQRS_LANE1,EQRS_LANE2,EQRS_LANE3,EQRS_CK;\ninput HS_8BIT_MODE;       \ninput HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1,HSRX_DLYDIR_LANE2,HSRX_DLYDIR_LANE3,HSRX_DLYDIR_CK;\ninput HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1,HSRX_DLYLDN_LANE2,HSRX_DLYLDN_LANE3,HSRX_DLYLDN_CK;\ninput HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,HSRX_DLYMV_LANE2,HSRX_DLYMV_LANE3,HSRX_DLYMV_CK;\ninput HSRX_EN_CK;         \ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0,  HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput LALIGN_EN;          \ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput ONE_BYTE0_MATCH;    \ninput RX_CLK_1X;          \ninput RX_INVERT;          \ninput WALIGN_BY;          \ninput WALIGN_DVLD;\ninput WORD_LENDIAN;       \nparameter ALIGN_BYTE = 8'b10111000;\nparameter EN_CLKB1X = 1'b1;\nparameter EQ_ADPSEL_LANE0 = 1'b0;\nparameter EQ_ADPSEL_LANE1 = 1'b0;\nparameter EQ_ADPSEL_LANE2 = 1'b0;\nparameter EQ_ADPSEL_LANE3 = 1'b0;\nparameter EQ_ADPSEL_CK = 1'b0;\nparameter EQ_CS_LANE0 = 3'b100;\nparameter EQ_CS_LANE1 = 3'b100;\nparameter EQ_CS_LANE2 = 3'b100;\nparameter EQ_CS_LANE3 = 3'b100;\nparameter EQ_CS_CK = 3'b100;\nparameter EQ_PBIAS_LANE0 = 4'b0100;\nparameter EQ_PBIAS_LANE1 = 4'b0100;\nparameter EQ_PBIAS_LANE2 = 4'b0100;\nparameter EQ_PBIAS_LANE3 = 4'b0100;\nparameter EQ_PBIAS_CK = 4'b0100;\nparameter EQ_RS_LANE0 = 3'b100;\nparameter EQ_RS_LANE1 = 3'b100;\nparameter EQ_RS_LANE2 = 3'b100;\nparameter EQ_RS_LANE3 = 3'b100;\nparameter EQ_RS_CK = 3'b100;\nparameter EQ_ZLD_LANE0 = 4'b1000;\nparameter EQ_ZLD_LANE1 = 4'b1000;\nparameter EQ_ZLD_LANE2 = 4'b1000;\nparameter EQ_ZLD_LANE3 = 4'b1000;\nparameter EQ_ZLD_CK = 4'b1000;\nparameter HIGH_BW_LANE0 = 1'b1;\nparameter HIGH_BW_LANE1 = 1'b1;\nparameter HIGH_BW_LANE2 = 1'b1;\nparameter HIGH_BW_LANE3 = 1'b1;\nparameter HIGH_BW_CK = 1'b1;\nparameter HSRX_DLYCTL_CK = 7'b0000000;\nparameter HSRX_DLYCTL_LANE0 = 7'b0000000;\nparameter HSRX_DLYCTL_LANE1 = 7'b0000000;\nparameter HSRX_DLYCTL_LANE2 = 7'b0000000;\nparameter HSRX_DLYCTL_LANE3 = 7'b0000000;\nparameter HSRX_DLY_SEL = 1'b0;\nparameter HSRX_DUTY_LANE0 = 4'b1000;\nparameter HSRX_DUTY_LANE1 = 4'b1000;\nparameter HSRX_DUTY_LANE2 = 4'b1000;\nparameter HSRX_DUTY_LANE3 = 4'b1000;\nparameter HSRX_DUTY_CK = 4'b1000;\nparameter HSRX_EN = 1'b1;\nparameter HSRX_EQ_EN_LANE0 = 1'b1;\nparameter HSRX_EQ_EN_LANE1 = 1'b1;\nparameter HSRX_EQ_EN_LANE2 = 1'b1;\nparameter HSRX_EQ_EN_LANE3 = 1'b1;\nparameter HSRX_EQ_EN_CK = 1'b1;\nparameter HSRX_IBIAS = 4'b0011;\nparameter HSRX_IMARG_EN = 1'b1;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter HSRX_ODT_EN = 1'b1;\nparameter HSRX_ODT_TST = 4'b0000;\nparameter HSRX_ODT_TST_CK = 1'b0;\nparameter HSRX_STOP_EN = 1'b0;\nparameter HSRX_TST = 4'b0000;\nparameter HSRX_TST_CK = 1'b0;\nparameter HSRX_WAIT4EDGE = 1'b0;\nparameter HYST_NCTL = 2'b01;\nparameter HYST_PCTL = 2'b01;\nparameter LOW_LPRX_VTH = 1'b0;\nparameter LPRX_EN = 1'b1;\nparameter LPRX_TST = 4'b0000;\nparameter LPRX_TST_CK = 1'b0;\nparameter LPTX_EN = 1'b1;\nparameter LPTX_SW_LANE0 = 3'b100;\nparameter LPTX_SW_LANE1 = 3'b100;\nparameter LPTX_SW_LANE2 = 3'b100;\nparameter LPTX_SW_LANE3 = 3'b100;\nparameter LPTX_SW_CK = 3'b100;\nparameter LPTX_TST = 4'b0000;\nparameter LPTX_TST_CK = 1'b0;\nparameter MIPI_DIS_N = 1'b1;\nparameter PGA_BIAS_LANE0 =  4'b1000;\nparameter PGA_BIAS_LANE1 =  4'b1000;\nparameter PGA_BIAS_LANE2 =  4'b1000;\nparameter PGA_BIAS_LANE3 =  4'b1000;\nparameter PGA_BIAS_CK =  4'b1000;\nparameter PGA_GAIN_LANE0 =  4'b1000;\nparameter PGA_GAIN_LANE1 =  4'b1000;\nparameter PGA_GAIN_LANE2 =  4'b1000;\nparameter PGA_GAIN_LANE3 =  4'b1000;\nparameter PGA_GAIN_CK =  4'b1000;\nparameter RX_CLK1X_SYNC_SEL = 1'b0;\nparameter RX_ODT_TRIM_LANE0 = 4'b0111;\nparameter RX_ODT_TRIM_LANE1 = 4'b0111;\nparameter RX_ODT_TRIM_LANE2 = 4'b0111;\nparameter RX_ODT_TRIM_LANE3 = 4'b0111;\nparameter RX_ODT_TRIM_CK = 4'b0111;\nparameter STP_UNIT = 2'b00;\nparameter SYNC_CLK_SEL = 1'b1;\nparameter WALIGN_DVLD_SRC_SEL = 1'b0;\nendmodule\n\nmodule MIPI_DPHY (...);\noutput RX_CLK_O, TX_CLK_O;\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\ninput  D0LN_HSRX_DREN, D1LN_HSRX_DREN,  D2LN_HSRX_DREN,  D3LN_HSRX_DREN;\noutput  DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N,  DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;\ninout  CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;\ninput HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK;\ninput PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;\ninput TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;\ninput [15:0]  CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;\ninput HSTXD_VLD;\ninput CK0, CK90, CK180, CK270;\ninput DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;\ninput HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK;\ninput RX_DRST_N, TX_DRST_N, WALIGN_DVLD;\noutput [7:0] MRDATA;\ninput MA_INC, MCLK;\ninput [1:0] MOPCODE;\ninput [7:0] MWDATA;\noutput  ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;\noutput D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;\noutput D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;\ninput D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;\ninput HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;\ninput HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;\ninput HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,  HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;\ninput  ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;\nparameter        TX_PLLCLK = \"NONE\"; \nparameter        RX_ALIGN_BYTE                  = 8'b10111000 ; \nparameter        RX_HS_8BIT_MODE                = 1'b0 ; \nparameter        RX_LANE_ALIGN_EN               = 1'b0 ; \nparameter        TX_HS_8BIT_MODE                = 1'b0 ; \nparameter        HSREG_EN_LN0                   = 1'b0;  \nparameter        HSREG_EN_LN1                   = 1'b0;  \nparameter        HSREG_EN_LN2                   = 1'b0;  \nparameter        HSREG_EN_LN3                   = 1'b0;  \nparameter        HSREG_EN_LNCK                  = 1'b0;  \nparameter        LANE_DIV_SEL                   = 2'b00;  \nparameter        HSRX_EN                        = 1'b1 ;  \nparameter        HSRX_LANESEL                   = 4'b1111 ;   \nparameter        HSRX_LANESEL_CK                = 1'b1 ;   \nparameter        HSTX_EN_LN0                    = 1'b0 ;   \nparameter        HSTX_EN_LN1                    = 1'b0 ;   \nparameter        HSTX_EN_LN2                    = 1'b0 ;   \nparameter        HSTX_EN_LN3                    = 1'b0 ;   \nparameter        HSTX_EN_LNCK                   = 1'b0 ;   \nparameter        LPTX_EN_LN0                    = 1'b1 ;   \nparameter        LPTX_EN_LN1                    = 1'b1 ;   \nparameter        LPTX_EN_LN2                    = 1'b1 ;   \nparameter        LPTX_EN_LN3                    = 1'b1 ;   \nparameter        LPTX_EN_LNCK                   = 1'b1 ;   \nparameter        TXDP_EN_LN0                    = 1'b0 ;  \nparameter        TXDP_EN_LN1                    = 1'b0 ;   \nparameter        TXDP_EN_LN2                    = 1'b0 ;   \nparameter        TXDP_EN_LN3                    = 1'b0 ;   \nparameter        TXDP_EN_LNCK                   = 1'b0 ;\nparameter        CKLN_DELAY_EN                  = 1'b0;  \nparameter        CKLN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D0LN_DELAY_EN                  = 1'b0;  \nparameter        D0LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D0LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D1LN_DELAY_EN                  = 1'b0;  \nparameter        D1LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D1LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D2LN_DELAY_EN                  = 1'b0;  \nparameter        D2LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D2LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D3LN_DELAY_EN                  = 1'b0;  \nparameter        D3LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D3LN_DESKEW_BYPASS             = 1'b0;  \nparameter        DESKEW_EN_LOW_DELAY            = 1'b0;  \nparameter        DESKEW_EN_ONE_EDGE             = 1'b0;  \nparameter        DESKEW_FAST_LOOP_TIME          = 4'b0000;  \nparameter        DESKEW_FAST_MODE               = 1'b0;  \nparameter        DESKEW_HALF_OPENING            = 6'b010110; \nparameter        DESKEW_LSB_MODE                = 2'b00;  \nparameter        DESKEW_M                       = 3'b011;  \nparameter        DESKEW_M_TH                    = 13'b0000110100110; \nparameter        DESKEW_MAX_SETTING           = 7'b0100001; \nparameter        DESKEW_ONE_CLK_EDGE_EN       = 1'b0 ; \nparameter        DESKEW_RST_BYPASS              = 1'b0 ; \nparameter        RX_BYTE_LITTLE_ENDIAN          = 1'b1 ; \nparameter        RX_CLK_1X_SYNC_SEL             = 1'b0 ; \nparameter        RX_INVERT                      = 1'b0 ; \nparameter        RX_ONE_BYTE0_MATCH             = 1'b0 ; \nparameter        RX_RD_START_DEPTH              = 5'b00001; \nparameter        RX_SYNC_MODE                   = 1'b0 ; \nparameter        RX_WORD_ALIGN_BYPASS           = 1'b0 ; \nparameter        RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; \nparameter        RX_WORD_LITTLE_ENDIAN          = 1'b1 ; \nparameter        TX_BYPASS_MODE                 = 1'b0 ; \nparameter        TX_BYTECLK_SYNC_MODE           = 1'b0 ; \nparameter        TX_OCLK_USE_CIBCLK             = 1'b0 ; \nparameter        TX_RD_START_DEPTH              = 5'b00001; \nparameter        TX_SYNC_MODE                   = 1'b0 ; \nparameter        TX_WORD_LITTLE_ENDIAN          = 1'b1 ; \nparameter        EQ_CS_LANE0                    = 3'b100;  \nparameter        EQ_CS_LANE1                    = 3'b100;  \nparameter        EQ_CS_LANE2                    = 3'b100;  \nparameter        EQ_CS_LANE3                    = 3'b100;  \nparameter        EQ_CS_LANECK                   = 3'b100;  \nparameter        EQ_RS_LANE0                    = 3'b100;  \nparameter        EQ_RS_LANE1                    = 3'b100;  \nparameter        EQ_RS_LANE2                    = 3'b100;  \nparameter        EQ_RS_LANE3                    = 3'b100;  \nparameter        EQ_RS_LANECK                   = 3'b100;  \nparameter        HSCLK_LANE_LN0                 = 1'b0;  \nparameter        HSCLK_LANE_LN1                 = 1'b0;  \nparameter        HSCLK_LANE_LN2                 = 1'b0;  \nparameter        HSCLK_LANE_LN3                 = 1'b0;  \nparameter        HSCLK_LANE_LNCK                = 1'b1;  \nparameter        ALP_ED_EN_LANE0                = 1'b1 ; \nparameter        ALP_ED_EN_LANE1                = 1'b1 ;  \nparameter        ALP_ED_EN_LANE2                = 1'b1 ;  \nparameter        ALP_ED_EN_LANE3                = 1'b1 ;  \nparameter        ALP_ED_EN_LANECK               = 1'b1 ; \nparameter        ALP_ED_TST_LANE0               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE1               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE2               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE3               = 1'b0 ;  \nparameter        ALP_ED_TST_LANECK              = 1'b0 ;  \nparameter        ALP_EN_LN0                     = 1'b0 ; \nparameter        ALP_EN_LN1                     = 1'b0 ;  \nparameter        ALP_EN_LN2                     = 1'b0 ;  \nparameter        ALP_EN_LN3                     = 1'b0 ; \nparameter        ALP_EN_LNCK                    = 1'b0 ; \nparameter        ALP_HYS_EN_LANE0               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE1               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE2               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE3               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANECK              = 1'b1 ;  \nparameter        ALP_TH_LANE0                   = 4'b1000 ;   \nparameter        ALP_TH_LANE1                   = 4'b1000 ;   \nparameter        ALP_TH_LANE2                   = 4'b1000 ;   \nparameter        ALP_TH_LANE3                   = 4'b1000 ;   \nparameter        ALP_TH_LANECK                  = 4'b1000 ;   \nparameter        ANA_BYTECLK_PH                 = 2'b00 ;  \nparameter        BIT_REVERSE_LN0                = 1'b0 ;  \nparameter        BIT_REVERSE_LN1                = 1'b0 ;  \nparameter        BIT_REVERSE_LN2                = 1'b0 ;  \nparameter        BIT_REVERSE_LN3                = 1'b0 ;  \nparameter        BIT_REVERSE_LNCK               = 1'b0 ;  \nparameter        BYPASS_TXHCLKEN                = 1'b1 ;  \nparameter        BYPASS_TXHCLKEN_SYNC           = 1'b0 ;  \nparameter        BYTE_CLK_POLAR                 = 1'b0 ;  \nparameter        BYTE_REVERSE_LN0               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN1               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN2               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN3               = 1'b0 ;  \nparameter        BYTE_REVERSE_LNCK              = 1'b0 ;  \nparameter        EN_CLKB1X                      = 1'b1 ;  \nparameter        EQ_PBIAS_LANE0                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE1                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE2                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE3                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANECK                = 4'b1000 ;   \nparameter        EQ_ZLD_LANE0                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE1                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE2                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE3                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANECK                  = 4'b1000 ;   \nparameter        HIGH_BW_LANE0                  = 1'b1 ;   \nparameter        HIGH_BW_LANE1                  = 1'b1 ;   \nparameter        HIGH_BW_LANE2                  = 1'b1 ;   \nparameter        HIGH_BW_LANE3                  = 1'b1 ;   \nparameter        HIGH_BW_LANECK                 = 1'b1 ;   \nparameter        HSREG_VREF_CTL                 = 3'b100 ;   \nparameter        HSREG_VREF_EN                  = 1'b1 ;  \nparameter        HSRX_DLY_CTL_CK                = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE0             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE1             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE2             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE3             = 7'b0000000 ;   \nparameter        HSRX_DLY_SEL_LANE0             = 1'b0 ;  \nparameter        HSRX_DLY_SEL_LANE1             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANE2             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANE3             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANECK            = 1'b0 ;   \nparameter        HSRX_DUTY_LANE0                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE1                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE2                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE3                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANECK               = 4'b1000 ;  \nparameter        HSRX_EQ_EN_LANE0               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE1               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE2               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE3               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANECK              = 1'b1 ;  \nparameter        HSRX_IBIAS                     = 4'b0011 ;   \nparameter        HSRX_IBIAS_TEST_EN             = 1'b0 ;   \nparameter        HSRX_IMARG_EN                  = 1'b0 ;   \nparameter        HSRX_ODT_EN                    = 1'b1 ;   \nparameter        HSRX_ODT_TST                   = 4'b0000 ;   \nparameter        HSRX_ODT_TST_CK                = 1'b0 ;   \nparameter        HSRX_SEL                       = 4'b0000 ;   \nparameter        HSRX_STOP_EN                   = 1'b0 ; \nparameter        HSRX_TST                       = 4'b0000 ;   \nparameter        HSRX_TST_CK                    = 1'b0 ;   \nparameter        HSRX_WAIT4EDGE                 = 1'b1 ;   \nparameter        HYST_NCTL                      = 2'b01 ;  \nparameter        HYST_PCTL                      = 2'b01 ;  \nparameter        IBIAS_TEST_EN                  = 1'b0 ;   \nparameter        LB_CH_SEL                      = 1'b0 ;   \nparameter        LB_EN_LN0                      = 1'b0 ;   \nparameter        LB_EN_LN1                      = 1'b0 ;   \nparameter        LB_EN_LN2                      = 1'b0 ;   \nparameter        LB_EN_LN3                      = 1'b0 ;   \nparameter        LB_EN_LNCK                     = 1'b0 ;   \nparameter        LB_POLAR_LN0                   = 1'b0 ;   \nparameter        LB_POLAR_LN1                   = 1'b0 ;   \nparameter        LB_POLAR_LN2                   = 1'b0 ;   \nparameter        LB_POLAR_LN3                   = 1'b0 ;   \nparameter        LB_POLAR_LNCK                  = 1'b0 ;   \nparameter        LOW_LPRX_VTH                   = 1'b0 ;   \nparameter        LPBK_DATA2TO1                  = 4'b0000;  \nparameter        LPBK_DATA2TO1_CK               = 1'b0 ;   \nparameter        LPBK_EN                        = 1'b0 ;   \nparameter        LPBK_SEL                       = 4'b0000;  \nparameter        LPBKTST_EN                     = 4'b0000;  \nparameter        LPBKTST_EN_CK                  = 1'b0 ;   \nparameter        LPRX_EN                        = 1'b1 ;   \nparameter        LPRX_TST                       = 4'b0000;  \nparameter        LPRX_TST_CK                    = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN0             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN1             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN2             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN3             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LNCK            = 1'b0 ;   \nparameter        LPTX_NIMP_LN0                  = 3'b100 ; \nparameter        LPTX_NIMP_LN1                  = 3'b100 ; \nparameter        LPTX_NIMP_LN2                  = 3'b100 ; \nparameter        LPTX_NIMP_LN3                  = 3'b100 ; \nparameter        LPTX_NIMP_LNCK                 = 3'b100 ; \nparameter        LPTX_PIMP_LN0                  = 3'b100 ; \nparameter        LPTX_PIMP_LN1                  = 3'b100 ; \nparameter        LPTX_PIMP_LN2                  = 3'b100 ; \nparameter        LPTX_PIMP_LN3                  = 3'b100 ; \nparameter        LPTX_PIMP_LNCK                 = 3'b100 ; \nparameter        MIPI_PMA_DIS_N                 = 1'b1 ;   \nparameter        PGA_BIAS_LANE0                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE1                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE2                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE3                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANECK                = 4'b1000 ;   \nparameter        PGA_GAIN_LANE0                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE1                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE2                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE3                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANECK                = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE0              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE1              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE2              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE3              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANECK             = 4'b1000 ;   \nparameter        SLEWN_CTL_LN0                  = 4'b1111 ;  \nparameter        SLEWN_CTL_LN1                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LN2                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LN3                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LNCK                 = 4'b1111 ;   \nparameter        SLEWP_CTL_LN0                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN1                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN2                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN3                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LNCK                 = 4'b1111 ;   \nparameter        STP_UNIT                       = 2'b01 ;  \nparameter        TERMN_CTL_LN0                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN1                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN2                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN3                  = 4'b1000 ;   \nparameter        TERMN_CTL_LNCK                 = 4'b1000 ;   \nparameter        TERMP_CTL_LN0                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN1                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN2                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN3                  = 4'b1000 ;   \nparameter        TERMP_CTL_LNCK                 = 4'b1000 ;   \nparameter        TEST_EN_LN0                    = 1'b0 ;   \nparameter        TEST_EN_LN1                    = 1'b0 ;   \nparameter        TEST_EN_LN2                    = 1'b0 ;   \nparameter        TEST_EN_LN3                    = 1'b0 ;   \nparameter        TEST_EN_LNCK                   = 1'b0 ;   \nparameter        TEST_N_IMP_LN0                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN1                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN2                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN3                 = 1'b0 ;   \nparameter        TEST_N_IMP_LNCK                = 1'b0 ;   \nparameter        TEST_P_IMP_LN0                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN1                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN2                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN3                 = 1'b0 ;   \nparameter        TEST_P_IMP_LNCK                = 1'b0 ;   \nendmodule\n\nmodule MIPI_DPHYA (...);\noutput RX_CLK_O, TX_CLK_O;\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\ninput  D0LN_HSRX_DREN, D1LN_HSRX_DREN,  D2LN_HSRX_DREN,  D3LN_HSRX_DREN;\noutput  DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N,  DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;\ninout  CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;\ninput HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK;\ninput PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;\ninput TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;\ninput [15:0]  CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;\ninput HSTXD_VLD;\ninput CK0, CK90, CK180, CK270;\ninput DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;\ninput HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK;\ninput RX_DRST_N, TX_DRST_N, WALIGN_DVLD;\noutput [7:0] MRDATA;\ninput MA_INC, MCLK;\ninput [1:0] MOPCODE;\ninput [7:0] MWDATA;\ninput SPLL_CKN, SPLL_CKP;\noutput  ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;\noutput D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;\noutput D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;\ninput D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;\ninput HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;\ninput HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;\ninput HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,  HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;\ninput  ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;\nparameter        TX_PLLCLK = \"NONE\"; \nparameter        RX_ALIGN_BYTE                  = 8'b10111000 ; \nparameter        RX_HS_8BIT_MODE                = 1'b0 ; \nparameter        RX_LANE_ALIGN_EN               = 1'b0 ; \nparameter        TX_HS_8BIT_MODE                = 1'b0 ; \nparameter        HSREG_EN_LN0                   = 1'b0;  \nparameter        HSREG_EN_LN1                   = 1'b0;  \nparameter        HSREG_EN_LN2                   = 1'b0;  \nparameter        HSREG_EN_LN3                   = 1'b0;  \nparameter        HSREG_EN_LNCK                  = 1'b0;  \nparameter        LANE_DIV_SEL                   = 2'b00;  \nparameter        HSRX_EN                        = 1'b1 ;  \nparameter        HSRX_LANESEL                   = 4'b1111 ;   \nparameter        HSRX_LANESEL_CK                = 1'b1 ;   \nparameter        HSTX_EN_LN0                    = 1'b0 ;   \nparameter        HSTX_EN_LN1                    = 1'b0 ;   \nparameter        HSTX_EN_LN2                    = 1'b0 ;   \nparameter        HSTX_EN_LN3                    = 1'b0 ;   \nparameter        HSTX_EN_LNCK                   = 1'b0 ;   \nparameter        LPTX_EN_LN0                    = 1'b1 ;   \nparameter        LPTX_EN_LN1                    = 1'b1 ;   \nparameter        LPTX_EN_LN2                    = 1'b1 ;   \nparameter        LPTX_EN_LN3                    = 1'b1 ;   \nparameter        LPTX_EN_LNCK                   = 1'b1 ;   \nparameter        TXDP_EN_LN0                    = 1'b0 ;  \nparameter        TXDP_EN_LN1                    = 1'b0 ;   \nparameter        TXDP_EN_LN2                    = 1'b0 ;   \nparameter        TXDP_EN_LN3                    = 1'b0 ;   \nparameter        TXDP_EN_LNCK                   = 1'b0 ;\nparameter        SPLL_DIV_SEL                   = 2'b00;\nparameter        DPHY_CK_SEL                    = 2'b01;\nparameter        CKLN_DELAY_EN                  = 1'b0;  \nparameter        CKLN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D0LN_DELAY_EN                  = 1'b0;  \nparameter        D0LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D0LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D1LN_DELAY_EN                  = 1'b0;  \nparameter        D1LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D1LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D2LN_DELAY_EN                  = 1'b0;  \nparameter        D2LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D2LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D3LN_DELAY_EN                  = 1'b0;  \nparameter        D3LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D3LN_DESKEW_BYPASS             = 1'b0;  \nparameter        DESKEW_EN_LOW_DELAY            = 1'b0;  \nparameter        DESKEW_EN_ONE_EDGE             = 1'b0;  \nparameter        DESKEW_FAST_LOOP_TIME          = 4'b0000;  \nparameter        DESKEW_FAST_MODE               = 1'b0;  \nparameter        DESKEW_HALF_OPENING            = 6'b010110; \nparameter        DESKEW_LSB_MODE                = 2'b00;  \nparameter        DESKEW_M                       = 3'b011;  \nparameter        DESKEW_M_TH                    = 13'b0000110100110; \nparameter        DESKEW_MAX_SETTING           = 7'b0100001; \nparameter        DESKEW_ONE_CLK_EDGE_EN       = 1'b0 ; \nparameter        DESKEW_RST_BYPASS              = 1'b0 ; \nparameter        RX_BYTE_LITTLE_ENDIAN          = 1'b1 ; \nparameter        RX_CLK_1X_SYNC_SEL             = 1'b0 ; \nparameter        RX_INVERT                      = 1'b0 ; \nparameter        RX_ONE_BYTE0_MATCH             = 1'b0 ; \nparameter        RX_RD_START_DEPTH              = 5'b00001; \nparameter        RX_SYNC_MODE                   = 1'b0 ; \nparameter        RX_WORD_ALIGN_BYPASS           = 1'b0 ; \nparameter        RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; \nparameter        RX_WORD_LITTLE_ENDIAN          = 1'b1 ; \nparameter        TX_BYPASS_MODE                 = 1'b0 ; \nparameter        TX_BYTECLK_SYNC_MODE           = 1'b0 ; \nparameter        TX_OCLK_USE_CIBCLK             = 1'b0 ; \nparameter        TX_RD_START_DEPTH              = 5'b00001; \nparameter        TX_SYNC_MODE                   = 1'b0 ; \nparameter        TX_WORD_LITTLE_ENDIAN          = 1'b1 ; \nparameter        EQ_CS_LANE0                    = 3'b100;  \nparameter        EQ_CS_LANE1                    = 3'b100;  \nparameter        EQ_CS_LANE2                    = 3'b100;  \nparameter        EQ_CS_LANE3                    = 3'b100;  \nparameter        EQ_CS_LANECK                   = 3'b100;  \nparameter        EQ_RS_LANE0                    = 3'b100;  \nparameter        EQ_RS_LANE1                    = 3'b100;  \nparameter        EQ_RS_LANE2                    = 3'b100;  \nparameter        EQ_RS_LANE3                    = 3'b100;  \nparameter        EQ_RS_LANECK                   = 3'b100;  \nparameter        HSCLK_LANE_LN0                 = 1'b0;  \nparameter        HSCLK_LANE_LN1                 = 1'b0;  \nparameter        HSCLK_LANE_LN2                 = 1'b0;  \nparameter        HSCLK_LANE_LN3                 = 1'b0;  \nparameter        HSCLK_LANE_LNCK                = 1'b1;  \nparameter        ALP_ED_EN_LANE0                = 1'b1 ; \nparameter        ALP_ED_EN_LANE1                = 1'b1 ;  \nparameter        ALP_ED_EN_LANE2                = 1'b1 ;  \nparameter        ALP_ED_EN_LANE3                = 1'b1 ;  \nparameter        ALP_ED_EN_LANECK               = 1'b1 ; \nparameter        ALP_ED_TST_LANE0               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE1               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE2               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE3               = 1'b0 ;  \nparameter        ALP_ED_TST_LANECK              = 1'b0 ;  \nparameter        ALP_EN_LN0                     = 1'b0 ; \nparameter        ALP_EN_LN1                     = 1'b0 ;  \nparameter        ALP_EN_LN2                     = 1'b0 ;  \nparameter        ALP_EN_LN3                     = 1'b0 ; \nparameter        ALP_EN_LNCK                    = 1'b0 ; \nparameter        ALP_HYS_EN_LANE0               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE1               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE2               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE3               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANECK              = 1'b1 ;  \nparameter        ALP_TH_LANE0                   = 4'b1000 ;   \nparameter        ALP_TH_LANE1                   = 4'b1000 ;   \nparameter        ALP_TH_LANE2                   = 4'b1000 ;   \nparameter        ALP_TH_LANE3                   = 4'b1000 ;   \nparameter        ALP_TH_LANECK                  = 4'b1000 ;   \nparameter        ANA_BYTECLK_PH                 = 2'b00 ;  \nparameter        BIT_REVERSE_LN0                = 1'b0 ;  \nparameter        BIT_REVERSE_LN1                = 1'b0 ;  \nparameter        BIT_REVERSE_LN2                = 1'b0 ;  \nparameter        BIT_REVERSE_LN3                = 1'b0 ;  \nparameter        BIT_REVERSE_LNCK               = 1'b0 ;  \nparameter        BYPASS_TXHCLKEN                = 1'b1 ;  \nparameter        BYPASS_TXHCLKEN_SYNC           = 1'b0 ;  \nparameter        BYTE_CLK_POLAR                 = 1'b0 ;  \nparameter        BYTE_REVERSE_LN0               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN1               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN2               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN3               = 1'b0 ;  \nparameter        BYTE_REVERSE_LNCK              = 1'b0 ;  \nparameter        EN_CLKB1X                      = 1'b1 ;  \nparameter        EQ_PBIAS_LANE0                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE1                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE2                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE3                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANECK                = 4'b1000 ;   \nparameter        EQ_ZLD_LANE0                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE1                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE2                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE3                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANECK                  = 4'b1000 ;   \nparameter        HIGH_BW_LANE0                  = 1'b1 ;   \nparameter        HIGH_BW_LANE1                  = 1'b1 ;   \nparameter        HIGH_BW_LANE2                  = 1'b1 ;   \nparameter        HIGH_BW_LANE3                  = 1'b1 ;   \nparameter        HIGH_BW_LANECK                 = 1'b1 ;   \nparameter        HSREG_VREF_CTL                 = 3'b100 ;   \nparameter        HSREG_VREF_EN                  = 1'b1 ;  \nparameter        HSRX_DLY_CTL_CK                = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE0             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE1             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE2             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE3             = 7'b0000000 ;   \nparameter        HSRX_DLY_SEL_LANE0             = 1'b0 ;  \nparameter        HSRX_DLY_SEL_LANE1             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANE2             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANE3             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANECK            = 1'b0 ;   \nparameter        HSRX_DUTY_LANE0                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE1                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE2                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE3                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANECK               = 4'b1000 ;  \nparameter        HSRX_EQ_EN_LANE0               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE1               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE2               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE3               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANECK              = 1'b1 ;  \nparameter        HSRX_IBIAS                     = 4'b0011 ;   \nparameter        HSRX_IBIAS_TEST_EN             = 1'b0 ;   \nparameter        HSRX_IMARG_EN                  = 1'b0 ;   \nparameter        HSRX_ODT_EN                    = 1'b1 ;   \nparameter        HSRX_ODT_TST                   = 4'b0000 ;   \nparameter        HSRX_ODT_TST_CK                = 1'b0 ;   \nparameter        HSRX_SEL                       = 4'b0000 ;   \nparameter        HSRX_STOP_EN                   = 1'b0 ; \nparameter        HSRX_TST                       = 4'b0000 ;   \nparameter        HSRX_TST_CK                    = 1'b0 ;   \nparameter        HSRX_WAIT4EDGE                 = 1'b1 ;   \nparameter        HYST_NCTL                      = 2'b01 ;  \nparameter        HYST_PCTL                      = 2'b01 ;  \nparameter        IBIAS_TEST_EN                  = 1'b0 ;   \nparameter        LB_CH_SEL                      = 1'b0 ;   \nparameter        LB_EN_LN0                      = 1'b0 ;   \nparameter        LB_EN_LN1                      = 1'b0 ;   \nparameter        LB_EN_LN2                      = 1'b0 ;   \nparameter        LB_EN_LN3                      = 1'b0 ;   \nparameter        LB_EN_LNCK                     = 1'b0 ;   \nparameter        LB_POLAR_LN0                   = 1'b0 ;   \nparameter        LB_POLAR_LN1                   = 1'b0 ;   \nparameter        LB_POLAR_LN2                   = 1'b0 ;   \nparameter        LB_POLAR_LN3                   = 1'b0 ;   \nparameter        LB_POLAR_LNCK                  = 1'b0 ;   \nparameter        LOW_LPRX_VTH                   = 1'b0 ;   \nparameter        LPBK_DATA2TO1                  = 4'b0000;  \nparameter        LPBK_DATA2TO1_CK               = 1'b0 ;   \nparameter        LPBK_EN                        = 1'b0 ;   \nparameter        LPBK_SEL                       = 4'b0000;  \nparameter        LPBKTST_EN                     = 4'b0000;  \nparameter        LPBKTST_EN_CK                  = 1'b0 ;   \nparameter        LPRX_EN                        = 1'b1 ;   \nparameter        LPRX_TST                       = 4'b0000;  \nparameter        LPRX_TST_CK                    = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN0             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN1             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN2             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN3             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LNCK            = 1'b0 ;   \nparameter        LPTX_NIMP_LN0                  = 3'b100 ; \nparameter        LPTX_NIMP_LN1                  = 3'b100 ; \nparameter        LPTX_NIMP_LN2                  = 3'b100 ; \nparameter        LPTX_NIMP_LN3                  = 3'b100 ; \nparameter        LPTX_NIMP_LNCK                 = 3'b100 ; \nparameter        LPTX_PIMP_LN0                  = 3'b100 ; \nparameter        LPTX_PIMP_LN1                  = 3'b100 ; \nparameter        LPTX_PIMP_LN2                  = 3'b100 ; \nparameter        LPTX_PIMP_LN3                  = 3'b100 ; \nparameter        LPTX_PIMP_LNCK                 = 3'b100 ; \nparameter        MIPI_PMA_DIS_N                 = 1'b1 ;   \nparameter        PGA_BIAS_LANE0                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE1                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE2                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE3                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANECK                = 4'b1000 ;   \nparameter        PGA_GAIN_LANE0                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE1                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE2                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE3                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANECK                = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE0              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE1              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE2              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE3              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANECK             = 4'b1000 ;   \nparameter        SLEWN_CTL_LN0                  = 4'b1111 ;  \nparameter        SLEWN_CTL_LN1                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LN2                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LN3                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LNCK                 = 4'b1111 ;   \nparameter        SLEWP_CTL_LN0                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN1                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN2                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN3                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LNCK                 = 4'b1111 ;   \nparameter        STP_UNIT                       = 2'b01 ;  \nparameter        TERMN_CTL_LN0                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN1                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN2                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN3                  = 4'b1000 ;   \nparameter        TERMN_CTL_LNCK                 = 4'b1000 ;   \nparameter        TERMP_CTL_LN0                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN1                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN2                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN3                  = 4'b1000 ;   \nparameter        TERMP_CTL_LNCK                 = 4'b1000 ;   \nparameter        TEST_EN_LN0                    = 1'b0 ;   \nparameter        TEST_EN_LN1                    = 1'b0 ;   \nparameter        TEST_EN_LN2                    = 1'b0 ;   \nparameter        TEST_EN_LN3                    = 1'b0 ;   \nparameter        TEST_EN_LNCK                   = 1'b0 ;   \nparameter        TEST_N_IMP_LN0                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN1                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN2                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN3                 = 1'b0 ;   \nparameter        TEST_N_IMP_LNCK                = 1'b0 ;   \nparameter        TEST_P_IMP_LN0                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN1                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN2                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN3                 = 1'b0 ;   \nparameter        TEST_P_IMP_LNCK                = 1'b0 ;   \nendmodule\n\nmodule MIPI_CPHY (...);\noutput [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD;\noutput D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD;\noutput [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD;\noutput D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR;\noutput [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA;\noutput D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O;   \noutput HSTX_FIFO_AE, HSTX_FIFO_AF;\noutput HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR;\noutput RX_CLK_MUXED;\noutput TX_CLK_1X_O;\noutput DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C;\noutput [7:0] MDRP_RDATA; \ninout  D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C;\ninput  D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN;\ninput  [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA;\ninput  D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD;\ninput  [1:0] D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS;\ninput  D0LN_RX_CLK_1X_I,D1LN_RX_CLK_1X_I, D2LN_RX_CLK_1X_I;\ninput  D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N;\ninput  HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2;\ninput  [7:0] MDRP_A_D_I;\ninput  MDRP_A_INC_I;\ninput  MDRP_CLK_I;\ninput  [1:0] MDRP_OPCODE_I;\ninput  PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX;\ninput  ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; \ninput  ARSTN_TX;\ninput  RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; \ninput  TX_CLK_1X_I;\ninput  TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; \ninput  TXHCLK_EN; \ninput  DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2;\ninput  GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270;\ninput  HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; \ninput  HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2;\ninput  LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; \ninput  SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP;\nparameter TX_PLLCLK = \"NONE\"; \nparameter D0LN_HS_TX_EN = 1'b1; \nparameter D1LN_HS_TX_EN = 1'b1;\nparameter D2LN_HS_TX_EN = 1'b1;\nparameter D0LN_HS_RX_EN = 1'b1; \nparameter D1LN_HS_RX_EN = 1'b1;\nparameter D2LN_HS_RX_EN = 1'b1;\nparameter TX_HS_21BIT_MODE = 1'b0; \nparameter RX_OUTCLK_SEL = 2'b00; \nparameter TX_W_LENDIAN = 1'b1; \nparameter CLK_SEL = 2'b00; \nparameter LNDIV_RATIO = 4'b0000; \nparameter LNDIV_EN = 1'b0; \nparameter D0LN_TX_REASGN_A = 2'b00; \nparameter D0LN_TX_REASGN_B = 2'b01; \nparameter D0LN_TX_REASGN_C = 2'b10; \nparameter D0LN_RX_HS_21BIT_MODE = 1'b0; \nparameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1;  \nparameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  \nparameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  \nparameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1;  \nparameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  \nparameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  \nparameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1;  \nparameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  \nparameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  \nparameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0;  \nparameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  \nparameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  \nparameter D0LN_RX_W_LENDIAN = 1'b1;  \nparameter D0LN_RX_REASGN_A = 2'b00; \nparameter D0LN_RX_REASGN_B = 2'b01; \nparameter D0LN_RX_REASGN_C = 2'b10; \nparameter HSRX_LNSEL = 3'b111; \nparameter EQ_RS_LN0 = 3'b001; \nparameter EQ_CS_LN0 = 3'b101; \nparameter PGA_GAIN_LN0 = 4'b0110; \nparameter PGA_BIAS_LN0 = 4'b1000; \nparameter EQ_PBIAS_LN0 = 4'b0100; \nparameter EQ_ZLD_LN0 = 4'b1000; \nparameter D1LN_TX_REASGN_A = 2'b00; \nparameter D1LN_TX_REASGN_B = 2'b01; \nparameter D1LN_TX_REASGN_C = 2'b10; \nparameter D1LN_RX_HS_21BIT_MODE = 1'b0; \nparameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1;  \nparameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  \nparameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  \nparameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1;  \nparameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  \nparameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  \nparameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1;  \nparameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  \nparameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  \nparameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0;  \nparameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  \nparameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  \nparameter D1LN_RX_W_LENDIAN = 1'b1;  \nparameter D1LN_RX_REASGN_A = 2'b00; \nparameter D1LN_RX_REASGN_B = 2'b01; \nparameter D1LN_RX_REASGN_C = 2'b10; \nparameter EQ_RS_LN1 = 3'b001; \nparameter EQ_CS_LN1 = 3'b101; \nparameter PGA_GAIN_LN1 = 4'b0110; \nparameter PGA_BIAS_LN1 = 4'b1000; \nparameter EQ_PBIAS_LN1 = 4'b0100; \nparameter EQ_ZLD_LN1 = 4'b1000; \nparameter D2LN_TX_REASGN_A = 2'b00; \nparameter D2LN_TX_REASGN_B = 2'b01; \nparameter D2LN_TX_REASGN_C = 2'b10; \nparameter D2LN_RX_HS_21BIT_MODE = 1'b0; \nparameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1;  \nparameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  \nparameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  \nparameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1;  \nparameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  \nparameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  \nparameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1;  \nparameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  \nparameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  \nparameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0;  \nparameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  \nparameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  \nparameter D2LN_RX_W_LENDIAN = 1'b1;  \nparameter D2LN_RX_REASGN_A = 2'b00; \nparameter D2LN_RX_REASGN_B = 2'b01; \nparameter D2LN_RX_REASGN_C = 2'b10; \nparameter EQ_RS_LN2 = 3'b001; \nparameter EQ_CS_LN2 = 3'b101; \nparameter PGA_GAIN_LN2 = 4'b0110; \nparameter PGA_BIAS_LN2 = 4'b1000; \nparameter EQ_PBIAS_LN2 = 4'b0100; \nparameter EQ_ZLD_LN2 = 4'b1000; \nendmodule\n\nmodule GTR12_QUAD (...);\nendmodule\n\nmodule GTR12_UPAR (...);\nendmodule\n\nmodule GTR12_PMAC (...);\nendmodule\n\nmodule GTR12_QUADA (...);\nendmodule\n\nmodule GTR12_UPARA (...);\nendmodule\n\nmodule GTR12_PMACA (...);\nendmodule\n\nmodule GTR12_QUADB (...);\nendmodule\n\nmodule DQS (...);\ninput DQSIN,PCLK,FCLK,RESET;\ninput [3:0] READ;\ninput [2:0] RCLKSEL;\ninput [7:0] DLLSTEP;\ninput [7:0] WSTEP;\ninput RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\noutput DQSR90, DQSW0, DQSW270; \noutput [2:0] RPOINT, WPOINT;\noutput RVALID,RBURST, RFLAG, WFLAG;\nparameter FIFO_MODE_SEL = 1'b0; \nparameter RD_PNTR = 3'b000; \nparameter DQS_MODE = \"X1\"; \nparameter HWL = \"false\";   \nendmodule\n",
+            "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n  assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n  MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n  MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n  MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n  input I0,I1;\n  input S0;\n  output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n  MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (CE)\n      Q <= D;\n  end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else\n      Q <= D;\t\n  end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n  always @(posedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else\n      Q <= D;\n  end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n  always @(posedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n  always @(posedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n  specify\n    (negedge CLK => (Q : D)) = (480, 660);\n    $setup(D, negedge CLK, 576);\n  endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (CE)\n      Q <= D;\n  end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n  \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else\n      Q <= D;\t\n  end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (SET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK) begin\n    if (RESET)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n  always @(negedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else\n      Q <= D;\n  end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n  parameter [0:0] INIT = 1'b1;\n  initial Q = INIT;\n  \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK or posedge PRESET) begin\n    if(PRESET)\n      Q <= 1'b1;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n  always @(negedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else\n      Q <= D;\n  end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n  parameter [0:0] INIT = 1'b0;\n  initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n  always @(negedge CLK or posedge CLEAR) begin\n    if(CLEAR)\n      Q <= 1'b0;\n    else if (CE)\n      Q <= D;\n  end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n  input I, OEN;\n  output O;\n  assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n  input I,OEN;\n  output O;\n  inout IO;\n  assign IO = OEN ? 1'bz : I;\n  assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n  input I;\n  output O;\n  output OB;\n  assign O = I;\n  assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n  input I;\n  output O;\n  output OB;\n  assign O = I;\n  assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET)  ;\n    parameter GSREN = \"\";\n    parameter LSREN = \"\";\n    parameter HWL = \"\";\n    parameter TCLK_SOURCE = \"\";\n    parameter TXCLK_POL = \"\";\n\n    input D0, D1, D2, D3;\n    input TX0, TX1;\n    input PCLK, FCLK, TCLK, RESET;\n    output  Q0,  Q1;\n\n    parameter ID = \"\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR,\nRADDR, CALIB, PCLK, FCLK, ICLK, RESET)  ;\nparameter GSREN = \"\";\nparameter LSREN = \"\";\n\ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput CALIB, RESET;\n\noutput Q0,Q1,Q2,Q3;\n\nparameter ID = \"\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG,\nWFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR,\nHOLD, RCLKSEL, PCLK, FCLK, RESET) ;\n    input DQSIN,PCLK,FCLK,RESET;\n    input [3:0] READ;\n    input [2:0] RCLKSEL;\n    input [7:0] DLLSTEP;\n    input [7:0] WSTEP;\n    input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\n\n    output DQSR90, DQSW0, DQSW270;\n    output [2:0] RPOINT, WPOINT;\n    output RVALID,RBURST, RFLAG, WFLAG;\n\n    parameter FIFO_MODE_SEL = \"\";\n    parameter RD_PNTR = \"\";\n    parameter DQS_MODE = \"\";\n    parameter HWL = \"\";\n    parameter GSREN = \"\";\n    parameter ID = \"\";\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox, keep *)\nmodule GSR (input GSRI);\nendmodule\n\n(* blackbox, keep *)\nmodule BANDGAP (input BGEN);\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0  => COUT) = (1010, 1380);\n\t(I1  => COUT) = (1021, 1505);\n\t(I3  => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = (I0 & I1) ^ I3;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\";         // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\";    // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0;             // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\";   // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0;            // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\";    // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8;             // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";      // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1;     // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1;    // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0;      // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0;     // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\";   // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\";  // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2;         // 2~128, only even numbers\nparameter CLKOUTD_SRC =  \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\";        // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\";         // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\";    // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0;             // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\";   // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0;            // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\";    // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8;             // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";      // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1;     // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1;    // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0;      // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0;     // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\";   // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\";  // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2;         // 2~128, only even numbers\nparameter CLKOUTD_SRC =  \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\";  // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\";       // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nparameter DCS_MODE = \"RISING\";\nendmodule\n\n(* blackbox *)\nmodule EMCU (\n  input          FCLK,\n  input          PORESETN,\n  input          SYSRESETN,\n  input          RTCSRCCLK,\n  output  [15:0] IOEXPOUTPUTO,\n  output  [15:0] IOEXPOUTPUTENO,\n  input   [15:0] IOEXPINPUTI,\n  output         UART0TXDO,\n  output         UART1TXDO,\n  output         UART0BAUDTICK,\n  output         UART1BAUDTICK,\n  input          UART0RXDI,\n  input          UART1RXDI,\n  output         INTMONITOR,\n  output         MTXHRESETN,\n  output  [12:0] SRAM0ADDR,\n  output   [3:0] SRAM0WREN,\n  output  [31:0] SRAM0WDATA,\n  output         SRAM0CS,\n  input   [31:0] SRAM0RDATA,\n  output         TARGFLASH0HSEL,\n  output  [28:0] TARGFLASH0HADDR,\n  output   [1:0] TARGFLASH0HTRANS,\n  output   [2:0] TARGFLASH0HSIZE,\n  output   [2:0] TARGFLASH0HBURST,\n  output         TARGFLASH0HREADYMUX,\n  input   [31:0] TARGFLASH0HRDATA,\n  input    [2:0] TARGFLASH0HRUSER,\n  input          TARGFLASH0HRESP,\n  input          TARGFLASH0EXRESP,\n  input          TARGFLASH0HREADYOUT,\n  output         TARGEXP0HSEL,\n  output  [31:0] TARGEXP0HADDR,\n  output   [1:0] TARGEXP0HTRANS,\n  output         TARGEXP0HWRITE,\n  output   [2:0] TARGEXP0HSIZE,\n  output   [2:0] TARGEXP0HBURST,\n  output   [3:0] TARGEXP0HPROT,\n  output   [1:0] TARGEXP0MEMATTR,\n  output         TARGEXP0EXREQ,\n  output   [3:0] TARGEXP0HMASTER,\n  output  [31:0] TARGEXP0HWDATA,\n  output         TARGEXP0HMASTLOCK,\n  output         TARGEXP0HREADYMUX,\n  output         TARGEXP0HAUSER,\n  output   [3:0] TARGEXP0HWUSER,\n  input   [31:0] TARGEXP0HRDATA,\n  input          TARGEXP0HREADYOUT,\n  input          TARGEXP0HRESP,\n  input          TARGEXP0EXRESP,\n  input    [2:0] TARGEXP0HRUSER,\n  output  [31:0] INITEXP0HRDATA,\n  output         INITEXP0HREADY,\n  output         INITEXP0HRESP,\n  output         INITEXP0EXRESP,\n  output   [2:0] INITEXP0HRUSER,\n  input          INITEXP0HSEL,\n  input   [31:0] INITEXP0HADDR,\n  input    [1:0] INITEXP0HTRANS,\n  input          INITEXP0HWRITE,\n  input    [2:0] INITEXP0HSIZE,\n  input    [2:0] INITEXP0HBURST,\n  input    [3:0] INITEXP0HPROT,\n  input    [1:0] INITEXP0MEMATTR,\n  input          INITEXP0EXREQ,\n  input    [3:0] INITEXP0HMASTER,\n  input   [31:0] INITEXP0HWDATA,\n  input          INITEXP0HMASTLOCK,\n  input          INITEXP0HAUSER,\n  input    [3:0] INITEXP0HWUSER,\n  output   [3:0] APBTARGEXP2PSTRB,\n  output   [2:0] APBTARGEXP2PPROT,\n  output         APBTARGEXP2PSEL,\n  output         APBTARGEXP2PENABLE,\n  output  [11:0] APBTARGEXP2PADDR,\n  output         APBTARGEXP2PWRITE,\n  output  [31:0] APBTARGEXP2PWDATA,\n  input   [31:0] APBTARGEXP2PRDATA,\n  input          APBTARGEXP2PREADY,\n  input          APBTARGEXP2PSLVERR,\n  input    [3:0] MTXREMAP,\n  output         DAPTDO,\n  output         DAPJTAGNSW,\n  output         DAPNTDOEN,\n  input          DAPSWDITMS,\n  input          DAPTDI,\n  input          DAPNTRST,\n  input          DAPSWCLKTCK,\n  output   [3:0] TPIUTRACEDATA,\n  output         TPIUTRACECLK,\n  input    [4:0] GPINT,\n  input          FLASHERR,\n  input          FLASHINT\n\n );\nendmodule\n\n\n",
+            "cells_xtra_gw1n.v": "// Created by cells_xtra.py\n\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule INV (...);\ninput  I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput  [17:0] A;\ninput  [17:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput  [8:0] A;\ninput  [8:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput  [8:0] A,SIA;\ninput  [8:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput  [17:0] A,SIA;\ninput  [17:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput  [35:0] A;\ninput  [35:0] B;\ninput  ASIGN,BSIGN;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput  [17:0] A;\ninput  [35:0] B;\ninput  [53:0] C;\ninput  ASIGN,BSIGN,ACCLOAD;\ninput  CE;\ninput  CLK;\ninput  RESET;\ninput  [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\";  \nparameter CLKOUTP_BYPASS = \"false\";   \nparameter CLKOUTD_BYPASS = \"false\";  \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC =  \"CLKOUT\";  \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput  I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput  I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput  I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput  I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput  I, IB, IL, MODESEL;\nendmodule\n\nmodule ELVDS_IBUF_MIPI (...);\noutput OH, OL;\ninput  I, IB;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput  I, MODESEL;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n\t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\t\t  \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n   \t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n\t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\t\t  \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE    =  4'd0,\n          ERA_S1  =  4'd1,\n\t\t  ERA_S2  =  4'd2,\n\t\t  ERA_S3  =  4'd3,\n\t\t  ERA_S4  =  4'd4,\n\t\t  ERA_S5  =  4'd5,\n\t\t  PRO_S1  =  4'd6,\n\t\t  PRO_S2  =  4'd7,\n\t\t  PRO_S3  =  4'd8,\n\t\t  PRO_S4  =  4'd9,\n\t\t  PRO_S5  =  4'd10,\n\t\t  RD_S1   =  4'd11,\n\t\t  RD_S2   =  4'd12;\t\t  \nendmodule\n",
+            "cells_xtra_gw2a.v": "// Created by cells_xtra.py\n\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule INV (...);\ninput  I;\noutput O;\nendmodule\n\n\nmodule IDDR_MEM (...);\nparameter GSREN = \"false\";  \nparameter LSREN = \"true\";    \ninput D, ICLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET;\noutput  Q0,Q1;\nendmodule\n\n\nmodule ODDR_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1;\ninput TX, PCLK, TCLK, RESET;\noutput  Q0, Q1;\nendmodule\n\n\nmodule IDES4_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET,CALIB;\noutput Q0,Q1,Q2,Q3;\nendmodule\n\n\nmodule IDES8_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET,CALIB;\noutput  Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7;\nendmodule\n\n\nmodule OSER4_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \nparameter HWL = \"false\";     \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3;\ninput TX0, TX1;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule OSER8_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \nparameter HWL = \"false\";    \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3, D4, D5, D6, D7;\ninput TX0, TX1, TX2, TX3;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput  SDTAP;\ninput  SETN;\ninput  VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\";    \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput  [17:0] A;\ninput  [17:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput  [8:0] A;\ninput  [8:0] B;\ninput  ASEL;\ninput  CE,CLK,RESET;\ninput  [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput  [8:0] A,SIA;\ninput  [8:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput  [17:0] A,SIA;\ninput  [17:0] B,SIB;\ninput  ASIGN,BSIGN;\ninput  ASEL,BSEL;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput  [35:0] A;\ninput  [35:0] B;\ninput  ASIGN,BSIGN;\ninput  CE;\ninput  CLK;\ninput  RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput  [17:0] A;\ninput  [35:0] B;\ninput  [53:0] C;\ninput  ASIGN,BSIGN,ACCLOAD;\ninput  CE;\ninput  CLK;\ninput  RESET;\ninput  [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\";  \nparameter CLKOUTP_BYPASS = \"false\";   \nparameter CLKOUTD_BYPASS = \"false\";  \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC =  \"CLKOUT\";  \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW2A-18\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DQS (...);\ninput DQSIN,PCLK,FCLK,RESET;\ninput [3:0] READ;\ninput [2:0] RCLKSEL;\ninput [7:0] DLLSTEP;\ninput [7:0] WSTEP;\ninput RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\noutput DQSR90, DQSW0, DQSW270; \noutput [2:0] RPOINT, WPOINT;\noutput RVALID,RBURST, RFLAG, WFLAG;\nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule IBUF_R (...);\ninput  I;\ninput RTEN;\noutput O;\nendmodule\n\nmodule IOBUF_R (...);\ninput I,OEN;\ninput RTEN;\noutput O;\ninout IO;\nendmodule\n\nmodule ELVDS_IBUF_R (...);\noutput O;\ninput I, IB;\ninput RTEN;\nendmodule\n\nmodule ELVDS_IOBUF_R (...);\noutput  O;\ninout IO, IOB;\ninput I, OEN;\ninput RTEN;\nendmodule\n\nmodule OTP (...);\ninput CSB, SCLK;\noutput DOUT;\nendmodule\n\nmodule SAMB (...);\ninput [23:0] SPIAD;\ninput LOADN_SPIAD;\nendmodule\n\nmodule ELVDS_IBUF_MIPI (...);\noutput OH, OL;\ninput  I, IB;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput  I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput  I, MODESEL;\nendmodule\n",
+            "cells_xtra_gw5a.v": "// Created by cells_xtra.py\n\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule INV (...);\ninput  I;\noutput O;\nendmodule\n\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput  I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput  I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput   O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput  I, IB;\ninput OEN, OENB;\ninput HSEN, HSREN;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput  I, IB, IL, MODESEL;\nendmodule\n\nmodule IBUF_R (...);\ninput  I;\ninput RTEN;\noutput O;\nendmodule\n\nmodule IOBUF_R (...);\ninput I,OEN;\ninput RTEN;\noutput O;\ninout IO;\nendmodule\n\nmodule ELVDS_IOBUF_R (...);\noutput  O;\ninout IO, IOB;\ninput I, OEN;\ninput RTEN;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput  I, MODESEL;\nendmodule\n\nmodule TLVDS_IBUF_ADC (...);\ninput I, IB;\ninput ADCEN;\nendmodule\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDP36KE (...);\nparameter ECC_WRITE_EN=\"FALSE\"; \nparameter ECC_READ_EN=\"FALSE\"; \nparameter READ_MODE = 1'b0; \nparameter BLK_SEL_A = 3'b000;\nparameter BLK_SEL_B = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_FILE = \"NONE\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [8:0] ADA, ADB;\ninput [63:0] DI;\ninput [7:0] DIP;\ninput [2:0] BLKSELA, BLKSELB;\ninput DECCI, SECCI;\noutput [63:0] DO;\noutput [7:0] DOP;\noutput DECCO, SECCO;\noutput [7:0] ECCP;\nendmodule\n\n\nmodule MULTADDALU12X12 (...);\nparameter A0REG_CLK = \"BYPASS\"; \nparameter A0REG_CE = \"CE0\"; \nparameter A0REG_RESET = \"RESET0\"; \nparameter A1REG_CLK = \"BYPASS\"; \nparameter A1REG_CE = \"CE0\"; \nparameter A1REG_RESET = \"RESET0\"; \nparameter B0REG_CLK = \"BYPASS\"; \nparameter B0REG_CE = \"CE0\"; \nparameter B0REG_RESET = \"RESET0\"; \nparameter B1REG_CLK = \"BYPASS\"; \nparameter B1REG_CE = \"CE0\"; \nparameter B1REG_RESET = \"RESET0\"; \nparameter ACCSEL_IREG_CLK = \"BYPASS\"; \nparameter ACCSEL_IREG_CE = \"CE0\"; \nparameter ACCSEL_IREG_RESET = \"RESET0\"; \nparameter CASISEL_IREG_CLK = \"BYPASS\"; \nparameter CASISEL_IREG_CE = \"CE0\"; \nparameter CASISEL_IREG_RESET = \"RESET0\"; \nparameter ADDSUB0_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_IREG_CE = \"CE0\"; \nparameter ADDSUB0_IREG_RESET = \"RESET0\"; \nparameter ADDSUB1_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_IREG_CE = \"CE0\"; \nparameter ADDSUB1_IREG_RESET = \"RESET0\"; \nparameter PREG0_CLK = \"BYPASS\"; \nparameter PREG0_CE = \"CE0\"; \nparameter PREG0_RESET = \"RESET0\"; \nparameter PREG1_CLK = \"BYPASS\"; \nparameter PREG1_CE = \"CE0\"; \nparameter PREG1_RESET = \"RESET0\"; \nparameter FB_PREG_EN = \"FALSE\"; \nparameter ACCSEL_PREG_CLK = \"BYPASS\"; \nparameter ACCSEL_PREG_CE = \"CE0\"; \nparameter ACCSEL_PREG_RESET = \"RESET0\"; \nparameter CASISEL_PREG_CLK = \"BYPASS\"; \nparameter CASISEL_PREG_CE = \"CE0\"; \nparameter CASISEL_PREG_RESET = \"RESET0\"; \nparameter ADDSUB0_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_PREG_CE = \"CE0\"; \nparameter ADDSUB0_PREG_RESET = \"RESET0\"; \nparameter ADDSUB1_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_PREG_CE = \"CE0\"; \nparameter ADDSUB1_PREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter PRE_LOAD = 48'h000000000000;\nparameter DYN_ADD_SUB_0 = \"FALSE\";\nparameter ADD_SUB_0 = 1'b0;\nparameter DYN_ADD_SUB_1 = \"FALSE\";\nparameter ADD_SUB_1 = 1'b0;\nparameter DYN_CASI_SEL = \"FALSE\";\nparameter CASI_SEL = 1'b0;\nparameter DYN_ACC_SEL = \"FALSE\";\nparameter ACC_SEL = 1'b0;\noutput [47:0] DOUT, CASO;\ninput  [11:0] A0, B0, A1, B1;\ninput  [47:0] CASI;\ninput  ACCSEL;\ninput  CASISEL;\ninput  [1:0] ADDSUB;\ninput  [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULTALU27X18 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter DREG_CLK = \"BYPASS\"; \nparameter DREG_CE = \"CE0\"; \nparameter DREG_RESET = \"RESET0\"; \nparameter C_IREG_CLK = \"BYPASS\"; \nparameter C_IREG_CE = \"CE0\"; \nparameter C_IREG_RESET = \"RESET0\"; \nparameter PSEL_IREG_CLK = \"BYPASS\"; \nparameter PSEL_IREG_CE = \"CE0\"; \nparameter PSEL_IREG_RESET = \"RESET0\"; \nparameter PADDSUB_IREG_CLK = \"BYPASS\"; \nparameter PADDSUB_IREG_CE = \"CE0\"; \nparameter PADDSUB_IREG_RESET = \"RESET0\"; \nparameter ADDSUB0_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_IREG_CE = \"CE0\"; \nparameter ADDSUB0_IREG_RESET = \"RESET0\"; \nparameter ADDSUB1_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_IREG_CE = \"CE0\"; \nparameter ADDSUB1_IREG_RESET = \"RESET0\"; \nparameter CSEL_IREG_CLK = \"BYPASS\"; \nparameter CSEL_IREG_CE = \"CE0\"; \nparameter CSEL_IREG_RESET = \"RESET0\"; \nparameter CASISEL_IREG_CLK = \"BYPASS\"; \nparameter CASISEL_IREG_CE = \"CE0\"; \nparameter CASISEL_IREG_RESET = \"RESET0\"; \nparameter ACCSEL_IREG_CLK = \"BYPASS\"; \nparameter ACCSEL_IREG_CE = \"CE0\"; \nparameter ACCSEL_IREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter ADDSUB0_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_PREG_CE = \"CE0\"; \nparameter ADDSUB0_PREG_RESET = \"RESET0\"; \nparameter ADDSUB1_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_PREG_CE = \"CE0\"; \nparameter ADDSUB1_PREG_RESET = \"RESET0\"; \nparameter CSEL_PREG_CLK = \"BYPASS\"; \nparameter CSEL_PREG_CE = \"CE0\"; \nparameter CSEL_PREG_RESET = \"RESET0\"; \nparameter CASISEL_PREG_CLK = \"BYPASS\"; \nparameter CASISEL_PREG_CE = \"CE0\"; \nparameter CASISEL_PREG_RESET = \"RESET0\"; \nparameter ACCSEL_PREG_CLK = \"BYPASS\"; \nparameter ACCSEL_PREG_CE = \"CE0\"; \nparameter ACCSEL_PREG_RESET = \"RESET0\"; \nparameter C_PREG_CLK = \"BYPASS\"; \nparameter C_PREG_CE = \"CE0\"; \nparameter C_PREG_RESET = \"RESET0\"; \nparameter FB_PREG_EN = \"FALSE\"; \nparameter SOA_PREG_EN = \"FALSE\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter PRE_LOAD = 48'h000000000000;\nparameter DYN_P_SEL = \"FALSE\";\nparameter P_SEL = 1'b0;\nparameter DYN_P_ADDSUB = \"FALSE\";\nparameter P_ADDSUB = 1'b0;\nparameter DYN_A_SEL = \"FALSE\";\nparameter A_SEL = 1'b0;\nparameter DYN_ADD_SUB_0 = \"FALSE\";\nparameter ADD_SUB_0 = 1'b0;\nparameter DYN_ADD_SUB_1 = \"FALSE\";\nparameter ADD_SUB_1 = 1'b0;\nparameter DYN_C_SEL = \"FALSE\";\nparameter C_SEL = 1'b1;\nparameter DYN_CASI_SEL = \"FALSE\";\nparameter CASI_SEL = 1'b0;\nparameter DYN_ACC_SEL = \"FALSE\";\nparameter ACC_SEL = 1'b0;\nparameter MULT12X12_EN = \"FALSE\";\noutput [47:0] DOUT, CASO;\noutput [26:0] SOA;\ninput  [26:0] A, SIA;\ninput  [17:0] B;\ninput  [47:0] C;\ninput  [25:0] D;\ninput  [47:0] CASI;\ninput  ACCSEL;\ninput  PSEL;\ninput  ASEL;\ninput  PADDSUB;\ninput  CSEL, CASISEL;\ninput  [1:0] ADDSUB;\ninput  [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULT12X12 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\noutput [23:0] DOUT;\ninput  [11:0] A, B;\ninput  [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULT27X36 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter DREG_CLK = \"BYPASS\"; \nparameter DREG_CE = \"CE0\"; \nparameter DREG_RESET = \"RESET0\"; \nparameter PADDSUB_IREG_CLK = \"BYPASS\"; \nparameter PADDSUB_IREG_CE = \"CE0\"; \nparameter PADDSUB_IREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter PSEL_IREG_CLK = \"BYPASS\"; \nparameter PSEL_IREG_CE = \"CE0\"; \nparameter PSEL_IREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter DYN_P_SEL = \"FALSE\";\nparameter P_SEL = 1'b0;\nparameter DYN_P_ADDSUB = \"FALSE\";\nparameter P_ADDSUB = 1'b0;\noutput [62:0] DOUT;\ninput  [26:0] A;\ninput  [35:0] B;\ninput  [25:0] D;\ninput  [1:0] CLK, CE, RESET;\ninput  PSEL;\ninput  PADDSUB;\nendmodule\n\nmodule IDDR_MEM (...);\ninput D, ICLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET;\noutput  Q0,Q1;\nendmodule\n\n\nmodule ODDR_MEM (...);\nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1;\ninput TX, PCLK, TCLK, RESET;\noutput  Q0, Q1;\nendmodule\n\n\nmodule IDES4_MEM (...);\ninput PCLK, D, ICLK, FCLK, RESET, CALIB;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\noutput Q0,Q1,Q2,Q3;\nendmodule\n\n\nmodule IDES8_MEM (...);\ninput PCLK, D, ICLK, FCLK, RESET, CALIB;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\noutput Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;\nendmodule\n\n\nmodule IDES14 (...);\ninput D, FCLK, PCLK, CALIB,RESET;\noutput Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13;\nendmodule\n\n\nmodule IDES32 (...);\ninput D, FCLK, PCLK, CALIB,RESET;\noutput Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31;\nendmodule\n\n\nmodule OSER4_MEM (...);\nparameter HWL = \"false\";     \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3;\ninput TX0, TX1;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule OSER8_MEM (...);\nparameter HWL = \"false\";    \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3, D4, D5, D6, D7;\ninput TX0, TX1, TX2, TX3;\ninput PCLK, FCLK, TCLK, RESET;\noutput  Q0,  Q1;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DLY_EN = \"FALSE\";\nparameter ADAPT_EN = \"FALSE\";\ninput  DI;\ninput  SDTAP;\ninput  VALUE;\ninput  [7:0] DLYSTEP;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule OSIDES32 (...);\noutput [31:0] Q;\ninput D;\ninput PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;\ninput RESET;\noutput DF;\ninput  SDTAP;\ninput  VALUE;\ninput  [7:0] DLYSTEP;\nparameter C_STATIC_DLY = 0; \nparameter DYN_DLY_EN = \"FALSE\";\nparameter ADAPT_EN = \"FALSE\";\nendmodule\n\nmodule DCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule DDRDLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = \"FALSE\";\nparameter CODESCAL = \"000\";\nparameter SCAL_EN = \"TRUE\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP, CSTEP;\ninput LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nparameter DYN_DLY_EN = \"FALSE\";\nparameter ADAPT_EN = \"FALSE\";\nparameter STEP_SEL = 1'b0;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nendmodule\n\nmodule CLKDIV2 (...);\ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DHCE (...);\ninput CLKIN;\ninput CEN;\noutput CLKOUT;\nendmodule\n\nmodule OSCA (...);\nparameter  FREQ_DIV = 100; \noutput OSCOUT;\ninput OSCEN;\nendmodule\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput PLLPWD;\ninput RESET_I;\ninput RESET_O;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] MDSEL;\ninput [2:0] MDSEL_FRAC;\ninput [6:0] ODSEL0;\ninput [2:0] ODSEL0_FRAC;\ninput [6:0] ODSEL1;\ninput [6:0] ODSEL2;\ninput [6:0] ODSEL3;\ninput [6:0] ODSEL4;\ninput [6:0] ODSEL5;\ninput [6:0] ODSEL6;\ninput [3:0] DT0,DT1,DT2,DT3;\ninput [5:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] LPFCAP;\ninput [2:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLK0;\ninput ENCLK1;\ninput ENCLK2;\ninput ENCLK3;\ninput ENCLK4;\ninput ENCLK5;\ninput ENCLK6;\ninput SSCPOL;\ninput SSCON;\ninput [6:0] SSCMDSEL;\ninput [2:0] SSCMDSEL_FRAC;\noutput LOCK;\noutput CLKOUT0;\noutput CLKOUT1;\noutput CLKOUT2;\noutput CLKOUT3;\noutput CLKOUT4;\noutput CLKOUT5;\noutput CLKOUT6;\noutput CLKFBOUT;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 1; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 1; \nparameter DYN_ODIV0_SEL= \"FALSE\";\nparameter ODIV0_SEL = 8; \nparameter DYN_ODIV1_SEL= \"FALSE\";\nparameter ODIV1_SEL = 8; \nparameter DYN_ODIV2_SEL= \"FALSE\";\nparameter ODIV2_SEL = 8; \nparameter DYN_ODIV3_SEL= \"FALSE\";\nparameter ODIV3_SEL = 8; \nparameter DYN_ODIV4_SEL= \"FALSE\";\nparameter ODIV4_SEL = 8; \nparameter DYN_ODIV5_SEL= \"FALSE\";\nparameter ODIV5_SEL = 8; \nparameter DYN_ODIV6_SEL= \"FALSE\";\nparameter ODIV6_SEL = 8; \nparameter DYN_MDIV_SEL= \"FALSE\";\nparameter MDIV_SEL = 8; \nparameter MDIV_FRAC_SEL = 0; \nparameter ODIV0_FRAC_SEL = 0; \nparameter CLKOUT0_EN = \"TRUE\";\nparameter CLKOUT1_EN = \"FALSE\";\nparameter CLKOUT2_EN = \"FALSE\";\nparameter CLKOUT3_EN = \"FALSE\";\nparameter CLKOUT4_EN = \"FALSE\";\nparameter CLKOUT5_EN = \"FALSE\";\nparameter CLKOUT6_EN = \"FALSE\";\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DT0_SEL = \"FALSE\"; \nparameter DYN_DT1_SEL = \"FALSE\"; \nparameter DYN_DT2_SEL = \"FALSE\"; \nparameter DYN_DT3_SEL = \"FALSE\"; \nparameter CLKOUT0_DT_DIR = 1'b1; \nparameter CLKOUT1_DT_DIR = 1'b1; \nparameter CLKOUT2_DT_DIR = 1'b1; \nparameter CLKOUT3_DT_DIR = 1'b1; \nparameter CLKOUT0_DT_STEP = 0; \nparameter CLKOUT1_DT_STEP = 0; \nparameter CLKOUT2_DT_STEP = 0; \nparameter CLKOUT3_DT_STEP = 0; \nparameter CLK0_IN_SEL = 1'b0;\nparameter CLK0_OUT_SEL = 1'b0;\nparameter CLK1_IN_SEL = 1'b0;\nparameter CLK1_OUT_SEL = 1'b0;\nparameter CLK2_IN_SEL = 1'b0;\nparameter CLK2_OUT_SEL = 1'b0;\nparameter CLK3_IN_SEL = 1'b0;\nparameter CLK3_OUT_SEL = 1'b0;\nparameter CLK4_IN_SEL = 2'b00;\nparameter CLK4_OUT_SEL = 1'b0;\nparameter CLK5_IN_SEL = 1'b0;\nparameter CLK5_OUT_SEL = 1'b0;\nparameter CLK6_IN_SEL = 1'b0;\nparameter CLK6_OUT_SEL = 1'b0;\nparameter DYN_DPA_EN = \"FALSE\";\nparameter CLKOUT0_PE_COARSE = 0;\nparameter CLKOUT0_PE_FINE = 0;\nparameter CLKOUT1_PE_COARSE = 0;\nparameter CLKOUT1_PE_FINE = 0;\nparameter CLKOUT2_PE_COARSE = 0;\nparameter CLKOUT2_PE_FINE = 0;\nparameter CLKOUT3_PE_COARSE = 0;\nparameter CLKOUT3_PE_FINE = 0;\nparameter CLKOUT4_PE_COARSE = 0;\nparameter CLKOUT4_PE_FINE = 0;\nparameter CLKOUT5_PE_COARSE = 0;\nparameter CLKOUT5_PE_FINE = 0;\nparameter CLKOUT6_PE_COARSE = 0;\nparameter CLKOUT6_PE_FINE = 0;\nparameter DYN_PE0_SEL = \"FALSE\";\nparameter DYN_PE1_SEL = \"FALSE\";\nparameter DYN_PE2_SEL = \"FALSE\";\nparameter DYN_PE3_SEL = \"FALSE\";\nparameter DYN_PE4_SEL = \"FALSE\";\nparameter DYN_PE5_SEL = \"FALSE\";\nparameter DYN_PE6_SEL = \"FALSE\";\nparameter DE0_EN = \"FALSE\";\nparameter DE1_EN = \"FALSE\";\nparameter DE2_EN = \"FALSE\";\nparameter DE3_EN = \"FALSE\";\nparameter DE4_EN = \"FALSE\";\nparameter DE5_EN = \"FALSE\";\nparameter DE6_EN = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_O_EN =  \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 6'bXXXXXX;\nparameter DYN_LPF_SEL= \"FALSE\";\nparameter LPF_RES = 3'bXXX;\nparameter LPF_CAP = 2'b00;\nparameter SSC_EN = \"FALSE\";\nendmodule\n\nmodule PLLA (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput PLLPWD;\ninput RESET_I;\ninput RESET_O;\ninput [2:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput SSCPOL;\ninput SSCON;\ninput [6:0] SSCMDSEL;\ninput [2:0] SSCMDSEL_FRAC;\ninput MDCLK;\ninput [1:0] MDOPC;\ninput MDAINC;\ninput [7:0] MDWDI;\noutput [7:0] MDRDO;\noutput LOCK;\noutput CLKOUT0;\noutput CLKOUT1;\noutput CLKOUT2;\noutput CLKOUT3;\noutput CLKOUT4;\noutput CLKOUT5;\noutput CLKOUT6;\noutput CLKFBOUT;\nparameter FCLKIN = \"100.0\"; \nparameter IDIV_SEL = 1; \nparameter FBDIV_SEL = 1; \nparameter ODIV0_SEL = 8; \nparameter ODIV1_SEL = 8; \nparameter ODIV2_SEL = 8; \nparameter ODIV3_SEL = 8; \nparameter ODIV4_SEL = 8; \nparameter ODIV5_SEL = 8; \nparameter ODIV6_SEL = 8; \nparameter MDIV_SEL = 8; \nparameter MDIV_FRAC_SEL = 0; \nparameter ODIV0_FRAC_SEL = 0; \nparameter CLKOUT0_EN = \"TRUE\";\nparameter CLKOUT1_EN = \"FALSE\";\nparameter CLKOUT2_EN = \"FALSE\";\nparameter CLKOUT3_EN = \"FALSE\";\nparameter CLKOUT4_EN = \"FALSE\";\nparameter CLKOUT5_EN = \"FALSE\";\nparameter CLKOUT6_EN = \"FALSE\";\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter CLKOUT0_DT_DIR = 1'b1; \nparameter CLKOUT1_DT_DIR = 1'b1; \nparameter CLKOUT2_DT_DIR = 1'b1; \nparameter CLKOUT3_DT_DIR = 1'b1; \nparameter CLKOUT0_DT_STEP = 0; \nparameter CLKOUT1_DT_STEP = 0; \nparameter CLKOUT2_DT_STEP = 0; \nparameter CLKOUT3_DT_STEP = 0; \nparameter CLK0_IN_SEL = 1'b0;\nparameter CLK0_OUT_SEL = 1'b0;\nparameter CLK1_IN_SEL = 1'b0;\nparameter CLK1_OUT_SEL = 1'b0;\nparameter CLK2_IN_SEL = 1'b0;\nparameter CLK2_OUT_SEL = 1'b0;\nparameter CLK3_IN_SEL = 1'b0;\nparameter CLK3_OUT_SEL = 1'b0;\nparameter CLK4_IN_SEL = 2'b00;\nparameter CLK4_OUT_SEL = 1'b0;\nparameter CLK5_IN_SEL = 1'b0;\nparameter CLK5_OUT_SEL = 1'b0;\nparameter CLK6_IN_SEL = 1'b0;\nparameter CLK6_OUT_SEL = 1'b0;\nparameter DYN_DPA_EN = \"FALSE\";\nparameter CLKOUT0_PE_COARSE = 0;\nparameter CLKOUT0_PE_FINE = 0;\nparameter CLKOUT1_PE_COARSE = 0;\nparameter CLKOUT1_PE_FINE = 0;\nparameter CLKOUT2_PE_COARSE = 0;\nparameter CLKOUT2_PE_FINE = 0;\nparameter CLKOUT3_PE_COARSE = 0;\nparameter CLKOUT3_PE_FINE = 0;\nparameter CLKOUT4_PE_COARSE = 0;\nparameter CLKOUT4_PE_FINE = 0;\nparameter CLKOUT5_PE_COARSE = 0;\nparameter CLKOUT5_PE_FINE = 0;\nparameter CLKOUT6_PE_COARSE = 0;\nparameter CLKOUT6_PE_FINE = 0;\nparameter DYN_PE0_SEL = \"FALSE\";\nparameter DYN_PE1_SEL = \"FALSE\";\nparameter DYN_PE2_SEL = \"FALSE\";\nparameter DYN_PE3_SEL = \"FALSE\";\nparameter DYN_PE4_SEL = \"FALSE\";\nparameter DYN_PE5_SEL = \"FALSE\";\nparameter DYN_PE6_SEL = \"FALSE\";\nparameter DE0_EN = \"FALSE\";\nparameter DE1_EN = \"FALSE\";\nparameter DE2_EN = \"FALSE\";\nparameter DE3_EN = \"FALSE\";\nparameter DE4_EN = \"FALSE\";\nparameter DE5_EN = \"FALSE\";\nparameter DE6_EN = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_O_EN =  \"FALSE\";\nparameter ICP_SEL = 6'bXXXXXX;\nparameter LPF_RES = 3'bXXX;\nparameter LPF_CAP = 2'b00;\nparameter SSC_EN = \"FALSE\";\nendmodule\n\nmodule AE350_SOC (...);\ninput               POR_N;\ninput               HW_RSTN;\ninput               CORE_CLK;\ninput               DDR_CLK;\ninput               AHB_CLK;\ninput               APB_CLK;\ninput               DBG_TCK;\ninput               RTC_CLK;\ninput               CORE_CE;\ninput               AXI_CE;\ninput               DDR_CE;\ninput               AHB_CE;\ninput     [7:0]     APB_CE;\ninput               APB2AHB_CE;\ninput               SCAN_TEST;\ninput               SCAN_EN;\noutput              PRESETN;\noutput              HRESETN;\noutput              DDR_RSTN;\ninput       [15:0]  GP_INT;\ninput       [ 7:0]  DMA_REQ;\noutput      [ 7:0]  DMA_ACK;\noutput              CORE0_WFI_MODE;\ninput               WAKEUP_IN;           \noutput              RTC_WAKEUP;           \ninput               TEST_CLK;\ninput               TEST_MODE;\ninput               TEST_RSTN;\noutput  [31:0]      ROM_HADDR;\ninput   [31:0]      ROM_HRDATA;\ninput               ROM_HREADY;\ninput               ROM_HRESP;\noutput   [1:0]      ROM_HTRANS;\noutput              ROM_HWRITE;\noutput  [31:0]      APB_PADDR;\noutput              APB_PENABLE;\ninput   [31:0]      APB_PRDATA;\ninput               APB_PREADY;\noutput              APB_PSEL;\noutput  [31:0]      APB_PWDATA;\noutput              APB_PWRITE;\ninput               APB_PSLVERR;\noutput   [2:0]      APB_PPROT;\noutput   [3:0]      APB_PSTRB;\ninput   [31:0]      EXTS_HRDATA;\ninput               EXTS_HREADYIN;\ninput               EXTS_HRESP;\noutput  [31:0]      EXTS_HADDR;\noutput   [2:0]      EXTS_HBURST;\noutput   [3:0]      EXTS_HPROT;\noutput              EXTS_HSEL;\noutput   [2:0]      EXTS_HSIZE;\noutput   [1:0]      EXTS_HTRANS;\noutput  [31:0]      EXTS_HWDATA;\noutput              EXTS_HWRITE;\ninput   [31:0]      EXTM_HADDR;\ninput    [2:0]      EXTM_HBURST;\ninput    [3:0]      EXTM_HPROT;\noutput  [63:0]      EXTM_HRDATA;\ninput               EXTM_HREADY;\noutput              EXTM_HREADYOUT;\noutput              EXTM_HRESP;\ninput               EXTM_HSEL;\ninput    [2:0]      EXTM_HSIZE;\ninput    [1:0]      EXTM_HTRANS;\ninput   [63:0]      EXTM_HWDATA;\ninput               EXTM_HWRITE;\noutput  [31:0]      DDR_HADDR;\noutput   [2:0]      DDR_HBURST;\noutput   [3:0]      DDR_HPROT;\ninput   [63:0]      DDR_HRDATA;\ninput               DDR_HREADY;\ninput               DDR_HRESP;\noutput   [2:0]      DDR_HSIZE;\noutput   [1:0]      DDR_HTRANS;\noutput  [63:0]      DDR_HWDATA;\noutput              DDR_HWRITE;\ninput               TMS_IN;           \ninput               TRST_IN;\ninput               TDI_IN;\noutput              TDO_OUT;\noutput              TDO_OE;\ninput               SPI2_HOLDN_IN;\ninput               SPI2_WPN_IN;\ninput               SPI2_CLK_IN;\ninput               SPI2_CSN_IN;\ninput               SPI2_MISO_IN;\ninput               SPI2_MOSI_IN;\noutput              SPI2_HOLDN_OUT;\noutput              SPI2_HOLDN_OE;\noutput              SPI2_WPN_OUT;\noutput              SPI2_WPN_OE;\noutput              SPI2_CLK_OUT;\noutput              SPI2_CLK_OE;\noutput              SPI2_CSN_OUT;\noutput              SPI2_CSN_OE;\noutput              SPI2_MISO_OUT;\noutput              SPI2_MISO_OE;\noutput              SPI2_MOSI_OUT;\noutput              SPI2_MOSI_OE;\ninput               I2C_SCL_IN;\ninput               I2C_SDA_IN;\noutput              I2C_SCL;\noutput              I2C_SDA;\noutput              UART1_TXD;\noutput              UART1_RTSN;\ninput               UART1_RXD;\ninput               UART1_CTSN;\ninput               UART1_DSRN;\ninput               UART1_DCDN;\ninput               UART1_RIN;\noutput              UART1_DTRN;\noutput              UART1_OUT1N;\noutput              UART1_OUT2N;\noutput              UART2_TXD;\noutput              UART2_RTSN;\ninput               UART2_RXD;\ninput               UART2_CTSN;\ninput               UART2_DCDN;\ninput               UART2_DSRN;\ninput               UART2_RIN;\noutput              UART2_DTRN;\noutput              UART2_OUT1N;\noutput              UART2_OUT2N;\noutput              CH0_PWM;\noutput              CH0_PWMOE;\noutput              CH1_PWM;\noutput              CH1_PWMOE;\noutput              CH2_PWM;\noutput              CH2_PWMOE;\noutput              CH3_PWM;\noutput              CH3_PWMOE;\ninput     [31:0]    GPIO_IN;\noutput    [31:0]    GPIO_OE;\noutput    [31:0]    GPIO_OUT;\ninput\t [19:0]\tSCAN_IN;\ninput\t\tINTEG_TCK;\ninput\t\tINTEG_TDI;\ninput\t\tINTEG_TMS;\ninput\t\tINTEG_TRST;\noutput\t\tINTEG_TDO;\noutput   [19:0]\tSCAN_OUT;\ninput\t\tPGEN_CHAIN_I;\noutput\t\tPRDYN_CHAIN_O;\ninput\t[2:0]\tEMA;\ninput\t[1:0]\tEMAW;\ninput\t\tEMAS;\ninput\t\tRET1N;\ninput\t\tRET2N;\nendmodule\n\nmodule AE350_RAM (...);\ninput               POR_N;\ninput               HW_RSTN;\ninput               CORE_CLK;\ninput               AHB_CLK;\ninput               APB_CLK;\ninput               RTC_CLK;\ninput               CORE_CE;\ninput               AXI_CE;\ninput               AHB_CE;\ninput   [31:0]      EXTM_HADDR;\ninput    [2:0]      EXTM_HBURST;\ninput    [3:0]      EXTM_HPROT;\noutput  [63:0]      EXTM_HRDATA;\ninput               EXTM_HREADY;\noutput              EXTM_HREADYOUT;\noutput              EXTM_HRESP;\ninput               EXTM_HSEL;\ninput    [2:0]      EXTM_HSIZE;\ninput    [1:0]      EXTM_HTRANS;\ninput   [63:0]      EXTM_HWDATA;\ninput               EXTM_HWRITE;\ninput\t[2:0]\tEMA;\ninput\t[1:0]\tEMAW;\ninput\t\tEMAS;\ninput\t\tRET1N;\ninput\t\tRET2N;\nendmodule\n\nmodule SAMB (...);\nparameter MODE = 2'b00; \ninput [23:0] SPIAD;\ninput LOAD;\ninput ADWSEL; \nendmodule\n\nmodule OTP (...);\nparameter MODE = 1'b0; \ninput READ, SHIFT;\noutput DOUT;\nendmodule\n\nmodule CMSER (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [27:0] ERRLOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERRINJECT;\ninput [6:0] ERRINJLOC;\nendmodule\n\nmodule CMSERA (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [26:0] ERR0LOC;\noutput [26:0] ERR1LOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERR0INJECT,ERR1INJECT;\ninput [6:0] ERRINJ0LOC,ERRINJ1LOC;\nendmodule\n\nmodule ADCLRC (...);\nendmodule\n\nmodule ADCULC (...);\nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule MIPI_DPHY (...);\noutput RX_CLK_O, TX_CLK_O;\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\ninput  D0LN_HSRX_DREN, D1LN_HSRX_DREN,  D2LN_HSRX_DREN,  D3LN_HSRX_DREN;\noutput  DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N,  DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;\ninout  CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;\ninput HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK,\ninput PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;\ninput TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;\ninput [15:0]  CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;\ninput HSTXD_VLD;\ninput CK0, CK90, CK180, CK270;\ninput DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;\ninput HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, \ninput RX_DRST_N, TX_DRST_N, WALIGN_DVLD;\noutput [7:0] MRDATA;\ninput MA_INC, MCLK;\ninput [1:0] MOPCODE;\ninput [7:0] MWDATA;\noutput  ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;\noutput D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;\noutput D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;\ninput D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;\ninput HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;\ninput HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;\ninput HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,  HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;\ninput  ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;\nparameter        TX_PLLCLK = \"NONE\"; \nparameter        RX_ALIGN_BYTE                  = 8'b10111000 ; \nparameter        RX_HS_8BIT_MODE                = 1'b0 ; \nparameter        RX_LANE_ALIGN_EN               = 1'b0 ; \nparameter        TX_HS_8BIT_MODE                = 1'b0 ; \nparameter        HSREG_EN_LN0                   = 1'b0;  \nparameter        HSREG_EN_LN1                   = 1'b0;  \nparameter        HSREG_EN_LN2                   = 1'b0;  \nparameter        HSREG_EN_LN3                   = 1'b0;  \nparameter        HSREG_EN_LNCK                  = 1'b0;  \nparameter        LANE_DIV_SEL                   = 2'b00;  \nparameter        HSRX_EN                        = 1'b1 ;  \nparameter        HSRX_LANESEL                   = 4'b1111 ;   \nparameter        HSRX_LANESEL_CK                = 1'b1 ;   \nparameter        HSTX_EN_LN0                    = 1'b0 ;   \nparameter        HSTX_EN_LN1                    = 1'b0 ;   \nparameter        HSTX_EN_LN2                    = 1'b0 ;   \nparameter        HSTX_EN_LN3                    = 1'b0 ;   \nparameter        HSTX_EN_LNCK                   = 1'b0 ;   \nparameter        LPTX_EN_LN0                    = 1'b1 ;   \nparameter        LPTX_EN_LN1                    = 1'b1 ;   \nparameter        LPTX_EN_LN2                    = 1'b1 ;   \nparameter        LPTX_EN_LN3                    = 1'b1 ;   \nparameter        LPTX_EN_LNCK                   = 1'b1 ;   \nparameter        TXDP_EN_LN0                    = 1'b0 ;  \nparameter        TXDP_EN_LN1                    = 1'b0 ;   \nparameter        TXDP_EN_LN2                    = 1'b0 ;   \nparameter        TXDP_EN_LN3                    = 1'b0 ;   \nparameter        TXDP_EN_LNCK                   = 1'b0 ;\nparameter        CKLN_DELAY_EN                  = 1'b0;  \nparameter        CKLN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D0LN_DELAY_EN                  = 1'b0;  \nparameter        D0LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D0LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D1LN_DELAY_EN                  = 1'b0;  \nparameter        D1LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D1LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D2LN_DELAY_EN                  = 1'b0;  \nparameter        D2LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D2LN_DESKEW_BYPASS             = 1'b0;  \nparameter        D3LN_DELAY_EN                  = 1'b0;  \nparameter        D3LN_DELAY_OVR_VAL             = 7'b0000000; \nparameter        D3LN_DESKEW_BYPASS             = 1'b0;  \nparameter        DESKEW_EN_LOW_DELAY            = 1'b0;  \nparameter        DESKEW_EN_ONE_EDGE             = 1'b0;  \nparameter        DESKEW_FAST_LOOP_TIME          = 4'b0000;  \nparameter        DESKEW_FAST_MODE               = 1'b0;  \nparameter        DESKEW_HALF_OPENING            = 6'b010110; \nparameter        DESKEW_LSB_MODE                = 2'b00;  \nparameter        DESKEW_M                       = 3'b011;  \nparameter        DESKEW_M_TH                    = 13'b0000110100110; \nparameter        DESKEW_MAX_SETTING           = 7'b0100001; \nparameter        DESKEW_ONE_CLK_EDGE_EN       = 1'b0 ; \nparameter        DESKEW_RST_BYPASS              = 1'b0 ; \nparameter        RX_BYTE_LITTLE_ENDIAN          = 1'b1 ; \nparameter        RX_CLK_1X_SYNC_SEL             = 1'b0 ; \nparameter        RX_INVERT                      = 1'b0 ; \nparameter        RX_ONE_BYTE0_MATCH             = 1'b0 ; \nparameter        RX_RD_START_DEPTH              = 5'b00001; \nparameter        RX_SYNC_MODE                   = 1'b0 ; \nparameter        RX_WORD_ALIGN_BYPASS           = 1'b0 ; \nparameter        RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; \nparameter        RX_WORD_LITTLE_ENDIAN          = 1'b0 ; \nparameter        TX_BYPASS_MODE                 = 1'b0 ; \nparameter        TX_BYTECLK_SYNC_MODE           = 1'b0 ; \nparameter        TX_OCLK_USE_CIBCLK             = 1'b0 ; \nparameter        TX_RD_START_DEPTH              = 5'b00001; \nparameter        TX_SYNC_MODE                   = 1'b0 ; \nparameter        TX_WORD_LITTLE_ENDIAN          = 1'b1 ; \nparameter        EQ_CS_LANE0                    = 3'b100;  \nparameter        EQ_CS_LANE1                    = 3'b100;  \nparameter        EQ_CS_LANE2                    = 3'b100;  \nparameter        EQ_CS_LANE3                    = 3'b100;  \nparameter        EQ_CS_LANECK                   = 3'b100;  \nparameter        EQ_RS_LANE0                    = 3'b100;  \nparameter        EQ_RS_LANE1                    = 3'b100;  \nparameter        EQ_RS_LANE2                    = 3'b100;  \nparameter        EQ_RS_LANE3                    = 3'b100;  \nparameter        EQ_RS_LANECK                   = 3'b100;  \nparameter        HSCLK_LANE_LN0                 = 1'b0;  \nparameter        HSCLK_LANE_LN1                 = 1'b0;  \nparameter        HSCLK_LANE_LN2                 = 1'b0;  \nparameter        HSCLK_LANE_LN3                 = 1'b0;  \nparameter        HSCLK_LANE_LNCK                = 1'b1;  \nparameter        ALP_ED_EN_LANE0                = 1'b1 ; \nparameter        ALP_ED_EN_LANE1                = 1'b1 ;  \nparameter        ALP_ED_EN_LANE2                = 1'b1 ;  \nparameter        ALP_ED_EN_LANE3                = 1'b1 ;  \nparameter        ALP_ED_EN_LANECK               = 1'b1 ; \nparameter        ALP_ED_TST_LANE0               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE1               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE2               = 1'b0 ;  \nparameter        ALP_ED_TST_LANE3               = 1'b0 ;  \nparameter        ALP_ED_TST_LANECK              = 1'b0 ;  \nparameter        ALP_EN_LN0                     = 1'b0 ; \nparameter        ALP_EN_LN1                     = 1'b0 ;  \nparameter        ALP_EN_LN2                     = 1'b0 ;  \nparameter        ALP_EN_LN3                     = 1'b0 ; \nparameter        ALP_EN_LNCK                    = 1'b0 ; \nparameter        ALP_HYS_EN_LANE0               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE1               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE2               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANE3               = 1'b1 ;  \nparameter        ALP_HYS_EN_LANECK              = 1'b1 ;  \nparameter        ALP_TH_LANE0                   = 4'b1000 ;   \nparameter        ALP_TH_LANE1                   = 4'b1000 ;   \nparameter        ALP_TH_LANE2                   = 4'b1000 ;   \nparameter        ALP_TH_LANE3                   = 4'b1000 ;   \nparameter        ALP_TH_LANECK                  = 4'b1000 ;   \nparameter        ANA_BYTECLK_PH                 = 2'b00 ;  \nparameter        BIT_REVERSE_LN0                = 1'b0 ;  \nparameter        BIT_REVERSE_LN1                = 1'b0 ;  \nparameter        BIT_REVERSE_LN2                = 1'b0 ;  \nparameter        BIT_REVERSE_LN3                = 1'b0 ;  \nparameter        BIT_REVERSE_LNCK               = 1'b0 ;  \nparameter        BYPASS_TXHCLKEN                = 1'b1 ;  \nparameter        BYPASS_TXHCLKEN_SYNC           = 1'b0 ;  \nparameter        BYTE_CLK_POLAR                 = 1'b0 ;  \nparameter        BYTE_REVERSE_LN0               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN1               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN2               = 1'b0 ;  \nparameter        BYTE_REVERSE_LN3               = 1'b0 ;  \nparameter        BYTE_REVERSE_LNCK              = 1'b0 ;  \nparameter        EN_CLKB1X                      = 1'b1 ;  \nparameter        EQ_PBIAS_LANE0                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE1                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE2                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANE3                 = 4'b1000 ;   \nparameter        EQ_PBIAS_LANECK                = 4'b1000 ;   \nparameter        EQ_ZLD_LANE0                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE1                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE2                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANE3                   = 4'b1000 ;   \nparameter        EQ_ZLD_LANECK                  = 4'b1000 ;   \nparameter        HIGH_BW_LANE0                  = 1'b1 ;   \nparameter        HIGH_BW_LANE1                  = 1'b1 ;   \nparameter        HIGH_BW_LANE2                  = 1'b1 ;   \nparameter        HIGH_BW_LANE3                  = 1'b1 ;   \nparameter        HIGH_BW_LANECK                 = 1'b1 ;   \nparameter        HSREG_VREF_CTL                 = 3'b100 ;   \nparameter        HSREG_VREF_EN                  = 1'b1 ;  \nparameter        HSRX_DLY_CTL_CK                = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE0             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE1             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE2             = 7'b0000000 ;   \nparameter        HSRX_DLY_CTL_LANE3             = 7'b0000000 ;   \nparameter        HSRX_DLY_SEL_LANE0             = 1'b0 ;  \nparameter        HSRX_DLY_SEL_LANE1             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANE2             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANE3             = 1'b0 ;   \nparameter        HSRX_DLY_SEL_LANECK            = 1'b0 ;   \nparameter        HSRX_DUTY_LANE0                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE1                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE2                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANE3                = 4'b1000 ;  \nparameter        HSRX_DUTY_LANECK               = 4'b1000 ;  \nparameter        HSRX_EQ_EN_LANE0               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE1               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE2               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANE3               = 1'b1 ;  \nparameter        HSRX_EQ_EN_LANECK              = 1'b1 ;  \nparameter        HSRX_IBIAS                     = 4'b0011 ;   \nparameter        HSRX_IBIAS_TEST_EN             = 1'b0 ;   \nparameter        HSRX_IMARG_EN                  = 1'b0 ;   \nparameter        HSRX_ODT_EN                    = 1'b1 ;   \nparameter        HSRX_ODT_TST                   = 4'b0000 ;   \nparameter        HSRX_ODT_TST_CK                = 1'b0 ;   \nparameter        HSRX_SEL                       = 4'b0000 ;   \nparameter        HSRX_STOP_EN                   = 1'b0 ; \nparameter        HSRX_TST                       = 4'b0000 ;   \nparameter        HSRX_TST_CK                    = 1'b0 ;   \nparameter        HSRX_WAIT4EDGE                 = 1'b1 ;   \nparameter        HYST_NCTL                      = 2'b01 ;  \nparameter        HYST_PCTL                      = 2'b01 ;  \nparameter        IBIAS_TEST_EN                  = 1'b0 ;   \nparameter        LB_CH_SEL                      = 1'b0 ;   \nparameter        LB_EN_LN0                      = 1'b0 ;   \nparameter        LB_EN_LN1                      = 1'b0 ;   \nparameter        LB_EN_LN2                      = 1'b0 ;   \nparameter        LB_EN_LN3                      = 1'b0 ;   \nparameter        LB_EN_LNCK                     = 1'b0 ;   \nparameter        LB_POLAR_LN0                   = 1'b0 ;   \nparameter        LB_POLAR_LN1                   = 1'b0 ;   \nparameter        LB_POLAR_LN2                   = 1'b0 ;   \nparameter        LB_POLAR_LN3                   = 1'b0 ;   \nparameter        LB_POLAR_LNCK                  = 1'b0 ;   \nparameter        LOW_LPRX_VTH                   = 1'b0 ;   \nparameter        LPBK_DATA2TO1                  = 4'b0000;  \nparameter        LPBK_DATA2TO1_CK               = 1'b0 ;   \nparameter        LPBK_EN                        = 1'b0 ;   \nparameter        LPBK_SEL                       = 4'b0000;  \nparameter        LPBKTST_EN                     = 4'b0000;  \nparameter        LPBKTST_EN_CK                  = 1'b0 ;   \nparameter        LPRX_EN                        = 1'b1 ;   \nparameter        LPRX_TST                       = 4'b0000;  \nparameter        LPRX_TST_CK                    = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN0             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN1             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN2             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LN3             = 1'b0 ;   \nparameter        LPTX_DAT_POLAR_LNCK            = 1'b0 ;   \nparameter        LPTX_NIMP_LN0                  = 3'b100 ; \nparameter        LPTX_NIMP_LN1                  = 3'b100 ; \nparameter        LPTX_NIMP_LN2                  = 3'b100 ; \nparameter        LPTX_NIMP_LN3                  = 3'b100 ; \nparameter        LPTX_NIMP_LNCK                 = 3'b100 ; \nparameter        LPTX_PIMP_LN0                  = 3'b100 ; \nparameter        LPTX_PIMP_LN1                  = 3'b100 ; \nparameter        LPTX_PIMP_LN2                  = 3'b100 ; \nparameter        LPTX_PIMP_LN3                  = 3'b100 ; \nparameter        LPTX_PIMP_LNCK                 = 3'b100 ; \nparameter        MIPI_PMA_DIS_N                 = 1'b1 ;   \nparameter        PGA_BIAS_LANE0                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE1                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE2                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANE3                 = 4'b1000 ;   \nparameter        PGA_BIAS_LANECK                = 4'b1000 ;   \nparameter        PGA_GAIN_LANE0                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE1                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE2                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANE3                 = 4'b1000 ;   \nparameter        PGA_GAIN_LANECK                = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE0              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE1              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE2              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANE3              = 4'b1000 ;   \nparameter        RX_ODT_TRIM_LANECK             = 4'b1000 ;   \nparameter        SLEWN_CTL_LN0                  = 4'b1111 ;  \nparameter        SLEWN_CTL_LN1                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LN2                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LN3                  = 4'b1111 ;   \nparameter        SLEWN_CTL_LNCK                 = 4'b1111 ;   \nparameter        SLEWP_CTL_LN0                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN1                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN2                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LN3                  = 4'b1111 ;   \nparameter        SLEWP_CTL_LNCK                 = 4'b1111 ;   \nparameter        STP_UNIT                       = 2'b01 ;  \nparameter        TERMN_CTL_LN0                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN1                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN2                  = 4'b1000 ;   \nparameter        TERMN_CTL_LN3                  = 4'b1000 ;   \nparameter        TERMN_CTL_LNCK                 = 4'b1000 ;   \nparameter        TERMP_CTL_LN0                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN1                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN2                  = 4'b1000 ;   \nparameter        TERMP_CTL_LN3                  = 4'b1000 ;   \nparameter        TERMP_CTL_LNCK                 = 4'b1000 ;   \nparameter        TEST_EN_LN0                    = 1'b0 ;   \nparameter        TEST_EN_LN1                    = 1'b0 ;   \nparameter        TEST_EN_LN2                    = 1'b0 ;   \nparameter        TEST_EN_LN3                    = 1'b0 ;   \nparameter        TEST_EN_LNCK                   = 1'b0 ;   \nparameter        TEST_N_IMP_LN0                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN1                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN2                 = 1'b0 ;   \nparameter        TEST_N_IMP_LN3                 = 1'b0 ;   \nparameter        TEST_N_IMP_LNCK                = 1'b0 ;   \nparameter        TEST_P_IMP_LN0                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN1                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN2                 = 1'b0 ;   \nparameter        TEST_P_IMP_LN3                 = 1'b0 ;   \nparameter        TEST_P_IMP_LNCK                = 1'b0 ;   \nendmodule\n\nmodule GTR12_QUAD (...);\nendmodule\n\nmodule GTR12_UPAR (...);\nendmodule\n\nmodule GTR12_PMAC (...);\nendmodule\n\nmodule DQS (...);\ninput DQSIN,PCLK,FCLK,RESET;\ninput [3:0] READ;\ninput [2:0] RCLKSEL;\ninput [7:0] DLLSTEP;\ninput [7:0] WSTEP;\ninput RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\noutput DQSR90, DQSW0, DQSW270; \noutput [2:0] RPOINT, WPOINT;\noutput RVALID,RBURST, RFLAG, WFLAG;\nparameter FIFO_MODE_SEL = 1'b0; \nparameter RD_PNTR = 3'b000; \nparameter DQS_MODE = \"X1\"; \nparameter HWL = \"false\";   \nendmodule\n\n",
             "lutrams.txt": "ram distributed $__GOWIN_LUTRAM_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\twidthscale;\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
             "lutrams_map.v": "module $__GOWIN_LUTRAM_(...);\n\nparameter INIT = 64'bx;\nparameter BITS_USED = 0;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput PORT_W_WR_EN;\ninput [3:0] PORT_W_WR_DATA;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nfunction [15:0] init_slice;\ninput integer idx;\ninteger i;\nfor (i = 0; i < 16; i = i + 1)\n\tinit_slice[i] = INIT[4*i+idx];\nendfunction\n\ngenerate\n\ncasez(BITS_USED)\n4'b000z:\nRAM16SDP1 #(\n\t.INIT_0(init_slice(0)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[0]),\n\t.DO(PORT_R_RD_DATA[0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n4'b00zz:\nRAM16SDP2 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[1:0]),\n\t.DO(PORT_R_RD_DATA[1:0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\ndefault:\nRAM16SDP4 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n\t.INIT_2(init_slice(2)),\n\t.INIT_3(init_slice(3)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.DO(PORT_R_RD_DATA),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\nendcase\n\nendgenerate\n\nendmodule\n",
         },
@@ -163,32 +163,34 @@ export const filesystem = {
                 "bitpattern.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef BITPATTERN_H\n#define BITPATTERN_H\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct BitPatternPool\n{\n\tint width;\n\tstruct bits_t {\n\t\tstd::vector<RTLIL::State> bitdata;\n\t\tmutable Hasher::hash_t cached_hash;\n\t\tbits_t(int width = 0) : bitdata(width), cached_hash(0) { }\n\t\tRTLIL::State &operator[](int index) {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tconst RTLIL::State &operator[](int index) const {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tbool operator==(const bits_t &other) const {\n\t\t\tif (run_hash(*this) != run_hash(other))\n\t\t\t\treturn false;\n\t\t\treturn bitdata == other.bitdata;\n\t\t}\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\tif (!cached_hash)\n\t\t\t\tcached_hash = run_hash(bitdata);\n\t\t\th.eat(cached_hash);\n\t\t\treturn h;\n\t\t}\n\t};\n\tpool<bits_t> database;\n\n\tBitPatternPool(RTLIL::SigSpec sig)\n\t{\n\t\twidth = sig.size();\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\tif (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)\n\t\t\t\t\tpattern[i] = sig[i].data;\n\t\t\t\telse\n\t\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\t}\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tBitPatternPool(int width)\n\t{\n\t\tthis->width = width;\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tbits_t sig2bits(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits;\n\t\tbits.bitdata = sig.as_const().bits();\n\t\tfor (auto &b : bits.bitdata)\n\t\t\tif (b > RTLIL::State::S1)\n\t\t\t\tb = RTLIL::State::Sa;\n\t\treturn bits;\n\t}\n\n\tbool match(bits_t a, bits_t b)\n\t{\n\t\tlog_assert(int(a.bitdata.size()) == width);\n\t\tlog_assert(int(b.bitdata.size()) == width);\n\t\tfor (int i = 0; i < width; i++)\n\t\t\tif (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool has_any(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool has_all(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\t\tif (bits[i] > RTLIL::State::S1 && it[i] <= RTLIL::State::S1)\n\t\t\t\t\t\tgoto next_database_entry;\n\t\t\t\treturn true;\n\tnext_database_entry:;\n\t\t\t}\n\t\treturn false;\n\t}\n\n\tbool take(RTLIL::SigSpec sig)\n\t{\n\t\tbool status = false;\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto it = database.begin(); it != database.end();)\n\t\t\tif (match(*it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\t\tif ((*it)[i] != RTLIL::State::Sa || bits[i] == RTLIL::State::Sa)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbits_t new_pattern;\n\t\t\t\t\tnew_pattern.bitdata = it->bitdata;\n\t\t\t\t\tnew_pattern[i] = bits[i] == RTLIL::State::S1 ? RTLIL::State::S0 : RTLIL::State::S1;\n\t\t\t\t\tdatabase.insert(new_pattern);\n\t\t\t\t}\n\t\t\t\tit = database.erase(it);\n\t\t\t\tstatus = true;\n\t\t\t\tcontinue;\n\t\t\t} else\n\t\t\t\t++it;\n\t\treturn status;\n\t}\n\n\tbool take_all()\n\t{\n\t\tif (database.empty())\n\t\t\treturn false;\n\t\tdatabase.clear();\n\t\treturn true;\n\t}\n\n\tbool empty()\n\t{\n\t\treturn database.empty();\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "cellaigs.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLAIGS_H\n#define CELLAIGS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AigNode\n{\n\tIdString portname;\n\tint portbit;\n\tbool inverter;\n\tint left_parent, right_parent;\n\tvector<pair<IdString, int>> outports;\n\n\tAigNode();\n\tbool operator==(const AigNode &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct Aig\n{\n\tstring name;\n\tvector<AigNode> nodes;\n\tAig(Cell *cell);\n\n\tbool operator==(const Aig &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "celledges.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLEDGES_H\n#define CELLEDGES_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AbstractCellEdgesDatabase\n{\n\tvirtual ~AbstractCellEdgesDatabase() { }\n\tvirtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;\n\tbool add_edges_from_cell(RTLIL::Cell *cell);\n};\n\nstruct FwdCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tFwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[from_sigbit].insert(to_sigbit);\n\t}\n};\n\nstruct RevCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tRevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[to_sigbit].insert(from_sigbit);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "celltypes.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n\tbool is_combinatorial;\n\tbool is_synthesizable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($buf), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_),  {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_),  {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits())\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type.in(ID($_BUF_), ID($buf)))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "consteval.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits()[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).to_bits();\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> slave_bits = y_values.at(i).to_bits();\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits()[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($macc))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tfor (auto &port : macc.ports) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(chain)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\nX(area)\nX(capacitance)\n",
+                "celltypes.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n\tbool is_combinatorial;\n\tbool is_synthesizable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($buf), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_),  {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_),  {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits())\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type.in(ID($_BUF_), ID($buf)))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "consteval.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits()[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).to_bits();\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> slave_bits = y_values.at(i).to_bits();\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits()[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type.in(ID($macc), ID($macc_v2)))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tfor (auto &port : macc.ports) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(chain)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\nX(area)\nX(capacitance)\nX(NPRODUCTS)\nX(NADDENDS)\nX(PRODUCT_NEGATED)\nX(ADDEND_NEGATED)\nX(A_WIDTHS)\nX(B_WIDTHS)\nX(C_WIDTHS)\nX(C_SIGNED)\n",
                 "cost.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef COST_H\n#define COST_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellCosts\n{\n\n\tprivate:\n\tdict<RTLIL::IdString, int> mod_cost_cache_;\n\tDesign *design_ = nullptr;\n\n\tpublic:\n\tCellCosts(RTLIL::Design *design) : design_(design) { }\n\n\tstatic const dict<RTLIL::IdString, int>& default_gate_cost() {\n\t\t// Default size heuristics for several common PDK standard cells\n\t\t// used by abc and stat\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_),    1 },\n\t\t\t{ ID($_NOT_),    2 },\n\t\t\t{ ID($_AND_),    4 },\n\t\t\t{ ID($_NAND_),   4 },\n\t\t\t{ ID($_OR_),     4 },\n\t\t\t{ ID($_NOR_),    4 },\n\t\t\t{ ID($_ANDNOT_), 4 },\n\t\t\t{ ID($_ORNOT_),  4 },\n\t\t\t{ ID($_XOR_),    5 },\n\t\t\t{ ID($_XNOR_),   5 },\n\t\t\t{ ID($_AOI3_),   6 },\n\t\t\t{ ID($_OAI3_),   6 },\n\t\t\t{ ID($_AOI4_),   7 },\n\t\t\t{ ID($_OAI4_),   7 },\n\t\t\t{ ID($_MUX_),    4 },\n\t\t\t{ ID($_NMUX_),   4 },\n\t\t};\n\t\treturn db;\n\t}\n\n\tstatic const dict<RTLIL::IdString, int>& cmos_gate_cost() {\n\t\t// Estimated CMOS transistor counts for several common PDK standard cells\n\t\t// used by stat and optionally by abc\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_),     1 },\n\t\t\t{ ID($_NOT_),     2 },\n\t\t\t{ ID($_AND_),     6 },\n\t\t\t{ ID($_NAND_),    4 },\n\t\t\t{ ID($_OR_),      6 },\n\t\t\t{ ID($_NOR_),     4 },\n\t\t\t{ ID($_ANDNOT_),  6 },\n\t\t\t{ ID($_ORNOT_),   6 },\n\t\t\t{ ID($_XOR_),    12 },\n\t\t\t{ ID($_XNOR_),   12 },\n\t\t\t{ ID($_AOI3_),    6 },\n\t\t\t{ ID($_OAI3_),    6 },\n\t\t\t{ ID($_AOI4_),    8 },\n\t\t\t{ ID($_OAI4_),    8 },\n\t\t\t{ ID($_MUX_),    12 },\n\t\t\t{ ID($_NMUX_),   10 },\n\t\t\t{ ID($_DFF_P_),  16 },\n\t\t\t{ ID($_DFF_N_),  16 },\n\t\t};\n\t\treturn db;\n\t}\n\n\t// Get the cell cost for a cell based on its parameters.\n\t// This cost is an *approximate* upper bound for the number of gates that\n\t// the cell will get mapped to with \"opt -fast; techmap\"\n\t// The intended usage is for flattening heuristics and similar situations\n\tunsigned int get(RTLIL::Cell *cell);\n\t// Sum up the cell costs of all cells in the module\n\t// and all its submodules recursively\n\tunsigned int get(RTLIL::Module *mod);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "drivertools.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef DRIVERTOOLS_H\n#define DRIVERTOOLS_H\n\n#include <type_traits>\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// TODO move implementation into a .cc file\n\nstruct DriveBit;\n\nstruct DriveChunkWire;\nstruct DriveChunkPort;\nstruct DriveChunkMarker;\nstruct DriveChunk;\n\nstruct DriveSpec;\n\nconst char *log_signal(DriveChunkWire const &chunk);\nconst char *log_signal(DriveChunkPort const &chunk);\nconst char *log_signal(DriveChunkMarker const &chunk);\nconst char *log_signal(DriveChunk const &chunk);\nconst char *log_signal(DriveSpec const &chunk);\n\nenum class DriveType : unsigned char\n{\n\tNONE,\n\tCONSTANT,\n\tWIRE,\n\tPORT,\n\tMULTIPLE,\n\tMARKER,\n};\n\nstruct DriveBitWire\n{\n\tWire *wire;\n\tint offset;\n\n\tDriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {}\n\n\tbool operator==(const DriveBitWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\n\toperator SigBit() const\n\t{\n\t\treturn SigBit(wire, offset);\n\t}\n};\n\nstruct DriveBitPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\n\tDriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {}\n\n\tbool operator==(const DriveBitPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n};\n\n\nstruct DriveBitMarker\n{\n\tint marker;\n\tint offset;\n\n\tDriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {}\n\n\tbool operator==(const DriveBitMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n};\n\nstruct DriveBitMultiple\n{\nprivate:\n\tpool<DriveBit> multiple_;\n\npublic:\n\tDriveBitMultiple();\n\tDriveBitMultiple(DriveBit const &single);\n\n\tpool<DriveBit> const &multiple() const { return multiple_; }\n\n\tvoid merge(DriveBitMultiple const &other)\n\t{\n\t\tfor (DriveBit const &single : other.multiple_)\n\t\t\tmerge(single);\n\t}\n\n\tvoid merge(DriveBitMultiple &&other)\n\t{\n\t\tfor (DriveBit &single : other.multiple_)\n\t\t\tmerge(std::move(single));\n\t}\n\n\tvoid merge(DriveBit const &single);\n\tvoid merge(DriveBit &&single);\n\n\tbool operator==(const DriveBitMultiple &other) const\n\t{\n\t\treturn multiple_ == other.multiple_;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct DriveBit\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tState constant_;\n\t\tDriveBitWire wire_;\n\t\tDriveBitPort port_;\n\t\tDriveBitMarker marker_;\n\t\tDriveBitMultiple multiple_;\n\t};\npublic:\n\tDriveBit()  {}\n\n\tDriveBit(SigBit const &bit);\n\n\tDriveBit(DriveBit const &other) { *this = other; }\n\tDriveBit(DriveBit &&other) { *this = other; }\n\n\n\tDriveBit(State constant) { *this = constant; }\n\tDriveBit(DriveBitWire const &wire) { *this = wire; }\n\tDriveBit(DriveBitWire &&wire) { *this = wire; }\n\tDriveBit(DriveBitPort const &port) { *this = port; }\n\tDriveBit(DriveBitPort &&port) { *this = port; }\n\tDriveBit(DriveBitMarker const &marker) { *this = marker; }\n\tDriveBit(DriveBitMarker &&marker) { *this = marker; }\n\tDriveBit(DriveBitMultiple const &multiple) { *this = multiple; }\n\tDriveBit(DriveBitMultiple &&multiple) { *this = multiple; }\n\n\t~DriveBit() { set_none(); }\n\n\tvoid set_none()\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveBitWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveBitPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveBitMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveBitMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t}\n\n\tDriveBit &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBit &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(State constant)\n\t{\n\t\tset_none();\n\t\tconstant_ = constant;\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple const &multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple &&multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\tbool operator==(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveBit &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tlog_assert(!\"TODO\");\n\t\t}\n\t\tlog_abort();\n\t}\n\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tState &constant() { log_assert(is_constant()); return constant_; }\n\tState const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveBitWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveBitWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveBitPort &port() { log_assert(is_port()); return port_; }\n\tDriveBitPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveBitMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\tvoid merge(DriveBit const &other);\n\n};\n\ninline DriveBitMultiple::DriveBitMultiple() {}\ninline DriveBitMultiple::DriveBitMultiple(DriveBit const &single)\n{\n\tmultiple_.emplace(single);\n}\n\nstruct DriveChunkWire\n{\n\tWire *wire;\n\tint offset;\n\tint width;\n\n\tDriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {}\n\tDriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitWire operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitWire(wire, offset + i);\n\t}\n\n\tbool can_append(DriveBitWire const &bit) const;\n\tbool try_append(DriveBitWire const &bit);\n\tbool try_append(DriveChunkWire const &chunk);\n\n\t// Whether this chunk is a whole wire\n\tbool is_whole() const { return offset == 0 && width == wire->width; }\n\n\tbool operator==(const DriveChunkWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\texplicit operator SigChunk() const\n\t{\n\t\treturn SigChunk(wire, offset, width);\n\t}\n};\n\nstruct DriveChunkPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\tint width;\n\n\tDriveChunkPort(Cell *cell, IdString port, int offset, int width) :\n\t\tcell(cell), port(port), offset(offset), width(width) { }\n\tDriveChunkPort(Cell *cell, IdString port) :\n\t\tcell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { }\n\tDriveChunkPort(Cell *cell, std::pair<IdString, SigSpec> const &conn) :\n\t\tcell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { }\n\tDriveChunkPort(DriveBitPort const &bit) :\n\t\tcell(bit.cell), port(bit.port), offset(bit.offset), width(1) { }\n\n\tint size() const { return width; }\n\n\tDriveBitPort operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitPort(cell, port, offset + i);\n\t}\n\n\tbool can_append(DriveBitPort const &bit) const;\n\tbool try_append(DriveBitPort const &bit);\n\tbool try_append(DriveChunkPort const &chunk);\n\n\t// Whether this chunk is a whole port\n\tbool is_whole() const\n\t{\n\t\treturn offset == 0 && width == cell->connections().at(port).size();\n\t}\n\n\tbool operator==(const DriveChunkPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\n\nstruct DriveChunkMarker\n{\n\tint marker;\n\tint offset;\n\tint width;\n\n\tDriveChunkMarker(int marker, int offset, int width) :\n\t\tmarker(marker), offset(offset), width(width) {}\n\tDriveChunkMarker(DriveBitMarker const &bit) :\n\t\tmarker(bit.marker), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitMarker operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitMarker(marker, offset + i);\n\t}\n\n\tbool can_append(DriveBitMarker const &bit) const;\n\tbool try_append(DriveBitMarker const &bit);\n\tbool try_append(DriveChunkMarker const &chunk);\n\n\tbool operator==(const DriveChunkMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct DriveChunkMultiple\n{\nprivate:\n\tmutable pool<DriveChunk> multiple_;\n\tint width_;\n\npublic:\n\tpool<DriveChunk> const &multiple() const { return multiple_; }\n\n\tDriveChunkMultiple(DriveBitMultiple const &bit);\n\n\tint size() const { return width_; }\n\n\tDriveBitMultiple operator[](int i) const;\n\n\tbool can_append(DriveBitMultiple const &bit) const;\n\n\tbool try_append(DriveBitMultiple const &bit);\n\n\n\tbool can_append(DriveChunkMultiple const &bit) const;\n\n\tbool try_append(DriveChunkMultiple const &bit);\n\n\tbool operator==(const DriveChunkMultiple &other) const\n\t{\n\t\treturn width_ == other.width_ && multiple_ == other.multiple_;\n\t}\n\n\tbool operator<(const DriveChunkMultiple &other) const\n\t{\n\t\tif (multiple_.size() < other.multiple_.size())\n\n\t\tmultiple_.sort();\n\t\treturn false; // TODO implement, canonicalize order\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n};\n\nstruct DriveChunk\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tint none_;\n\t\tConst constant_;\n\t\tDriveChunkWire wire_;\n\t\tDriveChunkPort port_;\n\t\tDriveChunkMarker marker_;\n\t\tDriveChunkMultiple multiple_;\n\t};\n\npublic:\n\tDriveChunk() { set_none(); }\n\n\tDriveChunk(DriveChunk const &other) { *this = other; }\n\tDriveChunk(DriveChunk &&other) { *this = other; }\n\n\tDriveChunk(DriveBit const &other) { *this = other; }\n\n\tDriveChunk(Const const &constant) { *this = constant; }\n\tDriveChunk(Const &&constant) { *this = constant; }\n\tDriveChunk(DriveChunkWire const &wire) { *this = wire; }\n\tDriveChunk(DriveChunkWire &&wire) { *this = wire; }\n\tDriveChunk(DriveChunkPort const &port) { *this = port; }\n\tDriveChunk(DriveChunkPort &&port) { *this = port; }\n\tDriveChunk(DriveChunkMarker const &marker) { *this = marker; }\n\tDriveChunk(DriveChunkMarker &&marker) { *this = marker; }\n\tDriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; }\n\tDriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; }\n\n\t~DriveChunk() { set_none(); }\n\n\tDriveBit operator[](int i) const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn DriveBit();\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_[i];\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_[i];\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_[i];\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_[i];\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_[i];\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tvoid set_none(int width = 0)\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tnone_ = width;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tconstant_.~Const();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveChunkWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveChunkPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveChunkMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveChunkMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t\tnone_ = width;\n\t}\n\n\tDriveChunk &operator=(DriveChunk const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunk &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const const &constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(constant);\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const &&constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(std::move(constant));\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple const &multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple &&multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type())\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(1);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = Const(other.constant());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = DriveChunkWire(other.wire());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = DriveChunkPort(other.port());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = DriveChunkMarker(other.marker());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = DriveChunkMultiple(other.multiple());\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tbool can_append(DriveBit const &bit) const;\n\tbool try_append(DriveBit const &bit);\n\tbool try_append(DriveChunk const &chunk);\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\tbool operator==(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveChunk &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ < other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tConst &constant() { log_assert(is_constant()); return constant_; }\n\tConst const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveChunkWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveChunkPort &port() { log_assert(is_port()); return port_; }\n\tDriveChunkPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveChunkMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\n\tint size() const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn none_;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_.size();\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_.size();\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_.size();\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_.size();\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_.size();\n\t\t}\n\t\tlog_abort();\n\t}\n};\n\ninline DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit)\n\t: width_(1)\n{\n\tfor (auto const &bit : bit.multiple())\n\t\tmultiple_.emplace(bit);\n}\n\nstruct DriveSpec\n{\nprivate:\n\tint width_ = 0;\n\tmutable std::vector<DriveChunk> chunks_;\n\tmutable std::vector<DriveBit> bits_;\n\tmutable unsigned int hash_ = 0;\npublic:\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tDriveSpec() {}\n\n\tDriveSpec(DriveChunk const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkWire const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkPort const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMarker const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; }\n\n\tDriveSpec(DriveBit const &bit) { *this = bit; }\n\tDriveSpec(DriveBitWire const &bit) { *this = bit; }\n\tDriveSpec(DriveBitPort const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMarker const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMultiple const &bit) { *this = bit; }\n\n\tDriveSpec(std::vector<DriveChunk> const &chunks) : chunks_(chunks) { compute_width(); }\n\n\tDriveSpec(std::vector<DriveBit> const &bits)\n\t{\n\t\tfor (auto const &bit : bits)\n\t\t\tappend(bit);\n\t}\n\n\tDriveSpec(SigSpec const &sig)\n\t{\n\t\t// TODO: converting one chunk at a time would be faster\n\t\tfor (auto const &bit : sig.bits())\n\t\t\tappend(bit);\n\t}\n\n\tstd::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }\n\tstd::vector<DriveBit> const &bits() const { unpack(); return bits_; }\n\n\tint size() const { return width_; }\n\n\tvoid append(DriveBit const &bit);\n\n\tvoid append(DriveChunk const &chunk);\n\n\tvoid pack() const;\n\n\tvoid unpack() const;\n\n\tDriveBit &operator[](int index)\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tconst DriveBit &operator[](int index) const\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tvoid clear()\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\twidth_ = 0;\n\t}\n\n\tDriveSpec &operator=(DriveChunk const &chunk)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(chunk);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); }\n\n\tDriveSpec &operator=(DriveBit const &bit)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(bit);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); }\n\n\tvoid updhash() const {\n\t\tif (hash_ != 0)\n\t\t\treturn;\n\t\tpack();\n\t\thash_ = run_hash(chunks_);\n\t\thash_ |= (hash_ == 0);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\n\tbool operator==(DriveSpec const &other) const {\n\t\tupdhash();\n\t\tother.updhash();\n\t\tif (size() != other.size() || hash_ != other.hash_)\n\t\t\treturn false;\n\t\treturn chunks() == other.chunks();\n\t}\n\nprivate:\n\tvoid compute_width();\n};\n\n\n\nstruct DriverMap\n{\n\tCellTypes celltypes;\n\n\tDriverMap() { celltypes.setup(); }\n\tDriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); }\n\nprivate:\n\n\t// Internally we represent all DriveBits by mapping them to DriveBitIds\n\t// which use less memory and are cheaper to compare.\n\tstruct DriveBitId\n\t{\n\t\tint id = -1;\n\n\t\tDriveBitId() {};\n\n\t\tDriveBitId(int id) : id(id) { }\n\n\t\tbool operator==(const DriveBitId &other) const { return id == other.id; }\n\t\tbool operator!=(const DriveBitId &other) const { return id != other.id; }\n\t\tbool operator<(const DriveBitId &other) const { return id < other.id; }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t};\n\t// Essentially a dict<DriveBitId, pool<DriveBitId>> but using less memory\n\t// and fewer allocations\n\tstruct DriveBitGraph {\n\t\tdict<DriveBitId, DriveBitId> first_edges;\n\t\tdict<DriveBitId, DriveBitId> second_edges;\n\t\tdict<DriveBitId, pool<DriveBitId>> more_edges;\n\n\t\tvoid add_edge(DriveBitId src, DriveBitId dst);\n\t\tDriveBitId pop_edge(DriveBitId src);\n\t\tvoid clear(DriveBitId src);\n\t\tbool contains(DriveBitId src);\n\t\tint count(DriveBitId src);\n\n\t\tDriveBitId at(DriveBitId src, int index);\n\t};\n\n\t// The following two maps maintain a sparse DriveBit to DriveBitId mapping.\n\t// This saves a lot of memory compared to a `dict<DriveBit, DriveBitId>` or\n\t// `idict<DriveBit>`.\n\n\t// Maps wires to the first DriveBitId of the consecutive range used for\n\t// that wire.\n\tdict<Wire *, DriveBitId> wire_offsets;\n\n\t// Maps cell ports to a the first DriveBitId of the consecutive range used\n\t// for that cell port.\n\tdict<pair<Cell *, IdString>, DriveBitId> port_offsets;\n\n\t// For the inverse map that maps DriveBitIds back to DriveBits we use a\n\t// sorted map containing only the first DriveBit for each wire and cell\n\t// port.\n\tstd::map<DriveBitId, DriveBit> drive_bits;\n\n\t// As a memory optimization for gate level net lists we store single-bit\n\t// wires and cell ports in a `dict` which requires less memory and fewer\n\t// allocations than `std::map` but doesn't support the kind of lookups we\n\t// need for a sparse coarse grained mapping.\n\tdict<DriveBitId, DriveBit> isolated_drive_bits;\n\n\t// Used for allocating DriveBitIds, none and constant states use a fixewd\n\t// mapping to the first few ids, which we need to skip.\n\tint next_offset = 1 + (int)State::Sm;\n\n\t// Union-Find over directly connected bits that share the same single\n\t// driver or are undriven. We never merge connections between drivers\n\t// and/or kept wires.\n\tmfp<DriveBitId> same_driver;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally unambiguous (one side only drives or requires a driven value).\n\tDriveBitGraph connected_drivers;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally ambiguous. Every such ambiguous connection is also present in\n\t// the reverse direction and has to be resolved when querying drivers.\n\tDriveBitGraph connected_undirected;\n\n\t// Subset of `connected_undirected` for caching the resolved driving\n\t// direction. In case multiple drivers are present this can still contain\n\t// both orientations of a single connection, but for a single driver only\n\t// one will be present.\n\tDriveBitGraph connected_oriented;\n\n\t// Stores for which bits we already resolved the orientation (cached in\n\t// `connected_oriented`).\n\tpool<DriveBitId> oriented_present;\n\n\n\tenum class BitMode {\n\t\tNONE = 0, // Not driven, no need to keep wire\n\t\tDRIVEN = 1, // Not driven, uses a value driven elsewhere\n\t\tDRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection\n\t\tKEEP = 3, // Wire that should be kept\n\t\tTRISTATE = 4, // Can drive a value but can also use a value driven elsewhere\n\t\tDRIVER = 5, // Drives a value\n\t};\n\n\tBitMode bit_mode(DriveBit const &bit);\n\tDriveBitId id_from_drive_bit(DriveBit const &bit);\n\tDriveBit drive_bit_from_id(DriveBitId id);\n\n\tvoid connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_undirected(DriveBitId a_id, DriveBitId b_id);\n\npublic:\n\n\tvoid add(Module *module);\n\n\t// Add a single bit connection to the driver map.\n\tvoid add(DriveBit const &a, DriveBit const &b);\n\n\ttemplate<typename T>\n\tstatic constexpr bool is_sig_type() {\n\t\treturn\n\t\t\tstd::is_same<T, SigSpec>::value ||\n\t\t\tstd::is_same<T, SigChunk>::value ||\n\t\t\tstd::is_same<T, DriveSpec>::value ||\n\t\t\tstd::is_same<T, DriveChunk>::value ||\n\t\t\tstd::is_same<T, DriveChunkPort>::value ||\n\t\t\tstd::is_same<T, DriveChunkWire>::value ||\n\t\t\tstd::is_same<T, Const>::value;\n\t}\n\n\t// We use the enable_if to produce better compiler errors when unsupported\n\t// types are used\n\ttemplate<typename T, typename U>\n\ttypename std::enable_if<is_sig_type<T>() && is_sig_type<U>()>::type\n\tadd(T const &a, U const &b)\n\t{\n\t\tlog_assert(a.size() == b.size());\n\t\tfor (int i = 0; i != GetSize(a); ++i)\n\t\t\tadd(DriveBit(a[i]), DriveBit(b[i]));\n\t}\n\n\n\t// Specialized version that avoids unpacking\n\tvoid add(SigSpec const &a, SigSpec const &b);\n\nprivate:\n\tvoid add_port(Cell *cell, IdString const &port, SigSpec const &b);\n\n\t// Only used a local variables in `orient_undirected`, always cleared, only\n\t// stored to reduce allocations.\n\tpool<DriveBitId> orient_undirected_seen;\n\tpool<DriveBitId> orient_undirected_drivers;\n\tdict<DriveBitId, int> orient_undirected_distance;\n\n\tvoid orient_undirected(DriveBitId id);\n\npublic:\n\tDriveBit operator()(DriveBit const &bit);\n\n\tDriveSpec operator()(DriveSpec spec);\n\nprivate:\n\tbool keep_wire(Wire *wire) {\n\t\t// TODO configurable\n\t\treturn wire->has_attribute(ID(keep));\n\t}\n};\n\ninline Hasher DriveBitWire::hash_into(Hasher h) const\n{\n\th.eat(wire->name);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveBitPort::hash_into(Hasher h) const\n{\n\th.eat(cell->name);\n\th.eat(port);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveBitMarker::hash_into(Hasher h) const\n{\n\th.eat(marker);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveBitMultiple::hash_into(Hasher h) const\n{\n\th.eat(multiple_);\n\treturn h;\n}\n\ninline Hasher DriveBit::hash_into(Hasher h) const\n{\n\tswitch (type_) {\n\tcase DriveType::NONE:\n\t\th.eat(0);\n\t\tbreak;\n\tcase DriveType::CONSTANT:\n\t\th.eat(constant_);\n\t\tbreak;\n\tcase DriveType::WIRE:\n\t\th.eat(wire_);\n\t\tbreak;\n\tcase DriveType::PORT:\n\t\th.eat(port_);\n\t\tbreak;\n\tcase DriveType::MARKER:\n\t\th.eat(marker_);\n\t\tbreak;\n\tcase DriveType::MULTIPLE:\n\t\th.eat(multiple_);\n\t\tbreak;\n\t}\n\th.eat(type_);\n\treturn h;\n}\n\ninline Hasher DriveChunkWire::hash_into(Hasher h) const\n{\n\th.eat(wire->name);\n\th.eat(width);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveChunkPort::hash_into(Hasher h) const\n{\n\th.eat(cell->name);\n\th.eat(port);\n\th.eat(width);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveChunkMarker::hash_into(Hasher h) const\n{\n\th.eat(marker);\n\th.eat(width);\n\th.eat(offset);\n\treturn h;\n}\n\ninline Hasher DriveChunkMultiple::hash_into(Hasher h) const\n{\n\th.eat(width_);\n\th.eat(multiple_);\n\treturn h;\n}\n\ninline Hasher DriveChunk::hash_into(Hasher h) const\n{\n\tswitch (type_) {\n\tcase DriveType::NONE:\n\t\th.eat(0);\n\t\tbreak;\n\tcase DriveType::CONSTANT:\n\t\th.eat(constant_);\n\t\tbreak;\n\tcase DriveType::WIRE:\n\t\th.eat(wire_);\n\t\tbreak;\n\tcase DriveType::PORT:\n\t\th.eat(port_);\n\t\tbreak;\n\tcase DriveType::MARKER:\n\t\th.eat(marker_);\n\t\tbreak;\n\tcase DriveType::MULTIPLE:\n\t\th.eat(multiple_);\n\t\tbreak;\n\t}\n\th.eat(type_);\n\treturn h;\n}\n\ninline Hasher DriveSpec::hash_into(Hasher h) const\n{\n\tupdhash();\n\th.eat(hash_);\n\treturn h;\n}\n\ninline Hasher DriverMap::DriveBitId::hash_into(Hasher h) const\n{\n\th.eat(id);\n\treturn h;\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "ff.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2020  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FF_H\n#define FF_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Describes a flip-flop or a latch.\n//\n// If has_gclk, this is a formal verification FF with implicit global clock:\n// Q is simply previous cycle's D. Additionally if is_anyinit is true, this is\n// an $anyinit cell which always has an undefined initialization value. Note\n// that $anyinit is not considered to be among the FF celltypes, so a pass has\n// to explicitly opt-in to process $anyinit cells with FfData.\n//\n// Otherwise, the FF/latch can have any number of features selected by has_*\n// attributes that determine Q's value (in order of decreasing priority):\n//\n// - on start, register is initialized to val_init\n// - if has_sr is present:\n//   - sig_clr is per-bit async clear, and sets the corresponding bit to 0\n//     if active\n//   - sig_set is per-bit async set, and sets the corresponding bit to 1\n//     if active\n// - if has_arst is present:\n//   - sig_arst is whole-reg async reset, and sets the whole register to val_arst\n// - if has_aload is present:\n//   - sig_aload is whole-reg async load (aka latch gate enable), and sets the whole\n//     register to sig_ad\n// - if has_clk is present, and we're currently on a clock edge:\n//   - if has_ce is present and ce_over_srst is true:\n//     - ignore clock edge (don't change value) unless sig_ce is active\n//   - if has_srst is present:\n//     - sig_srst is whole-reg sync reset and sets the register to val_srst\n//   - if has_ce is present and ce_over_srst is false:\n//     - ignore clock edge (don't change value) unless sig_ce is active\n//   - set whole reg to sig_d\n// - if nothing of the above applies, the reg value remains unchanged\n//\n// Since the yosys FF cell library isn't fully generic, not all combinations\n// of the features above can be supported:\n//\n// - only one of has_srst, has_arst, has_sr can be used\n// - if has_clk is used together with has_aload, then has_srst, has_arst,\n//   has_sr cannot be used\n//\n// The valid feature combinations are thus:\n//\n// - has_clk + optional has_ce [dff/dffe]\n// - has_clk + optional has_ce + has_arst [adff/adffe]\n// - has_clk + optional has_ce + has_aload [aldff/aldffe]\n// - has_clk + optional has_ce + has_sr [dffsr/dffsre]\n// - has_clk + optional has_ce + has_srst [sdff/sdffe/sdffce]\n// - has_aload [dlatch]\n// - has_aload + has_arst [adlatch]\n// - has_aload + has_sr [dlatchsr]\n// - has_sr [sr]\n// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]\n// - empty set [not a cell — will be emitted as a simple direct connection]\n\nstruct FfData {\n\tModule *module;\n\tFfInitVals *initvals;\n\tCell *cell;\n\tIdString name;\n\t// The FF output.\n\tSigSpec sig_q;\n\t// The sync data input, present if has_clk or has_gclk.\n\tSigSpec sig_d;\n\t// The async data input, present if has_aload.\n\tSigSpec sig_ad;\n\t// The sync clock, present if has_clk.\n\tSigSpec sig_clk;\n\t// The clock enable, present if has_ce.\n\tSigSpec sig_ce;\n\t// The async load enable, present if has_aload.\n\tSigSpec sig_aload;\n\t// The async reset, preset if has_arst.\n\tSigSpec sig_arst;\n\t// The sync reset, preset if has_srst.\n\tSigSpec sig_srst;\n\t// The async clear (per-lane), present if has_sr.\n\tSigSpec sig_clr;\n\t// The async set (per-lane), present if has_sr.\n\tSigSpec sig_set;\n\t// True if this is a clocked (edge-sensitive) flip-flop.\n\tbool has_clk;\n\t// True if this is a $ff, exclusive with every other has_*.\n\tbool has_gclk;\n\t// True if this FF has a clock enable.  Depends on has_clk.\n\tbool has_ce;\n\t// True if this FF has async load function — this includes D latches.\n\t// If this and has_clk are both set, has_arst and has_sr cannot be set.\n\tbool has_aload;\n\t// True if this FF has sync set/reset.  Depends on has_clk, exclusive\n\t// with has_arst, has_sr, has_aload.\n\tbool has_srst;\n\t// True if this FF has async set/reset.  Exclusive with has_srst,\n\t// has_sr.  If this and has_clk are both set, has_aload cannot be set.\n\tbool has_arst;\n\t// True if this FF has per-bit async set + clear.  Exclusive with\n\t// has_srst, has_arst.  If this and has_clk are both set, has_aload\n\t// cannot be set.\n\tbool has_sr;\n\t// If has_ce and has_srst are both set, determines their relative\n\t// priorities: if true, inactive ce disables srst; if false, srst\n\t// operates independent of ce.\n\tbool ce_over_srst;\n\t// True if this FF is a fine cell, false if it is a coarse cell.\n\t// If true, width must be 1.\n\tbool is_fine;\n\t// True if this FF is an $anyinit cell.  Depends on has_gclk.\n\tbool is_anyinit;\n\t// Polarities, corresponding to sig_*.\n\t// True means rising edge, false means falling edge.\n\tbool pol_clk;\n\t// True means active-high, false\n\t// means active-low.\n\tbool pol_ce;\n\tbool pol_aload;\n\tbool pol_arst;\n\tbool pol_srst;\n\tbool pol_clr;\n\tbool pol_set;\n\t// The value loaded by sig_arst.\n\tConst val_arst;\n\t// The value loaded by sig_srst.\n\tConst val_srst;\n\t// The initial value at power-up.\n\tConst val_init;\n\t// The FF data width in bits.\n\tint width;\n\tdict<IdString, Const> attributes;\n\n\tFfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {\n\t\twidth = 0;\n\t\thas_clk = false;\n\t\thas_gclk = false;\n\t\thas_ce = false;\n\t\thas_aload = false;\n\t\thas_srst = false;\n\t\thas_arst = false;\n\t\thas_sr = false;\n\t\tce_over_srst = false;\n\t\tis_fine = false;\n\t\tis_anyinit = false;\n\t\tpol_clk = false;\n\t\tpol_aload = false;\n\t\tpol_ce = false;\n\t\tpol_arst = false;\n\t\tpol_srst = false;\n\t\tpol_clr = false;\n\t\tpol_set = false;\n\t}\n\n\tFfData(FfInitVals *initvals, Cell *cell_);\n\n\t// Returns a FF identical to this one, but only keeping bit indices from the argument.\n\tFfData slice(const std::vector<int> &bits);\n\n\tvoid add_dummy_ce();\n\tvoid add_dummy_srst();\n\tvoid add_dummy_arst();\n\tvoid add_dummy_aload();\n\tvoid add_dummy_sr();\n\tvoid add_dummy_clk();\n\n\tvoid arst_to_aload();\n\tvoid arst_to_sr();\n\n\tvoid aload_to_sr();\n\n\t// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and\n\t// fixes up control signals appropriately to preserve semantics.\n\tvoid convert_ce_over_srst(bool val);\n\n\tvoid unmap_ce();\n\tvoid unmap_srst();\n\n\tvoid unmap_ce_srst() {\n\t\tunmap_ce();\n\t\tunmap_srst();\n\t}\n\n\tCell *emit();\n\n\t// Removes init attribute from the Q output, but keeps val_init unchanged.\n\t// It will be automatically reattached on emit.  Use this before changing sig_q.\n\tvoid remove_init() {\n\t\tif (initvals)\n\t\t\tinitvals->remove_init(sig_q);\n\t}\n\n\tvoid remove();\n\n\t// Flip the sense of the given bit slices of the FF: insert inverters on data\n\t// inputs and output, flip the corresponding init/reset bits, swap clr/set\n\t// inputs with proper priority fix.\n\tvoid flip_bits(const pool<int> &bits);\n\n\tvoid flip_rst_bits(const pool<int> &bits);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "ffinit.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2020  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFINIT_H\n#define FFINIT_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FfInitVals\n{\n\tconst SigMap *sigmap;\n\tdict<SigBit, std::pair<State,SigBit>> initbits;\n\n\tvoid set(const SigMap *sigmap_, RTLIL::Module *module)\n\t{\n\t\tsigmap = sigmap_;\n\t\tinitbits.clear();\n\t\tfor (auto wire : module->wires())\n\t\t{\n\t\t\tif (wire->attributes.count(ID::init) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tSigSpec wirebits = (*sigmap)(wire);\n\t\t\tConst initval = wire->attributes.at(ID::init);\n\n\t\t\tfor (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)\n\t\t\t{\n\t\t\t\tSigBit bit = wirebits[i];\n\t\t\t\tState val = initval[i];\n\n\t\t\t\tif (val != State::S0 && val != State::S1 && bit.wire != nullptr)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (initbits.count(bit)) {\n\t\t\t\t\tif (initbits.at(bit).first != val)\n\t\t\t\t\t\tlog_error(\"Conflicting init values for signal %s (%s = %s != %s).\\n\",\n\t\t\t\t\t\t\t\tlog_signal(bit), log_signal(SigBit(wire, i)),\n\t\t\t\t\t\t\t\tlog_signal(val), log_signal(initbits.at(bit).first));\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tinitbits[bit] = std::make_pair(val,SigBit(wire,i));\n\t\t\t}\n\t\t}\n\t}\n\n\tRTLIL::State operator()(RTLIL::SigBit bit) const\n\t{\n\t\tauto it = initbits.find((*sigmap)(bit));\n\t\tif (it != initbits.end())\n\t\t\treturn it->second.first;\n\t\telse\n\t\t\treturn State::Sx;\n\t}\n\n\tRTLIL::Const operator()(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::Const res;\n\t\tfor (auto bit : sig)\n\t\t\tres.bits().push_back((*this)(bit));\n\t\treturn res;\n\t}\n\n\tvoid set_init(RTLIL::SigBit bit, RTLIL::State val)\n\t{\n\t\tSigBit mbit = (*sigmap)(bit);\n\t\tSigBit abit = bit;\n\t\tauto it = initbits.find(mbit);\n\t\tif (it != initbits.end())\n\t\t\tabit = it->second.second;\n\t\telse if (val == State::Sx)\n\t\t\treturn;\n\t\tlog_assert(abit.wire);\n\t\tinitbits[mbit] = std::make_pair(val,abit);\n\t\tauto it2 = abit.wire->attributes.find(ID::init);\n\t\tif (it2 != abit.wire->attributes.end()) {\n\t\t\tit2->second.bits()[abit.offset] = val;\n\t\t\tif (it2->second.is_fully_undef())\n\t\t\t\tabit.wire->attributes.erase(it2);\n\t\t} else if (val != State::Sx) {\n\t\t\tConst cval(State::Sx, GetSize(abit.wire));\n\t\t\tcval.bits()[abit.offset] = val;\n\t\t\tabit.wire->attributes[ID::init] = cval;\n\t\t}\n\t}\n\n\tvoid set_init(const RTLIL::SigSpec &sig, RTLIL::Const val)\n\t{\n\t\tlog_assert(GetSize(sig) == GetSize(val));\n\t\tfor (int i = 0; i < GetSize(sig); i++)\n\t\t\tset_init(sig[i], val[i]);\n\t}\n\n\tvoid remove_init(RTLIL::SigBit bit)\n\t{\n\t\tset_init(bit, State::Sx);\n\t}\n\n\tvoid remove_init(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto bit : sig)\n\t\t\tremove_init(bit);\n\t}\n\n\tvoid clear()\n\t{\n\t\tinitbits.clear();\n\t}\n\n\tFfInitVals (const SigMap *sigmap, RTLIL::Module *module)\n\t{\n\t\tset(sigmap, module);\n\t}\n\n\tFfInitVals () {}\n};\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "ffmerge.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2021  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFMERGE_H\n#define FFMERGE_H\n\n#include \"kernel/ffinit.h\"\n#include \"kernel/ff.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// A helper class for passes that want to merge FFs on the input or output\n// of a cell into the cell itself.\n//\n// The procedure is:\n//\n// 1. Construct this class (at beginning of processing for a given module).\n// 2. For every considered cell:\n//\n//    a. Call find_output_ff for every considered output.\n//    b. Call find_input_ff for every considered input.\n//    c. Look at the FF description returned (if any) from each call, reject\n//       results that cannot be merged into given cell for any reason.\n//       If both inputs and outputs are being merged, take care of FF bits that\n//       are returned in both input and output results (a FF bit cannot be\n//       merged to both).  Decide on the final set of FF bits to merge.\n//    d. Call remove_output_ff for every find_output_ff result that will be used\n//       for merging.  This removes the actual FF bits from design and from index.\n//    e. Call mark_input_ff for every find_input_ff result that will be used\n//       for merging.  This updates the index disallowing further usage of these\n//       FF bits for output FF merging, if they were eligible before.  The actual\n//       FF bits are still left in the design and can be merged into other inputs.\n//       If the FF bits are not otherwise used, they will be removed by later\n//       opt passes.\n//    f. Merge the FFs into the cell.\n//\n// Note that, if both inputs and outputs are being considered for merging in\n// a single pass, the result may be nondeterministic (depending on cell iteration\n// order) because a given FF bit could be eligible for both input and output merge,\n// perhaps in different cells.  For this reason, it may be a good idea to separate\n// input and output merging.\n\nstruct FfMergeHelper\n{\n\tconst SigMap *sigmap;\n\tRTLIL::Module *module;\n\tFfInitVals *initvals;\n\n\tdict<SigBit, std::pair<Cell*, int>> dff_driver;\n\tdict<SigBit, pool<std::pair<Cell*, int>>> dff_sink;\n\tdict<SigBit, int> sigbit_users_count;\n\n\t// Returns true if all bits in sig are completely unused.\n\tbool is_output_unused(RTLIL::SigSpec sig);\n\n\t// Finds the FF to merge into a given cell output.  Takes sig, which\n\t// is the current cell output — it will be the sig_d of the found FF.\n\t// If found, returns true, and fills the two output arguments.\n\t//\n\t// For every bit of sig, this function finds a FF bit that has\n\t// the same sig_d, and fills the output FfData according to the FF\n\t// bits found.  This function will only consider FF bits that are\n\t// the only user of the given sig bits — if any bit in sig is used\n\t// by anything other than a single FF, this function will return false.\n\t//\n\t// The returned FfData structure does not correspond to any actual FF\n\t// cell in the design — it is the amalgamation of extracted FF bits,\n\t// possibly coming from several FF cells.\n\t//\n\t// If some of the bits in sig have no users at all, this function\n\t// will accept them as well (and fill returned FfData with dummy values\n\t// for the given bit, effectively synthesizing an unused FF bit of the\n\t// appropriate type).  However, if all bits in sig are completely\n\t// unused, this function will fail and return false (having no idea\n\t// what kind of FF to produce) — use the above helper if that case\n\t// is important to handle.\n\t//\n\t// Note that this function does not remove the FF bits returned from\n\t// the design — this is so that the caller can decide whether to accept\n\t// this FF for merging or not.  If the result is accepted,\n\t// remove_output_ff should be called on the second output argument.\n\tbool find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// Like above, but returns a FF to merge into a given cell input.  Takes\n\t// sig_q, which is the current cell input — it will search for FFs with\n\t// matching sig_q.\n\t//\n\t// As opposed to find_output_ff, this function doesn't care about usage\n\t// counts, and may return FF bits that also have other fanout.  This\n\t// should not be a problem for input FF merging.\n\t//\n\t// As a special case, if some of the bits in sig_q are constant, this\n\t// function will accept them as well, by synthesizing in-place\n\t// a constant-input FF bit (with matching initial value and reset value).\n\t// However, this will not work if the input is all-constant — if the caller\n\t// cares about this case, it needs to check for it explicitely.\n\tbool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_output_ff result that will be merged.  This\n\t// marks the given FF bits as used up (and not to be considered for\n\t// further merging as inputs), and reconnects their Q ports to a dummy\n\t// wire (since the wire previously connected there will now be driven\n\t// by the merged-to cell instead).\n\tvoid remove_output_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_input_ff result that will be merged.  This\n\t// marks the given FF bits as used, and disallows merging them as\n\t// outputs.  They can, however, still be merged as inputs again\n\t// (perhaps for another cell).\n\tvoid mark_input_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\tvoid set(FfInitVals *initvals_, RTLIL::Module *module_);\n\n\tvoid clear();\n\n\tFfMergeHelper(FfInitVals *initvals, RTLIL::Module *module) {\n\t\tset(initvals, module);\n\t}\n\n\tFfMergeHelper() {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "fmt.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2020  whitequark <whitequark@whitequark.org>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n//   $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING  = 0,\n\t\tINTEGER = 1,\n\t\tTIME    = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n//   \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tLITERAL  \t= 0,\n\t\tINTEGER \t= 1,\n\t\tSTRING    = 2,\n\t\tUNICHAR   = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign = MINUS;\n\tbool hex_upper = false;\n\tbool show_base = false;\n\tbool group = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_literal(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "gzip.h": "#include <string>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_GZIP_H\n#define YOSYS_GZIP_H\n\nYOSYS_NAMESPACE_BEGIN\n\n#ifdef YOSYS_ENABLE_ZLIB\n\nnamespace Zlib {\n#include <zlib.h>\n}\n\n/*\nAn output stream that uses a stringbuf to buffer data internally,\nusing zlib to write gzip-compressed data every time the stream is flushed.\n*/\nclass gzip_ostream : public std::ostream {\npublic:\n\tgzip_ostream(): std::ostream(nullptr) {\n\t\trdbuf(&outbuf);\n\t}\n\tbool open(const std::string &filename) {\n\t\treturn outbuf.open(filename);\n\t}\nprivate:\n\tclass obuf : public std::stringbuf {\n\tpublic:\n\t\tobuf();\n\t\tbool open(const std::string &filename);\n\t\tvirtual int sync() override;\n\t\tvirtual ~obuf();\n\tprivate:\n\t\tstatic const int buffer_size = 4096;\n\t\tchar buffer[buffer_size];             // Internal buffer for compressed data\n\t\tZlib::gzFile gzf = nullptr;                 // Handle to the gzip file\n\t};\n\n\tobuf outbuf;  // The stream buffer instance\n};\n\n/*\nAn input stream that uses zlib to read gzip-compressed data from a file,\nbuffering the decompressed data internally using its own buffer.\n*/\nclass gzip_istream final : public std::istream {\npublic:\n\tgzip_istream() : std::istream(&inbuf) {}\n\tbool open(const std::string& filename) {\n\t\treturn inbuf.open(filename);\n\t}\nprivate:\n\tclass ibuf final : public std::streambuf {\n\tpublic:\n\t\tibuf() : gzf(nullptr) {}\n\t\tbool open(const std::string& filename);\n\t\tvirtual ~ibuf();\n\n\tprotected:\n\t\t// Called when the buffer is empty and more input is needed\n\t\tvirtual int_type underflow() override;\n\tprivate:\n\t\tstatic const int buffer_size = 8192;\n\t\tchar buffer[buffer_size];\n\t\tZlib::gzFile gzf;\n\t};\n\n\tibuf inbuf;  // The stream buffer instance\n};\n\n#endif // YOSYS_ENABLE_ZLIB\n\nstd::istream* uncompressed(const std::string filename, std::ios_base::openmode mode = std::ios_base::in);\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_GZIP_H\n",
                 "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <variant>\n#include <vector>\n#include <type_traits>\n#include <stdint.h>\n\n#define YS_HASHING_VERSION 1\n\nnamespace hashlib {\n\n/**\n * HASHING\n *\n * Also refer to docs/source/yosys_internals/hashing.rst\n *\n * The Hasher knows how to hash 32 and 64-bit integers. That's it.\n * In the future, it could be expanded to do vectors with SIMD.\n *\n * The Hasher doesn't know how to hash common standard containers\n * and compositions. However, hashlib provides centralized wrappers.\n *\n * Hashlib doesn't know how to hash silly Yosys-specific types.\n * Hashlib doesn't depend on Yosys and can be used standalone.\n * Please don't use hashlib standalone for new projects.\n * Never directly include kernel/hashlib.h in Yosys code.\n * Instead include kernel/yosys_common.h\n *\n * The hash_ops type is now always left to its default value, derived\n * from templated functions through SFINAE. Providing custom ops is\n * still supported.\n *\n * HASH TABLES\n *\n * We implement associative data structures with separate chaining.\n * Linked lists use integers into the indirection hashtable array\n * instead of pointers.\n */\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\nnamespace legacy {\n\tinline uint32_t djb2_add(uint32_t a, uint32_t b) {\n\t\treturn ((a << 5) + a) + b;\n\t}\n};\n\ntemplate<typename T>\nstruct hash_ops;\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\nclass HasherDJB32 {\npublic:\n\tusing hash_t = uint32_t;\n\n\tHasherDJB32() {\n\t\t// traditionally 5381 is used as starting value for the djb2 hash\n\t\tstate = 5381;\n\t}\n\tstatic void set_fudge(hash_t f) {\n\t\tfudge = f;\n\t}\n\nprivate:\n\tuint32_t state;\n\tstatic uint32_t fudge;\n\t// The XOR version of DJB2\n\t[[nodiscard]]\n\tstatic uint32_t djb2_xor(uint32_t a, uint32_t b) {\n\t\tuint32_t hash = ((a << 5) + a) ^ b;\n\t\treturn hash;\n\t}\n\tpublic:\n\tvoid hash32(uint32_t i) {\n\t\tstate = djb2_xor(i, state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\tvoid hash64(uint64_t i) {\n\t\tstate = djb2_xor((uint32_t)(i & 0xFFFFFFFFULL), state);\n\t\tstate = djb2_xor((uint32_t)(i >> 32ULL), state);\n\t\tstate = mkhash_xorshift(fudge ^ state);\n\t\treturn;\n\t}\n\t[[nodiscard]]\n\thash_t yield() {\n\t\treturn (hash_t)state;\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(T&& t) {\n\t\t*this = hash_ops<std::remove_cv_t<std::remove_reference_t<T>>>::hash_into(std::forward<T>(t), *this);\n\t}\n\n\ttemplate<typename T>\n\tvoid eat(const T& t) {\n\t\t*this = hash_ops<T>::hash_into(t, *this);\n\t}\n\n\tvoid commutative_eat(hash_t t) {\n\t\tstate ^= t;\n\t}\n\n\tvoid force(hash_t new_state) {\n\t\tstate = new_state;\n\t}\n};\n\nusing Hasher = HasherDJB32;\n\n// Boilerplate compressor for trivially implementing\n// top-level hash method with hash_into\n#define HASH_TOP_LOOP_FST [[nodiscard]] static inline Hasher hash\n#define HASH_TOP_LOOP_SND { \\\n\tHasher h; \\\n\th = hash_into(a, h); \\\n\treturn h; \\\n}\n\ntemplate<typename T>\nstruct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const T &a, Hasher h) {\n\t\tif constexpr (std::is_integral_v<T>) {\n\t\t\tstatic_assert(sizeof(T) <= sizeof(uint64_t));\n\t\t\tif (sizeof(T) == sizeof(uint64_t))\n\t\t\t\th.hash64(a);\n\t\t\telse\n\t\t\t\th.hash32(a);\n\t\t\treturn h;\n\t\t} else if constexpr (std::is_enum_v<T>) {\n\t\t\tusing u_type = std::underlying_type_t<T>;\n\t\t\treturn hash_ops<u_type>::hash_into((u_type) a, h);\n\t\t} else if constexpr (std::is_pointer_v<T>) {\n\t\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t) a, h);\n\t\t} else if constexpr (std::is_same_v<T, std::string>) {\n\t\t\tfor (auto c : a)\n\t\t\t\th.hash32(c);\n\t\t\treturn h;\n\t\t} else {\n\t\t\treturn a.hash_into(h);\n\t\t}\n\t}\n\tHASH_TOP_LOOP_FST (const T &a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::pair<P, Q> a, Hasher h) {\n\t\th = hash_ops<P>::hash_into(a.first, h);\n\t\th = hash_ops<Q>::hash_into(a.second, h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::pair<P, Q> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), Hasher>::type hash_into(std::tuple<T...>, Hasher h) {\n\t\treturn h;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), Hasher>::type hash_into(std::tuple<T...> a, Hasher h) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\th = hash_into<I+1>(a, h);\n\t\th = element_ops_t::hash_into(std::get<I>(a), h);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::tuple<T...> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::vector<T> a, Hasher h) {\n\t\th.eat((uint32_t)a.size());\n\t\tfor (auto k : a)\n\t\t\th.eat(k);\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (std::vector<T> a) HASH_TOP_LOOP_SND\n};\n\ntemplate<typename T, size_t N> struct hash_ops<std::array<T, N>> {\n    static inline bool cmp(std::array<T, N> a, std::array<T, N> b) {\n        return a == b;\n    }\n    [[nodiscard]] static inline Hasher hash_into(std::array<T, N> a, Hasher h) {\n        for (const auto& k : a)\n            h = hash_ops<T>::hash_into(k, h);\n        return h;\n    }\n\tHASH_TOP_LOOP_FST (std::array<T, N> a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\treturn strcmp(a, b) == 0;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const char *a, Hasher h) {\n\t\twhile (*a)\n\t\t\th.hash32(*(a++));\n\t\treturn h;\n\t}\n\tHASH_TOP_LOOP_FST (const char *a) HASH_TOP_LOOP_SND\n};\n\ntemplate <> struct hash_ops<char*> : hash_cstr_ops {};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(const void *a, Hasher h) {\n\t\treturn hash_ops<uintptr_t>::hash_into((uintptr_t)a, h);\n\t}\n\tHASH_TOP_LOOP_FST (const void *a) HASH_TOP_LOOP_SND\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\t[[nodiscard]] static inline Hasher hash_into(const T *a, Hasher h) {\n\t\tif (a)\n\t\t\th = a->hash_into(h);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n\ttemplate<typename T>\n\tHASH_TOP_LOOP_FST (const T *a) HASH_TOP_LOOP_SND\n};\n/**\n * If you find yourself using this function, think hard\n * about if it's the right thing to do. Mixing finalized\n * hashes together with XORs or worse can destroy\n * desirable qualities of the hash function\n */\ntemplate<typename T>\n[[nodiscard]]\nHasher::hash_t run_hash(const T& obj) {\n\treturn hash_ops<T>::hash(obj).yield();\n}\n\n/** Refer to docs/source/yosys_internals/hashing.rst */\ntemplate<typename T>\n[[nodiscard]]\n[[deprecated]]\ninline unsigned int mkhash(const T &v) {\n\treturn (unsigned int) run_hash<T>(v);\n}\n\ntemplate<> struct hash_ops<std::monostate> {\n\tstatic inline bool cmp(std::monostate a, std::monostate b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::monostate, Hasher h) {\n\t\treturn h;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::variant<T...>> {\n\tstatic inline bool cmp(std::variant<T...> a, std::variant<T...> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::variant<T...> a, Hasher h) {\n\t\tstd::visit([& h](const auto &v) { h.eat(v); }, a);\n\t\th.eat(a.index());\n\t\treturn h;\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::optional<T>> {\n\tstatic inline bool cmp(std::optional<T> a, std::optional<T> b) {\n\t\treturn a == b;\n\t}\n\t[[nodiscard]] static inline Hasher hash_into(std::optional<T> a, Hasher h) {\n\t\tif(a.has_value())\n\t\t\th.eat(*a);\n\t\telse\n\t\t\th.eat(0);\n\t\treturn h;\n\t}\n};\n\ninline unsigned int hashtable_size(unsigned int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<unsigned int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713, 2211715897, 2764644887, 3455806139\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(unsigned int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict {\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto &it : entries) {\n\t\t\tHasher entry_hash;\n\t\t\tentry_hash.eat(it.udata.first);\n\t\t\tentry_hash.eat(it.udata.second);\n\t\t\th.commutative_eat(entry_hash.yield());\n\t\t}\n\t\th.eat(entries.size());\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tHasher::hash_t do_hash(const K &key) const\n\t{\n\t\tHasher::hash_t hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key).yield() % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tHasher::hash_t hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, Hasher::hash_t hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tHasher::hash_t back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, Hasher::hash_t &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, Hasher::hash_t &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tHasher::hash_t hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tHasher::hash_t hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tHasher::hash_t hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tHasher::hash_t hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\tfor (auto &it : entries) {\n\t\t\th.commutative_eat(ops.hash(it.udata).yield());\n\t\t}\n\t\th.eat(entries.size());\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tHasher::hash_t hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
+                "io.h": "#include <string>\n#include <stdarg.h>\n#include \"kernel/yosys_common.h\"\n\n#ifndef YOSYS_IO_H\n#define YOSYS_IO_H\n\nYOSYS_NAMESPACE_BEGIN\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n\t// For the common case of strings shorter than 128, save a heap\n\t// allocation by using a stack allocated buffer.\n\tconst int kBufSize = 128;\n\tchar buf[kBufSize];\n\tbuf[0] = '\\0';\n\tva_list apc;\n\tva_copy(apc, ap);\n\tint n = vsnprintf(buf, kBufSize, fmt, apc);\n\tva_end(apc);\n\tif (n < kBufSize)\n\t\treturn std::string(buf);\n\n\tstd::string string;\n\tchar *str = NULL;\n#if defined(_WIN32) || defined(__CYGWIN__)\n\tint sz = 2 * kBufSize, rc;\n\twhile (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char *)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n\tif (vasprintf(&str, fmt, ap) < 0)\n\t\tstr = NULL;\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nYOSYS_NAMESPACE_END\n\n#endif // YOSYS_IO_H\n",
                 "json.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n    enum Scope {\n        VALUE,\n        OBJECT_FIRST,\n        OBJECT,\n        ARRAY_FIRST,\n        ARRAY,\n    };\n\n    struct Target {\n        virtual void emit(const char *data) = 0;\n        virtual void flush() {};\n        virtual ~Target() {};\n    };\n\n    std::string newline_indent = \"\\n\";\n    std::vector<std::unique_ptr<Target>> targets;\n    std::vector<Scope> state = {VALUE};\n    int compact_depth = INT_MAX;\npublic:\n\n    void emit_to_log();\n    void append_to_string(std::string &target);\n    bool write_to_file(const std::string &path);\n\n    bool active() { return !targets.empty(); }\n\n    void compact() { compact_depth = GetSize(state); }\n\n    void line(bool space_if_inline = true);\n    void raw(const char *raw_json);\n    void flush();\n    void begin_object();\n    void begin_array();\n    void end_object();\n    void end_array();\n    void name(const char *name);\n    void begin_value();\n    void end_value();\n    void value_json(const Json &value);\n    void value(unsigned int value) { value_json(Json((int)value)); }\n    template<typename T>\n    void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n    void entry_json(const char *name, const Json &value);\n    void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n    template<typename T>\n    void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n    template<typename T>\n    void object(const T &&values)\n    {\n        begin_object();\n        for (auto &item : values)\n            entry(item.first, item.second);\n        end_object();\n    }\n\n    template<typename T>\n    void array(const T &&values)\n    {\n        begin_object();\n        for (auto &item : values)\n            value(item);\n        end_object();\n    }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "log.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n#  include <intrin.h>\n#else\n#  include <sys/time.h>\n#  include <sys/resource.h>\n#  if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n#    include <signal.h>\n#  endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n#  define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n#  define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n#  define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n#  define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n#  define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...)  YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n#  define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\nconst char *log_str(const char *str);\nconst char *log_str(std::string const &str);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n#  define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n#  define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n    static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n    __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n#  define cover(...) do { } while (0)\n#  define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n#  ifdef _WIN32\n\t\treturn 0;\n#  elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n#  else\n#    error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n#  endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T> static inline void log_dump_val_worker(dict<K, T> &v);\ntemplate<typename K> static inline void log_dump_val_worker(pool<K> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T>\nstatic inline void log_dump_val_worker(dict<K, T> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(pool<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
-                "macc.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct port_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\tstd::vector<port_t> ports;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<port_t> new_ports;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tif (off.as_bool()) {\n\t\t\tport_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tnew_ports.swap(ports);\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tports.clear();\n\n\t\tauto config_bits = cell->getParam(ID::CONFIG);\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tport_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tports.push_back(this_port);\n\t\t}\n\n\t\tfor (auto bit : cell->getPort(ID::B))\n\t\t\tports.push_back(port_t{{bit}, {}, false, false});\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell) const\n\t{\n\t\tRTLIL::SigSpec port_a;\n\t\tstd::vector<RTLIL::State> config_bits;\n\t\tint max_size = 0, num_bits = 0;\n\n\t\tfor (auto &port : ports) {\n\t\t\tmax_size = max(max_size, GetSize(port.in_a));\n\t\t\tmax_size = max(max_size, GetSize(port.in_b));\n\t\t}\n\n\t\twhile (max_size)\n\t\t\tnum_bits++, max_size /= 2;\n\n\t\tlog_assert(num_bits < 16);\n\t\tconfig_bits.push_back(num_bits & 1 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 2 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 4 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 8 ? State::S1 : State::S0);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tconfig_bits.push_back(port.is_signed ? State::S1 : State::S0);\n\t\t\tconfig_bits.push_back(port.do_subtract ? State::S1 : State::S0);\n\n\t\t\tint size_a = GetSize(port.in_a);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tint size_b = GetSize(port.in_b);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tport_a.append(port.in_a);\n\t\t\tport_a.append(port.in_b);\n\t\t}\n\n\t\tcell->setPort(ID::A, port_a);\n\t\tcell->setPort(ID::B, {});\n\t\tcell->setParam(ID::CONFIG, config_bits);\n\t\tcell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));\n\t\tcell->setParam(ID::A_WIDTH, GetSize(port_a));\n\t\tcell->setParam(ID::B_WIDTH, 0);\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits())\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool is_simple_product()\n\t{\n\t\treturn ports.size() == 1 &&\n\t\t\t\t!ports[0].in_b.empty() &&\n\t\t\t\t!ports[0].do_subtract;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "macc.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct port_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\tstd::vector<port_t> ports;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<port_t> new_ports;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tif (off.as_bool()) {\n\t\t\tport_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tnew_ports.swap(ports);\n\t}\n\n\tvoid from_cell_v1(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tports.clear();\n\n\t\tauto config_bits = cell->getParam(ID::CONFIG);\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tport_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tports.push_back(this_port);\n\t\t}\n\n\t\tfor (auto bit : cell->getPort(ID::B))\n\t\t\tports.push_back(port_t{{bit}, {}, false, false});\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (cell->type == ID($macc)) {\n\t\t\tfrom_cell_v1(cell);\n\t\t\treturn;\n\t\t}\n\t\tlog_assert(cell->type == ID($macc_v2));\n\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\t\tRTLIL::SigSpec port_b = cell->getPort(ID::B);\n\t\tRTLIL::SigSpec port_c = cell->getPort(ID::C);\n\n\t\tports.clear();\n\n\t\tint nproducts = cell->getParam(ID::NPRODUCTS).as_int();\n\t\tconst Const &product_neg = cell->getParam(ID::PRODUCT_NEGATED);\n\t\tconst Const &a_widths = cell->getParam(ID::A_WIDTHS);\n\t\tconst Const &b_widths = cell->getParam(ID::B_WIDTHS);\n\t\tconst Const &a_signed = cell->getParam(ID::A_SIGNED);\n\t\tconst Const &b_signed = cell->getParam(ID::B_SIGNED);\n\t\tint ai = 0, bi = 0;\n\t\tfor (int i = 0; i < nproducts; i++) {\n\t\t\tport_t term;\n\n\t\t\tlog_assert(a_signed[i] == b_signed[i]);\n\t\t\tterm.is_signed = (a_signed[i] == State::S1);\n\t\t\tint a_width = a_widths.extract(16 * i, 16).as_int(false);\n\t\t\tint b_width = b_widths.extract(16 * i, 16).as_int(false);\n\n\t\t\tterm.in_a = port_a.extract(ai, a_width);\n\t\t\tai += a_width;\n\t\t\tterm.in_b = port_b.extract(bi, b_width);\n\t\t\tbi += b_width;\n\t\t\tterm.do_subtract = (product_neg[i] == State::S1);\n\n\t\t\tports.push_back(term);\n\t\t}\n\t\tlog_assert(port_a.size() == ai);\n\t\tlog_assert(port_b.size() == bi);\n\n\t\tint naddends = cell->getParam(ID::NADDENDS).as_int();\n\t\tconst Const &addend_neg = cell->getParam(ID::ADDEND_NEGATED);\n\t\tconst Const &c_widths = cell->getParam(ID::C_WIDTHS);\n\t\tconst Const &c_signed = cell->getParam(ID::C_SIGNED);\n\t\tint ci = 0;\n\t\tfor (int i = 0; i < naddends; i++) {\n\t\t\tport_t term;\n\n\t\t\tterm.is_signed = (c_signed[i] == State::S1);\n\t\t\tint c_width = c_widths.extract(16 * i, 16).as_int(false);\n\n\t\t\tterm.in_a = port_c.extract(ci, c_width);\n\t\t\tci += c_width;\n\t\t\tterm.do_subtract = (addend_neg[i] == State::S1);\n\n\t\t\tports.push_back(term);\n\t\t}\n\t\tlog_assert(port_c.size() == ci);\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell)\n\t{\n\t\tcell->type = ID($macc_v2);\n\n\t\tint nproducts = 0, naddends = 0;\n\t\tConst a_signed, b_signed, a_widths, b_widths, product_negated;\n\t\tConst c_signed, c_widths, addend_negated;\n\t\tSigSpec a, b, c;\n\n\t\tfor (int i = 0; i < (int) ports.size(); i++) {\n\t\t\tSigSpec term_a = ports[i].in_a, term_b = ports[i].in_b;\n\n\t\t\tif (term_b.empty()) {\n\t\t\t\t// addend\n\t\t\t\tc_widths.append(Const(term_a.size(), 16));\n\t\t\t\tc_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\taddend_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tc.append(term_a);\n\t\t\t\tnaddends++;\n\t\t\t} else {\n\t\t\t\t// product\n\t\t\t\ta_widths.append(Const(term_a.size(), 16));\n\t\t\t\tb_widths.append(Const(term_b.size(), 16));\n\t\t\t\ta_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tb_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\tproduct_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0);\n\t\t\t\ta.append(term_a);\n\t\t\t\tb.append(term_b);\n\t\t\t\tnproducts++;\n\t\t\t}\n\t\t}\n\n\t\tif (a_signed.empty())\n\t\t\ta_signed = {RTLIL::Sx};\n\t\tif (b_signed.empty())\n\t\t\tb_signed = {RTLIL::Sx};\n\t\tif (c_signed.empty())\n\t\t\tc_signed = {RTLIL::Sx};\n\t\tif (a_widths.empty())\n\t\t\ta_widths = {RTLIL::Sx};\n\t\tif (b_widths.empty())\n\t\t\tb_widths = {RTLIL::Sx};\n\t\tif (c_widths.empty())\n\t\t\tc_widths = {RTLIL::Sx};\n\t\tif (product_negated.empty())\n\t\t\tproduct_negated = {RTLIL::Sx};\n\t\tif (addend_negated.empty())\n\t\t\taddend_negated = {RTLIL::Sx};\n\n\t\tcell->setParam(ID::NPRODUCTS, nproducts);\n\t\tcell->setParam(ID::PRODUCT_NEGATED, product_negated);\n\t\tcell->setParam(ID::NADDENDS, naddends);\n\t\tcell->setParam(ID::ADDEND_NEGATED, addend_negated);\n\t\tcell->setParam(ID::A_SIGNED, a_signed);\n\t\tcell->setParam(ID::B_SIGNED, b_signed);\n\t\tcell->setParam(ID::C_SIGNED, c_signed);\n\t\tcell->setParam(ID::A_WIDTHS, a_widths);\n\t\tcell->setParam(ID::B_WIDTHS, b_widths);\n\t\tcell->setParam(ID::C_WIDTHS, c_widths);\n\t\tcell->setPort(ID::A, a);\n\t\tcell->setPort(ID::B, b);\n\t\tcell->setPort(ID::C, c);\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits())\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool is_simple_product()\n\t{\n\t\treturn ports.size() == 1 &&\n\t\t\t\t!ports[0].in_b.empty() &&\n\t\t\t\t!ports[0].do_subtract;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "mem.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2020  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MEM_H\n#define MEM_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n#include \"kernel/utils.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct MemRd : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity, ce_over_srst;\n\tConst arst_value, srst_value, init_value;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will bypass the written data\n\t// to this port's output (default behavior is to read old value).\n\t// Can only be set for write ports that have the same clock domain.\n\tstd::vector<bool> transparency_mask;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will return an all-X (don't care)\n\t// value.  Mutually exclusive with transparency_mask.\n\t// Can only be set for write ports that have the same clock domain.\n\t// For optimization purposes, this will also be set if we can\n\t// determine that the two ports can never be active simultanously\n\t// (making the above vacuously true).\n\tstd::vector<bool> collision_x_mask;\n\tSigSpec clk, en, arst, srst, addr, data;\n\n\tMemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n};\n\nstruct MemWr : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity;\n\tstd::vector<bool> priority_mask;\n\tSigSpec clk, en, addr, data;\n\n\tMemWr() : removed(false), cell(nullptr) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n\n\tstd::pair<SigSpec, std::vector<int>> compress_en();\n\tSigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig);\n};\n\nstruct MemInit : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tConst addr;\n\tConst data;\n\tConst en;\n\tMemInit() : removed(false), cell(nullptr) {}\n};\n\nstruct Mem : RTLIL::AttrObject {\n\tModule *module;\n\tIdString memid;\n\tbool packed;\n\tRTLIL::Memory *mem;\n\tCell *cell;\n\tint width, start_offset, size;\n\tstd::vector<MemInit> inits;\n\tstd::vector<MemRd> rd_ports;\n\tstd::vector<MemWr> wr_ports;\n\n\t// Removes this memory from the module.  The data in helper structures\n\t// is unaffected except for the cell/mem fields.\n\tvoid remove();\n\n\t// Commits all changes in helper structures into the module — ports and\n\t// inits marked as removed are actually removed, new ports/inits create\n\t// new cells, modified port/inits are commited into their existing\n\t// cells.  Note that this reindexes the ports and inits array (actually\n\t// removing the ports/inits marked as removed).\n\tvoid emit();\n\n\t// Marks all inits as removed.\n\tvoid clear_inits();\n\n\t// Coalesces inits: whenever two inits have overlapping or touching\n\t// address ranges, they are combined into one, with the higher-priority\n\t// one's data overwriting the other.  Running this results in\n\t// an inits list equivalent to the original, in which all entries\n\t// cover disjoint (and non-touching) address ranges, and all enable\n\t// masks are all-1.\n\tvoid coalesce_inits();\n\n\t// Checks consistency of this memory and all its ports/inits, using\n\t// log_assert.\n\tvoid check();\n\n\t// Gathers all initialization data into a single big const covering\n\t// the whole memory.  For all non-initialized bits, Sx will be returned.\n\tConst get_init_data() const;\n\n\t// Constructs and returns the helper structures for all memories\n\t// in a module.\n\tstatic std::vector<Mem> get_all_memories(Module *module);\n\n\t// Constructs and returns the helper structures for all selected\n\t// memories in a module.\n\tstatic std::vector<Mem> get_selected_memories(Module *module);\n\n\t// Converts a synchronous read port into an asynchronous one by\n\t// extracting the data (or, in some rare cases, address) register\n\t// into a separate cell, together with any soft-transparency\n\t// logic necessary to preserve its semantics.  Returns the created\n\t// register cell, if any.  Note that in some rare cases this function\n\t// may succeed and perform a conversion without creating a new\n\t// register — a nullptr result doesn't imply nothing was done.\n\tCell *extract_rdff(int idx, FfInitVals *initvals);\n\n\t// Splits all wide ports in this memory into equivalent narrow ones.\n\t// This function performs no modifications at all to the actual\n\t// netlist unless and until emit() is called.\n\tvoid narrow();\n\n\t// If write port idx2 currently has priority over write port idx1,\n\t// inserts extra logic on idx1's enable signal to disable writes\n\t// when idx2 is writing to the same address, then removes the priority\n\t// from the priority mask.  If there is a memory port that is\n\t// transparent with idx1, but not with idx2, that port is converted\n\t// to use soft transparency logic.\n\tvoid emulate_priority(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Creates soft-transparency logic on read port ridx, bypassing the\n\t// data from write port widx.  Should only be called when ridx is\n\t// transparent wrt widx in the first place.  Once we're done, the\n\t// transparency_mask bit will be cleared, and the collision_x_mask\n\t// bit will be set instead (since whatever value is read will be\n\t// replaced by the soft transparency logic).\n\tvoid emulate_transparency(int widx, int ridx, FfInitVals *initvals);\n\n\t// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).\n\t// Specifically, takes care of priority masks: any priority relations\n\t// that idx2 had are replicated onto idx1, unless they conflict with\n\t// priorities already present on idx1, in which case emulate_priority\n\t// is called.  Likewise, ensures transparency and undefined collision\n\t// masks of all read ports have the same values for both ports,\n\t// calling emulate_transparency if necessary.\n\tvoid prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares for merging read port idx2 into idx1.\n\t// Specifically, makes sure the transparency and undefined collision\n\t// masks of both ports are equal, by changing undefined behavior\n\t// of one port to the other's defined behavior, or by calling\n\t// emulate_transparency if necessary.\n\tvoid prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares the memory for widening a port to a given width.  This\n\t// involves ensuring that start_offset and size are aligned to the\n\t// target width.\n\tvoid widen_prep(int wide_log2);\n\n\t// Widens a write port up to a given width.  The newly port is\n\t// equivalent to the original, made by replicating enable/data bits\n\t// and masking enable bits with decoders on the low part of the\n\t// original address.\n\tvoid widen_wr_port(int idx, int wide_log2);\n\n\t// Emulates a sync read port's enable functionality in soft logic,\n\t// changing the actual read port's enable to be always-on.\n\tvoid emulate_rden(int idx, FfInitVals *initvals);\n\n\t// Emulates a sync read port's initial/reset value functionality in\n\t// soft logic, removing it from the actual read port.\n\tvoid emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals);\n\n\t// Given a read port with ce_over_srst set, converts it to a port\n\t// with ce_over_srst unset without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_ce_over_srst(int idx);\n\n\t// Given a read port with ce_over_srst unset, converts it to a port\n\t// with ce_over_srst set without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_srst_over_ce(int idx);\n\n\t// Returns true iff emulate_read_first makes sense to call.\n\tbool emulate_read_first_ok();\n\n\t// Emulates all read-first read-write port relationships in terms of\n\t// all-transparent ports, by delaying all write ports by one cycle.\n\t// This can only be used when all read ports and all write ports are\n\t// in the same clock domain.\n\tvoid emulate_read_first(FfInitVals *initvals);\n\n\tMem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}\n};\n\n// MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined\nclass MemContents {\npublic:\n\tclass range; class iterator;\n\tusing addr_t = uint32_t;\nprivate:\n\t// we ban _addr_width == sizeof(addr_t) * 8 because it adds too many cornercases\n\tint _addr_width;\n\tint _data_width;\n\tRTLIL::Const _default_value;\n\t// for each range, store the concatenation of the words at the start address\n\t// invariants:\n\t// - no overlapping or adjacent ranges\n\t// - no empty ranges\n\t// - all Consts are a multiple of the word size\n\tstd::map<addr_t, RTLIL::Const> _values;\n\t// returns an iterator to the range containing addr, if it exists, or the first range past addr\n\tstd::map<addr_t, RTLIL::Const>::iterator _range_at(addr_t addr) const;\n\taddr_t _range_size(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->second.size() / _data_width; }\n\taddr_t _range_begin(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->first; }\n\taddr_t _range_end(std::map<addr_t, RTLIL::Const>::iterator it) const { return _range_begin(it) + _range_size(it); }\n\t// check if the iterator points to a range containing addr\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const;\n\t// check if the iterator points to a range containing [begin_addr, end_addr). assumes end_addr >= begin_addr.\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// check if the iterator points to a range overlapping with [begin_addr, end_addr)\n\tbool _range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// return the offset the addr would have in the range at `it`\n\tsize_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }\n\t// assuming _range_contains(it, addr), return an iterator pointing to the data at addr\n\tstd::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits().begin() + _range_offset(it, addr); }\n\t// internal version of reserve_range that returns an iterator to the range\n\tstd::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);\n\t// write a single word at addr, return iterator to next word\n\tstd::vector<State>::iterator _range_write(std::vector<State>::iterator it, RTLIL::Const const &data);\npublic:\n\tclass range {\n\t\tint _data_width;\n\t\taddr_t _base;\n\t\tRTLIL::Const const &_values;\n\t\tfriend class iterator;\n\t\trange(int data_width, addr_t base, RTLIL::Const const &values)\n\t\t: _data_width(data_width), _base(base), _values(values) {}\n\tpublic:\n\t\taddr_t base() const { return _base; }\n\t\taddr_t size() const { return ((addr_t) _values.size()) / _data_width; }\n\t\taddr_t limit() const { return _base + size(); }\n\t\tRTLIL::Const const &concatenated() const { return _values; }\n\t\tRTLIL::Const operator[](addr_t addr) const {\n\t\t\tlog_assert(addr - _base < size());\n\t\t\treturn _values.extract((addr - _base) * _data_width, _data_width);\n\t\t}\n\t\tRTLIL::Const at_offset(addr_t offset) const { return (*this)[_base + offset]; }\n\t};\n\tclass iterator {\n\t\tMemContents const *_memory;\n\t\t// storing addr instead of an iterator gives more well-defined behaviour under insertions/deletions\n\t\t// use ~0 for end so that all end iterators compare the same\n\t\taddr_t _addr;\n\t\tfriend class MemContents;\n\t\titerator(MemContents const *memory, addr_t addr) : _memory(memory), _addr(addr) {}\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = range;\n\t\tusing pointer = arrow_proxy<range>;\n\t\tusing reference = range;\n\t\tusing difference_type = addr_t;\n\t\treference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); }\n\t\tpointer operator->() const { return arrow_proxy<range>(**this); }\n\t\tbool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; }\n\t\tbool operator ==(iterator const &other) const { return !(*this != other); }\n\t\titerator &operator++();\n\t};\n\tMemContents(int addr_width, int data_width, RTLIL::Const default_value)\n\t\t: _addr_width(addr_width), _data_width(data_width)\n\t\t, _default_value((default_value.extu(data_width), std::move(default_value)))\n\t{ log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); log_assert(_data_width > 0); }\n\tMemContents(int addr_width, int data_width) : MemContents(addr_width, data_width, RTLIL::Const(State::Sx, data_width)) {}\n\texplicit MemContents(Mem *mem);\n\tint addr_width() const { return _addr_width; }\n\tint data_width() const { return _data_width; }\n\tRTLIL::Const const &default_value() const { return _default_value; }\n\t// return the value at the address if it exists, the default_value of the memory otherwise. address must not exceed 2**addr_width.\n\tRTLIL::Const operator [](addr_t addr) const;\n\t// return the number of defined words in the range [begin_addr, end_addr)\n\taddr_t count_range(addr_t begin_addr, addr_t end_addr) const;\n\t// allocate memory for the range [begin_addr, end_addr), but leave the contents undefined.\n\tvoid reserve_range(addr_t begin_addr, addr_t end_addr) { _reserve_range(begin_addr, end_addr); }\n\t// insert multiple words (provided as a single concatenated RTLIL::Const) at the given address, overriding any previous assignment.\n\tvoid insert_concatenated(addr_t addr, RTLIL::Const const &values);\n\t// insert multiple words at the given address, overriding any previous assignment.\n\ttemplate<typename Iterator> void insert_range(addr_t addr, Iterator begin, Iterator end) {\n\t\tauto words = end - begin;\n\t\tlog_assert(addr < (addr_t)(1<<_addr_width)); log_assert(words <= (addr_t)(1<<_addr_width) - addr);\n\t\tauto range = _reserve_range(addr, addr + words);\n\t\tauto it = _range_data(range, addr);\n\t\tfor(; begin != end; ++begin)\n\t\t\tit = _range_write(it, *begin);\n\t}\n\t// undefine all words in the range [begin_addr, end_addr)\n\tvoid clear_range(addr_t begin_addr, addr_t end_addr);\n\t// check invariants, abort if invariants failed\n\tvoid check();\n\titerator end() const { return iterator(nullptr, ~(addr_t) 0); }\n\titerator begin() const { return _values.empty() ? end() : iterator(this, _values.begin()->first); }\n\tbool empty() const { return _values.empty(); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "modtools.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MODTOOLS_H\n#define MODTOOLS_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ModIndex : public RTLIL::Monitor\n{\n\tstruct PortInfo {\n\t\tRTLIL::Cell* cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tPortInfo() : cell(), port(), offset() { }\n\t\tPortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }\n\n\t\tbool operator<(const PortInfo &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (offset != other.offset)\n\t\t\t\treturn offset < other.offset;\n\t\t\treturn port < other.port;\n\t\t}\n\n\t\tbool operator==(const PortInfo &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tstruct SigBitInfo\n\t{\n\t\tbool is_input, is_output;\n\t\tpool<PortInfo> ports;\n\n\t\tSigBitInfo() : is_input(false), is_output(false) { }\n\n\t\tbool operator==(const SigBitInfo &other) const {\n\t\t\treturn is_input == other.is_input && is_output == other.is_output && ports == other.ports;\n\t\t}\n\n\t\tvoid merge(const SigBitInfo &other)\n\t\t{\n\t\t\tis_input = is_input || other.is_input;\n\t\t\tis_output = is_output || other.is_output;\n\t\t\tports.insert(other.ports.begin(), other.ports.end());\n\t\t}\n\t};\n\n\tSigMap sigmap;\n\tRTLIL::Module *module;\n\tstd::map<RTLIL::SigBit, SigBitInfo> database;\n\tint auto_reload_counter;\n\tbool auto_reload_module;\n\n\tvoid port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.insert(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tvoid port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.erase(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tconst SigBitInfo &info(RTLIL::SigBit bit)\n\t{\n\t\treturn database[sigmap(bit)];\n\t}\n\n\tvoid reload_module(bool reset_sigmap = true)\n\t{\n\t\tif (reset_sigmap) {\n\t\t\tsigmap.clear();\n\t\t\tsigmap.set(module);\n\t\t}\n\n\t\tdatabase.clear();\n\t\tfor (auto wire : module->wires())\n\t\t\tif (wire->port_input || wire->port_output)\n\t\t\t\tfor (int i = 0; i < GetSize(wire); i++) {\n\t\t\t\t\tRTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));\n\t\t\t\t\tif (bit.wire && wire->port_input)\n\t\t\t\t\t\tdatabase[bit].is_input = true;\n\t\t\t\t\tif (bit.wire && wire->port_output)\n\t\t\t\t\t\tdatabase[bit].is_output = true;\n\t\t\t\t}\n\t\tfor (auto cell : module->cells())\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tport_add(cell, conn.first, conn.second);\n\n\t\tif (auto_reload_module) {\n\t\t\tif (++auto_reload_counter > 2)\n\t\t\t\tlog_warning(\"Auto-reload in ModIndex -- possible performance bug!\\n\");\n\t\t\tauto_reload_module = false;\n\t\t}\n\t}\n\n\tvoid check()\n\t{\n#ifndef NDEBUG\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (auto it : database)\n\t\t\tlog_assert(it.first == sigmap(it.first));\n\n\t\tauto database_bak = std::move(database);\n\t\treload_module(false);\n\n\t\tif (!(database == database_bak))\n\t\t{\n\t\t\tfor (auto &it : database_bak)\n\t\t\t\tif (!database.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database_bak, not database: %s\\n\", log_signal(it.first));\n\n\t\t\tfor (auto &it : database)\n\t\t\t\tif (!database_bak.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database, not database_bak: %s\\n\", log_signal(it.first));\n\t\t\t\telse if (!(it.second == database_bak.at(it.first)))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Different content for database[%s].\\n\", log_signal(it.first));\n\n\t\t\tlog_assert(database == database_bak);\n\t\t}\n#endif\n\t}\n\n\tvoid notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override\n\t{\n\t\tlog_assert(module == cell->module);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tport_del(cell, port, old_sig);\n\t\tport_add(cell, port, sig);\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override\n\t{\n\t\tlog_assert(module == mod);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (int i = 0; i < GetSize(sigsig.first); i++)\n\t\t{\n\t\t\tRTLIL::SigBit lhs = sigmap(sigsig.first[i]);\n\t\t\tRTLIL::SigBit rhs = sigmap(sigsig.second[i]);\n\t\t\tbool has_lhs = database.count(lhs) != 0;\n\t\t\tbool has_rhs = database.count(rhs) != 0;\n\n\t\t\tif (!has_lhs && !has_rhs) {\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t} else\n\t\t\tif (!has_rhs) {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\tlhs = sigmap(lhs);\n\t\t\t\tif (lhs.wire)\n\t\t\t\t\tdatabase[lhs] = new_info;\n\t\t\t} else\n\t\t\tif (!has_lhs) {\n\t\t\t\tSigBitInfo new_info = database.at(rhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t} else {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tnew_info.merge(database.at(rhs));\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tvoid notify_blackout(RTLIL::Module *mod) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)\n\t{\n\t\tauto_reload_counter = 0;\n\t\tauto_reload_module = true;\n\t\tmodule->monitors.insert(this);\n\t}\n\n\t~ModIndex()\n\t{\n\t\tmodule->monitors.erase(this);\n\t}\n\n\tSigBitInfo *query(RTLIL::SigBit bit)\n\t{\n\t\tif (auto_reload_module)\n\t\t\treload_module();\n\n\t\tauto it = database.find(sigmap(bit));\n\t\tif (it == database.end())\n\t\t\treturn nullptr;\n\t\telse\n\t\t\treturn &it->second;\n\t}\n\n\tbool query_is_input(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_input;\n\t}\n\n\tbool query_is_output(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_output;\n\t}\n\n\tpool<PortInfo> &query_ports(RTLIL::SigBit bit)\n\t{\n\t\tstatic pool<PortInfo> empty_result_set;\n\t\tSigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn empty_result_set;\n\t\treturn info->ports;\n\t}\n\n\tvoid dump_db()\n\t{\n\t\tlog(\"--- ModIndex Dump ---\\n\");\n\n\t\tif (auto_reload_module) {\n\t\t\tlog(\"AUTO-RELOAD\\n\");\n\t\t\treload_module();\n\t\t}\n\n\t\tfor (auto &it : database) {\n\t\t\tlog(\"BIT %s:\\n\", log_signal(it.first));\n\t\t\tif (it.second.is_input)\n\t\t\t\tlog(\"  PRIMARY INPUT\\n\");\n\t\t\tif (it.second.is_output)\n\t\t\t\tlog(\"  PRIMARY OUTPUT\\n\");\n\t\t\tfor (auto &port : it.second.ports)\n\t\t\t\tlog(\"  PORT: %s.%s[%d] (%s)\\n\", log_id(port.cell),\n\t\t\t\t\t\tlog_id(port.port), port.offset, log_id(port.cell->type));\n\t\t}\n\t}\n};\n\nstruct ModWalker\n{\n\tstruct PortBit\n\t{\n\t\tRTLIL::Cell *cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\t\tPortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}\n\n\t\tbool operator<(const PortBit &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (port != other.port)\n\t\t\t\treturn port < other.port;\n\t\t\treturn offset < other.offset;\n\t\t}\n\n\t\tbool operator==(const PortBit &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tRTLIL::Design *design;\n\tRTLIL::Module *module;\n\n\tCellTypes ct;\n\tSigMap sigmap;\n\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_drivers;\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_consumers;\n\tpool<RTLIL::SigBit> signal_inputs, signal_outputs;\n\n\tdict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;\n\n\tvoid add_wire(RTLIL::Wire *wire)\n\t{\n\t\tif (wire->port_input) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_inputs.insert(bit);\n\t\t}\n\n\t\tif (wire->port_output) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_outputs.insert(bit);\n\t\t}\n\t}\n\n\tvoid add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)\n\t{\n\t\tfor (int i = 0; i < int(bits.size()); i++)\n\t\t\tif (bits[i].wire != NULL) {\n\t\t\t\tPortBit pbit {cell, port, i};\n\t\t\t\tif (is_output) {\n\t\t\t\t\tsignal_drivers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_outputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t\tif (is_input) {\n\t\t\t\t\tsignal_consumers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_inputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\tvoid add_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (ct.cell_known(cell->type)) {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second),\n\t\t\t\t\t\tct.cell_output(cell->type, conn.first),\n\t\t\t\t\t\tct.cell_input(cell->type, conn.first));\n\t\t} else {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second), true, true);\n\t\t}\n\t}\n\n\tModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)\n\t{\n\t\tct.setup(design);\n\t\tif (module)\n\t\t\tsetup(module);\n\t}\n\n\tvoid setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)\n\t{\n\t\tthis->module = module;\n\n\t\tsigmap.set(module);\n\n\t\tsignal_drivers.clear();\n\t\tsignal_consumers.clear();\n\t\tsignal_inputs.clear();\n\t\tsignal_outputs.clear();\n\t\tcell_inputs.clear();\n\t\tcell_outputs.clear();\n\n\t\tfor (auto &it : module->wires_)\n\t\t\tadd_wire(it.second);\n\t\tfor (auto &it : module->cells_)\n\t\t\tif (filter_ct == NULL || filter_ct->cell_known(it.second->type))\n\t\t\t\tadd_cell(it.second);\n\t}\n\n\t// get_* methods -- single RTLIL::SigBit\n\n\tinline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_drivers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_consumers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_inputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_outputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- container of RTLIL::SigBit's (always by reference)\n\n\ttemplate<typename T>\n\tinline bool get_drivers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_drivers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_consumers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_consumers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_inputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_outputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- call by RTLIL::SigSpec (always by value)\n\n\tbool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_drivers(result, bits);\n\t}\n\n\tbool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_consumers(result, bits);\n\t}\n\n\tbool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_inputs(result, bits);\n\t}\n\n\tbool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_outputs(result, bits);\n\t}\n\n\t// has_* methods -- call by reference\n\n\ttemplate<typename T>\n\tinline bool has_drivers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_consumers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_inputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_outputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n\n\t// has_* methods -- call by value\n\n\tinline bool has_drivers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\tinline bool has_consumers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\tinline bool has_inputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\tinline bool has_outputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "qcsat.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2021  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef QCSAT_H\n#define QCSAT_H\n\n#include \"kernel/satgen.h\"\n#include \"kernel/modtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// This is a helper class meant for easy construction of quick SAT queries\n// to a combinatorial input cone of some set of signals, meant for SAT-based\n// optimizations.  Various knobs are provided to set just how much of the\n// cone should be included in the model — since this class is meant for\n// optimization, it should not be a correctness problem when some cells are\n// skipped and the solver spuriously returns SAT with a solution that\n// cannot exist in reality due to skipped constraints (ie. only UNSAT results\n// from this class should be considered binding).\nstruct QuickConeSat {\n\tModWalker &modwalker;\n\tezSatPtr ez;\n\tSatGen satgen;\n\n\t// The effort level knobs.\n\n\t// The maximum \"complexity level\" of cells that will be imported.\n\t// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa\n\t// - 2: addition, subtraction, greater/less than comparisons, lcu\n\t// - 3: shifts\n\t// - 4: multiplication, division, power\n\tint max_cell_complexity = 2;\n\t// The maximum number of cells to import, or 0 for no limit.\n\tint max_cell_count = 0;\n\t// If non-0, skip importing cells with more than this number of output bits.\n\tint max_cell_outs = 0;\n\n\t// Internal state.\n\tpool<RTLIL::Cell*> imported_cells;\n\tpool<RTLIL::Wire*> imported_onehot;\n\tpool<RTLIL::SigBit> bits_queue;\n\n\tQuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}\n\n\t// Imports a signal into the SAT solver, queues its input cone to be\n\t// imported in the next prepare() call.\n\tstd::vector<int> importSig(SigSpec sig);\n\tint importSigBit(SigBit bit);\n\n\t// Imports the input cones of all previously importSig'd signals into\n\t// the SAT solver.\n\tvoid prepare();\n\n\t// Returns the \"complexity level\" of a given cell.\n\tstatic int cell_complexity(RTLIL::Cell *cell);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "register.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename,  std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "rtlil.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5  // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7  // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE   = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2,  // only used for parameters\n\t\tCONST_FLAG_REAL   = 4   // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic dict<char*, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic std::vector<int> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t\tif (idx) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\t}\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tif (!p[0])\n\t\t\treturn 0;\n\n\t\tauto it = global_id_index_.find((char*)p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tlog_assert(p[1] != 0);\n\t\tfor (const char *c = p; *c; c++)\n\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tif (global_id_storage_.empty()) {\n\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t}\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (!destruct_guard_ok || !idx)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tlog_assert(refcount == 0);\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn c_str()[0] == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(Args... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\nnamespace RTLIL {\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx      (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tmutable backing_tag tag;\n\tunion {\n\t\tmutable bitvectype bits_;\n\t\tmutable std::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits() const;\n\tstd::string& get_str() const;\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tstd::vector<RTLIL::State>& bits();\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\tvoid bitvectorize() const;\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const& parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator& operator++(int) { ++idx; return *this; }\n\t\tconst_iterator& operator--(int) { --idx; return *this; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tbits().resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbitvectype& bv = bits();\n\t\tbv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(size());\n\t\tfor (auto b : *this)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset;        // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig>   connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const    { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "rtlil.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5  // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7  // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE   = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2,  // only used for parameters\n\t\tCONST_FLAG_REAL   = 4   // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic dict<char*, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic std::vector<int> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t\tif (idx) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\t}\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tif (!p[0])\n\t\t\treturn 0;\n\n\t\tauto it = global_id_index_.find((char*)p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tlog_assert(p[1] != 0);\n\t\tfor (const char *c = p; *c; c++)\n\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tif (global_id_storage_.empty()) {\n\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t}\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (!destruct_guard_ok || !idx)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tlog_assert(refcount == 0);\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn c_str()[0] == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(Args... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\nnamespace RTLIL {\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx      (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tmutable backing_tag tag;\n\tunion {\n\t\tmutable bitvectype bits_;\n\t\tmutable std::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits() const;\n\tstd::string& get_str() const;\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tstd::vector<RTLIL::State>& bits();\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\tvoid bitvectorize() const;\n\n\tvoid append(const RTLIL::Const &other);\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const& parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator& operator++(int) { ++idx; return *this; }\n\t\tconst_iterator& operator--(int) { --idx; return *this; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tbits().resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbitvectype& bv = bits();\n\t\tbv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(size());\n\t\tfor (auto b : *this)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset;        // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig>   connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const    { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n\tint from_hdl_index(int hdl_index) {\n\t\tint zero_index = hdl_index - start_offset;\n\t\tint rtlil_index = upto ? width - 1 - zero_index : zero_index;\n\t\treturn rtlil_index >= 0 && rtlil_index < width ? rtlil_index : INT_MIN;\n\t}\n\n\tint to_hdl_index(int rtlil_index) {\n\t\tif (rtlil_index < 0 || rtlil_index >= width)\n\t\t\treturn INT_MIN;\n\t\tint zero_index = upto ? width - 1 - rtlil_index : rtlil_index;\n\t\treturn zero_index + start_offset;\n\t}\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "satgen.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tSigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string name = pf + (bit.wire->width == 1 ? stringf(\"%s\", log_id(bit.wire)) : stringf(\"%s [%d]\", log_id(bit.wire->name), bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "scopeinfo.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const\n\t\t{\n\t\t\th.eat(scope_name);\n\t\t\th.eat(target);\n\t\t\treturn h;\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(ptr); return h; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty() && object->name.isPublic())\n\t\tpath.push_back(object->name);\n\tif (!path.empty() && !(object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\"))) {\n\t\tpath.pop_back();\n\t\tpath.push_back(object->name);\n\t}\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\")) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else if (object->has_attribute(ID::hdlname)) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "sexpr.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SEXPR_H\n#define SEXPR_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nclass SExpr {\npublic:\n\tstd::variant<std::vector<SExpr>, std::string> _v;\npublic:\n\tSExpr(std::string a) : _v(std::move(a)) {}\n    SExpr(const char *a) : _v(a) {}\n    // FIXME: should maybe be defined for all integral types\n\tSExpr(int n) : _v(std::to_string(n)) {}\n\tSExpr(std::vector<SExpr> const &l) : _v(l) {}\n\tSExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}\n    // It would be nicer to have an std::initializer_list constructor,\n    // but that causes confusing issues with overload resolution sometimes.\n    template<typename... Args> static SExpr list(Args&&... args) {\n\t    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n    }\n    bool is_atom() const { return std::holds_alternative<std::string>(_v); }\n    std::string const &atom() const { return std::get<std::string>(_v); }\n    bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }\n    std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }\n\tstd::string to_string() const;\n};\n\nstd::ostream &operator<<(std::ostream &os, SExpr const &sexpr);\n\nnamespace SExprUtil {\n    // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list`\n    template<typename... Args> SExpr list(Args&&... args) {\n\t    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n    }\n}\n\n// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout.\nclass SExprWriter {\n    std::ostream &os;\n    int _max_line_width;\n    int _indent = 0;\n    int _pos = 0;\n    // If _pending_nl is set, print a newline before the next character.\n    // This lets us \"undo\" the last newline so we can put\n    // closing parentheses or a hanging comment on the same line.\n    bool _pending_nl = false;\n    // Unclosed parentheses (boolean stored is indent_rest)\n\tvector<bool> _unclosed;\n    // Used only for push() and pop() (stores _unclosed.size())\n\tvector<size_t> _unclosed_stack;\n\tvoid nl_if_pending();\n    void puts(std::string_view s);\n    int check_fit(SExpr const &sexpr, int space);\n    void print(SExpr const &sexpr, bool close = true, bool indent_rest = true);\npublic:\n    SExprWriter(std::ostream &os, int max_line_width = 80)\n        : os(os)\n        , _max_line_width(max_line_width)\n    {}\n    // Print an s-expr.\n    SExprWriter &operator <<(SExpr const &sexpr) {\n        print(sexpr);\n        _pending_nl = true;\n        return *this;\n    }\n    // Print an s-expr (which must be a list), but leave room for extra elements\n    // which may be printed using either << or further calls to open.\n    // If indent_rest = false, the remaining elements are not intended\n    // (for avoiding unreasonable indentation on deeply nested structures).\n    void open(SExpr const &sexpr, bool indent_rest = true) {\n        log_assert(sexpr.is_list());\n        print(sexpr, false, indent_rest);\n    }\n    // Close the s-expr opened with the last call to open\n    // (if an argument is given, close that many s-exprs).\n    void close(size_t n = 1);\n    // push() remembers how many s-exprs are currently open\n\tvoid push() {\n\t\t_unclosed_stack.push_back(_unclosed.size());\n\t}\n    // pop() closes all s-expr opened since the corresponding call to push()\n\tvoid pop() {\n\t\tauto t = _unclosed_stack.back();\n\t\tlog_assert(_unclosed.size() >= t);\n\t\tclose(_unclosed.size() - t);\n\t\t_unclosed_stack.pop_back();\n\t}\n    // Print a comment.\n    // If hanging = true, append it to the end of the last printed s-expr.\n\tvoid comment(std::string const &str, bool hanging = false);\n    // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses.\n    void flush() {\n        nl_if_pending();\n    }\n    // Destructor closes any unclosed parentheses and flushes.\n    ~SExprWriter();\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "sigtools.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SIGTOOLS_H\n#define SIGTOOLS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct SigPool\n{\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(first->name);\n\t\t\th.eat(second);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tpool<bitDef_t> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.insert(bit);\n\t}\n\n\tvoid add(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.insert(bit);\n\t}\n\n\tvoid del(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.erase(bit);\n\t}\n\n\tvoid del(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.erase(bit);\n\t}\n\n\tvoid expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\t\tfor (int i = 0; i < GetSize(from); i++) {\n\t\t\tbitDef_t bit_from(from[i]), bit_to(to[i]);\n\t\t\tif (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)\n\t\t\t\tbits.insert(bit_to);\n\t\t}\n\t}\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tRTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tbool check(const RTLIL::SigBit &bit) const\n\t{\n\t\treturn bit.wire != NULL && bits.count(bit);\n\t}\n\n\tbool check_any(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool check_all(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tRTLIL::SigSpec export_one() const\n\t{\n\t\tfor (auto &bit : bits)\n\t\t\treturn RTLIL::SigSpec(bit.first, bit.second);\n\t\treturn RTLIL::SigSpec();\n\t}\n\n\tRTLIL::SigSpec export_all() const\n\t{\n\t\tpool<RTLIL::SigBit> sig;\n\t\tfor (auto &bit : bits)\n\t\t\tsig.insert(RTLIL::SigBit(bit.first, bit.second));\n\t\treturn sig;\n\t}\n\n\tsize_t size() const\n\t{\n\t\treturn bits.size();\n\t}\n};\n\ntemplate <typename T, class Compare = void>\nstruct SigSet\n{\n\tstatic_assert(!std::is_same<Compare,void>::value, \"Default value for `Compare' class not found for SigSet<T>. Please specify.\");\n\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(first->name);\n\t\t\th.eat(second);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tdict<bitDef_t, std::set<T, Compare>> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid insert(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data);\n\t}\n\n\tvoid insert(const RTLIL::SigSpec& sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data.begin(), data.end());\n\t}\n\n\tvoid erase(const RTLIL::SigSpec& sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].clear();\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data);\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data.begin(), data.end());\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, std::set<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, pool<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tstd::set<T> find(const RTLIL::SigSpec &sig)\n\t{\n\t\tstd::set<T> result;\n\t\tfind(sig, result);\n\t\treturn result;\n\t}\n\n\tbool has(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n};\n\ntemplate<typename T>\nclass SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};\ntemplate<typename T>\nusing sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;\ntemplate<typename T>\nclass SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};\n\n/**\n * SigMap wraps a union-find \"database\"\n * to map SigBits of a module to canonical representative SigBits.\n * SigBits that are connected share a set in the underlying database.\n * If a SigBit has a const state (impl: bit.wire is nullptr),\n * it's promoted to a representative.\n */\nstruct SigMap\n{\n\tmfp<SigBit> database;\n\n\tSigMap(RTLIL::Module *module = NULL)\n\t{\n\t\tif (module != NULL)\n\t\t\tset(module);\n\t}\n\n\tvoid swap(SigMap &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid clear()\n\t{\n\t\tdatabase.clear();\n\t}\n\n\t// Rebuild SigMap for all connections in module\n\tvoid set(RTLIL::Module *module)\n\t{\n\t\tint bitcount = 0;\n\t\tfor (auto &it : module->connections())\n\t\t\tbitcount += it.first.size();\n\n\t\tdatabase.clear();\n\t\tdatabase.reserve(bitcount);\n\n\t\tfor (auto &it : module->connections())\n\t\t\tadd(it.first, it.second);\n\t}\n\n\t// Add connections from \"from\" to \"to\", bit-by-bit\n\tvoid add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\n\t\tfor (int i = 0; i < GetSize(from); i++)\n\t\t{\n\t\t\tint bfi = database.lookup(from[i]);\n\t\t\tint bti = database.lookup(to[i]);\n\n\t\t\tconst RTLIL::SigBit &bf = database[bfi];\n\t\t\tconst RTLIL::SigBit &bt = database[bti];\n\n\t\t\tif (bf.wire || bt.wire)\n\t\t\t{\n\t\t\t\tdatabase.imerge(bfi, bti);\n\n\t\t\t\tif (bf.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bfi);\n\n\t\t\t\tif (bt.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bti);\n\t\t\t}\n\t\t}\n\t}\n\n\t// Add sig as disconnected from anything\n\tvoid add(const RTLIL::SigBit &bit)\n\t{\n\t\tconst auto &b = database.find(bit);\n\t\tif (b.wire != nullptr)\n\t\t\tdatabase.promote(bit);\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tadd(bit);\n\t}\n\n\tinline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }\n\n\t// Modify bit to its representative\n\tvoid apply(RTLIL::SigBit &bit) const\n\t{\n\t\tbit = database.find(bit);\n\t}\n\n\tvoid apply(RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tapply(bit);\n\t}\n\n\tRTLIL::SigBit operator()(RTLIL::SigBit bit) const\n\t{\n\t\tapply(bit);\n\t\treturn bit;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::SigSpec sig) const\n\t{\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::Wire *wire) const\n\t{\n\t\tSigSpec sig(wire);\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\t// All non-const bits\n\tRTLIL::SigSpec allbits() const\n\t{\n\t\tRTLIL::SigSpec sig;\n\t\tfor (const auto &bit : database)\n\t\t\tif (bit.wire != nullptr)\n\t\t\t\tsig.append(bit);\n\t\treturn sig;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif /* SIGTOOLS_H */\n",
                 "timinginfo.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *            (C) 2020  Eddie Hung    <eddie@fpgeh.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tstd::optional<SigBit> get_connection(RTLIL::Cell *cell) {\n\t\t\tif (!cell->hasPort(name))\n\t\t\t\treturn {};\n\t\t\tauto &port = cell->getPort(name);\n\t\t\tif (offset >= port.size())\n\t\t\t\treturn {};\n\t\t\treturn port[offset];\n\t\t}\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(name);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(first);\n\t\t\th.eat(second);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "utils.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*>> backup_state;\n\tdict<Key, T> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>> class TopoSort\n{\n      public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n                IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n                        log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n                auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n                if (rv.second) {\n      \t              nodes.push_back(n);\n\t\t      edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n      private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\n// this class is used for implementing operator-> on iterators that return values rather than references\n// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained\ntemplate<class T>\nstruct arrow_proxy {\n\tT v;\n\texplicit arrow_proxy(T const & v) : v(v) {}\n\tT* operator->() { return &v; }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "utils.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*>> backup_state;\n\tdict<Key, T> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>> class TopoSort\n{\n      public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n                IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n                        log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n                auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n                if (rv.second) {\n      \t              nodes.push_back(n);\n\t\t      edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n      private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\n// this class is used for implementing operator-> on iterators that return values rather than references\n// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained\ntemplate<class T>\nstruct arrow_proxy {\n\tT v;\n\texplicit arrow_proxy(T const & v) : v(v) {}\n\tT* operator->() { return &v; }\n};\n\ninline int ceil_log2(int x)\n{\n#if defined(__GNUC__)\n        return x > 1 ? (8*sizeof(int)) - __builtin_clz(x-1) : 0;\n#else\n\tif (x <= 0)\n\t\treturn 0;\n\tfor (int i = 0; i < 32; i++)\n\t\tif (((x-1) >> i) == 0)\n\t\t\treturn i;\n\tlog_abort();\n#endif\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "yosys.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision!  ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\n#ifdef YOSYS_ENABLE_TCL\nstruct Tcl_Interp;\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "yosys_common.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n#  error It looks like you are trying to build Yosys without the config defines set. \\\n         When building Yosys with a custom make system, make sure you set all the \\\n         defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#define FRIEND_TEST(test_case_name, test_name) \\\n  friend class test_case_name##_##test_name##_Test\n\n#ifdef _WIN32\n#  undef NOMINMAX\n#  define NOMINMAX 1\n#  undef YY_NO_UNISTD_H\n#  define YY_NO_UNISTD_H 1\n\n#  include <windows.h>\n#  include <io.h>\n#  include <direct.h>\n\n#  define strtok_r strtok_s\n#  define strdup _strdup\n#  define snprintf _snprintf\n#  define getcwd _getcwd\n#  define mkdir _mkdir\n#  define popen _popen\n#  define pclose _pclose\n\n#  ifndef __MINGW32__\n#    define PATH_MAX MAX_PATH\n#    define isatty _isatty\n#    define fileno _fileno\n#  endif\n\n// The following defines conflict with our identifiers:\n#  undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n#  undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n#  define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE          Yosys\n#define PRIVATE_NAMESPACE_BEGIN  namespace {\n#define PRIVATE_NAMESPACE_END    }\n#define YOSYS_NAMESPACE_BEGIN    namespace Yosys {\n#define YOSYS_NAMESPACE_END      }\n#define YOSYS_NAMESPACE_PREFIX   Yosys::\n#define USING_YOSYS_NAMESPACE    using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n#  define YS_ATTRIBUTE(...)\n#else\n#  define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n#  define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n#  define YS_FALLTHROUGH [[fallthrough]];\n#else\n#  error \"C++17 or later compatible compiler is required\"\n#endif\n\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n#  error \"You've probably included hashlib.h under two namespace paths. Bad idea.\"\n#else\n#  include \"kernel/hashlib.h\"\n#  undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\nusing hashlib::Hasher;\nusing hashlib::run_hash;\nusing hashlib::hash_ops;\nusing hashlib::mkhash_xorshift;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(*content);\n\t\treturn h;\n\t}\n};\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n    struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n    namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n        // For the common case of strings shorter than 128, save a heap\n        // allocation by using a stack allocated buffer.\n        const int kBufSize = 128;\n        char buf[kBufSize];\n        buf[0] = '\\0';\n        va_list apc;\n        va_copy(apc, ap);\n        int n = vsnprintf(buf, kBufSize, fmt, apc);\n        va_end(apc);\n        if (n < kBufSize)\n          return std::string(buf);\n\n        std::string string;\n        char *str = NULL;\n#if defined(_WIN32 )|| defined(__CYGWIN__)\n        int sz = 2 * kBufSize, rc;\n        while (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char*)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n        if (vasprintf(&str, fmt, ap) < 0)\n          str = NULL;\n        if (str != NULL) {\n          string = str;\n          free(str);\n        }\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n//  sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n        static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "yosys_common.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n#  error It looks like you are trying to build Yosys without the config defines set. \\\n         When building Yosys with a custom make system, make sure you set all the \\\n         defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#define FRIEND_TEST(test_case_name, test_name) \\\n  friend class test_case_name##_##test_name##_Test\n\n#ifdef _WIN32\n#  undef NOMINMAX\n#  define NOMINMAX 1\n#  undef YY_NO_UNISTD_H\n#  define YY_NO_UNISTD_H 1\n\n#  include <windows.h>\n#  include <io.h>\n#  include <direct.h>\n\n#  define strtok_r strtok_s\n#  define strdup _strdup\n#  define snprintf _snprintf\n#  define getcwd _getcwd\n#  define mkdir _mkdir\n#  define popen _popen\n#  define pclose _pclose\n\n#  ifndef __MINGW32__\n#    define PATH_MAX MAX_PATH\n#    define isatty _isatty\n#    define fileno _fileno\n#  endif\n\n// The following defines conflict with our identifiers:\n#  undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n#  undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n#  define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE          Yosys\n#define PRIVATE_NAMESPACE_BEGIN  namespace {\n#define PRIVATE_NAMESPACE_END    }\n#define YOSYS_NAMESPACE_BEGIN    namespace Yosys {\n#define YOSYS_NAMESPACE_END      }\n#define YOSYS_NAMESPACE_PREFIX   Yosys::\n#define USING_YOSYS_NAMESPACE    using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n#  define YS_ATTRIBUTE(...)\n#else\n#  define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n#  define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n#  define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n#  define YS_FALLTHROUGH [[fallthrough]];\n#else\n#  error \"C++17 or later compatible compiler is required\"\n#endif\n\n#if defined(__has_cpp_attribute) && __has_cpp_attribute(gnu::cold)\n#  define YS_COLD [[gnu::cold]]\n#else\n#  define YS_COLD\n#endif\n\n#include \"kernel/io.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n#  error \"You've probably included hashlib.h under two namespace paths. Bad idea.\"\n#else\n#  include \"kernel/hashlib.h\"\n#  undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\nusing hashlib::Hasher;\nusing hashlib::run_hash;\nusing hashlib::hash_ops;\nusing hashlib::mkhash_xorshift;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(*content);\n\t\treturn h;\n\t}\n};\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n    struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n    namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n//  sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n        static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "yw.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YW_H\n#define YW_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/mem.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct IdPath : public std::vector<RTLIL::IdString>\n{\n\ttemplate<typename... T>\n\tIdPath(T&&... args) : std::vector<RTLIL::IdString>(std::forward<T>(args)...) { }\n\tIdPath prefix() const { return {begin(), end() - !empty()}; }\n\tstd::string str() const;\n\n\tbool has_address() const { int tmp; return get_address(tmp); };\n\tbool get_address(int &addr) const;\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(static_cast<const std::vector<RTLIL::IdString>&&>(*this));\n\t\treturn h;\n\t}\n};\n\nstruct WitnessHierarchyItem {\n\tRTLIL::Module *module;\n\tRTLIL::Wire *wire = nullptr;\n\tRTLIL::Cell *cell = nullptr;\n\tMem *mem = nullptr;\n\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Wire *wire) : module(module), wire(wire) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, Mem *mem) : module(module), mem(mem) {}\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback);\n\ntemplate<class T> static std::vector<std::string> witness_path(T *obj) {\n\tstd::vector<std::string> path;\n\tif (obj->name.isPublic()) {\n\t\tauto hdlname = obj->get_string_attribute(ID::hdlname);\n\t\tfor (auto token : split_tokens(hdlname))\n\t\t\tpath.push_back(\"\\\\\" + token);\n\t}\n\tif (path.empty())\n\t\tpath.push_back(obj->name.str());\n\treturn path;\n}\n\nstruct ReadWitness\n{\n\tstruct Clock {\n\t\tIdPath path;\n\t\tint offset;\n\t\tbool is_posedge = false;\n\t\tbool is_negedge = false;\n\t};\n\n\tstruct Signal {\n\t\tIdPath path;\n\t\tint offset;\n\t\tint width;\n\t\tbool init_only;\n\n\t\tint bits_offset;\n\t};\n\n\tstruct Step {\n\t\tstd::string bits;\n\t};\n\n\tstd::string filename;\n\tstd::vector<Clock> clocks;\n\tstd::vector<Signal> signals;\n\tstd::vector<Step> steps;\n\n\tReadWitness(const std::string &filename);\n\n\tRTLIL::Const get_bits(int t, int bits_offset, int width) const;\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *module, D data, T &callback)\n{\n\tauto const &const_path = path;\n\tsize_t path_size = path.size();\n\tfor (auto wire : module->wires())\n\t{\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : wire->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == wire->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty())\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(wire->name);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto cell : module->cells())\n\t{\n\t\tModule *child = module->design->module(cell->type);\n\t\tif (child == nullptr)\n\t\t\tcontinue;\n\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, 1, child, child_data, callback);\n\t\t}\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(cell->name);\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, hdlname.empty() ? hdlname_mode : -1, child, child_data, callback);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto mem : Mem::get_all_memories(module)) {\n\t\tstd::vector<std::string> hdlname;\n\n\t\tif (hdlname_mode >= 0 && mem.cell != nullptr)\n\t\t\thdlname = mem.cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == mem.cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t}\n\t\tpath.resize(path_size);\n\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(mem.memid);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\tpath.pop_back();\n\n\t\t\tif (mem.cell != nullptr && mem.cell->name != mem.memid) {\n\t\t\t\tpath.push_back(mem.cell->name);\n\t\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\t\tpath.pop_back();\n\t\t\t}\n\t\t}\n\t}\n}\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback)\n{\n\tIdPath path;\n\twitness_hierarchy_recursion<D, T>(path, 0, module, data, callback);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
             },
             "libs": {
@@ -213,7 +215,7 @@ export const filesystem = {
             "common": {
                 "altpll_bb.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n/* No clearbox model */\n`ifdef NO_CLEARBOX\n(* blackbox *)\nmodule altpll\n  ( inclk,\n    fbin,\n    pllena,\n    clkswitch,\n    areset,\n    pfdena,\n    clkena,\n    extclkena,\n    scanclk,\n    scanaclr,\n    scanclkena,\n    scanread,\n    scanwrite,\n    scandata,\n    phasecounterselect,\n    phaseupdown,\n    phasestep,\n    configupdate,\n    fbmimicbidir,\n    clk,\n    extclk,\n    clkbad,\n    enable0,\n    enable1,\n    activeclock,\n    clkloss,\n    locked,\n    scandataout,\n    scandone,\n    sclkout0,\n    sclkout1,\n    phasedone,\n    vcooverrange,\n    vcounderrange,\n    fbout,\n    fref,\n    icdrclk,\n    c0,\n    c1,\n    c2,\n    c3,\n    c4);\n\n   parameter   intended_device_family    = \"MAX 10\";\n   parameter   operation_mode            = \"NORMAL\";\n   parameter   pll_type                  = \"AUTO\";\n   parameter   qualify_conf_done         = \"OFF\";\n   parameter   compensate_clock          = \"CLK0\";\n   parameter   scan_chain                = \"LONG\";\n   parameter   primary_clock             = \"inclk0\";\n   parameter   inclk0_input_frequency    = 1000;\n   parameter   inclk1_input_frequency    = 0;\n   parameter   gate_lock_signal          = \"NO\";\n   parameter   gate_lock_counter         = 0;\n   parameter   lock_high                 = 1;\n   parameter   lock_low                  = 0;\n   parameter   valid_lock_multiplier     = 1;\n   parameter   invalid_lock_multiplier   = 5;\n   parameter   switch_over_type          = \"AUTO\";\n   parameter   switch_over_on_lossclk    = \"OFF\" ;\n   parameter   switch_over_on_gated_lock = \"OFF\" ;\n   parameter   enable_switch_over_counter = \"OFF\";\n   parameter   switch_over_counter       = 0;\n   parameter   feedback_source           = \"EXTCLK0\" ;\n   parameter   bandwidth                 = 0;\n   parameter   bandwidth_type            = \"UNUSED\";\n   parameter   lpm_hint                  = \"UNUSED\";\n   parameter   spread_frequency          = 0;\n   parameter   down_spread               = \"0.0\";\n   parameter   self_reset_on_gated_loss_lock = \"OFF\";\n   parameter   self_reset_on_loss_lock = \"OFF\";\n   parameter   lock_window_ui           = \"0.05\";\n   parameter   width_clock              = 6;\n   parameter   width_phasecounterselect = 4;\n   parameter   charge_pump_current_bits = 9999;\n   parameter   loop_filter_c_bits = 9999;\n   parameter   loop_filter_r_bits = 9999;\n   parameter   scan_chain_mif_file = \"UNUSED\";\n   parameter   clk9_multiply_by        = 1;\n   parameter   clk8_multiply_by        = 1;\n   parameter   clk7_multiply_by        = 1;\n   parameter   clk6_multiply_by        = 1;\n   parameter   clk5_multiply_by        = 1;\n   parameter   clk4_multiply_by        = 1;\n   parameter   clk3_multiply_by        = 1;\n   parameter   clk2_multiply_by        = 1;\n   parameter   clk1_multiply_by        = 1;\n   parameter   clk0_multiply_by        = 1;\n   parameter   clk9_divide_by          = 1;\n   parameter   clk8_divide_by          = 1;\n   parameter   clk7_divide_by          = 1;\n   parameter   clk6_divide_by          = 1;\n   parameter   clk5_divide_by          = 1;\n   parameter   clk4_divide_by          = 1;\n   parameter   clk3_divide_by          = 1;\n   parameter   clk2_divide_by          = 1;\n   parameter   clk1_divide_by          = 1;\n   parameter   clk0_divide_by          = 1;\n   parameter   clk9_phase_shift        = \"0\";\n   parameter   clk8_phase_shift        = \"0\";\n   parameter   clk7_phase_shift        = \"0\";\n   parameter   clk6_phase_shift        = \"0\";\n   parameter   clk5_phase_shift        = \"0\";\n   parameter   clk4_phase_shift        = \"0\";\n   parameter   clk3_phase_shift        = \"0\";\n   parameter   clk2_phase_shift        = \"0\";\n   parameter   clk1_phase_shift        = \"0\";\n   parameter   clk0_phase_shift        = \"0\";\n\n   parameter   clk9_duty_cycle         = 50;\n   parameter   clk8_duty_cycle         = 50;\n   parameter   clk7_duty_cycle         = 50;\n   parameter   clk6_duty_cycle         = 50;\n   parameter   clk5_duty_cycle         = 50;\n   parameter   clk4_duty_cycle         = 50;\n   parameter   clk3_duty_cycle         = 50;\n   parameter   clk2_duty_cycle         = 50;\n   parameter   clk1_duty_cycle         = 50;\n   parameter   clk0_duty_cycle         = 50;\n\n   parameter   clk9_use_even_counter_mode    = \"OFF\";\n   parameter   clk8_use_even_counter_mode    = \"OFF\";\n   parameter   clk7_use_even_counter_mode    = \"OFF\";\n   parameter   clk6_use_even_counter_mode    = \"OFF\";\n   parameter   clk5_use_even_counter_mode    = \"OFF\";\n   parameter   clk4_use_even_counter_mode    = \"OFF\";\n   parameter   clk3_use_even_counter_mode    = \"OFF\";\n   parameter   clk2_use_even_counter_mode    = \"OFF\";\n   parameter   clk1_use_even_counter_mode    = \"OFF\";\n   parameter   clk0_use_even_counter_mode    = \"OFF\";\n   parameter   clk9_use_even_counter_value   = \"OFF\";\n   parameter   clk8_use_even_counter_value   = \"OFF\";\n   parameter   clk7_use_even_counter_value   = \"OFF\";\n   parameter   clk6_use_even_counter_value   = \"OFF\";\n   parameter   clk5_use_even_counter_value   = \"OFF\";\n   parameter   clk4_use_even_counter_value   = \"OFF\";\n   parameter   clk3_use_even_counter_value   = \"OFF\";\n   parameter   clk2_use_even_counter_value   = \"OFF\";\n   parameter   clk1_use_even_counter_value   = \"OFF\";\n   parameter   clk0_use_even_counter_value   = \"OFF\";\n\n   parameter   clk2_output_frequency   = 0;\n   parameter   clk1_output_frequency   = 0;\n   parameter   clk0_output_frequency   = 0;\n\n   parameter   vco_min             = 0;\n   parameter   vco_max             = 0;\n   parameter   vco_center          = 0;\n   parameter   pfd_min             = 0;\n   parameter   pfd_max             = 0;\n   parameter   m_initial           = 1;\n   parameter   m                   = 0;\n   parameter   n                   = 1;\n   parameter   m2                  = 1;\n   parameter   n2                  = 1;\n   parameter   ss                  = 0;\n   parameter   l0_high             = 1;\n   parameter   l1_high             = 1;\n   parameter   g0_high             = 1;\n   parameter   g1_high             = 1;\n   parameter   g2_high             = 1;\n   parameter   g3_high             = 1;\n   parameter   e0_high             = 1;\n   parameter   e1_high             = 1;\n   parameter   e2_high             = 1;\n   parameter   e3_high             = 1;\n   parameter   l0_low              = 1;\n   parameter   l1_low              = 1;\n   parameter   g0_low              = 1;\n   parameter   g1_low              = 1;\n   parameter   g2_low              = 1;\n   parameter   g3_low              = 1;\n   parameter   e0_low              = 1;\n   parameter   e1_low              = 1;\n   parameter   e2_low              = 1;\n   parameter   e3_low              = 1;\n   parameter   l0_initial          = 1;\n   parameter   l1_initial          = 1;\n   parameter   g0_initial          = 1;\n   parameter   g1_initial          = 1;\n   parameter   g2_initial          = 1;\n   parameter   g3_initial          = 1;\n   parameter   e0_initial          = 1;\n   parameter   e1_initial          = 1;\n   parameter   e2_initial          = 1;\n   parameter   e3_initial          = 1;\n   parameter   l0_mode             = \"bypass\";\n   parameter   l1_mode             = \"bypass\";\n   parameter   g0_mode             = \"bypass\";\n   parameter   g1_mode             = \"bypass\";\n   parameter   g2_mode             = \"bypass\";\n   parameter   g3_mode             = \"bypass\";\n   parameter   e0_mode             = \"bypass\";\n   parameter   e1_mode             = \"bypass\";\n   parameter   e2_mode             = \"bypass\";\n   parameter   e3_mode             = \"bypass\";\n   parameter   l0_ph               = 0;\n   parameter   l1_ph               = 0;\n   parameter   g0_ph               = 0;\n   parameter   g1_ph               = 0;\n   parameter   g2_ph               = 0;\n   parameter   g3_ph               = 0;\n   parameter   e0_ph               = 0;\n   parameter   e1_ph               = 0;\n   parameter   e2_ph               = 0;\n   parameter   e3_ph               = 0;\n   parameter   m_ph                = 0;\n   parameter   l0_time_delay       = 0;\n   parameter   l1_time_delay       = 0;\n   parameter   g0_time_delay       = 0;\n   parameter   g1_time_delay       = 0;\n   parameter   g2_time_delay       = 0;\n   parameter   g3_time_delay       = 0;\n   parameter   e0_time_delay       = 0;\n   parameter   e1_time_delay       = 0;\n   parameter   e2_time_delay       = 0;\n   parameter   e3_time_delay       = 0;\n   parameter   m_time_delay        = 0;\n   parameter   n_time_delay        = 0;\n   parameter   extclk3_counter     = \"e3\" ;\n   parameter   extclk2_counter     = \"e2\" ;\n   parameter   extclk1_counter     = \"e1\" ;\n   parameter   extclk0_counter     = \"e0\" ;\n   parameter   clk9_counter        = \"c9\" ;\n   parameter   clk8_counter        = \"c8\" ;\n   parameter   clk7_counter        = \"c7\" ;\n   parameter   clk6_counter        = \"c6\" ;\n   parameter   clk5_counter        = \"l1\" ;\n   parameter   clk4_counter        = \"l0\" ;\n   parameter   clk3_counter        = \"g3\" ;\n   parameter   clk2_counter        = \"g2\" ;\n   parameter   clk1_counter        = \"g1\" ;\n   parameter   clk0_counter        = \"g0\" ;\n   parameter   enable0_counter     = \"l0\";\n   parameter   enable1_counter     = \"l0\";\n   parameter   charge_pump_current = 2;\n   parameter   loop_filter_r       = \"1.0\";\n   parameter   loop_filter_c       = 5;\n   parameter   vco_post_scale      = 0;\n   parameter   vco_frequency_control = \"AUTO\";\n   parameter   vco_phase_shift_step = 0;\n   parameter   lpm_type            = \"altpll\";\n\n   parameter port_clkena0 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena1 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena2 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena3 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena4 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena5 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena0 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena1 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena2 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena3 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk0 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk1 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk2 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk3 = \"PORT_CONNECTIVITY\";\n   parameter port_clk0 = \"PORT_CONNECTIVITY\";\n   parameter port_clk1 = \"PORT_CONNECTIVITY\";\n   parameter port_clk2 = \"PORT_CONNECTIVITY\";\n   parameter port_clk3 = \"PORT_CONNECTIVITY\";\n   parameter port_clk4 = \"PORT_CONNECTIVITY\";\n   parameter port_clk5 = \"PORT_CONNECTIVITY\";\n   parameter port_clk6 = \"PORT_CONNECTIVITY\";\n   parameter port_clk7 = \"PORT_CONNECTIVITY\";\n   parameter port_clk8 = \"PORT_CONNECTIVITY\";\n   parameter port_clk9 = \"PORT_CONNECTIVITY\";\n   parameter port_scandata = \"PORT_CONNECTIVITY\";\n   parameter port_scandataout = \"PORT_CONNECTIVITY\";\n   parameter port_scandone = \"PORT_CONNECTIVITY\";\n   parameter port_sclkout1 = \"PORT_CONNECTIVITY\";\n   parameter port_sclkout0 = \"PORT_CONNECTIVITY\";\n   parameter port_clkbad0 = \"PORT_CONNECTIVITY\";\n   parameter port_clkbad1 = \"PORT_CONNECTIVITY\";\n   parameter port_activeclock = \"PORT_CONNECTIVITY\";\n   parameter port_clkloss = \"PORT_CONNECTIVITY\";\n   parameter port_inclk1 = \"PORT_CONNECTIVITY\";\n   parameter port_inclk0 = \"PORT_CONNECTIVITY\";\n   parameter port_fbin = \"PORT_CONNECTIVITY\";\n   parameter port_fbout = \"PORT_CONNECTIVITY\";\n   parameter port_pllena = \"PORT_CONNECTIVITY\";\n   parameter port_clkswitch = \"PORT_CONNECTIVITY\";\n   parameter port_areset = \"PORT_CONNECTIVITY\";\n   parameter port_pfdena = \"PORT_CONNECTIVITY\";\n   parameter port_scanclk = \"PORT_CONNECTIVITY\";\n   parameter port_scanaclr = \"PORT_CONNECTIVITY\";\n   parameter port_scanread = \"PORT_CONNECTIVITY\";\n   parameter port_scanwrite = \"PORT_CONNECTIVITY\";\n   parameter port_enable0 = \"PORT_CONNECTIVITY\";\n   parameter port_enable1 = \"PORT_CONNECTIVITY\";\n   parameter port_locked = \"PORT_CONNECTIVITY\";\n   parameter port_configupdate = \"PORT_CONNECTIVITY\";\n   parameter port_phasecounterselect = \"PORT_CONNECTIVITY\";\n   parameter port_phasedone = \"PORT_CONNECTIVITY\";\n   parameter port_phasestep = \"PORT_CONNECTIVITY\";\n   parameter port_phaseupdown = \"PORT_CONNECTIVITY\";\n   parameter port_vcooverrange = \"PORT_CONNECTIVITY\";\n   parameter port_vcounderrange = \"PORT_CONNECTIVITY\";\n   parameter port_scanclkena = \"PORT_CONNECTIVITY\";\n   parameter using_fbmimicbidir_port = \"ON\";\n\n   input [1:0] inclk;\n   input       fbin;\n   input       pllena;\n   input       clkswitch;\n   input       areset;\n   input       pfdena;\n   input       clkena;\n   input       extclkena;\n   input       scanclk;\n   input       scanaclr;\n   input       scanclkena;\n   input       scanread;\n   input       scanwrite;\n   input       scandata;\n   input       phasecounterselect;\n   input       phaseupdown;\n   input       phasestep;\n   input       configupdate;\n   inout       fbmimicbidir;\n\n\n   output [width_clock-1:0] clk;\n   output [3:0]             extclk;\n   output [1:0]             clkbad;\n   output                   enable0;\n   output                   enable1;\n   output                   activeclock;\n   output                   clkloss;\n   output                   locked;\n   output                   scandataout;\n   output                   scandone;\n   output                   sclkout0;\n   output                   sclkout1;\n   output                   phasedone;\n   output                   vcooverrange;\n   output                   vcounderrange;\n   output                   fbout;\n   output                   fref;\n   output                   icdrclk;\n   output                   c0, c1, c2, c3, c4;\n\nendmodule // altpll\n`endif\n",
                 "brams_m9k.txt": "bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL\n  init   1\n  abits  13 @M1\n  dbits  1  @M1\n  abits  12 @M2\n  dbits  2  @M2\n  abits  11 @M3\n  dbits  4  @M3\n  abits  10 @M4\n  dbits  8  @M4\n  abits  10 @M5\n  dbits  9  @M5\n  abits  9  @M6\n  dbits  16 @M6\n  abits  9  @M7\n  dbits  18 @M7\n  abits  8  @M8\n  dbits  32 @M8\n  abits  8  @M9\n  dbits  36 @M9\n  groups 2\n  ports  1 1\n  wrmode 0 1\n  enable 1 1\n  transp 0 0\n  clocks 2 3\n  clkpol 2 3\nendbram\n\nmatch $__M9K_ALTSYNCRAM_SINGLEPORT_FULL\n  min efficiency 2\n  make_transp\nendmatch\n",
-                "brams_map_m9k.v": "module \\$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n\n   parameter CFG_ABITS = 8;\n   parameter CFG_DBITS = 36;\n   parameter ABITS = 1;\n   parameter DBITS = 1;\n   parameter CLKPOL2 = 1;\n   parameter CLKPOL3 = 1;\n\n   input CLK2;\n   input CLK3;\n   //Read data\n   output [CFG_DBITS-1:0] A1DATA;\n   input [CFG_ABITS-1:0]  A1ADDR;\n   input                  A1EN;\n   //Write data\n   output [CFG_DBITS-1:0] B1DATA;\n   input [CFG_ABITS-1:0]  B1ADDR;\n   input                  B1EN;\n\n   wire [CFG_DBITS-1:0]   B1DATA_t;\n\n   localparam MODE = CFG_DBITS == 1  ? 1:\n                     CFG_DBITS == 2  ? 2:\n                     CFG_DBITS == 4  ? 3:\n                     CFG_DBITS == 8  ? 4:\n                     CFG_DBITS == 9  ? 5:\n                     CFG_DBITS == 16 ? 6:\n                     CFG_DBITS == 18 ? 7:\n                     CFG_DBITS == 32 ? 8:\n                     CFG_DBITS == 36 ? 9:\n                     'bx;\n\n   localparam NUMWORDS = CFG_DBITS == 1  ? 8192:\n                         CFG_DBITS == 2  ? 4096:\n                         CFG_DBITS == 4  ? 2048:\n                         CFG_DBITS == 8  ? 1024:\n                         CFG_DBITS == 9  ? 1024:\n                         CFG_DBITS == 16 ?  512:\n                         CFG_DBITS == 18 ?  512:\n                         CFG_DBITS == 32 ?  256:\n                         CFG_DBITS == 36 ?  256:\n                         'bx;\n\n   altsyncram  #(.clock_enable_input_b           (\"ALTERNATE\"   ),\n                 .clock_enable_input_a           (\"ALTERNATE\"   ),\n                 .clock_enable_output_b          (\"NORMAL\"      ),\n                 .clock_enable_output_a          (\"NORMAL\"      ),\n                 .wrcontrol_aclr_a               (\"NONE\"        ),\n                 .indata_aclr_a                  (\"NONE\"        ),\n                 .address_aclr_a                 (\"NONE\"        ),\n                 .outdata_aclr_a                 (\"NONE\"        ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .operation_mode                 (\"SINGLE_PORT\" ),\n                 .intended_device_family         (\"CYCLONE IVE\" ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .lpm_type                       (\"altsyncram\"  ),\n                 .init_type                      (\"unused\"      ),\n                 .ram_block_type                 (\"AUTO\"        ),\n                 .lpm_hint                       (\"ENABLE_RUNTIME_MOD=NO\"), // Forced value\n                 .power_up_uninitialized         (\"FALSE\"),\n                 .read_during_write_mode_port_a  (\"NEW_DATA_NO_NBE_READ\"), // Forced value\n                 .width_byteena_a                (1), // Forced value\n                 .numwords_b                     ( NUMWORDS     ),\n                 .numwords_a                     ( NUMWORDS     ),\n                 .widthad_b                      ( CFG_DBITS    ),\n                 .width_b                        ( CFG_ABITS    ),\n                 .widthad_a                      ( CFG_DBITS    ),\n                 .width_a                        ( CFG_ABITS    )\n                 ) _TECHMAP_REPLACE_ (\n                                      .data_a(B1DATA),\n                                      .address_a(B1ADDR),\n                                      .wren_a(B1EN),\n                                      .rden_a(A1EN),\n                                      .q_a(A1DATA),\n                                      .data_b(B1DATA),\n                                      .address_b(0),\n                                      .wren_b(1'b0),\n                                      .rden_b(1'b0),\n                                      .q_b(),\n                                      .clock0(CLK2),\n                                      .clock1(1'b1), // Unused in single port mode\n                                      .clocken0(1'b1),\n                                      .clocken1(1'b1),\n                                      .clocken2(1'b1),\n                                      .clocken3(1'b1),\n                                      .aclr0(1'b0),\n                                      .aclr1(1'b0),\n                                      .addressstall_a(1'b0),\n                                      .addressstall_b(1'b0));\n\nendmodule\n\n",
+                "brams_map_m9k.v": "module \\$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n\n   parameter CFG_ABITS = 8;\n   parameter CFG_DBITS = 36;\n   parameter ABITS = 1;\n   parameter DBITS = 1;\n   parameter CLKPOL2 = 1;\n   parameter CLKPOL3 = 1;\n\n   input CLK2;\n   input CLK3;\n   //Read data\n   output [CFG_DBITS-1:0] A1DATA;\n   input [CFG_ABITS-1:0]  A1ADDR;\n   input                  A1EN;\n   //Write data\n   output [CFG_DBITS-1:0] B1DATA;\n   input [CFG_ABITS-1:0]  B1ADDR;\n   input                  B1EN;\n\n   wire [CFG_DBITS-1:0]   B1DATA_t;\n\n   localparam MODE = CFG_DBITS == 1  ? 1:\n                     CFG_DBITS == 2  ? 2:\n                     CFG_DBITS == 4  ? 3:\n                     CFG_DBITS == 8  ? 4:\n                     CFG_DBITS == 9  ? 5:\n                     CFG_DBITS == 16 ? 6:\n                     CFG_DBITS == 18 ? 7:\n                     CFG_DBITS == 32 ? 8:\n                     CFG_DBITS == 36 ? 9:\n                     'bx;\n\n   localparam NUMWORDS = CFG_DBITS == 1  ? 8192:\n                         CFG_DBITS == 2  ? 4096:\n                         CFG_DBITS == 4  ? 2048:\n                         CFG_DBITS == 8  ? 1024:\n                         CFG_DBITS == 9  ? 1024:\n                         CFG_DBITS == 16 ?  512:\n                         CFG_DBITS == 18 ?  512:\n                         CFG_DBITS == 32 ?  256:\n                         CFG_DBITS == 36 ?  256:\n                         'bx;\n\n   altsyncram  #(.clock_enable_input_b           (\"ALTERNATE\"   ),\n                 .clock_enable_input_a           (\"ALTERNATE\"   ),\n                 .clock_enable_output_b          (\"NORMAL\"      ),\n                 .clock_enable_output_a          (\"NORMAL\"      ),\n                 .wrcontrol_aclr_a               (\"NONE\"        ),\n                 .indata_aclr_a                  (\"NONE\"        ),\n                 .address_aclr_a                 (\"NONE\"        ),\n                 .outdata_aclr_a                 (\"NONE\"        ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .operation_mode                 (\"SINGLE_PORT\" ),\n                 .intended_device_family         (\"CYCLONE IVE\" ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .lpm_type                       (\"altsyncram\"  ),\n                 .init_type                      (\"unused\"      ),\n                 .ram_block_type                 (\"AUTO\"        ),\n                 .lpm_hint                       (\"ENABLE_RUNTIME_MOD=NO\"), // Forced value\n                 .power_up_uninitialized         (\"FALSE\"),\n                 .read_during_write_mode_port_a  (\"NEW_DATA_NO_NBE_READ\"), // Forced value\n                 .width_byteena_a                (1), // Forced value\n                 .numwords_b                     ( NUMWORDS     ),\n                 .numwords_a                     ( NUMWORDS     ),\n                 .widthad_b                      ( CFG_ABITS    ),\n                 .width_b                        ( CFG_DBITS    ),\n                 .widthad_a                      ( CFG_ABITS    ),\n                 .width_a                        ( CFG_DBITS    )\n                 ) _TECHMAP_REPLACE_ (\n                                      .data_a(B1DATA),\n                                      .address_a(B1ADDR),\n                                      .wren_a(B1EN),\n                                      .rden_a(A1EN),\n                                      .q_a(A1DATA),\n                                      .data_b(B1DATA),\n                                      .address_b(0),\n                                      .wren_b(1'b0),\n                                      .rden_b(1'b0),\n                                      .q_b(),\n                                      .clock0(CLK2),\n                                      .clock1(1'b1), // Unused in single port mode\n                                      .clocken0(1'b1),\n                                      .clocken1(1'b1),\n                                      .clocken2(1'b1),\n                                      .clocken3(1'b1),\n                                      .aclr0(1'b0),\n                                      .aclr1(1'b0),\n                                      .addressstall_a(1'b0),\n                                      .addressstall_b(1'b0));\n\nendmodule\n\n",
                 "ff_map.v": "// Async Active Low Reset DFF\nmodule  \\$_DFFE_PN0P_ (input D, C, R, E, output Q);\n   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n   generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) begin\n     dffeas #(.is_wysiwyg(\"TRUE\"), .power_up(\"high\")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));\n   end else begin\n     dffeas #(.is_wysiwyg(\"TRUE\"), .power_up(\"low\")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));\n   end\n   endgenerate\n   wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n",
                 "m9k_bb.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n(* blackbox *)\nmodule altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b,  wren_b, rden_b,\n                  q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,\n                  addressstall_a, addressstall_b);\n\n   parameter clock_enable_input_b          = \"ALTERNATE\";\n   parameter clock_enable_input_a          = \"ALTERNATE\";\n   parameter clock_enable_output_b         = \"NORMAL\";\n   parameter clock_enable_output_a         = \"NORMAL\";\n   parameter wrcontrol_aclr_a              = \"NONE\";\n   parameter indata_aclr_a                 = \"NONE\";\n   parameter address_aclr_a                = \"NONE\";\n   parameter outdata_aclr_a                = \"NONE\";\n   parameter outdata_reg_a                 = \"UNREGISTERED\";\n   parameter operation_mode                = \"SINGLE_PORT\";\n   parameter intended_device_family        = \"MAX 10 FPGA\";\n   parameter outdata_reg_b                 = \"UNREGISTERED\";\n   parameter lpm_type                      = \"altsyncram\";\n   parameter init_type                     = \"unused\";\n   parameter ram_block_type                = \"AUTO\";\n   parameter lpm_hint                      = \"ENABLE_RUNTIME_MOD=NO\";\n   parameter power_up_uninitialized        = \"FALSE\";\n   parameter read_during_write_mode_port_a = \"NEW_DATA_NO_NBE_READ\";\n   parameter width_byteena_a               = 1;\n   parameter numwords_b                    = 0;\n   parameter numwords_a                    = 0;\n   parameter widthad_b                     = 1;\n   parameter width_b                       = 1;\n   parameter widthad_a                     = 1;\n   parameter width_a                       = 1;\n\n   // Port A declarations\n   output [35:0] q_a;\n   input [35:0]  data_a;\n   input [7:0]   address_a;\n   input         wren_a;\n   input         rden_a;\n   // Port B declarations\n   output [35:0] q_b;\n   input [35:0]  data_b;\n   input [7:0]   address_b;\n   input         wren_b;\n   input         rden_b;\n   // Control signals\n   input         clock0, clock1;\n   input         clocken0, clocken1, clocken2, clocken3;\n   input         aclr0, aclr1;\n   input         addressstall_a;\n   input         addressstall_b;\n   // TODO: Implement the correct simulation model\n\nendmodule // altsyncram\n",
             },
@@ -231,7 +233,7 @@ export const filesystem = {
             },
             "max10": {
                 "cells_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n// > c60k28 (Viacheslav, VT) [at] yandex [dot] com\n// > Intel FPGA technology mapping. User must first simulate the generated \\\n// > netlist before going to test it on board.\n\n// Input buffer map\nmodule \\$__inpad (input I, output O);\n   fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));\nendmodule\n\n// Output buffer map\nmodule \\$__outpad (input I, output O);\n   fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));\nendmodule\n\n// LUT Map\n/* 0 -> datac\n   1 -> cin */\nmodule \\$lut (A, Y);\n   parameter WIDTH  = 0;\n   parameter LUT    = 0;\n   (* force_downto *)\n   input [WIDTH-1:0] A;\n   output            Y;\n   generate\n      if (WIDTH == 1) begin\n\t   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function\n      end else\n      if (WIDTH == 2) begin\n           fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input(\"datac\")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));\n      end else\n      if(WIDTH == 3) begin\n\t      fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input(\"datac\")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));\n      end else\n      if(WIDTH == 4) begin\n         fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input(\"datac\")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));\n      end else\n\t   wire _TECHMAP_FAIL_ = 1;\n   endgenerate\nendmodule //\n\n\n",
-                "cells_sim.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule VCC (output V);\n   assign V = 1'b1;\nendmodule // VCC\n\nmodule GND (output G);\n   assign G = 1'b0;\nendmodule // GND\n\n/* Altera MAX10 devices Input Buffer Primitive */\nmodule fiftyfivenm_io_ibuf\n  (output o, input i, input ibar);\n   assign ibar = ibar;\n   assign o    = i;\nendmodule // fiftyfivenm_io_ibuf\n\n/* Altera MAX10 devices Output Buffer Primitive */\nmodule fiftyfivenm_io_obuf\n  (output o, input i, input oe);\n   assign o  = i;\n   assign oe = oe;\nendmodule // fiftyfivenm_io_obuf\n\n/* Altera MAX10 4-input non-fracturable LUT Primitive */\nmodule fiftyfivenm_lcell_comb\n  (output combout, cout,\n   input dataa, datab, datac, datad, cin);\n\n   /* Internal parameters which define the behaviour\n    of the LUT primitive.\n    lut_mask define the lut function, can be expressed in 16-digit bin or hex.\n    sum_lutc_input define the type of LUT (combinational | arithmetic).\n    dont_touch for retiming || carry options.\n    lpm_type for WYSIWYG */\n\n   parameter lut_mask = 16'hFFFF;\n   parameter dont_touch = \"off\";\n   parameter lpm_type = \"fiftyfivenm_lcell_comb\";\n   parameter sum_lutc_input = \"datac\";\n\n   reg [1:0] lut_type;\n   reg       cout_rt;\n   reg       combout_rt;\n   wire      dataa_w;\n   wire      datab_w;\n   wire      datac_w;\n   wire      datad_w;\n   wire      cin_w;\n\n   assign dataa_w = dataa;\n   assign datab_w = datab;\n   assign datac_w = datac;\n   assign datad_w = datad;\n\n   function lut_data;\n      input [15:0] mask;\n      input        dataa, datab, datac, datad;\n      reg [7:0]    s3;\n      reg [3:0]    s2;\n      reg [1:0]    s1;\n      begin\n         s3 = datad ? mask[15:8] : mask[7:0];\n         s2 = datac ?   s3[7:4]  :   s3[3:0];\n         s1 = datab ?   s2[3:2]  :   s2[1:0];\n         lut_data = dataa ? s1[1] : s1[0];\n      end\n\n   endfunction\n\n   initial begin\n      if (sum_lutc_input == \"datac\") lut_type = 0;\n      else\n        if (sum_lutc_input == \"cin\")   lut_type = 1;\n        else begin\n           $error(\"Error in sum_lutc_input. Parameter %s is not a valid value.\\n\", sum_lutc_input);\n           $finish();\n        end\n   end\n\n   always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin\n      if (lut_type == 0) begin // logic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               datac_w, datad_w);\n      end\n      else if (lut_type == 1) begin // arithmetic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               cin_w, datad_w);\n      end\n      cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);\n   end\n\n   assign combout = combout_rt & 1'b1;\n   assign cout = cout_rt & 1'b1;\n\nendmodule // fiftyfivenm_lcell_comb\n\n/* Altera D Flip-Flop Primitive */\nmodule dffeas\n  (output q,\n   input d, clk, clrn, prn, ena,\n   input asdata, aload, sclr, sload);\n\n   // Timing simulation is not covered\n   parameter power_up=\"dontcare\";\n   parameter is_wysiwyg=\"false\";\n\n   reg   q_tmp;\n   wire  reset;\n   reg [7:0] debug_net;\n\n   assign reset       = (prn && sclr && ~clrn && ena);\n   assign q           = q_tmp & 1'b1;\n\n   always @(posedge clk, posedge aload) begin\n      if(reset)        q_tmp <= 0;\n      else q_tmp <= d;\n   end\n   assign q = q_tmp;\n\nendmodule // dffeas\n\n/* MAX10 altpll clearbox model */\n(* blackbox *)\nmodule fiftyfivenm_pll\n  (inclk,\n   fbin,\n   fbout,\n   clkswitch,\n   areset,\n   pfdena,\n   scanclk,\n   scandata,\n   scanclkena,\n   configupdate,\n   clk,\n   phasecounterselect,\n   phaseupdown,\n   phasestep,\n   clkbad,\n   activeclock,\n   locked,\n   scandataout,\n   scandone,\n   phasedone,\n   vcooverrange,\n   vcounderrange);\n\n   parameter operation_mode                = \"normal\";\n   parameter pll_type                      = \"auto\";\n   parameter compensate_clock              = \"clock0\";\n   parameter inclk0_input_frequency        = 0;\n   parameter inclk1_input_frequency        = 0;\n   parameter self_reset_on_loss_lock       = \"off\";\n   parameter switch_over_type              = \"auto\";\n   parameter switch_over_counter           = 1;\n   parameter enable_switch_over_counter    = \"off\";\n   parameter bandwidth                     = 0;\n   parameter bandwidth_type                = \"auto\";\n   parameter use_dc_coupling               = \"false\";\n   parameter lock_high = 0;\n   parameter lock_low = 0;\n   parameter lock_window_ui                = \"0.05\";\n   parameter test_bypass_lock_detect       = \"off\";\n   parameter clk0_output_frequency         = 0;\n   parameter clk0_multiply_by              = 0;\n   parameter clk0_divide_by                = 0;\n   parameter clk0_phase_shift              = \"0\";\n   parameter clk0_duty_cycle               = 50;\n   parameter clk1_output_frequency         = 0;\n   parameter clk1_multiply_by              = 0;\n   parameter clk1_divide_by                = 0;\n   parameter clk1_phase_shift              = \"0\";\n   parameter clk1_duty_cycle               = 50;\n   parameter clk2_output_frequency         = 0;\n   parameter clk2_multiply_by              = 0;\n   parameter clk2_divide_by                = 0;\n   parameter clk2_phase_shift              = \"0\";\n   parameter clk2_duty_cycle               = 50;\n   parameter clk3_output_frequency         = 0;\n   parameter clk3_multiply_by              = 0;\n   parameter clk3_divide_by                = 0;\n   parameter clk3_phase_shift              = \"0\";\n   parameter clk3_duty_cycle               = 50;\n   parameter clk4_output_frequency         = 0;\n   parameter clk4_multiply_by              = 0;\n   parameter clk4_divide_by                = 0;\n   parameter clk4_phase_shift              = \"0\";\n   parameter clk4_duty_cycle               = 50;\n   parameter pfd_min                       = 0;\n   parameter pfd_max                       = 0;\n   parameter vco_min                       = 0;\n   parameter vco_max                       = 0;\n   parameter vco_center                    = 0;\n   // Advanced user parameters\n   parameter m_initial = 1;\n   parameter m = 0;\n   parameter n = 1;\n   parameter c0_high = 1;\n   parameter c0_low = 1;\n   parameter c0_initial = 1;\n   parameter c0_mode = \"bypass\";\n   parameter c0_ph = 0;\n   parameter c1_high = 1;\n   parameter c1_low = 1;\n   parameter c1_initial = 1;\n   parameter c1_mode = \"bypass\";\n   parameter c1_ph = 0;\n   parameter c2_high = 1;\n   parameter c2_low = 1;\n   parameter c2_initial = 1;\n   parameter c2_mode = \"bypass\";\n   parameter c2_ph = 0;\n   parameter c3_high = 1;\n   parameter c3_low = 1;\n   parameter c3_initial = 1;\n   parameter c3_mode = \"bypass\";\n   parameter c3_ph = 0;\n   parameter c4_high = 1;\n   parameter c4_low = 1;\n   parameter c4_initial = 1;\n   parameter c4_mode = \"bypass\";\n   parameter c4_ph = 0;\n   parameter m_ph = 0;\n   parameter clk0_counter = \"unused\";\n   parameter clk1_counter = \"unused\";\n   parameter clk2_counter = \"unused\";\n   parameter clk3_counter = \"unused\";\n   parameter clk4_counter = \"unused\";\n   parameter c1_use_casc_in = \"off\";\n   parameter c2_use_casc_in = \"off\";\n   parameter c3_use_casc_in = \"off\";\n   parameter c4_use_casc_in = \"off\";\n   parameter m_test_source  = -1;\n   parameter c0_test_source = -1;\n   parameter c1_test_source = -1;\n   parameter c2_test_source = -1;\n   parameter c3_test_source = -1;\n   parameter c4_test_source = -1;\n   parameter vco_multiply_by = 0;\n   parameter vco_divide_by = 0;\n   parameter vco_post_scale = 1;\n   parameter vco_frequency_control = \"auto\";\n   parameter vco_phase_shift_step = 0;\n   parameter charge_pump_current = 10;\n   parameter loop_filter_r = \"1.0\";\n   parameter loop_filter_c = 0;\n   parameter pll_compensation_delay = 0;\n   parameter lpm_type = \"fiftyfivenm_pll\";\n   parameter phase_counter_select_width = 3;\n\n   input [1:0] inclk;\n   input       fbin;\n   input       clkswitch;\n   input       areset;\n   input       pfdena;\n   input [phase_counter_select_width - 1:0] phasecounterselect;\n   input                                    phaseupdown;\n   input                                    phasestep;\n   input                                    scanclk;\n   input                                    scanclkena;\n   input                                    scandata;\n   input                                    configupdate;\n   output [4:0]                             clk;\n   output [1:0]                             clkbad;\n   output                                   activeclock;\n   output                                   locked;\n   output                                   scandataout;\n   output                                   scandone;\n   output                                   fbout;\n   output                                   phasedone;\n   output                                   vcooverrange;\n   output                                   vcounderrange;\n\nendmodule // cycloneive_pll\n",
+                "cells_sim.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2024  Richard Herveille <richard.herveille@roalogic.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule VCC (output V);\n   assign V = 1'b1;\nendmodule // VCC\n\nmodule GND (output G);\n   assign G = 1'b0;\nendmodule // GND\n\n/* Altera MAX10 devices Input Buffer Primitive */\nmodule fiftyfivenm_io_ibuf\n  (output o, input i, input ibar);\n   assign ibar = ibar;\n   assign o    = i;\nendmodule // fiftyfivenm_io_ibuf\n\n/* Altera MAX10 devices Output Buffer Primitive */\nmodule fiftyfivenm_io_obuf\n  (output o, input i, input oe);\n   assign o  = i;\n   assign oe = oe;\nendmodule // fiftyfivenm_io_obuf\n\n/* Altera MAX10 4-input non-fracturable LUT Primitive */\nmodule fiftyfivenm_lcell_comb\n  (output combout, cout,\n   input dataa, datab, datac, datad, cin);\n\n   /* Internal parameters which define the behaviour\n    of the LUT primitive.\n    lut_mask define the lut function, can be expressed in 16-digit bin or hex.\n    sum_lutc_input define the type of LUT (combinational | arithmetic).\n    dont_touch for retiming || carry options.\n    lpm_type for WYSIWYG */\n\n   parameter lut_mask = 16'hFFFF;\n   parameter dont_touch = \"off\";\n   parameter lpm_type = \"fiftyfivenm_lcell_comb\";\n   parameter sum_lutc_input = \"datac\";\n\n   reg [1:0] lut_type;\n   reg       cout_rt;\n   reg       combout_rt;\n   wire      dataa_w;\n   wire      datab_w;\n   wire      datac_w;\n   wire      datad_w;\n   wire      cin_w;\n\n   assign dataa_w = dataa;\n   assign datab_w = datab;\n   assign datac_w = datac;\n   assign datad_w = datad;\n\n   function lut_data;\n      input [15:0] mask;\n      input        dataa, datab, datac, datad;\n      reg [7:0]    s3;\n      reg [3:0]    s2;\n      reg [1:0]    s1;\n      begin\n         s3 = datad ? mask[15:8] : mask[7:0];\n         s2 = datac ?   s3[7:4]  :   s3[3:0];\n         s1 = datab ?   s2[3:2]  :   s2[1:0];\n         lut_data = dataa ? s1[1] : s1[0];\n      end\n\n   endfunction\n\n   initial begin\n      if (sum_lutc_input == \"datac\") lut_type = 0;\n      else\n        if (sum_lutc_input == \"cin\")   lut_type = 1;\n        else begin\n           $error(\"Error in sum_lutc_input. Parameter %s is not a valid value.\\n\", sum_lutc_input);\n           $finish();\n        end\n   end\n\n   always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin\n      if (lut_type == 0) begin // logic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               datac_w, datad_w);\n      end\n      else if (lut_type == 1) begin // arithmetic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               cin_w, datad_w);\n      end\n      cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);\n   end\n\n   assign combout = combout_rt & 1'b1;\n   assign cout = cout_rt & 1'b1;\n\nendmodule // fiftyfivenm_lcell_comb\n\n/* Altera D Flip-Flop Primitive */\nmodule dffeas\n  (output q,\n   input d, clk, clrn, prn, ena,\n   input asdata, aload, sclr, sload);\n\n   // Timing simulation is not covered\n   parameter power_up=\"dontcare\";\n   parameter is_wysiwyg=\"false\";\n\n   reg   q_tmp;\n   wire  reset;\n   reg [7:0] debug_net;\n\n   assign reset       = (prn && sclr && ~clrn && ena);\n   assign q           = q_tmp & 1'b1;\n\n   always @(posedge clk, posedge aload) begin\n      if(reset)        q_tmp <= 0;\n      else q_tmp <= d;\n   end\n   assign q = q_tmp;\n\nendmodule // dffeas\n\n/* MAX10 altpll clearbox model */\n(* blackbox *)\nmodule fiftyfivenm_pll\n  (inclk,\n   fbin,\n   fbout,\n   clkswitch,\n   areset,\n   pfdena,\n   scanclk,\n   scandata,\n   scanclkena,\n   configupdate,\n   clk,\n   phasecounterselect,\n   phaseupdown,\n   phasestep,\n   clkbad,\n   activeclock,\n   locked,\n   scandataout,\n   scandone,\n   phasedone,\n   vcooverrange,\n   vcounderrange);\n\n   parameter operation_mode                = \"normal\";\n   parameter pll_type                      = \"auto\";\n   parameter compensate_clock              = \"clock0\";\n   parameter inclk0_input_frequency        = 0;\n   parameter inclk1_input_frequency        = 0;\n   parameter self_reset_on_loss_lock       = \"off\";\n   parameter switch_over_type              = \"auto\";\n   parameter switch_over_counter           = 1;\n   parameter enable_switch_over_counter    = \"off\";\n   parameter bandwidth                     = 0;\n   parameter bandwidth_type                = \"auto\";\n   parameter use_dc_coupling               = \"false\";\n   parameter lock_high = 0;\n   parameter lock_low = 0;\n   parameter lock_window_ui                = \"0.05\";\n   parameter test_bypass_lock_detect       = \"off\";\n   parameter clk0_output_frequency         = 0;\n   parameter clk0_multiply_by              = 0;\n   parameter clk0_divide_by                = 0;\n   parameter clk0_phase_shift              = \"0\";\n   parameter clk0_duty_cycle               = 50;\n   parameter clk1_output_frequency         = 0;\n   parameter clk1_multiply_by              = 0;\n   parameter clk1_divide_by                = 0;\n   parameter clk1_phase_shift              = \"0\";\n   parameter clk1_duty_cycle               = 50;\n   parameter clk2_output_frequency         = 0;\n   parameter clk2_multiply_by              = 0;\n   parameter clk2_divide_by                = 0;\n   parameter clk2_phase_shift              = \"0\";\n   parameter clk2_duty_cycle               = 50;\n   parameter clk3_output_frequency         = 0;\n   parameter clk3_multiply_by              = 0;\n   parameter clk3_divide_by                = 0;\n   parameter clk3_phase_shift              = \"0\";\n   parameter clk3_duty_cycle               = 50;\n   parameter clk4_output_frequency         = 0;\n   parameter clk4_multiply_by              = 0;\n   parameter clk4_divide_by                = 0;\n   parameter clk4_phase_shift              = \"0\";\n   parameter clk4_duty_cycle               = 50;\n   parameter pfd_min                       = 0;\n   parameter pfd_max                       = 0;\n   parameter vco_min                       = 0;\n   parameter vco_max                       = 0;\n   parameter vco_center                    = 0;\n   // Advanced user parameters\n   parameter m_initial = 1;\n   parameter m = 0;\n   parameter n = 1;\n   parameter c0_high = 1;\n   parameter c0_low = 1;\n   parameter c0_initial = 1;\n   parameter c0_mode = \"bypass\";\n   parameter c0_ph = 0;\n   parameter c1_high = 1;\n   parameter c1_low = 1;\n   parameter c1_initial = 1;\n   parameter c1_mode = \"bypass\";\n   parameter c1_ph = 0;\n   parameter c2_high = 1;\n   parameter c2_low = 1;\n   parameter c2_initial = 1;\n   parameter c2_mode = \"bypass\";\n   parameter c2_ph = 0;\n   parameter c3_high = 1;\n   parameter c3_low = 1;\n   parameter c3_initial = 1;\n   parameter c3_mode = \"bypass\";\n   parameter c3_ph = 0;\n   parameter c4_high = 1;\n   parameter c4_low = 1;\n   parameter c4_initial = 1;\n   parameter c4_mode = \"bypass\";\n   parameter c4_ph = 0;\n   parameter m_ph = 0;\n   parameter clk0_counter = \"unused\";\n   parameter clk1_counter = \"unused\";\n   parameter clk2_counter = \"unused\";\n   parameter clk3_counter = \"unused\";\n   parameter clk4_counter = \"unused\";\n   parameter c1_use_casc_in = \"off\";\n   parameter c2_use_casc_in = \"off\";\n   parameter c3_use_casc_in = \"off\";\n   parameter c4_use_casc_in = \"off\";\n   parameter m_test_source  = -1;\n   parameter c0_test_source = -1;\n   parameter c1_test_source = -1;\n   parameter c2_test_source = -1;\n   parameter c3_test_source = -1;\n   parameter c4_test_source = -1;\n   parameter vco_multiply_by = 0;\n   parameter vco_divide_by = 0;\n   parameter vco_post_scale = 1;\n   parameter vco_frequency_control = \"auto\";\n   parameter vco_phase_shift_step = 0;\n   parameter charge_pump_current = 10;\n   parameter loop_filter_r = \"1.0\";\n   parameter loop_filter_c = 0;\n   parameter pll_compensation_delay = 0;\n   parameter lpm_type = \"fiftyfivenm_pll\";\n   parameter phase_counter_select_width = 3;\n\n   input [1:0] inclk;\n   input       fbin;\n   input       clkswitch;\n   input       areset;\n   input       pfdena;\n   input [phase_counter_select_width - 1:0] phasecounterselect;\n   input                                    phaseupdown;\n   input                                    phasestep;\n   input                                    scanclk;\n   input                                    scanclkena;\n   input                                    scandata;\n   input                                    configupdate;\n   output [4:0]                             clk;\n   output [1:0]                             clkbad;\n   output                                   activeclock;\n   output                                   locked;\n   output                                   scandataout;\n   output                                   scandone;\n   output                                   fbout;\n   output                                   phasedone;\n   output                                   vcooverrange;\n   output                                   vcounderrange;\n\nendmodule // max10_pll\n\n\n/* MAX10 MULT clearbox model */\n(* blackbox *)\nmodule fiftyfivenm_mac_mult (\n  dataa,\n  datab,\n  dataout,\n  signa,\n  signb,\n\n  aclr,\n  clk,\n  ena\n);\n  parameter dataa_clock = \"none\";\n  parameter dataa_width = 18;\n  parameter datab_clock = \"none\";\n  parameter datab_width = 18;\n  parameter signa_clock = \"none\";\n  parameter signb_clock = \"none\";\n  parameter lpm_type    = \"fiftyfivenm_mac_mult\";\n\n  input  [dataa_width              -1:0] dataa;\n  input  [datab_width              -1:0] datab;\n  output [(dataa_width+datab_width)-1:0] dataout;\n  input                                  signa;\n  input                                  signb;\n  input                                  aclr;\n  input                                  clk;\n  input                                  ena;\nendmodule //fiftyfivenm_mac_mult\n\nmodule fiftyfivenm_mac_out (\n  dataa,\n  dataout,\n\n  aclr,\n  clk,\n  ena\n);\n\n  parameter dataa_width  = 38;\n  parameter output_clock = \"none\";\n  parameter lpm_type     = \"fiftyfivenm_mac_out\";\n\n  input  [dataa_width-1:0] dataa;\n  output [dataa_width-1:0] dataout;\n  input                    aclr;\n  input                    clk;\n  input                    ena;\nendmodule //fiftyfivenm_mac_out\n",
             },
         },
         "intel_alm": {
@@ -380,9 +382,9 @@ export const filesystem = {
             "cells_sim.v": "// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf\n\nmodule AND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A & B;\nendmodule\n\nmodule AND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A & B & C;\nendmodule\n\nmodule AND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A & B & C & D;\nendmodule\n\nmodule CFG1 (\n\toutput Y,\n\tinput A\n);\n\tparameter [1:0] INIT = 2'h0;\n\tassign Y = INIT >> A;\nendmodule\n\nmodule CFG2 (\n\toutput Y,\n\tinput A,\n\tinput B\n);\n\tparameter [3:0] INIT = 4'h0;\n\tassign Y = INIT >> {B, A};\nendmodule\n\nmodule CFG3 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C\n);\n\tparameter [7:0] INIT = 8'h0;\n\tassign Y = INIT >> {C, B, A};\nendmodule\n\nmodule CFG4 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C,\n\tinput D\n);\n\tparameter [15:0] INIT = 16'h0;\n\tassign Y = INIT >> {D, C, B, A};\nendmodule\n\nmodule BUFF (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule BUFD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT_PRESERVE (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule GCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule RCLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule RGCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule SLE (\n\toutput Q,\n\tinput ADn,\n\tinput ALn,\n\t(* clkbuf_sink *)\n\tinput CLK,\n\tinput D,\n\tinput LAT,\n\tinput SD,\n\tinput EN,\n\tinput SLn\n);\n\treg q_latch, q_ff;\n\n\talways @(posedge CLK, negedge ALn) begin\n\t\tif (!ALn) begin\n\t\t\tq_ff <= !ADn;\n\t\tend else if (EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\talways @* begin\n\t\tif (!ALn) begin\n\t\t\tq_latch <= !ADn;\n\t\tend else if (CLK && EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\tassign Q = LAT ? q_latch : q_ff;\nendmodule\n\nmodule ARI1 (\n\tinput A, B, C, D, FCI,\n\toutput Y, S, FCO\n);\n\tparameter [19:0] INIT = 20'h0;\n\twire [2:0] Fsel = {D, C, B};\n\twire F0 = INIT[Fsel];\n\twire F1 = INIT[8 + Fsel];\n\twire Yout = A ? F1 : F0;\n\tassign Y = Yout;\n\tassign S = FCI ^ Yout;\n\twire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];\n\twire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);\n\tassign FCO = P ? FCI : G;\nendmodule\n\n// module FCEND_BUFF\n// module FCINIT_BUFF\n// module FLASH_FREEZE\n// module OSCILLATOR\n// module SYSCTRL_RESET_STATUS\n// module LIVE_PROBE_FB\n\n(* blackbox *)\nmodule GCLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBIBUF (\n\tinput D,\n\tinput E,\n\tinput EN,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n// module DFN1\n// module DFN1C0\n// module DFN1E1\n// module DFN1E1C0\n// module DFN1E1P0\n// module DFN1P0\n// module DLN1\n// module DLN1C0\n// module DLN1P0\n\nmodule INV (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule INVD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule MX2 (\n\tinput A, B, S,\n\toutput Y\n);\n\tassign Y = S ? B : A;\nendmodule\n\nmodule MX4 (\n\tinput D0, D1, D2, D3, S0, S1,\n\toutput Y\n);\n\tassign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);\nendmodule\n\nmodule NAND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A & B);\nendmodule\n\nmodule NAND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A & B & C);\nendmodule\n\nmodule NAND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A & B & C & D);\nendmodule\n\nmodule NOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A | B);\nendmodule\n\nmodule NOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A | B | C);\nendmodule\n\nmodule NOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A | B | C | D);\nendmodule\n\nmodule OR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A | B;\nendmodule\n\nmodule OR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A | B | C;\nendmodule\n\nmodule OR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A | B | C | D;\nendmodule\n\nmodule XOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A ^ B;\nendmodule\n\nmodule XOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C;\nendmodule\n\nmodule XOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D;\nendmodule\n\nmodule XOR8 (\n\tinput A, B, C, D, E, F, G, H,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;\nendmodule\n\n// module UJTAG\n\nmodule BIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule BIBUF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PADP,\n\t(* iopad_external_pin *)\n\tinout PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule CLKBIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\nmodule CLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule CLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule INBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule INBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule OUTBUF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = D;\nendmodule\n\n(* blackbox *)\nmodule OUTBUF_DIFF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule TRIBUFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\nendmodule\n\n(* blackbox *)\nmodule TRIBUFF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\n// module DDR_IN\n// module DDR_OUT\n// module RAM1K18\n// module RAM64x18\n// module MACC\n\n(* blackbox *)\nmodule SYSRESET (\n\t(* iopad_external_pin *)\n\tinput  DEVRST_N,\n\toutput POWER_ON_RESET_N);\nendmodule\n\n\n(* blackbox *)\nmodule XTLOSC (\n\t(* iopad_external_pin *)\n\tinput  XTL,\n\toutput CLKOUT);\n\tparameter [1:0] MODE = 2'h3;\n\tparameter real FREQUENCY = 20.0;\nendmodule\n\n(* blackbox *)\nmodule RAM1K18 (\n\tinput [13:0]  A_ADDR,\n\tinput [2:0]   A_BLK,\n\t(* clkbuf_sink *)\n\tinput\t      A_CLK,\n\tinput [17:0]  A_DIN,\n\toutput [17:0] A_DOUT,\n\tinput [1:0]   A_WEN,\n\tinput [2:0]   A_WIDTH,\n\tinput\t      A_WMODE,\n\tinput\t      A_ARST_N,\n\tinput\t      A_DOUT_LAT,\n\tinput\t      A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t      A_DOUT_CLK,\n\tinput\t      A_DOUT_EN,\n\tinput\t      A_DOUT_SRST_N,\n\n\tinput [13:0]  B_ADDR,\n\tinput [2:0]   B_BLK,\n\t(* clkbuf_sink *)\n\tinput\t      B_CLK,\n\tinput [17:0]  B_DIN,\n\toutput [17:0] B_DOUT,\n\tinput [1:0]   B_WEN,\n\tinput [2:0]   B_WIDTH,\n\tinput\t      B_WMODE,\n\tinput\t      B_ARST_N,\n\tinput\t      B_DOUT_LAT,\n\tinput\t      B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t      B_DOUT_CLK,\n\tinput\t      B_DOUT_EN,\n\tinput\t      B_DOUT_SRST_N,\n\n\tinput\t      A_EN,\n\tinput\t      B_EN,\n\tinput\t      SII_LOCK,\n\toutput\t      BUSY);\nendmodule\n\n(* blackbox *)\nmodule RAM64x18 (\n\tinput [9:0]   A_ADDR,\n\tinput [1:0]   A_BLK,\n\tinput [2:0]   A_WIDTH,\n\toutput [17:0] A_DOUT,\n\tinput\t      A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t      A_DOUT_CLK,\n\tinput\t      A_DOUT_EN,\n\tinput\t      A_DOUT_LAT,\n\tinput\t      A_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t      A_ADDR_CLK,\n\tinput\t      A_ADDR_EN,\n\tinput\t      A_ADDR_LAT,\n\tinput\t      A_ADDR_SRST_N,\n\tinput\t      A_ADDR_ARST_N,\n\n\tinput [9:0]   B_ADDR,\n\tinput [1:0]   B_BLK,\n\tinput [2:0]   B_WIDTH,\n\toutput [17:0] B_DOUT,\n\tinput\t      B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t      B_DOUT_CLK,\n\tinput\t      B_DOUT_EN,\n\tinput\t      B_DOUT_LAT,\n\tinput\t      B_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t      B_ADDR_CLK,\n\tinput\t      B_ADDR_EN,\n\tinput\t      B_ADDR_LAT,\n\tinput\t      B_ADDR_SRST_N,\n\tinput\t      B_ADDR_ARST_N,\n\n\tinput [9:0]   C_ADDR,\n\t(* clkbuf_sink *)\n\tinput\t      C_CLK,\n\tinput [17:0]  C_DIN,\n\tinput\t      C_WEN,\n\tinput [1:0]   C_BLK,\n\tinput [2:0]   C_WIDTH,\n\n\tinput\t      A_EN,\n\tinput\t      B_EN,\n\tinput\t      C_EN,\n\tinput\t      SII_LOCK,\n\toutput\t      BUSY);\nendmodule\n",
         },
         "simcells.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The internal logic cell simulation library.\n *\n *  This Verilog library contains simple simulation models for the internal\n *  logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology\n *  mapper (see \"techmap.v\" in this directory) and expected by the \"abc\" pass.\n *\n */\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_BUF_ (A, Y)\n//* group comb_simple\n//-\n//- A buffer. This cell type is always optimized away by the opt_clean pass.\n//-\n//- Truth table:    A | Y\n//-                ---+---\n//-                 0 | 0\n//-                 1 | 1\n//-\nmodule \\$_BUF_ (A, Y);\ninput A;\noutput Y;\nassign Y = A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NOT_ (A, Y)\n//* group comb_simple\n//-\n//- An inverter gate.\n//-\n//- Truth table:    A | Y\n//-                ---+---\n//-                 0 | 1\n//-                 1 | 0\n//-\nmodule \\$_NOT_ (A, Y);\ninput A;\noutput Y;\nassign Y = ~A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_AND_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input AND gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 0\n//-                 1 0 | 0\n//-                 1 1 | 1\n//-\nmodule \\$_AND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & B;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NAND_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input NAND gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 1\n//-                 1 0 | 1\n//-                 1 1 | 0\n//-\nmodule \\$_NAND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A & B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_OR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input OR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 1\n//-                 1 0 | 1\n//-                 1 1 | 1\n//-\nmodule \\$_OR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | B;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input NOR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 0\n//-                 1 0 | 0\n//-                 1 1 | 0\n//-\nmodule \\$_NOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A | B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_XOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input XOR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 1\n//-                 1 0 | 1\n//-                 1 1 | 0\n//-\nmodule \\$_XOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A ^ B;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_XNOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input XNOR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 0\n//-                 1 0 | 0\n//-                 1 1 | 1\n//-\nmodule \\$_XNOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A ^ B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ANDNOT_ (A, B, Y)\n//* group comb_combined\n//-\n//- A 2-input AND-NOT gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 0\n//-                 1 0 | 1\n//-                 1 1 | 0\n//-\nmodule \\$_ANDNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & (~B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ORNOT_ (A, B, Y)\n//* group comb_combined\n//-\n//- A 2-input OR-NOT gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 0\n//-                 1 0 | 1\n//-                 1 1 | 1\n//-\nmodule \\$_ORNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | (~B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX_ (A, B, S, Y)\n//* group comb_simple\n//-\n//- A 2-input MUX gate.\n//-\n//- Truth table:    A B S | Y\n//-                -------+---\n//-                 a - 0 | a\n//-                 - b 1 | b\n//-\nmodule \\$_MUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? B : A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NMUX_ (A, B, S, Y)\n//-\n//- A 2-input inverting MUX gate.\n//* group comb_combined\n//-\n//- Truth table:    A B S | Y\n//-                -------+---\n//-                 0 - 0 | 1\n//-                 1 - 0 | 0\n//-                 - 0 1 | 1\n//-                 - 1 1 | 0\n//-\nmodule \\$_NMUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? !B : !A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX4_ (A, B, C, D, S, T, Y)\n//* group comb_combined\n//-\n//- A 4-input MUX gate.\n//-\n//- Truth table:    A B C D S T | Y\n//-                -------------+---\n//-                 a - - - 0 0 | a\n//-                 - b - - 1 0 | b\n//-                 - - c - 0 1 | c\n//-                 - - - d 1 1 | d\n//-\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\ninput A, B, C, D, S, T;\noutput Y;\nassign Y = T ? (S ? D : C) :\n               (S ? B : A);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y)\n//* group comb_combined\n//-\n//- An 8-input MUX gate.\n//-\n//- Truth table:    A B C D E F G H S T U | Y\n//-                -----------------------+---\n//-                 a - - - - - - - 0 0 0 | a\n//-                 - b - - - - - - 1 0 0 | b\n//-                 - - c - - - - - 0 1 0 | c\n//-                 - - - d - - - - 1 1 0 | d\n//-                 - - - - e - - - 0 0 1 | e\n//-                 - - - - - f - - 1 0 1 | f\n//-                 - - - - - - g - 0 1 1 | g\n//-                 - - - - - - - h 1 1 1 | h\n//-\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\ninput A, B, C, D, E, F, G, H, S, T, U;\noutput Y;\nassign Y = U ? T ? (S ? H : G) :\n                   (S ? F : E) :\n               T ? (S ? D : C) :\n                   (S ? B : A);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)\n//* group comb_combined\n//-\n//- A 16-input MUX gate.\n//-\n//- Truth table:    A B C D E F G H I J K L M N O P S T U V | Y\n//-                -----------------------------------------+---\n//-                 a - - - - - - - - - - - - - - - 0 0 0 0 | a\n//-                 - b - - - - - - - - - - - - - - 1 0 0 0 | b\n//-                 - - c - - - - - - - - - - - - - 0 1 0 0 | c\n//-                 - - - d - - - - - - - - - - - - 1 1 0 0 | d\n//-                 - - - - e - - - - - - - - - - - 0 0 1 0 | e\n//-                 - - - - - f - - - - - - - - - - 1 0 1 0 | f\n//-                 - - - - - - g - - - - - - - - - 0 1 1 0 | g\n//-                 - - - - - - - h - - - - - - - - 1 1 1 0 | h\n//-                 - - - - - - - - i - - - - - - - 0 0 0 1 | i\n//-                 - - - - - - - - - j - - - - - - 1 0 0 1 | j\n//-                 - - - - - - - - - - k - - - - - 0 1 0 1 | k\n//-                 - - - - - - - - - - - l - - - - 1 1 0 1 | l\n//-                 - - - - - - - - - - - - m - - - 0 0 1 1 | m\n//-                 - - - - - - - - - - - - - n - - 1 0 1 1 | n\n//-                 - - - - - - - - - - - - - - o - 0 1 1 1 | o\n//-                 - - - - - - - - - - - - - - - p 1 1 1 1 | p\n//-\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\ninput A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\noutput Y;\nassign Y = V ? U ? T ? (S ? P : O) :\n                       (S ? N : M) :\n                   T ? (S ? L : K) :\n                       (S ? J : I) :\n               U ? T ? (S ? H : G) :\n                       (S ? F : E) :\n                   T ? (S ? D : C) :\n                       (S ? B : A);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_AOI3_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 3-input And-Or-Invert gate.\n//-\n//- Truth table:    A B C | Y\n//-                -------+---\n//-                 0 0 0 | 1\n//-                 0 0 1 | 0\n//-                 0 1 0 | 1\n//-                 0 1 1 | 0\n//-                 1 0 0 | 1\n//-                 1 0 1 | 0\n//-                 1 1 0 | 0\n//-                 1 1 1 | 0\n//-\nmodule \\$_AOI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A & B) | C);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_OAI3_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 3-input Or-And-Invert gate.\n//-\n//- Truth table:    A B C | Y\n//-                -------+---\n//-                 0 0 0 | 1\n//-                 0 0 1 | 1\n//-                 0 1 0 | 1\n//-                 0 1 1 | 0\n//-                 1 0 0 | 1\n//-                 1 0 1 | 0\n//-                 1 1 0 | 1\n//-                 1 1 1 | 0\n//-\nmodule \\$_OAI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A | B) & C);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_AOI4_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 4-input And-Or-Invert gate.\n//-\n//- Truth table:    A B C D | Y\n//-                ---------+---\n//-                 0 0 0 0 | 1\n//-                 0 0 0 1 | 1\n//-                 0 0 1 0 | 1\n//-                 0 0 1 1 | 0\n//-                 0 1 0 0 | 1\n//-                 0 1 0 1 | 1\n//-                 0 1 1 0 | 1\n//-                 0 1 1 1 | 0\n//-                 1 0 0 0 | 1\n//-                 1 0 0 1 | 1\n//-                 1 0 1 0 | 1\n//-                 1 0 1 1 | 0\n//-                 1 1 0 0 | 0\n//-                 1 1 0 1 | 0\n//-                 1 1 1 0 | 0\n//-                 1 1 1 1 | 0\n//-\nmodule \\$_AOI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A & B) | (C & D));\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_OAI4_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 4-input Or-And-Invert gate.\n//-\n//- Truth table:    A B C D | Y\n//-                ---------+---\n//-                 0 0 0 0 | 1\n//-                 0 0 0 1 | 1\n//-                 0 0 1 0 | 1\n//-                 0 0 1 1 | 1\n//-                 0 1 0 0 | 1\n//-                 0 1 0 1 | 0\n//-                 0 1 1 0 | 0\n//-                 0 1 1 1 | 0\n//-                 1 0 0 0 | 1\n//-                 1 0 0 1 | 0\n//-                 1 0 1 0 | 0\n//-                 1 0 1 1 | 0\n//-                 1 1 0 0 | 1\n//-                 1 1 0 1 | 0\n//-                 1 1 1 0 | 0\n//-                 1 1 1 1 | 0\n//-\nmodule \\$_OAI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A | B) & (C | D));\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_TBUF_ (A, E, Y)\n//* group gate_other\n//-\n//- A tri-state buffer.\n//-\n//- Truth table:    A E | Y\n//-                -----+---\n//-                 a 1 | a\n//-                 - 0 | z\n//-\nmodule \\$_TBUF_ (A, E, Y);\ninput A, E;\noutput Y;\nassign Y = E ? A : 1'bz;\nendmodule\n\n// NOTE: the following cell types are autogenerated.  DO NOT EDIT them manually,\n// instead edit the templates in gen_ff_types.py and rerun it.\n\n// START AUTOGENERATED CELL TYPES\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_NN_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with negative polarity SET and negative polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 0 | 0\n//-                 0 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_NN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_NP_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with negative polarity SET and positive polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 1 | 0\n//-                 0 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_NP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_PN_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with positive polarity SET and negative polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 0 | 0\n//-                 1 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_PN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_PP_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with positive polarity SET and positive polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 1 | 0\n//-                 1 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_PP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n`ifdef SIMCELLS_FF\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_FF_ (D, Q)\n//* group reg_ff\n//-\n//- A D-type flip-flop that is clocked from the implicit global clock. (This cell\n//- type is usually only used in netlists for formal verification.)\n//-\nmodule \\$_FF_ (D, Q);\ninput D;\noutput reg Q;\nalways @($global_clock) begin\n\tQ <= D;\nend\nendmodule\n`endif\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_N_ (D, C, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop.\n//-\n//- Truth table:    D C | Q\n//-                -----+---\n//-                 d \\ | d\n//-                 - - | q\n//-\nmodule \\$_DFF_N_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(negedge C) begin\n\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_P_ (D, C, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop.\n//-\n//- Truth table:    D C | Q\n//-                -----+---\n//-                 d / | d\n//-                 - - | q\n//-\nmodule \\$_DFF_P_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(posedge C) begin\n\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d \\ 0 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_NN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d \\ 1 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_NP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d / 0 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_PN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d / 1 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_PP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_NN_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 0 a  | a\n//-                 d \\ - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_NN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_NP_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 1 a  | a\n//-                 d \\ - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_NP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_PN_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 0 a  | a\n//-                 d / - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_PN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_PP_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 1 a  | a\n//-                 d / - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_PP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NNN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d \\ - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NNP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d \\ - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NPN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d \\ - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NPP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d \\ - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PNN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d / - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PNP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d / - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PPN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d / - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PPP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d / - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NNN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NNP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NPN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NPP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PNN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PNP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PPN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PPP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 0 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 0 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 1 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 1 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 0 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 0 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 1 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 1 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 0 | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 1 | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 0 | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 1 | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 0 | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 1 | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 0 | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 1 | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 0 | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 1 | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 0 | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 1 | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 0 | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 1 | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 0 | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 1 | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_N_ (E, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch.\n//-\n//- Truth table:    E D | Q\n//-                -----+---\n//-                 0 d | d\n//-                 - - | q\n//-\nmodule \\$_DLATCH_N_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_P_ (E, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch.\n//-\n//- Truth table:    E D | Q\n//-                -----+---\n//-                 1 d | d\n//-                 - - | q\n//-\nmodule \\$_DLATCH_P_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NN0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 0\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NN1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 1\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NP0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 0\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NP1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 1\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PN0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 0\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PN1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 1\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PP0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 0\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PP1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 1\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NNN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NNP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NPN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NPP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PNN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PNP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PPN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PPP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n",
-        "simlib.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The Simulation Library.\n *\n *  This Verilog library contains simple simulation models for the internal\n *  cells ($not, ...) generated by the frontends and used in most passes.\n *\n *  This library can be used to verify the internal netlists as generated\n *  by the different frontends and passes.\n *\n *  Note that memory can only be simulated when all $memrd and $memwr cells\n *  have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n *  pass is doing).\n *\n */\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise inverter\n//* group unary\n//- This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $pos (A, Y)\n//* group unary\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $buf (A, Y)\n//* group unary\n//-\n//- A simple coarse-grain buffer cell type for the experimental buffered-normalized\n//- mode. Note this cell does't get removed by 'opt_clean' and is not recommended\n//- for general use.\n//-\nmodule \\$buf (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $neg (A, Y)\n//* group unary\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $and (A, B, Y)\n//* group binary\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $or (A, B, Y)\n//* group binary\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $xor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $xnor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_and (A, Y)\n//* group unary\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_or (A, Y)\n//* group unary\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_xor (A, Y)\n//* group unary\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_xnor (A, Y)\n//* group unary\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_bool (A, Y)\n//* group unary\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $shl (A, B, Y)\n//* group binary\n//-\n//- A logical shift-left operation. This corresponds to the Verilog '<<' operator.\n//-\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $shr (A, B, Y)\n//* group binary\n//-\n//- A logical shift-right operation. This corresponds to the Verilog '>>' operator.\n//-\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sshl (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-left operation. \n//- This corresponds to the Verilog '<<<' operator.\n//-\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sshr (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-right operation.\n//- This corresponds to the Verilog '>>>' operator.\n//-\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Variable shifter\n//* group binary\n//- Performs a right logical shift if the second operand is positive (or\n//- unsigned), and a left logical shift if it is negative.\n//-\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Indexed part-select\n//* group binary\n//* tags x-output\n//- Same as the `$shift` cell, but fills with 'x'.\n//-\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant  bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P;    // Propagate\ninput [WIDTH-1:0] G;    // Generate\ninput CI;               // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Arithmetic logic unit\n//* group arith\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- `$add`, `$sub`, `$lt`, `$le`, `$ge`, `$gt`, `$eq`, `$eqx`, `$ne`, `$nex`\n//- cells into this `$alu` cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A;      // Input operand\ninput [B_WIDTH-1:0] B;      // Input operand\noutput [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,\n                            //          used in combination with\n                            //          reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y;     // Sum\n\ninput CI;                   // Carry-in (set for $sub)\ninput BI;                   // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO;    // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $lt (A, B, Y)\n//* group binary\n//-\n//- A less-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<' operator.\n//-\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $le (A, B, Y)\n//* group binary\n//-\n//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<=' operator.\n//-\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $eq (A, B, Y)\n//* group binary\n//-\n//- An equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '==' operator.\n//-\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $ne (A, B, Y)\n//* group binary\n//-\n//- An inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!=' operator.\n//-\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case equality\n//* group binary\n//* tags x-aware\n//- An exact equality comparison between inputs 'A' and 'B'. Also known as the\n//- case equality operator. This corresponds to the Verilog '===' operator.\n//- Unlike equality comparison that can give 'x' as output, an exact equality\n//- comparison will strictly give '0' or '1' as output, even if input includes\n//- 'x' or 'z' values.\n//-\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case inequality\n//* group binary\n//* tags x-aware\n//- This corresponds to the Verilog '!==' operator.\n//-\n//- Refer to `$eqx` for more details.\n//-\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $ge (A, B, Y)\n//* group binary\n//-\n//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '>=' operator.\n//-\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $gt (A, B, Y)\n//* group binary\n//-\n//- A greater-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '>' operator.\n//-\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $add (A, B, Y)\n//* group binary\n//-\n//-  Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator.\n//-\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sub (A, B, Y)\n//* group binary\n//-\n//- Subtraction between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '-' operator.\n//-\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $mul (A, B, Y)\n//* group binary\n//-\n//- Multiplication of inputs 'A' and 'B'.\n//- This corresponds to the Verilog '*' operator.\n//-\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $macc (A, B, Y)\n//* group arith\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n//     * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED   (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A    (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B    (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Divider\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '/' operator, performing division and\n//- truncating the result (rounding towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Modulo\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '%' operator, giving the module (or\n//- remainder) of division and truncating the result (rounding towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $divfloor (A, B, Y)\n//* group binary\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $modfloor (A, B, Y)\n//* group binary\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $pow (A, B, Y)\n//* group binary\n//-\n//- Exponentiation of an input (Y = A ** B). \n//- This corresponds to the Verilog '**' operator.\n//-\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_not (A, Y)\n//* group unary\n//-\n//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.\n//-\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_and (A, B, Y)\n//* group binary\n//-\n//- A logical AND. This corresponds to the Verilog '&&' operator.\n//-\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_or (A, B, Y)\n//* group binary\n//-\n//- A logical OR. This corresponds to the Verilog '||' operator.\n//-\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group wire\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $concat (A, B, Y)\n//* group wire\n//-\n//- Concatenation of inputs into a single output ( Y = {B, A} ).\n//-\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $mux (A, B, S, Y)\n//-\n//- Multiplexer i.e selecting between two inputs based on select signal.\n//-\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Binary-encoded multiplexer\n//* group mux\n//- Selects between 'slices' of A where each value of S corresponds to a unique\n//- slice.\n//-\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Priority-encoded multiplexer\n//* group mux\n//* tags x-output\n//- Selects between 'slices' of B where each slice corresponds to a single bit\n//- of S. Outputs A when all bits of S are low.\n//-\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $demux (A, S, Y)\n//-\n//- Demultiplexer i.e routing single input to several outputs based on select signal.\n//- Unselected outputs are driven to zero.\n//-\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n//* group logic\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group logic\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $tribuf (A, EN, Y)\n//-\n//- A tri-state buffer. \n//- This buffer conditionally drives the output with the value of the input\n//- based on the enable signal.\n//-\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN     ? (EDGE_POL    ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise case equality\n//* group binary\n//* tags x-aware\n//- A bit-wise version of `$eqx`.\n//-\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise multiplexer\n//* group mux\n//- Equivalent to a series of 1-bit wide `$mux` cells.\n//-\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group fsm\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <-   MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n//* group mem\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
+        "simlib.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The Simulation Library.\n *\n *  This Verilog library contains simple simulation models for the internal\n *  cells ($not, ...) generated by the frontends and used in most passes.\n *\n *  This library can be used to verify the internal netlists as generated\n *  by the different frontends and passes.\n *\n *  Note that memory can only be simulated when all $memrd and $memwr cells\n *  have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n *  pass is doing).\n *\n */\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise inverter\n//* group unary\n//- This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $pos (A, Y)\n//* group unary\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $buf (A, Y)\n//* group unary\n//-\n//- A simple coarse-grain buffer cell type for the experimental buffered-normalized\n//- mode. Note this cell does't get removed by 'opt_clean' and is not recommended\n//- for general use.\n//-\nmodule \\$buf (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $neg (A, Y)\n//* group unary\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $and (A, B, Y)\n//* group binary\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $or (A, B, Y)\n//* group binary\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $xor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $xnor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_and (A, Y)\n//* group unary\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_or (A, Y)\n//* group unary\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_xor (A, Y)\n//* group unary\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_xnor (A, Y)\n//* group unary\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_bool (A, Y)\n//* group unary\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $shl (A, B, Y)\n//* group binary\n//-\n//- A logical shift-left operation. This corresponds to the Verilog '<<' operator.\n//-\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $shr (A, B, Y)\n//* group binary\n//-\n//- A logical shift-right operation. This corresponds to the Verilog '>>' operator.\n//-\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sshl (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-left operation. \n//- This corresponds to the Verilog '<<<' operator.\n//-\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sshr (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-right operation.\n//- This corresponds to the Verilog '>>>' operator.\n//-\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Variable shifter\n//* group binary\n//- Performs a right logical shift if the second operand is positive (or\n//- unsigned), and a left logical shift if it is negative.\n//-\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Indexed part-select\n//* group binary\n//* tags x-output\n//- Same as the `$shift` cell, but fills with 'x'.\n//-\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant  bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P;    // Propagate\ninput [WIDTH-1:0] G;    // Generate\ninput CI;               // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Arithmetic logic unit\n//* group arith\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- `$add`, `$sub`, `$lt`, `$le`, `$ge`, `$gt`, `$eq`, `$eqx`, `$ne`, `$nex`\n//- cells into this `$alu` cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A;      // Input operand\ninput [B_WIDTH-1:0] B;      // Input operand\noutput [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,\n                            //          used in combination with\n                            //          reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y;     // Sum\n\ninput CI;                   // Carry-in (set for $sub)\ninput BI;                   // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO;    // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $lt (A, B, Y)\n//* group binary\n//-\n//- A less-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<' operator.\n//-\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $le (A, B, Y)\n//* group binary\n//-\n//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<=' operator.\n//-\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $eq (A, B, Y)\n//* group binary\n//-\n//- An equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '==' operator.\n//-\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $ne (A, B, Y)\n//* group binary\n//-\n//- An inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!=' operator.\n//-\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case equality\n//* group binary\n//* tags x-aware\n//- An exact equality comparison between inputs 'A' and 'B'. Also known as the\n//- case equality operator. This corresponds to the Verilog '===' operator.\n//- Unlike equality comparison that can give 'x' as output, an exact equality\n//- comparison will strictly give '0' or '1' as output, even if input includes\n//- 'x' or 'z' values.\n//-\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case inequality\n//* group binary\n//* tags x-aware\n//- This corresponds to the Verilog '!==' operator.\n//-\n//- Refer to `$eqx` for more details.\n//-\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $ge (A, B, Y)\n//* group binary\n//-\n//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '>=' operator.\n//-\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $gt (A, B, Y)\n//* group binary\n//-\n//- A greater-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '>' operator.\n//-\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $add (A, B, Y)\n//* group binary\n//-\n//-  Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator.\n//-\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sub (A, B, Y)\n//* group binary\n//-\n//- Subtraction between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '-' operator.\n//-\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $mul (A, B, Y)\n//* group binary\n//-\n//- Multiplication of inputs 'A' and 'B'.\n//- This corresponds to the Verilog '*' operator.\n//-\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $macc (A, B, Y)\n//* group arith\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n//     * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED   (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A    (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B    (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $macc_v2 (A, B, C, Y)\n//* group arith\n//-\n//- Multiply and add.\n//- This cell represents a generic fused multiply-add operation, it supersedes the\n//- earlier $macc cell.\n//-\nmodule \\$macc_v2 (A, B, C, Y);\n\nparameter NPRODUCTS = 0;\nparameter NADDENDS = 0;\nparameter A_WIDTHS = 16'h0000;\nparameter B_WIDTHS = 16'h0000;\nparameter C_WIDTHS = 16'h0000;\nparameter Y_WIDTH = 0;\n\nparameter PRODUCT_NEGATED = 1'bx;\nparameter ADDEND_NEGATED = 1'bx;\nparameter A_SIGNED = 1'bx;\nparameter B_SIGNED = 1'bx;\nparameter C_SIGNED = 1'bx;\n\nfunction integer sum_widths1;\n\tinput [(16*NPRODUCTS)-1:0] widths;\n\tinteger i;\n\tbegin\n\t\tsum_widths1 = 0;\n\t\tfor (i = 0; i < NPRODUCTS; i++) begin\n\t\t\tsum_widths1 = sum_widths1 + widths[16*i+:16];\n\t\tend\n\tend\nendfunction\n\nfunction integer sum_widths2;\n\tinput [(16*NADDENDS)-1:0] widths;\n\tinteger i;\n\tbegin\n\t\tsum_widths2 = 0;\n\t\tfor (i = 0; i < NADDENDS; i++) begin\n\t\t\tsum_widths2 = sum_widths2 + widths[16*i+:16];\n\t\tend\n\tend\nendfunction\n\ninput [sum_widths1(A_WIDTHS)-1:0] A; // concatenation of LHS factors\ninput [sum_widths1(B_WIDTHS)-1:0] B; // concatenation of RHS factors\ninput [sum_widths2(C_WIDTHS)-1:0] C; // concatenation of summands\noutput reg [Y_WIDTH-1:0] Y; // output sum\n\ninteger i, j, ai, bi, ci, aw, bw, cw;\nreg [Y_WIDTH-1:0] product;\nreg [Y_WIDTH-1:0] addend, oper_a, oper_b;\n\nalways @* begin\n\tY = 0;\n\tai = 0;\n\tbi = 0;\n\tfor (i = 0; i < NPRODUCTS; i = i+1)\n\tbegin\n\t\taw = A_WIDTHS[16*i+:16];\n\t\tbw = B_WIDTHS[16*i+:16];\n\n\t\toper_a = 0;\n\t\toper_b = 0;\n\t\tfor (j = 0; j < Y_WIDTH && j < aw; j = j + 1)\n\t\t\toper_a[j] = A[ai + j];\n\t\tfor (j = 0; j < Y_WIDTH && j < bw; j = j + 1)\n\t\t\toper_b[j] = B[bi + j];\n\t\t// A_SIGNED[i] == B_SIGNED[i] as RTLIL invariant\n\t\tif (A_SIGNED[i] && B_SIGNED[i]) begin\n\t\t\tfor (j = aw; j > 0 && j < Y_WIDTH; j = j + 1)\n\t\t\t\toper_a[j] = oper_a[j - 1];\n\t\t\tfor (j = bw; j > 0 && j < Y_WIDTH; j = j + 1)\n\t\t\t\toper_b[j] = oper_b[j - 1];\n\t\tend\n\n\t\tproduct = oper_a * oper_b;\n\n\t\tif (PRODUCT_NEGATED[i])\n\t\t\tY = Y - product;\n\t\telse\n\t\t\tY = Y + product;\n\n\t\tai = ai + aw;\n\t\tbi = bi + bw;\n\tend\n\n\tci = 0;\n\tfor (i = 0; i < NADDENDS; i = i+1)\n\tbegin\n\t\tcw = C_WIDTHS[16*i+:16];\n\n\t\taddend = 0;\n\t\tfor (j = 0; j < Y_WIDTH && j < cw; j = j + 1)\n\t\t\taddend[j] = C[ci + j];\n\t\tif (C_SIGNED[i]) begin\n\t\t\tfor (j = cw; j > 0 && j < Y_WIDTH; j = j + 1)\n\t\t\t\taddend[j] = addend[j - 1];\n\t\tend\n\n\t\tif (ADDEND_NEGATED[i])\n\t\t\tY = Y - addend;\n\t\telse\n\t\t\tY = Y + addend;\n\n\t\tci = ci + cw;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Divider\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '/' operator, performing division and\n//- truncating the result (rounding towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Modulo\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '%' operator, giving the module (or\n//- remainder) of division and truncating the result (rounding towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $divfloor (A, B, Y)\n//* group binary\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $modfloor (A, B, Y)\n//* group binary\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $pow (A, B, Y)\n//* group binary\n//-\n//- Exponentiation of an input (Y = A ** B). \n//- This corresponds to the Verilog '**' operator.\n//-\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_not (A, Y)\n//* group unary\n//-\n//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.\n//-\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_and (A, B, Y)\n//* group binary\n//-\n//- A logical AND. This corresponds to the Verilog '&&' operator.\n//-\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_or (A, B, Y)\n//* group binary\n//-\n//- A logical OR. This corresponds to the Verilog '||' operator.\n//-\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group wire\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $concat (A, B, Y)\n//* group wire\n//-\n//- Concatenation of inputs into a single output ( Y = {B, A} ).\n//-\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $mux (A, B, S, Y)\n//-\n//- Multiplexer i.e selecting between two inputs based on select signal.\n//-\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Binary-encoded multiplexer\n//* group mux\n//- Selects between 'slices' of A where each value of S corresponds to a unique\n//- slice.\n//-\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Priority-encoded multiplexer\n//* group mux\n//* tags x-output\n//- Selects between 'slices' of B where each slice corresponds to a single bit\n//- of S. Outputs A when all bits of S are low.\n//-\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $demux (A, S, Y)\n//-\n//- Demultiplexer i.e routing single input to several outputs based on select signal.\n//- Unselected outputs are driven to zero.\n//-\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n//* group logic\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group logic\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $tribuf (A, EN, Y)\n//-\n//- A tri-state buffer. \n//- This buffer conditionally drives the output with the value of the input\n//- based on the enable signal.\n//-\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN     ? (EDGE_POL    ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise case equality\n//* group binary\n//* tags x-aware\n//- A bit-wise version of `$eqx`.\n//-\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise multiplexer\n//* group mux\n//- Equivalent to a series of 1-bit wide `$mux` cells.\n//-\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter signed ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter signed TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group fsm\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <-   MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n//* group mem\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
         "smtmap.v": "(* techmap_celltype = \"$pmux\" *)\nmodule smt_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*(S_WIDTH+1)-1:0] C;\n\n\t\tassign C[WIDTH-1:0] = A;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1)\n\t\t\tassign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i];\n\t\tassign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH];\n\tendgenerate\nendmodule\n",
-        "techmap.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The internal logic cell technology mapper.\n *\n *  This Verilog library contains the mapping of internal cells (e.g. $not with\n *  variable bit width) to the internal logic cells (such as the single bit $_NOT_\n *  gate). Usually this logic network is then mapped to the actual technology\n *  using e.g. the \"abc\" pass.\n *\n *  Note that this library does not map $mem cells. They must be mapped to logic\n *  and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n *  which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\n`ifndef NODIV\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n`endif\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
+        "techmap.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The internal logic cell technology mapper.\n *\n *  This Verilog library contains the mapping of internal cells (e.g. $not with\n *  variable bit width) to the internal logic cells (such as the single bit $_NOT_\n *  gate). Usually this logic network is then mapped to the actual technology\n *  using e.g. the \"abc\" pass.\n *\n *  Note that this library does not map $mem cells. They must be mapped to logic\n *  and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n *  which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$buf $pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc $macc_v2\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\n`ifndef NODIV\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n`endif\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
         "xilinx": {
             "abc9_model.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *                2019  Eddie Hung    <eddie@fpgeh.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n\n// Box containing MUXF7.[AB] + MUXF8,\n//   Necessary to make these an atomic unit so that\n//   ABC cannot optimise just one of the MUXF7 away\n//   and expect to save on its delay\n(* abc9_box, lib_whitebox *)\nmodule \\$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);\n  assign O = S1 ? (S0 ? I3 : I2)\n                : (S0 ? I1 : I0);\n  specify\n    (I0 => O) = 294;\n    (I1 => O) = 297;\n    (I2 => O) = 311;\n    (I3 => O) = 317;\n    (S0 => O) = 390;\n    (S1 => O) = 273;\n  endspecify\nendmodule\n",
             "arith_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n// LCU\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _80_xilinx_lcu (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = WIDTH <= 2;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [WIDTH-1:0] S = P & ~G;\n\n\tgenerate for (i = 0; i < WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(G[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\tend endgenerate\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH    = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH    = MAX_WIDTH - WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S =  {{PAD_WIDTH{1'b0}}, P & ~G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign CO = C;\n\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI    (1'd0),\n\t\t\t.DI    (GG[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4]),\n\t\t\t);\n\t\tend else begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI    (C [i*4 - 1]),\n\t\t\t.DI    (GG[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4]),\n\t\t\t);\n\t\tend\n\tend endgenerate\nend endgenerate\n\nendmodule\n\n\n// ============================================================================\n// ALU\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_xilinx_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\tparameter _TECHMAP_CONSTVAL_CI_ = 0;\n\tparameter _TECHMAP_CONSTMSK_CI_ = 0;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] S  = {AA ^ BB};\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(AA[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\t\tXORCY xorcy (\n\t\t\t.CI(C[i]),\n\t\t\t.LI(S[i]),\n\t\t\t.O(Y[i])\n\t\t);\n\tend endgenerate\n\n\tassign X = S;\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH    = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH    = MAX_WIDTH - Y_WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, AA ^ BB};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] O;\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign Y = O, CO = C;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI    (1'd0),\n\t\t\t.DI    (DI[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.O     (O [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4])\n\t\t\t);\n\t\tend else begin\n\t\t    CARRY4 carry4\n\t\t    (\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI    (C [i*4 - 1]),\n\t\t\t.DI    (DI[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.O     (O [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4])\n\t\t    );\n\t\tend\n\tend endgenerate\n\n\tassign X = S;\n\nend endgenerate\nendmodule\n\n",
@@ -398,7 +400,7 @@ export const filesystem = {
             "brams_xcu_map.v": "module $__XILINX_BLOCKRAM_TDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_MODE = \"FULL\";\nparameter OPTION_HAS_RDFIRST = 0;\n\nparameter PORT_A_RD_WIDTH = 1;\nparameter PORT_A_WR_WIDTH = 1;\nparameter PORT_A_WR_EN_WIDTH = 1;\nparameter PORT_A_RD_USED = 1;\nparameter PORT_A_WR_USED = 1;\nparameter PORT_A_OPTION_WRITE_MODE = \"NO_CHANGE\";\nparameter PORT_A_RD_INIT_VALUE = 0;\nparameter PORT_A_RD_SRST_VALUE = 1;\n\nparameter PORT_B_RD_WIDTH = 1;\nparameter PORT_B_WR_WIDTH = 1;\nparameter PORT_B_WR_EN_WIDTH = 1;\nparameter PORT_B_RD_USED = 0;\nparameter PORT_B_WR_USED = 0;\nparameter PORT_B_OPTION_WRITE_MODE = \"NO_CHANGE\";\nparameter PORT_B_RD_INIT_VALUE = 0;\nparameter PORT_B_RD_SRST_VALUE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput [15:0] PORT_A_ADDR;\ninput [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;\ninput [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;\noutput [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;\ninput PORT_A_RD_SRST;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput [15:0] PORT_B_ADDR;\ninput [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;\ninput [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;\noutput [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;\ninput PORT_B_RD_SRST;\n\n`include \"brams_defs.vh\"\n\n`define PARAMS_COMMON \\\n\t.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \\\n\t.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \\\n\t.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \\\n\t.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \\\n\t.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \\\n\t.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \\\n\t.DOA_REG(0), \\\n\t.DOB_REG(0), \\\n\t.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \\\n\t.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \\\n\t.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \\\n\t.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)),\n\n`define PORTS_COMMON \\\n\t.DOUTADOUT(DO_A), \\\n\t.DOUTPADOUTP(DOP_A), \\\n\t.DINADIN(DI_A), \\\n\t.DINPADINP(DIP_A), \\\n\t.DOUTBDOUT(DO_B), \\\n\t.DOUTPBDOUTP(DOP_B), \\\n\t.DINBDIN(DI_B), \\\n\t.DINPBDINP(DIP_B), \\\n\t.CLKARDCLK(PORT_A_CLK), \\\n\t.CLKBWRCLK(PORT_B_CLK), \\\n\t.ENARDEN(PORT_A_CLK_EN), \\\n\t.ENBWREN(PORT_B_CLK_EN), \\\n\t.REGCEAREGCE(1'b0), \\\n\t.REGCEB(1'b0), \\\n\t.ADDRENA(1'b1), \\\n\t.ADDRENB(1'b1), \\\n\t.RSTRAMARSTRAM(PORT_A_RD_SRST), \\\n\t.RSTRAMB(PORT_B_RD_SRST), \\\n\t.RSTREGARSTREG(1'b0), \\\n\t.RSTREGB(1'b0), \\\n\t.WEA(WE_A), \\\n\t.WEBWE(WE_B), \\\n\t.ADDRARDADDR(PORT_A_ADDR), \\\n\t.ADDRBWRADDR(PORT_B_ADDR), \\\n\t.SLEEP(1'b0),\n\n`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)\n`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)\n`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)\n`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)\n\nwire [3:0] WE_A = {4{PORT_A_WR_EN}};\nwire [3:0] WE_B = {4{PORT_B_WR_EN}};\n\ngenerate\n\nif (OPTION_MODE == \"HALF\") begin\n\tRAMB18E2 #(\n\t\t`PARAMS_INIT_18\n\t\t`PARAMS_INITP_18\n\t\t`PARAMS_COMMON\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_COMMON\n\t);\nend else if (OPTION_MODE == \"FULL\") begin\n\tRAMB36E2 #(\n\t\t`PARAMS_INIT_36\n\t\t`PARAMS_INITP_36\n\t\t`PARAMS_COMMON\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_COMMON\n\t);\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__XILINX_BLOCKRAM_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_MODE = \"FULL\";\nparameter OPTION_WRITE_MODE = \"READ_FIRST\";\n\nparameter PORT_W_WIDTH = 1;\nparameter PORT_W_WR_EN_WIDTH = 1;\nparameter PORT_W_USED = 1;\n\nparameter PORT_R_WIDTH = 1;\nparameter PORT_R_USED = 0;\nparameter PORT_R_RD_INIT_VALUE = 0;\nparameter PORT_R_RD_SRST_VALUE = 0;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput [15:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\ninput [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput [15:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\ninput PORT_R_RD_SRST;\n\n`include \"brams_defs.vh\"\n\n`define PARAMS_COMMON \\\n\t.WRITE_MODE_A(OPTION_WRITE_MODE), \\\n\t.WRITE_MODE_B(OPTION_WRITE_MODE), \\\n\t.READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \\\n\t.READ_WIDTH_B(0), \\\n\t.WRITE_WIDTH_A(0), \\\n\t.WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \\\n\t.DOA_REG(0), \\\n\t.DOB_REG(0),\n\n`define PORTS_COMMON \\\n\t.CLKBWRCLK(PORT_W_CLK), \\\n\t.CLKARDCLK(PORT_R_CLK), \\\n\t.ENBWREN(PORT_W_CLK_EN), \\\n\t.ENARDEN(PORT_R_CLK_EN), \\\n\t.REGCEAREGCE(1'b0), \\\n\t.REGCEB(1'b0), \\\n\t.ADDRENA(1'b1), \\\n\t.ADDRENB(1'b1), \\\n\t.RSTRAMARSTRAM(PORT_R_RD_SRST), \\\n\t.RSTRAMB(1'b0), \\\n\t.RSTREGARSTREG(1'b0), \\\n\t.RSTREGB(1'b0), \\\n\t.WEA(0), \\\n\t.WEBWE(PORT_W_WR_EN), \\\n\t.ADDRARDADDR(PORT_R_ADDR), \\\n\t.ADDRBWRADDR(PORT_W_ADDR), \\\n\t.SLEEP(1'b0),\n\n`MAKE_DI(DI, DIP, PORT_W_WR_DATA)\n`MAKE_DO(DO, DOP, PORT_R_RD_DATA)\n\ngenerate\n\nif (OPTION_MODE == \"HALF\") begin\n\tRAMB18E2 #(\n\t\t`PARAMS_INIT_18\n\t\t`PARAMS_INITP_18\n\t\t`PARAMS_COMMON\n\t\t.INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),\n\t\t.INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0),\n\t\t.SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),\n\t\t.SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0),\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_COMMON\n\t\t.DOUTADOUT(DO[15:0]),\n\t\t.DOUTBDOUT(DO[31:16]),\n\t\t.DOUTPADOUTP(DOP[1:0]),\n\t\t.DOUTPBDOUTP(DOP[3:2]),\n\t\t.DINADIN(DI[15:0]),\n\t\t.DINBDIN(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]),\n\t\t.DINPADINP(DIP[1:0]),\n\t\t.DINPBDINP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]),\n\t);\nend else if (OPTION_MODE == \"FULL\") begin\n\tRAMB36E2 #(\n\t\t`PARAMS_INIT_36\n\t\t`PARAMS_INITP_36\n\t\t`PARAMS_COMMON\n\t\t.INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),\n\t\t.INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0),\n\t\t.SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),\n\t\t.SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0),\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_COMMON\n\t\t.DOUTADOUT(DO[31:0]),\n\t\t.DOUTBDOUT(DO[63:32]),\n\t\t.DOUTPADOUTP(DOP[3:0]),\n\t\t.DOUTPBDOUTP(DOP[7:4]),\n\t\t.DINADIN(DI[31:0]),\n\t\t.DINBDIN(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),\n\t\t.DINPADINP(DIP[3:0]),\n\t\t.DINPBDINP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),\n\t);\nend\n\nendgenerate\n\nendmodule\n\n",
             "brams_xcv.txt": "# Block RAMs for the original Virtex.\n# The corresponding mapping file is brams_xcv_map.v\n\nram block $__XILINX_BLOCKRAM_ {\n\tabits 12;\n\twidths 1 2 4 8 16 per_port;\n\tcost 32;\n\tinit any;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\trdwr new;\n\t\trdinit zero;\n\t\trdsrst zero gated_clken;\n\t\toptional;\n\t}\n}\n",
             "brams_xcv_map.v": "module $__XILINX_BLOCKRAM_ (...);\n\nparameter INIT = 0;\n\nparameter PORT_A_WIDTH = 1;\nparameter PORT_B_WIDTH = 1;\nparameter PORT_A_USED = 1;\nparameter PORT_B_USED = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput [11:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\ninput PORT_A_WR_EN;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\ninput PORT_A_RD_SRST;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput [11:0] PORT_B_ADDR;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\ninput PORT_B_WR_EN;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\ninput PORT_B_RD_SRST;\n\n`define PARAMS_INIT \\\n\t.INIT_00(INIT[0*256+:256]), \\\n\t.INIT_01(INIT[1*256+:256]), \\\n\t.INIT_02(INIT[2*256+:256]), \\\n\t.INIT_03(INIT[3*256+:256]), \\\n\t.INIT_04(INIT[4*256+:256]), \\\n\t.INIT_05(INIT[5*256+:256]), \\\n\t.INIT_06(INIT[6*256+:256]), \\\n\t.INIT_07(INIT[7*256+:256]), \\\n\t.INIT_08(INIT[8*256+:256]), \\\n\t.INIT_09(INIT[9*256+:256]), \\\n\t.INIT_0A(INIT[10*256+:256]), \\\n\t.INIT_0B(INIT[11*256+:256]), \\\n\t.INIT_0C(INIT[12*256+:256]), \\\n\t.INIT_0D(INIT[13*256+:256]), \\\n\t.INIT_0E(INIT[14*256+:256]), \\\n\t.INIT_0F(INIT[15*256+:256]),\n\n`define PORTS_DP(addr_slice_a, addr_slice_b) \\\n\t.CLKA(PORT_A_CLK), \\\n\t.ENA(PORT_A_CLK_EN), \\\n\t.WEA(PORT_A_WR_EN), \\\n\t.RSTA(PORT_A_RD_SRST), \\\n\t.ADDRA(PORT_A_ADDR addr_slice_a), \\\n\t.DOA(PORT_A_RD_DATA), \\\n\t.DIA(PORT_A_WR_DATA), \\\n\t.CLKB(PORT_B_CLK), \\\n\t.ENB(PORT_B_CLK_EN), \\\n\t.WEB(PORT_B_WR_EN), \\\n\t.RSTB(PORT_B_RD_SRST), \\\n\t.ADDRB(PORT_B_ADDR addr_slice_b), \\\n\t.DOB(PORT_B_RD_DATA), \\\n\t.DIB(PORT_B_WR_DATA),\n\n`define PORTS_DP_SWAP(addr_slice_a, addr_slice_b) \\\n\t.CLKB(PORT_A_CLK), \\\n\t.ENB(PORT_A_CLK_EN), \\\n\t.WEB(PORT_A_WR_EN), \\\n\t.RSTB(PORT_A_RD_SRST), \\\n\t.ADDRB(PORT_A_ADDR addr_slice_a), \\\n\t.DOB(PORT_A_RD_DATA), \\\n\t.DIB(PORT_A_WR_DATA), \\\n\t.CLKA(PORT_B_CLK), \\\n\t.ENA(PORT_B_CLK_EN), \\\n\t.WEA(PORT_B_WR_EN), \\\n\t.RSTA(PORT_B_RD_SRST), \\\n\t.ADDRA(PORT_B_ADDR addr_slice_b), \\\n\t.DOA(PORT_B_RD_DATA), \\\n\t.DIA(PORT_B_WR_DATA),\n\n`define PORTS_SP(addr_slice) \\\n\t.CLK(PORT_A_CLK), \\\n\t.EN(PORT_A_CLK_EN), \\\n\t.WE(PORT_A_WR_EN), \\\n\t.RST(PORT_A_RD_SRST), \\\n\t.ADDR(PORT_A_ADDR addr_slice), \\\n\t.DO(PORT_A_RD_DATA), \\\n\t.DI(PORT_A_WR_DATA),\n\ngenerate\n\nif (!PORT_B_USED) begin\n\tcase (PORT_A_WIDTH)\n\t1: RAMB4_S1 #(\n\t\t`PARAMS_INIT\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_SP([11:0])\n\t);\n\t2: RAMB4_S2 #(\n\t\t`PARAMS_INIT\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_SP([11:1])\n\t);\n\t4: RAMB4_S4 #(\n\t\t`PARAMS_INIT\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_SP([11:2])\n\t);\n\t8: RAMB4_S8 #(\n\t\t`PARAMS_INIT\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_SP([11:3])\n\t);\n\t16: RAMB4_S16 #(\n\t\t`PARAMS_INIT\n\t) _TECHMAP_REPLACE_ (\n\t\t`PORTS_SP([11:4])\n\t);\n\tendcase\nend else begin\n\tcase (PORT_A_WIDTH)\n\t1:\tcase(PORT_B_WIDTH)\n\t\t1: RAMB4_S1_S1 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:0], [11:0])\n\t\t);\n\t\t2: RAMB4_S1_S2 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:0], [11:1])\n\t\t);\n\t\t4: RAMB4_S1_S4 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:0], [11:2])\n\t\t);\n\t\t8: RAMB4_S1_S8 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:0], [11:3])\n\t\t);\n\t\t16: RAMB4_S1_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:0], [11:4])\n\t\t);\n\t\tendcase\n\t2:\tcase(PORT_B_WIDTH)\n\t\t1: RAMB4_S1_S2 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:1], [11:0])\n\t\t);\n\t\t2: RAMB4_S2_S2 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:1], [11:1])\n\t\t);\n\t\t4: RAMB4_S2_S4 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:1], [11:2])\n\t\t);\n\t\t8: RAMB4_S2_S8 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:1], [11:3])\n\t\t);\n\t\t16: RAMB4_S2_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:1], [11:4])\n\t\t);\n\t\tendcase\n\t4:\tcase(PORT_B_WIDTH)\n\t\t1: RAMB4_S1_S4 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:2], [11:0])\n\t\t);\n\t\t2: RAMB4_S2_S4 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:2], [11:1])\n\t\t);\n\t\t4: RAMB4_S4_S4 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:2], [11:2])\n\t\t);\n\t\t8: RAMB4_S4_S8 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:2], [11:3])\n\t\t);\n\t\t16: RAMB4_S4_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:2], [11:4])\n\t\t);\n\t\tendcase\n\t8:\tcase(PORT_B_WIDTH)\n\t\t1: RAMB4_S1_S8 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:3], [11:0])\n\t\t);\n\t\t2: RAMB4_S2_S8 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:3], [11:1])\n\t\t);\n\t\t4: RAMB4_S4_S8 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:3], [11:2])\n\t\t);\n\t\t8: RAMB4_S8_S8 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:3], [11:3])\n\t\t);\n\t\t16: RAMB4_S8_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:3], [11:4])\n\t\t);\n\t\tendcase\n\t16:\tcase(PORT_B_WIDTH)\n\t\t1: RAMB4_S1_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:4], [11:0])\n\t\t);\n\t\t2: RAMB4_S2_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:4], [11:1])\n\t\t);\n\t\t4: RAMB4_S4_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:4], [11:2])\n\t\t);\n\t\t8: RAMB4_S8_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP_SWAP([11:4], [11:3])\n\t\t);\n\t\t16: RAMB4_S16_S16 #(\n\t\t\t`PARAMS_INIT\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t`PORTS_DP([11:4], [11:4])\n\t\t);\n\t\tendcase\n\tendcase\nend\n\nendgenerate\n\nendmodule\n",
-            "cells_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *                2019  Eddie Hung    <eddie@fpgeh.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule \\$__SHREG_ (input C, input D, input E, output Q);\n  parameter DEPTH = 0;\n  parameter [DEPTH-1:0] INIT = 0;\n  parameter CLKPOL = 1;\n  parameter ENPOL = 2;\n\n  \\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));\nendmodule\n\nmodule \\$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);\n  parameter DEPTH = 0;\n  parameter [DEPTH-1:0] INIT = 0;\n  parameter CLKPOL = 1;\n  parameter ENPOL = 2;\n\n  // shregmap's INIT parameter shifts out LSB first;\n  // however Xilinx expects MSB first\n  function [DEPTH-1:0] brev;\n    input [DEPTH-1:0] din;\n    integer i;\n    begin\n      for (i = 0; i < DEPTH; i=i+1)\n        brev[i] = din[DEPTH-1-i];\n    end\n  endfunction\n  localparam [DEPTH-1:0] INIT_R = brev(INIT);\n\n  parameter _TECHMAP_CONSTMSK_L_ = 0;\n\n  wire CE;\n  generate\n    if (ENPOL == 0)\n      assign CE = ~E;\n    else if (ENPOL == 1)\n      assign CE = E;\n    else\n      assign CE = 1'b1;\n    if (DEPTH == 1) begin\n      if (CLKPOL)\n          FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));\n      else\n          FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));\n    end else\n    if (DEPTH <= 16) begin\n      SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));\n    end else\n    if (DEPTH > 17 && DEPTH <= 32) begin\n      SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));\n    end else\n    if (DEPTH > 33 && DEPTH <= 64) begin\n      wire T0, T1, T2;\n      SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T2;\n      else\n        MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));\n    end else\n    if (DEPTH > 65 && DEPTH <= 96) begin\n      wire T0, T1, T2, T3, T4, T5, T6;\n      SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));\n      SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T4;\n      else\n        \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));\n    end else\n    if (DEPTH > 97 && DEPTH < 128) begin\n      wire T0, T1, T2, T3, T4, T5, T6, T7, T8;\n      SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));\n      SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));\n      SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T6;\n      else\n        \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));\n    end\n    else if (DEPTH == 128) begin\n      wire T0, T1, T2, T3, T4, T5, T6;\n      SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));\n      SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));\n      SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));\n      SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T6;\n      else\n        \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));\n    end\n    // For fixed length, if just 1 over a convenient value, decompose\n    else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin\n      wire T;\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));\n      \\$__XILINX_SHREG_ #(.DEPTH(1),       .INIT(INIT[0]),         .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));\n    end\n    // For variable length, if just 1 over a convenient value, then bump up one more\n    else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));\n    else begin\n      localparam depth0 = 128;\n      localparam num_srl128 = DEPTH / depth0;\n      localparam depthN = DEPTH % depth0;\n      wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;\n      wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;\n      assign S[0] = D;\n      genvar i;\n      for (i = 0; i < num_srl128; i++)\n        \\$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(S[i]),          .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));\n\n      if (depthN > 0)\n        \\$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]),               .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));\n\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];\n      else\n        assign Q = T[L[DEPTH-1:$clog2(depth0)]];\n    end\n  endgenerate\nendmodule\n\n`ifdef MIN_MUX_INPUTS\nmodule \\$__XILINX_SHIFTX (A, B, Y);\n  parameter A_SIGNED = 0;\n  parameter B_SIGNED = 0;\n  parameter A_WIDTH = 1;\n  parameter B_WIDTH = 1;\n  parameter Y_WIDTH = 1;\n\n  (* force_downto *)\n  input [A_WIDTH-1:0] A;\n  (* force_downto *)\n  input [B_WIDTH-1:0] B;\n  (* force_downto *)\n  output [Y_WIDTH-1:0] Y;\n\n  parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;\n  parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;\n  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n  function integer A_WIDTH_trimmed;\n    input integer start;\n  begin\n    A_WIDTH_trimmed = start;\n    while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)\n      A_WIDTH_trimmed = A_WIDTH_trimmed - 1;\n  end\n  endfunction\n\n  generate\n    genvar i, j;\n    // Bit-blast\n    if (Y_WIDTH > 1) begin\n      for (i = 0; i < Y_WIDTH; i++)\n        \\$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));\n    end\n    // If the LSB of B is constant zero (and Y_WIDTH is 1) then\n    //   we can optimise by removing every other entry from A\n    //   and popping the constant zero from B\n    else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin\n      wire [(A_WIDTH+1)/2-1:0] A_i;\n      for (i = 0; i < (A_WIDTH+1)/2; i++)\n        assign A_i[i] = A[i*2];\n      \\$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));\n    end\n    // Trim off any leading 1'bx -es in A\n    else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin\n      localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);\n      \\$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));\n    end\n    else if (A_WIDTH < `MIN_MUX_INPUTS) begin\n      wire _TECHMAP_FAIL_ = 1;\n    end\n    else if (A_WIDTH == 2) begin\n      MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));\n    end\n    else if (A_WIDTH <= 4) begin\n      wire [4-1:0] Ax;\n      if (A_WIDTH == 4)\n        assign Ax = A;\n      else\n        // Rather than extend with 1'bx which gets flattened to 1'b0\n        // causing the \"don't care\" status to get lost, extend with\n        // the same driver of F7B.I0 so that we can optimise F7B away\n        // later\n        assign Ax = {A[1], A};\n      \\$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));\n    end\n    // Note that the following decompositions are 'backwards' in that\n    // the LSBs are placed on the hard resources, and the soft resources\n    // are used for MSBs.\n    // This has the effect of more effectively utilising the hard mux;\n    // take for example a 5:1 multiplexer, currently this would map as:\n    //\n    //     A[0] \\___  __                             A[0] \\__  __\n    //     A[4] /   \\|  \\       whereas the more     A[1] /  \\|  \\\n    //     A[1] _____|   |      obvious mapping      A[2] \\___|   |\n    //     A[2] _____|   |--    of MSBs to hard      A[3] /   |   |__\n    //     A[3]______|   |      resources would      A[4] ____|   |\n    //               |__/       lead to:             1'bx ____|   |\n    //                ||                                      |__/\n    //                ||                                       ||\n    //              B[1:0]                                   B[1:2]\n    //\n    // Expectation would be that the 'forward' mapping (right) is more\n    // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers\n    // on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs)\n    // but that the 'backwards' mapping (left) is more delay efficient\n    // since smaller LUTs are faster than wider ones.\n    else if (A_WIDTH <= 8) begin\n      wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};\n      wire T0 = B[2] ? Ax[4] : Ax[0];\n      wire T1 = B[2] ? Ax[5] : Ax[1];\n      wire T2 = B[2] ? Ax[6] : Ax[2];\n      wire T3 = B[2] ? Ax[7] : Ax[3];\n      \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));\n    end\n    else if (A_WIDTH <= 16) begin\n      wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A};\n      wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]\n                     : B[3] ? Ax[ 8] : Ax[0];\n      wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]\n                     : B[3] ? Ax[ 9] : Ax[1];\n      wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6]\n                     : B[3] ? Ax[10] : Ax[2];\n      wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7]\n                     : B[3] ? Ax[11] : Ax[3];\n      \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));\n    end\n    else begin\n      localparam num_mux16 = (A_WIDTH+15) / 16;\n      localparam clog2_num_mux16 = $clog2(num_mux16);\n      wire [num_mux16-1:0] T;\n      wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};\n      for (i = 0; i < num_mux16; i++)\n        \\$__XILINX_SHIFTX  #(\n          .A_SIGNED(A_SIGNED),\n          .B_SIGNED(B_SIGNED),\n          .A_WIDTH(16),\n          .B_WIDTH(4),\n          .Y_WIDTH(Y_WIDTH)\n        ) fpga_mux (\n          .A(Ax[i*16+:16]),\n          .B(B[3:0]),\n          .Y(T[i])\n        );\n      \\$__XILINX_SHIFTX  #(\n          .A_SIGNED(A_SIGNED),\n          .B_SIGNED(B_SIGNED),\n          .A_WIDTH(num_mux16),\n          .B_WIDTH(clog2_num_mux16),\n          .Y_WIDTH(Y_WIDTH)\n      ) _TECHMAP_REPLACE_ (\n          .A(T),\n          .B(B[B_WIDTH-1-:clog2_num_mux16]),\n          .Y(Y));\n    end\n  endgenerate\nendmodule\n\n(* techmap_celltype = \"$__XILINX_SHIFTX\" *)\nmodule _90__XILINX_SHIFTX (A, B, Y);\n  parameter A_SIGNED = 0;\n  parameter B_SIGNED = 0;\n  parameter A_WIDTH = 1;\n  parameter B_WIDTH = 1;\n  parameter Y_WIDTH = 1;\n\n  (* force_downto *)\n  input [A_WIDTH-1:0] A;\n  (* force_downto *)\n  input [B_WIDTH-1:0] B;\n  (* force_downto *)\n  output [Y_WIDTH-1:0] Y;\n\n  \\$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));\nendmodule\n\nmodule \\$_MUX_ (A, B, S, Y);\n  input A, B, S;\n  output Y;\n  generate\n    if (`MIN_MUX_INPUTS == 2)\n      \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));\n    else\n      wire _TECHMAP_FAIL_ = 1;\n  endgenerate\nendmodule\n\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\n  input A, B, C, D, S, T;\n  output Y;\n  \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));\nendmodule\n\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\n  input A, B, C, D, E, F, G, H, S, T, U;\n  output Y;\n  \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));\nendmodule\n\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\n  input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\n  output Y;\n  \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));\nendmodule\n`endif\n\nmodule \\$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);\n  output O;\n  input I0, I1, I2, I3, S0, S1;\n  wire T0, T1;\n  parameter _TECHMAP_BITS_CONNMAP_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;\n  parameter _TECHMAP_CONSTMSK_S0_ = 0;\n  parameter _TECHMAP_CONSTVAL_S0_ = 0;\n  parameter _TECHMAP_CONSTMSK_S1_ = 0;\n  parameter _TECHMAP_CONSTVAL_S1_ = 0;\n  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)\n    assign T0 = I1;\n  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)\n    assign T0 = I0;\n  else\n    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));\n  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)\n    assign T1 = I3;\n  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)\n    assign T1 = I2;\n  else\n    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));\n  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)\n    assign O = T1;\n  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))\n    assign O = T0;\n  else\n    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));\nendmodule\n",
+            "cells_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *                2019  Eddie Hung    <eddie@fpgeh.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule \\$__SHREG_ (input C, input D, input E, output Q);\n  parameter DEPTH = 0;\n  parameter [DEPTH-1:0] INIT = 0;\n  parameter CLKPOL = 1;\n  parameter ENPOL = 2;\n\n  \\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));\nendmodule\n\nmodule \\$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);\n  parameter DEPTH = 0;\n  parameter [DEPTH-1:0] INIT = 0;\n  parameter CLKPOL = 1;\n  parameter ENPOL = 2;\n\n  // shregmap's INIT parameter shifts out LSB first;\n  // however Xilinx expects MSB first\n  function [DEPTH-1:0] brev;\n    input [DEPTH-1:0] din;\n    integer i;\n    begin\n      for (i = 0; i < DEPTH; i=i+1)\n        brev[i] = din[DEPTH-1-i];\n    end\n  endfunction\n  localparam [DEPTH-1:0] INIT_R = brev(INIT);\n\n  parameter _TECHMAP_CONSTMSK_L_ = 0;\n\n  wire CE;\n  generate\n    if (ENPOL == 0)\n      assign CE = ~E;\n    else if (ENPOL == 1)\n      assign CE = E;\n    else\n      assign CE = 1'b1;\n    if (DEPTH == 1) begin\n      if (CLKPOL)\n          FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));\n      else\n          FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));\n    end else\n    if (DEPTH <= 16) begin\n      SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));\n    end else\n    if (DEPTH > 17 && DEPTH <= 32) begin\n      SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));\n    end else\n    if (DEPTH > 33 && DEPTH <= 64) begin\n      wire T0, T1, T2;\n      SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T2;\n      else\n        MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));\n    end else\n    if (DEPTH > 65 && DEPTH <= 96) begin\n      wire T0, T1, T2, T3, T4, T5, T6;\n      SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));\n      SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T4;\n      else\n        \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));\n    end else\n    if (DEPTH > 97 && DEPTH < 128) begin\n      wire T0, T1, T2, T3, T4, T5, T6, T7, T8;\n      SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));\n      SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));\n      SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T6;\n      else\n        \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));\n    end\n    else if (DEPTH == 128) begin\n      wire T0, T1, T2, T3, T4, T5, T6;\n      SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));\n      SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));\n      SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));\n      SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T6;\n      else\n        \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));\n    end\n    // For fixed length, if just 1 over a convenient value, decompose\n    else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin\n      wire T;\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));\n      \\$__XILINX_SHREG_ #(.DEPTH(1),       .INIT(INIT[0]),         .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));\n    end\n    // For variable length, if just 1 over a convenient value, then bump up one more\n    else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));\n    else begin\n      localparam depth0 = 128;\n      localparam num_srl128 = DEPTH / depth0;\n      localparam depthN = DEPTH % depth0;\n      wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;\n      wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;\n      assign S[0] = D;\n      genvar i;\n      for (i = 0; i < num_srl128; i++)\n        \\$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(S[i]),          .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));\n\n      if (depthN > 0)\n        \\$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]),               .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));\n\n      if (&_TECHMAP_CONSTMSK_L_)\n        assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];\n      else\n        assign Q = T[L[DEPTH-1:$clog2(depth0)]];\n    end\n  endgenerate\nendmodule\n\n`ifdef MIN_MUX_INPUTS\nmodule \\$__XILINX_SHIFTX (A, B, Y);\n  parameter A_SIGNED = 0;\n  parameter B_SIGNED = 0;\n  parameter A_WIDTH = 1;\n  parameter B_WIDTH = 1;\n  parameter Y_WIDTH = 1;\n\n  (* force_downto *)\n  input [A_WIDTH-1:0] A;\n  (* force_downto *)\n  input [B_WIDTH-1:0] B;\n  (* force_downto *)\n  output [Y_WIDTH-1:0] Y;\n\n  parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;\n  parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;\n  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n  function integer A_WIDTH_trimmed;\n    input integer start;\n  begin\n    A_WIDTH_trimmed = start;\n    while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)\n      A_WIDTH_trimmed = A_WIDTH_trimmed - 1;\n  end\n  endfunction\n\n  generate\n    genvar i, j;\n    // Bit-blast\n    if (Y_WIDTH > 1) begin\n      for (i = 0; i < Y_WIDTH; i++)\n        \\$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));\n    end\n    // If the LSB of B is constant zero (and Y_WIDTH is 1) then\n    //   we can optimise by removing every other entry from A\n    //   and popping the constant zero from B\n    else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin\n      wire [(A_WIDTH+1)/2-1:0] A_i;\n      for (i = 0; i < (A_WIDTH+1)/2; i++)\n        assign A_i[i] = A[i*2];\n      \\$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));\n    end\n    // Trim off any leading 1'bx -es in A\n    else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin\n      localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);\n      if (A_WIDTH_new == 0)\n        assign Y = 1'bx;\n      else\n        \\$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));\n    end\n    else if (A_WIDTH < `MIN_MUX_INPUTS) begin\n      wire _TECHMAP_FAIL_ = 1;\n    end\n    else if (A_WIDTH == 2) begin\n      MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));\n    end\n    else if (A_WIDTH <= 4) begin\n      wire [4-1:0] Ax;\n      if (A_WIDTH == 4)\n        assign Ax = A;\n      else\n        // Rather than extend with 1'bx which gets flattened to 1'b0\n        // causing the \"don't care\" status to get lost, extend with\n        // the same driver of F7B.I0 so that we can optimise F7B away\n        // later\n        assign Ax = {A[1], A};\n      \\$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));\n    end\n    // Note that the following decompositions are 'backwards' in that\n    // the LSBs are placed on the hard resources, and the soft resources\n    // are used for MSBs.\n    // This has the effect of more effectively utilising the hard mux;\n    // take for example a 5:1 multiplexer, currently this would map as:\n    //\n    //     A[0] \\___  __                             A[0] \\__  __\n    //     A[4] /   \\|  \\       whereas the more     A[1] /  \\|  \\\n    //     A[1] _____|   |      obvious mapping      A[2] \\___|   |\n    //     A[2] _____|   |--    of MSBs to hard      A[3] /   |   |__\n    //     A[3]______|   |      resources would      A[4] ____|   |\n    //               |__/       lead to:             1'bx ____|   |\n    //                ||                                      |__/\n    //                ||                                       ||\n    //              B[1:0]                                   B[1:2]\n    //\n    // Expectation would be that the 'forward' mapping (right) is more\n    // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers\n    // on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs)\n    // but that the 'backwards' mapping (left) is more delay efficient\n    // since smaller LUTs are faster than wider ones.\n    else if (A_WIDTH <= 8) begin\n      wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};\n      wire T0 = B[2] ? Ax[4] : Ax[0];\n      wire T1 = B[2] ? Ax[5] : Ax[1];\n      wire T2 = B[2] ? Ax[6] : Ax[2];\n      wire T3 = B[2] ? Ax[7] : Ax[3];\n      \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));\n    end\n    else if (A_WIDTH <= 16) begin\n      wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A};\n      wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]\n                     : B[3] ? Ax[ 8] : Ax[0];\n      wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]\n                     : B[3] ? Ax[ 9] : Ax[1];\n      wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6]\n                     : B[3] ? Ax[10] : Ax[2];\n      wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7]\n                     : B[3] ? Ax[11] : Ax[3];\n      \\$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));\n    end\n    else begin\n      localparam num_mux16 = (A_WIDTH+15) / 16;\n      localparam clog2_num_mux16 = $clog2(num_mux16);\n      wire [num_mux16-1:0] T;\n      wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};\n      for (i = 0; i < num_mux16; i++)\n        \\$__XILINX_SHIFTX  #(\n          .A_SIGNED(A_SIGNED),\n          .B_SIGNED(B_SIGNED),\n          .A_WIDTH(16),\n          .B_WIDTH(4),\n          .Y_WIDTH(Y_WIDTH)\n        ) fpga_mux (\n          .A(Ax[i*16+:16]),\n          .B(B[3:0]),\n          .Y(T[i])\n        );\n      \\$__XILINX_SHIFTX  #(\n          .A_SIGNED(A_SIGNED),\n          .B_SIGNED(B_SIGNED),\n          .A_WIDTH(num_mux16),\n          .B_WIDTH(clog2_num_mux16),\n          .Y_WIDTH(Y_WIDTH)\n      ) _TECHMAP_REPLACE_ (\n          .A(T),\n          .B(B[B_WIDTH-1-:clog2_num_mux16]),\n          .Y(Y));\n    end\n  endgenerate\nendmodule\n\n(* techmap_celltype = \"$__XILINX_SHIFTX\" *)\nmodule _90__XILINX_SHIFTX (A, B, Y);\n  parameter A_SIGNED = 0;\n  parameter B_SIGNED = 0;\n  parameter A_WIDTH = 1;\n  parameter B_WIDTH = 1;\n  parameter Y_WIDTH = 1;\n\n  (* force_downto *)\n  input [A_WIDTH-1:0] A;\n  (* force_downto *)\n  input [B_WIDTH-1:0] B;\n  (* force_downto *)\n  output [Y_WIDTH-1:0] Y;\n\n  \\$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));\nendmodule\n\nmodule \\$_MUX_ (A, B, S, Y);\n  input A, B, S;\n  output Y;\n  generate\n    if (`MIN_MUX_INPUTS == 2)\n      \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));\n    else\n      wire _TECHMAP_FAIL_ = 1;\n  endgenerate\nendmodule\n\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\n  input A, B, C, D, S, T;\n  output Y;\n  \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));\nendmodule\n\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\n  input A, B, C, D, E, F, G, H, S, T, U;\n  output Y;\n  \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));\nendmodule\n\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\n  input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\n  output Y;\n  \\$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));\nendmodule\n`endif\n\nmodule \\$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);\n  output O;\n  input I0, I1, I2, I3, S0, S1;\n  wire T0, T1;\n  parameter _TECHMAP_BITS_CONNMAP_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;\n  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;\n  parameter _TECHMAP_CONSTMSK_S0_ = 0;\n  parameter _TECHMAP_CONSTVAL_S0_ = 0;\n  parameter _TECHMAP_CONSTMSK_S1_ = 0;\n  parameter _TECHMAP_CONSTVAL_S1_ = 0;\n  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)\n    assign T0 = I1;\n  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)\n    assign T0 = I0;\n  else\n    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));\n  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)\n    assign T1 = I3;\n  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)\n    assign T1 = I2;\n  else\n    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));\n  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)\n    assign O = T1;\n  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))\n    assign O = T0;\n  else\n    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));\nendmodule\n",
             "cells_sim.v": new URL("./share/xilinx/cells_sim.v", import.meta.url),
             "cells_xtra.v": new URL("./share/xilinx/cells_xtra.v", import.meta.url),
             "ff_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n`ifndef _NO_FFS\n\n// Async reset, enable.\n\nmodule  \\$_DFFE_NP0P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_DFFE_PP0P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\nmodule  \\$_DFFE_NP1P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_DFFE_PP1P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// Async set and reset, enable.\n\nmodule  \\$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDCPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// Sync reset, enable.\n\nmodule  \\$_SDFFE_NP0P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_SDFFE_PP0P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\nmodule  \\$_SDFFE_NP1P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_SDFFE_PP1P_ (input D, C, E, R, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// Latches with reset.\n\nmodule  \\$_DLATCH_NP0_ (input E, R, D, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_DLATCH_PP0_ (input E, R, D, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  LDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_DLATCH_NP1_ (input E, R, D, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_DLATCH_PP1_ (input E, R, D, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  LDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// Latches with set and reset.\n\nmodule  \\$_DLATCH_NPP_ (input E, S, R, D, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\nmodule  \\$_DLATCH_PPP_ (input E, S, R, D, output Q);\n  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n  LDCPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));\n  wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n`endif\n\n",