npm - @yowasp/yosys - Versions diffs - 0.50.857 → 0.51.871 - Mend

@yowasp/yosys 0.50.857 → 0.51.871

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package/gen/resources-yosys.js CHANGED Viewed

@@ -180,7 +180,7 @@ export const filesystem = {
                 "modtools.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MODTOOLS_H\n#define MODTOOLS_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ModIndex : public RTLIL::Monitor\n{\n\tstruct PortInfo {\n\t\tRTLIL::Cell* cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tPortInfo() : cell(), port(), offset() { }\n\t\tPortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }\n\n\t\tbool operator<(const PortInfo &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (offset != other.offset)\n\t\t\t\treturn offset < other.offset;\n\t\t\treturn port < other.port;\n\t\t}\n\n\t\tbool operator==(const PortInfo &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tstruct SigBitInfo\n\t{\n\t\tbool is_input, is_output;\n\t\tpool<PortInfo> ports;\n\n\t\tSigBitInfo() : is_input(false), is_output(false) { }\n\n\t\tbool operator==(const SigBitInfo &other) const {\n\t\t\treturn is_input == other.is_input && is_output == other.is_output && ports == other.ports;\n\t\t}\n\n\t\tvoid merge(const SigBitInfo &other)\n\t\t{\n\t\t\tis_input = is_input || other.is_input;\n\t\t\tis_output = is_output || other.is_output;\n\t\t\tports.insert(other.ports.begin(), other.ports.end());\n\t\t}\n\t};\n\n\tSigMap sigmap;\n\tRTLIL::Module *module;\n\tstd::map<RTLIL::SigBit, SigBitInfo> database;\n\tint auto_reload_counter;\n\tbool auto_reload_module;\n\n\tvoid port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.insert(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tvoid port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.erase(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tconst SigBitInfo &info(RTLIL::SigBit bit)\n\t{\n\t\treturn database[sigmap(bit)];\n\t}\n\n\tvoid reload_module(bool reset_sigmap = true)\n\t{\n\t\tif (reset_sigmap) {\n\t\t\tsigmap.clear();\n\t\t\tsigmap.set(module);\n\t\t}\n\n\t\tdatabase.clear();\n\t\tfor (auto wire : module->wires())\n\t\t\tif (wire->port_input || wire->port_output)\n\t\t\t\tfor (int i = 0; i < GetSize(wire); i++) {\n\t\t\t\t\tRTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));\n\t\t\t\t\tif (bit.wire && wire->port_input)\n\t\t\t\t\t\tdatabase[bit].is_input = true;\n\t\t\t\t\tif (bit.wire && wire->port_output)\n\t\t\t\t\t\tdatabase[bit].is_output = true;\n\t\t\t\t}\n\t\tfor (auto cell : module->cells())\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tport_add(cell, conn.first, conn.second);\n\n\t\tif (auto_reload_module) {\n\t\t\tif (++auto_reload_counter > 2)\n\t\t\t\tlog_warning(\"Auto-reload in ModIndex -- possible performance bug!\\n\");\n\t\t\tauto_reload_module = false;\n\t\t}\n\t}\n\n\tvoid check()\n\t{\n#ifndef NDEBUG\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (auto it : database)\n\t\t\tlog_assert(it.first == sigmap(it.first));\n\n\t\tauto database_bak = std::move(database);\n\t\treload_module(false);\n\n\t\tif (!(database == database_bak))\n\t\t{\n\t\t\tfor (auto &it : database_bak)\n\t\t\t\tif (!database.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database_bak, not database: %s\\n\", log_signal(it.first));\n\n\t\t\tfor (auto &it : database)\n\t\t\t\tif (!database_bak.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database, not database_bak: %s\\n\", log_signal(it.first));\n\t\t\t\telse if (!(it.second == database_bak.at(it.first)))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Different content for database[%s].\\n\", log_signal(it.first));\n\n\t\t\tlog_assert(database == database_bak);\n\t\t}\n#endif\n\t}\n\n\tvoid notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override\n\t{\n\t\tlog_assert(module == cell->module);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tport_del(cell, port, old_sig);\n\t\tport_add(cell, port, sig);\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override\n\t{\n\t\tlog_assert(module == mod);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (int i = 0; i < GetSize(sigsig.first); i++)\n\t\t{\n\t\t\tRTLIL::SigBit lhs = sigmap(sigsig.first[i]);\n\t\t\tRTLIL::SigBit rhs = sigmap(sigsig.second[i]);\n\t\t\tbool has_lhs = database.count(lhs) != 0;\n\t\t\tbool has_rhs = database.count(rhs) != 0;\n\n\t\t\tif (!has_lhs && !has_rhs) {\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t} else\n\t\t\tif (!has_rhs) {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\tlhs = sigmap(lhs);\n\t\t\t\tif (lhs.wire)\n\t\t\t\t\tdatabase[lhs] = new_info;\n\t\t\t} else\n\t\t\tif (!has_lhs) {\n\t\t\t\tSigBitInfo new_info = database.at(rhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t} else {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tnew_info.merge(database.at(rhs));\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tvoid notify_blackout(RTLIL::Module *mod) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)\n\t{\n\t\tauto_reload_counter = 0;\n\t\tauto_reload_module = true;\n\t\tmodule->monitors.insert(this);\n\t}\n\n\t~ModIndex()\n\t{\n\t\tmodule->monitors.erase(this);\n\t}\n\n\tSigBitInfo *query(RTLIL::SigBit bit)\n\t{\n\t\tif (auto_reload_module)\n\t\t\treload_module();\n\n\t\tauto it = database.find(sigmap(bit));\n\t\tif (it == database.end())\n\t\t\treturn nullptr;\n\t\telse\n\t\t\treturn &it->second;\n\t}\n\n\tbool query_is_input(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_input;\n\t}\n\n\tbool query_is_output(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_output;\n\t}\n\n\tpool<PortInfo> &query_ports(RTLIL::SigBit bit)\n\t{\n\t\tstatic pool<PortInfo> empty_result_set;\n\t\tSigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn empty_result_set;\n\t\treturn info->ports;\n\t}\n\n\tvoid dump_db()\n\t{\n\t\tlog(\"--- ModIndex Dump ---\\n\");\n\n\t\tif (auto_reload_module) {\n\t\t\tlog(\"AUTO-RELOAD\\n\");\n\t\t\treload_module();\n\t\t}\n\n\t\tfor (auto &it : database) {\n\t\t\tlog(\"BIT %s:\\n\", log_signal(it.first));\n\t\t\tif (it.second.is_input)\n\t\t\t\tlog(\"  PRIMARY INPUT\\n\");\n\t\t\tif (it.second.is_output)\n\t\t\t\tlog(\"  PRIMARY OUTPUT\\n\");\n\t\t\tfor (auto &port : it.second.ports)\n\t\t\t\tlog(\"  PORT: %s.%s[%d] (%s)\\n\", log_id(port.cell),\n\t\t\t\t\t\tlog_id(port.port), port.offset, log_id(port.cell->type));\n\t\t}\n\t}\n};\n\nstruct ModWalker\n{\n\tstruct PortBit\n\t{\n\t\tRTLIL::Cell *cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\t\tPortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}\n\n\t\tbool operator<(const PortBit &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (port != other.port)\n\t\t\t\treturn port < other.port;\n\t\t\treturn offset < other.offset;\n\t\t}\n\n\t\tbool operator==(const PortBit &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\t\th.eat(cell->name);\n\t\t\th.eat(port);\n\t\t\th.eat(offset);\n\t\t\treturn h;\n\t\t}\n\t};\n\n\tRTLIL::Design *design;\n\tRTLIL::Module *module;\n\n\tCellTypes ct;\n\tSigMap sigmap;\n\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_drivers;\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_consumers;\n\tpool<RTLIL::SigBit> signal_inputs, signal_outputs;\n\n\tdict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;\n\n\tvoid add_wire(RTLIL::Wire *wire)\n\t{\n\t\tif (wire->port_input) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_inputs.insert(bit);\n\t\t}\n\n\t\tif (wire->port_output) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_outputs.insert(bit);\n\t\t}\n\t}\n\n\tvoid add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)\n\t{\n\t\tfor (int i = 0; i < int(bits.size()); i++)\n\t\t\tif (bits[i].wire != NULL) {\n\t\t\t\tPortBit pbit {cell, port, i};\n\t\t\t\tif (is_output) {\n\t\t\t\t\tsignal_drivers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_outputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t\tif (is_input) {\n\t\t\t\t\tsignal_consumers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_inputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\tvoid add_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (ct.cell_known(cell->type)) {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second),\n\t\t\t\t\t\tct.cell_output(cell->type, conn.first),\n\t\t\t\t\t\tct.cell_input(cell->type, conn.first));\n\t\t} else {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second), true, true);\n\t\t}\n\t}\n\n\tModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)\n\t{\n\t\tct.setup(design);\n\t\tif (module)\n\t\t\tsetup(module);\n\t}\n\n\tvoid setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)\n\t{\n\t\tthis->module = module;\n\n\t\tsigmap.set(module);\n\n\t\tsignal_drivers.clear();\n\t\tsignal_consumers.clear();\n\t\tsignal_inputs.clear();\n\t\tsignal_outputs.clear();\n\t\tcell_inputs.clear();\n\t\tcell_outputs.clear();\n\n\t\tfor (auto &it : module->wires_)\n\t\t\tadd_wire(it.second);\n\t\tfor (auto &it : module->cells_)\n\t\t\tif (filter_ct == NULL || filter_ct->cell_known(it.second->type))\n\t\t\t\tadd_cell(it.second);\n\t}\n\n\t// get_* methods -- single RTLIL::SigBit\n\n\tinline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_drivers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_consumers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_inputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_outputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- container of RTLIL::SigBit's (always by reference)\n\n\ttemplate<typename T>\n\tinline bool get_drivers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_drivers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_consumers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_consumers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_inputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_outputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- call by RTLIL::SigSpec (always by value)\n\n\tbool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_drivers(result, bits);\n\t}\n\n\tbool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_consumers(result, bits);\n\t}\n\n\tbool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_inputs(result, bits);\n\t}\n\n\tbool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_outputs(result, bits);\n\t}\n\n\t// has_* methods -- call by reference\n\n\ttemplate<typename T>\n\tinline bool has_drivers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_consumers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_inputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_outputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n\n\t// has_* methods -- call by value\n\n\tinline bool has_drivers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\tinline bool has_consumers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\tinline bool has_inputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\tinline bool has_outputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "qcsat.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2021  Marcelina Kościelnicka <mwk@0x04.net>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef QCSAT_H\n#define QCSAT_H\n\n#include \"kernel/satgen.h\"\n#include \"kernel/modtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// This is a helper class meant for easy construction of quick SAT queries\n// to a combinatorial input cone of some set of signals, meant for SAT-based\n// optimizations.  Various knobs are provided to set just how much of the\n// cone should be included in the model — since this class is meant for\n// optimization, it should not be a correctness problem when some cells are\n// skipped and the solver spuriously returns SAT with a solution that\n// cannot exist in reality due to skipped constraints (ie. only UNSAT results\n// from this class should be considered binding).\nstruct QuickConeSat {\n\tModWalker &modwalker;\n\tezSatPtr ez;\n\tSatGen satgen;\n\n\t// The effort level knobs.\n\n\t// The maximum \"complexity level\" of cells that will be imported.\n\t// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa\n\t// - 2: addition, subtraction, greater/less than comparisons, lcu\n\t// - 3: shifts\n\t// - 4: multiplication, division, power\n\tint max_cell_complexity = 2;\n\t// The maximum number of cells to import, or 0 for no limit.\n\tint max_cell_count = 0;\n\t// If non-0, skip importing cells with more than this number of output bits.\n\tint max_cell_outs = 0;\n\n\t// Internal state.\n\tpool<RTLIL::Cell*> imported_cells;\n\tpool<RTLIL::Wire*> imported_onehot;\n\tpool<RTLIL::SigBit> bits_queue;\n\n\tQuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}\n\n\t// Imports a signal into the SAT solver, queues its input cone to be\n\t// imported in the next prepare() call.\n\tstd::vector<int> importSig(SigSpec sig);\n\tint importSigBit(SigBit bit);\n\n\t// Imports the input cones of all previously importSig'd signals into\n\t// the SAT solver.\n\tvoid prepare();\n\n\t// Returns the \"complexity level\" of a given cell.\n\tstatic int cell_complexity(RTLIL::Cell *cell);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "register.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename,  std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
-                "rtlil.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5  // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7  // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE   = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2,  // only used for parameters\n\t\tCONST_FLAG_REAL   = 4   // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic dict<char*, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic std::vector<int> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t\tif (idx) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\t}\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tif (!p[0])\n\t\t\treturn 0;\n\n\t\tauto it = global_id_index_.find((char*)p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tlog_assert(p[1] != 0);\n\t\tfor (const char *c = p; *c; c++)\n\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tif (global_id_storage_.empty()) {\n\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t}\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (!destruct_guard_ok || !idx)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tlog_assert(refcount == 0);\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn c_str()[0] == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(Args... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\nnamespace RTLIL {\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx      (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tmutable backing_tag tag;\n\tunion {\n\t\tmutable bitvectype bits_;\n\t\tmutable std::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits() const;\n\tstd::string& get_str() const;\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tstd::vector<RTLIL::State>& bits();\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\tvoid bitvectorize() const;\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const& parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator& operator++(int) { ++idx; return *this; }\n\t\tconst_iterator& operator--(int) { --idx; return *this; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tbits().resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbitvectype& bv = bits();\n\t\tbv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(size());\n\t\tfor (auto b : *this)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset;        // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig>   connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const    { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
+                "rtlil.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5  // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7  // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE   = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2,  // only used for parameters\n\t\tCONST_FLAG_REAL   = 4   // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\tstruct IdString;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n};\n\nstruct RTLIL::IdString\n{\n\t#undef YOSYS_XTRACE_GET_PUT\n\t#undef YOSYS_SORT_ID_FREE_LIST\n\t#undef YOSYS_USE_STICKY_IDS\n\t#undef YOSYS_NO_IDS_REFCNT\n\n\t// the global id string cache\n\n\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\tstatic struct destruct_guard_t {\n\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t} destruct_guard;\n\n\tstatic std::vector<char*> global_id_storage_;\n\tstatic dict<char*, int> global_id_index_;\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic std::vector<int> global_refcount_storage_;\n\tstatic std::vector<int> global_free_idx_list_;\n#endif\n\n#ifdef YOSYS_USE_STICKY_IDS\n\tstatic int last_created_idx_ptr_;\n\tstatic int last_created_idx_[8];\n#endif\n\n\tstatic inline void xtrace_db_dump()\n\t{\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t{\n\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\telse\n\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\t}\n\n\tstatic inline void checkpoint()\n\t{\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tlast_created_idx_ptr_ = 0;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tif (last_created_idx_[i])\n\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\tlast_created_idx_[i] = 0;\n\t\t}\n\t#endif\n\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t#endif\n\t}\n\n\tstatic inline int get_reference(int idx)\n\t{\n\t\tif (idx) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_[idx]++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\t\t}\n\t\treturn idx;\n\t}\n\n\tstatic int get_reference(const char *p)\n\t{\n\t\tlog_assert(destruct_guard_ok);\n\n\t\tif (!p[0])\n\t\t\treturn 0;\n\n\t\tauto it = global_id_index_.find((char*)p);\n\t\tif (it != global_id_index_.end()) {\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t#endif\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t#endif\n\t\t\treturn it->second;\n\t\t}\n\n\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\tlog_assert(p[1] != 0);\n\t\tfor (const char *c = p; *c; c++)\n\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tif (global_free_idx_list_.empty()) {\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t}\n\n\t\tint idx = global_free_idx_list_.back();\n\t\tglobal_free_idx_list_.pop_back();\n\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\tglobal_refcount_storage_.at(idx)++;\n\t#else\n\t\tif (global_id_storage_.empty()) {\n\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t}\n\t\tint idx = global_id_storage_.size();\n\t\tglobal_id_storage_.push_back(strdup(p));\n\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t#endif\n\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace)\n\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t// Avoid Create->Delete->Create pattern\n\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t#endif\n\n\t\treturn idx;\n\t}\n\n#ifndef YOSYS_NO_IDS_REFCNT\n\tstatic inline void put_reference(int idx)\n\t{\n\t\t// put_reference() may be called from destructors after the destructor of\n\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\tif (!destruct_guard_ok || !idx)\n\t\t\treturn;\n\n\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t}\n\t#endif\n\n\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\tif (--refcount > 0)\n\t\t\treturn;\n\n\t\tlog_assert(refcount == 0);\n\t\tfree_reference(idx);\n\t}\n\tstatic inline void free_reference(int idx)\n\t{\n\t\tif (yosys_xtrace) {\n\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t}\n\n\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\tfree(global_id_storage_.at(idx));\n\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\tglobal_free_idx_list_.push_back(idx);\n\t}\n#else\n\tstatic inline void put_reference(int) { }\n#endif\n\n\t// the actual IdString object is just is a single int\n\n\tint index_;\n\n\tinline IdString() : index_(0) { }\n\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\tinline ~IdString() { put_reference(index_); }\n\n\tinline void operator=(const IdString &rhs) {\n\t\tput_reference(index_);\n\t\tindex_ = get_reference(rhs.index_);\n\t}\n\n\tinline void operator=(const char *rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline void operator=(const std::string &rhs) {\n\t\tIdString id(rhs);\n\t\t*this = id;\n\t}\n\n\tinline const char *c_str() const {\n\t\treturn global_id_storage_.at(index_);\n\t}\n\n\tinline std::string str() const {\n\t\treturn std::string(global_id_storage_.at(index_));\n\t}\n\n\tinline bool operator<(const IdString &rhs) const {\n\t\treturn index_ < rhs.index_;\n\t}\n\n\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\tchar operator[](size_t i) const {\n\t\t\t\t\tconst char *p = c_str();\n#ifndef NDEBUG\n\t\tfor (; i != 0; i--, p++)\n\t\t\tlog_assert(*p != 0);\n\t\treturn *p;\n#else\n\t\treturn *(p + i);\n#endif\n\t}\n\n\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\treturn std::string(c_str() + pos);\n\t\telse\n\t\t\treturn std::string(c_str() + pos, len);\n\t}\n\n\tint compare(size_t pos, size_t len, const char* s) const {\n\t\treturn strncmp(c_str()+pos, s, len);\n\t}\n\n\tbool begins_with(const char* prefix) const {\n\t\tsize_t len = strlen(prefix);\n\t\tif (size() < len) return false;\n\t\treturn compare(0, len, prefix) == 0;\n\t}\n\n\tbool ends_with(const char* suffix) const {\n\t\tsize_t len = strlen(suffix);\n\t\tif (size() < len) return false;\n\t\treturn compare(size()-len, len, suffix) == 0;\n\t}\n\n\tbool contains(const char* str) const {\n\t\treturn strstr(c_str(), str);\n\t}\n\n\tsize_t size() const {\n\t\treturn strlen(c_str());\n\t}\n\n\tbool empty() const {\n\t\treturn c_str()[0] == 0;\n\t}\n\n\tvoid clear() {\n\t\t*this = IdString();\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { return hash_ops<int>::hash_into(index_, h); }\n\n\t[[nodiscard]] Hasher hash_top() const {\n\t\tHasher h;\n\t\th.force((Hasher::hash_t) index_);\n\t\treturn h;\n\t}\n\n\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t// set has an influence on the algorithm.\n\n\ttemplate<typename T> struct compare_ptr_by_name {\n\t\tbool operator()(const T *a, const T *b) const {\n\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t}\n\t};\n\n\t// often one needs to check if a given IdString is part of a list (for example a list\n\t// of cell types). the following functions helps with that.\n\ttemplate<typename... Args>\n\tbool in(Args... args) const {\n\t\treturn (... || in(args));\n\t}\n\n\tbool in(const IdString &rhs) const { return *this == rhs; }\n\tbool in(const char *rhs) const { return *this == rhs; }\n\tbool in(const std::string &rhs) const { return *this == rhs; }\n\tinline bool in(const pool<IdString> &rhs) const;\n\tinline bool in(const pool<IdString> &&rhs) const;\n\n\tbool isPublic() const { return begins_with(\"\\\\\"); }\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::IdString> {\n\t\tstatic inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::IdString id) {\n\t\t\treturn id.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString id, Hasher h) {\n\t\t\treturn id.hash_into(h);\n\t\t}\n\t};\n};\n\n/**\n * How to not use these methods:\n * 1. if(celltype.in({...})) -> if(celltype.in(...))\n * 2. pool<IdString> p; ... a.in(p) -> (bool)p.count(a)\n */\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n[[deprecated]]\ninline bool RTLIL::IdString::in(const pool<IdString> &&rhs) const { return rhs.count(*this) != 0; }\n\nnamespace RTLIL {\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor  (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and   (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx      (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt          (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor    (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux        (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx       (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux       (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tmutable backing_tag tag;\n\tunion {\n\t\tmutable bitvectype bits_;\n\t\tmutable std::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits() const;\n\tstd::string& get_str() const;\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tstd::vector<RTLIL::State>& bits();\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\tvoid bitvectorize() const;\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const& parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator& operator++(int) { ++idx; return *this; }\n\t\tconst_iterator& operator--(int) { --idx; return *this; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tbits().resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbitvectype& bv = bits();\n\t\tbv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());\n\t}\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const {\n\t\th.eat(size());\n\t\tfor (auto b : *this)\n\t\t\th.eat(b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset;        // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const;\n\t[[nodiscard]] Hasher hash_top() const;\n};\n\nnamespace hashlib {\n\ttemplate <>\n\tstruct hash_ops<RTLIL::SigBit> {\n\t\tstatic inline bool cmp(const RTLIL::SigBit &a, const RTLIL::SigBit &b) {\n\t\t\treturn a == b;\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash(const RTLIL::SigBit sb) {\n\t\t\treturn sb.hash_top();\n\t\t}\n\t\t[[nodiscard]] static inline Hasher hash_into(const RTLIL::SigBit sb, Hasher h) {\n\t\t\treturn sb.hash_into(h);\n\t\t}\n\t};\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tHasher::hash_t hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { if (!hash_) updhash(); h.eat(hash_); return h; }\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig>   connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf    (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d,   const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst,  const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate     (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate    (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate   (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate  (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr    (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr   (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux     (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux      (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate     (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate  (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate    (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate   (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell*   addSetTag       (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag          (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell*   addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const    { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n\tint from_hdl_index(int hdl_index) {\n\t\tint zero_index = hdl_index - start_offset;\n\t\tint rtlil_index = upto ? width - 1 - zero_index : zero_index;\n\t\treturn rtlil_index >= 0 && rtlil_index < width ? rtlil_index : INT_MIN;\n\t}\n\n\tint to_hdl_index(int rtlil_index) {\n\t\tif (rtlil_index < 0 || rtlil_index >= width)\n\t\t\treturn INT_MIN;\n\t\tint zero_index = upto ? width - 1 - rtlil_index : rtlil_index;\n\t\treturn zero_index + start_offset;\n\t}\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tHasher::hash_t hashidx_;\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline Hasher RTLIL::SigBit::hash_into(Hasher h) const {\n\tif (wire) {\n\t\th.eat(offset);\n\t\th.eat(wire->name);\n\t\treturn h;\n\t}\n\th.eat(data);\n\treturn h;\n}\n\n\ninline Hasher RTLIL::SigBit::hash_top() const {\n\tHasher h;\n\tif (wire) {\n\t\th.force(hashlib::legacy::djb2_add(wire->name.index_, offset));\n\t\treturn h;\n\t}\n\th.force(data);\n\treturn h;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "satgen.h": "/* -*- c++ -*-\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tSigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string name = pf + (bit.wire->width == 1 ? stringf(\"%s\", log_id(bit.wire)) : stringf(\"%s [%d]\", log_id(bit.wire->name), bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "scopeinfo.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2024  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\t[[nodiscard]] Hasher hash_into(Hasher h) const\n\t\t{\n\t\t\th.eat(scope_name);\n\t\t\th.eat(target);\n\t\t\treturn h;\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\t[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(ptr); return h; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty() && object->name.isPublic())\n\t\tpath.push_back(object->name);\n\tif (!path.empty() && !(object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\"))) {\n\t\tpath.pop_back();\n\t\tpath.push_back(object->name);\n\t}\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic() || object->name.begins_with(\"$paramod\") || object->name.begins_with(\"$abstract\")) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else if (object->has_attribute(ID::hdlname)) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
                 "sexpr.h": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2024  Emily Schmidt <emily@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SEXPR_H\n#define SEXPR_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nclass SExpr {\npublic:\n\tstd::variant<std::vector<SExpr>, std::string> _v;\npublic:\n\tSExpr(std::string a) : _v(std::move(a)) {}\n    SExpr(const char *a) : _v(a) {}\n    // FIXME: should maybe be defined for all integral types\n\tSExpr(int n) : _v(std::to_string(n)) {}\n\tSExpr(std::vector<SExpr> const &l) : _v(l) {}\n\tSExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}\n    // It would be nicer to have an std::initializer_list constructor,\n    // but that causes confusing issues with overload resolution sometimes.\n    template<typename... Args> static SExpr list(Args&&... args) {\n\t    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n    }\n    bool is_atom() const { return std::holds_alternative<std::string>(_v); }\n    std::string const &atom() const { return std::get<std::string>(_v); }\n    bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }\n    std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }\n\tstd::string to_string() const;\n};\n\nstd::ostream &operator<<(std::ostream &os, SExpr const &sexpr);\n\nnamespace SExprUtil {\n    // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list`\n    template<typename... Args> SExpr list(Args&&... args) {\n\t    return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n    }\n}\n\n// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout.\nclass SExprWriter {\n    std::ostream &os;\n    int _max_line_width;\n    int _indent = 0;\n    int _pos = 0;\n    // If _pending_nl is set, print a newline before the next character.\n    // This lets us \"undo\" the last newline so we can put\n    // closing parentheses or a hanging comment on the same line.\n    bool _pending_nl = false;\n    // Unclosed parentheses (boolean stored is indent_rest)\n\tvector<bool> _unclosed;\n    // Used only for push() and pop() (stores _unclosed.size())\n\tvector<size_t> _unclosed_stack;\n\tvoid nl_if_pending();\n    void puts(std::string_view s);\n    int check_fit(SExpr const &sexpr, int space);\n    void print(SExpr const &sexpr, bool close = true, bool indent_rest = true);\npublic:\n    SExprWriter(std::ostream &os, int max_line_width = 80)\n        : os(os)\n        , _max_line_width(max_line_width)\n    {}\n    // Print an s-expr.\n    SExprWriter &operator <<(SExpr const &sexpr) {\n        print(sexpr);\n        _pending_nl = true;\n        return *this;\n    }\n    // Print an s-expr (which must be a list), but leave room for extra elements\n    // which may be printed using either << or further calls to open.\n    // If indent_rest = false, the remaining elements are not intended\n    // (for avoiding unreasonable indentation on deeply nested structures).\n    void open(SExpr const &sexpr, bool indent_rest = true) {\n        log_assert(sexpr.is_list());\n        print(sexpr, false, indent_rest);\n    }\n    // Close the s-expr opened with the last call to open\n    // (if an argument is given, close that many s-exprs).\n    void close(size_t n = 1);\n    // push() remembers how many s-exprs are currently open\n\tvoid push() {\n\t\t_unclosed_stack.push_back(_unclosed.size());\n\t}\n    // pop() closes all s-expr opened since the corresponding call to push()\n\tvoid pop() {\n\t\tauto t = _unclosed_stack.back();\n\t\tlog_assert(_unclosed.size() >= t);\n\t\tclose(_unclosed.size() - t);\n\t\t_unclosed_stack.pop_back();\n\t}\n    // Print a comment.\n    // If hanging = true, append it to the end of the last printed s-expr.\n\tvoid comment(std::string const &str, bool hanging = false);\n    // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses.\n    void flush() {\n        nl_if_pending();\n    }\n    // Destructor closes any unclosed parentheses and flushes.\n    ~SExprWriter();\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
@@ -213,7 +213,7 @@ export const filesystem = {
             "common": {
                 "altpll_bb.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n/* No clearbox model */\n`ifdef NO_CLEARBOX\n(* blackbox *)\nmodule altpll\n  ( inclk,\n    fbin,\n    pllena,\n    clkswitch,\n    areset,\n    pfdena,\n    clkena,\n    extclkena,\n    scanclk,\n    scanaclr,\n    scanclkena,\n    scanread,\n    scanwrite,\n    scandata,\n    phasecounterselect,\n    phaseupdown,\n    phasestep,\n    configupdate,\n    fbmimicbidir,\n    clk,\n    extclk,\n    clkbad,\n    enable0,\n    enable1,\n    activeclock,\n    clkloss,\n    locked,\n    scandataout,\n    scandone,\n    sclkout0,\n    sclkout1,\n    phasedone,\n    vcooverrange,\n    vcounderrange,\n    fbout,\n    fref,\n    icdrclk,\n    c0,\n    c1,\n    c2,\n    c3,\n    c4);\n\n   parameter   intended_device_family    = \"MAX 10\";\n   parameter   operation_mode            = \"NORMAL\";\n   parameter   pll_type                  = \"AUTO\";\n   parameter   qualify_conf_done         = \"OFF\";\n   parameter   compensate_clock          = \"CLK0\";\n   parameter   scan_chain                = \"LONG\";\n   parameter   primary_clock             = \"inclk0\";\n   parameter   inclk0_input_frequency    = 1000;\n   parameter   inclk1_input_frequency    = 0;\n   parameter   gate_lock_signal          = \"NO\";\n   parameter   gate_lock_counter         = 0;\n   parameter   lock_high                 = 1;\n   parameter   lock_low                  = 0;\n   parameter   valid_lock_multiplier     = 1;\n   parameter   invalid_lock_multiplier   = 5;\n   parameter   switch_over_type          = \"AUTO\";\n   parameter   switch_over_on_lossclk    = \"OFF\" ;\n   parameter   switch_over_on_gated_lock = \"OFF\" ;\n   parameter   enable_switch_over_counter = \"OFF\";\n   parameter   switch_over_counter       = 0;\n   parameter   feedback_source           = \"EXTCLK0\" ;\n   parameter   bandwidth                 = 0;\n   parameter   bandwidth_type            = \"UNUSED\";\n   parameter   lpm_hint                  = \"UNUSED\";\n   parameter   spread_frequency          = 0;\n   parameter   down_spread               = \"0.0\";\n   parameter   self_reset_on_gated_loss_lock = \"OFF\";\n   parameter   self_reset_on_loss_lock = \"OFF\";\n   parameter   lock_window_ui           = \"0.05\";\n   parameter   width_clock              = 6;\n   parameter   width_phasecounterselect = 4;\n   parameter   charge_pump_current_bits = 9999;\n   parameter   loop_filter_c_bits = 9999;\n   parameter   loop_filter_r_bits = 9999;\n   parameter   scan_chain_mif_file = \"UNUSED\";\n   parameter   clk9_multiply_by        = 1;\n   parameter   clk8_multiply_by        = 1;\n   parameter   clk7_multiply_by        = 1;\n   parameter   clk6_multiply_by        = 1;\n   parameter   clk5_multiply_by        = 1;\n   parameter   clk4_multiply_by        = 1;\n   parameter   clk3_multiply_by        = 1;\n   parameter   clk2_multiply_by        = 1;\n   parameter   clk1_multiply_by        = 1;\n   parameter   clk0_multiply_by        = 1;\n   parameter   clk9_divide_by          = 1;\n   parameter   clk8_divide_by          = 1;\n   parameter   clk7_divide_by          = 1;\n   parameter   clk6_divide_by          = 1;\n   parameter   clk5_divide_by          = 1;\n   parameter   clk4_divide_by          = 1;\n   parameter   clk3_divide_by          = 1;\n   parameter   clk2_divide_by          = 1;\n   parameter   clk1_divide_by          = 1;\n   parameter   clk0_divide_by          = 1;\n   parameter   clk9_phase_shift        = \"0\";\n   parameter   clk8_phase_shift        = \"0\";\n   parameter   clk7_phase_shift        = \"0\";\n   parameter   clk6_phase_shift        = \"0\";\n   parameter   clk5_phase_shift        = \"0\";\n   parameter   clk4_phase_shift        = \"0\";\n   parameter   clk3_phase_shift        = \"0\";\n   parameter   clk2_phase_shift        = \"0\";\n   parameter   clk1_phase_shift        = \"0\";\n   parameter   clk0_phase_shift        = \"0\";\n\n   parameter   clk9_duty_cycle         = 50;\n   parameter   clk8_duty_cycle         = 50;\n   parameter   clk7_duty_cycle         = 50;\n   parameter   clk6_duty_cycle         = 50;\n   parameter   clk5_duty_cycle         = 50;\n   parameter   clk4_duty_cycle         = 50;\n   parameter   clk3_duty_cycle         = 50;\n   parameter   clk2_duty_cycle         = 50;\n   parameter   clk1_duty_cycle         = 50;\n   parameter   clk0_duty_cycle         = 50;\n\n   parameter   clk9_use_even_counter_mode    = \"OFF\";\n   parameter   clk8_use_even_counter_mode    = \"OFF\";\n   parameter   clk7_use_even_counter_mode    = \"OFF\";\n   parameter   clk6_use_even_counter_mode    = \"OFF\";\n   parameter   clk5_use_even_counter_mode    = \"OFF\";\n   parameter   clk4_use_even_counter_mode    = \"OFF\";\n   parameter   clk3_use_even_counter_mode    = \"OFF\";\n   parameter   clk2_use_even_counter_mode    = \"OFF\";\n   parameter   clk1_use_even_counter_mode    = \"OFF\";\n   parameter   clk0_use_even_counter_mode    = \"OFF\";\n   parameter   clk9_use_even_counter_value   = \"OFF\";\n   parameter   clk8_use_even_counter_value   = \"OFF\";\n   parameter   clk7_use_even_counter_value   = \"OFF\";\n   parameter   clk6_use_even_counter_value   = \"OFF\";\n   parameter   clk5_use_even_counter_value   = \"OFF\";\n   parameter   clk4_use_even_counter_value   = \"OFF\";\n   parameter   clk3_use_even_counter_value   = \"OFF\";\n   parameter   clk2_use_even_counter_value   = \"OFF\";\n   parameter   clk1_use_even_counter_value   = \"OFF\";\n   parameter   clk0_use_even_counter_value   = \"OFF\";\n\n   parameter   clk2_output_frequency   = 0;\n   parameter   clk1_output_frequency   = 0;\n   parameter   clk0_output_frequency   = 0;\n\n   parameter   vco_min             = 0;\n   parameter   vco_max             = 0;\n   parameter   vco_center          = 0;\n   parameter   pfd_min             = 0;\n   parameter   pfd_max             = 0;\n   parameter   m_initial           = 1;\n   parameter   m                   = 0;\n   parameter   n                   = 1;\n   parameter   m2                  = 1;\n   parameter   n2                  = 1;\n   parameter   ss                  = 0;\n   parameter   l0_high             = 1;\n   parameter   l1_high             = 1;\n   parameter   g0_high             = 1;\n   parameter   g1_high             = 1;\n   parameter   g2_high             = 1;\n   parameter   g3_high             = 1;\n   parameter   e0_high             = 1;\n   parameter   e1_high             = 1;\n   parameter   e2_high             = 1;\n   parameter   e3_high             = 1;\n   parameter   l0_low              = 1;\n   parameter   l1_low              = 1;\n   parameter   g0_low              = 1;\n   parameter   g1_low              = 1;\n   parameter   g2_low              = 1;\n   parameter   g3_low              = 1;\n   parameter   e0_low              = 1;\n   parameter   e1_low              = 1;\n   parameter   e2_low              = 1;\n   parameter   e3_low              = 1;\n   parameter   l0_initial          = 1;\n   parameter   l1_initial          = 1;\n   parameter   g0_initial          = 1;\n   parameter   g1_initial          = 1;\n   parameter   g2_initial          = 1;\n   parameter   g3_initial          = 1;\n   parameter   e0_initial          = 1;\n   parameter   e1_initial          = 1;\n   parameter   e2_initial          = 1;\n   parameter   e3_initial          = 1;\n   parameter   l0_mode             = \"bypass\";\n   parameter   l1_mode             = \"bypass\";\n   parameter   g0_mode             = \"bypass\";\n   parameter   g1_mode             = \"bypass\";\n   parameter   g2_mode             = \"bypass\";\n   parameter   g3_mode             = \"bypass\";\n   parameter   e0_mode             = \"bypass\";\n   parameter   e1_mode             = \"bypass\";\n   parameter   e2_mode             = \"bypass\";\n   parameter   e3_mode             = \"bypass\";\n   parameter   l0_ph               = 0;\n   parameter   l1_ph               = 0;\n   parameter   g0_ph               = 0;\n   parameter   g1_ph               = 0;\n   parameter   g2_ph               = 0;\n   parameter   g3_ph               = 0;\n   parameter   e0_ph               = 0;\n   parameter   e1_ph               = 0;\n   parameter   e2_ph               = 0;\n   parameter   e3_ph               = 0;\n   parameter   m_ph                = 0;\n   parameter   l0_time_delay       = 0;\n   parameter   l1_time_delay       = 0;\n   parameter   g0_time_delay       = 0;\n   parameter   g1_time_delay       = 0;\n   parameter   g2_time_delay       = 0;\n   parameter   g3_time_delay       = 0;\n   parameter   e0_time_delay       = 0;\n   parameter   e1_time_delay       = 0;\n   parameter   e2_time_delay       = 0;\n   parameter   e3_time_delay       = 0;\n   parameter   m_time_delay        = 0;\n   parameter   n_time_delay        = 0;\n   parameter   extclk3_counter     = \"e3\" ;\n   parameter   extclk2_counter     = \"e2\" ;\n   parameter   extclk1_counter     = \"e1\" ;\n   parameter   extclk0_counter     = \"e0\" ;\n   parameter   clk9_counter        = \"c9\" ;\n   parameter   clk8_counter        = \"c8\" ;\n   parameter   clk7_counter        = \"c7\" ;\n   parameter   clk6_counter        = \"c6\" ;\n   parameter   clk5_counter        = \"l1\" ;\n   parameter   clk4_counter        = \"l0\" ;\n   parameter   clk3_counter        = \"g3\" ;\n   parameter   clk2_counter        = \"g2\" ;\n   parameter   clk1_counter        = \"g1\" ;\n   parameter   clk0_counter        = \"g0\" ;\n   parameter   enable0_counter     = \"l0\";\n   parameter   enable1_counter     = \"l0\";\n   parameter   charge_pump_current = 2;\n   parameter   loop_filter_r       = \"1.0\";\n   parameter   loop_filter_c       = 5;\n   parameter   vco_post_scale      = 0;\n   parameter   vco_frequency_control = \"AUTO\";\n   parameter   vco_phase_shift_step = 0;\n   parameter   lpm_type            = \"altpll\";\n\n   parameter port_clkena0 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena1 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena2 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena3 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena4 = \"PORT_CONNECTIVITY\";\n   parameter port_clkena5 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena0 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena1 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena2 = \"PORT_CONNECTIVITY\";\n   parameter port_extclkena3 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk0 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk1 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk2 = \"PORT_CONNECTIVITY\";\n   parameter port_extclk3 = \"PORT_CONNECTIVITY\";\n   parameter port_clk0 = \"PORT_CONNECTIVITY\";\n   parameter port_clk1 = \"PORT_CONNECTIVITY\";\n   parameter port_clk2 = \"PORT_CONNECTIVITY\";\n   parameter port_clk3 = \"PORT_CONNECTIVITY\";\n   parameter port_clk4 = \"PORT_CONNECTIVITY\";\n   parameter port_clk5 = \"PORT_CONNECTIVITY\";\n   parameter port_clk6 = \"PORT_CONNECTIVITY\";\n   parameter port_clk7 = \"PORT_CONNECTIVITY\";\n   parameter port_clk8 = \"PORT_CONNECTIVITY\";\n   parameter port_clk9 = \"PORT_CONNECTIVITY\";\n   parameter port_scandata = \"PORT_CONNECTIVITY\";\n   parameter port_scandataout = \"PORT_CONNECTIVITY\";\n   parameter port_scandone = \"PORT_CONNECTIVITY\";\n   parameter port_sclkout1 = \"PORT_CONNECTIVITY\";\n   parameter port_sclkout0 = \"PORT_CONNECTIVITY\";\n   parameter port_clkbad0 = \"PORT_CONNECTIVITY\";\n   parameter port_clkbad1 = \"PORT_CONNECTIVITY\";\n   parameter port_activeclock = \"PORT_CONNECTIVITY\";\n   parameter port_clkloss = \"PORT_CONNECTIVITY\";\n   parameter port_inclk1 = \"PORT_CONNECTIVITY\";\n   parameter port_inclk0 = \"PORT_CONNECTIVITY\";\n   parameter port_fbin = \"PORT_CONNECTIVITY\";\n   parameter port_fbout = \"PORT_CONNECTIVITY\";\n   parameter port_pllena = \"PORT_CONNECTIVITY\";\n   parameter port_clkswitch = \"PORT_CONNECTIVITY\";\n   parameter port_areset = \"PORT_CONNECTIVITY\";\n   parameter port_pfdena = \"PORT_CONNECTIVITY\";\n   parameter port_scanclk = \"PORT_CONNECTIVITY\";\n   parameter port_scanaclr = \"PORT_CONNECTIVITY\";\n   parameter port_scanread = \"PORT_CONNECTIVITY\";\n   parameter port_scanwrite = \"PORT_CONNECTIVITY\";\n   parameter port_enable0 = \"PORT_CONNECTIVITY\";\n   parameter port_enable1 = \"PORT_CONNECTIVITY\";\n   parameter port_locked = \"PORT_CONNECTIVITY\";\n   parameter port_configupdate = \"PORT_CONNECTIVITY\";\n   parameter port_phasecounterselect = \"PORT_CONNECTIVITY\";\n   parameter port_phasedone = \"PORT_CONNECTIVITY\";\n   parameter port_phasestep = \"PORT_CONNECTIVITY\";\n   parameter port_phaseupdown = \"PORT_CONNECTIVITY\";\n   parameter port_vcooverrange = \"PORT_CONNECTIVITY\";\n   parameter port_vcounderrange = \"PORT_CONNECTIVITY\";\n   parameter port_scanclkena = \"PORT_CONNECTIVITY\";\n   parameter using_fbmimicbidir_port = \"ON\";\n\n   input [1:0] inclk;\n   input       fbin;\n   input       pllena;\n   input       clkswitch;\n   input       areset;\n   input       pfdena;\n   input       clkena;\n   input       extclkena;\n   input       scanclk;\n   input       scanaclr;\n   input       scanclkena;\n   input       scanread;\n   input       scanwrite;\n   input       scandata;\n   input       phasecounterselect;\n   input       phaseupdown;\n   input       phasestep;\n   input       configupdate;\n   inout       fbmimicbidir;\n\n\n   output [width_clock-1:0] clk;\n   output [3:0]             extclk;\n   output [1:0]             clkbad;\n   output                   enable0;\n   output                   enable1;\n   output                   activeclock;\n   output                   clkloss;\n   output                   locked;\n   output                   scandataout;\n   output                   scandone;\n   output                   sclkout0;\n   output                   sclkout1;\n   output                   phasedone;\n   output                   vcooverrange;\n   output                   vcounderrange;\n   output                   fbout;\n   output                   fref;\n   output                   icdrclk;\n   output                   c0, c1, c2, c3, c4;\n\nendmodule // altpll\n`endif\n",
                 "brams_m9k.txt": "bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL\n  init   1\n  abits  13 @M1\n  dbits  1  @M1\n  abits  12 @M2\n  dbits  2  @M2\n  abits  11 @M3\n  dbits  4  @M3\n  abits  10 @M4\n  dbits  8  @M4\n  abits  10 @M5\n  dbits  9  @M5\n  abits  9  @M6\n  dbits  16 @M6\n  abits  9  @M7\n  dbits  18 @M7\n  abits  8  @M8\n  dbits  32 @M8\n  abits  8  @M9\n  dbits  36 @M9\n  groups 2\n  ports  1 1\n  wrmode 0 1\n  enable 1 1\n  transp 0 0\n  clocks 2 3\n  clkpol 2 3\nendbram\n\nmatch $__M9K_ALTSYNCRAM_SINGLEPORT_FULL\n  min efficiency 2\n  make_transp\nendmatch\n",
-                "brams_map_m9k.v": "module \\$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n\n   parameter CFG_ABITS = 8;\n   parameter CFG_DBITS = 36;\n   parameter ABITS = 1;\n   parameter DBITS = 1;\n   parameter CLKPOL2 = 1;\n   parameter CLKPOL3 = 1;\n\n   input CLK2;\n   input CLK3;\n   //Read data\n   output [CFG_DBITS-1:0] A1DATA;\n   input [CFG_ABITS-1:0]  A1ADDR;\n   input                  A1EN;\n   //Write data\n   output [CFG_DBITS-1:0] B1DATA;\n   input [CFG_ABITS-1:0]  B1ADDR;\n   input                  B1EN;\n\n   wire [CFG_DBITS-1:0]   B1DATA_t;\n\n   localparam MODE = CFG_DBITS == 1  ? 1:\n                     CFG_DBITS == 2  ? 2:\n                     CFG_DBITS == 4  ? 3:\n                     CFG_DBITS == 8  ? 4:\n                     CFG_DBITS == 9  ? 5:\n                     CFG_DBITS == 16 ? 6:\n                     CFG_DBITS == 18 ? 7:\n                     CFG_DBITS == 32 ? 8:\n                     CFG_DBITS == 36 ? 9:\n                     'bx;\n\n   localparam NUMWORDS = CFG_DBITS == 1  ? 8192:\n                         CFG_DBITS == 2  ? 4096:\n                         CFG_DBITS == 4  ? 2048:\n                         CFG_DBITS == 8  ? 1024:\n                         CFG_DBITS == 9  ? 1024:\n                         CFG_DBITS == 16 ?  512:\n                         CFG_DBITS == 18 ?  512:\n                         CFG_DBITS == 32 ?  256:\n                         CFG_DBITS == 36 ?  256:\n                         'bx;\n\n   altsyncram  #(.clock_enable_input_b           (\"ALTERNATE\"   ),\n                 .clock_enable_input_a           (\"ALTERNATE\"   ),\n                 .clock_enable_output_b          (\"NORMAL\"      ),\n                 .clock_enable_output_a          (\"NORMAL\"      ),\n                 .wrcontrol_aclr_a               (\"NONE\"        ),\n                 .indata_aclr_a                  (\"NONE\"        ),\n                 .address_aclr_a                 (\"NONE\"        ),\n                 .outdata_aclr_a                 (\"NONE\"        ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .operation_mode                 (\"SINGLE_PORT\" ),\n                 .intended_device_family         (\"CYCLONE IVE\" ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .lpm_type                       (\"altsyncram\"  ),\n                 .init_type                      (\"unused\"      ),\n                 .ram_block_type                 (\"AUTO\"        ),\n                 .lpm_hint                       (\"ENABLE_RUNTIME_MOD=NO\"), // Forced value\n                 .power_up_uninitialized         (\"FALSE\"),\n                 .read_during_write_mode_port_a  (\"NEW_DATA_NO_NBE_READ\"), // Forced value\n                 .width_byteena_a                (1), // Forced value\n                 .numwords_b                     ( NUMWORDS     ),\n                 .numwords_a                     ( NUMWORDS     ),\n                 .widthad_b                      ( CFG_DBITS    ),\n                 .width_b                        ( CFG_ABITS    ),\n                 .widthad_a                      ( CFG_DBITS    ),\n                 .width_a                        ( CFG_ABITS    )\n                 ) _TECHMAP_REPLACE_ (\n                                      .data_a(B1DATA),\n                                      .address_a(B1ADDR),\n                                      .wren_a(B1EN),\n                                      .rden_a(A1EN),\n                                      .q_a(A1DATA),\n                                      .data_b(B1DATA),\n                                      .address_b(0),\n                                      .wren_b(1'b0),\n                                      .rden_b(1'b0),\n                                      .q_b(),\n                                      .clock0(CLK2),\n                                      .clock1(1'b1), // Unused in single port mode\n                                      .clocken0(1'b1),\n                                      .clocken1(1'b1),\n                                      .clocken2(1'b1),\n                                      .clocken3(1'b1),\n                                      .aclr0(1'b0),\n                                      .aclr1(1'b0),\n                                      .addressstall_a(1'b0),\n                                      .addressstall_b(1'b0));\n\nendmodule\n\n",
+                "brams_map_m9k.v": "module \\$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n\n   parameter CFG_ABITS = 8;\n   parameter CFG_DBITS = 36;\n   parameter ABITS = 1;\n   parameter DBITS = 1;\n   parameter CLKPOL2 = 1;\n   parameter CLKPOL3 = 1;\n\n   input CLK2;\n   input CLK3;\n   //Read data\n   output [CFG_DBITS-1:0] A1DATA;\n   input [CFG_ABITS-1:0]  A1ADDR;\n   input                  A1EN;\n   //Write data\n   output [CFG_DBITS-1:0] B1DATA;\n   input [CFG_ABITS-1:0]  B1ADDR;\n   input                  B1EN;\n\n   wire [CFG_DBITS-1:0]   B1DATA_t;\n\n   localparam MODE = CFG_DBITS == 1  ? 1:\n                     CFG_DBITS == 2  ? 2:\n                     CFG_DBITS == 4  ? 3:\n                     CFG_DBITS == 8  ? 4:\n                     CFG_DBITS == 9  ? 5:\n                     CFG_DBITS == 16 ? 6:\n                     CFG_DBITS == 18 ? 7:\n                     CFG_DBITS == 32 ? 8:\n                     CFG_DBITS == 36 ? 9:\n                     'bx;\n\n   localparam NUMWORDS = CFG_DBITS == 1  ? 8192:\n                         CFG_DBITS == 2  ? 4096:\n                         CFG_DBITS == 4  ? 2048:\n                         CFG_DBITS == 8  ? 1024:\n                         CFG_DBITS == 9  ? 1024:\n                         CFG_DBITS == 16 ?  512:\n                         CFG_DBITS == 18 ?  512:\n                         CFG_DBITS == 32 ?  256:\n                         CFG_DBITS == 36 ?  256:\n                         'bx;\n\n   altsyncram  #(.clock_enable_input_b           (\"ALTERNATE\"   ),\n                 .clock_enable_input_a           (\"ALTERNATE\"   ),\n                 .clock_enable_output_b          (\"NORMAL\"      ),\n                 .clock_enable_output_a          (\"NORMAL\"      ),\n                 .wrcontrol_aclr_a               (\"NONE\"        ),\n                 .indata_aclr_a                  (\"NONE\"        ),\n                 .address_aclr_a                 (\"NONE\"        ),\n                 .outdata_aclr_a                 (\"NONE\"        ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .operation_mode                 (\"SINGLE_PORT\" ),\n                 .intended_device_family         (\"CYCLONE IVE\" ),\n                 .outdata_reg_a                  (\"UNREGISTERED\"),\n                 .lpm_type                       (\"altsyncram\"  ),\n                 .init_type                      (\"unused\"      ),\n                 .ram_block_type                 (\"AUTO\"        ),\n                 .lpm_hint                       (\"ENABLE_RUNTIME_MOD=NO\"), // Forced value\n                 .power_up_uninitialized         (\"FALSE\"),\n                 .read_during_write_mode_port_a  (\"NEW_DATA_NO_NBE_READ\"), // Forced value\n                 .width_byteena_a                (1), // Forced value\n                 .numwords_b                     ( NUMWORDS     ),\n                 .numwords_a                     ( NUMWORDS     ),\n                 .widthad_b                      ( CFG_ABITS    ),\n                 .width_b                        ( CFG_DBITS    ),\n                 .widthad_a                      ( CFG_ABITS    ),\n                 .width_a                        ( CFG_DBITS    )\n                 ) _TECHMAP_REPLACE_ (\n                                      .data_a(B1DATA),\n                                      .address_a(B1ADDR),\n                                      .wren_a(B1EN),\n                                      .rden_a(A1EN),\n                                      .q_a(A1DATA),\n                                      .data_b(B1DATA),\n                                      .address_b(0),\n                                      .wren_b(1'b0),\n                                      .rden_b(1'b0),\n                                      .q_b(),\n                                      .clock0(CLK2),\n                                      .clock1(1'b1), // Unused in single port mode\n                                      .clocken0(1'b1),\n                                      .clocken1(1'b1),\n                                      .clocken2(1'b1),\n                                      .clocken3(1'b1),\n                                      .aclr0(1'b0),\n                                      .aclr1(1'b0),\n                                      .addressstall_a(1'b0),\n                                      .addressstall_b(1'b0));\n\nendmodule\n\n",
                 "ff_map.v": "// Async Active Low Reset DFF\nmodule  \\$_DFFE_PN0P_ (input D, C, R, E, output Q);\n   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;\n   generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) begin\n     dffeas #(.is_wysiwyg(\"TRUE\"), .power_up(\"high\")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));\n   end else begin\n     dffeas #(.is_wysiwyg(\"TRUE\"), .power_up(\"low\")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(E), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));\n   end\n   endgenerate\n   wire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n",
                 "m9k_bb.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n(* blackbox *)\nmodule altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b,  wren_b, rden_b,\n                  q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,\n                  addressstall_a, addressstall_b);\n\n   parameter clock_enable_input_b          = \"ALTERNATE\";\n   parameter clock_enable_input_a          = \"ALTERNATE\";\n   parameter clock_enable_output_b         = \"NORMAL\";\n   parameter clock_enable_output_a         = \"NORMAL\";\n   parameter wrcontrol_aclr_a              = \"NONE\";\n   parameter indata_aclr_a                 = \"NONE\";\n   parameter address_aclr_a                = \"NONE\";\n   parameter outdata_aclr_a                = \"NONE\";\n   parameter outdata_reg_a                 = \"UNREGISTERED\";\n   parameter operation_mode                = \"SINGLE_PORT\";\n   parameter intended_device_family        = \"MAX 10 FPGA\";\n   parameter outdata_reg_b                 = \"UNREGISTERED\";\n   parameter lpm_type                      = \"altsyncram\";\n   parameter init_type                     = \"unused\";\n   parameter ram_block_type                = \"AUTO\";\n   parameter lpm_hint                      = \"ENABLE_RUNTIME_MOD=NO\";\n   parameter power_up_uninitialized        = \"FALSE\";\n   parameter read_during_write_mode_port_a = \"NEW_DATA_NO_NBE_READ\";\n   parameter width_byteena_a               = 1;\n   parameter numwords_b                    = 0;\n   parameter numwords_a                    = 0;\n   parameter widthad_b                     = 1;\n   parameter width_b                       = 1;\n   parameter widthad_a                     = 1;\n   parameter width_a                       = 1;\n\n   // Port A declarations\n   output [35:0] q_a;\n   input [35:0]  data_a;\n   input [7:0]   address_a;\n   input         wren_a;\n   input         rden_a;\n   // Port B declarations\n   output [35:0] q_b;\n   input [35:0]  data_b;\n   input [7:0]   address_b;\n   input         wren_b;\n   input         rden_b;\n   // Control signals\n   input         clock0, clock1;\n   input         clocken0, clocken1, clocken2, clocken3;\n   input         aclr0, aclr1;\n   input         addressstall_a;\n   input         addressstall_b;\n   // TODO: Implement the correct simulation model\n\nendmodule // altsyncram\n",
             },
@@ -231,7 +231,7 @@ export const filesystem = {
             },
             "max10": {
                 "cells_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n// > c60k28 (Viacheslav, VT) [at] yandex [dot] com\n// > Intel FPGA technology mapping. User must first simulate the generated \\\n// > netlist before going to test it on board.\n\n// Input buffer map\nmodule \\$__inpad (input I, output O);\n   fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));\nendmodule\n\n// Output buffer map\nmodule \\$__outpad (input I, output O);\n   fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));\nendmodule\n\n// LUT Map\n/* 0 -> datac\n   1 -> cin */\nmodule \\$lut (A, Y);\n   parameter WIDTH  = 0;\n   parameter LUT    = 0;\n   (* force_downto *)\n   input [WIDTH-1:0] A;\n   output            Y;\n   generate\n      if (WIDTH == 1) begin\n\t   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function\n      end else\n      if (WIDTH == 2) begin\n           fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input(\"datac\")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));\n      end else\n      if(WIDTH == 3) begin\n\t      fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input(\"datac\")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));\n      end else\n      if(WIDTH == 4) begin\n         fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input(\"datac\")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));\n      end else\n\t   wire _TECHMAP_FAIL_ = 1;\n   endgenerate\nendmodule //\n\n\n",
-                "cells_sim.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule VCC (output V);\n   assign V = 1'b1;\nendmodule // VCC\n\nmodule GND (output G);\n   assign G = 1'b0;\nendmodule // GND\n\n/* Altera MAX10 devices Input Buffer Primitive */\nmodule fiftyfivenm_io_ibuf\n  (output o, input i, input ibar);\n   assign ibar = ibar;\n   assign o    = i;\nendmodule // fiftyfivenm_io_ibuf\n\n/* Altera MAX10 devices Output Buffer Primitive */\nmodule fiftyfivenm_io_obuf\n  (output o, input i, input oe);\n   assign o  = i;\n   assign oe = oe;\nendmodule // fiftyfivenm_io_obuf\n\n/* Altera MAX10 4-input non-fracturable LUT Primitive */\nmodule fiftyfivenm_lcell_comb\n  (output combout, cout,\n   input dataa, datab, datac, datad, cin);\n\n   /* Internal parameters which define the behaviour\n    of the LUT primitive.\n    lut_mask define the lut function, can be expressed in 16-digit bin or hex.\n    sum_lutc_input define the type of LUT (combinational | arithmetic).\n    dont_touch for retiming || carry options.\n    lpm_type for WYSIWYG */\n\n   parameter lut_mask = 16'hFFFF;\n   parameter dont_touch = \"off\";\n   parameter lpm_type = \"fiftyfivenm_lcell_comb\";\n   parameter sum_lutc_input = \"datac\";\n\n   reg [1:0] lut_type;\n   reg       cout_rt;\n   reg       combout_rt;\n   wire      dataa_w;\n   wire      datab_w;\n   wire      datac_w;\n   wire      datad_w;\n   wire      cin_w;\n\n   assign dataa_w = dataa;\n   assign datab_w = datab;\n   assign datac_w = datac;\n   assign datad_w = datad;\n\n   function lut_data;\n      input [15:0] mask;\n      input        dataa, datab, datac, datad;\n      reg [7:0]    s3;\n      reg [3:0]    s2;\n      reg [1:0]    s1;\n      begin\n         s3 = datad ? mask[15:8] : mask[7:0];\n         s2 = datac ?   s3[7:4]  :   s3[3:0];\n         s1 = datab ?   s2[3:2]  :   s2[1:0];\n         lut_data = dataa ? s1[1] : s1[0];\n      end\n\n   endfunction\n\n   initial begin\n      if (sum_lutc_input == \"datac\") lut_type = 0;\n      else\n        if (sum_lutc_input == \"cin\")   lut_type = 1;\n        else begin\n           $error(\"Error in sum_lutc_input. Parameter %s is not a valid value.\\n\", sum_lutc_input);\n           $finish();\n        end\n   end\n\n   always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin\n      if (lut_type == 0) begin // logic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               datac_w, datad_w);\n      end\n      else if (lut_type == 1) begin // arithmetic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               cin_w, datad_w);\n      end\n      cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);\n   end\n\n   assign combout = combout_rt & 1'b1;\n   assign cout = cout_rt & 1'b1;\n\nendmodule // fiftyfivenm_lcell_comb\n\n/* Altera D Flip-Flop Primitive */\nmodule dffeas\n  (output q,\n   input d, clk, clrn, prn, ena,\n   input asdata, aload, sclr, sload);\n\n   // Timing simulation is not covered\n   parameter power_up=\"dontcare\";\n   parameter is_wysiwyg=\"false\";\n\n   reg   q_tmp;\n   wire  reset;\n   reg [7:0] debug_net;\n\n   assign reset       = (prn && sclr && ~clrn && ena);\n   assign q           = q_tmp & 1'b1;\n\n   always @(posedge clk, posedge aload) begin\n      if(reset)        q_tmp <= 0;\n      else q_tmp <= d;\n   end\n   assign q = q_tmp;\n\nendmodule // dffeas\n\n/* MAX10 altpll clearbox model */\n(* blackbox *)\nmodule fiftyfivenm_pll\n  (inclk,\n   fbin,\n   fbout,\n   clkswitch,\n   areset,\n   pfdena,\n   scanclk,\n   scandata,\n   scanclkena,\n   configupdate,\n   clk,\n   phasecounterselect,\n   phaseupdown,\n   phasestep,\n   clkbad,\n   activeclock,\n   locked,\n   scandataout,\n   scandone,\n   phasedone,\n   vcooverrange,\n   vcounderrange);\n\n   parameter operation_mode                = \"normal\";\n   parameter pll_type                      = \"auto\";\n   parameter compensate_clock              = \"clock0\";\n   parameter inclk0_input_frequency        = 0;\n   parameter inclk1_input_frequency        = 0;\n   parameter self_reset_on_loss_lock       = \"off\";\n   parameter switch_over_type              = \"auto\";\n   parameter switch_over_counter           = 1;\n   parameter enable_switch_over_counter    = \"off\";\n   parameter bandwidth                     = 0;\n   parameter bandwidth_type                = \"auto\";\n   parameter use_dc_coupling               = \"false\";\n   parameter lock_high = 0;\n   parameter lock_low = 0;\n   parameter lock_window_ui                = \"0.05\";\n   parameter test_bypass_lock_detect       = \"off\";\n   parameter clk0_output_frequency         = 0;\n   parameter clk0_multiply_by              = 0;\n   parameter clk0_divide_by                = 0;\n   parameter clk0_phase_shift              = \"0\";\n   parameter clk0_duty_cycle               = 50;\n   parameter clk1_output_frequency         = 0;\n   parameter clk1_multiply_by              = 0;\n   parameter clk1_divide_by                = 0;\n   parameter clk1_phase_shift              = \"0\";\n   parameter clk1_duty_cycle               = 50;\n   parameter clk2_output_frequency         = 0;\n   parameter clk2_multiply_by              = 0;\n   parameter clk2_divide_by                = 0;\n   parameter clk2_phase_shift              = \"0\";\n   parameter clk2_duty_cycle               = 50;\n   parameter clk3_output_frequency         = 0;\n   parameter clk3_multiply_by              = 0;\n   parameter clk3_divide_by                = 0;\n   parameter clk3_phase_shift              = \"0\";\n   parameter clk3_duty_cycle               = 50;\n   parameter clk4_output_frequency         = 0;\n   parameter clk4_multiply_by              = 0;\n   parameter clk4_divide_by                = 0;\n   parameter clk4_phase_shift              = \"0\";\n   parameter clk4_duty_cycle               = 50;\n   parameter pfd_min                       = 0;\n   parameter pfd_max                       = 0;\n   parameter vco_min                       = 0;\n   parameter vco_max                       = 0;\n   parameter vco_center                    = 0;\n   // Advanced user parameters\n   parameter m_initial = 1;\n   parameter m = 0;\n   parameter n = 1;\n   parameter c0_high = 1;\n   parameter c0_low = 1;\n   parameter c0_initial = 1;\n   parameter c0_mode = \"bypass\";\n   parameter c0_ph = 0;\n   parameter c1_high = 1;\n   parameter c1_low = 1;\n   parameter c1_initial = 1;\n   parameter c1_mode = \"bypass\";\n   parameter c1_ph = 0;\n   parameter c2_high = 1;\n   parameter c2_low = 1;\n   parameter c2_initial = 1;\n   parameter c2_mode = \"bypass\";\n   parameter c2_ph = 0;\n   parameter c3_high = 1;\n   parameter c3_low = 1;\n   parameter c3_initial = 1;\n   parameter c3_mode = \"bypass\";\n   parameter c3_ph = 0;\n   parameter c4_high = 1;\n   parameter c4_low = 1;\n   parameter c4_initial = 1;\n   parameter c4_mode = \"bypass\";\n   parameter c4_ph = 0;\n   parameter m_ph = 0;\n   parameter clk0_counter = \"unused\";\n   parameter clk1_counter = \"unused\";\n   parameter clk2_counter = \"unused\";\n   parameter clk3_counter = \"unused\";\n   parameter clk4_counter = \"unused\";\n   parameter c1_use_casc_in = \"off\";\n   parameter c2_use_casc_in = \"off\";\n   parameter c3_use_casc_in = \"off\";\n   parameter c4_use_casc_in = \"off\";\n   parameter m_test_source  = -1;\n   parameter c0_test_source = -1;\n   parameter c1_test_source = -1;\n   parameter c2_test_source = -1;\n   parameter c3_test_source = -1;\n   parameter c4_test_source = -1;\n   parameter vco_multiply_by = 0;\n   parameter vco_divide_by = 0;\n   parameter vco_post_scale = 1;\n   parameter vco_frequency_control = \"auto\";\n   parameter vco_phase_shift_step = 0;\n   parameter charge_pump_current = 10;\n   parameter loop_filter_r = \"1.0\";\n   parameter loop_filter_c = 0;\n   parameter pll_compensation_delay = 0;\n   parameter lpm_type = \"fiftyfivenm_pll\";\n   parameter phase_counter_select_width = 3;\n\n   input [1:0] inclk;\n   input       fbin;\n   input       clkswitch;\n   input       areset;\n   input       pfdena;\n   input [phase_counter_select_width - 1:0] phasecounterselect;\n   input                                    phaseupdown;\n   input                                    phasestep;\n   input                                    scanclk;\n   input                                    scanclkena;\n   input                                    scandata;\n   input                                    configupdate;\n   output [4:0]                             clk;\n   output [1:0]                             clkbad;\n   output                                   activeclock;\n   output                                   locked;\n   output                                   scandataout;\n   output                                   scandone;\n   output                                   fbout;\n   output                                   phasedone;\n   output                                   vcooverrange;\n   output                                   vcounderrange;\n\nendmodule // cycloneive_pll\n",
+                "cells_sim.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2024  Richard Herveille <richard.herveille@roalogic.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule VCC (output V);\n   assign V = 1'b1;\nendmodule // VCC\n\nmodule GND (output G);\n   assign G = 1'b0;\nendmodule // GND\n\n/* Altera MAX10 devices Input Buffer Primitive */\nmodule fiftyfivenm_io_ibuf\n  (output o, input i, input ibar);\n   assign ibar = ibar;\n   assign o    = i;\nendmodule // fiftyfivenm_io_ibuf\n\n/* Altera MAX10 devices Output Buffer Primitive */\nmodule fiftyfivenm_io_obuf\n  (output o, input i, input oe);\n   assign o  = i;\n   assign oe = oe;\nendmodule // fiftyfivenm_io_obuf\n\n/* Altera MAX10 4-input non-fracturable LUT Primitive */\nmodule fiftyfivenm_lcell_comb\n  (output combout, cout,\n   input dataa, datab, datac, datad, cin);\n\n   /* Internal parameters which define the behaviour\n    of the LUT primitive.\n    lut_mask define the lut function, can be expressed in 16-digit bin or hex.\n    sum_lutc_input define the type of LUT (combinational | arithmetic).\n    dont_touch for retiming || carry options.\n    lpm_type for WYSIWYG */\n\n   parameter lut_mask = 16'hFFFF;\n   parameter dont_touch = \"off\";\n   parameter lpm_type = \"fiftyfivenm_lcell_comb\";\n   parameter sum_lutc_input = \"datac\";\n\n   reg [1:0] lut_type;\n   reg       cout_rt;\n   reg       combout_rt;\n   wire      dataa_w;\n   wire      datab_w;\n   wire      datac_w;\n   wire      datad_w;\n   wire      cin_w;\n\n   assign dataa_w = dataa;\n   assign datab_w = datab;\n   assign datac_w = datac;\n   assign datad_w = datad;\n\n   function lut_data;\n      input [15:0] mask;\n      input        dataa, datab, datac, datad;\n      reg [7:0]    s3;\n      reg [3:0]    s2;\n      reg [1:0]    s1;\n      begin\n         s3 = datad ? mask[15:8] : mask[7:0];\n         s2 = datac ?   s3[7:4]  :   s3[3:0];\n         s1 = datab ?   s2[3:2]  :   s2[1:0];\n         lut_data = dataa ? s1[1] : s1[0];\n      end\n\n   endfunction\n\n   initial begin\n      if (sum_lutc_input == \"datac\") lut_type = 0;\n      else\n        if (sum_lutc_input == \"cin\")   lut_type = 1;\n        else begin\n           $error(\"Error in sum_lutc_input. Parameter %s is not a valid value.\\n\", sum_lutc_input);\n           $finish();\n        end\n   end\n\n   always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin\n      if (lut_type == 0) begin // logic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               datac_w, datad_w);\n      end\n      else if (lut_type == 1) begin // arithmetic function\n         combout_rt = lut_data(lut_mask, dataa_w, datab_w,\n                               cin_w, datad_w);\n      end\n      cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);\n   end\n\n   assign combout = combout_rt & 1'b1;\n   assign cout = cout_rt & 1'b1;\n\nendmodule // fiftyfivenm_lcell_comb\n\n/* Altera D Flip-Flop Primitive */\nmodule dffeas\n  (output q,\n   input d, clk, clrn, prn, ena,\n   input asdata, aload, sclr, sload);\n\n   // Timing simulation is not covered\n   parameter power_up=\"dontcare\";\n   parameter is_wysiwyg=\"false\";\n\n   reg   q_tmp;\n   wire  reset;\n   reg [7:0] debug_net;\n\n   assign reset       = (prn && sclr && ~clrn && ena);\n   assign q           = q_tmp & 1'b1;\n\n   always @(posedge clk, posedge aload) begin\n      if(reset)        q_tmp <= 0;\n      else q_tmp <= d;\n   end\n   assign q = q_tmp;\n\nendmodule // dffeas\n\n/* MAX10 altpll clearbox model */\n(* blackbox *)\nmodule fiftyfivenm_pll\n  (inclk,\n   fbin,\n   fbout,\n   clkswitch,\n   areset,\n   pfdena,\n   scanclk,\n   scandata,\n   scanclkena,\n   configupdate,\n   clk,\n   phasecounterselect,\n   phaseupdown,\n   phasestep,\n   clkbad,\n   activeclock,\n   locked,\n   scandataout,\n   scandone,\n   phasedone,\n   vcooverrange,\n   vcounderrange);\n\n   parameter operation_mode                = \"normal\";\n   parameter pll_type                      = \"auto\";\n   parameter compensate_clock              = \"clock0\";\n   parameter inclk0_input_frequency        = 0;\n   parameter inclk1_input_frequency        = 0;\n   parameter self_reset_on_loss_lock       = \"off\";\n   parameter switch_over_type              = \"auto\";\n   parameter switch_over_counter           = 1;\n   parameter enable_switch_over_counter    = \"off\";\n   parameter bandwidth                     = 0;\n   parameter bandwidth_type                = \"auto\";\n   parameter use_dc_coupling               = \"false\";\n   parameter lock_high = 0;\n   parameter lock_low = 0;\n   parameter lock_window_ui                = \"0.05\";\n   parameter test_bypass_lock_detect       = \"off\";\n   parameter clk0_output_frequency         = 0;\n   parameter clk0_multiply_by              = 0;\n   parameter clk0_divide_by                = 0;\n   parameter clk0_phase_shift              = \"0\";\n   parameter clk0_duty_cycle               = 50;\n   parameter clk1_output_frequency         = 0;\n   parameter clk1_multiply_by              = 0;\n   parameter clk1_divide_by                = 0;\n   parameter clk1_phase_shift              = \"0\";\n   parameter clk1_duty_cycle               = 50;\n   parameter clk2_output_frequency         = 0;\n   parameter clk2_multiply_by              = 0;\n   parameter clk2_divide_by                = 0;\n   parameter clk2_phase_shift              = \"0\";\n   parameter clk2_duty_cycle               = 50;\n   parameter clk3_output_frequency         = 0;\n   parameter clk3_multiply_by              = 0;\n   parameter clk3_divide_by                = 0;\n   parameter clk3_phase_shift              = \"0\";\n   parameter clk3_duty_cycle               = 50;\n   parameter clk4_output_frequency         = 0;\n   parameter clk4_multiply_by              = 0;\n   parameter clk4_divide_by                = 0;\n   parameter clk4_phase_shift              = \"0\";\n   parameter clk4_duty_cycle               = 50;\n   parameter pfd_min                       = 0;\n   parameter pfd_max                       = 0;\n   parameter vco_min                       = 0;\n   parameter vco_max                       = 0;\n   parameter vco_center                    = 0;\n   // Advanced user parameters\n   parameter m_initial = 1;\n   parameter m = 0;\n   parameter n = 1;\n   parameter c0_high = 1;\n   parameter c0_low = 1;\n   parameter c0_initial = 1;\n   parameter c0_mode = \"bypass\";\n   parameter c0_ph = 0;\n   parameter c1_high = 1;\n   parameter c1_low = 1;\n   parameter c1_initial = 1;\n   parameter c1_mode = \"bypass\";\n   parameter c1_ph = 0;\n   parameter c2_high = 1;\n   parameter c2_low = 1;\n   parameter c2_initial = 1;\n   parameter c2_mode = \"bypass\";\n   parameter c2_ph = 0;\n   parameter c3_high = 1;\n   parameter c3_low = 1;\n   parameter c3_initial = 1;\n   parameter c3_mode = \"bypass\";\n   parameter c3_ph = 0;\n   parameter c4_high = 1;\n   parameter c4_low = 1;\n   parameter c4_initial = 1;\n   parameter c4_mode = \"bypass\";\n   parameter c4_ph = 0;\n   parameter m_ph = 0;\n   parameter clk0_counter = \"unused\";\n   parameter clk1_counter = \"unused\";\n   parameter clk2_counter = \"unused\";\n   parameter clk3_counter = \"unused\";\n   parameter clk4_counter = \"unused\";\n   parameter c1_use_casc_in = \"off\";\n   parameter c2_use_casc_in = \"off\";\n   parameter c3_use_casc_in = \"off\";\n   parameter c4_use_casc_in = \"off\";\n   parameter m_test_source  = -1;\n   parameter c0_test_source = -1;\n   parameter c1_test_source = -1;\n   parameter c2_test_source = -1;\n   parameter c3_test_source = -1;\n   parameter c4_test_source = -1;\n   parameter vco_multiply_by = 0;\n   parameter vco_divide_by = 0;\n   parameter vco_post_scale = 1;\n   parameter vco_frequency_control = \"auto\";\n   parameter vco_phase_shift_step = 0;\n   parameter charge_pump_current = 10;\n   parameter loop_filter_r = \"1.0\";\n   parameter loop_filter_c = 0;\n   parameter pll_compensation_delay = 0;\n   parameter lpm_type = \"fiftyfivenm_pll\";\n   parameter phase_counter_select_width = 3;\n\n   input [1:0] inclk;\n   input       fbin;\n   input       clkswitch;\n   input       areset;\n   input       pfdena;\n   input [phase_counter_select_width - 1:0] phasecounterselect;\n   input                                    phaseupdown;\n   input                                    phasestep;\n   input                                    scanclk;\n   input                                    scanclkena;\n   input                                    scandata;\n   input                                    configupdate;\n   output [4:0]                             clk;\n   output [1:0]                             clkbad;\n   output                                   activeclock;\n   output                                   locked;\n   output                                   scandataout;\n   output                                   scandone;\n   output                                   fbout;\n   output                                   phasedone;\n   output                                   vcooverrange;\n   output                                   vcounderrange;\n\nendmodule // max10_pll\n\n\n/* MAX10 MULT clearbox model */\n(* blackbox *)\nmodule fiftyfivenm_mac_mult (\n  dataa,\n  datab,\n  dataout,\n  signa,\n  signb,\n\n  aclr,\n  clk,\n  ena\n);\n  parameter dataa_clock = \"none\";\n  parameter dataa_width = 18;\n  parameter datab_clock = \"none\";\n  parameter datab_width = 18;\n  parameter signa_clock = \"none\";\n  parameter signb_clock = \"none\";\n  parameter lpm_type    = \"fiftyfivenm_mac_mult\";\n\n  input  [dataa_width              -1:0] dataa;\n  input  [datab_width              -1:0] datab;\n  output [(dataa_width+datab_width)-1:0] dataout;\n  input                                  signa;\n  input                                  signb;\n  input                                  aclr;\n  input                                  clk;\n  input                                  ena;\nendmodule //fiftyfivenm_mac_mult\n\nmodule fiftyfivenm_mac_out (\n  dataa,\n  dataout,\n\n  aclr,\n  clk,\n  ena\n);\n\n  parameter dataa_width  = 38;\n  parameter output_clock = \"none\";\n  parameter lpm_type     = \"fiftyfivenm_mac_out\";\n\n  input  [dataa_width-1:0] dataa;\n  output [dataa_width-1:0] dataout;\n  input                    aclr;\n  input                    clk;\n  input                    ena;\nendmodule //fiftyfivenm_mac_out\n",
             },
         },
         "intel_alm": {
@@ -382,7 +382,7 @@ export const filesystem = {
         "simcells.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The internal logic cell simulation library.\n *\n *  This Verilog library contains simple simulation models for the internal\n *  logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology\n *  mapper (see \"techmap.v\" in this directory) and expected by the \"abc\" pass.\n *\n */\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_BUF_ (A, Y)\n//* group comb_simple\n//-\n//- A buffer. This cell type is always optimized away by the opt_clean pass.\n//-\n//- Truth table:    A | Y\n//-                ---+---\n//-                 0 | 0\n//-                 1 | 1\n//-\nmodule \\$_BUF_ (A, Y);\ninput A;\noutput Y;\nassign Y = A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NOT_ (A, Y)\n//* group comb_simple\n//-\n//- An inverter gate.\n//-\n//- Truth table:    A | Y\n//-                ---+---\n//-                 0 | 1\n//-                 1 | 0\n//-\nmodule \\$_NOT_ (A, Y);\ninput A;\noutput Y;\nassign Y = ~A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_AND_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input AND gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 0\n//-                 1 0 | 0\n//-                 1 1 | 1\n//-\nmodule \\$_AND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & B;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NAND_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input NAND gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 1\n//-                 1 0 | 1\n//-                 1 1 | 0\n//-\nmodule \\$_NAND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A & B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_OR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input OR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 1\n//-                 1 0 | 1\n//-                 1 1 | 1\n//-\nmodule \\$_OR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | B;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input NOR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 0\n//-                 1 0 | 0\n//-                 1 1 | 0\n//-\nmodule \\$_NOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A | B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_XOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input XOR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 1\n//-                 1 0 | 1\n//-                 1 1 | 0\n//-\nmodule \\$_XOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A ^ B;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_XNOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input XNOR gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 0\n//-                 1 0 | 0\n//-                 1 1 | 1\n//-\nmodule \\$_XNOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A ^ B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ANDNOT_ (A, B, Y)\n//* group comb_combined\n//-\n//- A 2-input AND-NOT gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 0\n//-                 0 1 | 0\n//-                 1 0 | 1\n//-                 1 1 | 0\n//-\nmodule \\$_ANDNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & (~B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ORNOT_ (A, B, Y)\n//* group comb_combined\n//-\n//- A 2-input OR-NOT gate.\n//-\n//- Truth table:    A B | Y\n//-                -----+---\n//-                 0 0 | 1\n//-                 0 1 | 0\n//-                 1 0 | 1\n//-                 1 1 | 1\n//-\nmodule \\$_ORNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | (~B);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX_ (A, B, S, Y)\n//* group comb_simple\n//-\n//- A 2-input MUX gate.\n//-\n//- Truth table:    A B S | Y\n//-                -------+---\n//-                 a - 0 | a\n//-                 - b 1 | b\n//-\nmodule \\$_MUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? B : A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_NMUX_ (A, B, S, Y)\n//-\n//- A 2-input inverting MUX gate.\n//* group comb_combined\n//-\n//- Truth table:    A B S | Y\n//-                -------+---\n//-                 0 - 0 | 1\n//-                 1 - 0 | 0\n//-                 - 0 1 | 1\n//-                 - 1 1 | 0\n//-\nmodule \\$_NMUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? !B : !A;\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX4_ (A, B, C, D, S, T, Y)\n//* group comb_combined\n//-\n//- A 4-input MUX gate.\n//-\n//- Truth table:    A B C D S T | Y\n//-                -------------+---\n//-                 a - - - 0 0 | a\n//-                 - b - - 1 0 | b\n//-                 - - c - 0 1 | c\n//-                 - - - d 1 1 | d\n//-\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\ninput A, B, C, D, S, T;\noutput Y;\nassign Y = T ? (S ? D : C) :\n               (S ? B : A);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y)\n//* group comb_combined\n//-\n//- An 8-input MUX gate.\n//-\n//- Truth table:    A B C D E F G H S T U | Y\n//-                -----------------------+---\n//-                 a - - - - - - - 0 0 0 | a\n//-                 - b - - - - - - 1 0 0 | b\n//-                 - - c - - - - - 0 1 0 | c\n//-                 - - - d - - - - 1 1 0 | d\n//-                 - - - - e - - - 0 0 1 | e\n//-                 - - - - - f - - 1 0 1 | f\n//-                 - - - - - - g - 0 1 1 | g\n//-                 - - - - - - - h 1 1 1 | h\n//-\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\ninput A, B, C, D, E, F, G, H, S, T, U;\noutput Y;\nassign Y = U ? T ? (S ? H : G) :\n                   (S ? F : E) :\n               T ? (S ? D : C) :\n                   (S ? B : A);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)\n//* group comb_combined\n//-\n//- A 16-input MUX gate.\n//-\n//- Truth table:    A B C D E F G H I J K L M N O P S T U V | Y\n//-                -----------------------------------------+---\n//-                 a - - - - - - - - - - - - - - - 0 0 0 0 | a\n//-                 - b - - - - - - - - - - - - - - 1 0 0 0 | b\n//-                 - - c - - - - - - - - - - - - - 0 1 0 0 | c\n//-                 - - - d - - - - - - - - - - - - 1 1 0 0 | d\n//-                 - - - - e - - - - - - - - - - - 0 0 1 0 | e\n//-                 - - - - - f - - - - - - - - - - 1 0 1 0 | f\n//-                 - - - - - - g - - - - - - - - - 0 1 1 0 | g\n//-                 - - - - - - - h - - - - - - - - 1 1 1 0 | h\n//-                 - - - - - - - - i - - - - - - - 0 0 0 1 | i\n//-                 - - - - - - - - - j - - - - - - 1 0 0 1 | j\n//-                 - - - - - - - - - - k - - - - - 0 1 0 1 | k\n//-                 - - - - - - - - - - - l - - - - 1 1 0 1 | l\n//-                 - - - - - - - - - - - - m - - - 0 0 1 1 | m\n//-                 - - - - - - - - - - - - - n - - 1 0 1 1 | n\n//-                 - - - - - - - - - - - - - - o - 0 1 1 1 | o\n//-                 - - - - - - - - - - - - - - - p 1 1 1 1 | p\n//-\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\ninput A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\noutput Y;\nassign Y = V ? U ? T ? (S ? P : O) :\n                       (S ? N : M) :\n                   T ? (S ? L : K) :\n                       (S ? J : I) :\n               U ? T ? (S ? H : G) :\n                       (S ? F : E) :\n                   T ? (S ? D : C) :\n                       (S ? B : A);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_AOI3_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 3-input And-Or-Invert gate.\n//-\n//- Truth table:    A B C | Y\n//-                -------+---\n//-                 0 0 0 | 1\n//-                 0 0 1 | 0\n//-                 0 1 0 | 1\n//-                 0 1 1 | 0\n//-                 1 0 0 | 1\n//-                 1 0 1 | 0\n//-                 1 1 0 | 0\n//-                 1 1 1 | 0\n//-\nmodule \\$_AOI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A & B) | C);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_OAI3_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 3-input Or-And-Invert gate.\n//-\n//- Truth table:    A B C | Y\n//-                -------+---\n//-                 0 0 0 | 1\n//-                 0 0 1 | 1\n//-                 0 1 0 | 1\n//-                 0 1 1 | 0\n//-                 1 0 0 | 1\n//-                 1 0 1 | 0\n//-                 1 1 0 | 1\n//-                 1 1 1 | 0\n//-\nmodule \\$_OAI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A | B) & C);\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_AOI4_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 4-input And-Or-Invert gate.\n//-\n//- Truth table:    A B C D | Y\n//-                ---------+---\n//-                 0 0 0 0 | 1\n//-                 0 0 0 1 | 1\n//-                 0 0 1 0 | 1\n//-                 0 0 1 1 | 0\n//-                 0 1 0 0 | 1\n//-                 0 1 0 1 | 1\n//-                 0 1 1 0 | 1\n//-                 0 1 1 1 | 0\n//-                 1 0 0 0 | 1\n//-                 1 0 0 1 | 1\n//-                 1 0 1 0 | 1\n//-                 1 0 1 1 | 0\n//-                 1 1 0 0 | 0\n//-                 1 1 0 1 | 0\n//-                 1 1 1 0 | 0\n//-                 1 1 1 1 | 0\n//-\nmodule \\$_AOI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A & B) | (C & D));\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_OAI4_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 4-input Or-And-Invert gate.\n//-\n//- Truth table:    A B C D | Y\n//-                ---------+---\n//-                 0 0 0 0 | 1\n//-                 0 0 0 1 | 1\n//-                 0 0 1 0 | 1\n//-                 0 0 1 1 | 1\n//-                 0 1 0 0 | 1\n//-                 0 1 0 1 | 0\n//-                 0 1 1 0 | 0\n//-                 0 1 1 1 | 0\n//-                 1 0 0 0 | 1\n//-                 1 0 0 1 | 0\n//-                 1 0 1 0 | 0\n//-                 1 0 1 1 | 0\n//-                 1 1 0 0 | 1\n//-                 1 1 0 1 | 0\n//-                 1 1 1 0 | 0\n//-                 1 1 1 1 | 0\n//-\nmodule \\$_OAI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A | B) & (C | D));\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_TBUF_ (A, E, Y)\n//* group gate_other\n//-\n//- A tri-state buffer.\n//-\n//- Truth table:    A E | Y\n//-                -----+---\n//-                 a 1 | a\n//-                 - 0 | z\n//-\nmodule \\$_TBUF_ (A, E, Y);\ninput A, E;\noutput Y;\nassign Y = E ? A : 1'bz;\nendmodule\n\n// NOTE: the following cell types are autogenerated.  DO NOT EDIT them manually,\n// instead edit the templates in gen_ff_types.py and rerun it.\n\n// START AUTOGENERATED CELL TYPES\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_NN_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with negative polarity SET and negative polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 0 | 0\n//-                 0 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_NN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_NP_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with negative polarity SET and positive polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 1 | 0\n//-                 0 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_NP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_PN_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with positive polarity SET and negative polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 0 | 0\n//-                 1 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_PN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SR_PP_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with positive polarity SET and positive polarity RESET.\n//-\n//- Truth table:    S R | Q\n//-                -----+---\n//-                 - 1 | 0\n//-                 1 - | 1\n//-                 - - | q\n//-\nmodule \\$_SR_PP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n`ifdef SIMCELLS_FF\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_FF_ (D, Q)\n//* group reg_ff\n//-\n//- A D-type flip-flop that is clocked from the implicit global clock. (This cell\n//- type is usually only used in netlists for formal verification.)\n//-\nmodule \\$_FF_ (D, Q);\ninput D;\noutput reg Q;\nalways @($global_clock) begin\n\tQ <= D;\nend\nendmodule\n`endif\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_N_ (D, C, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop.\n//-\n//- Truth table:    D C | Q\n//-                -----+---\n//-                 d \\ | d\n//-                 - - | q\n//-\nmodule \\$_DFF_N_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(negedge C) begin\n\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_P_ (D, C, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop.\n//-\n//- Truth table:    D C | Q\n//-                -----+---\n//-                 d / | d\n//-                 - - | q\n//-\nmodule \\$_DFF_P_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(posedge C) begin\n\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d \\ 0 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_NN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d \\ 1 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_NP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d / 0 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_PN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table:    D C E | Q\n//-                -------+---\n//-                 d / 1 | d\n//-                 - - - | q\n//-\nmodule \\$_DFFE_PP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_NP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 0 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFF_PP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - - 1 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_DFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 0 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - - 1 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_NN_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 0 a  | a\n//-                 d \\ - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_NN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_NP_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 1 a  | a\n//-                 d \\ - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_NP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_PN_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 0 a  | a\n//-                 d / - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_PN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFF_PP_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table:    D C L AD | Q\n//-                ----------+---\n//-                 - - 1 a  | a\n//-                 d / - -  | d\n//-                 - - - -  | q\n//-\nmodule \\$_ALDFF_PP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NNN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d \\ - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NNP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d \\ - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NPN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d \\ - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_NPP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d \\ - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_NPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PNN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d / - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PNP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 0 a  - | a\n//-                 d / - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PPN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d / - -  0 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_ALDFFE_PPP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table:    D C L AD E | Q\n//-                ------------+---\n//-                 - - 1 a  - | a\n//-                 d / - -  1 | d\n//-                 - - - -  - | q\n//-\nmodule \\$_ALDFFE_PPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NNN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NNP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NPN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_NPP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 \\ - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_NPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PNN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PNP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PPN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSR_PPP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    C S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 / - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DFFSR_PPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NNPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_NPPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 \\ - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PNPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 0 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 0 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 0 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DFFSRE_PPPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table:    C S R E D | Q\n//-                -----------+---\n//-                 - - 1 - - | 0\n//-                 - 1 - - - | 1\n//-                 / - - 1 d | d\n//-                 - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n        else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 0 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 0 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 1 | 0\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_NP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - \\ 1 | 1\n//-                 d \\ - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 0 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 0 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 1 | 0\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFF_PP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table:    D C R | Q\n//-                -------+---\n//-                 - / 1 | 1\n//-                 d / - | d\n//-                 - - - | q\n//-\nmodule \\$_SDFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 - | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 - | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 0 | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 1 | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 0 | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 0 1 | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 0 | 0\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 1 | 0\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 0 | 1\n//-                 d \\ - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - \\ 1 1 | 1\n//-                 d \\ - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 0 | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 1 | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 0 | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 0 1 | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 0 | 0\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 1 | 0\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 0 | 1\n//-                 d / - 0 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_SDFFCE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table:    D C R E | Q\n//-                ---------+---\n//-                 - / 1 1 | 1\n//-                 d / - 1 | d\n//-                 - - - - | q\n//-\nmodule \\$_SDFFCE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_N_ (E, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch.\n//-\n//- Truth table:    E D | Q\n//-                -----+---\n//-                 0 d | d\n//-                 - - | q\n//-\nmodule \\$_DLATCH_N_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_P_ (E, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch.\n//-\n//- Truth table:    E D | Q\n//-                -----+---\n//-                 1 d | d\n//-                 - - | q\n//-\nmodule \\$_DLATCH_P_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NN0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 0\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NN1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 1\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NP0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 0\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_NP1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 1\n//-                 0 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_NP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PN0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 0\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PN1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 0 - | 1\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n                Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PP0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity reset.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 0\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCH_PP1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set.\n//-\n//- Truth table:    E R D | Q\n//-                -------+---\n//-                 - 1 - | 1\n//-                 1 - d | d\n//-                 - - - | q\n//-\nmodule \\$_DLATCH_PP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n                Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NNN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NNP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NPN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_NPP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 0 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_NPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PNN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 0 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PNP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 0 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PPN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 0 - | 0\n//-                 - 1 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $_DLATCHSR_PPP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table:    E S R D | Q\n//-                ---------+---\n//-                 - - 1 - | 0\n//-                 - 1 - - | 1\n//-                 1 - - d | d\n//-                 - - - - | q\n//-\nmodule \\$_DLATCHSR_PPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n",
         "simlib.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The Simulation Library.\n *\n *  This Verilog library contains simple simulation models for the internal\n *  cells ($not, ...) generated by the frontends and used in most passes.\n *\n *  This library can be used to verify the internal netlists as generated\n *  by the different frontends and passes.\n *\n *  Note that memory can only be simulated when all $memrd and $memwr cells\n *  have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n *  pass is doing).\n *\n */\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise inverter\n//* group unary\n//- This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $pos (A, Y)\n//* group unary\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $buf (A, Y)\n//* group unary\n//-\n//- A simple coarse-grain buffer cell type for the experimental buffered-normalized\n//- mode. Note this cell does't get removed by 'opt_clean' and is not recommended\n//- for general use.\n//-\nmodule \\$buf (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $neg (A, Y)\n//* group unary\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $and (A, B, Y)\n//* group binary\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $or (A, B, Y)\n//* group binary\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $xor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $xnor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_and (A, Y)\n//* group unary\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_or (A, Y)\n//* group unary\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_xor (A, Y)\n//* group unary\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_xnor (A, Y)\n//* group unary\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $reduce_bool (A, Y)\n//* group unary\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $shl (A, B, Y)\n//* group binary\n//-\n//- A logical shift-left operation. This corresponds to the Verilog '<<' operator.\n//-\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $shr (A, B, Y)\n//* group binary\n//-\n//- A logical shift-right operation. This corresponds to the Verilog '>>' operator.\n//-\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sshl (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-left operation. \n//- This corresponds to the Verilog '<<<' operator.\n//-\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sshr (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-right operation.\n//- This corresponds to the Verilog '>>>' operator.\n//-\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Variable shifter\n//* group binary\n//- Performs a right logical shift if the second operand is positive (or\n//- unsigned), and a left logical shift if it is negative.\n//-\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Indexed part-select\n//* group binary\n//* tags x-output\n//- Same as the `$shift` cell, but fills with 'x'.\n//-\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant  bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P;    // Propagate\ninput [WIDTH-1:0] G;    // Generate\ninput CI;               // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Arithmetic logic unit\n//* group arith\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- `$add`, `$sub`, `$lt`, `$le`, `$ge`, `$gt`, `$eq`, `$eqx`, `$ne`, `$nex`\n//- cells into this `$alu` cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A;      // Input operand\ninput [B_WIDTH-1:0] B;      // Input operand\noutput [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,\n                            //          used in combination with\n                            //          reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y;     // Sum\n\ninput CI;                   // Carry-in (set for $sub)\ninput BI;                   // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO;    // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $lt (A, B, Y)\n//* group binary\n//-\n//- A less-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<' operator.\n//-\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $le (A, B, Y)\n//* group binary\n//-\n//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<=' operator.\n//-\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $eq (A, B, Y)\n//* group binary\n//-\n//- An equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '==' operator.\n//-\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $ne (A, B, Y)\n//* group binary\n//-\n//- An inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!=' operator.\n//-\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case equality\n//* group binary\n//* tags x-aware\n//- An exact equality comparison between inputs 'A' and 'B'. Also known as the\n//- case equality operator. This corresponds to the Verilog '===' operator.\n//- Unlike equality comparison that can give 'x' as output, an exact equality\n//- comparison will strictly give '0' or '1' as output, even if input includes\n//- 'x' or 'z' values.\n//-\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case inequality\n//* group binary\n//* tags x-aware\n//- This corresponds to the Verilog '!==' operator.\n//-\n//- Refer to `$eqx` for more details.\n//-\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $ge (A, B, Y)\n//* group binary\n//-\n//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '>=' operator.\n//-\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $gt (A, B, Y)\n//* group binary\n//-\n//- A greater-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '>' operator.\n//-\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $add (A, B, Y)\n//* group binary\n//-\n//-  Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator.\n//-\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $sub (A, B, Y)\n//* group binary\n//-\n//- Subtraction between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '-' operator.\n//-\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $mul (A, B, Y)\n//* group binary\n//-\n//- Multiplication of inputs 'A' and 'B'.\n//- This corresponds to the Verilog '*' operator.\n//-\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $macc (A, B, Y)\n//* group arith\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n//     * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED   (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A    (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B    (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Divider\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '/' operator, performing division and\n//- truncating the result (rounding towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Modulo\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '%' operator, giving the module (or\n//- remainder) of division and truncating the result (rounding towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $divfloor (A, B, Y)\n//* group binary\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $modfloor (A, B, Y)\n//* group binary\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $pow (A, B, Y)\n//* group binary\n//-\n//- Exponentiation of an input (Y = A ** B). \n//- This corresponds to the Verilog '**' operator.\n//-\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_not (A, Y)\n//* group unary\n//-\n//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.\n//-\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_and (A, B, Y)\n//* group binary\n//-\n//- A logical AND. This corresponds to the Verilog '&&' operator.\n//-\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $logic_or (A, B, Y)\n//* group binary\n//-\n//- A logical OR. This corresponds to the Verilog '||' operator.\n//-\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group wire\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $concat (A, B, Y)\n//* group wire\n//-\n//- Concatenation of inputs into a single output ( Y = {B, A} ).\n//-\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $mux (A, B, S, Y)\n//-\n//- Multiplexer i.e selecting between two inputs based on select signal.\n//-\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Binary-encoded multiplexer\n//* group mux\n//- Selects between 'slices' of A where each value of S corresponds to a unique\n//- slice.\n//-\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Priority-encoded multiplexer\n//* group mux\n//* tags x-output\n//- Selects between 'slices' of B where each slice corresponds to a single bit\n//- of S. Outputs A when all bits of S are low.\n//-\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $demux (A, S, Y)\n//-\n//- Demultiplexer i.e routing single input to several outputs based on select signal.\n//- Unselected outputs are driven to zero.\n//-\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n//* group logic\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group logic\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//-     $tribuf (A, EN, Y)\n//-\n//- A tri-state buffer. \n//- This buffer conditionally drives the output with the value of the input\n//- based on the enable signal.\n//-\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN     ? (EDGE_POL    ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise case equality\n//* group binary\n//* tags x-aware\n//- A bit-wise version of `$eqx`.\n//-\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise multiplexer\n//* group mux\n//- Equivalent to a series of 1-bit wide `$mux` cells.\n//-\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group fsm\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <-   MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n//* group mem\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
         "smtmap.v": "(* techmap_celltype = \"$pmux\" *)\nmodule smt_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*(S_WIDTH+1)-1:0] C;\n\n\t\tassign C[WIDTH-1:0] = A;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1)\n\t\t\tassign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i];\n\t\tassign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH];\n\tendgenerate\nendmodule\n",
-        "techmap.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The internal logic cell technology mapper.\n *\n *  This Verilog library contains the mapping of internal cells (e.g. $not with\n *  variable bit width) to the internal logic cells (such as the single bit $_NOT_\n *  gate). Usually this logic network is then mapped to the actual technology\n *  using e.g. the \"abc\" pass.\n *\n *  Note that this library does not map $mem cells. They must be mapped to logic\n *  and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n *  which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\n`ifndef NODIV\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n`endif\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
+        "techmap.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n *  ---\n *\n *  The internal logic cell technology mapper.\n *\n *  This Verilog library contains the mapping of internal cells (e.g. $not with\n *  variable bit width) to the internal logic cells (such as the single bit $_NOT_\n *  gate). Usually this logic network is then mapped to the actual technology\n *  using e.g. the \"abc\" pass.\n *\n *  Note that this library does not map $mem cells. They must be mapped to logic\n *  and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n *  which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$buf $pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\n`ifndef NODIV\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n`endif\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
         "xilinx": {
             "abc9_model.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *                2019  Eddie Hung    <eddie@fpgeh.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n\n// Box containing MUXF7.[AB] + MUXF8,\n//   Necessary to make these an atomic unit so that\n//   ABC cannot optimise just one of the MUXF7 away\n//   and expect to save on its delay\n(* abc9_box, lib_whitebox *)\nmodule \\$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);\n  assign O = S1 ? (S0 ? I3 : I2)\n                : (S0 ? I1 : I0);\n  specify\n    (I0 => O) = 294;\n    (I1 => O) = 297;\n    (I2 => O) = 311;\n    (I3 => O) = 317;\n    (S0 => O) = 390;\n    (S1 => O) = 273;\n  endspecify\nendmodule\n",
             "arith_map.v": "/*\n *  yosys -- Yosys Open SYnthesis Suite\n *\n *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n// LCU\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _80_xilinx_lcu (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = WIDTH <= 2;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [WIDTH-1:0] S = P & ~G;\n\n\tgenerate for (i = 0; i < WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(G[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\tend endgenerate\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH    = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH    = MAX_WIDTH - WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S =  {{PAD_WIDTH{1'b0}}, P & ~G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign CO = C;\n\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI    (1'd0),\n\t\t\t.DI    (GG[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4]),\n\t\t\t);\n\t\tend else begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI    (C [i*4 - 1]),\n\t\t\t.DI    (GG[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4]),\n\t\t\t);\n\t\tend\n\tend endgenerate\nend endgenerate\n\nendmodule\n\n\n// ============================================================================\n// ALU\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_xilinx_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\tparameter _TECHMAP_CONSTVAL_CI_ = 0;\n\tparameter _TECHMAP_CONSTMSK_CI_ = 0;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] S  = {AA ^ BB};\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(AA[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\t\tXORCY xorcy (\n\t\t\t.CI(C[i]),\n\t\t\t.LI(S[i]),\n\t\t\t.O(Y[i])\n\t\t);\n\tend endgenerate\n\n\tassign X = S;\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH    = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH    = MAX_WIDTH - Y_WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, AA ^ BB};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] O;\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign Y = O, CO = C;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI    (1'd0),\n\t\t\t.DI    (DI[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.O     (O [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4])\n\t\t\t);\n\t\tend else begin\n\t\t    CARRY4 carry4\n\t\t    (\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI    (C [i*4 - 1]),\n\t\t\t.DI    (DI[i*4 +: 4]),\n\t\t\t.S     (S [i*4 +: 4]),\n\t\t\t.O     (O [i*4 +: 4]),\n\t\t\t.CO    (C [i*4 +: 4])\n\t\t    );\n\t\tend\n\tend endgenerate\n\n\tassign X = S;\n\nend endgenerate\nendmodule\n\n",