@yowasp/yosys 0.46.789 → 0.48.833

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Files changed (4) hide show
  1. package/gen/resources-yosys.js +23 -19
  2. package/gen/share/quicklogic/qlf_k6n10f/bram_types_sim.v +1 -1
  3. package/gen/yosys.core.wasm +0 -0
  4. package/package.json +1 -1
package/gen/resources-yosys.js CHANGED
@@ -28,7 +28,9 @@ export const filesystem = {
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  },
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  "cells.lib": "library(yosys_cells) {\n\tcell(DFF_N) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_P) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NN0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NN1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NP0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NP1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PN0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PN1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PP0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PP1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n}\n",
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+ "han-carlson.v": "(* techmap_celltype = \"$lcu\" *)\nmodule _80_lcu_han_carlson (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\ti = 0;\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\t\tif (i < $clog2(WIDTH)) begin\n\n\t\t\t// First layer: BK\n\t\t\tfor (j = WIDTH - 1; j >= 0; j = j - 1) begin\n\t\t\t\tif (j % 2 == 1) begin\n\t\t\t\t\tg[j] = g[j] | p[j] & g[j - 1];\n\t\t\t\t\tp[j] = p[j] & p[j - 1];\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t// Inner (log(WIDTH) - 1) layers: KS\n\t\t\tfor (i = 1; i < $clog2(WIDTH); i = i + 1) begin\n\t\t\t\tfor (j = WIDTH - 1; j >= 2**i; j = j - 1) begin\n\t\t\t\t\tif (j % 2 == 1) begin\n\t\t\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**i];\n\t\t\t\t\t\tp[j] = p[j] & p[j - 2**i];\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\t// Last layer: BK\n\t\t\tif (i < ($clog2(WIDTH) + 1)) begin\n\t\t\t\tfor (j = WIDTH - 1; j >= 0; j = j - 1) begin\n\t\t\t\t\tif ((j % 2 == 0) && (j > 0)) begin\n\t\t\t\t\t\tg[j] = g[j] | p[j] & g[j - 1];\n\t\t\t\t\t\tp[j] = p[j] & p[j - 1];\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n",
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  "kogge-stone.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Martin Povišer <povik@cutebit.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _80_lcu_kogge_stone (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\tfor (i = 0; i < $clog2(WIDTH); i = i + 1) begin\n\t\t\t// iterate in reverse so we don't confuse a result from this stage and the previous\n\t\t\tfor (j = WIDTH - 1; j >= 2**i; j = j - 1) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**i];\n\t\t\t\tp[j] = p[j] & p[j - 2**i];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n",
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+ "sklansky.v": "(* techmap_celltype = \"$lcu\" *)\nmodule _80_lcu_sklansky (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\tfor (i = 0; i < $clog2(WIDTH); i = i + 1) begin\n\t\t\t// iterate in reverse so we don't confuse a result from this stage and the previous\n\t\t\tfor (j = WIDTH - 1; j >= 0; j = j - 1) begin\n\t\t\t\tif (j & 2**i) begin\n\t\t\t\t\tg[j] = g[j] | p[j] & g[(j & ~(2**i - 1)) - 1];\n\t\t\t\t\tp[j] = p[j] & p[(j & ~(2**i - 1)) - 1];\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n",
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  "cmp2lcu.v": "// This pass performs an optimisation that decomposes wide arithmetic\n// comparisons into LUT-size chunks (as guided by the `LUT_WIDTH\n// macro) connected to a single lookahead-carry-unit $lcu cell,\n// which is typically mapped to dedicated (and fast) FPGA\n// carry-chains.\n(* techmap_celltype = \"$lt $le $gt $ge\" *)\nmodule _80_lcu_cmp_ (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\n(* force_downto *)\noutput [Y_WIDTH-1:0] Y;\n\nparameter _TECHMAP_CELLTYPE_ = \"\";\n\ngenerate\n if (_TECHMAP_CELLTYPE_ == \"\" || `LUT_WIDTH < 2)\n wire _TECHMAP_FAIL_ = 1;\n else if (_TECHMAP_CELLTYPE_ == \"$lt\") begin\n // Transform $lt into $gt by swapping A and B\n $gt #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));\n end\n else if (_TECHMAP_CELLTYPE_ == \"$le\") begin\n // Transform $le into $ge by swapping A and B\n $ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));\n end\n else begin\n // Perform sign extension on A and B\n localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;\n (* force_downto *)\n wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n (* force_downto *)\n wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};\n // For $ge operation, start with the assumption that A and B are\n // equal (propagating this equality if A and B turn out to be so)\n localparam CI = _TECHMAP_CELLTYPE_ == \"$ge\";\n $__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))\n _TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));\n end\nendgenerate\nendmodule\n\nmodule $__CMP2LCU (A, B, P, G, Y);\n\nparameter AB_WIDTH = 0;\nparameter AB_SIGNED = 0;\nparameter LCU_WIDTH = 1;\nparameter BUDGET = 0;\nparameter CI = 0;\n\n(* force_downto *)\ninput [AB_WIDTH-1:0] A; // A from original $gt/$ge\n(* force_downto *)\ninput [AB_WIDTH-1:0] B; // B from original $gt/$ge\n(* force_downto *)\ninput [LCU_WIDTH-1:0] P; // P of $lcu\n(* force_downto *)\ninput [LCU_WIDTH-1:0] G; // G of $lcu\noutput Y;\n\nparameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;\nparameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\nparameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;\n\ngenerate\n if (AB_WIDTH == 0) begin\n (* force_downto *)\n wire [LCU_WIDTH-1:0] CO;\n $lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));\n assign Y = CO[LCU_WIDTH-1];\n end\n else begin\n localparam COST =\n _TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]\n ? 0\n : (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]\n ? 1\n : 2);\n\n if (BUDGET < COST)\n $__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))\n _TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, 1'b1}), .G({G, 1'b0}), .Y(Y));\n else begin\n wire PP, GG;\n // Bit-wise equality (xnor) of A and B\n assign PP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1];\n if (AB_SIGNED)\n assign GG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1];\n else if (_TECHMAP_CONSTMSK_P_[LCU_WIDTH-1]) // First compare for LUT if P (and G) is constant\n assign GG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1];\n else\n // Priority \"encoder\" that checks A[i] == 1'b1 && B[i] == 1'b0\n // from MSB down, deferring to less significant bits if the\n // MSBs are equal\n assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);\n (* force_downto *)\n wire [LCU_WIDTH-1:0] P_, G_;\n if (LCU_WIDTH == 1) begin\n // Propagate only if all pairs are equal\n // (inconclusive evidence to say A >= B)\n assign P_ = P[0] & PP;\n // Generate if any comparisons call for it\n assign G_ = G[0] | GG;\n end\n else begin\n // Propagate only if all pairs are equal\n // (inconclusive evidence to say A >= B)\n assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP};\n // Generate if any comparisons call for it\n assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG};\n end\n if (AB_WIDTH == 1)\n $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))\n _TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));\n else\n $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))\n _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));\n end\n end\nendgenerate\nendmodule\n",
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  "cmp2lut.v": "// Certain arithmetic operations between a signal of width n and a constant can be directly mapped\n// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process\n// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often\n// cannot be optimized further.\n//\n// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells\n// with n <= k inputs should be techmapped in this way, because this shortens the critical path\n// from n to 1 by avoiding carry chains.\n\n(* techmap_celltype = \"$lt $le $gt $ge\" *)\nmodule _90_lut_cmp_ (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\n(* force_downto *)\noutput [Y_WIDTH-1:0] Y;\n\nparameter _TECHMAP_CELLTYPE_ = \"\";\n\nparameter _TECHMAP_CONSTMSK_A_ = 0;\nparameter _TECHMAP_CONSTVAL_A_ = 0;\nparameter _TECHMAP_CONSTMSK_B_ = 0;\nparameter _TECHMAP_CONSTVAL_B_ = 0;\n\nfunction automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;\n\tinput integer width;\n\tinput integer operation;\n\tinput integer swap;\n\tinput integer sign;\n\tinput integer operand;\n\tinteger n, i_var, i_cst, lhs, rhs, o_bit;\n\tbegin\n\t\tgen_lut = width'b0;\n\t\tfor (n = 0; n < (1 << width); n++) begin\n\t\t\tif (sign)\n\t\t\t\ti_var = n[width-1:0];\n\t\t\telse\n\t\t\t\ti_var = n;\n\t\t\ti_cst = operand;\n\t\t\tif (swap) begin\n\t\t\t\tlhs = i_cst;\n\t\t\t\trhs = i_var;\n\t\t\tend else begin\n\t\t\t\tlhs = i_var;\n\t\t\t\trhs = i_cst;\n\t\t\tend\n\t\t\tif (operation == 0)\n\t\t\t\to_bit = (lhs < rhs);\n\t\t\tif (operation == 1)\n\t\t\t\to_bit = (lhs <= rhs);\n\t\t\tif (operation == 2)\n\t\t\t\to_bit = (lhs > rhs);\n\t\t\tif (operation == 3)\n\t\t\t\to_bit = (lhs >= rhs);\n\t\t\tgen_lut = gen_lut | (o_bit << n);\n\t\tend\n\tend\nendfunction\n\ngenerate\n\tlocalparam operation =\n\t\t_TECHMAP_CELLTYPE_ == \"$lt\" ? 0 :\n\t\t_TECHMAP_CELLTYPE_ == \"$le\" ? 1 :\n\t\t_TECHMAP_CELLTYPE_ == \"$gt\" ? 2 :\n\t\t_TECHMAP_CELLTYPE_ == \"$ge\" ? 3 :\n\t\t-1;\n\n\tif (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)\n\t\twire _TECHMAP_FAIL_ = 1;\n\telse if (&_TECHMAP_CONSTMSK_B_)\n\t\t\\$lut #(\n\t\t\t.WIDTH(A_WIDTH),\n\t\t\t.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(A),\n\t\t\t.Y(Y)\n\t\t);\n\telse if (&_TECHMAP_CONSTMSK_A_)\n\t\t\\$lut #(\n\t\t\t.WIDTH(B_WIDTH),\n\t\t\t.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(B),\n\t\t\t.Y(Y)\n\t\t);\n\telse\n\t\twire _TECHMAP_FAIL_ = 1;\nendgenerate\n\nendmodule\n",
@@ -96,7 +98,9 @@ export const filesystem = {
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  "brams_map.v": "`define DEF_FUNCS \\\n\tfunction [255:0] init_slice_x8; \\\n\t\tinput integer idx; \\\n\t\tinteger i; \\\n\t\tfor (i = 0; i < 32; i = i + 1) begin \\\n\t\t\tinit_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \\\n\t\tend \\\n\tendfunction \\\n\tfunction [287:0] init_slice_x9; \\\n\t\tinput integer idx; \\\n\t\tinit_slice_x9 = INIT[idx * 288+:288]; \\\n\tendfunction \\\n\n`define x8_width(width) (width / 9 * 8 + width % 9)\n`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}\n`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}\n`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})\n\n\n`define INIT(func) \\\n\t.INIT_RAM_00(func('h00)), \\\n\t.INIT_RAM_01(func('h01)), \\\n\t.INIT_RAM_02(func('h02)), \\\n\t.INIT_RAM_03(func('h03)), \\\n\t.INIT_RAM_04(func('h04)), \\\n\t.INIT_RAM_05(func('h05)), \\\n\t.INIT_RAM_06(func('h06)), \\\n\t.INIT_RAM_07(func('h07)), \\\n\t.INIT_RAM_08(func('h08)), \\\n\t.INIT_RAM_09(func('h09)), \\\n\t.INIT_RAM_0A(func('h0a)), \\\n\t.INIT_RAM_0B(func('h0b)), \\\n\t.INIT_RAM_0C(func('h0c)), \\\n\t.INIT_RAM_0D(func('h0d)), \\\n\t.INIT_RAM_0E(func('h0e)), \\\n\t.INIT_RAM_0F(func('h0f)), \\\n\t.INIT_RAM_10(func('h10)), \\\n\t.INIT_RAM_11(func('h11)), \\\n\t.INIT_RAM_12(func('h12)), \\\n\t.INIT_RAM_13(func('h13)), \\\n\t.INIT_RAM_14(func('h14)), \\\n\t.INIT_RAM_15(func('h15)), \\\n\t.INIT_RAM_16(func('h16)), \\\n\t.INIT_RAM_17(func('h17)), \\\n\t.INIT_RAM_18(func('h18)), \\\n\t.INIT_RAM_19(func('h19)), \\\n\t.INIT_RAM_1A(func('h1a)), \\\n\t.INIT_RAM_1B(func('h1b)), \\\n\t.INIT_RAM_1C(func('h1c)), \\\n\t.INIT_RAM_1D(func('h1d)), \\\n\t.INIT_RAM_1E(func('h1e)), \\\n\t.INIT_RAM_1F(func('h1f)), \\\n\t.INIT_RAM_20(func('h20)), \\\n\t.INIT_RAM_21(func('h21)), \\\n\t.INIT_RAM_22(func('h22)), \\\n\t.INIT_RAM_23(func('h23)), \\\n\t.INIT_RAM_24(func('h24)), \\\n\t.INIT_RAM_25(func('h25)), \\\n\t.INIT_RAM_26(func('h26)), \\\n\t.INIT_RAM_27(func('h27)), \\\n\t.INIT_RAM_28(func('h28)), \\\n\t.INIT_RAM_29(func('h29)), \\\n\t.INIT_RAM_2A(func('h2a)), \\\n\t.INIT_RAM_2B(func('h2b)), \\\n\t.INIT_RAM_2C(func('h2c)), \\\n\t.INIT_RAM_2D(func('h2d)), \\\n\t.INIT_RAM_2E(func('h2e)), \\\n\t.INIT_RAM_2F(func('h2f)), \\\n\t.INIT_RAM_30(func('h30)), \\\n\t.INIT_RAM_31(func('h31)), \\\n\t.INIT_RAM_32(func('h32)), \\\n\t.INIT_RAM_33(func('h33)), \\\n\t.INIT_RAM_34(func('h34)), \\\n\t.INIT_RAM_35(func('h35)), \\\n\t.INIT_RAM_36(func('h36)), \\\n\t.INIT_RAM_37(func('h37)), \\\n\t.INIT_RAM_38(func('h38)), \\\n\t.INIT_RAM_39(func('h39)), \\\n\t.INIT_RAM_3A(func('h3a)), \\\n\t.INIT_RAM_3B(func('h3b)), \\\n\t.INIT_RAM_3C(func('h3c)), \\\n\t.INIT_RAM_3D(func('h3d)), \\\n\t.INIT_RAM_3E(func('h3e)), \\\n\t.INIT_RAM_3F(func('h3f)),\n\nmodule $__GOWIN_SP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 36;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DO);\n\n\tSP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_A_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_A_RD_DATA = DO;\n\n\tSPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(PORT_A_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_DP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;\n\n`DEF_FUNCS\n\nwire RSTA = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire RSTB = OPTION_RESET_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST;\nwire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\nwire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin\n\n\twire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);\n\twire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);\n\twire [15:0] DOA;\n\twire [15:0] DOB;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DOA);\n\tassign PORT_B_RD_DATA = `x8_rd_data(DOB);\n\n\tDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend else begin\n\n\twire [17:0] DIA = PORT_A_WR_DATA;\n\twire [17:0] DIB = PORT_B_WR_DATA;\n\twire [17:0] DOA;\n\twire [17:0] DOB;\n\n\tassign PORT_A_RD_DATA = DOA;\n\tassign PORT_B_RD_DATA = DOB;\n\n\tDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(PORT_A_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_B_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 18;\nparameter PORT_W_WIDTH = 18;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput PORT_W_WR_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST;\nwire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);\nwire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;\n\ngenerate\n\nif (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_R_RD_DATA = `x8_rd_data(DO);\n\n\tSDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_W_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_R_RD_DATA = DO;\n\n\tSDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(PORT_W_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_R_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n",
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  "cells_map.v": "`default_nettype none\n//All DFF* have INIT, but the hardware is always initialised to the reset\n//value regardless. The parameter is ignored.\n\n// DFFN\t\t\t D Flip-Flop with Negative-Edge Clock\nmodule\t\\$_DFF_N_ (input D, C, output Q);\n\tDFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFF\t\t\t D Flip-Flop\nmodule\t\\$_DFF_P_ (input D, C, output Q);\n\tDFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFE\t\t\t D Flip-Flop with Clock Enable\nmodule\t\\$_DFFE_PP_ (input D, C, E, output Q);\n\tDFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNE\t\t D Flip-Flop with Negative-Edge Clock and Clock Enable\nmodule\t\\$_DFFE_NP_ (input D, C, E, output Q);\n\tDFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFR\t\t\t D Flip-Flop with Synchronous Reset\nmodule\t\\$_SDFF_PP0_ (input D, C, R, output Q);\n\tDFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNR\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Reset\nmodule\t\\$_SDFF_NP0_ (input D, C, R, output Q);\n\tDFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFRE\t\t D Flip-Flop with Clock Enable and Synchronous Reset\nmodule\t\\$_SDFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNRE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset\nmodule\t\\$_SDFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFS\t\t\t D Flip-Flop with Synchronous Set\nmodule\t\\$_SDFF_PP1_ (input D, C, R, output Q);\n\tDFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNS\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Set\nmodule\t\\$_SDFF_NP1_ (input D, C, R, output Q);\n\tDFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFSE\t\t D Flip-Flop with Clock Enable and Synchronous Set\nmodule\t\\$_SDFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNSE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set\nmodule\t\\$_SDFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFP\t\t\t D Flip-Flop with Asynchronous Preset\nmodule\t\\$_DFF_PP1_ (input D, C, R, output Q);\n\tDFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNP\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Preset\nmodule\t\\$_DFF_NP1_ (input D, C, R, output Q);\n\tDFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFC\t\t\t D Flip-Flop with Asynchronous Clear\nmodule\t\\$_DFF_PP0_ (input D, C, R, output Q);\n\tDFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNC\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Clear\nmodule\t\\$_DFF_NP0_ (input D, C, R, output Q);\n\tDFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFPE\t\t D Flip-Flop with Clock Enable and Asynchronous Preset\nmodule\t\\$_DFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNPE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset\nmodule\t\\$_DFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFCE\t\t D Flip-Flop with Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNCE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\t\tLUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]));\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tLUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tLUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tLUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\n\t\tend else\n\t\tif (WIDTH == 5) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));\n\t\t\tMUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 6) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));\n\t\t\tMUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 7) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));\n\t\t\tMUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 8) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));\n\t\t\tMUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));\n\t\tend else begin\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\tend\n\tendgenerate\nendmodule\n",
98
100
  "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n specify\n (negedge CLK => (Q : D)) = (480, 660);\n $setup(D, negedge CLK, 576);\n endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n input I, OEN;\n output O;\n assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n input I,OEN;\n output O;\n inout IO;\n assign IO = OEN ? 1'bz : I;\n assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET) ;\n parameter GSREN = \"\";\n parameter LSREN = \"\";\n parameter HWL = \"\";\n parameter TCLK_SOURCE = \"\";\n parameter TXCLK_POL = \"\";\n\n input D0, D1, D2, D3;\n input TX0, TX1;\n input PCLK, FCLK, TCLK, RESET;\n output Q0, Q1;\n\n parameter ID = \"\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR,\nRADDR, CALIB, PCLK, FCLK, ICLK, RESET) ;\nparameter GSREN = \"\";\nparameter LSREN = \"\";\n\ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput CALIB, RESET;\n\noutput Q0,Q1,Q2,Q3;\n\nparameter ID = \"\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG,\nWFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR,\nHOLD, RCLKSEL, PCLK, FCLK, RESET) ;\n input DQSIN,PCLK,FCLK,RESET;\n input [3:0] READ;\n input [2:0] RCLKSEL;\n input [7:0] DLLSTEP;\n input [7:0] WSTEP;\n input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\n\n output DQSR90, DQSW0, DQSW270;\n output [2:0] RPOINT, WPOINT;\n output RVALID,RBURST, RFLAG, WFLAG;\n\n parameter FIFO_MODE_SEL = \"\";\n parameter RD_PNTR = \"\";\n parameter DQS_MODE = \"\";\n parameter HWL = \"\";\n parameter GSREN = \"\";\n parameter ID = \"\";\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox, keep *)\nmodule GSR (input GSRI);\nendmodule\n\n(* blackbox, keep *)\nmodule BANDGAP (input BGEN);\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0 => COUT) = (1010, 1380);\n\t(I1 => COUT) = (1021, 1505);\n\t(I3 => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = I0 & I1;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\"; // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\"; // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nparameter DCS_MODE = \"RISING\";\nendmodule\n\n(* blackbox *)\nmodule EMCU (\n input FCLK,\n input PORESETN,\n input SYSRESETN,\n input RTCSRCCLK,\n output [15:0] IOEXPOUTPUTO,\n output [15:0] IOEXPOUTPUTENO,\n input [15:0] IOEXPINPUTI,\n output UART0TXDO,\n output UART1TXDO,\n output UART0BAUDTICK,\n output UART1BAUDTICK,\n input UART0RXDI,\n input UART1RXDI,\n output INTMONITOR,\n output MTXHRESETN,\n output [12:0] SRAM0ADDR,\n output [3:0] SRAM0WREN,\n output [31:0] SRAM0WDATA,\n output SRAM0CS,\n input [31:0] SRAM0RDATA,\n output TARGFLASH0HSEL,\n output [28:0] TARGFLASH0HADDR,\n output [1:0] TARGFLASH0HTRANS,\n output [2:0] TARGFLASH0HSIZE,\n output [2:0] TARGFLASH0HBURST,\n output TARGFLASH0HREADYMUX,\n input [31:0] TARGFLASH0HRDATA,\n input [2:0] TARGFLASH0HRUSER,\n input TARGFLASH0HRESP,\n input TARGFLASH0EXRESP,\n input TARGFLASH0HREADYOUT,\n output TARGEXP0HSEL,\n output [31:0] TARGEXP0HADDR,\n output [1:0] TARGEXP0HTRANS,\n output TARGEXP0HWRITE,\n output [2:0] TARGEXP0HSIZE,\n output [2:0] TARGEXP0HBURST,\n output [3:0] TARGEXP0HPROT,\n output [1:0] TARGEXP0MEMATTR,\n output TARGEXP0EXREQ,\n output [3:0] TARGEXP0HMASTER,\n output [31:0] TARGEXP0HWDATA,\n output TARGEXP0HMASTLOCK,\n output TARGEXP0HREADYMUX,\n output TARGEXP0HAUSER,\n output [3:0] TARGEXP0HWUSER,\n input [31:0] TARGEXP0HRDATA,\n input TARGEXP0HREADYOUT,\n input TARGEXP0HRESP,\n input TARGEXP0EXRESP,\n input [2:0] TARGEXP0HRUSER,\n output [31:0] INITEXP0HRDATA,\n output INITEXP0HREADY,\n output INITEXP0HRESP,\n output INITEXP0EXRESP,\n output [2:0] INITEXP0HRUSER,\n input INITEXP0HSEL,\n input [31:0] INITEXP0HADDR,\n input [1:0] INITEXP0HTRANS,\n input INITEXP0HWRITE,\n input [2:0] INITEXP0HSIZE,\n input [2:0] INITEXP0HBURST,\n input [3:0] INITEXP0HPROT,\n input [1:0] INITEXP0MEMATTR,\n input INITEXP0EXREQ,\n input [3:0] INITEXP0HMASTER,\n input [31:0] INITEXP0HWDATA,\n input INITEXP0HMASTLOCK,\n input INITEXP0HAUSER,\n input [3:0] INITEXP0HWUSER,\n output [3:0] APBTARGEXP2PSTRB,\n output [2:0] APBTARGEXP2PPROT,\n output APBTARGEXP2PSEL,\n output APBTARGEXP2PENABLE,\n output [11:0] APBTARGEXP2PADDR,\n output APBTARGEXP2PWRITE,\n output [31:0] APBTARGEXP2PWDATA,\n input [31:0] APBTARGEXP2PRDATA,\n input APBTARGEXP2PREADY,\n input APBTARGEXP2PSLVERR,\n input [3:0] MTXREMAP,\n output DAPTDO,\n output DAPJTAGNSW,\n output DAPNTDOEN,\n input DAPSWDITMS,\n input DAPTDI,\n input DAPNTRST,\n input DAPSWCLKTCK,\n output [3:0] TPIUTRACEDATA,\n output TPIUTRACECLK,\n input [4:0] GPINT,\n input FLASHERR,\n input FLASHINT\n\n );\nendmodule\n\n\n",
99
- "cells_xtra.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n \t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule FLASH128K (...);\ninput [31:0] DIN;\ninput [14:0] ADDR;\ninput CS,AE,OE;\ninput PCLK;\ninput PROG, SERA, MASE;\ninput NVSTR;\ninput IFREN;\ninput RESETN;\noutput [31:0] DOUT;\noutput TBIT;\nparameter IDLE = 4'd0,\n READ_S1 = 4'd1,\n READ_S2 = 4'd2,\n PROG_S1 = 4'd3,\n PROG_S2 = 4'd4,\n PROG_S3 = 4'd5,\n PROG_S4 = 4'd6,\n SERA_S1 = 4'd7,\n SERA_S2 = 4'd8,\n SERA_S3 = 4'd9,\n SERA_S4 = 4'd10,\n MASE_S1 = 4'd11,\n MASE_S2 = 4'd12,\n MASE_S3 = 4'd13,\n MASE_S4 = 4'd14;\nendmodule\n\nmodule MCU (...);\nendmodule\n\nmodule USB20_PHY (...);\nparameter DATABUS16_8 = 1'b0;\nparameter ADP_PRBEN = 1'b0;\nparameter TEST_MODE = 5'b00000;\nparameter HSDRV1 = 1'b0; \nparameter HSDRV0 = 1'b0; \nparameter CLK_SEL = 1'b0;\nparameter M = 4'b0000; \nparameter N = 6'b101000; \nparameter C = 2'b01; \nparameter FOC_LOCK = 1'b0;\ninput [15:0] DATAIN;\ninput TXVLD;\ninput TXVLDH;\ninput RESET;\ninput SUSPENDM;\ninput [1:0] XCVRSEL;\ninput TERMSEL;\ninput [1:0] OPMODE;\noutput [15:0] DATAOUT;\noutput TXREADY;\noutput RXACTIVE;\noutput RXVLD;\noutput RXVLDH;\noutput CLK; \noutput RXERROR;\ninout DP;\ninout DM;\noutput [1:0] LINESTATE;\ninput IDPULLUP;\ninput DPPD;\ninput DMPD;\ninput CHARGVBUS;\ninput DISCHARGVBUS;\ninput TXBITSTUFFEN;\ninput TXBITSTUFFENH;\ninput TXENN;\ninput TXDAT;\ninput TXSE0;\ninput FSLSSERIAL;\noutput HOSTDIS;\noutput IDDIG;\noutput ADPPRB;\noutput ADPSNS;\noutput SESSVLD;\noutput VBUSVLD;\noutput RXDP;\noutput RXDM;\noutput RXRCV;\noutput LBKERR;\noutput CLKRDY;\ninput INTCLK;\ninout ID;\ninout VBUS;\ninout REXT;\ninput XIN;\ninout XOUT;\ninput\tTEST;\noutput\tCLK480PAD;\ninput SCANCLK; \ninput SCANEN; \ninput SCANMODE; \ninput TRESETN; \ninput SCANIN1; \noutput SCANOUT1; \ninput SCANIN2; \noutput SCANOUT2; \ninput SCANIN3; \noutput SCANOUT3; \ninput SCANIN4; \noutput SCANOUT4; \ninput SCANIN5; \noutput SCANOUT5; \ninput SCANIN6; \noutput SCANOUT6; \nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK; \ninput HS_8BIT_MODE; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput LALIGN_EN; \ninput WALIGN_BY; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN; \ninput HSRX_STOP; \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON; \ninput RESET; \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH; \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ; \ninput DRST_N; \ninput ONE_BYTE0_MATCH; \ninput WORD_LENDIAN; \ninput [2:0] FIFO_RD_STD; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b1;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n",
101
+ "cells_xtra_gw1n.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\nendmodule\n\nmodule ELVDS_IBUF_MIPI (...);\noutput OH, OL;\ninput I, IB;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule TLVDS_OEN_BK (...);\ninput OEN;\nparameter OEN_BANK = \"0\"; \nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n \t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK; \ninput HS_8BIT_MODE; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput LALIGN_EN; \ninput WALIGN_BY; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN; \ninput HSRX_STOP; \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON; \ninput RESET; \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH; \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ; \ninput DRST_N; \ninput ONE_BYTE0_MATCH; \ninput WORD_LENDIAN; \ninput [2:0] FIFO_RD_STD; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b0;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule PWRGRD (...);\ninput PDEN; \nendmodule\n",
102
+ "cells_xtra_gw2a.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IDDR_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, ICLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET;\noutput Q0,Q1;\nendmodule\n\n\nmodule ODDR_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1;\ninput TX, PCLK, TCLK, RESET;\noutput Q0, Q1;\nendmodule\n\n\nmodule IDES4_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET,CALIB;\noutput Q0,Q1,Q2,Q3;\nendmodule\n\n\nmodule IDES8_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET,CALIB;\noutput Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7;\nendmodule\n\n\nmodule OSER4_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \nparameter HWL = \"false\"; \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3;\ninput TX0, TX1;\ninput PCLK, FCLK, TCLK, RESET;\noutput Q0, Q1;\nendmodule\n\n\nmodule OSER8_MEM (...);\nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \nparameter HWL = \"false\"; \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3, D4, D5, D6, D7;\ninput TX0, TX1, TX2, TX3;\ninput PCLK, FCLK, TCLK, RESET;\noutput Q0, Q1;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW2A-18\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DQS (...);\ninput DQSIN,PCLK,FCLK,RESET;\ninput [3:0] READ;\ninput [2:0] RCLKSEL;\ninput [7:0] DLLSTEP;\ninput [7:0] WSTEP;\ninput RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\noutput DQSR90, DQSW0, DQSW270; \noutput [2:0] RPOINT, WPOINT;\noutput RVALID,RBURST, RFLAG, WFLAG;\nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IBUF_R (...);\ninput I;\ninput RTEN;\noutput O;\nendmodule\n\nmodule IOBUF_R (...);\ninput I,OEN;\ninput RTEN;\noutput O;\ninout IO;\nendmodule\n\nmodule ELVDS_IBUF_R (...);\noutput O;\ninput I, IB;\ninput RTEN;\nendmodule\n\nmodule ELVDS_IOBUF_R (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\ninput RTEN;\nendmodule\n\nmodule OTP (...);\ninput CSB, SCLK;\noutput DOUT;\nendmodule\n\nmodule SAMB (...);\ninput [23:0] SPIAD;\ninput LOADN_SPIAD;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule ELVDS_IBUF_MIPI (...);\noutput OH, OL;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n",
103
+ "cells_xtra_gw5a.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, GE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, GE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSEN, HSREN;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\ninout IO, IOB;\ninput OEN, OENB;\nendmodule\n\nmodule ELVDS_IOBUF_R (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\ninput RTEN;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule TLVDS_IBUF_ADC (...);\ninput I, IB;\ninput ADCEN;\nendmodule\n\nmodule MIPI_CPHY_IBUF (...);\noutput OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2;\ninout IO0, IOB0, IO1, IOB1, IO2, IOB2;\ninput I0, IB0, I1, IB1, I2, IB2;\ninput OEN, OENB;\ninput HSEN;\nendmodule\n\nmodule MIPI_CPHY_OBUF (...);\noutput O0, OB0, O1, OB1, O2, OB2;\ninput I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2;\ninout IO0, IOB0, IO1, IOB1, IO2, IOB2;\ninput OEN, OENB, MODESEL, VCOME;\nendmodule\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDP36KE (...);\nparameter ECC_WRITE_EN=\"TRUE\"; \nparameter ECC_READ_EN=\"TRUE\"; \nparameter READ_MODE = 1'b0; \nparameter BLK_SEL_A = 3'b000;\nparameter BLK_SEL_B = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_FILE = \"NONE\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INITP_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESET; \ninput [8:0] ADA, ADB;\ninput [63:0] DI;\ninput [7:0] DIP;\ninput [2:0] BLKSELA, BLKSELB;\ninput DECCI, SECCI;\noutput [63:0] DO;\noutput [7:0] DOP;\noutput DECCO, SECCO;\noutput [7:0] ECCP;\nendmodule\n\n\nmodule SDP136K (...);\ninput CLKA, CLKB;\ninput WE, RE;\ninput [10:0] ADA, ADB;\ninput [67:0] DI;\noutput [67:0] DO;\nendmodule\n\nmodule MULTADDALU12X12 (...);\nparameter A0REG_CLK = \"BYPASS\"; \nparameter A0REG_CE = \"CE0\"; \nparameter A0REG_RESET = \"RESET0\"; \nparameter A1REG_CLK = \"BYPASS\"; \nparameter A1REG_CE = \"CE0\"; \nparameter A1REG_RESET = \"RESET0\"; \nparameter B0REG_CLK = \"BYPASS\"; \nparameter B0REG_CE = \"CE0\"; \nparameter B0REG_RESET = \"RESET0\"; \nparameter B1REG_CLK = \"BYPASS\"; \nparameter B1REG_CE = \"CE0\"; \nparameter B1REG_RESET = \"RESET0\"; \nparameter ACCSEL_IREG_CLK = \"BYPASS\"; \nparameter ACCSEL_IREG_CE = \"CE0\"; \nparameter ACCSEL_IREG_RESET = \"RESET0\"; \nparameter CASISEL_IREG_CLK = \"BYPASS\"; \nparameter CASISEL_IREG_CE = \"CE0\"; \nparameter CASISEL_IREG_RESET = \"RESET0\"; \nparameter ADDSUB0_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_IREG_CE = \"CE0\"; \nparameter ADDSUB0_IREG_RESET = \"RESET0\"; \nparameter ADDSUB1_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_IREG_CE = \"CE0\"; \nparameter ADDSUB1_IREG_RESET = \"RESET0\"; \nparameter PREG0_CLK = \"BYPASS\"; \nparameter PREG0_CE = \"CE0\"; \nparameter PREG0_RESET = \"RESET0\"; \nparameter PREG1_CLK = \"BYPASS\"; \nparameter PREG1_CE = \"CE0\"; \nparameter PREG1_RESET = \"RESET0\"; \nparameter FB_PREG_EN = \"FALSE\"; \nparameter ACCSEL_PREG_CLK = \"BYPASS\"; \nparameter ACCSEL_PREG_CE = \"CE0\"; \nparameter ACCSEL_PREG_RESET = \"RESET0\"; \nparameter CASISEL_PREG_CLK = \"BYPASS\"; \nparameter CASISEL_PREG_CE = \"CE0\"; \nparameter CASISEL_PREG_RESET = \"RESET0\"; \nparameter ADDSUB0_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_PREG_CE = \"CE0\"; \nparameter ADDSUB0_PREG_RESET = \"RESET0\"; \nparameter ADDSUB1_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_PREG_CE = \"CE0\"; \nparameter ADDSUB1_PREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter PRE_LOAD = 48'h000000000000;\nparameter DYN_ADD_SUB_0 = \"FALSE\";\nparameter ADD_SUB_0 = 1'b0;\nparameter DYN_ADD_SUB_1 = \"FALSE\";\nparameter ADD_SUB_1 = 1'b0;\nparameter DYN_CASI_SEL = \"FALSE\";\nparameter CASI_SEL = 1'b0;\nparameter DYN_ACC_SEL = \"FALSE\";\nparameter ACC_SEL = 1'b0;\noutput [47:0] DOUT, CASO;\ninput [11:0] A0, B0, A1, B1;\ninput [47:0] CASI;\ninput ACCSEL;\ninput CASISEL;\ninput [1:0] ADDSUB;\ninput [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULTALU27X18 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter DREG_CLK = \"BYPASS\"; \nparameter DREG_CE = \"CE0\"; \nparameter DREG_RESET = \"RESET0\"; \nparameter C_IREG_CLK = \"BYPASS\"; \nparameter C_IREG_CE = \"CE0\"; \nparameter C_IREG_RESET = \"RESET0\"; \nparameter PSEL_IREG_CLK = \"BYPASS\"; \nparameter PSEL_IREG_CE = \"CE0\"; \nparameter PSEL_IREG_RESET = \"RESET0\"; \nparameter PADDSUB_IREG_CLK = \"BYPASS\"; \nparameter PADDSUB_IREG_CE = \"CE0\"; \nparameter PADDSUB_IREG_RESET = \"RESET0\"; \nparameter ADDSUB0_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_IREG_CE = \"CE0\"; \nparameter ADDSUB0_IREG_RESET = \"RESET0\"; \nparameter ADDSUB1_IREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_IREG_CE = \"CE0\"; \nparameter ADDSUB1_IREG_RESET = \"RESET0\"; \nparameter CSEL_IREG_CLK = \"BYPASS\"; \nparameter CSEL_IREG_CE = \"CE0\"; \nparameter CSEL_IREG_RESET = \"RESET0\"; \nparameter CASISEL_IREG_CLK = \"BYPASS\"; \nparameter CASISEL_IREG_CE = \"CE0\"; \nparameter CASISEL_IREG_RESET = \"RESET0\"; \nparameter ACCSEL_IREG_CLK = \"BYPASS\"; \nparameter ACCSEL_IREG_CE = \"CE0\"; \nparameter ACCSEL_IREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter ADDSUB0_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB0_PREG_CE = \"CE0\"; \nparameter ADDSUB0_PREG_RESET = \"RESET0\"; \nparameter ADDSUB1_PREG_CLK = \"BYPASS\"; \nparameter ADDSUB1_PREG_CE = \"CE0\"; \nparameter ADDSUB1_PREG_RESET = \"RESET0\"; \nparameter CSEL_PREG_CLK = \"BYPASS\"; \nparameter CSEL_PREG_CE = \"CE0\"; \nparameter CSEL_PREG_RESET = \"RESET0\"; \nparameter CASISEL_PREG_CLK = \"BYPASS\"; \nparameter CASISEL_PREG_CE = \"CE0\"; \nparameter CASISEL_PREG_RESET = \"RESET0\"; \nparameter ACCSEL_PREG_CLK = \"BYPASS\"; \nparameter ACCSEL_PREG_CE = \"CE0\"; \nparameter ACCSEL_PREG_RESET = \"RESET0\"; \nparameter C_PREG_CLK = \"BYPASS\"; \nparameter C_PREG_CE = \"CE0\"; \nparameter C_PREG_RESET = \"RESET0\"; \nparameter FB_PREG_EN = \"FALSE\"; \nparameter SOA_PREG_EN = \"FALSE\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter PRE_LOAD = 48'h000000000000;\nparameter DYN_P_SEL = \"FALSE\";\nparameter P_SEL = 1'b0;\nparameter DYN_P_ADDSUB = \"FALSE\";\nparameter P_ADDSUB = 1'b0;\nparameter DYN_A_SEL = \"FALSE\";\nparameter A_SEL = 1'b0;\nparameter DYN_ADD_SUB_0 = \"FALSE\";\nparameter ADD_SUB_0 = 1'b0;\nparameter DYN_ADD_SUB_1 = \"FALSE\";\nparameter ADD_SUB_1 = 1'b0;\nparameter DYN_C_SEL = \"FALSE\";\nparameter C_SEL = 1'b1;\nparameter DYN_CASI_SEL = \"FALSE\";\nparameter CASI_SEL = 1'b0;\nparameter DYN_ACC_SEL = \"FALSE\";\nparameter ACC_SEL = 1'b0;\nparameter MULT12X12_EN = \"FALSE\";\noutput [47:0] DOUT, CASO;\noutput [26:0] SOA;\ninput [26:0] A, SIA;\ninput [17:0] B;\ninput [47:0] C;\ninput [25:0] D;\ninput [47:0] CASI;\ninput ACCSEL;\ninput PSEL;\ninput ASEL;\ninput PADDSUB;\ninput CSEL, CASISEL;\ninput [1:0] ADDSUB;\ninput [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULT12X12 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\noutput [23:0] DOUT;\ninput [11:0] A, B;\ninput [1:0] CLK, CE, RESET;\nendmodule\n\nmodule MULT27X36 (...);\nparameter AREG_CLK = \"BYPASS\"; \nparameter AREG_CE = \"CE0\"; \nparameter AREG_RESET = \"RESET0\"; \nparameter BREG_CLK = \"BYPASS\"; \nparameter BREG_CE = \"CE0\"; \nparameter BREG_RESET = \"RESET0\"; \nparameter DREG_CLK = \"BYPASS\"; \nparameter DREG_CE = \"CE0\"; \nparameter DREG_RESET = \"RESET0\"; \nparameter PADDSUB_IREG_CLK = \"BYPASS\"; \nparameter PADDSUB_IREG_CE = \"CE0\"; \nparameter PADDSUB_IREG_RESET = \"RESET0\"; \nparameter PREG_CLK = \"BYPASS\"; \nparameter PREG_CE = \"CE0\"; \nparameter PREG_RESET = \"RESET0\"; \nparameter PSEL_IREG_CLK = \"BYPASS\"; \nparameter PSEL_IREG_CE = \"CE0\"; \nparameter PSEL_IREG_RESET = \"RESET0\"; \nparameter OREG_CLK = \"BYPASS\"; \nparameter OREG_CE = \"CE0\"; \nparameter OREG_RESET = \"RESET0\"; \nparameter MULT_RESET_MODE = \"SYNC\";\nparameter DYN_P_SEL = \"FALSE\";\nparameter P_SEL = 1'b0;\nparameter DYN_P_ADDSUB = \"FALSE\";\nparameter P_ADDSUB = 1'b0;\noutput [62:0] DOUT;\ninput [26:0] A;\ninput [35:0] B;\ninput [25:0] D;\ninput [1:0] CLK, CE, RESET;\ninput PSEL;\ninput PADDSUB;\nendmodule\n\nmodule MULTACC (...);\noutput [23:0] DATAO, CASO;\ninput CE, CLK;\ninput [5:0] COFFIN0, COFFIN1, COFFIN2;\ninput [9:0] DATAIN0, DATAIN1;\ninput [9:0] DATAIN2;\ninput RSTN;\ninput [23:0] CASI;\nparameter COFFIN_WIDTH = 4; \nparameter DATAIN_WIDTH = 8; \nparameter IREG = 1'b0; \nparameter OREG = 1'b0; \nparameter PREG = 1'b0; \nparameter ACC_EN = \"FALSE\"; \nparameter CASI_EN = \"FALSE\"; \nparameter CASO_EN = \"FALSE\"; \nendmodule\n\nmodule IDDR_MEM (...);\ninput D, ICLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput RESET;\noutput Q0,Q1;\nendmodule\n\n\nmodule ODDR_MEM (...);\nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1;\ninput TX, PCLK, TCLK, RESET;\noutput Q0, Q1;\nendmodule\n\n\nmodule IDES4_MEM (...);\ninput PCLK, D, ICLK, FCLK, RESET, CALIB;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\noutput Q0,Q1,Q2,Q3;\nendmodule\n\n\nmodule IDES8_MEM (...);\ninput PCLK, D, ICLK, FCLK, RESET, CALIB;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\noutput Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;\nendmodule\n\n\nmodule IDES14 (...);\ninput D, FCLK, PCLK, CALIB,RESET;\noutput Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13;\nendmodule\n\n\nmodule IDES32 (...);\ninput D, FCLK, PCLK, CALIB,RESET;\noutput Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31;\nendmodule\n\n\nmodule OSER4_MEM (...);\nparameter HWL = \"false\"; \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3;\ninput TX0, TX1;\ninput PCLK, FCLK, TCLK, RESET;\noutput Q0, Q1;\nendmodule\n\n\nmodule OSER8_MEM (...);\nparameter HWL = \"false\"; \nparameter TCLK_SOURCE = \"DQSW\"; \nparameter TXCLK_POL = 1'b0; \ninput D0, D1, D2, D3, D4, D5, D6, D7;\ninput TX0, TX1, TX2, TX3;\ninput PCLK, FCLK, TCLK, RESET;\noutput Q0, Q1;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DLY_EN = \"FALSE\";\nparameter ADAPT_EN = \"FALSE\";\ninput DI;\ninput SDTAP;\ninput VALUE;\ninput [7:0] DLYSTEP;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule OSIDES32 (...);\noutput [31:0] Q;\ninput D;\ninput PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;\ninput RESET;\noutput DF0, DF1;\ninput SDTAP0, SDTAP1;\ninput VALUE0,VALUE1;\ninput [7:0] DLYSTEP0,DLYSTEP1;\nparameter C_STATIC_DLY_0 = 0; \nparameter DYN_DLY_EN_0 = \"FALSE\";\nparameter ADAPT_EN_0 = \"FALSE\";\nparameter C_STATIC_DLY_1 = 0; \nparameter DYN_DLY_EN_1 = \"FALSE\";\nparameter ADAPT_EN_1 = \"FALSE\";\nendmodule\n\nmodule OSIDES64 (...);\noutput [63:0] Q;\ninput D;\ninput PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;\ninput RESET;\noutput DF0, DF1, DF2, DF3;\ninput SDTAP0, SDTAP1, SDTAP2, SDTAP3;\ninput VALUE0, VALUE1, VALUE2, VALUE3;\ninput [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3;\nparameter C_STATIC_DLY_0 = 0; \nparameter DYN_DLY_EN_0 = \"FALSE\";\nparameter ADAPT_EN_0 = \"FALSE\";\nparameter C_STATIC_DLY_1 = 0; \nparameter DYN_DLY_EN_1 = \"FALSE\";\nparameter ADAPT_EN_1 = \"FALSE\";\nparameter C_STATIC_DLY_2 = 0; \nparameter DYN_DLY_EN_2 = \"FALSE\";\nparameter ADAPT_EN_2 = \"FALSE\";\nparameter C_STATIC_DLY_3 = 0; \nparameter DYN_DLY_EN_3 = \"FALSE\";\nparameter ADAPT_EN_3 = \"FALSE\";\nendmodule\n\nmodule DCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule DDRDLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = \"FALSE\";\nparameter CODESCAL = \"000\";\nparameter SCAL_EN = \"TRUE\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP, CSTEP;\ninput LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nparameter DYN_DLY_EN = \"FALSE\";\nparameter ADAPT_EN = \"FALSE\";\nparameter STEP_SEL = 1'b0;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nendmodule\n\nmodule CLKDIV2 (...);\ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DHCE (...);\ninput CLKIN;\ninput CEN;\noutput CLKOUT;\nendmodule\n\nmodule OSCA (...);\nparameter FREQ_DIV = 100; \noutput OSCOUT;\ninput OSCEN;\nendmodule\n\nmodule OSCB (...);\nparameter FREQ_MODE = \"25\"; \nparameter FREQ_DIV = 10; \nparameter DYN_TRIM_EN = \"FALSE\"; \noutput OSCOUT;\noutput OSCREF;\ninput OSCEN, FMODE;\ninput [7:0] RTRIM;\ninput [5:0] RTCTRIM; \nendmodule\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput PLLPWD;\ninput RESET_I;\ninput RESET_O;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] MDSEL;\ninput [2:0] MDSEL_FRAC;\ninput [6:0] ODSEL0;\ninput [2:0] ODSEL0_FRAC;\ninput [6:0] ODSEL1;\ninput [6:0] ODSEL2;\ninput [6:0] ODSEL3;\ninput [6:0] ODSEL4;\ninput [6:0] ODSEL5;\ninput [6:0] ODSEL6;\ninput [3:0] DT0,DT1,DT2,DT3;\ninput [5:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] LPFCAP;\ninput [2:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLK0;\ninput ENCLK1;\ninput ENCLK2;\ninput ENCLK3;\ninput ENCLK4;\ninput ENCLK5;\ninput ENCLK6;\ninput SSCPOL;\ninput SSCON;\ninput [6:0] SSCMDSEL;\ninput [2:0] SSCMDSEL_FRAC;\noutput LOCK;\noutput CLKOUT0;\noutput CLKOUT1;\noutput CLKOUT2;\noutput CLKOUT3;\noutput CLKOUT4;\noutput CLKOUT5;\noutput CLKOUT6;\noutput CLKFBOUT;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 1; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 1; \nparameter DYN_ODIV0_SEL= \"FALSE\";\nparameter ODIV0_SEL = 8; \nparameter DYN_ODIV1_SEL= \"FALSE\";\nparameter ODIV1_SEL = 8; \nparameter DYN_ODIV2_SEL= \"FALSE\";\nparameter ODIV2_SEL = 8; \nparameter DYN_ODIV3_SEL= \"FALSE\";\nparameter ODIV3_SEL = 8; \nparameter DYN_ODIV4_SEL= \"FALSE\";\nparameter ODIV4_SEL = 8; \nparameter DYN_ODIV5_SEL= \"FALSE\";\nparameter ODIV5_SEL = 8; \nparameter DYN_ODIV6_SEL= \"FALSE\";\nparameter ODIV6_SEL = 8; \nparameter DYN_MDIV_SEL= \"FALSE\";\nparameter MDIV_SEL = 8; \nparameter MDIV_FRAC_SEL = 0; \nparameter ODIV0_FRAC_SEL = 0; \nparameter CLKOUT0_EN = \"TRUE\";\nparameter CLKOUT1_EN = \"FALSE\";\nparameter CLKOUT2_EN = \"FALSE\";\nparameter CLKOUT3_EN = \"FALSE\";\nparameter CLKOUT4_EN = \"FALSE\";\nparameter CLKOUT5_EN = \"FALSE\";\nparameter CLKOUT6_EN = \"FALSE\";\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DT0_SEL = \"FALSE\"; \nparameter DYN_DT1_SEL = \"FALSE\"; \nparameter DYN_DT2_SEL = \"FALSE\"; \nparameter DYN_DT3_SEL = \"FALSE\"; \nparameter CLKOUT0_DT_DIR = 1'b1; \nparameter CLKOUT1_DT_DIR = 1'b1; \nparameter CLKOUT2_DT_DIR = 1'b1; \nparameter CLKOUT3_DT_DIR = 1'b1; \nparameter CLKOUT0_DT_STEP = 0; \nparameter CLKOUT1_DT_STEP = 0; \nparameter CLKOUT2_DT_STEP = 0; \nparameter CLKOUT3_DT_STEP = 0; \nparameter CLK0_IN_SEL = 1'b0;\nparameter CLK0_OUT_SEL = 1'b0;\nparameter CLK1_IN_SEL = 1'b0;\nparameter CLK1_OUT_SEL = 1'b0;\nparameter CLK2_IN_SEL = 1'b0;\nparameter CLK2_OUT_SEL = 1'b0;\nparameter CLK3_IN_SEL = 1'b0;\nparameter CLK3_OUT_SEL = 1'b0;\nparameter CLK4_IN_SEL = 2'b00;\nparameter CLK4_OUT_SEL = 1'b0;\nparameter CLK5_IN_SEL = 1'b0;\nparameter CLK5_OUT_SEL = 1'b0;\nparameter CLK6_IN_SEL = 1'b0;\nparameter CLK6_OUT_SEL = 1'b0;\nparameter DYN_DPA_EN = \"FALSE\";\nparameter CLKOUT0_PE_COARSE = 0;\nparameter CLKOUT0_PE_FINE = 0;\nparameter CLKOUT1_PE_COARSE = 0;\nparameter CLKOUT1_PE_FINE = 0;\nparameter CLKOUT2_PE_COARSE = 0;\nparameter CLKOUT2_PE_FINE = 0;\nparameter CLKOUT3_PE_COARSE = 0;\nparameter CLKOUT3_PE_FINE = 0;\nparameter CLKOUT4_PE_COARSE = 0;\nparameter CLKOUT4_PE_FINE = 0;\nparameter CLKOUT5_PE_COARSE = 0;\nparameter CLKOUT5_PE_FINE = 0;\nparameter CLKOUT6_PE_COARSE = 0;\nparameter CLKOUT6_PE_FINE = 0;\nparameter DYN_PE0_SEL = \"FALSE\";\nparameter DYN_PE1_SEL = \"FALSE\";\nparameter DYN_PE2_SEL = \"FALSE\";\nparameter DYN_PE3_SEL = \"FALSE\";\nparameter DYN_PE4_SEL = \"FALSE\";\nparameter DYN_PE5_SEL = \"FALSE\";\nparameter DYN_PE6_SEL = \"FALSE\";\nparameter DE0_EN = \"FALSE\";\nparameter DE1_EN = \"FALSE\";\nparameter DE2_EN = \"FALSE\";\nparameter DE3_EN = \"FALSE\";\nparameter DE4_EN = \"FALSE\";\nparameter DE5_EN = \"FALSE\";\nparameter DE6_EN = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_O_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 6'bXXXXXX;\nparameter DYN_LPF_SEL= \"FALSE\";\nparameter LPF_RES = 3'bXXX;\nparameter LPF_CAP = 2'b00;\nparameter SSC_EN = \"FALSE\";\nendmodule\n\nmodule PLLA (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput PLLPWD;\ninput RESET_I;\ninput RESET_O;\ninput [2:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput SSCPOL;\ninput SSCON;\ninput [6:0] SSCMDSEL;\ninput [2:0] SSCMDSEL_FRAC;\ninput MDCLK;\ninput [1:0] MDOPC;\ninput MDAINC;\ninput [7:0] MDWDI;\noutput [7:0] MDRDO;\noutput LOCK;\noutput CLKOUT0;\noutput CLKOUT1;\noutput CLKOUT2;\noutput CLKOUT3;\noutput CLKOUT4;\noutput CLKOUT5;\noutput CLKOUT6;\noutput CLKFBOUT;\nparameter FCLKIN = \"100.0\"; \nparameter IDIV_SEL = 1; \nparameter FBDIV_SEL = 1; \nparameter ODIV0_SEL = 8; \nparameter ODIV1_SEL = 8; \nparameter ODIV2_SEL = 8; \nparameter ODIV3_SEL = 8; \nparameter ODIV4_SEL = 8; \nparameter ODIV5_SEL = 8; \nparameter ODIV6_SEL = 8; \nparameter MDIV_SEL = 8; \nparameter MDIV_FRAC_SEL = 0; \nparameter ODIV0_FRAC_SEL = 0; \nparameter CLKOUT0_EN = \"TRUE\";\nparameter CLKOUT1_EN = \"FALSE\";\nparameter CLKOUT2_EN = \"FALSE\";\nparameter CLKOUT3_EN = \"FALSE\";\nparameter CLKOUT4_EN = \"FALSE\";\nparameter CLKOUT5_EN = \"FALSE\";\nparameter CLKOUT6_EN = \"FALSE\";\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter CLKOUT0_DT_DIR = 1'b1; \nparameter CLKOUT1_DT_DIR = 1'b1; \nparameter CLKOUT2_DT_DIR = 1'b1; \nparameter CLKOUT3_DT_DIR = 1'b1; \nparameter CLKOUT0_DT_STEP = 0; \nparameter CLKOUT1_DT_STEP = 0; \nparameter CLKOUT2_DT_STEP = 0; \nparameter CLKOUT3_DT_STEP = 0; \nparameter CLK0_IN_SEL = 1'b0;\nparameter CLK0_OUT_SEL = 1'b0;\nparameter CLK1_IN_SEL = 1'b0;\nparameter CLK1_OUT_SEL = 1'b0;\nparameter CLK2_IN_SEL = 1'b0;\nparameter CLK2_OUT_SEL = 1'b0;\nparameter CLK3_IN_SEL = 1'b0;\nparameter CLK3_OUT_SEL = 1'b0;\nparameter CLK4_IN_SEL = 2'b00;\nparameter CLK4_OUT_SEL = 1'b0;\nparameter CLK5_IN_SEL = 1'b0;\nparameter CLK5_OUT_SEL = 1'b0;\nparameter CLK6_IN_SEL = 1'b0;\nparameter CLK6_OUT_SEL = 1'b0;\nparameter DYN_DPA_EN = \"FALSE\";\nparameter CLKOUT0_PE_COARSE = 0;\nparameter CLKOUT0_PE_FINE = 0;\nparameter CLKOUT1_PE_COARSE = 0;\nparameter CLKOUT1_PE_FINE = 0;\nparameter CLKOUT2_PE_COARSE = 0;\nparameter CLKOUT2_PE_FINE = 0;\nparameter CLKOUT3_PE_COARSE = 0;\nparameter CLKOUT3_PE_FINE = 0;\nparameter CLKOUT4_PE_COARSE = 0;\nparameter CLKOUT4_PE_FINE = 0;\nparameter CLKOUT5_PE_COARSE = 0;\nparameter CLKOUT5_PE_FINE = 0;\nparameter CLKOUT6_PE_COARSE = 0;\nparameter CLKOUT6_PE_FINE = 0;\nparameter DYN_PE0_SEL = \"FALSE\";\nparameter DYN_PE1_SEL = \"FALSE\";\nparameter DYN_PE2_SEL = \"FALSE\";\nparameter DYN_PE3_SEL = \"FALSE\";\nparameter DYN_PE4_SEL = \"FALSE\";\nparameter DYN_PE5_SEL = \"FALSE\";\nparameter DYN_PE6_SEL = \"FALSE\";\nparameter DE0_EN = \"FALSE\";\nparameter DE1_EN = \"FALSE\";\nparameter DE2_EN = \"FALSE\";\nparameter DE3_EN = \"FALSE\";\nparameter DE4_EN = \"FALSE\";\nparameter DE5_EN = \"FALSE\";\nparameter DE6_EN = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_O_EN = \"FALSE\";\nparameter ICP_SEL = 6'bXXXXXX;\nparameter LPF_RES = 3'bXXX;\nparameter LPF_CAP = 2'b00;\nparameter SSC_EN = \"FALSE\";\nendmodule\n\nmodule AE350_SOC (...);\ninput POR_N;\ninput HW_RSTN;\ninput CORE_CLK;\ninput DDR_CLK;\ninput AHB_CLK;\ninput APB_CLK;\ninput DBG_TCK;\ninput RTC_CLK;\ninput CORE_CE;\ninput AXI_CE;\ninput DDR_CE;\ninput AHB_CE;\ninput [7:0] APB_CE;\ninput APB2AHB_CE;\ninput SCAN_TEST;\ninput SCAN_EN;\noutput PRESETN;\noutput HRESETN;\noutput DDR_RSTN;\ninput [15:0] GP_INT;\ninput [ 7:0] DMA_REQ;\noutput [ 7:0] DMA_ACK;\noutput CORE0_WFI_MODE;\ninput WAKEUP_IN; \noutput RTC_WAKEUP; \ninput TEST_CLK;\ninput TEST_MODE;\ninput TEST_RSTN;\noutput [31:0] ROM_HADDR;\ninput [31:0] ROM_HRDATA;\ninput ROM_HREADY;\ninput ROM_HRESP;\noutput [1:0] ROM_HTRANS;\noutput ROM_HWRITE;\noutput [31:0] APB_PADDR;\noutput APB_PENABLE;\ninput [31:0] APB_PRDATA;\ninput APB_PREADY;\noutput APB_PSEL;\noutput [31:0] APB_PWDATA;\noutput APB_PWRITE;\ninput APB_PSLVERR;\noutput [2:0] APB_PPROT;\noutput [3:0] APB_PSTRB;\ninput [31:0] EXTS_HRDATA;\ninput EXTS_HREADYIN;\ninput EXTS_HRESP;\noutput [31:0] EXTS_HADDR;\noutput [2:0] EXTS_HBURST;\noutput [3:0] EXTS_HPROT;\noutput EXTS_HSEL;\noutput [2:0] EXTS_HSIZE;\noutput [1:0] EXTS_HTRANS;\noutput [31:0] EXTS_HWDATA;\noutput EXTS_HWRITE;\ninput [31:0] EXTM_HADDR;\ninput [2:0] EXTM_HBURST;\ninput [3:0] EXTM_HPROT;\noutput [63:0] EXTM_HRDATA;\ninput EXTM_HREADY;\noutput EXTM_HREADYOUT;\noutput EXTM_HRESP;\ninput EXTM_HSEL;\ninput [2:0] EXTM_HSIZE;\ninput [1:0] EXTM_HTRANS;\ninput [63:0] EXTM_HWDATA;\ninput EXTM_HWRITE;\noutput [31:0] DDR_HADDR;\noutput [2:0] DDR_HBURST;\noutput [3:0] DDR_HPROT;\ninput [63:0] DDR_HRDATA;\ninput DDR_HREADY;\ninput DDR_HRESP;\noutput [2:0] DDR_HSIZE;\noutput [1:0] DDR_HTRANS;\noutput [63:0] DDR_HWDATA;\noutput DDR_HWRITE;\ninput TMS_IN; \ninput TRST_IN;\ninput TDI_IN;\noutput TDO_OUT;\noutput TDO_OE;\ninput SPI2_HOLDN_IN;\ninput SPI2_WPN_IN;\ninput SPI2_CLK_IN;\ninput SPI2_CSN_IN;\ninput SPI2_MISO_IN;\ninput SPI2_MOSI_IN;\noutput SPI2_HOLDN_OUT;\noutput SPI2_HOLDN_OE;\noutput SPI2_WPN_OUT;\noutput SPI2_WPN_OE;\noutput SPI2_CLK_OUT;\noutput SPI2_CLK_OE;\noutput SPI2_CSN_OUT;\noutput SPI2_CSN_OE;\noutput SPI2_MISO_OUT;\noutput SPI2_MISO_OE;\noutput SPI2_MOSI_OUT;\noutput SPI2_MOSI_OE;\ninput I2C_SCL_IN;\ninput I2C_SDA_IN;\noutput I2C_SCL;\noutput I2C_SDA;\noutput UART1_TXD;\noutput UART1_RTSN;\ninput UART1_RXD;\ninput UART1_CTSN;\ninput UART1_DSRN;\ninput UART1_DCDN;\ninput UART1_RIN;\noutput UART1_DTRN;\noutput UART1_OUT1N;\noutput UART1_OUT2N;\noutput UART2_TXD;\noutput UART2_RTSN;\ninput UART2_RXD;\ninput UART2_CTSN;\ninput UART2_DCDN;\ninput UART2_DSRN;\ninput UART2_RIN;\noutput UART2_DTRN;\noutput UART2_OUT1N;\noutput UART2_OUT2N;\noutput CH0_PWM;\noutput CH0_PWMOE;\noutput CH1_PWM;\noutput CH1_PWMOE;\noutput CH2_PWM;\noutput CH2_PWMOE;\noutput CH3_PWM;\noutput CH3_PWMOE;\ninput [31:0] GPIO_IN;\noutput [31:0] GPIO_OE;\noutput [31:0] GPIO_OUT;\ninput\t [19:0]\tSCAN_IN;\ninput\t\tINTEG_TCK;\ninput\t\tINTEG_TDI;\ninput\t\tINTEG_TMS;\ninput\t\tINTEG_TRST;\noutput\t\tINTEG_TDO;\noutput [19:0]\tSCAN_OUT;\ninput\t\tPGEN_CHAIN_I;\noutput\t\tPRDYN_CHAIN_O;\ninput\t[2:0]\tEMA;\ninput\t[1:0]\tEMAW;\ninput\t\tEMAS;\ninput\t\tRET1N;\ninput\t\tRET2N;\nendmodule\n\nmodule AE350_RAM (...);\ninput POR_N;\ninput HW_RSTN;\ninput CORE_CLK;\ninput AHB_CLK;\ninput APB_CLK;\ninput RTC_CLK;\ninput CORE_CE;\ninput AXI_CE;\ninput AHB_CE;\ninput [31:0] EXTM_HADDR;\ninput [2:0] EXTM_HBURST;\ninput [3:0] EXTM_HPROT;\noutput [63:0] EXTM_HRDATA;\ninput EXTM_HREADY;\noutput EXTM_HREADYOUT;\noutput EXTM_HRESP;\ninput EXTM_HSEL;\ninput [2:0] EXTM_HSIZE;\ninput [1:0] EXTM_HTRANS;\ninput [63:0] EXTM_HWDATA;\ninput EXTM_HWRITE;\ninput\t[2:0]\tEMA;\ninput\t[1:0]\tEMAW;\ninput\t\tEMAS;\ninput\t\tRET1N;\ninput\t\tRET2N;\nendmodule\n\nmodule SAMB (...);\nparameter MODE = 2'b00; \ninput [23:0] SPIAD;\ninput LOAD;\ninput ADWSEL; \nendmodule\n\nmodule OTP (...);\nparameter MODE = 2'b01; \ninput CLK, READ, SHIFT;\noutput DOUT;\nendmodule\n\nmodule CMSER (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [27:0] ERRLOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERRINJECT;\ninput [6:0] ERRINJLOC;\nendmodule\n\nmodule CMSERA (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [26:0] ERR0LOC;\noutput [26:0] ERR1LOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERR0INJECT,ERR1INJECT;\ninput [6:0] ERRINJ0LOC,ERRINJ1LOC;\nendmodule\n\nmodule CMSERB (...);\noutput RUNNING;\noutput CRCERR;\noutput CRCDONE;\noutput ECCCORR;\noutput ECCUNCORR; \noutput [12:0] ERRLOC;\noutput ECCDEC;\noutput DSRRD;\noutput DSRWR; \noutput ASRRESET;\noutput ASRINC;\noutput REFCLK;\ninput CLK;\ninput [2:0] SEREN;\ninput ERR0INJECT,ERR1INJECT;\ninput [6:0] ERRINJ0LOC,ERRINJ1LOC;\nendmodule\n\nmodule SAMBA (...);\nparameter MODE = 2'b00; \ninput SPIAD;\ninput LOAD;\nendmodule\n\nmodule ADCLRC (...);\nendmodule\n\nmodule ADCULC (...);\nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput D0LN_DESKEW_DONE,D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE;\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput BYTE_LENDIAN; \ninput [2:0] FIFO_RD_STD; \ninput HSRX_STOP; \ninput PWRON; \ninput RESET; \ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput DESKEW_BY,DESKEW_EN_OEDGE;\ninput [5:0] DESKEW_HALF_OPENING;\ninput [2:0] DESKEW_LNSEL; \ninput [1:0] DESKEW_LSB_MODE;\ninput [2:0] DESKEW_M;\ninput [12:0] DESKEW_MTH; \ninput [6:0] DESKEW_MSET;\ninput DESKEW_OCLKEDG_EN;\ninput [6:0] DESKEW_OWVAL;\ninput DESKEW_REQ; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput DRST_N; \ninput [2:0] EQCS_LANE0,EQCS_LANE1,EQCS_LANE2,EQCS_LANE3,EQCS_CK;\ninput [2:0] EQRS_LANE0,EQRS_LANE1,EQRS_LANE2,EQRS_LANE3,EQRS_CK;\ninput HS_8BIT_MODE; \ninput HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1,HSRX_DLYDIR_LANE2,HSRX_DLYDIR_LANE3,HSRX_DLYDIR_CK;\ninput HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1,HSRX_DLYLDN_LANE2,HSRX_DLYLDN_LANE3,HSRX_DLYLDN_CK;\ninput HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,HSRX_DLYMV_LANE2,HSRX_DLYMV_LANE3,HSRX_DLYMV_CK;\ninput HSRX_EN_CK; \ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput LALIGN_EN; \ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput ONE_BYTE0_MATCH; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput WALIGN_BY; \ninput WALIGN_DVLD;\ninput WORD_LENDIAN; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter EN_CLKB1X = 1'b1;\nparameter EQ_ADPSEL_LANE0 = 1'b0;\nparameter EQ_ADPSEL_LANE1 = 1'b0;\nparameter EQ_ADPSEL_LANE2 = 1'b0;\nparameter EQ_ADPSEL_LANE3 = 1'b0;\nparameter EQ_ADPSEL_CK = 1'b0;\nparameter EQ_CS_LANE0 = 3'b100;\nparameter EQ_CS_LANE1 = 3'b100;\nparameter EQ_CS_LANE2 = 3'b100;\nparameter EQ_CS_LANE3 = 3'b100;\nparameter EQ_CS_CK = 3'b100;\nparameter EQ_PBIAS_LANE0 = 4'b0100;\nparameter EQ_PBIAS_LANE1 = 4'b0100;\nparameter EQ_PBIAS_LANE2 = 4'b0100;\nparameter EQ_PBIAS_LANE3 = 4'b0100;\nparameter EQ_PBIAS_CK = 4'b0100;\nparameter EQ_RS_LANE0 = 3'b100;\nparameter EQ_RS_LANE1 = 3'b100;\nparameter EQ_RS_LANE2 = 3'b100;\nparameter EQ_RS_LANE3 = 3'b100;\nparameter EQ_RS_CK = 3'b100;\nparameter EQ_ZLD_LANE0 = 4'b1000;\nparameter EQ_ZLD_LANE1 = 4'b1000;\nparameter EQ_ZLD_LANE2 = 4'b1000;\nparameter EQ_ZLD_LANE3 = 4'b1000;\nparameter EQ_ZLD_CK = 4'b1000;\nparameter HIGH_BW_LANE0 = 1'b1;\nparameter HIGH_BW_LANE1 = 1'b1;\nparameter HIGH_BW_LANE2 = 1'b1;\nparameter HIGH_BW_LANE3 = 1'b1;\nparameter HIGH_BW_CK = 1'b1;\nparameter HSRX_DLYCTL_CK = 7'b0000000;\nparameter HSRX_DLYCTL_LANE0 = 7'b0000000;\nparameter HSRX_DLYCTL_LANE1 = 7'b0000000;\nparameter HSRX_DLYCTL_LANE2 = 7'b0000000;\nparameter HSRX_DLYCTL_LANE3 = 7'b0000000;\nparameter HSRX_DLY_SEL = 1'b0;\nparameter HSRX_DUTY_LANE0 = 4'b1000;\nparameter HSRX_DUTY_LANE1 = 4'b1000;\nparameter HSRX_DUTY_LANE2 = 4'b1000;\nparameter HSRX_DUTY_LANE3 = 4'b1000;\nparameter HSRX_DUTY_CK = 4'b1000;\nparameter HSRX_EN = 1'b1;\nparameter HSRX_EQ_EN_LANE0 = 1'b1;\nparameter HSRX_EQ_EN_LANE1 = 1'b1;\nparameter HSRX_EQ_EN_LANE2 = 1'b1;\nparameter HSRX_EQ_EN_LANE3 = 1'b1;\nparameter HSRX_EQ_EN_CK = 1'b1;\nparameter HSRX_IBIAS = 4'b0011;\nparameter HSRX_IMARG_EN = 1'b1;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter HSRX_ODT_EN = 1'b1;\nparameter HSRX_ODT_TST = 4'b0000;\nparameter HSRX_ODT_TST_CK = 1'b0;\nparameter HSRX_STOP_EN = 1'b0;\nparameter HSRX_TST = 4'b0000;\nparameter HSRX_TST_CK = 1'b0;\nparameter HSRX_WAIT4EDGE = 1'b0;\nparameter HYST_NCTL = 2'b01;\nparameter HYST_PCTL = 2'b01;\nparameter LOW_LPRX_VTH = 1'b0;\nparameter LPRX_EN = 1'b1;\nparameter LPRX_TST = 4'b0000;\nparameter LPRX_TST_CK = 1'b0;\nparameter LPTX_EN = 1'b1;\nparameter LPTX_SW_LANE0 = 3'b100;\nparameter LPTX_SW_LANE1 = 3'b100;\nparameter LPTX_SW_LANE2 = 3'b100;\nparameter LPTX_SW_LANE3 = 3'b100;\nparameter LPTX_SW_CK = 3'b100;\nparameter LPTX_TST = 4'b0000;\nparameter LPTX_TST_CK = 1'b0;\nparameter MIPI_DIS_N = 1'b1;\nparameter PGA_BIAS_LANE0 = 4'b1000;\nparameter PGA_BIAS_LANE1 = 4'b1000;\nparameter PGA_BIAS_LANE2 = 4'b1000;\nparameter PGA_BIAS_LANE3 = 4'b1000;\nparameter PGA_BIAS_CK = 4'b1000;\nparameter PGA_GAIN_LANE0 = 4'b1000;\nparameter PGA_GAIN_LANE1 = 4'b1000;\nparameter PGA_GAIN_LANE2 = 4'b1000;\nparameter PGA_GAIN_LANE3 = 4'b1000;\nparameter PGA_GAIN_CK = 4'b1000;\nparameter RX_CLK1X_SYNC_SEL = 1'b0;\nparameter RX_ODT_TRIM_LANE0 = 4'b0111;\nparameter RX_ODT_TRIM_LANE1 = 4'b0111;\nparameter RX_ODT_TRIM_LANE2 = 4'b0111;\nparameter RX_ODT_TRIM_LANE3 = 4'b0111;\nparameter RX_ODT_TRIM_CK = 4'b0111;\nparameter STP_UNIT = 2'b00;\nparameter SYNC_CLK_SEL = 1'b1;\nparameter WALIGN_DVLD_SRC_SEL = 1'b0;\nendmodule\n\nmodule MIPI_DPHY (...);\noutput RX_CLK_O, TX_CLK_O;\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;\ninout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;\ninput HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK;\ninput PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;\ninput TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;\ninput [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;\ninput HSTXD_VLD;\ninput CK0, CK90, CK180, CK270;\ninput DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;\ninput HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK;\ninput RX_DRST_N, TX_DRST_N, WALIGN_DVLD;\noutput [7:0] MRDATA;\ninput MA_INC, MCLK;\ninput [1:0] MOPCODE;\ninput [7:0] MWDATA;\noutput ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;\noutput D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;\noutput D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;\ninput D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;\ninput HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;\ninput HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;\ninput HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;\ninput ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;\nparameter TX_PLLCLK = \"NONE\"; \nparameter RX_ALIGN_BYTE = 8'b10111000 ; \nparameter RX_HS_8BIT_MODE = 1'b0 ; \nparameter RX_LANE_ALIGN_EN = 1'b0 ; \nparameter TX_HS_8BIT_MODE = 1'b0 ; \nparameter HSREG_EN_LN0 = 1'b0; \nparameter HSREG_EN_LN1 = 1'b0; \nparameter HSREG_EN_LN2 = 1'b0; \nparameter HSREG_EN_LN3 = 1'b0; \nparameter HSREG_EN_LNCK = 1'b0; \nparameter LANE_DIV_SEL = 2'b00; \nparameter HSRX_EN = 1'b1 ; \nparameter HSRX_LANESEL = 4'b1111 ; \nparameter HSRX_LANESEL_CK = 1'b1 ; \nparameter HSTX_EN_LN0 = 1'b0 ; \nparameter HSTX_EN_LN1 = 1'b0 ; \nparameter HSTX_EN_LN2 = 1'b0 ; \nparameter HSTX_EN_LN3 = 1'b0 ; \nparameter HSTX_EN_LNCK = 1'b0 ; \nparameter LPTX_EN_LN0 = 1'b1 ; \nparameter LPTX_EN_LN1 = 1'b1 ; \nparameter LPTX_EN_LN2 = 1'b1 ; \nparameter LPTX_EN_LN3 = 1'b1 ; \nparameter LPTX_EN_LNCK = 1'b1 ; \nparameter TXDP_EN_LN0 = 1'b0 ; \nparameter TXDP_EN_LN1 = 1'b0 ; \nparameter TXDP_EN_LN2 = 1'b0 ; \nparameter TXDP_EN_LN3 = 1'b0 ; \nparameter TXDP_EN_LNCK = 1'b0 ;\nparameter CKLN_DELAY_EN = 1'b0; \nparameter CKLN_DELAY_OVR_VAL = 7'b0000000; \nparameter D0LN_DELAY_EN = 1'b0; \nparameter D0LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D0LN_DESKEW_BYPASS = 1'b0; \nparameter D1LN_DELAY_EN = 1'b0; \nparameter D1LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D1LN_DESKEW_BYPASS = 1'b0; \nparameter D2LN_DELAY_EN = 1'b0; \nparameter D2LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D2LN_DESKEW_BYPASS = 1'b0; \nparameter D3LN_DELAY_EN = 1'b0; \nparameter D3LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D3LN_DESKEW_BYPASS = 1'b0; \nparameter DESKEW_EN_LOW_DELAY = 1'b0; \nparameter DESKEW_EN_ONE_EDGE = 1'b0; \nparameter DESKEW_FAST_LOOP_TIME = 4'b0000; \nparameter DESKEW_FAST_MODE = 1'b0; \nparameter DESKEW_HALF_OPENING = 6'b010110; \nparameter DESKEW_LSB_MODE = 2'b00; \nparameter DESKEW_M = 3'b011; \nparameter DESKEW_M_TH = 13'b0000110100110; \nparameter DESKEW_MAX_SETTING = 7'b0100001; \nparameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; \nparameter DESKEW_RST_BYPASS = 1'b0 ; \nparameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; \nparameter RX_CLK_1X_SYNC_SEL = 1'b0 ; \nparameter RX_INVERT = 1'b0 ; \nparameter RX_ONE_BYTE0_MATCH = 1'b0 ; \nparameter RX_RD_START_DEPTH = 5'b00001; \nparameter RX_SYNC_MODE = 1'b0 ; \nparameter RX_WORD_ALIGN_BYPASS = 1'b0 ; \nparameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; \nparameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; \nparameter TX_BYPASS_MODE = 1'b0 ; \nparameter TX_BYTECLK_SYNC_MODE = 1'b0 ; \nparameter TX_OCLK_USE_CIBCLK = 1'b0 ; \nparameter TX_RD_START_DEPTH = 5'b00001; \nparameter TX_SYNC_MODE = 1'b0 ; \nparameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; \nparameter EQ_CS_LANE0 = 3'b100; \nparameter EQ_CS_LANE1 = 3'b100; \nparameter EQ_CS_LANE2 = 3'b100; \nparameter EQ_CS_LANE3 = 3'b100; \nparameter EQ_CS_LANECK = 3'b100; \nparameter EQ_RS_LANE0 = 3'b100; \nparameter EQ_RS_LANE1 = 3'b100; \nparameter EQ_RS_LANE2 = 3'b100; \nparameter EQ_RS_LANE3 = 3'b100; \nparameter EQ_RS_LANECK = 3'b100; \nparameter HSCLK_LANE_LN0 = 1'b0; \nparameter HSCLK_LANE_LN1 = 1'b0; \nparameter HSCLK_LANE_LN2 = 1'b0; \nparameter HSCLK_LANE_LN3 = 1'b0; \nparameter HSCLK_LANE_LNCK = 1'b1; \nparameter ALP_ED_EN_LANE0 = 1'b1 ; \nparameter ALP_ED_EN_LANE1 = 1'b1 ; \nparameter ALP_ED_EN_LANE2 = 1'b1 ; \nparameter ALP_ED_EN_LANE3 = 1'b1 ; \nparameter ALP_ED_EN_LANECK = 1'b1 ; \nparameter ALP_ED_TST_LANE0 = 1'b0 ; \nparameter ALP_ED_TST_LANE1 = 1'b0 ; \nparameter ALP_ED_TST_LANE2 = 1'b0 ; \nparameter ALP_ED_TST_LANE3 = 1'b0 ; \nparameter ALP_ED_TST_LANECK = 1'b0 ; \nparameter ALP_EN_LN0 = 1'b0 ; \nparameter ALP_EN_LN1 = 1'b0 ; \nparameter ALP_EN_LN2 = 1'b0 ; \nparameter ALP_EN_LN3 = 1'b0 ; \nparameter ALP_EN_LNCK = 1'b0 ; \nparameter ALP_HYS_EN_LANE0 = 1'b1 ; \nparameter ALP_HYS_EN_LANE1 = 1'b1 ; \nparameter ALP_HYS_EN_LANE2 = 1'b1 ; \nparameter ALP_HYS_EN_LANE3 = 1'b1 ; \nparameter ALP_HYS_EN_LANECK = 1'b1 ; \nparameter ALP_TH_LANE0 = 4'b1000 ; \nparameter ALP_TH_LANE1 = 4'b1000 ; \nparameter ALP_TH_LANE2 = 4'b1000 ; \nparameter ALP_TH_LANE3 = 4'b1000 ; \nparameter ALP_TH_LANECK = 4'b1000 ; \nparameter ANA_BYTECLK_PH = 2'b00 ; \nparameter BIT_REVERSE_LN0 = 1'b0 ; \nparameter BIT_REVERSE_LN1 = 1'b0 ; \nparameter BIT_REVERSE_LN2 = 1'b0 ; \nparameter BIT_REVERSE_LN3 = 1'b0 ; \nparameter BIT_REVERSE_LNCK = 1'b0 ; \nparameter BYPASS_TXHCLKEN = 1'b1 ; \nparameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; \nparameter BYTE_CLK_POLAR = 1'b0 ; \nparameter BYTE_REVERSE_LN0 = 1'b0 ; \nparameter BYTE_REVERSE_LN1 = 1'b0 ; \nparameter BYTE_REVERSE_LN2 = 1'b0 ; \nparameter BYTE_REVERSE_LN3 = 1'b0 ; \nparameter BYTE_REVERSE_LNCK = 1'b0 ; \nparameter EN_CLKB1X = 1'b1 ; \nparameter EQ_PBIAS_LANE0 = 4'b1000 ; \nparameter EQ_PBIAS_LANE1 = 4'b1000 ; \nparameter EQ_PBIAS_LANE2 = 4'b1000 ; \nparameter EQ_PBIAS_LANE3 = 4'b1000 ; \nparameter EQ_PBIAS_LANECK = 4'b1000 ; \nparameter EQ_ZLD_LANE0 = 4'b1000 ; \nparameter EQ_ZLD_LANE1 = 4'b1000 ; \nparameter EQ_ZLD_LANE2 = 4'b1000 ; \nparameter EQ_ZLD_LANE3 = 4'b1000 ; \nparameter EQ_ZLD_LANECK = 4'b1000 ; \nparameter HIGH_BW_LANE0 = 1'b1 ; \nparameter HIGH_BW_LANE1 = 1'b1 ; \nparameter HIGH_BW_LANE2 = 1'b1 ; \nparameter HIGH_BW_LANE3 = 1'b1 ; \nparameter HIGH_BW_LANECK = 1'b1 ; \nparameter HSREG_VREF_CTL = 3'b100 ; \nparameter HSREG_VREF_EN = 1'b1 ; \nparameter HSRX_DLY_CTL_CK = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; \nparameter HSRX_DLY_SEL_LANE0 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANE1 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANE2 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANE3 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANECK = 1'b0 ; \nparameter HSRX_DUTY_LANE0 = 4'b1000 ; \nparameter HSRX_DUTY_LANE1 = 4'b1000 ; \nparameter HSRX_DUTY_LANE2 = 4'b1000 ; \nparameter HSRX_DUTY_LANE3 = 4'b1000 ; \nparameter HSRX_DUTY_LANECK = 4'b1000 ; \nparameter HSRX_EQ_EN_LANE0 = 1'b1 ; \nparameter HSRX_EQ_EN_LANE1 = 1'b1 ; \nparameter HSRX_EQ_EN_LANE2 = 1'b1 ; \nparameter HSRX_EQ_EN_LANE3 = 1'b1 ; \nparameter HSRX_EQ_EN_LANECK = 1'b1 ; \nparameter HSRX_IBIAS = 4'b0011 ; \nparameter HSRX_IBIAS_TEST_EN = 1'b0 ; \nparameter HSRX_IMARG_EN = 1'b0 ; \nparameter HSRX_ODT_EN = 1'b1 ; \nparameter HSRX_ODT_TST = 4'b0000 ; \nparameter HSRX_ODT_TST_CK = 1'b0 ; \nparameter HSRX_SEL = 4'b0000 ; \nparameter HSRX_STOP_EN = 1'b0 ; \nparameter HSRX_TST = 4'b0000 ; \nparameter HSRX_TST_CK = 1'b0 ; \nparameter HSRX_WAIT4EDGE = 1'b1 ; \nparameter HYST_NCTL = 2'b01 ; \nparameter HYST_PCTL = 2'b01 ; \nparameter IBIAS_TEST_EN = 1'b0 ; \nparameter LB_CH_SEL = 1'b0 ; \nparameter LB_EN_LN0 = 1'b0 ; \nparameter LB_EN_LN1 = 1'b0 ; \nparameter LB_EN_LN2 = 1'b0 ; \nparameter LB_EN_LN3 = 1'b0 ; \nparameter LB_EN_LNCK = 1'b0 ; \nparameter LB_POLAR_LN0 = 1'b0 ; \nparameter LB_POLAR_LN1 = 1'b0 ; \nparameter LB_POLAR_LN2 = 1'b0 ; \nparameter LB_POLAR_LN3 = 1'b0 ; \nparameter LB_POLAR_LNCK = 1'b0 ; \nparameter LOW_LPRX_VTH = 1'b0 ; \nparameter LPBK_DATA2TO1 = 4'b0000; \nparameter LPBK_DATA2TO1_CK = 1'b0 ; \nparameter LPBK_EN = 1'b0 ; \nparameter LPBK_SEL = 4'b0000; \nparameter LPBKTST_EN = 4'b0000; \nparameter LPBKTST_EN_CK = 1'b0 ; \nparameter LPRX_EN = 1'b1 ; \nparameter LPRX_TST = 4'b0000; \nparameter LPRX_TST_CK = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN0 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN1 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN2 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN3 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LNCK = 1'b0 ; \nparameter LPTX_NIMP_LN0 = 3'b100 ; \nparameter LPTX_NIMP_LN1 = 3'b100 ; \nparameter LPTX_NIMP_LN2 = 3'b100 ; \nparameter LPTX_NIMP_LN3 = 3'b100 ; \nparameter LPTX_NIMP_LNCK = 3'b100 ; \nparameter LPTX_PIMP_LN0 = 3'b100 ; \nparameter LPTX_PIMP_LN1 = 3'b100 ; \nparameter LPTX_PIMP_LN2 = 3'b100 ; \nparameter LPTX_PIMP_LN3 = 3'b100 ; \nparameter LPTX_PIMP_LNCK = 3'b100 ; \nparameter MIPI_PMA_DIS_N = 1'b1 ; \nparameter PGA_BIAS_LANE0 = 4'b1000 ; \nparameter PGA_BIAS_LANE1 = 4'b1000 ; \nparameter PGA_BIAS_LANE2 = 4'b1000 ; \nparameter PGA_BIAS_LANE3 = 4'b1000 ; \nparameter PGA_BIAS_LANECK = 4'b1000 ; \nparameter PGA_GAIN_LANE0 = 4'b1000 ; \nparameter PGA_GAIN_LANE1 = 4'b1000 ; \nparameter PGA_GAIN_LANE2 = 4'b1000 ; \nparameter PGA_GAIN_LANE3 = 4'b1000 ; \nparameter PGA_GAIN_LANECK = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE0 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE1 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE2 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE3 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANECK = 4'b1000 ; \nparameter SLEWN_CTL_LN0 = 4'b1111 ; \nparameter SLEWN_CTL_LN1 = 4'b1111 ; \nparameter SLEWN_CTL_LN2 = 4'b1111 ; \nparameter SLEWN_CTL_LN3 = 4'b1111 ; \nparameter SLEWN_CTL_LNCK = 4'b1111 ; \nparameter SLEWP_CTL_LN0 = 4'b1111 ; \nparameter SLEWP_CTL_LN1 = 4'b1111 ; \nparameter SLEWP_CTL_LN2 = 4'b1111 ; \nparameter SLEWP_CTL_LN3 = 4'b1111 ; \nparameter SLEWP_CTL_LNCK = 4'b1111 ; \nparameter STP_UNIT = 2'b01 ; \nparameter TERMN_CTL_LN0 = 4'b1000 ; \nparameter TERMN_CTL_LN1 = 4'b1000 ; \nparameter TERMN_CTL_LN2 = 4'b1000 ; \nparameter TERMN_CTL_LN3 = 4'b1000 ; \nparameter TERMN_CTL_LNCK = 4'b1000 ; \nparameter TERMP_CTL_LN0 = 4'b1000 ; \nparameter TERMP_CTL_LN1 = 4'b1000 ; \nparameter TERMP_CTL_LN2 = 4'b1000 ; \nparameter TERMP_CTL_LN3 = 4'b1000 ; \nparameter TERMP_CTL_LNCK = 4'b1000 ; \nparameter TEST_EN_LN0 = 1'b0 ; \nparameter TEST_EN_LN1 = 1'b0 ; \nparameter TEST_EN_LN2 = 1'b0 ; \nparameter TEST_EN_LN3 = 1'b0 ; \nparameter TEST_EN_LNCK = 1'b0 ; \nparameter TEST_N_IMP_LN0 = 1'b0 ; \nparameter TEST_N_IMP_LN1 = 1'b0 ; \nparameter TEST_N_IMP_LN2 = 1'b0 ; \nparameter TEST_N_IMP_LN3 = 1'b0 ; \nparameter TEST_N_IMP_LNCK = 1'b0 ; \nparameter TEST_P_IMP_LN0 = 1'b0 ; \nparameter TEST_P_IMP_LN1 = 1'b0 ; \nparameter TEST_P_IMP_LN2 = 1'b0 ; \nparameter TEST_P_IMP_LN3 = 1'b0 ; \nparameter TEST_P_IMP_LNCK = 1'b0 ; \nendmodule\n\nmodule MIPI_DPHYA (...);\noutput RX_CLK_O, TX_CLK_O;\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;\ninout CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;\ninput HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK;\ninput PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;\ninput TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;\ninput [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;\ninput HSTXD_VLD;\ninput CK0, CK90, CK180, CK270;\ninput DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;\ninput HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK;\ninput RX_DRST_N, TX_DRST_N, WALIGN_DVLD;\noutput [7:0] MRDATA;\ninput MA_INC, MCLK;\ninput [1:0] MOPCODE;\ninput [7:0] MWDATA;\ninput SPLL_CKN, SPLL_CKP;\noutput ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;\noutput D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;\noutput D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;\ninput D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;\ninput HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;\ninput HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;\ninput HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;\ninput ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;\nparameter TX_PLLCLK = \"NONE\"; \nparameter RX_ALIGN_BYTE = 8'b10111000 ; \nparameter RX_HS_8BIT_MODE = 1'b0 ; \nparameter RX_LANE_ALIGN_EN = 1'b0 ; \nparameter TX_HS_8BIT_MODE = 1'b0 ; \nparameter HSREG_EN_LN0 = 1'b0; \nparameter HSREG_EN_LN1 = 1'b0; \nparameter HSREG_EN_LN2 = 1'b0; \nparameter HSREG_EN_LN3 = 1'b0; \nparameter HSREG_EN_LNCK = 1'b0; \nparameter LANE_DIV_SEL = 2'b00; \nparameter HSRX_EN = 1'b1 ; \nparameter HSRX_LANESEL = 4'b1111 ; \nparameter HSRX_LANESEL_CK = 1'b1 ; \nparameter HSTX_EN_LN0 = 1'b0 ; \nparameter HSTX_EN_LN1 = 1'b0 ; \nparameter HSTX_EN_LN2 = 1'b0 ; \nparameter HSTX_EN_LN3 = 1'b0 ; \nparameter HSTX_EN_LNCK = 1'b0 ; \nparameter LPTX_EN_LN0 = 1'b1 ; \nparameter LPTX_EN_LN1 = 1'b1 ; \nparameter LPTX_EN_LN2 = 1'b1 ; \nparameter LPTX_EN_LN3 = 1'b1 ; \nparameter LPTX_EN_LNCK = 1'b1 ; \nparameter TXDP_EN_LN0 = 1'b0 ; \nparameter TXDP_EN_LN1 = 1'b0 ; \nparameter TXDP_EN_LN2 = 1'b0 ; \nparameter TXDP_EN_LN3 = 1'b0 ; \nparameter TXDP_EN_LNCK = 1'b0 ;\nparameter SPLL_DIV_SEL = 2'b00;\nparameter DPHY_CK_SEL = 2'b01;\nparameter CKLN_DELAY_EN = 1'b0; \nparameter CKLN_DELAY_OVR_VAL = 7'b0000000; \nparameter D0LN_DELAY_EN = 1'b0; \nparameter D0LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D0LN_DESKEW_BYPASS = 1'b0; \nparameter D1LN_DELAY_EN = 1'b0; \nparameter D1LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D1LN_DESKEW_BYPASS = 1'b0; \nparameter D2LN_DELAY_EN = 1'b0; \nparameter D2LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D2LN_DESKEW_BYPASS = 1'b0; \nparameter D3LN_DELAY_EN = 1'b0; \nparameter D3LN_DELAY_OVR_VAL = 7'b0000000; \nparameter D3LN_DESKEW_BYPASS = 1'b0; \nparameter DESKEW_EN_LOW_DELAY = 1'b0; \nparameter DESKEW_EN_ONE_EDGE = 1'b0; \nparameter DESKEW_FAST_LOOP_TIME = 4'b0000; \nparameter DESKEW_FAST_MODE = 1'b0; \nparameter DESKEW_HALF_OPENING = 6'b010110; \nparameter DESKEW_LSB_MODE = 2'b00; \nparameter DESKEW_M = 3'b011; \nparameter DESKEW_M_TH = 13'b0000110100110; \nparameter DESKEW_MAX_SETTING = 7'b0100001; \nparameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; \nparameter DESKEW_RST_BYPASS = 1'b0 ; \nparameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; \nparameter RX_CLK_1X_SYNC_SEL = 1'b0 ; \nparameter RX_INVERT = 1'b0 ; \nparameter RX_ONE_BYTE0_MATCH = 1'b0 ; \nparameter RX_RD_START_DEPTH = 5'b00001; \nparameter RX_SYNC_MODE = 1'b0 ; \nparameter RX_WORD_ALIGN_BYPASS = 1'b0 ; \nparameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; \nparameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; \nparameter TX_BYPASS_MODE = 1'b0 ; \nparameter TX_BYTECLK_SYNC_MODE = 1'b0 ; \nparameter TX_OCLK_USE_CIBCLK = 1'b0 ; \nparameter TX_RD_START_DEPTH = 5'b00001; \nparameter TX_SYNC_MODE = 1'b0 ; \nparameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; \nparameter EQ_CS_LANE0 = 3'b100; \nparameter EQ_CS_LANE1 = 3'b100; \nparameter EQ_CS_LANE2 = 3'b100; \nparameter EQ_CS_LANE3 = 3'b100; \nparameter EQ_CS_LANECK = 3'b100; \nparameter EQ_RS_LANE0 = 3'b100; \nparameter EQ_RS_LANE1 = 3'b100; \nparameter EQ_RS_LANE2 = 3'b100; \nparameter EQ_RS_LANE3 = 3'b100; \nparameter EQ_RS_LANECK = 3'b100; \nparameter HSCLK_LANE_LN0 = 1'b0; \nparameter HSCLK_LANE_LN1 = 1'b0; \nparameter HSCLK_LANE_LN2 = 1'b0; \nparameter HSCLK_LANE_LN3 = 1'b0; \nparameter HSCLK_LANE_LNCK = 1'b1; \nparameter ALP_ED_EN_LANE0 = 1'b1 ; \nparameter ALP_ED_EN_LANE1 = 1'b1 ; \nparameter ALP_ED_EN_LANE2 = 1'b1 ; \nparameter ALP_ED_EN_LANE3 = 1'b1 ; \nparameter ALP_ED_EN_LANECK = 1'b1 ; \nparameter ALP_ED_TST_LANE0 = 1'b0 ; \nparameter ALP_ED_TST_LANE1 = 1'b0 ; \nparameter ALP_ED_TST_LANE2 = 1'b0 ; \nparameter ALP_ED_TST_LANE3 = 1'b0 ; \nparameter ALP_ED_TST_LANECK = 1'b0 ; \nparameter ALP_EN_LN0 = 1'b0 ; \nparameter ALP_EN_LN1 = 1'b0 ; \nparameter ALP_EN_LN2 = 1'b0 ; \nparameter ALP_EN_LN3 = 1'b0 ; \nparameter ALP_EN_LNCK = 1'b0 ; \nparameter ALP_HYS_EN_LANE0 = 1'b1 ; \nparameter ALP_HYS_EN_LANE1 = 1'b1 ; \nparameter ALP_HYS_EN_LANE2 = 1'b1 ; \nparameter ALP_HYS_EN_LANE3 = 1'b1 ; \nparameter ALP_HYS_EN_LANECK = 1'b1 ; \nparameter ALP_TH_LANE0 = 4'b1000 ; \nparameter ALP_TH_LANE1 = 4'b1000 ; \nparameter ALP_TH_LANE2 = 4'b1000 ; \nparameter ALP_TH_LANE3 = 4'b1000 ; \nparameter ALP_TH_LANECK = 4'b1000 ; \nparameter ANA_BYTECLK_PH = 2'b00 ; \nparameter BIT_REVERSE_LN0 = 1'b0 ; \nparameter BIT_REVERSE_LN1 = 1'b0 ; \nparameter BIT_REVERSE_LN2 = 1'b0 ; \nparameter BIT_REVERSE_LN3 = 1'b0 ; \nparameter BIT_REVERSE_LNCK = 1'b0 ; \nparameter BYPASS_TXHCLKEN = 1'b1 ; \nparameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; \nparameter BYTE_CLK_POLAR = 1'b0 ; \nparameter BYTE_REVERSE_LN0 = 1'b0 ; \nparameter BYTE_REVERSE_LN1 = 1'b0 ; \nparameter BYTE_REVERSE_LN2 = 1'b0 ; \nparameter BYTE_REVERSE_LN3 = 1'b0 ; \nparameter BYTE_REVERSE_LNCK = 1'b0 ; \nparameter EN_CLKB1X = 1'b1 ; \nparameter EQ_PBIAS_LANE0 = 4'b1000 ; \nparameter EQ_PBIAS_LANE1 = 4'b1000 ; \nparameter EQ_PBIAS_LANE2 = 4'b1000 ; \nparameter EQ_PBIAS_LANE3 = 4'b1000 ; \nparameter EQ_PBIAS_LANECK = 4'b1000 ; \nparameter EQ_ZLD_LANE0 = 4'b1000 ; \nparameter EQ_ZLD_LANE1 = 4'b1000 ; \nparameter EQ_ZLD_LANE2 = 4'b1000 ; \nparameter EQ_ZLD_LANE3 = 4'b1000 ; \nparameter EQ_ZLD_LANECK = 4'b1000 ; \nparameter HIGH_BW_LANE0 = 1'b1 ; \nparameter HIGH_BW_LANE1 = 1'b1 ; \nparameter HIGH_BW_LANE2 = 1'b1 ; \nparameter HIGH_BW_LANE3 = 1'b1 ; \nparameter HIGH_BW_LANECK = 1'b1 ; \nparameter HSREG_VREF_CTL = 3'b100 ; \nparameter HSREG_VREF_EN = 1'b1 ; \nparameter HSRX_DLY_CTL_CK = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; \nparameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; \nparameter HSRX_DLY_SEL_LANE0 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANE1 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANE2 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANE3 = 1'b0 ; \nparameter HSRX_DLY_SEL_LANECK = 1'b0 ; \nparameter HSRX_DUTY_LANE0 = 4'b1000 ; \nparameter HSRX_DUTY_LANE1 = 4'b1000 ; \nparameter HSRX_DUTY_LANE2 = 4'b1000 ; \nparameter HSRX_DUTY_LANE3 = 4'b1000 ; \nparameter HSRX_DUTY_LANECK = 4'b1000 ; \nparameter HSRX_EQ_EN_LANE0 = 1'b1 ; \nparameter HSRX_EQ_EN_LANE1 = 1'b1 ; \nparameter HSRX_EQ_EN_LANE2 = 1'b1 ; \nparameter HSRX_EQ_EN_LANE3 = 1'b1 ; \nparameter HSRX_EQ_EN_LANECK = 1'b1 ; \nparameter HSRX_IBIAS = 4'b0011 ; \nparameter HSRX_IBIAS_TEST_EN = 1'b0 ; \nparameter HSRX_IMARG_EN = 1'b0 ; \nparameter HSRX_ODT_EN = 1'b1 ; \nparameter HSRX_ODT_TST = 4'b0000 ; \nparameter HSRX_ODT_TST_CK = 1'b0 ; \nparameter HSRX_SEL = 4'b0000 ; \nparameter HSRX_STOP_EN = 1'b0 ; \nparameter HSRX_TST = 4'b0000 ; \nparameter HSRX_TST_CK = 1'b0 ; \nparameter HSRX_WAIT4EDGE = 1'b1 ; \nparameter HYST_NCTL = 2'b01 ; \nparameter HYST_PCTL = 2'b01 ; \nparameter IBIAS_TEST_EN = 1'b0 ; \nparameter LB_CH_SEL = 1'b0 ; \nparameter LB_EN_LN0 = 1'b0 ; \nparameter LB_EN_LN1 = 1'b0 ; \nparameter LB_EN_LN2 = 1'b0 ; \nparameter LB_EN_LN3 = 1'b0 ; \nparameter LB_EN_LNCK = 1'b0 ; \nparameter LB_POLAR_LN0 = 1'b0 ; \nparameter LB_POLAR_LN1 = 1'b0 ; \nparameter LB_POLAR_LN2 = 1'b0 ; \nparameter LB_POLAR_LN3 = 1'b0 ; \nparameter LB_POLAR_LNCK = 1'b0 ; \nparameter LOW_LPRX_VTH = 1'b0 ; \nparameter LPBK_DATA2TO1 = 4'b0000; \nparameter LPBK_DATA2TO1_CK = 1'b0 ; \nparameter LPBK_EN = 1'b0 ; \nparameter LPBK_SEL = 4'b0000; \nparameter LPBKTST_EN = 4'b0000; \nparameter LPBKTST_EN_CK = 1'b0 ; \nparameter LPRX_EN = 1'b1 ; \nparameter LPRX_TST = 4'b0000; \nparameter LPRX_TST_CK = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN0 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN1 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN2 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LN3 = 1'b0 ; \nparameter LPTX_DAT_POLAR_LNCK = 1'b0 ; \nparameter LPTX_NIMP_LN0 = 3'b100 ; \nparameter LPTX_NIMP_LN1 = 3'b100 ; \nparameter LPTX_NIMP_LN2 = 3'b100 ; \nparameter LPTX_NIMP_LN3 = 3'b100 ; \nparameter LPTX_NIMP_LNCK = 3'b100 ; \nparameter LPTX_PIMP_LN0 = 3'b100 ; \nparameter LPTX_PIMP_LN1 = 3'b100 ; \nparameter LPTX_PIMP_LN2 = 3'b100 ; \nparameter LPTX_PIMP_LN3 = 3'b100 ; \nparameter LPTX_PIMP_LNCK = 3'b100 ; \nparameter MIPI_PMA_DIS_N = 1'b1 ; \nparameter PGA_BIAS_LANE0 = 4'b1000 ; \nparameter PGA_BIAS_LANE1 = 4'b1000 ; \nparameter PGA_BIAS_LANE2 = 4'b1000 ; \nparameter PGA_BIAS_LANE3 = 4'b1000 ; \nparameter PGA_BIAS_LANECK = 4'b1000 ; \nparameter PGA_GAIN_LANE0 = 4'b1000 ; \nparameter PGA_GAIN_LANE1 = 4'b1000 ; \nparameter PGA_GAIN_LANE2 = 4'b1000 ; \nparameter PGA_GAIN_LANE3 = 4'b1000 ; \nparameter PGA_GAIN_LANECK = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE0 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE1 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE2 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANE3 = 4'b1000 ; \nparameter RX_ODT_TRIM_LANECK = 4'b1000 ; \nparameter SLEWN_CTL_LN0 = 4'b1111 ; \nparameter SLEWN_CTL_LN1 = 4'b1111 ; \nparameter SLEWN_CTL_LN2 = 4'b1111 ; \nparameter SLEWN_CTL_LN3 = 4'b1111 ; \nparameter SLEWN_CTL_LNCK = 4'b1111 ; \nparameter SLEWP_CTL_LN0 = 4'b1111 ; \nparameter SLEWP_CTL_LN1 = 4'b1111 ; \nparameter SLEWP_CTL_LN2 = 4'b1111 ; \nparameter SLEWP_CTL_LN3 = 4'b1111 ; \nparameter SLEWP_CTL_LNCK = 4'b1111 ; \nparameter STP_UNIT = 2'b01 ; \nparameter TERMN_CTL_LN0 = 4'b1000 ; \nparameter TERMN_CTL_LN1 = 4'b1000 ; \nparameter TERMN_CTL_LN2 = 4'b1000 ; \nparameter TERMN_CTL_LN3 = 4'b1000 ; \nparameter TERMN_CTL_LNCK = 4'b1000 ; \nparameter TERMP_CTL_LN0 = 4'b1000 ; \nparameter TERMP_CTL_LN1 = 4'b1000 ; \nparameter TERMP_CTL_LN2 = 4'b1000 ; \nparameter TERMP_CTL_LN3 = 4'b1000 ; \nparameter TERMP_CTL_LNCK = 4'b1000 ; \nparameter TEST_EN_LN0 = 1'b0 ; \nparameter TEST_EN_LN1 = 1'b0 ; \nparameter TEST_EN_LN2 = 1'b0 ; \nparameter TEST_EN_LN3 = 1'b0 ; \nparameter TEST_EN_LNCK = 1'b0 ; \nparameter TEST_N_IMP_LN0 = 1'b0 ; \nparameter TEST_N_IMP_LN1 = 1'b0 ; \nparameter TEST_N_IMP_LN2 = 1'b0 ; \nparameter TEST_N_IMP_LN3 = 1'b0 ; \nparameter TEST_N_IMP_LNCK = 1'b0 ; \nparameter TEST_P_IMP_LN0 = 1'b0 ; \nparameter TEST_P_IMP_LN1 = 1'b0 ; \nparameter TEST_P_IMP_LN2 = 1'b0 ; \nparameter TEST_P_IMP_LN3 = 1'b0 ; \nparameter TEST_P_IMP_LNCK = 1'b0 ; \nendmodule\n\nmodule MIPI_CPHY (...);\noutput [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD;\noutput D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD;\noutput [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD;\noutput D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR;\noutput [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA;\noutput D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O; \noutput HSTX_FIFO_AE, HSTX_FIFO_AF;\noutput HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR;\noutput RX_CLK_MUXED;\noutput TX_CLK_1X_O;\noutput DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C;\noutput [7:0] MDRP_RDATA; \ninout D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C;\ninput D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN;\ninput [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA;\ninput D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD;\ninput [1:0] D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS;\ninput D0LN_RX_CLK_1X_I,D1LN_RX_CLK_1X_I, D2LN_RX_CLK_1X_I;\ninput D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N;\ninput HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2;\ninput [7:0] MDRP_A_D_I;\ninput MDRP_A_INC_I;\ninput MDRP_CLK_I;\ninput [1:0] MDRP_OPCODE_I;\ninput PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX;\ninput ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; \ninput ARSTN_TX;\ninput RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; \ninput TX_CLK_1X_I;\ninput TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; \ninput TXHCLK_EN; \ninput DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2;\ninput GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270;\ninput HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; \ninput HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2;\ninput LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; \ninput SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP;\nparameter TX_PLLCLK = \"NONE\"; \nparameter D0LN_HS_TX_EN = 1'b1; \nparameter D1LN_HS_TX_EN = 1'b1;\nparameter D2LN_HS_TX_EN = 1'b1;\nparameter D0LN_HS_RX_EN = 1'b1; \nparameter D1LN_HS_RX_EN = 1'b1;\nparameter D2LN_HS_RX_EN = 1'b1;\nparameter TX_HS_21BIT_MODE = 1'b0; \nparameter RX_OUTCLK_SEL = 2'b00; \nparameter TX_W_LENDIAN = 1'b1; \nparameter CLK_SEL = 2'b00; \nparameter LNDIV_RATIO = 4'b0000; \nparameter LNDIV_EN = 1'b0; \nparameter D0LN_TX_REASGN_A = 2'b00; \nparameter D0LN_TX_REASGN_B = 2'b01; \nparameter D0LN_TX_REASGN_C = 2'b10; \nparameter D0LN_RX_HS_21BIT_MODE = 1'b0; \nparameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1; \nparameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001; \nparameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100; \nparameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1; \nparameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001; \nparameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100; \nparameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1; \nparameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001; \nparameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100; \nparameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0; \nparameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001; \nparameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100; \nparameter D0LN_RX_W_LENDIAN = 1'b1; \nparameter D0LN_RX_REASGN_A = 2'b00; \nparameter D0LN_RX_REASGN_B = 2'b01; \nparameter D0LN_RX_REASGN_C = 2'b10; \nparameter HSRX_LNSEL = 3'b111; \nparameter EQ_RS_LN0 = 3'b001; \nparameter EQ_CS_LN0 = 3'b101; \nparameter PGA_GAIN_LN0 = 4'b0110; \nparameter PGA_BIAS_LN0 = 4'b1000; \nparameter EQ_PBIAS_LN0 = 4'b0100; \nparameter EQ_ZLD_LN0 = 4'b1000; \nparameter D1LN_TX_REASGN_A = 2'b00; \nparameter D1LN_TX_REASGN_B = 2'b01; \nparameter D1LN_TX_REASGN_C = 2'b10; \nparameter D1LN_RX_HS_21BIT_MODE = 1'b0; \nparameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1; \nparameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001; \nparameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100; \nparameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1; \nparameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001; \nparameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100; \nparameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1; \nparameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001; \nparameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100; \nparameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0; \nparameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001; \nparameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100; \nparameter D1LN_RX_W_LENDIAN = 1'b1; \nparameter D1LN_RX_REASGN_A = 2'b00; \nparameter D1LN_RX_REASGN_B = 2'b01; \nparameter D1LN_RX_REASGN_C = 2'b10; \nparameter EQ_RS_LN1 = 3'b001; \nparameter EQ_CS_LN1 = 3'b101; \nparameter PGA_GAIN_LN1 = 4'b0110; \nparameter PGA_BIAS_LN1 = 4'b1000; \nparameter EQ_PBIAS_LN1 = 4'b0100; \nparameter EQ_ZLD_LN1 = 4'b1000; \nparameter D2LN_TX_REASGN_A = 2'b00; \nparameter D2LN_TX_REASGN_B = 2'b01; \nparameter D2LN_TX_REASGN_C = 2'b10; \nparameter D2LN_RX_HS_21BIT_MODE = 1'b0; \nparameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1; \nparameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001; \nparameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100; \nparameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1; \nparameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001; \nparameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100; \nparameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1; \nparameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001; \nparameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100; \nparameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0; \nparameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001; \nparameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100; \nparameter D2LN_RX_W_LENDIAN = 1'b1; \nparameter D2LN_RX_REASGN_A = 2'b00; \nparameter D2LN_RX_REASGN_B = 2'b01; \nparameter D2LN_RX_REASGN_C = 2'b10; \nparameter EQ_RS_LN2 = 3'b001; \nparameter EQ_CS_LN2 = 3'b101; \nparameter PGA_GAIN_LN2 = 4'b0110; \nparameter PGA_BIAS_LN2 = 4'b1000; \nparameter EQ_PBIAS_LN2 = 4'b0100; \nparameter EQ_ZLD_LN2 = 4'b1000; \nendmodule\n\nmodule GTR12_QUAD (...);\nendmodule\n\nmodule GTR12_UPAR (...);\nendmodule\n\nmodule GTR12_PMAC (...);\nendmodule\n\nmodule GTR12_QUADA (...);\nendmodule\n\nmodule GTR12_UPARA (...);\nendmodule\n\nmodule GTR12_PMACA (...);\nendmodule\n\nmodule GTR12_QUADB (...);\nendmodule\n\nmodule DQS (...);\ninput DQSIN,PCLK,FCLK,RESET;\ninput [3:0] READ;\ninput [2:0] RCLKSEL;\ninput [7:0] DLLSTEP;\ninput [7:0] WSTEP;\ninput RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\noutput DQSR90, DQSW0, DQSW270; \noutput [2:0] RPOINT, WPOINT;\noutput RVALID,RBURST, RFLAG, WFLAG;\nparameter FIFO_MODE_SEL = 1'b0; \nparameter RD_PNTR = 3'b000; \nparameter DQS_MODE = \"X1\"; \nparameter HWL = \"false\"; \nendmodule\n",
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  "lutrams.txt": "ram distributed $__GOWIN_LUTRAM_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\twidthscale;\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
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  "lutrams_map.v": "module $__GOWIN_LUTRAM_(...);\n\nparameter INIT = 64'bx;\nparameter BITS_USED = 0;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput PORT_W_WR_EN;\ninput [3:0] PORT_W_WR_DATA;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nfunction [15:0] init_slice;\ninput integer idx;\ninteger i;\nfor (i = 0; i < 16; i = i + 1)\n\tinit_slice[i] = INIT[4*i+idx];\nendfunction\n\ngenerate\n\ncasez(BITS_USED)\n4'b000z:\nRAM16SDP1 #(\n\t.INIT_0(init_slice(0)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[0]),\n\t.DO(PORT_R_RD_DATA[0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n4'b00zz:\nRAM16SDP2 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[1:0]),\n\t.DO(PORT_R_RD_DATA[1:0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\ndefault:\nRAM16SDP4 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n\t.INIT_2(init_slice(2)),\n\t.INIT_3(init_slice(3)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.DO(PORT_R_RD_DATA),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\nendcase\n\nendgenerate\n\nendmodule\n",
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  },
@@ -134,10 +138,10 @@ export const filesystem = {
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  "cxxrtl_capi_vcd.cc": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi_vcd.h`.\n\n#include <cxxrtl/capi/cxxrtl_capi_vcd.h>\n#include <cxxrtl/cxxrtl_vcd.h>\n\nextern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle);\n\nstruct _cxxrtl_vcd {\n\tcxxrtl::vcd_writer writer;\n\tbool flush = false;\n};\n\ncxxrtl_vcd cxxrtl_vcd_create() {\n\treturn new _cxxrtl_vcd;\n}\n\nvoid cxxrtl_vcd_destroy(cxxrtl_vcd vcd) {\n\tdelete vcd;\n}\n\nvoid cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit) {\n\tvcd->writer.timescale(number, unit);\n}\n\nvoid cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, cxxrtl_object *object) {\n\t// Note the copy. We don't know whether `object` came from a design (in which case it is\n\t// an instance of `debug_item`), or from user code (in which case it is an instance of\n\t// `cxxrtl_object`), so casting the pointer wouldn't be safe.\n\tvcd->writer.add(name, cxxrtl::debug_item(*object));\n}\n\nvoid cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle) {\n\tvcd->writer.add(cxxrtl_debug_items_from_handle(handle));\n}\n\nvoid cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tint (*filter)(void *data, const char *name,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t const cxxrtl_object *object)) {\n\tvcd->writer.add(cxxrtl_debug_items_from_handle(handle),\n\t\t[=](const std::string &name, const cxxrtl::debug_item &item) {\n\t\t\treturn filter(data, name.c_str(), static_cast<const cxxrtl_object*>(&item));\n\t\t});\n}\n\nvoid cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle) {\n\tvcd->writer.add_without_memories(cxxrtl_debug_items_from_handle(handle));\n}\n\nvoid cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time) {\n\tif (vcd->flush) {\n\t\tvcd->writer.buffer.clear();\n\t\tvcd->flush = false;\n\t}\n\tvcd->writer.sample(time);\n}\n\nvoid cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size) {\n\tif (vcd->flush) {\n\t\tvcd->writer.buffer.clear();\n\t\tvcd->flush = false;\n\t}\n\t*data = vcd->writer.buffer.c_str();\n\t*size = vcd->writer.buffer.size();\n\tvcd->flush = true;\n}\n",
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  "cxxrtl_capi_vcd.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_CAPI_VCD_H\n#define CXXRTL_CAPI_VCD_H\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`.\n//\n// The CXXRTL C API for VCD writing makes it possible to insert virtual probes into designs and\n// dump waveforms to Value Change Dump files.\n\n#include <stddef.h>\n#include <stdint.h>\n\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// Opaque reference to a VCD writer.\ntypedef struct _cxxrtl_vcd *cxxrtl_vcd;\n\n// Create a VCD writer.\ncxxrtl_vcd cxxrtl_vcd_create();\n\n// Release all resources used by a VCD writer.\nvoid cxxrtl_vcd_destroy(cxxrtl_vcd vcd);\n\n// Set VCD timescale.\n//\n// The `number` must be 1, 10, or 100, and the `unit` must be one of `\"s\"`, `\"ms\"`, `\"us\"`, `\"ns\"`,\n// `\"ps\"`, or `\"fs\"`.\n//\n// Timescale can only be set before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit);\n\n// Schedule a specific CXXRTL object to be sampled.\n//\n// The `name` is a full hierarchical name as described for `cxxrtl_get`; it does not need to match\n// the original name of `object`, if any. The `object` must outlive the VCD writer, but there are\n// no other requirements; if desired, it can be provided by user code, rather than come from\n// a design.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, struct cxxrtl_object *object);\n\n// Schedule all CXXRTL objects in a simulation.\n//\n// The design `handle` must outlive the VCD writer.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle);\n\n// Schedule CXXRTL objects in a simulation that match a given predicate.\n//\n// For every object in the simulation, `filter` is called with the provided `data`, the full\n// hierarchical name of the object (see `cxxrtl_get` for details), and the object description.\n// The object will be sampled if the predicate returns a non-zero value.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,\n int (*filter)(void *data, const char *name,\n const struct cxxrtl_object *object));\n\n// Schedule all CXXRTL objects in a simulation except for memories.\n//\n// The design `handle` must outlive the VCD writer.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle);\n\n// Sample all scheduled objects.\n//\n// First, `time` is written to the internal buffer. Second, the values of every signal changed since\n// the previous call to `cxxrtl_vcd_sample` (all values if this is the first call) are written to\n// the internal buffer. The contents of the buffer can be retrieved with `cxxrtl_vcd_read`.\nvoid cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time);\n\n// Retrieve buffered VCD data.\n//\n// The pointer to the start of the next chunk of VCD data is assigned to `*data`, and the length\n// of that chunk is assigned to `*size`. The pointer to the data is valid until the next call to\n// `cxxrtl_vcd_sample` or `cxxrtl_vcd_read`. Once all of the buffered data has been retrieved,\n// this function will always return zero sized chunks.\nvoid cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n",
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- "cxxrtl.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.\n//\n// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides\n// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass\n// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler\n// to unwrap the abstraction and generate efficient code.\n\n#ifndef CXXRTL_H\n#define CXXRTL_H\n\n#include <cstddef>\n#include <cstdint>\n#include <cstring>\n#include <cassert>\n#include <limits>\n#include <type_traits>\n#include <tuple>\n#include <vector>\n#include <map>\n#include <algorithm>\n#include <memory>\n#include <functional>\n#include <sstream>\n#include <iostream>\n\n// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifndef __has_attribute\n#\tdefine __has_attribute(x) 0\n#endif\n\n// CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.\n// It generates a lot of specialized template functions with relatively large bodies that, when inlined\n// into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.\n// Because of this, most of the CXXRTL runtime must be always inlined for best performance.\n#if __has_attribute(always_inline)\n#define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))\n#else\n#define CXXRTL_ALWAYS_INLINE inline\n#endif\n// Conversely, some functions in the generated code are extremely large yet very cold, with both of these\n// properties being extreme enough to confuse C++ compilers into spending pathological amounts of time\n// on a futile (the code becomes worse) attempt to optimize the least important parts of code.\n#if __has_attribute(optnone)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))\n#elif __has_attribute(optimize)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))\n#else\n#define CXXRTL_EXTREMELY_COLD\n#endif\n\n// CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior\n// of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at\n// most result in undefined simulation results).\n//\n// Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating\n// the simulation into another process that should survive violating RTL contracts.\n#ifndef CXXRTL_ASSERT\n#ifndef CXXRTL_NDEBUG\n#define CXXRTL_ASSERT(x) assert(x)\n#else\n#define CXXRTL_ASSERT(x)\n#endif\n#endif\n\nnamespace cxxrtl {\n\n// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size\n// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving\n// and introspecting the simulation in Python.\n//\n// It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on\n// narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.\n// However, (a) most of our operations do not change those bits in the first place because of invariants that are\n// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.\n// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be\n// clobbered results in simpler generated code.\ntypedef uint32_t chunk_t;\ntypedef uint64_t wide_chunk_t;\n\ntemplate<typename T>\nstruct chunk_traits {\n\tstatic_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,\n\t \"chunk type must be an unsigned integral type\");\n\tusing type = T;\n\tstatic constexpr size_t bits = std::numeric_limits<T>::digits;\n\tstatic constexpr T mask = std::numeric_limits<T>::max();\n};\n\ntemplate<class T>\nstruct expr_base;\n\ntemplate<size_t Bits>\nstruct value : public expr_base<value<Bits>> {\n\tstatic constexpr size_t bits = Bits;\n\n\tusing chunk = chunk_traits<chunk_t>;\n\tstatic constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask\n\t\t: chunk::mask >> (chunk::bits - (Bits % chunk::bits));\n\n\tstatic constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;\n\tchunk::type data[chunks] = {};\n\n\tvalue() = default;\n\ttemplate<typename... Init>\n\texplicit constexpr value(Init ...init) : data{init...} {}\n\n\tvalue(const value<Bits> &) = default;\n\tvalue<Bits> &operator=(const value<Bits> &) = default;\n\n\tvalue(value<Bits> &&) = default;\n\tvalue<Bits> &operator=(value<Bits> &&) = default;\n\n\t// A (no-op) helper that forces the cast to value<>.\n\tCXXRTL_ALWAYS_INLINE\n\tconst value<Bits> &val() const {\n\t\treturn *this;\n\t}\n\n\tstd::string str() const {\n\t\tstd::stringstream ss;\n\t\tss << *this;\n\t\treturn ss.str();\n\t}\n\n\t// Conversion operations.\n\t//\n\t// These functions ensure that a conversion is never out of range, and should be always used, if at all\n\t// possible, instead of direct manipulation of the `data` member. For very large types, .slice() and\n\t// .concat() can be used to split them into more manageable parts.\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"get<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"get<T>() requires T to be at least as wide as the value is\");\n\t\tIntegerT result = 0;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult |= IntegerT(data[n]) << (n * chunk::bits);\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tauto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();\n\t\tIntegerT result;\n\t\tmemcpy(&result, &unsigned_result, sizeof(IntegerT));\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"set<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"set<T>() requires the value to be at least as wide as T is\");\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tdata[n] = (value >> (n * chunk::bits)) & chunk::mask;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\ttypename std::make_unsigned<IntegerT>::type unsigned_value;\n\t\tmemcpy(&unsigned_value, &value, sizeof(IntegerT));\n\t\tset(unsigned_value);\n\t}\n\n\t// Operations with compile-time parameters.\n\t//\n\t// These operations are used to implement slicing, concatenation, and blitting.\n\t// The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);\n\t// the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> trunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"trunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < result.chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zext() const {\n\t\tstatic_assert(NewBits >= Bits, \"zext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> sext() const {\n\t\tstatic_assert(NewBits >= Bits, \"sext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tif (is_neg()) {\n\t\t\tresult.data[chunks - 1] |= ~msb_mask;\n\t\t\tfor (size_t n = chunks; n < result.chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rtrunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"rtrunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (Bits - NewBits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tif (shift_chunks + result.chunks < chunks) {\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);\n\t\t}\n\t\tfor (size_t n = result.chunks; n > 0; n--) {\n\t\t\tresult.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + n - 1] << (chunk::bits - shift_bits);\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rzext() const {\n\t\tstatic_assert(NewBits >= Bits, \"rzext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (NewBits - Bits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (shift_chunks + chunks < result.chunks)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\t// Bit blit operation, i.e. a partial read-modify-write.\n\ttemplate<size_t Stop, size_t Start>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits> blit(const value<Stop - Start + 1> &source) const {\n\t\tstatic_assert(Stop >= Start, \"blit() may not reverse bit order\");\n\t\tconstexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));\n\t\tconstexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0\n\t\t\t: (chunk::mask << (Stop % chunk::bits + 1));\n\t\tvalue<Bits> masked = *this;\n\t\tif (Start / chunk::bits == Stop / chunk::bits) {\n\t\t\tmasked.data[Start / chunk::bits] &= stop_mask | start_mask;\n\t\t} else {\n\t\t\tmasked.data[Start / chunk::bits] &= start_mask;\n\t\t\tfor (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)\n\t\t\t\tmasked.data[n] = 0;\n\t\t\tmasked.data[Stop / chunk::bits] &= stop_mask;\n\t\t}\n\t\tvalue<Bits> shifted = source\n\t\t\t.template rzext<Stop + 1>()\n\t\t\t.template zext<Bits>();\n\t\treturn masked.bit_or(shifted);\n\t}\n\n\t// Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower\n\t// than the operand. In C++17 these can be replaced with `if constexpr`.\n\ttemplate<size_t NewBits, typename = void>\n\tstruct zext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template zext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits, typename = void>\n\tstruct sext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template sext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zcast() const {\n\t\treturn zext_cast<NewBits>()(*this);\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> scast() const {\n\t\treturn sext_cast<NewBits>()(*this);\n\t}\n\n\t// Bit replication is far more efficient than the equivalent concatenation.\n\ttemplate<size_t Count>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits * Count> repeat() const {\n\t\tstatic_assert(Bits == 1, \"repeat() is implemented only for 1-bit values\");\n\t\treturn *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();\n\t}\n\n\t// Operations with run-time parameters (offsets, amounts, etc).\n\t//\n\t// These operations are used for computations.\n\tbool bit(size_t offset) const {\n\t\treturn data[offset / chunk::bits] & (1 << (offset % chunk::bits));\n\t}\n\n\tvoid set_bit(size_t offset, bool value = true) {\n\t\tsize_t offset_chunks = offset / chunk::bits;\n\t\tsize_t offset_bits = offset % chunk::bits;\n\t\tdata[offset_chunks] &= ~(1 << offset_bits);\n\t\tdata[offset_chunks] |= value ? 1 << offset_bits : 0;\n\t}\n\n\texplicit operator bool() const {\n\t\treturn !is_zero();\n\t}\n\n\tbool is_zero() const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool is_neg() const {\n\t\treturn data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));\n\t}\n\n\tbool operator ==(const value<Bits> &other) const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != other.data[n])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator !=(const value<Bits> &other) const {\n\t\treturn !(*this == other);\n\t}\n\n\tvalue<Bits> bit_not() const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = ~data[n];\n\t\tresult.data[chunks - 1] &= msb_mask;\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_and(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] & other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_or(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] | other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_xor(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] ^ other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {\n\t\treturn bit_and(mask.bit_not()).bit_or(val.bit_and(mask));\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> shl(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shl() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn {};\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn {};\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits, bool Signed = false>\n\tvalue<Bits> shr(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shr() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Signed && is_neg()) {\n\t\t\tsize_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;\n\t\t\tsize_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;\n\t\t\tfor (size_t n = top_chunk_idx + 1; n < chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tif (amount.data[0] != 0)\n\t\t\t\tresult.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> sshr(const value<AmountBits> &amount) const {\n\t\treturn shr<AmountBits, /*Signed=*/true>(amount);\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> bmux(const value<SelBits> &sel) const {\n\t\tstatic_assert(ResultBits << SelBits == Bits, \"invalid sizes used in bmux()\");\n\t\tsize_t amount = sel.data[0] * ResultBits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tif (ResultBits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tcarry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> demux(const value<SelBits> &sel) const {\n\t\tstatic_assert(Bits << SelBits == ResultBits, \"invalid sizes used in demux()\");\n\t\tsize_t amount = sel.data[0] * Bits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Bits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\tsize_t ctpop() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\t// This loop implements the population count idiom as recognized by LLVM and GCC.\n\t\t\tfor (chunk::type x = data[n]; x != 0; count++)\n\t\t\t\tx = x & (x - 1);\n\t\t}\n\t\treturn count;\n\t}\n\n\tsize_t ctlz() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tchunk::type x = data[chunks - 1 - n];\n\t\t\t// First add to `count` as if the chunk is zero\n\t\t\tconstexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;\n\t\t\tcount += (n == 0 ? msb_chunk_bits : chunk::bits);\n\t\t\t// If the chunk isn't zero, correct the `count` value and return\n\t\t\tif (x != 0) {\n\t\t\t\tfor (; x != 0; count--)\n\t\t\t\t\tx >>= 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\treturn count;\n\t}\n\n\ttemplate<bool Invert, bool CarryIn>\n\tstd::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry = CarryIn;\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;\n\t\t\tif (result.chunks - 1 == n)\n\t\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t\tcarry = (result.data[n] < data[n]) ||\n\t\t\t (result.data[n] == data[n] && carry);\n\t\t}\n\t\treturn {result, carry};\n\t}\n\n\tvalue<Bits> add(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/false, /*CarryIn=*/false>(other).first;\n\t}\n\n\tvalue<Bits> sub(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/true, /*CarryIn=*/true>(other).first;\n\t}\n\n\tvalue<Bits> neg() const {\n\t\treturn value<Bits>().sub(*this);\n\t}\n\n\tbool ucmp(const value<Bits> &other) const {\n\t\tbool carry;\n\t\tstd::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\treturn !carry; // a.ucmp(b) ≡ a u< b\n\t}\n\n\tbool scmp(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry;\n\t\tstd::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\tbool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());\n\t\treturn result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b\n\t}\n\n\ttemplate<size_t ResultBits>\n\tvalue<ResultBits> mul(const value<Bits> &other) const {\n\t\tvalue<ResultBits> result;\n\t\twide_chunk_t wide_result[result.chunks + 1] = {};\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tfor (size_t m = 0; m < chunks && n + m < result.chunks; m++) {\n\t\t\t\twide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);\n\t\t\t\twide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;\n\t\t\t\twide_result[n + m] &= chunk::mask;\n\t\t\t}\n\t\t}\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = wide_result[n];\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {\n\t\tvalue<Bits> quotient;\n\t\tvalue<Bits> dividend = *this;\n\t\tif (dividend.ucmp(divisor))\n\t\t\treturn {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};\n\t\tint64_t divisor_shift = divisor.ctlz() - dividend.ctlz();\n\t\tassert(divisor_shift >= 0);\n\t\tdivisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});\n\t\tfor (size_t step = 0; step <= divisor_shift; step++) {\n\t\t\tquotient = quotient.shl(value<Bits>{1u});\n\t\t\tif (!dividend.ucmp(divisor)) {\n\t\t\t\tdividend = dividend.sub(divisor);\n\t\t\t\tquotient.set_bit(0, true);\n\t\t\t}\n\t\t\tdivisor = divisor.shr(value<Bits>{1u});\n\t\t}\n\t\treturn {quotient, /*remainder=*/dividend};\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {\n\t\tvalue<Bits + 1> quotient;\n\t\tvalue<Bits + 1> remainder;\n\t\tvalue<Bits + 1> dividend = sext<Bits + 1>();\n\t\tvalue<Bits + 1> divisor = other.template sext<Bits + 1>();\n\t\tif (is_neg()) dividend = dividend.neg();\n\t\tif (other.is_neg()) divisor = divisor.neg();\n\t\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\t\tif (is_neg() != other.is_neg()) quotient = quotient.neg();\n\t\tif (is_neg()) remainder = remainder.neg();\n\t\treturn {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};\n\t}\n};\n\n// Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, size_t Stop, size_t Start>\nstruct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {\n\tstatic_assert(Stop >= Start, \"slice_expr() may not reverse bit order\");\n\tstatic_assert(Start < T::bits && Stop < T::bits, \"slice_expr() must be within bounds\");\n\tstatic constexpr size_t bits = Stop - Start + 1;\n\n\tT &expr;\n\n\tslice_expr(T &expr) : expr(expr) {}\n\tslice_expr(const slice_expr<T, Stop, Start> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\treturn static_cast<const value<T::bits> &>(expr)\n\t\t\t.template rtrunc<T::bits - Start>()\n\t\t\t.template trunc<bits>();\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {\n\t\t// Generic partial assignment implemented using a read-modify-write operation on the sliced expression.\n\t\texpr = static_cast<const value<T::bits> &>(expr)\n\t\t\t.template blit<Stop, Start>(rhs);\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, class U>\nstruct concat_expr : public expr_base<concat_expr<T, U>> {\n\tstatic constexpr size_t bits = T::bits + U::bits;\n\n\tT &ms_expr;\n\tU &ls_expr;\n\n\tconcat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}\n\tconcat_expr(const concat_expr<T, U> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\tvalue<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)\n\t\t\t.template rzext<bits>();\n\t\tvalue<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)\n\t\t\t.template zext<bits>();\n\t\treturn ms_shifted.bit_or(ls_extended);\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, U> &operator=(const value<bits> &rhs) {\n\t\tms_expr = rhs.template rtrunc<T::bits>();\n\t\tls_expr = rhs.template trunc<U::bits>();\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.\n//\n// Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because\n// they refer to temporaries that will, in general, only live until the end of the statement. For example, both of\n// these snippets perform use-after-free:\n//\n// const auto &a = val.slice<7,0>().slice<1>();\n// value<1> b = a;\n//\n// auto &&c = val.slice<7,0>().slice<1>();\n// c = value<1>{1u};\n//\n// An easy way to write code using slices and concatenations safely is to follow two simple rules:\n// * Never explicitly name any type except `value<W>` or `const value<W> &`.\n// * Never use a `const auto &` or `auto &&` in any such expression.\n// Then, any code that compiles will be well-defined.\ntemplate<class T>\nstruct expr_base {\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<const T, Stop, Start> slice() const {\n\t\treturn {*static_cast<const T *>(this)};\n\t}\n\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> slice() {\n\t\treturn {*static_cast<T *>(this)};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {\n\t\treturn {*static_cast<const T *>(this), other};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {\n\t\treturn {*static_cast<T *>(this), other};\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const value<Bits> &val) {\n\tauto old_flags = os.flags(std::ios::right);\n\tauto old_width = os.width(0);\n\tauto old_fill = os.fill('0');\n\tos << val.bits << '\\'' << std::hex;\n\tfor (size_t n = val.chunks - 1; n != (size_t)-1; n--) {\n\t\tif (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)\n\t\t\tos.width((Bits % value<Bits>::chunk::bits + 3) / 4);\n\t\telse\n\t\t\tos.width((value<Bits>::chunk::bits + 3) / 4);\n\t\tos << val.data[n];\n\t}\n\tos.fill(old_fill);\n\tos.width(old_width);\n\tos.flags(old_flags);\n\treturn os;\n}\n\ntemplate<size_t Bits>\nstruct wire {\n\tstatic constexpr size_t bits = Bits;\n\n\tvalue<Bits> curr;\n\tvalue<Bits> next;\n\n\twire() = default;\n\texplicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}\n\ttemplate<typename... Init>\n\texplicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}\n\n\t// Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,\n\t// e.g. because a module is built with a different optimization level, then existing code could\n\t// unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure\n\t// this doesn't happen, prohibit copying and copy-assigning wires.\n\twire(const wire<Bits> &) = delete;\n\twire<Bits> &operator=(const wire<Bits> &) = delete;\n\n\twire(wire<Bits> &&) = default;\n\twire<Bits> &operator=(wire<Bits> &&) = default;\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\treturn curr.template get<IntegerT>();\n\t}\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT other) {\n\t\tnext.template set<IntegerT>(other);\n\t}\n\n\t// This method intentionally takes a mandatory argument (to make it more difficult to misuse in\n\t// black box implementations, leading to missed observer events). It is generic over its argument\n\t// to allow the `on_update` method to be non-virtual.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tif (curr != next) {\n\t\t\tobserver.on_update(curr.chunks, curr.data, next.data);\n\t\t\tcurr = next;\n\t\t\treturn true;\n\t\t}\n\t\treturn false;\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {\n\tos << val.curr;\n\treturn os;\n}\n\ntemplate<size_t Width>\nstruct memory {\n\tconst size_t depth;\n\tstd::unique_ptr<value<Width>[]> data;\n\n\texplicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}\n\n\tmemory(const memory<Width> &) = delete;\n\tmemory<Width> &operator=(const memory<Width> &) = delete;\n\n\tmemory(memory<Width> &&) = default;\n\tmemory<Width> &operator=(memory<Width> &&other) {\n\t\tassert(depth == other.depth);\n\t\tdata = std::move(other.data);\n\t\twrite_queue = std::move(other.write_queue);\n\t\treturn *this;\n\t}\n\n\t// An operator for direct memory reads. May be used at any time during the simulation.\n\tconst value<Width> &operator [](size_t index) const {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// An operator for direct memory writes. May only be used before the simulation is started. If used\n\t// after the simulation is started, the design may malfunction.\n\tvalue<Width> &operator [](size_t index) {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// A simple way to make a writable memory would be to use an array of wires instead of an array of values.\n\t// However, there are two significant downsides to this approach: first, it has large overhead (2× space\n\t// overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port\n\t// priorities. Although in principle write ports could be ordered or conditionally enabled in generated\n\t// code based on their priorities and selected addresses, the feedback arc set problem is computationally\n\t// expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)\n\t// a particular write port evaluation order.\n\t//\n\t// The approach used here instead is to queue writes into a buffer during the eval phase, then perform\n\t// the writes during the commit phase in the priority order. This approach has low overhead, with both space\n\t// and time proportional to the amount of write ports. Because virtually every memory in a practical design\n\t// has at most two write ports, linear search is used on every write, being the fastest and simplest approach.\n\tstruct write {\n\t\tsize_t index;\n\t\tvalue<Width> val;\n\t\tvalue<Width> mask;\n\t\tint priority;\n\t};\n\tstd::vector<write> write_queue;\n\n\tvoid update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {\n\t\tassert(index < depth);\n\t\t// Queue up the write while keeping the queue sorted by priority.\n\t\twrite_queue.insert(\n\t\t\tstd::upper_bound(write_queue.begin(), write_queue.end(), priority,\n\t\t\t\t[](const int a, const write& b) { return a < b.priority; }),\n\t\t\twrite { index, val, mask, priority });\n\t}\n\n\t// See the note for `wire::commit()`.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tbool changed = false;\n\t\tfor (const write &entry : write_queue) {\n\t\t\tvalue<Width> elem = data[entry.index];\n\t\t\telem = elem.update(entry.val, entry.mask);\n\t\t\tif (data[entry.index] != elem) {\n\t\t\t\tobserver.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);\n\t\t\t\tchanged |= true;\n\t\t\t}\n\t\t\tdata[entry.index] = elem;\n\t\t}\n\t\twrite_queue.clear();\n\t\treturn changed;\n\t}\n};\n\nstruct metadata {\n\tconst enum {\n\t\tMISSING = 0,\n\t\tUINT \t= 1,\n\t\tSINT \t= 2,\n\t\tSTRING \t= 3,\n\t\tDOUBLE \t= 4,\n\t} value_type;\n\n\t// In debug mode, using the wrong .as_*() function will assert.\n\t// In release mode, using the wrong .as_*() function will safely return a default value.\n\tconst uint64_t uint_value = 0;\n\tconst int64_t sint_value = 0;\n\tconst std::string string_value = \"\";\n\tconst double double_value = 0.0;\n\n\tmetadata() : value_type(MISSING) {}\n\tmetadata(uint64_t value) : value_type(UINT), uint_value(value) {}\n\tmetadata(int64_t value) : value_type(SINT), sint_value(value) {}\n\tmetadata(const std::string &value) : value_type(STRING), string_value(value) {}\n\tmetadata(const char *value) : value_type(STRING), string_value(value) {}\n\tmetadata(double value) : value_type(DOUBLE), double_value(value) {}\n\n\tmetadata(const metadata &) = default;\n\tmetadata &operator=(const metadata &) = delete;\n\n\tuint64_t as_uint() const {\n\t\tassert(value_type == UINT);\n\t\treturn uint_value;\n\t}\n\n\tint64_t as_sint() const {\n\t\tassert(value_type == SINT);\n\t\treturn sint_value;\n\t}\n\n\tconst std::string &as_string() const {\n\t\tassert(value_type == STRING);\n\t\treturn string_value;\n\t}\n\n\tdouble as_double() const {\n\t\tassert(value_type == DOUBLE);\n\t\treturn double_value;\n\t}\n\n\t// Internal CXXRTL use only.\n\tstatic std::map<std::string, metadata> deserialize(const char *ptr) {\n\t\tstd::map<std::string, metadata> result;\n\t\tstd::string name;\n\t\t// Grammar:\n\t\t// string ::= [^\\0]+ \\0\n\t\t// metadata ::= [uid] .{8} | s <string>\n\t\t// map ::= ( <string> <metadata> )* \\0\n\t\tfor (;;) {\n\t\t\tif (*ptr) {\n\t\t\t\tname += *ptr++;\n\t\t\t} else if (!name.empty()) {\n\t\t\t\tptr++;\n\t\t\t\tauto get_u64 = [&]() {\n\t\t\t\t\tuint64_t result = 0;\n\t\t\t\t\tfor (size_t count = 0; count < 8; count++)\n\t\t\t\t\t\tresult = (result << 8) | *ptr++;\n\t\t\t\t\treturn result;\n\t\t\t\t};\n\t\t\t\tchar type = *ptr++;\n\t\t\t\tif (type == 'u') {\n\t\t\t\t\tuint64_t value = get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'i') {\n\t\t\t\t\tint64_t value = (int64_t)get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'd') {\n\t\t\t\t\tdouble dvalue;\n\t\t\t\t\tuint64_t uvalue = get_u64();\n\t\t\t\t\tstatic_assert(sizeof(dvalue) == sizeof(uvalue), \"double must be 64 bits in size\");\n\t\t\t\t\tmemcpy(&dvalue, &uvalue, sizeof(dvalue));\n\t\t\t\t\tresult.emplace(name, dvalue);\n\t\t\t\t} else if (type == 's') {\n\t\t\t\t\tstd::string value;\n\t\t\t\t\twhile (*ptr)\n\t\t\t\t\t\tvalue += *ptr++;\n\t\t\t\t\tptr++;\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else {\n\t\t\t\t\tassert(false && \"Unknown type specifier\");\n\t\t\t\t\treturn result;\n\t\t\t\t}\n\t\t\t\tname.clear();\n\t\t\t} else {\n\t\t\t\treturn result;\n\t\t\t}\n\t\t}\n\t}\n};\n\ntypedef std::map<std::string, metadata> metadata_map;\n\nstruct performer;\n\n// An object that allows formatting a string lazily.\nstruct lazy_fmt {\n\tvirtual std::string operator() () const = 0;\n};\n\n// Flavor of a `$check` cell.\nenum class flavor {\n\t// Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement.\n\tASSERT,\n\t// Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement.\n\tASSUME,\n\t// Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement.\n\tASSERT_EVENTUALLY,\n\t// Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement.\n\tASSUME_EVENTUALLY,\n\t// Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement.\n\tCOVER,\n};\n\n// An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented\n// below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not\n// taken into account.\nstruct performer {\n\t// Called by generated formatting code to evaluate a Verilog `$time` expression.\n\tvirtual int64_t vlog_time() const { return 0; }\n\n\t// Called by generated formatting code to evaluate a Verilog `$realtime` expression.\n\tvirtual double vlog_realtime() const { return vlog_time(); }\n\n\t// Called when a `$print` cell is triggered.\n\tvirtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tstd::cout << formatter();\n\t}\n\n\t// Called when a `$check` cell is triggered.\n\tvirtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tif (type == flavor::ASSERT || type == flavor::ASSUME) {\n\t\t\tif (!condition)\n\t\t\t\tstd::cerr << formatter();\n\t\t\tCXXRTL_ASSERT(condition && \"Check failed\");\n\t\t}\n\t}\n};\n\n// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in\n// the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and\n// a comparatively heavyweight template-based solution is justified.\nstruct observer {\n\t// Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks\n\t// at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and\n\t// `base` points to the first chunk.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}\n\n\t// Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`\n\t// with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to\n\t// the memory element chunk count and `base` points to the first chunk of the first element of the memory.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}\n};\n\n// Must be kept in sync with `struct FmtPart` in kernel/fmt.h!\n// Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.\nstruct fmt_part {\n\tenum {\n\t\tLITERAL = 0,\n\t\tINTEGER = 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\t// + value<Bits> val;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify; // = RIGHT;\n\tchar padding; // = '\\0';\n\tsize_t width; // = 0;\n\n\t// INTEGER type\n\tunsigned base; // = 10;\n\tbool signed_; // = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign; // = MINUS;\n\tbool hex_upper; // = false;\n\tbool show_base; // = false;\n\tbool group; // = false;\n\n\t// VLOG_TIME type\n\tbool realtime; // = false;\n\t// + int64_t itime;\n\t// + double ftime;\n\n\t// Format the part as a string.\n\t//\n\t// The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.\n\ttemplate<size_t Bits>\n\tstd::string render(value<Bits> val, performer *performer = nullptr)\n\t{\n\t\t// We might want to replace some of these bit() calls with direct\n\t\t// chunk access if it turns out to be slow enough to matter.\n\t\tstd::string buf;\n\t\tstd::string prefix;\n\t\tswitch (type) {\n\t\t\tcase LITERAL:\n\t\t\t\treturn str;\n\n\t\t\tcase STRING: {\n\t\t\t\tbuf.reserve(Bits/8);\n\t\t\t\tfor (int i = 0; i < Bits; i += 8) {\n\t\t\t\t\tchar ch = 0;\n\t\t\t\t\tfor (int j = 0; j < 8 && i + j < int(Bits); j++)\n\t\t\t\t\t\tif (val.bit(i + j))\n\t\t\t\t\t\t\tch |= 1 << j;\n\t\t\t\t\tif (ch != 0)\n\t\t\t\t\t\tbuf.append({ch});\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase UNICHAR: {\n\t\t\t\tuint32_t codepoint = val.template get<uint32_t>();\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0xf0 | (codepoint >> 18));\n\t\t\t\telse if (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0xe0 | (codepoint >> 12));\n\t\t\t\telse if (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0xc0 | (codepoint >> 6));\n\t\t\t\telse\n\t\t\t\t\tbuf += (char)codepoint;\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 12) & 0x3f));\n\t\t\t\tif (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 6) & 0x3f));\n\t\t\t\tif (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 0) & 0x3f));\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase INTEGER: {\n\t\t\t\tbool negative = signed_ && val.is_neg();\n\t\t\t\tif (negative) {\n\t\t\t\t\tprefix = \"-\";\n\t\t\t\t\tval = val.neg();\n\t\t\t\t} else {\n\t\t\t\t\tswitch (sign) {\n\t\t\t\t\t\tcase MINUS: break;\n\t\t\t\t\t\tcase PLUS_MINUS: prefix = \"+\"; break;\n\t\t\t\t\t\tcase SPACE_MINUS: prefix = \" \"; break;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tsize_t val_width = Bits;\n\t\t\t\tif (base != 10) {\n\t\t\t\t\tval_width = 1;\n\t\t\t\t\tfor (size_t index = 0; index < Bits; index++)\n\t\t\t\t\t\tif (val.bit(index))\n\t\t\t\t\t\t\tval_width = index + 1;\n\t\t\t\t}\n\n\t\t\t\tif (base == 2) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0b\";\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index++) {\n\t\t\t\t\t\tif (group && index > 0 && index % 4 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += (val.bit(index) ? '1' : '0');\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 8 || base == 16) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += (base == 16) ? (hex_upper ? \"0X\" : \"0x\") : \"0o\";\n\t\t\t\t\tsize_t step = (base == 16) ? 4 : 3;\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index += step) {\n\t\t\t\t\t\tif (group && index > 0 && index % (4 * step) == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tuint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);\n\t\t\t\t\t\tif (step == 4)\n\t\t\t\t\t\t\tvalue |= val.bit(index + 3) << 3;\n\t\t\t\t\t\tbuf += (hex_upper ? \"0123456789ABCDEF\" : \"0123456789abcdef\")[value];\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 10) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0d\";\n\t\t\t\t\tif (val.is_zero())\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();\n\t\t\t\t\tsize_t index = 0;\n\t\t\t\t\twhile (!xval.is_zero()) {\n\t\t\t\t\t\tif (group && index > 0 && index % 3 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> quotient, remainder;\n\t\t\t\t\t\tif (Bits >= 4)\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);\n\t\t\t\t\t\tbuf += '0' + remainder.template trunc<4>().template get<uint8_t>();\n\t\t\t\t\t\txval = quotient;\n\t\t\t\t\t\tindex++;\n\t\t\t\t\t}\n\t\t\t\t} else assert(false && \"Unsupported base for fmt_part\");\n\t\t\t\tif (justify == NUMERIC && group && padding == '0') {\n\t\t\t\t\tint group_size = base == 10 ? 3 : 4;\n\t\t\t\t\twhile (prefix.size() + buf.size() < width) {\n\t\t\t\t\t\tif (buf.size() % (group_size + 1) == group_size)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase VLOG_TIME: {\n\t\t\t\tif (performer) {\n\t\t\t\t\tbuf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());\n\t\t\t\t} else {\n\t\t\t\t\tbuf = realtime ? std::to_string(0.0) : std::to_string(0);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tstd::string str;\n\t\tassert(width == 0 || padding != '\\0');\n\t\tif (prefix.size() + buf.size() < width) {\n\t\t\tsize_t pad_width = width - prefix.size() - buf.size();\n\t\t\tswitch (justify) {\n\t\t\t\tcase LEFT:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tbreak;\n\t\t\t\tcase RIGHT:\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\tcase NUMERIC:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t} else {\n\t\t\tstr += prefix;\n\t\t\tstr += buf;\n\t\t}\n\t\treturn str;\n\t}\n};\n\n// Tag class to disambiguate values/wires and their aliases.\nstruct debug_alias {};\n\n// Tag declaration to disambiguate values and debug outlines.\nusing debug_outline = ::_cxxrtl_outline;\n\n// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.\n// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.\n//\n// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used\n// in the C API, or it would not be possible to cast between the pointers to these.\n//\n// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created\n// from external C code.\nstruct debug_item : ::cxxrtl_object {\n\t// Object types.\n\tenum : uint32_t {\n\t\tVALUE = CXXRTL_VALUE,\n\t\tWIRE = CXXRTL_WIRE,\n\t\tMEMORY = CXXRTL_MEMORY,\n\t\tALIAS = CXXRTL_ALIAS,\n\t\tOUTLINE = CXXRTL_OUTLINE,\n\t};\n\n\t// Object flags.\n\tenum : uint32_t {\n\t\tINPUT = CXXRTL_INPUT,\n\t\tOUTPUT = CXXRTL_OUTPUT,\n\t\tINOUT = CXXRTL_INOUT,\n\t\tDRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,\n\t\tDRIVEN_COMB = CXXRTL_DRIVEN_COMB,\n\t\tUNDRIVEN = CXXRTL_UNDRIVEN,\n\t};\n\n\tdebug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}\n\n\ttemplate<size_t Bits>\n\tdebug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.data;\n\t\tnext = item.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = WIRE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.curr.data;\n\t\tnext = item.next.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Width>\n\tdebug_item(memory<Width> &item, size_t zero_offset = 0) {\n\t\tstatic_assert(Width == 0 || sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),\n\t\t \"memory<Width> is not compatible with C layout\");\n\t\ttype = MEMORY;\n\t\tflags = 0;\n\t\twidth = Width;\n\t\tlsb_at = 0;\n\t\tdepth = item.depth;\n\t\tzero_at = zero_offset;\n\t\tcurr = item.data ? item.data[0].data : nullptr;\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.curr.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = OUTLINE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = &group;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tIntegerT get() const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\tstd::copy(curr, curr + value<Bits>::chunks, item.data);\n\t\treturn item.template get<IntegerT>();\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tvoid set(IntegerT other) const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\titem.template set<IntegerT>(other);\n\t\tstd::copy(item.data, item.data + value<Bits>::chunks, next);\n\t}\n};\nstatic_assert(std::is_standard_layout<debug_item>::value, \"debug_item is not compatible with C layout\");\n\n} // namespace cxxrtl\n\ntypedef struct _cxxrtl_attr_set {\n\tcxxrtl::metadata_map map;\n} *cxxrtl_attr_set;\n\nnamespace cxxrtl {\n\n// Representation of an attribute set in the C++ interface.\nusing debug_attrs = ::_cxxrtl_attr_set;\n\nstruct debug_items {\n\t// Debug items may be composed of multiple parts, but the attributes are shared between all of them.\n\t// There are additional invariants, not all of which are not checked by this code:\n\t// - Memories and non-memories cannot be mixed together.\n\t// - Bit indices (considering `lsb_at` and `width`) must not overlap.\n\t// - Row indices (considering `depth` and `zero_at`) must be the same.\n\t// - The `INPUT` and `OUTPUT` flags must be the same for all parts.\n\t// Other than that, the parts can be quite different, e.g. it is OK to mix a value, a wire, an alias,\n\t// and an outline, in the debug information for a single name in four parts.\n\tstd::map<std::string, std::vector<debug_item>> table;\n\tstd::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;\n\n\tvoid add(const std::string &path, debug_item &&item, metadata_map &&item_attrs = {}) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tstd::unique_ptr<debug_attrs> &attrs = attrs_table[path];\n\t\tif (attrs.get() == nullptr)\n\t\t\tattrs = std::unique_ptr<debug_attrs>(new debug_attrs);\n\t\tfor (auto attr : item_attrs)\n\t\t\tattrs->map.insert(attr);\n\t\titem.attrs = attrs.get();\n\t\tstd::vector<debug_item> &parts = table[path];\n\t\tparts.emplace_back(item);\n\t\tstd::sort(parts.begin(), parts.end(),\n\t\t\t[](const debug_item &a, const debug_item &b) {\n\t\t\t\treturn a.lsb_at < b.lsb_at;\n\t\t\t});\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\ttemplate<class... T>\n\tvoid add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {\n\t\tadd(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));\n\t}\n\n\tsize_t count(const std::string &path) const {\n\t\tif (table.count(path) == 0)\n\t\t\treturn 0;\n\t\treturn table.at(path).size();\n\t}\n\n\tconst std::vector<debug_item> &at(const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n\n\t// Like `at()`, but operates only on single-part debug items.\n\tconst debug_item &operator [](const std::string &path) const {\n\t\tconst std::vector<debug_item> &parts = table.at(path);\n\t\tassert(parts.size() == 1);\n\t\treturn parts.at(0);\n\t}\n\n\tbool is_memory(const std::string &path) const {\n\t\treturn at(path).at(0).type == debug_item::MEMORY;\n\t}\n\n\tconst metadata_map &attrs(const std::string &path) const {\n\t\treturn attrs_table.at(path)->map;\n\t}\n};\n\n// Only `module` scopes are defined. The type is implicit, since Yosys does not currently support\n// any other scope types.\nstruct debug_scope {\n\tstd::string module_name;\n\tstd::unique_ptr<debug_attrs> module_attrs;\n\tstd::unique_ptr<debug_attrs> cell_attrs;\n};\n\nstruct debug_scopes {\n\tstd::map<std::string, debug_scope> table;\n\n\tvoid add(const std::string &path, const std::string &module_name, metadata_map &&module_attrs, metadata_map &&cell_attrs) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tassert(table.count(path) == 0);\n\t\tdebug_scope &scope = table[path];\n\t\tscope.module_name = module_name;\n\t\tscope.module_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { module_attrs });\n\t\tscope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\tvoid add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {\n\t\tadd(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));\n\t}\n\n\tsize_t contains(const std::string &path) const {\n\t\treturn table.count(path);\n\t}\n\n\tconst debug_scope &operator [](const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n};\n\n// Tag class to disambiguate the default constructor used by the toplevel module that calls `reset()`,\n// and the constructor of interior modules that should not call it.\nstruct interior {};\n\n// The core API of the `module` class consists of only four virtual methods: `reset()`, `eval()`,\n// `commit`, and `debug_info()`. (The virtual destructor is made necessary by C++.) Every other method\n// is a convenience method, and exists solely to simplify some common pattern for C++ API consumers.\n// No behavior may be added to such convenience methods that other parts of CXXRTL can rely on, since\n// there is no guarantee they will be called (and, for example, other CXXRTL libraries will often call\n// the `eval()` and `commit()` directly instead, as well as being exposed in the C API).\nstruct module {\n\tmodule() {}\n\tvirtual ~module() {}\n\n\t// Modules with black boxes cannot be copied. Although not all designs include black boxes,\n\t// delete the copy constructor and copy assignment operator to make sure that any downstream\n\t// code that manipulates modules doesn't accidentally depend on their availability.\n\tmodule(const module &) = delete;\n\tmodule &operator=(const module &) = delete;\n\n\tmodule(module &&) = default;\n\tmodule &operator=(module &&) = default;\n\n\tvirtual void reset() = 0;\n\n\t// The `eval()` callback object, `performer`, is included in the virtual call signature since\n\t// the generated code has broadly identical performance properties.\n\tvirtual bool eval(performer *performer = nullptr) = 0;\n\n\t// The `commit()` callback object, `observer`, is not included in the virtual call signature since\n\t// the generated code is severely pessimized by it. To observe commit events, the non-virtual\n\t// `commit(observer *)` overload must be called directly on a `module` subclass.\n\tvirtual bool commit() = 0;\n\n\tsize_t step(performer *performer = nullptr) {\n\t\tsize_t deltas = 0;\n\t\tbool converged = false;\n\t\tdo {\n\t\t\tconverged = eval(performer);\n\t\t\tdeltas++;\n\t\t} while (commit() && !converged);\n\t\treturn deltas;\n\t}\n\n\tvirtual void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) {\n\t\t(void)items, (void)scopes, (void)path, (void)cell_attrs;\n\t}\n\n\t// Compatibility method.\n#if __has_attribute(deprecated)\n\t__attribute__((deprecated(\"Use `debug_info(&items, /*scopes=*/nullptr, path);` instead.\")))\n#endif\n\tvoid debug_info(debug_items &items, std::string path) {\n\t\tdebug_info(&items, /*scopes=*/nullptr, path);\n\t}\n};\n\n} // namespace cxxrtl\n\n// Internal structures used to communicate with the implementation of the C interface.\n\ntypedef struct _cxxrtl_toplevel {\n\tstd::unique_ptr<cxxrtl::module> module;\n} *cxxrtl_toplevel;\n\ntypedef struct _cxxrtl_outline {\n\tstd::function<void()> eval;\n} *cxxrtl_outline;\n\n// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic\n// and indepenent of Yosys implementation details.\n//\n// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these\n// functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,\n// whereas basic operations on arbitrary width values require operands to be of the same width. These functions\n// bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`\n// if the corresponding operand is unsigned, and `s` if it is signed.\nnamespace cxxrtl_yosys {\n\nusing namespace cxxrtl;\n\n// std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.\ntemplate<class T>\nCXXRTL_ALWAYS_INLINE\nconstexpr T max(const T &a, const T &b) {\n\treturn a > b ? a : b;\n}\n\n// Logic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_not(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };\n}\n\n// Reduction operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_and(const value<BitsA> &a) {\n\treturn value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_or(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xnor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_bool(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\n// Bitwise operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_and(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_or(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.sshr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_us<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_ss<BitsY>(a, b);\n}\n\n// Comparison operations\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\n// Arithmetic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().add(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().add(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().sub(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().sub(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;\n\treturn a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template zext<Bits>();\n\tvalue<Bits> divisor = b.template zext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template sext<Bits>();\n\tvalue<Bits> divisor = b.template sext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.sdivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\n// GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and\n// a=b*N+r where N is some integer\n// In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0\n// then return the remainder + b\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> r;\n\tr = divmod_ss<BitsY>(a, b).second;\n\tif((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn add_ss<BitsY>(b, r);\n\treturn r;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\n// Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.\n// In other words, returns (truncating) a/b, except if a and b have different signs\n// and there's non-zero remainder, subtract one more towards floor.\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> q, r;\n\tstd::tie(q, r) = divmod_ss<BitsY>(a, b);\n\tif ((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn sub_uu<BitsY>(q, value<1> { 1u });\n\treturn q;\n\n}\n\n// Memory helper\nstruct memory_index {\n\tbool valid;\n\tsize_t index;\n\n\ttemplate<size_t BitsAddr>\n\tmemory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {\n\t\tstatic_assert(value<BitsAddr>::chunks <= 1, \"memory address is too wide\");\n\t\tsize_t offset_index = addr.data[0];\n\n\t\tvalid = (offset_index >= offset && offset_index < offset + depth);\n\t\tindex = offset_index - offset;\n\t}\n};\n\n} // namespace cxxrtl_yosys\n\n#endif\n",
141
+ "cxxrtl.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.\n//\n// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides\n// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass\n// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler\n// to unwrap the abstraction and generate efficient code.\n\n#ifndef CXXRTL_H\n#define CXXRTL_H\n\n#include <cstddef>\n#include <cstdint>\n#include <cstring>\n#include <cassert>\n#include <limits>\n#include <type_traits>\n#include <tuple>\n#include <vector>\n#include <map>\n#include <algorithm>\n#include <memory>\n#include <functional>\n#include <sstream>\n#include <iostream>\n\n// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifndef __has_attribute\n#\tdefine __has_attribute(x) 0\n#endif\n\n// CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.\n// It generates a lot of specialized template functions with relatively large bodies that, when inlined\n// into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.\n// Because of this, most of the CXXRTL runtime must be always inlined for best performance.\n#if __has_attribute(always_inline)\n#define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))\n#else\n#define CXXRTL_ALWAYS_INLINE inline\n#endif\n// Conversely, some functions in the generated code are extremely large yet very cold, with both of these\n// properties being extreme enough to confuse C++ compilers into spending pathological amounts of time\n// on a futile (the code becomes worse) attempt to optimize the least important parts of code.\n#if __has_attribute(optnone)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))\n#elif __has_attribute(optimize)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))\n#else\n#define CXXRTL_EXTREMELY_COLD\n#endif\n\n// CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior\n// of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at\n// most result in undefined simulation results).\n//\n// Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating\n// the simulation into another process that should survive violating RTL contracts.\n#ifndef CXXRTL_ASSERT\n#ifndef CXXRTL_NDEBUG\n#define CXXRTL_ASSERT(x) assert(x)\n#else\n#define CXXRTL_ASSERT(x)\n#endif\n#endif\n\nnamespace cxxrtl {\n\n// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size\n// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving\n// and introspecting the simulation in Python.\n//\n// It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on\n// narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.\n// However, (a) most of our operations do not change those bits in the first place because of invariants that are\n// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.\n// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be\n// clobbered results in simpler generated code.\ntypedef uint32_t chunk_t;\ntypedef uint64_t wide_chunk_t;\n\ntemplate<typename T>\nstruct chunk_traits {\n\tstatic_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,\n\t \"chunk type must be an unsigned integral type\");\n\tusing type = T;\n\tstatic constexpr size_t bits = std::numeric_limits<T>::digits;\n\tstatic constexpr T mask = std::numeric_limits<T>::max();\n};\n\ntemplate<class T>\nstruct expr_base;\n\ntemplate<size_t Bits>\nstruct value : public expr_base<value<Bits>> {\n\tstatic constexpr size_t bits = Bits;\n\n\tusing chunk = chunk_traits<chunk_t>;\n\tstatic constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask\n\t\t: chunk::mask >> (chunk::bits - (Bits % chunk::bits));\n\n\tstatic constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;\n\tchunk::type data[chunks] = {};\n\n\tvalue() = default;\n\ttemplate<typename... Init>\n\texplicit constexpr value(Init ...init) : data{init...} {}\n\n\tvalue(const value<Bits> &) = default;\n\tvalue<Bits> &operator=(const value<Bits> &) = default;\n\n\tvalue(value<Bits> &&) = default;\n\tvalue<Bits> &operator=(value<Bits> &&) = default;\n\n\t// A (no-op) helper that forces the cast to value<>.\n\tCXXRTL_ALWAYS_INLINE\n\tconst value<Bits> &val() const {\n\t\treturn *this;\n\t}\n\n\tstd::string str() const {\n\t\tstd::stringstream ss;\n\t\tss << *this;\n\t\treturn ss.str();\n\t}\n\n\t// Conversion operations.\n\t//\n\t// These functions ensure that a conversion is never out of range, and should be always used, if at all\n\t// possible, instead of direct manipulation of the `data` member. For very large types, .slice() and\n\t// .concat() can be used to split them into more manageable parts.\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"get<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"get<T>() requires T to be at least as wide as the value is\");\n\t\tIntegerT result = 0;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult |= IntegerT(data[n]) << (n * chunk::bits);\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tauto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();\n\t\tIntegerT result;\n\t\tmemcpy(&result, &unsigned_result, sizeof(IntegerT));\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"set<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"set<T>() requires the value to be at least as wide as T is\");\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tdata[n] = (value >> (n * chunk::bits)) & chunk::mask;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\ttypename std::make_unsigned<IntegerT>::type unsigned_value;\n\t\tmemcpy(&unsigned_value, &value, sizeof(IntegerT));\n\t\tset(unsigned_value);\n\t}\n\n\t// Operations with compile-time parameters.\n\t//\n\t// These operations are used to implement slicing, concatenation, and blitting.\n\t// The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);\n\t// the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> trunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"trunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < result.chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zext() const {\n\t\tstatic_assert(NewBits >= Bits, \"zext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> sext() const {\n\t\tstatic_assert(NewBits >= Bits, \"sext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tif (is_neg()) {\n\t\t\tresult.data[chunks - 1] |= ~msb_mask;\n\t\t\tfor (size_t n = chunks; n < result.chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rtrunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"rtrunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (Bits - NewBits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tif (shift_chunks + result.chunks < chunks) {\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);\n\t\t}\n\t\tfor (size_t n = result.chunks; n > 0; n--) {\n\t\t\tresult.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + n - 1] << (chunk::bits - shift_bits);\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rzext() const {\n\t\tstatic_assert(NewBits >= Bits, \"rzext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (NewBits - Bits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (shift_chunks + chunks < result.chunks)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\t// Bit blit operation, i.e. a partial read-modify-write.\n\ttemplate<size_t Stop, size_t Start>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits> blit(const value<Stop - Start + 1> &source) const {\n\t\tstatic_assert(Stop >= Start, \"blit() may not reverse bit order\");\n\t\tconstexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));\n\t\tconstexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0\n\t\t\t: (chunk::mask << (Stop % chunk::bits + 1));\n\t\tvalue<Bits> masked = *this;\n\t\tif (Start / chunk::bits == Stop / chunk::bits) {\n\t\t\tmasked.data[Start / chunk::bits] &= stop_mask | start_mask;\n\t\t} else {\n\t\t\tmasked.data[Start / chunk::bits] &= start_mask;\n\t\t\tfor (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)\n\t\t\t\tmasked.data[n] = 0;\n\t\t\tmasked.data[Stop / chunk::bits] &= stop_mask;\n\t\t}\n\t\tvalue<Bits> shifted = source\n\t\t\t.template rzext<Stop + 1>()\n\t\t\t.template zext<Bits>();\n\t\treturn masked.bit_or(shifted);\n\t}\n\n\t// Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower\n\t// than the operand. In C++17 these can be replaced with `if constexpr`.\n\ttemplate<size_t NewBits, typename = void>\n\tstruct zext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template zext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits, typename = void>\n\tstruct sext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template sext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zcast() const {\n\t\treturn zext_cast<NewBits>()(*this);\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> scast() const {\n\t\treturn sext_cast<NewBits>()(*this);\n\t}\n\n\t// Bit replication is far more efficient than the equivalent concatenation.\n\ttemplate<size_t Count>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits * Count> repeat() const {\n\t\tstatic_assert(Bits == 1, \"repeat() is implemented only for 1-bit values\");\n\t\treturn *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();\n\t}\n\n\t// Operations with run-time parameters (offsets, amounts, etc).\n\t//\n\t// These operations are used for computations.\n\tbool bit(size_t offset) const {\n\t\treturn data[offset / chunk::bits] & (1 << (offset % chunk::bits));\n\t}\n\n\tvoid set_bit(size_t offset, bool value = true) {\n\t\tsize_t offset_chunks = offset / chunk::bits;\n\t\tsize_t offset_bits = offset % chunk::bits;\n\t\tdata[offset_chunks] &= ~(1 << offset_bits);\n\t\tdata[offset_chunks] |= value ? 1 << offset_bits : 0;\n\t}\n\n\texplicit operator bool() const {\n\t\treturn !is_zero();\n\t}\n\n\tbool is_zero() const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool is_neg() const {\n\t\treturn data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));\n\t}\n\n\tbool operator ==(const value<Bits> &other) const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != other.data[n])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator !=(const value<Bits> &other) const {\n\t\treturn !(*this == other);\n\t}\n\n\tvalue<Bits> bit_not() const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = ~data[n];\n\t\tresult.data[chunks - 1] &= msb_mask;\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_and(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] & other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_or(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] | other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_xor(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] ^ other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {\n\t\treturn bit_and(mask.bit_not()).bit_or(val.bit_and(mask));\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> shl(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shl() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn {};\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn {};\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits, bool Signed = false>\n\tvalue<Bits> shr(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shr() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Signed && is_neg()) {\n\t\t\tsize_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;\n\t\t\tsize_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;\n\t\t\tfor (size_t n = top_chunk_idx + 1; n < chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tif (amount.data[0] != 0)\n\t\t\t\tresult.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> sshr(const value<AmountBits> &amount) const {\n\t\treturn shr<AmountBits, /*Signed=*/true>(amount);\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> bmux(const value<SelBits> &sel) const {\n\t\tstatic_assert(ResultBits << SelBits == Bits, \"invalid sizes used in bmux()\");\n\t\tsize_t amount = sel.data[0] * ResultBits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tif (ResultBits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tcarry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> demux(const value<SelBits> &sel) const {\n\t\tstatic_assert(Bits << SelBits == ResultBits, \"invalid sizes used in demux()\");\n\t\tsize_t amount = sel.data[0] * Bits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Bits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\tsize_t ctpop() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\t// This loop implements the population count idiom as recognized by LLVM and GCC.\n\t\t\tfor (chunk::type x = data[n]; x != 0; count++)\n\t\t\t\tx = x & (x - 1);\n\t\t}\n\t\treturn count;\n\t}\n\n\tsize_t ctlz() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tchunk::type x = data[chunks - 1 - n];\n\t\t\t// First add to `count` as if the chunk is zero\n\t\t\tconstexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;\n\t\t\tcount += (n == 0 ? msb_chunk_bits : chunk::bits);\n\t\t\t// If the chunk isn't zero, correct the `count` value and return\n\t\t\tif (x != 0) {\n\t\t\t\tfor (; x != 0; count--)\n\t\t\t\t\tx >>= 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\treturn count;\n\t}\n\n\ttemplate<bool Invert, bool CarryIn>\n\tstd::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry = CarryIn;\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;\n\t\t\tif (result.chunks - 1 == n)\n\t\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t\tcarry = (result.data[n] < data[n]) ||\n\t\t\t (result.data[n] == data[n] && carry);\n\t\t}\n\t\treturn {result, carry};\n\t}\n\n\tvalue<Bits> add(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/false, /*CarryIn=*/false>(other).first;\n\t}\n\n\tvalue<Bits> sub(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/true, /*CarryIn=*/true>(other).first;\n\t}\n\n\tvalue<Bits> neg() const {\n\t\treturn value<Bits>().sub(*this);\n\t}\n\n\tbool ucmp(const value<Bits> &other) const {\n\t\tbool carry;\n\t\tstd::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\treturn !carry; // a.ucmp(b) ≡ a u< b\n\t}\n\n\tbool scmp(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry;\n\t\tstd::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\tbool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());\n\t\treturn result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b\n\t}\n\n\ttemplate<size_t ResultBits>\n\tvalue<ResultBits> mul(const value<Bits> &other) const {\n\t\tvalue<ResultBits> result;\n\t\twide_chunk_t wide_result[result.chunks + 1] = {};\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tfor (size_t m = 0; m < chunks && n + m < result.chunks; m++) {\n\t\t\t\twide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);\n\t\t\t\twide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;\n\t\t\t\twide_result[n + m] &= chunk::mask;\n\t\t\t}\n\t\t}\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = wide_result[n];\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {\n\t\tvalue<Bits> quotient;\n\t\tvalue<Bits> dividend = *this;\n\t\tif (dividend.ucmp(divisor))\n\t\t\treturn {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};\n\t\tint64_t divisor_shift = divisor.ctlz() - dividend.ctlz();\n\t\tassert(divisor_shift >= 0);\n\t\tdivisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});\n\t\tfor (size_t step = 0; step <= divisor_shift; step++) {\n\t\t\tquotient = quotient.shl(value<Bits>{1u});\n\t\t\tif (!dividend.ucmp(divisor)) {\n\t\t\t\tdividend = dividend.sub(divisor);\n\t\t\t\tquotient.set_bit(0, true);\n\t\t\t}\n\t\t\tdivisor = divisor.shr(value<Bits>{1u});\n\t\t}\n\t\treturn {quotient, /*remainder=*/dividend};\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {\n\t\tvalue<Bits + 1> quotient;\n\t\tvalue<Bits + 1> remainder;\n\t\tvalue<Bits + 1> dividend = sext<Bits + 1>();\n\t\tvalue<Bits + 1> divisor = other.template sext<Bits + 1>();\n\t\tif (is_neg()) dividend = dividend.neg();\n\t\tif (other.is_neg()) divisor = divisor.neg();\n\t\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\t\tif (is_neg() != other.is_neg()) quotient = quotient.neg();\n\t\tif (is_neg()) remainder = remainder.neg();\n\t\treturn {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};\n\t}\n};\n\n// Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, size_t Stop, size_t Start>\nstruct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {\n\tstatic_assert(Stop >= Start, \"slice_expr() may not reverse bit order\");\n\tstatic_assert(Start < T::bits && Stop < T::bits, \"slice_expr() must be within bounds\");\n\tstatic constexpr size_t bits = Stop - Start + 1;\n\n\tT &expr;\n\n\tslice_expr(T &expr) : expr(expr) {}\n\tslice_expr(const slice_expr<T, Stop, Start> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\treturn static_cast<const value<T::bits> &>(expr)\n\t\t\t.template rtrunc<T::bits - Start>()\n\t\t\t.template trunc<bits>();\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {\n\t\t// Generic partial assignment implemented using a read-modify-write operation on the sliced expression.\n\t\texpr = static_cast<const value<T::bits> &>(expr)\n\t\t\t.template blit<Stop, Start>(rhs);\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, class U>\nstruct concat_expr : public expr_base<concat_expr<T, U>> {\n\tstatic constexpr size_t bits = T::bits + U::bits;\n\n\tT &ms_expr;\n\tU &ls_expr;\n\n\tconcat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}\n\tconcat_expr(const concat_expr<T, U> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\tvalue<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)\n\t\t\t.template rzext<bits>();\n\t\tvalue<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)\n\t\t\t.template zext<bits>();\n\t\treturn ms_shifted.bit_or(ls_extended);\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, U> &operator=(const value<bits> &rhs) {\n\t\tms_expr = rhs.template rtrunc<T::bits>();\n\t\tls_expr = rhs.template trunc<U::bits>();\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.\n//\n// Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because\n// they refer to temporaries that will, in general, only live until the end of the statement. For example, both of\n// these snippets perform use-after-free:\n//\n// const auto &a = val.slice<7,0>().slice<1>();\n// value<1> b = a;\n//\n// auto &&c = val.slice<7,0>().slice<1>();\n// c = value<1>{1u};\n//\n// An easy way to write code using slices and concatenations safely is to follow two simple rules:\n// * Never explicitly name any type except `value<W>` or `const value<W> &`.\n// * Never use a `const auto &` or `auto &&` in any such expression.\n// Then, any code that compiles will be well-defined.\ntemplate<class T>\nstruct expr_base {\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<const T, Stop, Start> slice() const {\n\t\treturn {*static_cast<const T *>(this)};\n\t}\n\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> slice() {\n\t\treturn {*static_cast<T *>(this)};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {\n\t\treturn {*static_cast<const T *>(this), other};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {\n\t\treturn {*static_cast<T *>(this), other};\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const value<Bits> &val) {\n\tauto old_flags = os.flags(std::ios::right);\n\tauto old_width = os.width(0);\n\tauto old_fill = os.fill('0');\n\tos << val.bits << '\\'' << std::hex;\n\tfor (size_t n = val.chunks - 1; n != (size_t)-1; n--) {\n\t\tif (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)\n\t\t\tos.width((Bits % value<Bits>::chunk::bits + 3) / 4);\n\t\telse\n\t\t\tos.width((value<Bits>::chunk::bits + 3) / 4);\n\t\tos << val.data[n];\n\t}\n\tos.fill(old_fill);\n\tos.width(old_width);\n\tos.flags(old_flags);\n\treturn os;\n}\n\ntemplate<size_t Bits>\nstruct wire {\n\tstatic constexpr size_t bits = Bits;\n\n\tvalue<Bits> curr;\n\tvalue<Bits> next;\n\n\twire() = default;\n\texplicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}\n\ttemplate<typename... Init>\n\texplicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}\n\n\t// Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,\n\t// e.g. because a module is built with a different optimization level, then existing code could\n\t// unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure\n\t// this doesn't happen, prohibit copying and copy-assigning wires.\n\twire(const wire<Bits> &) = delete;\n\twire<Bits> &operator=(const wire<Bits> &) = delete;\n\n\twire(wire<Bits> &&) = default;\n\twire<Bits> &operator=(wire<Bits> &&) = default;\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\treturn curr.template get<IntegerT>();\n\t}\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT other) {\n\t\tnext.template set<IntegerT>(other);\n\t}\n\n\t// This method intentionally takes a mandatory argument (to make it more difficult to misuse in\n\t// black box implementations, leading to missed observer events). It is generic over its argument\n\t// to allow the `on_update` method to be non-virtual.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tif (curr != next) {\n\t\t\tobserver.on_update(curr.chunks, curr.data, next.data);\n\t\t\tcurr = next;\n\t\t\treturn true;\n\t\t}\n\t\treturn false;\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {\n\tos << val.curr;\n\treturn os;\n}\n\ntemplate<size_t Width>\nstruct memory {\n\tconst size_t depth;\n\tstd::unique_ptr<value<Width>[]> data;\n\n\texplicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}\n\n\tmemory(const memory<Width> &) = delete;\n\tmemory<Width> &operator=(const memory<Width> &) = delete;\n\n\tmemory(memory<Width> &&) = default;\n\tmemory<Width> &operator=(memory<Width> &&other) {\n\t\tassert(depth == other.depth);\n\t\tdata = std::move(other.data);\n\t\twrite_queue = std::move(other.write_queue);\n\t\treturn *this;\n\t}\n\n\t// An operator for direct memory reads. May be used at any time during the simulation.\n\tconst value<Width> &operator [](size_t index) const {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// An operator for direct memory writes. May only be used before the simulation is started. If used\n\t// after the simulation is started, the design may malfunction.\n\tvalue<Width> &operator [](size_t index) {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// A simple way to make a writable memory would be to use an array of wires instead of an array of values.\n\t// However, there are two significant downsides to this approach: first, it has large overhead (2× space\n\t// overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port\n\t// priorities. Although in principle write ports could be ordered or conditionally enabled in generated\n\t// code based on their priorities and selected addresses, the feedback arc set problem is computationally\n\t// expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)\n\t// a particular write port evaluation order.\n\t//\n\t// The approach used here instead is to queue writes into a buffer during the eval phase, then perform\n\t// the writes during the commit phase in the priority order. This approach has low overhead, with both space\n\t// and time proportional to the amount of write ports. Because virtually every memory in a practical design\n\t// has at most two write ports, linear search is used on every write, being the fastest and simplest approach.\n\tstruct write {\n\t\tsize_t index;\n\t\tvalue<Width> val;\n\t\tvalue<Width> mask;\n\t\tint priority;\n\t};\n\tstd::vector<write> write_queue;\n\n\tvoid update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {\n\t\tassert(index < depth);\n\t\t// Queue up the write while keeping the queue sorted by priority.\n\t\twrite_queue.insert(\n\t\t\tstd::upper_bound(write_queue.begin(), write_queue.end(), priority,\n\t\t\t\t[](const int a, const write& b) { return a < b.priority; }),\n\t\t\twrite { index, val, mask, priority });\n\t}\n\n\t// See the note for `wire::commit()`.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tbool changed = false;\n\t\tfor (const write &entry : write_queue) {\n\t\t\tvalue<Width> elem = data[entry.index];\n\t\t\telem = elem.update(entry.val, entry.mask);\n\t\t\tif (data[entry.index] != elem) {\n\t\t\t\tobserver.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);\n\t\t\t\tchanged |= true;\n\t\t\t}\n\t\t\tdata[entry.index] = elem;\n\t\t}\n\t\twrite_queue.clear();\n\t\treturn changed;\n\t}\n};\n\nstruct metadata {\n\tconst enum {\n\t\tMISSING = 0,\n\t\tUINT \t= 1,\n\t\tSINT \t= 2,\n\t\tSTRING \t= 3,\n\t\tDOUBLE \t= 4,\n\t} value_type;\n\n\t// In debug mode, using the wrong .as_*() function will assert.\n\t// In release mode, using the wrong .as_*() function will safely return a default value.\n\tconst uint64_t uint_value = 0;\n\tconst int64_t sint_value = 0;\n\tconst std::string string_value = \"\";\n\tconst double double_value = 0.0;\n\n\tmetadata() : value_type(MISSING) {}\n\tmetadata(uint64_t value) : value_type(UINT), uint_value(value) {}\n\tmetadata(int64_t value) : value_type(SINT), sint_value(value) {}\n\tmetadata(const std::string &value) : value_type(STRING), string_value(value) {}\n\tmetadata(const char *value) : value_type(STRING), string_value(value) {}\n\tmetadata(double value) : value_type(DOUBLE), double_value(value) {}\n\n\tmetadata(const metadata &) = default;\n\tmetadata &operator=(const metadata &) = delete;\n\n\tuint64_t as_uint() const {\n\t\tassert(value_type == UINT);\n\t\treturn uint_value;\n\t}\n\n\tint64_t as_sint() const {\n\t\tassert(value_type == SINT);\n\t\treturn sint_value;\n\t}\n\n\tconst std::string &as_string() const {\n\t\tassert(value_type == STRING);\n\t\treturn string_value;\n\t}\n\n\tdouble as_double() const {\n\t\tassert(value_type == DOUBLE);\n\t\treturn double_value;\n\t}\n\n\t// Internal CXXRTL use only.\n\tstatic std::map<std::string, metadata> deserialize(const char *ptr) {\n\t\tstd::map<std::string, metadata> result;\n\t\tstd::string name;\n\t\t// Grammar:\n\t\t// string ::= [^\\0]+ \\0\n\t\t// metadata ::= [uid] .{8} | s <string>\n\t\t// map ::= ( <string> <metadata> )* \\0\n\t\tfor (;;) {\n\t\t\tif (*ptr) {\n\t\t\t\tname += *ptr++;\n\t\t\t} else if (!name.empty()) {\n\t\t\t\tptr++;\n\t\t\t\tauto get_u64 = [&]() {\n\t\t\t\t\tuint64_t result = 0;\n\t\t\t\t\tfor (size_t count = 0; count < 8; count++)\n\t\t\t\t\t\tresult = (result << 8) | *ptr++;\n\t\t\t\t\treturn result;\n\t\t\t\t};\n\t\t\t\tchar type = *ptr++;\n\t\t\t\tif (type == 'u') {\n\t\t\t\t\tuint64_t value = get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'i') {\n\t\t\t\t\tint64_t value = (int64_t)get_u64();\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else if (type == 'd') {\n\t\t\t\t\tdouble dvalue;\n\t\t\t\t\tuint64_t uvalue = get_u64();\n\t\t\t\t\tstatic_assert(sizeof(dvalue) == sizeof(uvalue), \"double must be 64 bits in size\");\n\t\t\t\t\tmemcpy(&dvalue, &uvalue, sizeof(dvalue));\n\t\t\t\t\tresult.emplace(name, dvalue);\n\t\t\t\t} else if (type == 's') {\n\t\t\t\t\tstd::string value;\n\t\t\t\t\twhile (*ptr)\n\t\t\t\t\t\tvalue += *ptr++;\n\t\t\t\t\tptr++;\n\t\t\t\t\tresult.emplace(name, value);\n\t\t\t\t} else {\n\t\t\t\t\tassert(false && \"Unknown type specifier\");\n\t\t\t\t\treturn result;\n\t\t\t\t}\n\t\t\t\tname.clear();\n\t\t\t} else {\n\t\t\t\treturn result;\n\t\t\t}\n\t\t}\n\t}\n};\n\ntypedef std::map<std::string, metadata> metadata_map;\n\nstruct performer;\n\n// An object that allows formatting a string lazily.\nstruct lazy_fmt {\n\tvirtual std::string operator() () const = 0;\n};\n\n// Flavor of a `$check` cell.\nenum class flavor {\n\t// Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement.\n\tASSERT,\n\t// Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement.\n\tASSUME,\n\t// Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement.\n\tASSERT_EVENTUALLY,\n\t// Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement.\n\tASSUME_EVENTUALLY,\n\t// Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement.\n\tCOVER,\n};\n\n// An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented\n// below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not\n// taken into account.\nstruct performer {\n\t// Called by generated formatting code to evaluate a Verilog `$time` expression.\n\tvirtual int64_t vlog_time() const { return 0; }\n\n\t// Called by generated formatting code to evaluate a Verilog `$realtime` expression.\n\tvirtual double vlog_realtime() const { return vlog_time(); }\n\n\t// Called when a `$print` cell is triggered.\n\tvirtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tstd::cout << formatter();\n\t}\n\n\t// Called when a `$check` cell is triggered.\n\tvirtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tif (type == flavor::ASSERT || type == flavor::ASSUME) {\n\t\t\tif (!condition)\n\t\t\t\tstd::cerr << formatter();\n\t\t\tCXXRTL_ASSERT(condition && \"Check failed\");\n\t\t}\n\t}\n};\n\n// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in\n// the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and\n// a comparatively heavyweight template-based solution is justified.\nstruct observer {\n\t// Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks\n\t// at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and\n\t// `base` points to the first chunk.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}\n\n\t// Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`\n\t// with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to\n\t// the memory element chunk count and `base` points to the first chunk of the first element of the memory.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}\n};\n\n// Must be kept in sync with `struct FmtPart` in kernel/fmt.h!\n// Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.\nstruct fmt_part {\n\tenum {\n\t\tLITERAL = 0,\n\t\tINTEGER = 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\t// + value<Bits> val;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify; // = RIGHT;\n\tchar padding; // = '\\0';\n\tsize_t width; // = 0;\n\n\t// INTEGER type\n\tunsigned base; // = 10;\n\tbool signed_; // = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign; // = MINUS;\n\tbool hex_upper; // = false;\n\tbool show_base; // = false;\n\tbool group; // = false;\n\n\t// VLOG_TIME type\n\tbool realtime; // = false;\n\t// + int64_t itime;\n\t// + double ftime;\n\n\t// Format the part as a string.\n\t//\n\t// The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.\n\ttemplate<size_t Bits>\n\tstd::string render(value<Bits> val, performer *performer = nullptr)\n\t{\n\t\t// We might want to replace some of these bit() calls with direct\n\t\t// chunk access if it turns out to be slow enough to matter.\n\t\tstd::string buf;\n\t\tstd::string prefix;\n\t\tswitch (type) {\n\t\t\tcase LITERAL:\n\t\t\t\treturn str;\n\n\t\t\tcase STRING: {\n\t\t\t\tbuf.reserve(Bits/8);\n\t\t\t\tfor (int i = 0; i < Bits; i += 8) {\n\t\t\t\t\tchar ch = 0;\n\t\t\t\t\tfor (int j = 0; j < 8 && i + j < int(Bits); j++)\n\t\t\t\t\t\tif (val.bit(i + j))\n\t\t\t\t\t\t\tch |= 1 << j;\n\t\t\t\t\tif (ch != 0)\n\t\t\t\t\t\tbuf.append({ch});\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase UNICHAR: {\n\t\t\t\tuint32_t codepoint = val.template zcast<32>().template get<uint32_t>();\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0xf0 | (codepoint >> 18));\n\t\t\t\telse if (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0xe0 | (codepoint >> 12));\n\t\t\t\telse if (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0xc0 | (codepoint >> 6));\n\t\t\t\telse\n\t\t\t\t\tbuf += (char)codepoint;\n\t\t\t\tif (codepoint >= 0x10000)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 12) & 0x3f));\n\t\t\t\tif (codepoint >= 0x800)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 6) & 0x3f));\n\t\t\t\tif (codepoint >= 0x80)\n\t\t\t\t\tbuf += (char)(0x80 | ((codepoint >> 0) & 0x3f));\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase INTEGER: {\n\t\t\t\tbool negative = signed_ && val.is_neg();\n\t\t\t\tif (negative) {\n\t\t\t\t\tprefix = \"-\";\n\t\t\t\t\tval = val.neg();\n\t\t\t\t} else {\n\t\t\t\t\tswitch (sign) {\n\t\t\t\t\t\tcase MINUS: break;\n\t\t\t\t\t\tcase PLUS_MINUS: prefix = \"+\"; break;\n\t\t\t\t\t\tcase SPACE_MINUS: prefix = \" \"; break;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tsize_t val_width = Bits;\n\t\t\t\tif (base != 10) {\n\t\t\t\t\tval_width = 1;\n\t\t\t\t\tfor (size_t index = 0; index < Bits; index++)\n\t\t\t\t\t\tif (val.bit(index))\n\t\t\t\t\t\t\tval_width = index + 1;\n\t\t\t\t}\n\n\t\t\t\tif (base == 2) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0b\";\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index++) {\n\t\t\t\t\t\tif (group && index > 0 && index % 4 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += (val.bit(index) ? '1' : '0');\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 8 || base == 16) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += (base == 16) ? (hex_upper ? \"0X\" : \"0x\") : \"0o\";\n\t\t\t\t\tsize_t step = (base == 16) ? 4 : 3;\n\t\t\t\t\tfor (size_t index = 0; index < val_width; index += step) {\n\t\t\t\t\t\tif (group && index > 0 && index % (4 * step) == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tuint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);\n\t\t\t\t\t\tif (step == 4)\n\t\t\t\t\t\t\tvalue |= val.bit(index + 3) << 3;\n\t\t\t\t\t\tbuf += (hex_upper ? \"0123456789ABCDEF\" : \"0123456789abcdef\")[value];\n\t\t\t\t\t}\n\t\t\t\t} else if (base == 10) {\n\t\t\t\t\tif (show_base)\n\t\t\t\t\t\tprefix += \"0d\";\n\t\t\t\t\tif (val.is_zero())\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();\n\t\t\t\t\tsize_t index = 0;\n\t\t\t\t\twhile (!xval.is_zero()) {\n\t\t\t\t\t\tif (group && index > 0 && index % 3 == 0)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> quotient, remainder;\n\t\t\t\t\t\tif (Bits >= 4)\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);\n\t\t\t\t\t\tbuf += '0' + remainder.template trunc<4>().template get<uint8_t>();\n\t\t\t\t\t\txval = quotient;\n\t\t\t\t\t\tindex++;\n\t\t\t\t\t}\n\t\t\t\t} else assert(false && \"Unsupported base for fmt_part\");\n\t\t\t\tif (justify == NUMERIC && group && padding == '0') {\n\t\t\t\t\tint group_size = base == 10 ? 3 : 4;\n\t\t\t\t\twhile (prefix.size() + buf.size() < width) {\n\t\t\t\t\t\tif (buf.size() % (group_size + 1) == group_size)\n\t\t\t\t\t\t\tbuf += '_';\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase VLOG_TIME: {\n\t\t\t\tif (performer) {\n\t\t\t\t\tbuf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());\n\t\t\t\t} else {\n\t\t\t\t\tbuf = realtime ? std::to_string(0.0) : std::to_string(0);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tstd::string str;\n\t\tassert(width == 0 || padding != '\\0');\n\t\tif (prefix.size() + buf.size() < width) {\n\t\t\tsize_t pad_width = width - prefix.size() - buf.size();\n\t\t\tswitch (justify) {\n\t\t\t\tcase LEFT:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tbreak;\n\t\t\t\tcase RIGHT:\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\tcase NUMERIC:\n\t\t\t\t\tstr += prefix;\n\t\t\t\t\tstr += std::string(pad_width, padding);\n\t\t\t\t\tstr += buf;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t} else {\n\t\t\tstr += prefix;\n\t\t\tstr += buf;\n\t\t}\n\t\treturn str;\n\t}\n};\n\n// Tag class to disambiguate values/wires and their aliases.\nstruct debug_alias {};\n\n// Tag declaration to disambiguate values and debug outlines.\nusing debug_outline = ::_cxxrtl_outline;\n\n// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.\n// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.\n//\n// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used\n// in the C API, or it would not be possible to cast between the pointers to these.\n//\n// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created\n// from external C code.\nstruct debug_item : ::cxxrtl_object {\n\t// Object types.\n\tenum : uint32_t {\n\t\tVALUE = CXXRTL_VALUE,\n\t\tWIRE = CXXRTL_WIRE,\n\t\tMEMORY = CXXRTL_MEMORY,\n\t\tALIAS = CXXRTL_ALIAS,\n\t\tOUTLINE = CXXRTL_OUTLINE,\n\t};\n\n\t// Object flags.\n\tenum : uint32_t {\n\t\tINPUT = CXXRTL_INPUT,\n\t\tOUTPUT = CXXRTL_OUTPUT,\n\t\tINOUT = CXXRTL_INOUT,\n\t\tDRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,\n\t\tDRIVEN_COMB = CXXRTL_DRIVEN_COMB,\n\t\tUNDRIVEN = CXXRTL_UNDRIVEN,\n\t};\n\n\tdebug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}\n\n\ttemplate<size_t Bits>\n\tdebug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.data;\n\t\tnext = item.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = WIRE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.curr.data;\n\t\tnext = item.next.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Width>\n\tdebug_item(memory<Width> &item, size_t zero_offset = 0) {\n\t\tstatic_assert(Width == 0 || sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),\n\t\t \"memory<Width> is not compatible with C layout\");\n\t\ttype = MEMORY;\n\t\tflags = 0;\n\t\twidth = Width;\n\t\tlsb_at = 0;\n\t\tdepth = item.depth;\n\t\tzero_at = zero_offset;\n\t\tcurr = item.data ? item.data[0].data : nullptr;\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 ||\n\t\t (sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t)),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.curr.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(Bits == 0 || sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = OUTLINE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = &group;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tIntegerT get() const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\tstd::copy(curr, curr + value<Bits>::chunks, item.data);\n\t\treturn item.template get<IntegerT>();\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tvoid set(IntegerT other) const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\titem.template set<IntegerT>(other);\n\t\tstd::copy(item.data, item.data + value<Bits>::chunks, next);\n\t}\n};\nstatic_assert(std::is_standard_layout<debug_item>::value, \"debug_item is not compatible with C layout\");\n\n} // namespace cxxrtl\n\ntypedef struct _cxxrtl_attr_set {\n\tcxxrtl::metadata_map map;\n} *cxxrtl_attr_set;\n\nnamespace cxxrtl {\n\n// Representation of an attribute set in the C++ interface.\nusing debug_attrs = ::_cxxrtl_attr_set;\n\nstruct debug_items {\n\t// Debug items may be composed of multiple parts, but the attributes are shared between all of them.\n\t// There are additional invariants, not all of which are not checked by this code:\n\t// - Memories and non-memories cannot be mixed together.\n\t// - Bit indices (considering `lsb_at` and `width`) must not overlap.\n\t// - Row indices (considering `depth` and `zero_at`) must be the same.\n\t// - The `INPUT` and `OUTPUT` flags must be the same for all parts.\n\t// Other than that, the parts can be quite different, e.g. it is OK to mix a value, a wire, an alias,\n\t// and an outline, in the debug information for a single name in four parts.\n\tstd::map<std::string, std::vector<debug_item>> table;\n\tstd::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;\n\n\tvoid add(const std::string &path, debug_item &&item, metadata_map &&item_attrs = {}) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tstd::unique_ptr<debug_attrs> &attrs = attrs_table[path];\n\t\tif (attrs.get() == nullptr)\n\t\t\tattrs = std::unique_ptr<debug_attrs>(new debug_attrs);\n\t\tfor (auto attr : item_attrs)\n\t\t\tattrs->map.insert(attr);\n\t\titem.attrs = attrs.get();\n\t\tstd::vector<debug_item> &parts = table[path];\n\t\tparts.emplace_back(item);\n\t\tstd::sort(parts.begin(), parts.end(),\n\t\t\t[](const debug_item &a, const debug_item &b) {\n\t\t\t\treturn a.lsb_at < b.lsb_at;\n\t\t\t});\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\ttemplate<class... T>\n\tvoid add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {\n\t\tadd(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));\n\t}\n\n\tsize_t count(const std::string &path) const {\n\t\tif (table.count(path) == 0)\n\t\t\treturn 0;\n\t\treturn table.at(path).size();\n\t}\n\n\tconst std::vector<debug_item> &at(const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n\n\t// Like `at()`, but operates only on single-part debug items.\n\tconst debug_item &operator [](const std::string &path) const {\n\t\tconst std::vector<debug_item> &parts = table.at(path);\n\t\tassert(parts.size() == 1);\n\t\treturn parts.at(0);\n\t}\n\n\tbool is_memory(const std::string &path) const {\n\t\treturn at(path).at(0).type == debug_item::MEMORY;\n\t}\n\n\tconst metadata_map &attrs(const std::string &path) const {\n\t\treturn attrs_table.at(path)->map;\n\t}\n};\n\n// Only `module` scopes are defined. The type is implicit, since Yosys does not currently support\n// any other scope types.\nstruct debug_scope {\n\tstd::string module_name;\n\tstd::unique_ptr<debug_attrs> module_attrs;\n\tstd::unique_ptr<debug_attrs> cell_attrs;\n};\n\nstruct debug_scopes {\n\tstd::map<std::string, debug_scope> table;\n\n\tvoid add(const std::string &path, const std::string &module_name, metadata_map &&module_attrs, metadata_map &&cell_attrs) {\n\t\tassert((path.empty() || path[path.size() - 1] != ' ') && path.find(\" \") == std::string::npos);\n\t\tassert(table.count(path) == 0);\n\t\tdebug_scope &scope = table[path];\n\t\tscope.module_name = module_name;\n\t\tscope.module_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { module_attrs });\n\t\tscope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });\n\t}\n\n\t// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.\n\tvoid add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {\n\t\tadd(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));\n\t}\n\n\tsize_t contains(const std::string &path) const {\n\t\treturn table.count(path);\n\t}\n\n\tconst debug_scope &operator [](const std::string &path) const {\n\t\treturn table.at(path);\n\t}\n};\n\n// Tag class to disambiguate the default constructor used by the toplevel module that calls `reset()`,\n// and the constructor of interior modules that should not call it.\nstruct interior {};\n\n// The core API of the `module` class consists of only four virtual methods: `reset()`, `eval()`,\n// `commit`, and `debug_info()`. (The virtual destructor is made necessary by C++.) Every other method\n// is a convenience method, and exists solely to simplify some common pattern for C++ API consumers.\n// No behavior may be added to such convenience methods that other parts of CXXRTL can rely on, since\n// there is no guarantee they will be called (and, for example, other CXXRTL libraries will often call\n// the `eval()` and `commit()` directly instead, as well as being exposed in the C API).\nstruct module {\n\tmodule() {}\n\tvirtual ~module() {}\n\n\t// Modules with black boxes cannot be copied. Although not all designs include black boxes,\n\t// delete the copy constructor and copy assignment operator to make sure that any downstream\n\t// code that manipulates modules doesn't accidentally depend on their availability.\n\tmodule(const module &) = delete;\n\tmodule &operator=(const module &) = delete;\n\n\tmodule(module &&) = default;\n\tmodule &operator=(module &&) = default;\n\n\tvirtual void reset() = 0;\n\n\t// The `eval()` callback object, `performer`, is included in the virtual call signature since\n\t// the generated code has broadly identical performance properties.\n\tvirtual bool eval(performer *performer = nullptr) = 0;\n\n\t// The `commit()` callback object, `observer`, is not included in the virtual call signature since\n\t// the generated code is severely pessimized by it. To observe commit events, the non-virtual\n\t// `commit(observer *)` overload must be called directly on a `module` subclass.\n\tvirtual bool commit() = 0;\n\n\tsize_t step(performer *performer = nullptr) {\n\t\tsize_t deltas = 0;\n\t\tbool converged = false;\n\t\tdo {\n\t\t\tconverged = eval(performer);\n\t\t\tdeltas++;\n\t\t} while (commit() && !converged);\n\t\treturn deltas;\n\t}\n\n\tvirtual void debug_info(debug_items *items, debug_scopes *scopes, std::string path, metadata_map &&cell_attrs = {}) {\n\t\t(void)items, (void)scopes, (void)path, (void)cell_attrs;\n\t}\n\n\t// Compatibility method.\n#if __has_attribute(deprecated)\n\t__attribute__((deprecated(\"Use `debug_info(&items, /*scopes=*/nullptr, path);` instead.\")))\n#endif\n\tvoid debug_info(debug_items &items, std::string path) {\n\t\tdebug_info(&items, /*scopes=*/nullptr, path);\n\t}\n};\n\n} // namespace cxxrtl\n\n// Internal structures used to communicate with the implementation of the C interface.\n\ntypedef struct _cxxrtl_toplevel {\n\tstd::unique_ptr<cxxrtl::module> module;\n} *cxxrtl_toplevel;\n\ntypedef struct _cxxrtl_outline {\n\tstd::function<void()> eval;\n} *cxxrtl_outline;\n\n// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic\n// and indepenent of Yosys implementation details.\n//\n// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these\n// functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,\n// whereas basic operations on arbitrary width values require operands to be of the same width. These functions\n// bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`\n// if the corresponding operand is unsigned, and `s` if it is signed.\nnamespace cxxrtl_yosys {\n\nusing namespace cxxrtl;\n\n// std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.\ntemplate<class T>\nCXXRTL_ALWAYS_INLINE\nconstexpr T max(const T &a, const T &b) {\n\treturn a > b ? a : b;\n}\n\n// Logic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_not(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };\n}\n\n// Reduction operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_and(const value<BitsA> &a) {\n\treturn value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_or(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xnor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_bool(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\n// Bitwise operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_and(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_or(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.sshr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_us<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_ss<BitsY>(a, b);\n}\n\n// Comparison operations\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\n// Arithmetic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().add(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().add(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().sub(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().sub(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;\n\treturn a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template zext<Bits>();\n\tvalue<Bits> divisor = b.template zext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template sext<Bits>();\n\tvalue<Bits> divisor = b.template sext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.sdivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\n// GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and\n// a=b*N+r where N is some integer\n// In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0\n// then return the remainder + b\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> r;\n\tr = divmod_ss<BitsY>(a, b).second;\n\tif((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn add_ss<BitsY>(b, r);\n\treturn r;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\n// Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.\n// In other words, returns (truncating) a/b, except if a and b have different signs\n// and there's non-zero remainder, subtract one more towards floor.\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> q, r;\n\tstd::tie(q, r) = divmod_ss<BitsY>(a, b);\n\tif ((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn sub_uu<BitsY>(q, value<1> { 1u });\n\treturn q;\n\n}\n\n// Memory helper\nstruct memory_index {\n\tbool valid;\n\tsize_t index;\n\n\ttemplate<size_t BitsAddr>\n\tmemory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {\n\t\tstatic_assert(value<BitsAddr>::chunks <= 1, \"memory address is too wide\");\n\t\tsize_t offset_index = addr.data[0];\n\n\t\tvalid = (offset_index >= offset && offset_index < offset + depth);\n\t\tindex = offset_index - offset;\n\t}\n};\n\n} // namespace cxxrtl_yosys\n\n#endif\n",
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  "cxxrtl_replay.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2023 Catherine <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_REPLAY_H\n#define CXXRTL_REPLAY_H\n\n#if !defined(WIN32)\n#include <unistd.h>\n#define O_BINARY 0\n#else\n#include <io.h>\n#endif\n\n#include <fcntl.h>\n#include <cstring>\n#include <cstdio>\n#include <atomic>\n#include <unordered_map>\n\n#include <cxxrtl/cxxrtl.h>\n#include <cxxrtl/cxxrtl_time.h>\n\n// Theory of operation\n// ===================\n//\n// Log format\n// ----------\n//\n// The replay log is a simple data format based on a sequence of 32-bit words. The following BNF-like grammar describes\n// enough detail to understand the overall structure of the log data and be able to read hex dumps. For a greater\n// degree of detail see the source code. The format is considered fully internal to CXXRTL and is subject to change\n// without notice.\n//\n// <file> ::= <file-header> <definitions> <sample>+\n// <file-header> ::= 0x52585843 0x00004c54\n// <definitions> ::= <packet-define>* <packet-end>\n// <sample> ::= <packet-sample> (<packet-change> | <packet-diag>)* <packet-end>\n// <packet-define> ::= 0xc0000000 ...\n// <packet-sample> ::= 0xc0000001 ...\n// <packet-change> ::= 0x0??????? <chunk>+ | 0x1??????? <index> <chunk>+ | 0x2??????? | 0x3???????\n// <chunk>, <index> ::= 0x????????\n// <packet-diag> ::= <packet-break> | <packet-print> | <packet-assert> | <packet-assume>\n// <packet-break> ::= 0xc0000010 <message> <source-location>\n// <packet-print> ::= 0xc0000011 <message> <source-location>\n// <packet-assert> ::= 0xc0000012 <message> <source-location>\n// <packet-assume> ::= 0xc0000013 <message> <source-location>\n// <packet-end> ::= 0xFFFFFFFF\n//\n// The replay log contains sample data, however, it does not cover the entire design. Rather, it only contains sample\n// data for the subset of debug items containing _design state_: inputs and registers/latches. This keeps its size to\n// a minimum, and recording speed to a maximum. The player samples any missing data by setting the design state items\n// to the same values they had during recording, and re-evaluating the design.\n//\n// Packets for diagnostics (prints, breakpoints, assertions, and assumptions) are used solely for diagnostics emitted\n// by the C++ testbench driving the simulation, and are not recorded while evaluating the design. (Diagnostics emitted\n// by the RTL can be reconstructed at replay time, so recording them would be a waste of space.)\n//\n// Limits\n// ------\n//\n// The log may contain:\n//\n// * Up to 2**28-1 debug items containing design state.\n// * Up to 2**32 chunks per debug item.\n// * Up to 2**32 rows per memory.\n// * Up to 2**32 samples.\n//\n// Of these limits, the last two are most likely to be eventually exceeded by practical recordings. However, other\n// performance considerations will likely limit the size of such practical recordings first, so the log data format\n// will undergo a breaking change at that point.\n//\n// Operations\n// ----------\n//\n// As suggested by the name \"replay log\", this format is designed for recording (writing) once and playing (reading)\n// many times afterwards, such that reading the format can be done linearly and quickly. The log format is designed to\n// support three primary read operations:\n//\n// 1. Initialization\n// 2. Rewinding (to time T)\n// 3. Replaying (for N samples)\n//\n// During initialization, the player establishes the mapping between debug item names and their 28-bit identifiers in\n// the log. It is done once.\n//\n// During rewinding, the player begins reading at the latest non-incremental sample that still lies before the requested\n// sample time. It continues reading incremental samples after that point until it reaches the requested sample time.\n// This process is very cheap as the design is not evaluated; it is essentially a (convoluted) memory copy operation.\n//\n// During replaying, the player evaluates the design at the current time, which causes all debug items to assume\n// the values they had before recording. This process is expensive. Once done, the player advances to the next state\n// by reading the next (complete or incremental) sample, as above. Since a range of samples is replayed, this process\n// is repeated several times in a row.\n//\n// In principle, when replaying, the player could only read the state of the inputs and the time delta and use a normal\n// eval/commit loop to progress the simulation, which is fully deterministic so its calculated design state should be\n// exactly the same as the recorded design state. In practice, it is both faster and more reliable (in presence of e.g.\n// user-defined black boxes) to read the recorded values instead of calculating them.\n//\n// Note: The operations described above are conceptual and do not correspond exactly to methods on `cxxrtl::player`.\n// The `cxxrtl::player::replay()` method does not evaluate the design. This is so that delta cycles could be ignored\n// if they are not of interest while replaying.\n\nnamespace cxxrtl {\n\n// A single diagnostic that can be manipulated as an object (including being written to and read from a file).\n// This differs from the base CXXRTL interface, where diagnostics can only be emitted via a procedure call, and are\n// not materialized as objects.\nstruct diagnostic {\n\t// The `BREAK` flavor corresponds to a breakpoint, which is a diagnostic type that can currently only be emitted\n\t// by the C++ testbench code.\n\tenum flavor {\n\t\tBREAK = 0,\n\t\tPRINT = 1,\n\t\tASSERT = 2,\n\t\tASSUME = 3,\n\t};\n\n\tflavor type;\n\tstd::string message;\n\tstd::string location; // same format as the `src` attribute of `$print` or `$check` cell\n\n\tdiagnostic()\n\t: type(BREAK) {}\n\n\tdiagnostic(flavor type, const std::string &message, const std::string &location)\n\t: type(type), message(message), location(location) {}\n\n\tdiagnostic(flavor type, const std::string &message, const char *file, unsigned line)\n\t: type(type), message(message), location(std::string(file) + ':' + std::to_string(line)) {}\n};\n\n// A spool stores CXXRTL design state changes in a file.\nclass spool {\npublic:\n\t// Unique pointer to a specific sample within a replay log. (Timestamps are not unique.)\n\ttypedef uint32_t pointer_t;\n\n\t// Numeric identifier assigned to a debug item within a replay log. Range limited to [1, MAXIMUM_IDENT].\n\ttypedef uint32_t ident_t;\n\n\tstatic constexpr uint16_t VERSION = 0x0400;\n\n\tstatic constexpr uint64_t HEADER_MAGIC = 0x00004c5452585843;\n\tstatic constexpr uint64_t VERSION_MASK = 0xffff000000000000;\n\n\tstatic constexpr uint32_t PACKET_DEFINE = 0xc0000000;\n\n\tstatic constexpr uint32_t PACKET_SAMPLE = 0xc0000001;\n\tenum sample_flag : uint32_t {\n\t\tEMPTY = 0,\n\t\tINCREMENTAL = 1,\n\t};\n\n\tstatic constexpr uint32_t MAXIMUM_IDENT = 0x0fffffff;\n\tstatic constexpr uint32_t CHANGE_MASK = 0x30000000;\n\n\tstatic constexpr uint32_t PACKET_CHANGE = 0x00000000/* | ident */;\n\tstatic constexpr uint32_t PACKET_CHANGEI = 0x10000000/* | ident */;\n\tstatic constexpr uint32_t PACKET_CHANGEL = 0x20000000/* | ident */;\n\tstatic constexpr uint32_t PACKET_CHANGEH = 0x30000000/* | ident */;\n\n\tstatic constexpr uint32_t PACKET_DIAGNOSTIC = 0xc0000010/* | diagnostic::flavor */;\n\tstatic constexpr uint32_t DIAGNOSTIC_MASK = 0x0000000f;\n\n\tstatic constexpr uint32_t PACKET_END = 0xffffffff;\n\n\t// Writing spools.\n\n\tclass writer {\n\t\tint fd;\n\t\tsize_t position;\n\t\tstd::vector<uint32_t> buffer;\n\n\t\t// These functions aren't overloaded because of implicit numeric conversions.\n\n\t\tvoid emit_word(uint32_t word) {\n\t\t\tif (position + 1 == buffer.size())\n\t\t\t\tflush();\n\t\t\tbuffer[position++] = word;\n\t\t}\n\n\t\tvoid emit_dword(uint64_t dword) {\n\t\t\temit_word(dword >> 0);\n\t\t\temit_word(dword >> 32);\n\t\t}\n\n\t\tvoid emit_ident(ident_t ident) {\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\t\t\temit_word(ident);\n\t\t}\n\n\t\tvoid emit_size(size_t size) {\n\t\t\tassert(size <= std::numeric_limits<uint32_t>::max());\n\t\t\temit_word(size);\n\t\t}\n\n\t\t// Same implementation as `emit_size()`, different declared intent.\n\t\tvoid emit_index(size_t index) {\n\t\t\tassert(index <= std::numeric_limits<uint32_t>::max());\n\t\t\temit_word(index);\n\t\t}\n\n\t\tvoid emit_string(std::string str) {\n\t\t\t// Align to a word boundary, and add at least one terminating \\0.\n\t\t\tstr.resize(str.size() + (sizeof(uint32_t) - (str.size() + sizeof(uint32_t)) % sizeof(uint32_t)));\n\t\t\tfor (size_t index = 0; index < str.size(); index += sizeof(uint32_t)) {\n\t\t\t\tuint32_t word;\n\t\t\t\tmemcpy(&word, &str[index], sizeof(uint32_t));\n\t\t\t\temit_word(word);\n\t\t\t}\n\t\t}\n\n\t\tvoid emit_time(const time &timestamp) {\n\t\t\tconst value<time::bits> &raw_timestamp(timestamp);\n\t\t\temit_word(raw_timestamp.data[0]);\n\t\t\temit_word(raw_timestamp.data[1]);\n\t\t\temit_word(raw_timestamp.data[2]);\n\t\t}\n\n\tpublic:\n\t\t// Creates a writer, and transfers ownership of `fd`, which must be open for appending.\n\t\t//\n\t\t// The buffer size is currently fixed to a \"reasonably large\" size, determined empirically by measuring writer\n\t\t// performance on a representative design; large but not so large it would e.g. cause address space exhaustion\n\t\t// on 32-bit platforms.\n\t\twriter(spool &spool) : fd(spool.take_write()), position(0), buffer(32 * 1024 * 1024) {\n\t\t\tassert(fd != -1);\n#if !defined(WIN32)\n\t\t\tint result = ftruncate(fd, 0);\n#else\n\t\t\tint result = _chsize_s(fd, 0);\n#endif\n\t\t\tassert(result == 0);\n\t\t}\n\n\t\twriter(writer &&moved) : fd(moved.fd), position(moved.position), buffer(moved.buffer) {\n\t\t\tmoved.fd = -1;\n\t\t\tmoved.position = 0;\n\t\t}\n\n\t\twriter(const writer &) = delete;\n\t\twriter &operator=(const writer &) = delete;\n\n\t\t// Both write() calls and fwrite() calls are too expensive to perform implicitly. The API consumer must determine\n\t\t// the optimal time to flush the writer and do that explicitly for best performance.\n\t\tvoid flush() {\n\t\t\tassert(fd != -1);\n\t\t\tsize_t data_size = position * sizeof(uint32_t);\n\t\t\tsize_t data_written = write(fd, buffer.data(), data_size);\n\t\t\tassert(data_size == data_written);\n\t\t\tposition = 0;\n\t\t}\n\n\t\t~writer() {\n\t\t\tif (fd != -1) {\n\t\t\t\tflush();\n\t\t\t\tclose(fd);\n\t\t\t}\n\t\t}\n\n\t\tvoid write_magic() {\n\t\t\t// `CXXRTL` followed by version in binary. This header will read backwards on big-endian machines, which allows\n\t\t\t// detection of this case, both visually and programmatically.\n\t\t\temit_dword(((uint64_t)VERSION << 48) | HEADER_MAGIC);\n\t\t}\n\n\t\tvoid write_define(ident_t ident, const std::string &name, size_t part_index, size_t chunks, size_t depth) {\n\t\t\temit_word(PACKET_DEFINE);\n\t\t\temit_ident(ident);\n\t\t\temit_string(name);\n\t\t\temit_index(part_index);\n\t\t\temit_size(chunks);\n\t\t\temit_size(depth);\n\t\t}\n\n\t\tvoid write_sample(bool incremental, pointer_t pointer, const time &timestamp) {\n\t\t\tuint32_t flags = (incremental ? sample_flag::INCREMENTAL : 0);\n\t\t\temit_word(PACKET_SAMPLE);\n\t\t\temit_word(flags);\n\t\t\temit_word(pointer);\n\t\t\temit_time(timestamp);\n\t\t}\n\n\t\tvoid write_change(ident_t ident, size_t chunks, const chunk_t *data) {\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\n\t\t\tif (chunks == 1 && *data == 0) {\n\t\t\t\temit_word(PACKET_CHANGEL | ident);\n\t\t\t} else if (chunks == 1 && *data == 1) {\n\t\t\t\temit_word(PACKET_CHANGEH | ident);\n\t\t\t} else {\n\t\t\t\temit_word(PACKET_CHANGE | ident);\n\t\t\t\tfor (size_t offset = 0; offset < chunks; offset++)\n\t\t\t\t\temit_word(data[offset]);\n\t\t\t}\n\t\t}\n\n\t\tvoid write_change(ident_t ident, size_t chunks, const chunk_t *data, size_t index) {\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\n\t\t\temit_word(PACKET_CHANGEI | ident);\n\t\t\temit_index(index);\n\t\t\tfor (size_t offset = 0; offset < chunks; offset++)\n\t\t\t\temit_word(data[offset]);\n\t\t}\n\n\t\tvoid write_diagnostic(const diagnostic &diagnostic) {\n\t\t\temit_word(PACKET_DIAGNOSTIC | diagnostic.type);\n\t\t\temit_string(diagnostic.message);\n\t\t\temit_string(diagnostic.location);\n\t\t}\n\n\t\tvoid write_end() {\n\t\t\temit_word(PACKET_END);\n\t\t}\n\t};\n\n\t// Reading spools.\n\n\tclass reader {\n\t\tFILE *f;\n\n\t\tuint32_t absorb_word() {\n\t\t\t// If we're at end of file, `fread` will not write to `word`, and `PACKET_END` will be returned.\n\t\t\tuint32_t word = PACKET_END;\n\t\t\tfread(&word, sizeof(word), 1, f);\n\t\t\treturn word;\n\t\t}\n\n\t\tuint64_t absorb_dword() {\n\t\t\tuint32_t lo = absorb_word();\n\t\t\tuint32_t hi = absorb_word();\n\t\t\treturn ((uint64_t)hi << 32) | lo;\n\t\t}\n\n\t\tident_t absorb_ident() {\n\t\t\tident_t ident = absorb_word();\n\t\t\tassert(ident <= MAXIMUM_IDENT);\n\t\t\treturn ident;\n\t\t}\n\n\t\tsize_t absorb_size() {\n\t\t\treturn absorb_word();\n\t\t}\n\n\t\tsize_t absorb_index() {\n\t\t\treturn absorb_word();\n\t\t}\n\n\t\tstd::string absorb_string() {\n\t\t\tstd::string str;\n\t\t\tdo {\n\t\t\t\tsize_t end = str.size();\n\t\t\t\tstr.resize(end + 4);\n\t\t\t\tuint32_t word = absorb_word();\n\t\t\t\tmemcpy(&str[end], &word, sizeof(uint32_t));\n\t\t\t} while (str.back() != '\\0');\n\t\t\t// Strings have no embedded zeroes besides the terminating one(s).\n\t\t\treturn str.substr(0, str.find('\\0'));\n\t\t}\n\n\t\ttime absorb_time() {\n\t\t\tvalue<time::bits> raw_timestamp;\n\t\t\traw_timestamp.data[0] = absorb_word();\n\t\t\traw_timestamp.data[1] = absorb_word();\n\t\t\traw_timestamp.data[2] = absorb_word();\n\t\t\treturn time(raw_timestamp);\n\t\t}\n\n\tpublic:\n\t\ttypedef uint64_t pos_t;\n\n\t\t// Creates a reader, and transfers ownership of `fd`, which must be open for reading.\n\t\treader(spool &spool) : f(fdopen(spool.take_read(), \"r\")) {\n\t\t\tassert(f != nullptr);\n\t\t}\n\n\t\treader(reader &&moved) : f(moved.f) {\n\t\t\tmoved.f = nullptr;\n\t\t}\n\n\t\treader(const reader &) = delete;\n\t\treader &operator=(const reader &) = delete;\n\n\t\t~reader() {\n\t\t\tif (f != nullptr)\n\t\t\t\tfclose(f);\n\t\t}\n\n\t\tpos_t position() {\n\t\t\treturn ftell(f);\n\t\t}\n\n\t\tvoid rewind(pos_t position) {\n\t\t\tfseek(f, position, SEEK_SET);\n\t\t}\n\n\t\tvoid read_magic() {\n\t\t\tuint64_t magic = absorb_dword();\n\t\t\tassert((magic & ~VERSION_MASK) == HEADER_MAGIC);\n\t\t\tassert((magic >> 48) == VERSION);\n\t\t}\n\n\t\tbool read_define(ident_t &ident, std::string &name, size_t &part_index, size_t &chunks, size_t &depth) {\n\t\t\tuint32_t header = absorb_word();\n\t\t\tif (header == PACKET_END)\n\t\t\t\treturn false;\n\t\t\tassert(header == PACKET_DEFINE);\n\t\t\tident = absorb_ident();\n\t\t\tname = absorb_string();\n\t\t\tpart_index = absorb_index();\n\t\t\tchunks = absorb_size();\n\t\t\tdepth = absorb_size();\n\t\t\treturn true;\n\t\t}\n\n\t\tbool read_sample(bool &incremental, pointer_t &pointer, time &timestamp) {\n\t\t\tuint32_t header = absorb_word();\n\t\t\tif (header == PACKET_END)\n\t\t\t\treturn false;\n\t\t\tassert(header == PACKET_SAMPLE);\n\t\t\tuint32_t flags = absorb_word();\n\t\t\tincremental = (flags & sample_flag::INCREMENTAL);\n\t\t\tpointer = absorb_word();\n\t\t\ttimestamp = absorb_time();\n\t\t\treturn true;\n\t\t}\n\n\t\tbool read_header(uint32_t &header) {\n\t\t\theader = absorb_word();\n\t\t\treturn header != PACKET_END;\n\t\t}\n\n\t\t// This method must be separate from `read_change_data` because `chunks` and `depth` can only be looked up\n\t\t// if `ident` is known.\n\t\tbool read_change_ident(uint32_t header, ident_t &ident) {\n\t\t\tif ((header & ~(CHANGE_MASK | MAXIMUM_IDENT)) != 0)\n\t\t\t\treturn false; // some other packet\n\t\t\tident = header & MAXIMUM_IDENT;\n\t\t\treturn true;\n\t\t}\n\n\t\tvoid read_change_data(uint32_t header, size_t chunks, size_t depth, chunk_t *data) {\n\t\t\tuint32_t index = 0;\n\t\t\tswitch (header & CHANGE_MASK) {\n\t\t\t\tcase PACKET_CHANGEL:\n\t\t\t\t\t*data = 0;\n\t\t\t\t\treturn;\n\t\t\t\tcase PACKET_CHANGEH:\n\t\t\t\t\t*data = 1;\n\t\t\t\t\treturn;\n\t\t\t\tcase PACKET_CHANGE:\n\t\t\t\t\tbreak;\n\t\t\t\tcase PACKET_CHANGEI:\n\t\t\t\t\tindex = absorb_word();\n\t\t\t\t\tassert(index < depth);\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tassert(false && \"Unrecognized change packet\");\n\t\t\t}\n\t\t\tfor (size_t offset = 0; offset < chunks; offset++)\n\t\t\t\tdata[chunks * index + offset] = absorb_word();\n\t\t}\n\n\t\tbool read_diagnostic(uint32_t header, diagnostic &diagnostic) {\n\t\t\tif ((header & ~DIAGNOSTIC_MASK) != PACKET_DIAGNOSTIC)\n\t\t\t\treturn false; // some other packet\n\t\t\tuint32_t type = header & DIAGNOSTIC_MASK;\n\t\t\tassert(type == diagnostic::BREAK || type == diagnostic::PRINT ||\n\t\t\t type == diagnostic::ASSERT || type == diagnostic::ASSUME);\n\t\t\tdiagnostic.type = (diagnostic::flavor)type;\n\t\t\tdiagnostic.message = absorb_string();\n\t\t\tdiagnostic.location = absorb_string();\n\t\t\treturn true;\n\t\t}\n\t};\n\n\t// Opening spools. For certain uses of the record/replay mechanism, two distinct open files (two open files, i.e.\n\t// two distinct file pointers, and not just file descriptors, which share the file pointer if duplicated) are used,\n\t// for a reader and writer thread. This class manages the lifetime of the descriptors for these files. When only\n\t// one of them is used, the other is closed harmlessly when the spool is destroyed.\nprivate:\n\tstd::atomic<int> writefd;\n\tstd::atomic<int> readfd;\n\npublic:\n\tspool(const std::string &filename)\n\t\t: writefd(open(filename.c_str(), O_CREAT|O_BINARY|O_WRONLY|O_APPEND, 0644)),\n\t\t readfd(open(filename.c_str(), O_BINARY|O_RDONLY)) {\n\t\tassert(writefd.load() != -1 && readfd.load() != -1);\n\t}\n\n\tspool(spool &&moved) : writefd(moved.writefd.exchange(-1)), readfd(moved.readfd.exchange(-1)) {}\n\n\tspool(const spool &) = delete;\n\tspool &operator=(const spool &) = delete;\n\n\t~spool() {\n\t\tint fd;\n\t\tif ((fd = writefd.exchange(-1)) != -1)\n\t\t\tclose(fd);\n\t\tif ((fd = readfd.exchange(-1)) != -1)\n\t\t\tclose(fd);\n\t}\n\n\t// Atomically acquire a write file descriptor for the spool. Can be called once, and will return -1 the next time\n\t// it is called. Thread-safe.\n\tint take_write() {\n\t\treturn writefd.exchange(-1);\n\t}\n\n\t// Atomically acquire a read file descriptor for the spool. Can be called once, and will return -1 the next time\n\t// it is called. Thread-safe.\n\tint take_read() {\n\t\treturn readfd.exchange(-1);\n\t}\n};\n\n// A CXXRTL recorder samples design state, producing complete or incremental updates, and writes them to a spool.\nclass recorder {\n\tstruct variable {\n\t\tspool::ident_t ident; /* <= spool::MAXIMUM_IDENT */\n\t\tsize_t chunks;\n\t\tsize_t depth; /* == 1 for wires */\n\t\tchunk_t *curr;\n\t\tbool memory;\n\t};\n\n\tspool::writer writer;\n\tstd::vector<variable> variables;\n\tstd::vector<size_t> inputs; // values of inputs must be recorded explicitly, as their changes are not observed\n\tstd::unordered_map<const chunk_t*, spool::ident_t> ident_lookup;\n\tbool streaming = false; // whether variable definitions have been written\n\tspool::pointer_t pointer = 0;\n\ttime timestamp;\n\npublic:\n\ttemplate<typename ...Args>\n\trecorder(Args &&...args) : writer(std::forward<Args>(args)...) {}\n\n\tvoid start(module &module, std::string top_path = \"\") {\n\t\tdebug_items items;\n\t\tmodule.debug_info(&items, /*scopes=*/nullptr, top_path);\n\t\tstart(items);\n\t}\n\n\tvoid start(const debug_items &items) {\n\t\tassert(!streaming);\n\n\t\twriter.write_magic();\n\t\tfor (auto item : items.table)\n\t\t\tfor (size_t part_index = 0; part_index < item.second.size(); part_index++) {\n\t\t\t\tauto &part = item.second[part_index];\n\t\t\t\tif ((part.flags & debug_item::INPUT) || (part.flags & debug_item::DRIVEN_SYNC) ||\n\t\t\t\t\t\t(part.type == debug_item::MEMORY)) {\n\t\t\t\t\tvariable var;\n\t\t\t\t\tvar.ident = variables.size() + 1;\n\t\t\t\t\tvar.chunks = (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8);\n\t\t\t\t\tvar.depth = part.depth;\n\t\t\t\t\tvar.curr = part.curr;\n\t\t\t\t\tvar.memory = (part.type == debug_item::MEMORY);\n\t\t\t\t\tident_lookup[var.curr] = var.ident;\n\n\t\t\t\t\tassert(variables.size() < spool::MAXIMUM_IDENT);\n\t\t\t\t\tif (part.flags & debug_item::INPUT)\n\t\t\t\t\t\tinputs.push_back(variables.size());\n\t\t\t\t\tvariables.push_back(var);\n\n\t\t\t\t\twriter.write_define(var.ident, item.first, part_index, var.chunks, var.depth);\n\t\t\t\t}\n\t\t\t}\n\t\twriter.write_end();\n\t\tstreaming = true;\n\t}\n\n\tconst time &latest_time() {\n\t\treturn timestamp;\n\t}\n\n\tconst time &advance_time(const time &delta) {\n\t\tassert(!delta.is_negative());\n\t\ttimestamp += delta;\n\t\treturn timestamp;\n\t}\n\n\tvoid record_complete() {\n\t\tassert(streaming);\n\n\t\twriter.write_sample(/*incremental=*/false, pointer++, timestamp);\n\t\tfor (auto var : variables) {\n\t\t\tassert(var.ident != 0);\n\t\t\tif (!var.memory)\n\t\t\t\twriter.write_change(var.ident, var.chunks, var.curr);\n\t\t\telse\n\t\t\t\tfor (size_t index = 0; index < var.depth; index++)\n\t\t\t\t\twriter.write_change(var.ident, var.chunks, &var.curr[var.chunks * index], index);\n\t\t}\n\t\twriter.write_end();\n\t}\n\n\t// This function is generic over ModuleT to encourage observer callbacks to be inlined into the commit function.\n\ttemplate<class ModuleT>\n\tbool record_incremental(ModuleT &module) {\n\t\tassert(streaming);\n\n\t\tstruct : observer {\n\t\t\tstd::unordered_map<const chunk_t*, spool::ident_t> *ident_lookup;\n\t\t\tspool::writer *writer;\n\n\t\t\tCXXRTL_ALWAYS_INLINE\n\t\t\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {\n\t\t\t\twriter->write_change(ident_lookup->at(base), chunks, value);\n\t\t\t}\n\n\t\t\tCXXRTL_ALWAYS_INLINE\n\t\t\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {\n\t\t\t\twriter->write_change(ident_lookup->at(base), chunks, value, index);\n\t\t\t}\n\t\t} record_observer;\n\t\trecord_observer.ident_lookup = &ident_lookup;\n\t\trecord_observer.writer = &writer;\n\n\t\twriter.write_sample(/*incremental=*/true, pointer++, timestamp);\n\t\tfor (auto input_index : inputs) {\n\t\t\tvariable &var = variables.at(input_index);\n\t\t\tassert(!var.memory);\n\t\t\twriter.write_change(var.ident, var.chunks, var.curr);\n\t\t}\n\t\tbool changed = module.commit(record_observer);\n\t\twriter.write_end();\n\t\treturn changed;\n\t}\n\n\tvoid record_diagnostic(const diagnostic &diagnostic) {\n\t\tassert(streaming);\n\n\t\t// Emit an incremental delta cycle per diagnostic to simplify the logic of the recorder. This is inefficient, but\n\t\t// diagnostics should be rare enough that this inefficiency does not matter. If it turns out to be an issue, this\n\t\t// code should be changed to accumulate diagnostics to a buffer that is flushed in `record_{complete,incremental}`\n\t\t// and also in `advance_time` before the timestamp is changed. (Right now `advance_time` never writes to the spool.)\n\t\twriter.write_sample(/*incremental=*/true, pointer++, timestamp);\n\t\twriter.write_diagnostic(diagnostic);\n\t\twriter.write_end();\n\t}\n\n\tvoid flush() {\n\t\twriter.flush();\n\t}\n};\n\n// A CXXRTL player reads samples from a spool, and changes the design state accordingly. To start reading samples,\n// a spool must have been initialized: the recorder must have been started and an initial complete sample must have\n// been written.\nclass player {\n\tstruct variable {\n\t\tsize_t chunks;\n\t\tsize_t depth; /* == 1 for wires */\n\t\tchunk_t *curr;\n\t};\n\n\tspool::reader reader;\n\tstd::unordered_map<spool::ident_t, variable> variables;\n\tbool streaming = false; // whether variable definitions have been read\n\tbool initialized = false; // whether a sample has ever been read\n\tspool::pointer_t pointer = 0;\n\ttime timestamp;\n\n\tstd::map<spool::pointer_t, spool::reader::pos_t, std::greater<spool::pointer_t>> index_by_pointer;\n\tstd::map<time, spool::reader::pos_t, std::greater<time>> index_by_timestamp;\n\n\tbool peek_sample(spool::pointer_t &pointer, time &timestamp) {\n\t\tbool incremental;\n\t\tauto position = reader.position();\n\t\tbool success = reader.read_sample(incremental, pointer, timestamp);\n\t\treader.rewind(position);\n\t\treturn success;\n\t}\n\npublic:\n\ttemplate<typename ...Args>\n\tplayer(Args &&...args) : reader(std::forward<Args>(args)...) {}\n\n\t// The `top_path` must match the one given to the recorder.\n\tvoid start(module &module, std::string top_path = \"\") {\n\t\tdebug_items items;\n\t\tmodule.debug_info(&items, /*scopes=*/nullptr, top_path);\n\t\tstart(items);\n\t}\n\n\tvoid start(const debug_items &items) {\n\t\tassert(!streaming);\n\n\t\treader.read_magic();\n\t\twhile (true) {\n\t\t\tspool::ident_t ident;\n\t\t\tstd::string name;\n\t\t\tsize_t part_index;\n\t\t\tsize_t chunks;\n\t\t\tsize_t depth;\n\t\t\tif (!reader.read_define(ident, name, part_index, chunks, depth))\n\t\t\t\tbreak;\n\t\t\tassert(variables.count(ident) == 0);\n\t\t\tassert(items.count(name) != 0);\n\t\t\tassert(part_index < items.count(name));\n\n\t\t\tconst debug_item &part = items.at(name).at(part_index);\n\t\t\tassert(chunks == (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8));\n\t\t\tassert(depth == part.depth);\n\n\t\t\tvariable &var = variables[ident];\n\t\t\tvar.chunks = chunks;\n\t\t\tvar.depth = depth;\n\t\t\tvar.curr = part.curr;\n\t\t}\n\t\tassert(variables.size() > 0);\n\t\tstreaming = true;\n\n\t\t// Establish the initial state of the design.\n\t\tstd::vector<diagnostic> diagnostics;\n\t\tinitialized = replay(&diagnostics);\n\t\tassert(initialized && diagnostics.empty());\n\t}\n\n\t// Returns the pointer of the current sample.\n\tspool::pointer_t current_pointer() {\n\t\tassert(initialized);\n\t\treturn pointer;\n\t}\n\n\t// Returns the time of the current sample.\n\tconst time &current_time() {\n\t\tassert(initialized);\n\t\treturn timestamp;\n\t}\n\n\t// Returns `true` if there is a next sample to read, and sets `pointer` to its pointer if there is.\n\tbool get_next_pointer(spool::pointer_t &pointer) {\n\t\tassert(streaming);\n\t\ttime timestamp;\n\t\treturn peek_sample(pointer, timestamp);\n\t}\n\n\t// Returns `true` if there is a next sample to read, and sets `timestamp` to its time if there is.\n\tbool get_next_time(time &timestamp) {\n\t\tassert(streaming);\n\t\tuint32_t pointer;\n\t\treturn peek_sample(pointer, timestamp);\n\t}\n\n\t// If this function returns `true`, then `current_pointer() == at_pointer`, and the module contains values that\n\t// correspond to this pointer in the replay log. To obtain a valid pointer, call `current_pointer()`; while pointers\n\t// are monotonically increasing for each consecutive sample, using arithmetic operations to create a new pointer is\n\t// not allowed. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in this sample.\n\tbool rewind_to(spool::pointer_t at_pointer, std::vector<diagnostic> *diagnostics) {\n\t\tassert(initialized);\n\n\t\t// The pointers in the replay log start from one that is greater than `at_pointer`. In this case the pointer will\n\t\t// never be reached.\n\t\tassert(index_by_pointer.size() > 0);\n\t\tif (at_pointer < index_by_pointer.rbegin()->first)\n\t\t\treturn false;\n\n\t\t// Find the last complete sample whose pointer is less than or equal to `at_pointer`. Note that the comparison\n\t\t// function used here is `std::greater`, inverting the direction of `lower_bound`.\n\t\tauto position_it = index_by_pointer.lower_bound(at_pointer);\n\t\tassert(position_it != index_by_pointer.end());\n\t\treader.rewind(position_it->second);\n\n\t\t// Replay samples until eventually arriving to `at_pointer` or encountering end of file.\n\t\twhile(replay(diagnostics)) {\n\t\t\tif (pointer == at_pointer)\n\t\t\t\treturn true;\n\n\t\t\tif (diagnostics)\n\t\t\t\tdiagnostics->clear();\n\t\t}\n\t\treturn false;\n\t}\n\n\t// If this function returns `true`, then `current_time() <= at_or_before_timestamp`, and the module contains values\n\t// that correspond to `current_time()` in the replay log. If `current_time() == at_or_before_timestamp` and there\n\t// are several consecutive samples with the same time, the module contains values that correspond to the first of\n\t// these samples. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in this sample.\n\tbool rewind_to_or_before(const time &at_or_before_timestamp, std::vector<diagnostic> *diagnostics) {\n\t\tassert(initialized);\n\n\t\t// The timestamps in the replay log start from one that is greater than `at_or_before_timestamp`. In this case\n\t\t// the timestamp will never be reached. Otherwise, this function will always succeed.\n\t\tassert(index_by_timestamp.size() > 0);\n\t\tif (at_or_before_timestamp < index_by_timestamp.rbegin()->first)\n\t\t\treturn false;\n\n\t\t// Find the last complete sample whose timestamp is less than or equal to `at_or_before_timestamp`. Note that\n\t\t// the comparison function used here is `std::greater`, inverting the direction of `lower_bound`.\n\t\tauto position_it = index_by_timestamp.lower_bound(at_or_before_timestamp);\n\t\tassert(position_it != index_by_timestamp.end());\n\t\treader.rewind(position_it->second);\n\n\t\t// Replay samples until eventually arriving to or past `at_or_before_timestamp` or encountering end of file.\n\t\twhile (replay(diagnostics)) {\n\t\t\tif (timestamp == at_or_before_timestamp)\n\t\t\t\tbreak;\n\n\t\t\ttime next_timestamp;\n\t\t\tif (!get_next_time(next_timestamp))\n\t\t\t\tbreak;\n\t\t\tif (next_timestamp > at_or_before_timestamp)\n\t\t\t\tbreak;\n\n\t\t\tif (diagnostics)\n\t\t\t\tdiagnostics->clear();\n\t\t}\n\t\treturn true;\n\t}\n\n\t// If this function returns `true`, then `current_pointer()` and `current_time()` are updated for the next sample\n\t// and the module now contains values that correspond to that sample. If it returns `false`, there was no next sample\n\t// to read. The `diagnostics` argument, if not `nullptr`, receives the diagnostics recorded in the next sample.\n\tbool replay(std::vector<diagnostic> *diagnostics) {\n\t\tassert(streaming);\n\n\t\tbool incremental;\n\t\tauto position = reader.position();\n\t\tif (!reader.read_sample(incremental, pointer, timestamp))\n\t\t\treturn false;\n\n\t\t// The very first sample that is read must be a complete sample. This is required for the rewind functions to work.\n\t\tassert(initialized || !incremental);\n\n\t\t// It is possible (though not very useful) to have several complete samples with the same timestamp in a row.\n\t\t// Ensure that we associate the timestamp with the position of the first such complete sample. (This condition\n\t\t// works because the player never jumps over a sample.)\n\t\tif (!incremental && !index_by_pointer.count(pointer)) {\n\t\t\tassert(!index_by_timestamp.count(timestamp));\n\t\t\tindex_by_pointer[pointer] = position;\n\t\t\tindex_by_timestamp[timestamp] = position;\n\t\t}\n\n\t\tuint32_t header;\n\t\twhile (reader.read_header(header)) {\n\t\t\tspool::ident_t ident;\n\t\t\tdiagnostic diag;\n\t\t\tif (reader.read_change_ident(header, ident)) {\n\t\t\t\tvariable &var = variables.at(ident);\n\t\t\t\treader.read_change_data(header, var.chunks, var.depth, var.curr);\n\t\t\t} else if (reader.read_diagnostic(header, diag)) {\n\t\t\t\tif (diagnostics)\n\t\t\t\t\tdiagnostics->push_back(diag);\n\t\t\t} else assert(false && \"Unrecognized packet header\");\n\t\t}\n\t\treturn true;\n\t}\n};\n\n}\n\n#endif\n",
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  "cxxrtl_time.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2023 Catherine <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_TIME_H\n#define CXXRTL_TIME_H\n\n#include <cinttypes>\n#include <string>\n\n#include <cxxrtl/cxxrtl.h>\n\nnamespace cxxrtl {\n\n// A timestamp or a difference in time, stored as a 96-bit number of femtoseconds (10e-15 s). The range and resolution\n// of this format can represent any VCD timestamp within approx. ±1255321.2 years, without the need for a timescale.\nclass time {\npublic:\n\tstatic constexpr size_t bits = 96; // 3 chunks\n\nprivate:\n\tstatic constexpr size_t resolution_digits = 15;\n\n\tstatic_assert(sizeof(chunk_t) == 4, \"a chunk is expected to be 32-bit\");\n\tstatic constexpr value<bits> resolution = value<bits> {\n\t\tchunk_t(1000000000000000ull & 0xffffffffull), chunk_t(1000000000000000ull >> 32), 0u\n\t};\n\n\t// Signed number of femtoseconds from the beginning of time.\n\tvalue<bits> raw;\n\npublic:\n\tconstexpr time() {}\n\n\texplicit constexpr time(const value<bits> &raw) : raw(raw) {}\n\texplicit operator const value<bits> &() const { return raw; }\n\n\tstatic constexpr time maximum() {\n\t\treturn time(value<bits> { 0xffffffffu, 0xffffffffu, 0x7fffffffu });\n\t}\n\n\ttime(int64_t secs, int64_t femtos) {\n\t\tvalue<64> secs_val;\n\t\tsecs_val.set(secs);\n\t\tvalue<64> femtos_val;\n\t\tfemtos_val.set(femtos);\n\t\traw = secs_val.sext<bits>().mul<bits>(resolution).add(femtos_val.sext<bits>());\n\t}\n\n\tbool is_zero() const {\n\t\treturn raw.is_zero();\n\t}\n\n\t// Extracts the sign of the value.\n\tbool is_negative() const {\n\t\treturn raw.is_neg();\n\t}\n\n\t// Extracts the number of whole seconds. Negative if the value is negative.\n\tint64_t secs() const {\n\t\treturn raw.sdivmod(resolution).first.trunc<64>().get<int64_t>();\n\t}\n\n\t// Extracts the number of femtoseconds in the fractional second. Negative if the value is negative.\n\tint64_t femtos() const {\n\t\treturn raw.sdivmod(resolution).second.trunc<64>().get<int64_t>();\n\t}\n\n\tbool operator==(const time &other) const {\n\t\treturn raw == other.raw;\n\t}\n\n\tbool operator!=(const time &other) const {\n\t\treturn raw != other.raw;\n\t}\n\n\tbool operator>(const time &other) const {\n\t\treturn other.raw.scmp(raw);\n\t}\n\n\tbool operator>=(const time &other) const {\n\t\treturn !raw.scmp(other.raw);\n\t}\n\n\tbool operator<(const time &other) const {\n\t\treturn raw.scmp(other.raw);\n\t}\n\n\tbool operator<=(const time &other) const {\n\t\treturn !other.raw.scmp(raw);\n\t}\n\n\ttime operator+(const time &other) const {\n\t\treturn time(raw.add(other.raw));\n\t}\n\n\ttime &operator+=(const time &other) {\n\t\t*this = *this + other;\n\t\treturn *this;\n\t}\n\n\ttime operator-() const {\n\t\treturn time(raw.neg());\n\t}\n\n\ttime operator-(const time &other) const {\n\t\treturn *this + (-other);\n\t}\n\n\ttime &operator-=(const time &other) {\n\t\t*this = *this - other;\n\t\treturn *this;\n\t}\n\n\toperator std::string() const {\n\t\tchar buf[48]; // x=2**95; len(f\"-{x/1_000_000_000_000_000}.{x^1_000_000_000_000_000}\") == 48\n\t\tint64_t secs = this->secs();\n\t\tint64_t femtos = this->femtos();\n\t\tsnprintf(buf, sizeof(buf), \"%s%\" PRIi64 \".%015\" PRIi64,\n\t\t\tis_negative() ? \"-\" : \"\", secs >= 0 ? secs : -secs, femtos >= 0 ? femtos : -femtos);\n\t\treturn buf;\n\t}\n\n#if __cplusplus >= 201603L\n\t[[nodiscard(\"ignoring parse errors\")]]\n#endif\n\tbool parse(const std::string &str) {\n\t\tenum {\n\t\t\tparse_sign_opt,\n\t\t\tparse_integral,\n\t\t\tparse_fractional,\n\t\t} state = parse_sign_opt;\n\t\tbool negative = false;\n\t\tint64_t integral = 0;\n\t\tint64_t fractional = 0;\n\t\tsize_t frac_digits = 0;\n\t\tfor (auto chr : str) {\n\t\t\tswitch (state) {\n\t\t\t\tcase parse_sign_opt:\n\t\t\t\t\tstate = parse_integral;\n\t\t\t\t\tif (chr == '+' || chr == '-') {\n\t\t\t\t\t\tnegative = (chr == '-');\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\t/* fallthrough */\n\t\t\t\tcase parse_integral:\n\t\t\t\t\tif (chr >= '0' && chr <= '9') {\n\t\t\t\t\t\tintegral *= 10;\n\t\t\t\t\t\tintegral += chr - '0';\n\t\t\t\t\t} else if (chr == '.') {\n\t\t\t\t\t\tstate = parse_fractional;\n\t\t\t\t\t} else {\n\t\t\t\t\t\treturn false;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase parse_fractional:\n\t\t\t\t\tif (chr >= '0' && chr <= '9' && frac_digits < resolution_digits) {\n\t\t\t\t\t\tfractional *= 10;\n\t\t\t\t\t\tfractional += chr - '0';\n\t\t\t\t\t\tfrac_digits++;\n\t\t\t\t\t} else {\n\t\t\t\t\t\treturn false;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (frac_digits == 0)\n\t\t\treturn false;\n\t\twhile (frac_digits++ < resolution_digits)\n\t\t\tfractional *= 10;\n\t\t*this = negative ? -time { integral, fractional} : time { integral, fractional };\n\t\treturn true;\n\t}\n};\n\n// Out-of-line definition required until C++17.\nconstexpr value<time::bits> time::resolution;\n\nstd::ostream &operator<<(std::ostream &os, const time &val) {\n\tos << (std::string)val;\n\treturn os;\n}\n\n// These literals are (confusingly) compatible with the ones from `std::chrono`: the `std::chrono` literals do not\n// have an underscore (e.g. 1ms) and the `cxxrtl::time` literals do (e.g. 1_ms). This syntactic difference is\n// a requirement of the C++ standard. Despite being compatible the literals should not be mixed in the same namespace.\nnamespace time_literals {\n\ntime operator\"\"_s(unsigned long long seconds) {\n\treturn time { (int64_t)seconds, 0 };\n}\n\ntime operator\"\"_ms(unsigned long long milliseconds) {\n\treturn time { 0, (int64_t)milliseconds * 1000000000000 };\n}\n\ntime operator\"\"_us(unsigned long long microseconds) {\n\treturn time { 0, (int64_t)microseconds * 1000000000 };\n}\n\ntime operator\"\"_ns(unsigned long long nanoseconds) {\n\treturn time { 0, (int64_t)nanoseconds * 1000000 };\n}\n\ntime operator\"\"_ps(unsigned long long picoseconds) {\n\treturn time { 0, (int64_t)picoseconds * 1000 };\n}\n\ntime operator\"\"_fs(unsigned long long femtoseconds) {\n\treturn time { 0, (int64_t)femtoseconds };\n}\n\n};\n\n};\n\n#endif\n",
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- "cxxrtl_vcd.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_VCD_H\n#define CXXRTL_VCD_H\n\n#include <cxxrtl/cxxrtl.h>\n\nnamespace cxxrtl {\n\nclass vcd_writer {\n\tstruct variable {\n\t\tsize_t ident;\n\t\tsize_t width;\n\t\tchunk_t *curr;\n\t\tsize_t cache_offset;\n\t\tdebug_outline *outline;\n\t\tbool *outline_warm;\n\t};\n\n\tstd::vector<std::string> current_scope;\n\tstd::map<debug_outline*, bool> outlines;\n\tstd::vector<variable> variables;\n\tstd::vector<chunk_t> cache;\n\tstd::map<chunk_t*, size_t> aliases;\n\tbool streaming = false;\n\n\tvoid emit_timescale(unsigned number, const std::string &unit) {\n\t\tassert(!streaming);\n\t\tassert(number == 1 || number == 10 || number == 100);\n\t\tassert(unit == \"s\" || unit == \"ms\" || unit == \"us\" ||\n\t\t unit == \"ns\" || unit == \"ps\" || unit == \"fs\");\n\t\tbuffer += \"$timescale \" + std::to_string(number) + \" \" + unit + \" $end\\n\";\n\t}\n\n\tvoid emit_scope(const std::vector<std::string> &scope) {\n\t\tassert(!streaming);\n\t\twhile (current_scope.size() > scope.size() ||\n\t\t (current_scope.size() > 0 &&\n\t\t\tcurrent_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {\n\t\t\tbuffer += \"$upscope $end\\n\";\n\t\t\tcurrent_scope.pop_back();\n\t\t}\n\t\twhile (current_scope.size() < scope.size()) {\n\t\t\tbuffer += \"$scope module \" + scope[current_scope.size()] + \" $end\\n\";\n\t\t\tcurrent_scope.push_back(scope[current_scope.size()]);\n\t\t}\n\t}\n\n\tvoid emit_ident(size_t ident) {\n\t\tdo {\n\t\t\tbuffer += '!' + ident % 94; // \"base94\"\n\t\t\tident /= 94;\n\t\t} while (ident != 0);\n\t}\n\n\tvoid emit_name(const std::string &name) {\n\t\tfor (char c : name) {\n\t\t\tif (c == ':') {\n\t\t\t\t// Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file\n\t\t\t\t// to be unreadable. It cannot be escaped either, so replace it with the sideways colon.\n\t\t\t\tbuffer += \"..\";\n\t\t\t} else {\n\t\t\t\tbuffer += c;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid emit_var(const variable &var, const std::string &type, const std::string &name,\n\t size_t lsb_at, bool multipart) {\n\t\tassert(!streaming);\n\t\tbuffer += \"$var \" + type + \" \" + std::to_string(var.width) + \" \";\n\t\temit_ident(var.ident);\n\t\tbuffer += \" \";\n\t\temit_name(name);\n\t\tif (multipart || name.back() == ']' || lsb_at != 0) {\n\t\t\tif (var.width == 1)\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at) + \"]\";\n\t\t\telse\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at + var.width - 1) + \":\" + std::to_string(lsb_at) + \"]\";\n\t\t}\n\t\tbuffer += \" $end\\n\";\n\t}\n\n\tvoid emit_enddefinitions() {\n\t\tassert(!streaming);\n\t\tbuffer += \"$enddefinitions $end\\n\";\n\t\tstreaming = true;\n\t}\n\n\tvoid emit_time(uint64_t timestamp) {\n\t\tassert(streaming);\n\t\tbuffer += \"#\" + std::to_string(timestamp) + \"\\n\";\n\t}\n\n\tvoid emit_scalar(const variable &var) {\n\t\tassert(streaming);\n\t\tassert(var.width == 1);\n\t\tbuffer += (*var.curr ? '1' : '0');\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid emit_vector(const variable &var) {\n\t\tassert(streaming);\n\t\tbuffer += 'b';\n\t\tfor (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {\n\t\t\tbool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));\n\t\t\tbuffer += (bit_curr ? '1' : '0');\n\t\t}\n\t\tbuffer += ' ';\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid reset_outlines() {\n\t\tfor (auto &outline_it : outlines)\n\t\t\toutline_it.second = /*warm=*/(outline_it.first == nullptr);\n\t}\n\n\tvariable &register_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) {\n\t\tif (aliases.count(curr)) {\n\t\t\treturn variables[aliases[curr]];\n\t\t} else {\n\t\t\tauto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first;\n\t\t\tconst size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\taliases[curr] = variables.size();\n\t\t\tif (constant) {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second });\n\t\t\t} else {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second });\n\t\t\t\tcache.insert(cache.end(), &curr[0], &curr[chunks]);\n\t\t\t}\n\t\t\treturn variables.back();\n\t\t}\n\t}\n\n\tbool test_variable(const variable &var) {\n\t\tif (var.cache_offset == (size_t)-1)\n\t\t\treturn false; // constant\n\t\tif (!*var.outline_warm) {\n\t\t\tvar.outline->eval();\n\t\t\t*var.outline_warm = true;\n\t\t}\n\t\tconst size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\tif (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) {\n\t\t\treturn false;\n\t\t} else {\n\t\t\tstd::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]);\n\t\t\treturn true;\n\t\t}\n\t}\n\n\tstatic std::vector<std::string> split_hierarchy(const std::string &hier_name) {\n\t\tstd::vector<std::string> hierarchy;\n\t\tsize_t prev = 0;\n\t\twhile (true) {\n\t\t\tsize_t curr = hier_name.find_first_of(' ', prev);\n\t\t\tif (curr == std::string::npos) {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev));\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev, curr - prev));\n\t\t\t\tprev = curr + 1;\n\t\t\t}\n\t\t}\n\t\treturn hierarchy;\n\t}\n\npublic:\n\tstd::string buffer;\n\n\tvoid timescale(unsigned number, const std::string &unit) {\n\t\temit_timescale(number, unit);\n\t}\n\n\tvoid add(const std::string &hier_name, const debug_item &item, bool multipart = false) {\n\t\tstd::vector<std::string> scope = split_hierarchy(hier_name);\n\t\tstd::string name = scope.back();\n\t\tscope.pop_back();\n\n\t\temit_scope(scope);\n\t\tswitch (item.type) {\n\t\t\t// Not the best naming but oh well...\n\t\t\tcase debug_item::VALUE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::WIRE:\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"reg\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::MEMORY: {\n\t\t\t\tconst size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\t\tfor (size_t index = 0; index < item.depth; index++) {\n\t\t\t\t\tchunk_t *nth_curr = &item.curr[stride * index];\n\t\t\t\t\tstd::string nth_name = name + '[' + std::to_string(index) + ']';\n\t\t\t\t\temit_var(register_variable(item.width, nth_curr),\n\t\t\t\t\t \"reg\", nth_name, item.lsb_at, multipart);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase debug_item::ALIAS:\n\t\t\t\t// Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value\n\t\t\t\t// can actually change, and must be tracked. In most cases the VCD identifier will be\n\t\t\t\t// unified with the aliased reg, but we should handle the case where only the alias is\n\t\t\t\t// added to the VCD writer, too.\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::OUTLINE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\ttemplate<class Filter>\n\tvoid add(const debug_items &items, const Filter &filter) {\n\t\t// `debug_items` is a map, so the items are already sorted in an order optimal for emitting\n\t\t// VCD scope sections.\n\t\tfor (auto &it : items.table)\n\t\t\tfor (auto &part : it.second)\n\t\t\t\tif (filter(it.first, part))\n\t\t\t\t\tadd(it.first, part, it.second.size() > 1);\n\t}\n\n\tvoid add(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &) {\n\t\t\treturn true;\n\t\t});\n\t}\n\n\tvoid add_without_memories(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &item) {\n\t\t\treturn item.type != debug_item::MEMORY;\n\t\t});\n\t}\n\n\tvoid sample(uint64_t timestamp) {\n\t\tbool first_sample = !streaming;\n\t\tif (first_sample) {\n\t\t\temit_scope({});\n\t\t\temit_enddefinitions();\n\t\t}\n\t\treset_outlines();\n\t\temit_time(timestamp);\n\t\tfor (auto var : variables)\n\t\t\tif (test_variable(var) || first_sample) {\n\t\t\t\tif (var.width == 1)\n\t\t\t\t\temit_scalar(var);\n\t\t\t\telse\n\t\t\t\t\temit_vector(var);\n\t\t\t}\n\t}\n};\n\n}\n\n#endif\n",
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+ "cxxrtl_vcd.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_VCD_H\n#define CXXRTL_VCD_H\n\n#include <cxxrtl/cxxrtl.h>\n\nnamespace cxxrtl {\n\nclass vcd_writer {\n\tstruct variable {\n\t\tsize_t ident;\n\t\tsize_t width;\n\t\tchunk_t *curr;\n\t\tsize_t cache_offset;\n\t\tdebug_outline *outline;\n\t\tbool *outline_warm;\n\t};\n\n\tstd::vector<std::string> current_scope;\n\tstd::map<debug_outline*, bool> outlines;\n\tstd::vector<variable> variables;\n\tstd::vector<chunk_t> cache;\n\tstd::map<chunk_t*, size_t> aliases;\n\tbool streaming = false;\n\n\tvoid emit_timescale(unsigned number, const std::string &unit) {\n\t\tassert(!streaming);\n\t\tassert(number == 1 || number == 10 || number == 100);\n\t\tassert(unit == \"s\" || unit == \"ms\" || unit == \"us\" ||\n\t\t unit == \"ns\" || unit == \"ps\" || unit == \"fs\");\n\t\tbuffer += \"$timescale \" + std::to_string(number) + \" \" + unit + \" $end\\n\";\n\t}\n\n\tvoid emit_scope(const std::vector<std::string> &scope) {\n\t\tassert(!streaming);\n\t\tsize_t same_scope_count = 0;\n\t\twhile ((same_scope_count < current_scope.size()) &&\n\t\t\t (same_scope_count < scope.size()) &&\n\t\t\t (current_scope[same_scope_count] == scope[same_scope_count])) {\n\t\t\tsame_scope_count++;\n\t\t}\n\t\twhile (current_scope.size() > same_scope_count) {\n\t\t\tbuffer += \"$upscope $end\\n\";\n\t\t\tcurrent_scope.pop_back();\n\t\t}\n\t\twhile (current_scope.size() < scope.size()) {\n\t\t\tbuffer += \"$scope module \" + scope[current_scope.size()] + \" $end\\n\";\n\t\t\tcurrent_scope.push_back(scope[current_scope.size()]);\n\t\t}\n\t}\n\n\tvoid emit_ident(size_t ident) {\n\t\tdo {\n\t\t\tbuffer += '!' + ident % 94; // \"base94\"\n\t\t\tident /= 94;\n\t\t} while (ident != 0);\n\t}\n\n\tvoid emit_name(const std::string &name) {\n\t\tfor (char c : name) {\n\t\t\tif (c == ':') {\n\t\t\t\t// Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file\n\t\t\t\t// to be unreadable. It cannot be escaped either, so replace it with the sideways colon.\n\t\t\t\tbuffer += \"..\";\n\t\t\t} else {\n\t\t\t\tbuffer += c;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid emit_var(const variable &var, const std::string &type, const std::string &name,\n\t size_t lsb_at, bool multipart) {\n\t\tassert(!streaming);\n\t\tbuffer += \"$var \" + type + \" \" + std::to_string(var.width) + \" \";\n\t\temit_ident(var.ident);\n\t\tbuffer += \" \";\n\t\temit_name(name);\n\t\tif (multipart || name.back() == ']' || lsb_at != 0) {\n\t\t\tif (var.width == 1)\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at) + \"]\";\n\t\t\telse\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at + var.width - 1) + \":\" + std::to_string(lsb_at) + \"]\";\n\t\t}\n\t\tbuffer += \" $end\\n\";\n\t}\n\n\tvoid emit_enddefinitions() {\n\t\tassert(!streaming);\n\t\tbuffer += \"$enddefinitions $end\\n\";\n\t\tstreaming = true;\n\t}\n\n\tvoid emit_time(uint64_t timestamp) {\n\t\tassert(streaming);\n\t\tbuffer += \"#\" + std::to_string(timestamp) + \"\\n\";\n\t}\n\n\tvoid emit_scalar(const variable &var) {\n\t\tassert(streaming);\n\t\tassert(var.width == 1);\n\t\tbuffer += (*var.curr ? '1' : '0');\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid emit_vector(const variable &var) {\n\t\tassert(streaming);\n\t\tbuffer += 'b';\n\t\tfor (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {\n\t\t\tbool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));\n\t\t\tbuffer += (bit_curr ? '1' : '0');\n\t\t}\n\t\tif (var.width == 0)\n\t\t\tbuffer += '0';\n\t\tbuffer += ' ';\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid reset_outlines() {\n\t\tfor (auto &outline_it : outlines)\n\t\t\toutline_it.second = /*warm=*/(outline_it.first == nullptr);\n\t}\n\n\tvariable &register_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) {\n\t\tif (aliases.count(curr)) {\n\t\t\treturn variables[aliases[curr]];\n\t\t} else {\n\t\t\tauto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first;\n\t\t\tconst size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\taliases[curr] = variables.size();\n\t\t\tif (constant) {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second });\n\t\t\t} else {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second });\n\t\t\t\tcache.insert(cache.end(), &curr[0], &curr[chunks]);\n\t\t\t}\n\t\t\treturn variables.back();\n\t\t}\n\t}\n\n\tbool test_variable(const variable &var) {\n\t\tif (var.cache_offset == (size_t)-1)\n\t\t\treturn false; // constant\n\t\tif (!*var.outline_warm) {\n\t\t\tvar.outline->eval();\n\t\t\t*var.outline_warm = true;\n\t\t}\n\t\tconst size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\tif (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) {\n\t\t\treturn false;\n\t\t} else {\n\t\t\tstd::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]);\n\t\t\treturn true;\n\t\t}\n\t}\n\n\tstatic std::vector<std::string> split_hierarchy(const std::string &hier_name) {\n\t\tstd::vector<std::string> hierarchy;\n\t\tsize_t prev = 0;\n\t\twhile (true) {\n\t\t\tsize_t curr = hier_name.find_first_of(' ', prev);\n\t\t\tif (curr == std::string::npos) {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev));\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev, curr - prev));\n\t\t\t\tprev = curr + 1;\n\t\t\t}\n\t\t}\n\t\treturn hierarchy;\n\t}\n\npublic:\n\tstd::string buffer;\n\n\tvoid timescale(unsigned number, const std::string &unit) {\n\t\temit_timescale(number, unit);\n\t}\n\n\tvoid add(const std::string &hier_name, const debug_item &item, bool multipart = false) {\n\t\tstd::vector<std::string> scope = split_hierarchy(hier_name);\n\t\tstd::string name = scope.back();\n\t\tscope.pop_back();\n\n\t\temit_scope(scope);\n\t\tswitch (item.type) {\n\t\t\t// Not the best naming but oh well...\n\t\t\tcase debug_item::VALUE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::WIRE:\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"reg\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::MEMORY: {\n\t\t\t\tconst size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\t\tfor (size_t index = 0; index < item.depth; index++) {\n\t\t\t\t\tchunk_t *nth_curr = &item.curr[stride * index];\n\t\t\t\t\tstd::string nth_name = name + '[' + std::to_string(index) + ']';\n\t\t\t\t\temit_var(register_variable(item.width, nth_curr),\n\t\t\t\t\t \"reg\", nth_name, item.lsb_at, multipart);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase debug_item::ALIAS:\n\t\t\t\t// Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value\n\t\t\t\t// can actually change, and must be tracked. In most cases the VCD identifier will be\n\t\t\t\t// unified with the aliased reg, but we should handle the case where only the alias is\n\t\t\t\t// added to the VCD writer, too.\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::OUTLINE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\ttemplate<class Filter>\n\tvoid add(const debug_items &items, const Filter &filter) {\n\t\t// `debug_items` is a map, so the items are already sorted in an order optimal for emitting\n\t\t// VCD scope sections.\n\t\tfor (auto &it : items.table)\n\t\t\tfor (auto &part : it.second)\n\t\t\t\tif (filter(it.first, part))\n\t\t\t\t\tadd(it.first, part, it.second.size() > 1);\n\t}\n\n\tvoid add(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &) {\n\t\t\treturn true;\n\t\t});\n\t}\n\n\tvoid add_without_memories(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &item) {\n\t\t\treturn item.type != debug_item::MEMORY;\n\t\t});\n\t}\n\n\tvoid sample(uint64_t timestamp) {\n\t\tbool first_sample = !streaming;\n\t\tif (first_sample) {\n\t\t\temit_scope({});\n\t\t\temit_enddefinitions();\n\t\t}\n\t\treset_outlines();\n\t\temit_time(timestamp);\n\t\tfor (auto var : variables)\n\t\t\tif (test_variable(var) || first_sample) {\n\t\t\t\tif (var.width == 1)\n\t\t\t\t\temit_scalar(var);\n\t\t\t\telse\n\t\t\t\t\temit_vector(var);\n\t\t\t}\n\t}\n};\n\n}\n\n#endif\n",
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@@ -156,35 +160,35 @@ export const filesystem = {
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  "binding.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef BINDING_H\n#define BINDING_H\n\n#include \"kernel/rtlil.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct RTLIL::Binding\n{\n\t// Represents a bind construct.\n\t//\n\t// The target of the binding is represented by target_type and\n\t// target_name (see comments above the fields).\n\n\tBinding(RTLIL::IdString target_type,\n\t RTLIL::IdString target_name);\n\n\tvirtual ~Binding() {}\n\n\t// Return a string describing the binding\n\tvirtual std::string describe() const = 0;\n\nprotected:\n\t// May be empty. If not, it's the name of the module or interface to\n\t// bind to.\n\tRTLIL::IdString target_type;\n\n\t// If target_type is nonempty (the usual case), this is a hierarchical\n\t// reference to the bind target. If target_type is empty, we have to\n\t// wait until the hierarchy pass to figure out whether this was the name\n\t// of a module/interface type or an instance.\n\tRTLIL::IdString target_name;\n\n\t// An attribute name which contains an ID that's unique across binding\n\t// instances (used to ensure we don't apply a binding twice to a module)\n\tRTLIL::IdString attr_name;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
159
- "bitpattern.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef BITPATTERN_H\n#define BITPATTERN_H\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct BitPatternPool\n{\n\tint width;\n\tstruct bits_t {\n\t\tstd::vector<RTLIL::State> bitdata;\n\t\tmutable unsigned int cached_hash;\n\t\tbits_t(int width = 0) : bitdata(width), cached_hash(0) { }\n\t\tRTLIL::State &operator[](int index) {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tconst RTLIL::State &operator[](int index) const {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tbool operator==(const bits_t &other) const {\n\t\t\tif (hash() != other.hash())\n\t\t\t\treturn false;\n\t\t\treturn bitdata == other.bitdata;\n\t\t}\n\t\tunsigned int hash() const {\n\t\t\tif (!cached_hash)\n\t\t\t\tcached_hash = hash_ops<std::vector<RTLIL::State>>::hash(bitdata);\n\t\t\treturn cached_hash;\n\t\t}\n\t};\n\tpool<bits_t> database;\n\n\tBitPatternPool(RTLIL::SigSpec sig)\n\t{\n\t\twidth = sig.size();\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\tif (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)\n\t\t\t\t\tpattern[i] = sig[i].data;\n\t\t\t\telse\n\t\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\t}\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tBitPatternPool(int width)\n\t{\n\t\tthis->width = width;\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tbits_t sig2bits(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits;\n\t\tbits.bitdata = sig.as_const().bits;\n\t\tfor (auto &b : bits.bitdata)\n\t\t\tif (b > RTLIL::State::S1)\n\t\t\t\tb = RTLIL::State::Sa;\n\t\treturn bits;\n\t}\n\n\tbool match(bits_t a, bits_t b)\n\t{\n\t\tlog_assert(int(a.bitdata.size()) == width);\n\t\tlog_assert(int(b.bitdata.size()) == width);\n\t\tfor (int i = 0; i < width; i++)\n\t\t\tif (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool has_any(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool has_all(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\t\tif (bits[i] > RTLIL::State::S1 && it[i] <= RTLIL::State::S1)\n\t\t\t\t\t\tgoto next_database_entry;\n\t\t\t\treturn true;\n\tnext_database_entry:;\n\t\t\t}\n\t\treturn false;\n\t}\n\n\tbool take(RTLIL::SigSpec sig)\n\t{\n\t\tbool status = false;\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto it = database.begin(); it != database.end();)\n\t\t\tif (match(*it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\t\tif ((*it)[i] != RTLIL::State::Sa || bits[i] == RTLIL::State::Sa)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbits_t new_pattern;\n\t\t\t\t\tnew_pattern.bitdata = it->bitdata;\n\t\t\t\t\tnew_pattern[i] = bits[i] == RTLIL::State::S1 ? RTLIL::State::S0 : RTLIL::State::S1;\n\t\t\t\t\tdatabase.insert(new_pattern);\n\t\t\t\t}\n\t\t\t\tit = database.erase(it);\n\t\t\t\tstatus = true;\n\t\t\t\tcontinue;\n\t\t\t} else\n\t\t\t\t++it;\n\t\treturn status;\n\t}\n\n\tbool take_all()\n\t{\n\t\tif (database.empty())\n\t\t\treturn false;\n\t\tdatabase.clear();\n\t\treturn true;\n\t}\n\n\tbool empty()\n\t{\n\t\treturn database.empty();\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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+ "bitpattern.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef BITPATTERN_H\n#define BITPATTERN_H\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct BitPatternPool\n{\n\tint width;\n\tstruct bits_t {\n\t\tstd::vector<RTLIL::State> bitdata;\n\t\tmutable unsigned int cached_hash;\n\t\tbits_t(int width = 0) : bitdata(width), cached_hash(0) { }\n\t\tRTLIL::State &operator[](int index) {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tconst RTLIL::State &operator[](int index) const {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tbool operator==(const bits_t &other) const {\n\t\t\tif (hash() != other.hash())\n\t\t\t\treturn false;\n\t\t\treturn bitdata == other.bitdata;\n\t\t}\n\t\tunsigned int hash() const {\n\t\t\tif (!cached_hash)\n\t\t\t\tcached_hash = hash_ops<std::vector<RTLIL::State>>::hash(bitdata);\n\t\t\treturn cached_hash;\n\t\t}\n\t};\n\tpool<bits_t> database;\n\n\tBitPatternPool(RTLIL::SigSpec sig)\n\t{\n\t\twidth = sig.size();\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\tif (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)\n\t\t\t\t\tpattern[i] = sig[i].data;\n\t\t\t\telse\n\t\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\t}\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tBitPatternPool(int width)\n\t{\n\t\tthis->width = width;\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tbits_t sig2bits(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits;\n\t\tbits.bitdata = sig.as_const().bits();\n\t\tfor (auto &b : bits.bitdata)\n\t\t\tif (b > RTLIL::State::S1)\n\t\t\t\tb = RTLIL::State::Sa;\n\t\treturn bits;\n\t}\n\n\tbool match(bits_t a, bits_t b)\n\t{\n\t\tlog_assert(int(a.bitdata.size()) == width);\n\t\tlog_assert(int(b.bitdata.size()) == width);\n\t\tfor (int i = 0; i < width; i++)\n\t\t\tif (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool has_any(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool has_all(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\t\tif (bits[i] > RTLIL::State::S1 && it[i] <= RTLIL::State::S1)\n\t\t\t\t\t\tgoto next_database_entry;\n\t\t\t\treturn true;\n\tnext_database_entry:;\n\t\t\t}\n\t\treturn false;\n\t}\n\n\tbool take(RTLIL::SigSpec sig)\n\t{\n\t\tbool status = false;\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto it = database.begin(); it != database.end();)\n\t\t\tif (match(*it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\t\tif ((*it)[i] != RTLIL::State::Sa || bits[i] == RTLIL::State::Sa)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbits_t new_pattern;\n\t\t\t\t\tnew_pattern.bitdata = it->bitdata;\n\t\t\t\t\tnew_pattern[i] = bits[i] == RTLIL::State::S1 ? RTLIL::State::S0 : RTLIL::State::S1;\n\t\t\t\t\tdatabase.insert(new_pattern);\n\t\t\t\t}\n\t\t\t\tit = database.erase(it);\n\t\t\t\tstatus = true;\n\t\t\t\tcontinue;\n\t\t\t} else\n\t\t\t\t++it;\n\t\treturn status;\n\t}\n\n\tbool take_all()\n\t{\n\t\tif (database.empty())\n\t\t\treturn false;\n\t\tdatabase.clear();\n\t\treturn true;\n\t}\n\n\tbool empty()\n\t{\n\t\treturn database.empty();\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "cellaigs.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLAIGS_H\n#define CELLAIGS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AigNode\n{\n\tIdString portname;\n\tint portbit;\n\tbool inverter;\n\tint left_parent, right_parent;\n\tvector<pair<IdString, int>> outports;\n\n\tAigNode();\n\tbool operator==(const AigNode &other) const;\n\tunsigned int hash() const;\n};\n\nstruct Aig\n{\n\tstring name;\n\tvector<AigNode> nodes;\n\tAig(Cell *cell);\n\n\tbool operator==(const Aig &other) const;\n\tunsigned int hash() const;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "celledges.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLEDGES_H\n#define CELLEDGES_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AbstractCellEdgesDatabase\n{\n\tvirtual ~AbstractCellEdgesDatabase() { }\n\tvirtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;\n\tbool add_edges_from_cell(RTLIL::Cell *cell);\n};\n\nstruct FwdCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tFwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[from_sigbit].insert(to_sigbit);\n\t}\n};\n\nstruct RevCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tRevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[to_sigbit].insert(from_sigbit);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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- "celltypes.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($buf), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits)\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type.in(ID($_BUF_), ID($buf)))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.bits.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
163
- "consteval.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).bits;\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y.bits[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($macc))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tif (!eval(macc.bit_ports, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (auto &port : macc.ports) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
164
- "constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(chain)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(qwp_position)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\n",
166
+ "celltypes.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n\tbool is_combinatorial;\n\tbool is_synthesizable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($buf), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits())\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type.in(ID($_BUF_), ID($buf)))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
167
+ "consteval.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits()[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).to_bits();\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> slave_bits = y_values.at(i).to_bits();\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits()[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($macc))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tif (!eval(macc.bit_ports, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (auto &port : macc.ports) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
168
+ "constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(chain)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\nX(area)\nX(capacitance)\n",
165
169
  "cost.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef COST_H\n#define COST_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellCosts\n{\n\n\tprivate:\n\tdict<RTLIL::IdString, int> mod_cost_cache_;\n\tDesign *design_ = nullptr;\n\n\tpublic:\n\tCellCosts(RTLIL::Design *design) : design_(design) { }\n\n\tstatic const dict<RTLIL::IdString, int>& default_gate_cost() {\n\t\t// Default size heuristics for several common PDK standard cells\n\t\t// used by abc and stat\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 4 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 4 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 4 },\n\t\t\t{ ID($_ORNOT_), 4 },\n\t\t\t{ ID($_XOR_), 5 },\n\t\t\t{ ID($_XNOR_), 5 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 7 },\n\t\t\t{ ID($_OAI4_), 7 },\n\t\t\t{ ID($_MUX_), 4 },\n\t\t\t{ ID($_NMUX_), 4 },\n\t\t};\n\t\treturn db;\n\t}\n\n\tstatic const dict<RTLIL::IdString, int>& cmos_gate_cost() {\n\t\t// Estimated CMOS transistor counts for several common PDK standard cells\n\t\t// used by stat and optionally by abc\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 6 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 6 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 6 },\n\t\t\t{ ID($_ORNOT_), 6 },\n\t\t\t{ ID($_XOR_), 12 },\n\t\t\t{ ID($_XNOR_), 12 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 8 },\n\t\t\t{ ID($_OAI4_), 8 },\n\t\t\t{ ID($_MUX_), 12 },\n\t\t\t{ ID($_NMUX_), 10 },\n\t\t\t{ ID($_DFF_P_), 16 },\n\t\t\t{ ID($_DFF_N_), 16 },\n\t\t};\n\t\treturn db;\n\t}\n\n\t// Get the cell cost for a cell based on its parameters.\n\t// This cost is an *approximate* upper bound for the number of gates that\n\t// the cell will get mapped to with \"opt -fast; techmap\"\n\t// The intended usage is for flattening heuristics and similar situations\n\tunsigned int get(RTLIL::Cell *cell);\n\t// Sum up the cell costs of all cells in the module\n\t// and all its submodules recursively\n\tunsigned int get(RTLIL::Module *mod);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
166
- "drivertools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef DRIVERTOOLS_H\n#define DRIVERTOOLS_H\n\n#include <type_traits>\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// TODO move implementation into a .cc file\n\nstruct DriveBit;\n\nstruct DriveChunkWire;\nstruct DriveChunkPort;\nstruct DriveChunkMarker;\nstruct DriveChunk;\n\nstruct DriveSpec;\n\nconst char *log_signal(DriveChunkWire const &chunk);\nconst char *log_signal(DriveChunkPort const &chunk);\nconst char *log_signal(DriveChunkMarker const &chunk);\nconst char *log_signal(DriveChunk const &chunk);\nconst char *log_signal(DriveSpec const &chunk);\n\nenum class DriveType : unsigned char\n{\n\tNONE,\n\tCONSTANT,\n\tWIRE,\n\tPORT,\n\tMULTIPLE,\n\tMARKER,\n};\n\nstruct DriveBitWire\n{\n\tWire *wire;\n\tint offset;\n\n\tDriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {}\n\n\tbool operator==(const DriveBitWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\t}\n\n\toperator SigBit() const\n\t{\n\t\treturn SigBit(wire, offset);\n\t}\n};\n\nstruct DriveBitPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\n\tDriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {}\n\n\tbool operator==(const DriveBitPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t}\n};\n\n\nstruct DriveBitMarker\n{\n\tint marker;\n\tint offset;\n\n\tDriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {}\n\n\tbool operator==(const DriveBitMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(marker, offset);\n\t}\n\n};\n\nstruct DriveBitMultiple\n{\nprivate:\n\tpool<DriveBit> multiple_;\n\npublic:\n\tDriveBitMultiple();\n\tDriveBitMultiple(DriveBit const &single);\n\n\tpool<DriveBit> const &multiple() const { return multiple_; }\n\n\tvoid merge(DriveBitMultiple const &other)\n\t{\n\t\tfor (DriveBit const &single : other.multiple_)\n\t\t\tmerge(single);\n\t}\n\n\tvoid merge(DriveBitMultiple &&other)\n\t{\n\t\tfor (DriveBit &single : other.multiple_)\n\t\t\tmerge(std::move(single));\n\t}\n\n\tvoid merge(DriveBit const &single);\n\tvoid merge(DriveBit &&single);\n\n\tbool operator==(const DriveBitMultiple &other) const\n\t{\n\t\treturn multiple_ == other.multiple_;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t return multiple_.hash();\n\t}\n};\n\nstruct DriveBit\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tState constant_;\n\t\tDriveBitWire wire_;\n\t\tDriveBitPort port_;\n\t\tDriveBitMarker marker_;\n\t\tDriveBitMultiple multiple_;\n\t};\npublic:\n\tDriveBit() {}\n\n\tDriveBit(SigBit const &bit);\n\n\tDriveBit(DriveBit const &other) { *this = other; }\n\tDriveBit(DriveBit &&other) { *this = other; }\n\n\n\tDriveBit(State constant) { *this = constant; }\n\tDriveBit(DriveBitWire const &wire) { *this = wire; }\n\tDriveBit(DriveBitWire &&wire) { *this = wire; }\n\tDriveBit(DriveBitPort const &port) { *this = port; }\n\tDriveBit(DriveBitPort &&port) { *this = port; }\n\tDriveBit(DriveBitMarker const &marker) { *this = marker; }\n\tDriveBit(DriveBitMarker &&marker) { *this = marker; }\n\tDriveBit(DriveBitMultiple const &multiple) { *this = multiple; }\n\tDriveBit(DriveBitMultiple &&multiple) { *this = multiple; }\n\n\t~DriveBit() { set_none(); }\n\n\tvoid set_none()\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveBitWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveBitPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveBitMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveBitMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t}\n\n\tDriveBit &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBit &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(State constant)\n\t{\n\t\tset_none();\n\t\tconstant_ = constant;\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple const &multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple &&multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\tunsigned int inner;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tinner = 0;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tinner = constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\tinner = wire_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tinner = port_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tinner = marker_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tinner = multiple_.hash();\n\t\t\t\tbreak;\n\t\t}\n\t\treturn mkhash((unsigned int)type_, inner);\n\t}\n\n\tbool operator==(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveBit &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tlog_assert(!\"TODO\");\n\t\t}\n\t\tlog_abort();\n\t}\n\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tState &constant() { log_assert(is_constant()); return constant_; }\n\tState const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveBitWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveBitWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveBitPort &port() { log_assert(is_port()); return port_; }\n\tDriveBitPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveBitMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\tvoid merge(DriveBit const &other);\n\n};\n\ninline DriveBitMultiple::DriveBitMultiple() {}\ninline DriveBitMultiple::DriveBitMultiple(DriveBit const &single)\n{\n\tmultiple_.emplace(single);\n}\n\nstruct DriveChunkWire\n{\n\tWire *wire;\n\tint offset;\n\tint width;\n\n\tDriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {}\n\tDriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitWire operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitWire(wire, offset + i);\n\t}\n\n\tbool can_append(DriveBitWire const &bit) const;\n\tbool try_append(DriveBitWire const &bit);\n\tbool try_append(DriveChunkWire const &chunk);\n\n\t// Whether this chunk is a whole wire\n\tbool is_whole() const { return offset == 0 && width == wire->width; }\n\n\tbool operator==(const DriveChunkWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(wire->name.hash(), width), offset);\n\t}\n\n\texplicit operator SigChunk() const\n\t{\n\t\treturn SigChunk(wire, offset, width);\n\t}\n};\n\nstruct DriveChunkPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\tint width;\n\n\tDriveChunkPort(Cell *cell, IdString port, int offset, int width) :\n\t\tcell(cell), port(port), offset(offset), width(width) { }\n\tDriveChunkPort(Cell *cell, IdString port) :\n\t\tcell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { }\n\tDriveChunkPort(Cell *cell, std::pair<IdString, SigSpec> const &conn) :\n\t\tcell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { }\n\tDriveChunkPort(DriveBitPort const &bit) :\n\t\tcell(bit.cell), port(bit.port), offset(bit.offset), width(1) { }\n\n\tint size() const { return width; }\n\n\tDriveBitPort operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitPort(cell, port, offset + i);\n\t}\n\n\tbool can_append(DriveBitPort const &bit) const;\n\tbool try_append(DriveBitPort const &bit);\n\tbool try_append(DriveChunkPort const &chunk);\n\n\t// Whether this chunk is a whole port\n\tbool is_whole() const\n\t{\n\t\treturn offset == 0 && width == cell->connections().at(port).size();\n\t}\n\n\tbool operator==(const DriveChunkPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset);\n\t}\n};\n\n\nstruct DriveChunkMarker\n{\n\tint marker;\n\tint offset;\n\tint width;\n\n\tDriveChunkMarker(int marker, int offset, int width) :\n\t\tmarker(marker), offset(offset), width(width) {}\n\tDriveChunkMarker(DriveBitMarker const &bit) :\n\t\tmarker(bit.marker), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitMarker operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitMarker(marker, offset + i);\n\t}\n\n\tbool can_append(DriveBitMarker const &bit) const;\n\tbool try_append(DriveBitMarker const &bit);\n\tbool try_append(DriveChunkMarker const &chunk);\n\n\tbool operator==(const DriveChunkMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(marker, width), offset);\n\t}\n};\n\nstruct DriveChunkMultiple\n{\nprivate:\n\tmutable pool<DriveChunk> multiple_;\n\tint width_;\n\npublic:\n\tpool<DriveChunk> const &multiple() const { return multiple_; }\n\n\tDriveChunkMultiple(DriveBitMultiple const &bit);\n\n\tint size() const { return width_; }\n\n\tDriveBitMultiple operator[](int i) const;\n\n\tbool can_append(DriveBitMultiple const &bit) const;\n\n\tbool try_append(DriveBitMultiple const &bit);\n\n\n\tbool can_append(DriveChunkMultiple const &bit) const;\n\n\tbool try_append(DriveChunkMultiple const &bit);\n\n\tbool operator==(const DriveChunkMultiple &other) const\n\t{\n\t\treturn width_ == other.width_ && multiple_ == other.multiple_;\n\t}\n\n\tbool operator<(const DriveChunkMultiple &other) const\n\t{\n\t\tif (multiple_.size() < other.multiple_.size())\n\n\t\tmultiple_.sort();\n\t\treturn false; // TODO implement, canonicalize order\n\t}\n\n\tunsigned int hash() const\n\t{\n\t return mkhash(width_, multiple_.hash());\n\t}\n};\n\nstruct DriveChunk\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tint none_;\n\t\tConst constant_;\n\t\tDriveChunkWire wire_;\n\t\tDriveChunkPort port_;\n\t\tDriveChunkMarker marker_;\n\t\tDriveChunkMultiple multiple_;\n\t};\n\npublic:\n\tDriveChunk() { set_none(); }\n\n\tDriveChunk(DriveChunk const &other) { *this = other; }\n\tDriveChunk(DriveChunk &&other) { *this = other; }\n\n\tDriveChunk(DriveBit const &other) { *this = other; }\n\n\tDriveChunk(Const const &constant) { *this = constant; }\n\tDriveChunk(Const &&constant) { *this = constant; }\n\tDriveChunk(DriveChunkWire const &wire) { *this = wire; }\n\tDriveChunk(DriveChunkWire &&wire) { *this = wire; }\n\tDriveChunk(DriveChunkPort const &port) { *this = port; }\n\tDriveChunk(DriveChunkPort &&port) { *this = port; }\n\tDriveChunk(DriveChunkMarker const &marker) { *this = marker; }\n\tDriveChunk(DriveChunkMarker &&marker) { *this = marker; }\n\tDriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; }\n\tDriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; }\n\n\t~DriveChunk() { set_none(); }\n\n\tDriveBit operator[](int i) const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn DriveBit();\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_[i];\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_[i];\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_[i];\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_[i];\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_[i];\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tvoid set_none(int width = 0)\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tnone_ = width;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tconstant_.~Const();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveChunkWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveChunkPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveChunkMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveChunkMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t\tnone_ = width;\n\t}\n\n\tDriveChunk &operator=(DriveChunk const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunk &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const const &constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(constant);\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const &&constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(std::move(constant));\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple const &multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple &&multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type())\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(1);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = Const(other.constant());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = DriveChunkWire(other.wire());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = DriveChunkPort(other.port());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = DriveChunkMarker(other.marker());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = DriveChunkMultiple(other.multiple());\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tbool can_append(DriveBit const &bit) const;\n\tbool try_append(DriveBit const &bit);\n\tbool try_append(DriveChunk const &chunk);\n\n\tunsigned int hash() const\n\t{\n\t\tunsigned int inner;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tinner = 0;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tinner = constant_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\tinner = wire_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tinner = port_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tinner = marker_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tinner = multiple_.hash();\n\t\t\t\tbreak;\n\t\t}\n\t\treturn mkhash((unsigned int)type_, inner);\n\t}\n\n\tbool operator==(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveChunk &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ < other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tConst &constant() { log_assert(is_constant()); return constant_; }\n\tConst const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveChunkWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveChunkPort &port() { log_assert(is_port()); return port_; }\n\tDriveChunkPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveChunkMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\n\tint size() const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn none_;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_.size();\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_.size();\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_.size();\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_.size();\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_.size();\n\t\t}\n\t\tlog_abort();\n\t}\n};\n\ninline DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit)\n\t: width_(1)\n{\n\tfor (auto const &bit : bit.multiple())\n\t\tmultiple_.emplace(bit);\n}\n\nstruct DriveSpec\n{\nprivate:\n\tint width_ = 0;\n\tmutable std::vector<DriveChunk> chunks_;\n\tmutable std::vector<DriveBit> bits_;\n\tmutable unsigned int hash_ = 0;\npublic:\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tDriveSpec() {}\n\n\tDriveSpec(DriveChunk const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkWire const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkPort const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMarker const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; }\n\n\tDriveSpec(DriveBit const &bit) { *this = bit; }\n\tDriveSpec(DriveBitWire const &bit) { *this = bit; }\n\tDriveSpec(DriveBitPort const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMarker const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMultiple const &bit) { *this = bit; }\n\n\tDriveSpec(std::vector<DriveChunk> const &chunks) : chunks_(chunks) { compute_width(); }\n\n\tDriveSpec(std::vector<DriveBit> const &bits)\n\t{\n\t\tfor (auto const &bit : bits)\n\t\t\tappend(bit);\n\t}\n\n\tDriveSpec(SigSpec const &sig)\n\t{\n\t\t// TODO: converting one chunk at a time would be faster\n\t\tfor (auto const &bit : sig.bits())\n\t\t\tappend(bit);\n\t}\n\n\tstd::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }\n\tstd::vector<DriveBit> const &bits() const { unpack(); return bits_; }\n\n\tint size() const { return width_; }\n\n\tvoid append(DriveBit const &bit);\n\n\tvoid append(DriveChunk const &chunk);\n\n\tvoid pack() const;\n\n\tvoid unpack() const;\n\n\tDriveBit &operator[](int index)\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tconst DriveBit &operator[](int index) const\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tvoid clear()\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\twidth_ = 0;\n\t}\n\n\tDriveSpec &operator=(DriveChunk const &chunk)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(chunk);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); }\n\n\tDriveSpec &operator=(DriveBit const &bit)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(bit);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); }\n\n\tunsigned int hash() const {\n\t\tif (hash_ != 0) return hash_;\n\n\t\tpack();\n\t\thash_ = hash_ops<std::vector<DriveChunk>>().hash(chunks_);\n\t\thash_ |= (hash_ == 0);\n\t\treturn hash_;\n\t}\n\n\tbool operator==(DriveSpec const &other) const {\n\t\tif (size() != other.size() || hash() != other.hash())\n\t\t\treturn false;\n\t\treturn chunks() == other.chunks();\n\t}\n\nprivate:\n\tvoid compute_width();\n};\n\n\n\nstruct DriverMap\n{\n\tCellTypes celltypes;\n\n\tDriverMap() { celltypes.setup(); }\n\tDriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); }\n\nprivate:\n\n\t// Internally we represent all DriveBits by mapping them to DriveBitIds\n\t// which use less memory and are cheaper to compare.\n\tstruct DriveBitId\n\t{\n\t\tint id = -1;\n\n\t\tDriveBitId() {};\n\n\t\tDriveBitId(int id) : id(id) { }\n\n\t\tbool operator==(const DriveBitId &other) const { return id == other.id; }\n\t\tbool operator!=(const DriveBitId &other) const { return id != other.id; }\n\t\tbool operator<(const DriveBitId &other) const { return id < other.id; }\n\t\tunsigned int hash() const { return id; }\n\t};\n\t// Essentially a dict<DriveBitId, pool<DriveBitId>> but using less memory\n\t// and fewer allocations\n\tstruct DriveBitGraph {\n\t\tdict<DriveBitId, DriveBitId> first_edges;\n\t\tdict<DriveBitId, DriveBitId> second_edges;\n\t\tdict<DriveBitId, pool<DriveBitId>> more_edges;\n\n\t\tvoid add_edge(DriveBitId src, DriveBitId dst);\n\t\tDriveBitId pop_edge(DriveBitId src);\n\t\tvoid clear(DriveBitId src);\n\t\tbool contains(DriveBitId src);\n\t\tint count(DriveBitId src);\n\n\t\tDriveBitId at(DriveBitId src, int index);\n\t};\n\n\t// The following two maps maintain a sparse DriveBit to DriveBitId mapping.\n\t// This saves a lot of memory compared to a `dict<DriveBit, DriveBitId>` or\n\t// `idict<DriveBit>`.\n\n\t// Maps wires to the first DriveBitId of the consecutive range used for\n\t// that wire.\n\tdict<Wire *, DriveBitId> wire_offsets;\n\n\t// Maps cell ports to a the first DriveBitId of the consecutive range used\n\t// for that cell port.\n\tdict<pair<Cell *, IdString>, DriveBitId> port_offsets;\n\n\t// For the inverse map that maps DriveBitIds back to DriveBits we use a\n\t// sorted map containing only the first DriveBit for each wire and cell\n\t// port.\n\tstd::map<DriveBitId, DriveBit> drive_bits;\n\n\t// As a memory optimization for gate level net lists we store single-bit\n\t// wires and cell ports in a `dict` which requires less memory and fewer\n\t// allocations than `std::map` but doesn't support the kind of lookups we\n\t// need for a sparse coarse grained mapping.\n\tdict<DriveBitId, DriveBit> isolated_drive_bits;\n\n\t// Used for allocating DriveBitIds, none and constant states use a fixewd\n\t// mapping to the first few ids, which we need to skip.\n\tint next_offset = 1 + (int)State::Sm;\n\n\t// Union-Find over directly connected bits that share the same single\n\t// driver or are undriven. We never merge connections between drivers\n\t// and/or kept wires.\n\tmfp<DriveBitId> same_driver;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally unambiguous (one side only drives or requires a driven value).\n\tDriveBitGraph connected_drivers;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally ambiguous. Every such ambiguous connection is also present in\n\t// the reverse direction and has to be resolved when querying drivers.\n\tDriveBitGraph connected_undirected;\n\n\t// Subset of `connected_undirected` for caching the resolved driving\n\t// direction. In case multiple drivers are present this can still contain\n\t// both orientations of a single connection, but for a single driver only\n\t// one will be present.\n\tDriveBitGraph connected_oriented;\n\n\t// Stores for which bits we already resolved the orientation (cached in\n\t// `connected_oriented`).\n\tpool<DriveBitId> oriented_present;\n\n\n\tenum class BitMode {\n\t\tNONE = 0, // Not driven, no need to keep wire\n\t\tDRIVEN = 1, // Not driven, uses a value driven elsewhere\n\t\tDRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection\n\t\tKEEP = 3, // Wire that should be kept\n\t\tTRISTATE = 4, // Can drive a value but can also use a value driven elsewhere\n\t\tDRIVER = 5, // Drives a value\n\t};\n\n\tBitMode bit_mode(DriveBit const &bit);\n\tDriveBitId id_from_drive_bit(DriveBit const &bit);\n\tDriveBit drive_bit_from_id(DriveBitId id);\n\n\tvoid connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_undirected(DriveBitId a_id, DriveBitId b_id);\n\npublic:\n\n\tvoid add(Module *module);\n\n\t// Add a single bit connection to the driver map.\n\tvoid add(DriveBit const &a, DriveBit const &b);\n\n\ttemplate<typename T>\n\tstatic constexpr bool is_sig_type() {\n\t\treturn\n\t\t\tstd::is_same<T, SigSpec>::value ||\n\t\t\tstd::is_same<T, SigChunk>::value ||\n\t\t\tstd::is_same<T, DriveSpec>::value ||\n\t\t\tstd::is_same<T, DriveChunk>::value ||\n\t\t\tstd::is_same<T, DriveChunkPort>::value ||\n\t\t\tstd::is_same<T, DriveChunkWire>::value ||\n\t\t\tstd::is_same<T, Const>::value;\n\t}\n\n\t// We use the enable_if to produce better compiler errors when unsupported\n\t// types are used\n\ttemplate<typename T, typename U>\n\ttypename std::enable_if<is_sig_type<T>() && is_sig_type<U>()>::type\n\tadd(T const &a, U const &b)\n\t{\n\t\tlog_assert(a.size() == b.size());\n\t\tfor (int i = 0; i != GetSize(a); ++i)\n\t\t\tadd(DriveBit(a[i]), DriveBit(b[i]));\n\t}\n\n\n\t// Specialized version that avoids unpacking\n\tvoid add(SigSpec const &a, SigSpec const &b);\n\nprivate:\n\tvoid add_port(Cell *cell, IdString const &port, SigSpec const &b);\n\n\t// Only used a local variables in `orient_undirected`, always cleared, only\n\t// stored to reduce allocations.\n\tpool<DriveBitId> orient_undirected_seen;\n\tpool<DriveBitId> orient_undirected_drivers;\n\tdict<DriveBitId, int> orient_undirected_distance;\n\n\tvoid orient_undirected(DriveBitId id);\n\npublic:\n\tDriveBit operator()(DriveBit const &bit);\n\n\tDriveSpec operator()(DriveSpec spec);\n\nprivate:\n\tbool keep_wire(Wire *wire) {\n\t\t// TODO configurable\n\t\treturn wire->has_attribute(ID(keep));\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
170
+ "drivertools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef DRIVERTOOLS_H\n#define DRIVERTOOLS_H\n\n#include <type_traits>\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// TODO move implementation into a .cc file\n\nstruct DriveBit;\n\nstruct DriveChunkWire;\nstruct DriveChunkPort;\nstruct DriveChunkMarker;\nstruct DriveChunk;\n\nstruct DriveSpec;\n\nconst char *log_signal(DriveChunkWire const &chunk);\nconst char *log_signal(DriveChunkPort const &chunk);\nconst char *log_signal(DriveChunkMarker const &chunk);\nconst char *log_signal(DriveChunk const &chunk);\nconst char *log_signal(DriveSpec const &chunk);\n\nenum class DriveType : unsigned char\n{\n\tNONE,\n\tCONSTANT,\n\tWIRE,\n\tPORT,\n\tMULTIPLE,\n\tMARKER,\n};\n\nstruct DriveBitWire\n{\n\tWire *wire;\n\tint offset;\n\n\tDriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {}\n\n\tbool operator==(const DriveBitWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\t}\n\n\toperator SigBit() const\n\t{\n\t\treturn SigBit(wire, offset);\n\t}\n};\n\nstruct DriveBitPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\n\tDriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {}\n\n\tbool operator==(const DriveBitPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t}\n};\n\n\nstruct DriveBitMarker\n{\n\tint marker;\n\tint offset;\n\n\tDriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {}\n\n\tbool operator==(const DriveBitMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(marker, offset);\n\t}\n\n};\n\nstruct DriveBitMultiple\n{\nprivate:\n\tpool<DriveBit> multiple_;\n\npublic:\n\tDriveBitMultiple();\n\tDriveBitMultiple(DriveBit const &single);\n\n\tpool<DriveBit> const &multiple() const { return multiple_; }\n\n\tvoid merge(DriveBitMultiple const &other)\n\t{\n\t\tfor (DriveBit const &single : other.multiple_)\n\t\t\tmerge(single);\n\t}\n\n\tvoid merge(DriveBitMultiple &&other)\n\t{\n\t\tfor (DriveBit &single : other.multiple_)\n\t\t\tmerge(std::move(single));\n\t}\n\n\tvoid merge(DriveBit const &single);\n\tvoid merge(DriveBit &&single);\n\n\tbool operator==(const DriveBitMultiple &other) const\n\t{\n\t\treturn multiple_ == other.multiple_;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t return multiple_.hash();\n\t}\n};\n\nstruct DriveBit\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tState constant_;\n\t\tDriveBitWire wire_;\n\t\tDriveBitPort port_;\n\t\tDriveBitMarker marker_;\n\t\tDriveBitMultiple multiple_;\n\t};\npublic:\n\tDriveBit() {}\n\n\tDriveBit(SigBit const &bit);\n\n\tDriveBit(DriveBit const &other) { *this = other; }\n\tDriveBit(DriveBit &&other) { *this = other; }\n\n\n\tDriveBit(State constant) { *this = constant; }\n\tDriveBit(DriveBitWire const &wire) { *this = wire; }\n\tDriveBit(DriveBitWire &&wire) { *this = wire; }\n\tDriveBit(DriveBitPort const &port) { *this = port; }\n\tDriveBit(DriveBitPort &&port) { *this = port; }\n\tDriveBit(DriveBitMarker const &marker) { *this = marker; }\n\tDriveBit(DriveBitMarker &&marker) { *this = marker; }\n\tDriveBit(DriveBitMultiple const &multiple) { *this = multiple; }\n\tDriveBit(DriveBitMultiple &&multiple) { *this = multiple; }\n\n\t~DriveBit() { set_none(); }\n\n\tvoid set_none()\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveBitWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveBitPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveBitMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveBitMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t}\n\n\tDriveBit &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBit &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(State constant)\n\t{\n\t\tset_none();\n\t\tconstant_ = constant;\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple const &multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple &&multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\tunsigned int inner = 0;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tinner = 0;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tinner = constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\tinner = wire_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tinner = port_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tinner = marker_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tinner = multiple_.hash();\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tlog_abort();\n\t\t\t\tbreak;\n\t\t}\n\t\treturn mkhash((unsigned int)type_, inner);\n\t}\n\n\tbool operator==(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveBit &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tlog_assert(!\"TODO\");\n\t\t}\n\t\tlog_abort();\n\t}\n\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tState &constant() { log_assert(is_constant()); return constant_; }\n\tState const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveBitWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveBitWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveBitPort &port() { log_assert(is_port()); return port_; }\n\tDriveBitPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveBitMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\tvoid merge(DriveBit const &other);\n\n};\n\ninline DriveBitMultiple::DriveBitMultiple() {}\ninline DriveBitMultiple::DriveBitMultiple(DriveBit const &single)\n{\n\tmultiple_.emplace(single);\n}\n\nstruct DriveChunkWire\n{\n\tWire *wire;\n\tint offset;\n\tint width;\n\n\tDriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {}\n\tDriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitWire operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitWire(wire, offset + i);\n\t}\n\n\tbool can_append(DriveBitWire const &bit) const;\n\tbool try_append(DriveBitWire const &bit);\n\tbool try_append(DriveChunkWire const &chunk);\n\n\t// Whether this chunk is a whole wire\n\tbool is_whole() const { return offset == 0 && width == wire->width; }\n\n\tbool operator==(const DriveChunkWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(wire->name.hash(), width), offset);\n\t}\n\n\texplicit operator SigChunk() const\n\t{\n\t\treturn SigChunk(wire, offset, width);\n\t}\n};\n\nstruct DriveChunkPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\tint width;\n\n\tDriveChunkPort(Cell *cell, IdString port, int offset, int width) :\n\t\tcell(cell), port(port), offset(offset), width(width) { }\n\tDriveChunkPort(Cell *cell, IdString port) :\n\t\tcell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { }\n\tDriveChunkPort(Cell *cell, std::pair<IdString, SigSpec> const &conn) :\n\t\tcell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { }\n\tDriveChunkPort(DriveBitPort const &bit) :\n\t\tcell(bit.cell), port(bit.port), offset(bit.offset), width(1) { }\n\n\tint size() const { return width; }\n\n\tDriveBitPort operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitPort(cell, port, offset + i);\n\t}\n\n\tbool can_append(DriveBitPort const &bit) const;\n\tbool try_append(DriveBitPort const &bit);\n\tbool try_append(DriveChunkPort const &chunk);\n\n\t// Whether this chunk is a whole port\n\tbool is_whole() const\n\t{\n\t\treturn offset == 0 && width == cell->connections().at(port).size();\n\t}\n\n\tbool operator==(const DriveChunkPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset);\n\t}\n};\n\n\nstruct DriveChunkMarker\n{\n\tint marker;\n\tint offset;\n\tint width;\n\n\tDriveChunkMarker(int marker, int offset, int width) :\n\t\tmarker(marker), offset(offset), width(width) {}\n\tDriveChunkMarker(DriveBitMarker const &bit) :\n\t\tmarker(bit.marker), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitMarker operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitMarker(marker, offset + i);\n\t}\n\n\tbool can_append(DriveBitMarker const &bit) const;\n\tbool try_append(DriveBitMarker const &bit);\n\tbool try_append(DriveChunkMarker const &chunk);\n\n\tbool operator==(const DriveChunkMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(marker, width), offset);\n\t}\n};\n\nstruct DriveChunkMultiple\n{\nprivate:\n\tmutable pool<DriveChunk> multiple_;\n\tint width_;\n\npublic:\n\tpool<DriveChunk> const &multiple() const { return multiple_; }\n\n\tDriveChunkMultiple(DriveBitMultiple const &bit);\n\n\tint size() const { return width_; }\n\n\tDriveBitMultiple operator[](int i) const;\n\n\tbool can_append(DriveBitMultiple const &bit) const;\n\n\tbool try_append(DriveBitMultiple const &bit);\n\n\n\tbool can_append(DriveChunkMultiple const &bit) const;\n\n\tbool try_append(DriveChunkMultiple const &bit);\n\n\tbool operator==(const DriveChunkMultiple &other) const\n\t{\n\t\treturn width_ == other.width_ && multiple_ == other.multiple_;\n\t}\n\n\tbool operator<(const DriveChunkMultiple &other) const\n\t{\n\t\tif (multiple_.size() < other.multiple_.size())\n\n\t\tmultiple_.sort();\n\t\treturn false; // TODO implement, canonicalize order\n\t}\n\n\tunsigned int hash() const\n\t{\n\t return mkhash(width_, multiple_.hash());\n\t}\n};\n\nstruct DriveChunk\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tint none_;\n\t\tConst constant_;\n\t\tDriveChunkWire wire_;\n\t\tDriveChunkPort port_;\n\t\tDriveChunkMarker marker_;\n\t\tDriveChunkMultiple multiple_;\n\t};\n\npublic:\n\tDriveChunk() { set_none(); }\n\n\tDriveChunk(DriveChunk const &other) { *this = other; }\n\tDriveChunk(DriveChunk &&other) { *this = other; }\n\n\tDriveChunk(DriveBit const &other) { *this = other; }\n\n\tDriveChunk(Const const &constant) { *this = constant; }\n\tDriveChunk(Const &&constant) { *this = constant; }\n\tDriveChunk(DriveChunkWire const &wire) { *this = wire; }\n\tDriveChunk(DriveChunkWire &&wire) { *this = wire; }\n\tDriveChunk(DriveChunkPort const &port) { *this = port; }\n\tDriveChunk(DriveChunkPort &&port) { *this = port; }\n\tDriveChunk(DriveChunkMarker const &marker) { *this = marker; }\n\tDriveChunk(DriveChunkMarker &&marker) { *this = marker; }\n\tDriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; }\n\tDriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; }\n\n\t~DriveChunk() { set_none(); }\n\n\tDriveBit operator[](int i) const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn DriveBit();\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_[i];\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_[i];\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_[i];\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_[i];\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_[i];\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tvoid set_none(int width = 0)\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tnone_ = width;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tconstant_.~Const();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveChunkWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveChunkPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveChunkMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveChunkMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t\tnone_ = width;\n\t}\n\n\tDriveChunk &operator=(DriveChunk const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunk &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const const &constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(constant);\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const &&constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(std::move(constant));\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple const &multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple &&multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type())\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(1);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = Const(other.constant());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = DriveChunkWire(other.wire());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = DriveChunkPort(other.port());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = DriveChunkMarker(other.marker());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = DriveChunkMultiple(other.multiple());\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tbool can_append(DriveBit const &bit) const;\n\tbool try_append(DriveBit const &bit);\n\tbool try_append(DriveChunk const &chunk);\n\n\tunsigned int hash() const\n\t{\n\t\tunsigned int inner = 0;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tinner = 0;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tinner = constant_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\tinner = wire_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tinner = port_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tinner = marker_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tinner = multiple_.hash();\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tlog_abort();\n\t\t\t\tbreak;\n\t\t}\n\t\treturn mkhash((unsigned int)type_, inner);\n\t}\n\n\tbool operator==(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveChunk &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ < other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tConst &constant() { log_assert(is_constant()); return constant_; }\n\tConst const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveChunkWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveChunkPort &port() { log_assert(is_port()); return port_; }\n\tDriveChunkPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveChunkMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\n\tint size() const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn none_;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_.size();\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_.size();\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_.size();\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_.size();\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_.size();\n\t\t}\n\t\tlog_abort();\n\t}\n};\n\ninline DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit)\n\t: width_(1)\n{\n\tfor (auto const &bit : bit.multiple())\n\t\tmultiple_.emplace(bit);\n}\n\nstruct DriveSpec\n{\nprivate:\n\tint width_ = 0;\n\tmutable std::vector<DriveChunk> chunks_;\n\tmutable std::vector<DriveBit> bits_;\n\tmutable unsigned int hash_ = 0;\npublic:\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tDriveSpec() {}\n\n\tDriveSpec(DriveChunk const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkWire const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkPort const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMarker const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; }\n\n\tDriveSpec(DriveBit const &bit) { *this = bit; }\n\tDriveSpec(DriveBitWire const &bit) { *this = bit; }\n\tDriveSpec(DriveBitPort const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMarker const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMultiple const &bit) { *this = bit; }\n\n\tDriveSpec(std::vector<DriveChunk> const &chunks) : chunks_(chunks) { compute_width(); }\n\n\tDriveSpec(std::vector<DriveBit> const &bits)\n\t{\n\t\tfor (auto const &bit : bits)\n\t\t\tappend(bit);\n\t}\n\n\tDriveSpec(SigSpec const &sig)\n\t{\n\t\t// TODO: converting one chunk at a time would be faster\n\t\tfor (auto const &bit : sig.bits())\n\t\t\tappend(bit);\n\t}\n\n\tstd::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }\n\tstd::vector<DriveBit> const &bits() const { unpack(); return bits_; }\n\n\tint size() const { return width_; }\n\n\tvoid append(DriveBit const &bit);\n\n\tvoid append(DriveChunk const &chunk);\n\n\tvoid pack() const;\n\n\tvoid unpack() const;\n\n\tDriveBit &operator[](int index)\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tconst DriveBit &operator[](int index) const\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tvoid clear()\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\twidth_ = 0;\n\t}\n\n\tDriveSpec &operator=(DriveChunk const &chunk)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(chunk);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); }\n\n\tDriveSpec &operator=(DriveBit const &bit)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(bit);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); }\n\n\tunsigned int hash() const {\n\t\tif (hash_ != 0) return hash_;\n\n\t\tpack();\n\t\thash_ = hash_ops<std::vector<DriveChunk>>().hash(chunks_);\n\t\thash_ |= (hash_ == 0);\n\t\treturn hash_;\n\t}\n\n\tbool operator==(DriveSpec const &other) const {\n\t\tif (size() != other.size() || hash() != other.hash())\n\t\t\treturn false;\n\t\treturn chunks() == other.chunks();\n\t}\n\nprivate:\n\tvoid compute_width();\n};\n\n\n\nstruct DriverMap\n{\n\tCellTypes celltypes;\n\n\tDriverMap() { celltypes.setup(); }\n\tDriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); }\n\nprivate:\n\n\t// Internally we represent all DriveBits by mapping them to DriveBitIds\n\t// which use less memory and are cheaper to compare.\n\tstruct DriveBitId\n\t{\n\t\tint id = -1;\n\n\t\tDriveBitId() {};\n\n\t\tDriveBitId(int id) : id(id) { }\n\n\t\tbool operator==(const DriveBitId &other) const { return id == other.id; }\n\t\tbool operator!=(const DriveBitId &other) const { return id != other.id; }\n\t\tbool operator<(const DriveBitId &other) const { return id < other.id; }\n\t\tunsigned int hash() const { return id; }\n\t};\n\t// Essentially a dict<DriveBitId, pool<DriveBitId>> but using less memory\n\t// and fewer allocations\n\tstruct DriveBitGraph {\n\t\tdict<DriveBitId, DriveBitId> first_edges;\n\t\tdict<DriveBitId, DriveBitId> second_edges;\n\t\tdict<DriveBitId, pool<DriveBitId>> more_edges;\n\n\t\tvoid add_edge(DriveBitId src, DriveBitId dst);\n\t\tDriveBitId pop_edge(DriveBitId src);\n\t\tvoid clear(DriveBitId src);\n\t\tbool contains(DriveBitId src);\n\t\tint count(DriveBitId src);\n\n\t\tDriveBitId at(DriveBitId src, int index);\n\t};\n\n\t// The following two maps maintain a sparse DriveBit to DriveBitId mapping.\n\t// This saves a lot of memory compared to a `dict<DriveBit, DriveBitId>` or\n\t// `idict<DriveBit>`.\n\n\t// Maps wires to the first DriveBitId of the consecutive range used for\n\t// that wire.\n\tdict<Wire *, DriveBitId> wire_offsets;\n\n\t// Maps cell ports to a the first DriveBitId of the consecutive range used\n\t// for that cell port.\n\tdict<pair<Cell *, IdString>, DriveBitId> port_offsets;\n\n\t// For the inverse map that maps DriveBitIds back to DriveBits we use a\n\t// sorted map containing only the first DriveBit for each wire and cell\n\t// port.\n\tstd::map<DriveBitId, DriveBit> drive_bits;\n\n\t// As a memory optimization for gate level net lists we store single-bit\n\t// wires and cell ports in a `dict` which requires less memory and fewer\n\t// allocations than `std::map` but doesn't support the kind of lookups we\n\t// need for a sparse coarse grained mapping.\n\tdict<DriveBitId, DriveBit> isolated_drive_bits;\n\n\t// Used for allocating DriveBitIds, none and constant states use a fixewd\n\t// mapping to the first few ids, which we need to skip.\n\tint next_offset = 1 + (int)State::Sm;\n\n\t// Union-Find over directly connected bits that share the same single\n\t// driver or are undriven. We never merge connections between drivers\n\t// and/or kept wires.\n\tmfp<DriveBitId> same_driver;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally unambiguous (one side only drives or requires a driven value).\n\tDriveBitGraph connected_drivers;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally ambiguous. Every such ambiguous connection is also present in\n\t// the reverse direction and has to be resolved when querying drivers.\n\tDriveBitGraph connected_undirected;\n\n\t// Subset of `connected_undirected` for caching the resolved driving\n\t// direction. In case multiple drivers are present this can still contain\n\t// both orientations of a single connection, but for a single driver only\n\t// one will be present.\n\tDriveBitGraph connected_oriented;\n\n\t// Stores for which bits we already resolved the orientation (cached in\n\t// `connected_oriented`).\n\tpool<DriveBitId> oriented_present;\n\n\n\tenum class BitMode {\n\t\tNONE = 0, // Not driven, no need to keep wire\n\t\tDRIVEN = 1, // Not driven, uses a value driven elsewhere\n\t\tDRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection\n\t\tKEEP = 3, // Wire that should be kept\n\t\tTRISTATE = 4, // Can drive a value but can also use a value driven elsewhere\n\t\tDRIVER = 5, // Drives a value\n\t};\n\n\tBitMode bit_mode(DriveBit const &bit);\n\tDriveBitId id_from_drive_bit(DriveBit const &bit);\n\tDriveBit drive_bit_from_id(DriveBitId id);\n\n\tvoid connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_undirected(DriveBitId a_id, DriveBitId b_id);\n\npublic:\n\n\tvoid add(Module *module);\n\n\t// Add a single bit connection to the driver map.\n\tvoid add(DriveBit const &a, DriveBit const &b);\n\n\ttemplate<typename T>\n\tstatic constexpr bool is_sig_type() {\n\t\treturn\n\t\t\tstd::is_same<T, SigSpec>::value ||\n\t\t\tstd::is_same<T, SigChunk>::value ||\n\t\t\tstd::is_same<T, DriveSpec>::value ||\n\t\t\tstd::is_same<T, DriveChunk>::value ||\n\t\t\tstd::is_same<T, DriveChunkPort>::value ||\n\t\t\tstd::is_same<T, DriveChunkWire>::value ||\n\t\t\tstd::is_same<T, Const>::value;\n\t}\n\n\t// We use the enable_if to produce better compiler errors when unsupported\n\t// types are used\n\ttemplate<typename T, typename U>\n\ttypename std::enable_if<is_sig_type<T>() && is_sig_type<U>()>::type\n\tadd(T const &a, U const &b)\n\t{\n\t\tlog_assert(a.size() == b.size());\n\t\tfor (int i = 0; i != GetSize(a); ++i)\n\t\t\tadd(DriveBit(a[i]), DriveBit(b[i]));\n\t}\n\n\n\t// Specialized version that avoids unpacking\n\tvoid add(SigSpec const &a, SigSpec const &b);\n\nprivate:\n\tvoid add_port(Cell *cell, IdString const &port, SigSpec const &b);\n\n\t// Only used a local variables in `orient_undirected`, always cleared, only\n\t// stored to reduce allocations.\n\tpool<DriveBitId> orient_undirected_seen;\n\tpool<DriveBitId> orient_undirected_drivers;\n\tdict<DriveBitId, int> orient_undirected_distance;\n\n\tvoid orient_undirected(DriveBitId id);\n\npublic:\n\tDriveBit operator()(DriveBit const &bit);\n\n\tDriveSpec operator()(DriveSpec spec);\n\nprivate:\n\tbool keep_wire(Wire *wire) {\n\t\t// TODO configurable\n\t\treturn wire->has_attribute(ID(keep));\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "ff.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FF_H\n#define FF_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Describes a flip-flop or a latch.\n//\n// If has_gclk, this is a formal verification FF with implicit global clock:\n// Q is simply previous cycle's D. Additionally if is_anyinit is true, this is\n// an $anyinit cell which always has an undefined initialization value. Note\n// that $anyinit is not considered to be among the FF celltypes, so a pass has\n// to explicitly opt-in to process $anyinit cells with FfData.\n//\n// Otherwise, the FF/latch can have any number of features selected by has_*\n// attributes that determine Q's value (in order of decreasing priority):\n//\n// - on start, register is initialized to val_init\n// - if has_sr is present:\n// - sig_clr is per-bit async clear, and sets the corresponding bit to 0\n// if active\n// - sig_set is per-bit async set, and sets the corresponding bit to 1\n// if active\n// - if has_arst is present:\n// - sig_arst is whole-reg async reset, and sets the whole register to val_arst\n// - if has_aload is present:\n// - sig_aload is whole-reg async load (aka latch gate enable), and sets the whole\n// register to sig_ad\n// - if has_clk is present, and we're currently on a clock edge:\n// - if has_ce is present and ce_over_srst is true:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - if has_srst is present:\n// - sig_srst is whole-reg sync reset and sets the register to val_srst\n// - if has_ce is present and ce_over_srst is false:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - set whole reg to sig_d\n// - if nothing of the above applies, the reg value remains unchanged\n//\n// Since the yosys FF cell library isn't fully generic, not all combinations\n// of the features above can be supported:\n//\n// - only one of has_srst, has_arst, has_sr can be used\n// - if has_clk is used together with has_aload, then has_srst, has_arst,\n// has_sr cannot be used\n//\n// The valid feature combinations are thus:\n//\n// - has_clk + optional has_ce [dff/dffe]\n// - has_clk + optional has_ce + has_arst [adff/adffe]\n// - has_clk + optional has_ce + has_aload [aldff/aldffe]\n// - has_clk + optional has_ce + has_sr [dffsr/dffsre]\n// - has_clk + optional has_ce + has_srst [sdff/sdffe/sdffce]\n// - has_aload [dlatch]\n// - has_aload + has_arst [adlatch]\n// - has_aload + has_sr [dlatchsr]\n// - has_sr [sr]\n// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]\n// - empty set [not a cell — will be emitted as a simple direct connection]\n\nstruct FfData {\n\tModule *module;\n\tFfInitVals *initvals;\n\tCell *cell;\n\tIdString name;\n\t// The FF output.\n\tSigSpec sig_q;\n\t// The sync data input, present if has_clk or has_gclk.\n\tSigSpec sig_d;\n\t// The async data input, present if has_aload.\n\tSigSpec sig_ad;\n\t// The sync clock, present if has_clk.\n\tSigSpec sig_clk;\n\t// The clock enable, present if has_ce.\n\tSigSpec sig_ce;\n\t// The async load enable, present if has_aload.\n\tSigSpec sig_aload;\n\t// The async reset, preset if has_arst.\n\tSigSpec sig_arst;\n\t// The sync reset, preset if has_srst.\n\tSigSpec sig_srst;\n\t// The async clear (per-lane), present if has_sr.\n\tSigSpec sig_clr;\n\t// The async set (per-lane), present if has_sr.\n\tSigSpec sig_set;\n\t// True if this is a clocked (edge-sensitive) flip-flop.\n\tbool has_clk;\n\t// True if this is a $ff, exclusive with every other has_*.\n\tbool has_gclk;\n\t// True if this FF has a clock enable. Depends on has_clk.\n\tbool has_ce;\n\t// True if this FF has async load function — this includes D latches.\n\t// If this and has_clk are both set, has_arst and has_sr cannot be set.\n\tbool has_aload;\n\t// True if this FF has sync set/reset. Depends on has_clk, exclusive\n\t// with has_arst, has_sr, has_aload.\n\tbool has_srst;\n\t// True if this FF has async set/reset. Exclusive with has_srst,\n\t// has_sr. If this and has_clk are both set, has_aload cannot be set.\n\tbool has_arst;\n\t// True if this FF has per-bit async set + clear. Exclusive with\n\t// has_srst, has_arst. If this and has_clk are both set, has_aload\n\t// cannot be set.\n\tbool has_sr;\n\t// If has_ce and has_srst are both set, determines their relative\n\t// priorities: if true, inactive ce disables srst; if false, srst\n\t// operates independent of ce.\n\tbool ce_over_srst;\n\t// True if this FF is a fine cell, false if it is a coarse cell.\n\t// If true, width must be 1.\n\tbool is_fine;\n\t// True if this FF is an $anyinit cell. Depends on has_gclk.\n\tbool is_anyinit;\n\t// Polarities, corresponding to sig_*.\n\t// True means rising edge, false means falling edge.\n\tbool pol_clk;\n\t// True means active-high, false\n\t// means active-low.\n\tbool pol_ce;\n\tbool pol_aload;\n\tbool pol_arst;\n\tbool pol_srst;\n\tbool pol_clr;\n\tbool pol_set;\n\t// The value loaded by sig_arst.\n\tConst val_arst;\n\t// The value loaded by sig_srst.\n\tConst val_srst;\n\t// The initial value at power-up.\n\tConst val_init;\n\t// The FF data width in bits.\n\tint width;\n\tdict<IdString, Const> attributes;\n\n\tFfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {\n\t\twidth = 0;\n\t\thas_clk = false;\n\t\thas_gclk = false;\n\t\thas_ce = false;\n\t\thas_aload = false;\n\t\thas_srst = false;\n\t\thas_arst = false;\n\t\thas_sr = false;\n\t\tce_over_srst = false;\n\t\tis_fine = false;\n\t\tis_anyinit = false;\n\t\tpol_clk = false;\n\t\tpol_aload = false;\n\t\tpol_ce = false;\n\t\tpol_arst = false;\n\t\tpol_srst = false;\n\t\tpol_clr = false;\n\t\tpol_set = false;\n\t}\n\n\tFfData(FfInitVals *initvals, Cell *cell_);\n\n\t// Returns a FF identical to this one, but only keeping bit indices from the argument.\n\tFfData slice(const std::vector<int> &bits);\n\n\tvoid add_dummy_ce();\n\tvoid add_dummy_srst();\n\tvoid add_dummy_arst();\n\tvoid add_dummy_aload();\n\tvoid add_dummy_sr();\n\tvoid add_dummy_clk();\n\n\tvoid arst_to_aload();\n\tvoid arst_to_sr();\n\n\tvoid aload_to_sr();\n\n\t// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and\n\t// fixes up control signals appropriately to preserve semantics.\n\tvoid convert_ce_over_srst(bool val);\n\n\tvoid unmap_ce();\n\tvoid unmap_srst();\n\n\tvoid unmap_ce_srst() {\n\t\tunmap_ce();\n\t\tunmap_srst();\n\t}\n\n\tCell *emit();\n\n\t// Removes init attribute from the Q output, but keeps val_init unchanged.\n\t// It will be automatically reattached on emit. Use this before changing sig_q.\n\tvoid remove_init() {\n\t\tif (initvals)\n\t\t\tinitvals->remove_init(sig_q);\n\t}\n\n\tvoid remove();\n\n\t// Flip the sense of the given bit slices of the FF: insert inverters on data\n\t// inputs and output, flip the corresponding init/reset bits, swap clr/set\n\t// inputs with proper priority fix.\n\tvoid flip_bits(const pool<int> &bits);\n\n\tvoid flip_rst_bits(const pool<int> &bits);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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- "ffinit.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFINIT_H\n#define FFINIT_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FfInitVals\n{\n\tconst SigMap *sigmap;\n\tdict<SigBit, std::pair<State,SigBit>> initbits;\n\n\tvoid set(const SigMap *sigmap_, RTLIL::Module *module)\n\t{\n\t\tsigmap = sigmap_;\n\t\tinitbits.clear();\n\t\tfor (auto wire : module->wires())\n\t\t{\n\t\t\tif (wire->attributes.count(ID::init) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tSigSpec wirebits = (*sigmap)(wire);\n\t\t\tConst initval = wire->attributes.at(ID::init);\n\n\t\t\tfor (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)\n\t\t\t{\n\t\t\t\tSigBit bit = wirebits[i];\n\t\t\t\tState val = initval[i];\n\n\t\t\t\tif (val != State::S0 && val != State::S1 && bit.wire != nullptr)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (initbits.count(bit)) {\n\t\t\t\t\tif (initbits.at(bit).first != val)\n\t\t\t\t\t\tlog_error(\"Conflicting init values for signal %s (%s = %s != %s).\\n\",\n\t\t\t\t\t\t\t\tlog_signal(bit), log_signal(SigBit(wire, i)),\n\t\t\t\t\t\t\t\tlog_signal(val), log_signal(initbits.at(bit).first));\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tinitbits[bit] = std::make_pair(val,SigBit(wire,i));\n\t\t\t}\n\t\t}\n\t}\n\n\tRTLIL::State operator()(RTLIL::SigBit bit) const\n\t{\n\t\tauto it = initbits.find((*sigmap)(bit));\n\t\tif (it != initbits.end())\n\t\t\treturn it->second.first;\n\t\telse\n\t\t\treturn State::Sx;\n\t}\n\n\tRTLIL::Const operator()(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::Const res;\n\t\tfor (auto bit : sig)\n\t\t\tres.bits.push_back((*this)(bit));\n\t\treturn res;\n\t}\n\n\tvoid set_init(RTLIL::SigBit bit, RTLIL::State val)\n\t{\n\t\tSigBit mbit = (*sigmap)(bit);\n\t\tSigBit abit = bit;\n\t\tauto it = initbits.find(mbit);\n\t\tif (it != initbits.end())\n\t\t\tabit = it->second.second;\n\t\telse if (val == State::Sx)\n\t\t\treturn;\n\t\tlog_assert(abit.wire);\n\t\tinitbits[mbit] = std::make_pair(val,abit);\n\t\tauto it2 = abit.wire->attributes.find(ID::init);\n\t\tif (it2 != abit.wire->attributes.end()) {\n\t\t\tit2->second[abit.offset] = val;\n\t\t\tif (it2->second.is_fully_undef())\n\t\t\t\tabit.wire->attributes.erase(it2);\n\t\t} else if (val != State::Sx) {\n\t\t\tConst cval(State::Sx, GetSize(abit.wire));\n\t\t\tcval[abit.offset] = val;\n\t\t\tabit.wire->attributes[ID::init] = cval;\n\t\t}\n\t}\n\n\tvoid set_init(const RTLIL::SigSpec &sig, RTLIL::Const val)\n\t{\n\t\tlog_assert(GetSize(sig) == GetSize(val));\n\t\tfor (int i = 0; i < GetSize(sig); i++)\n\t\t\tset_init(sig[i], val[i]);\n\t}\n\n\tvoid remove_init(RTLIL::SigBit bit)\n\t{\n\t\tset_init(bit, State::Sx);\n\t}\n\n\tvoid remove_init(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto bit : sig)\n\t\t\tremove_init(bit);\n\t}\n\n\tvoid clear()\n\t{\n\t\tinitbits.clear();\n\t}\n\n\tFfInitVals (const SigMap *sigmap, RTLIL::Module *module)\n\t{\n\t\tset(sigmap, module);\n\t}\n\n\tFfInitVals () {}\n};\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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+ "ffinit.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFINIT_H\n#define FFINIT_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FfInitVals\n{\n\tconst SigMap *sigmap;\n\tdict<SigBit, std::pair<State,SigBit>> initbits;\n\n\tvoid set(const SigMap *sigmap_, RTLIL::Module *module)\n\t{\n\t\tsigmap = sigmap_;\n\t\tinitbits.clear();\n\t\tfor (auto wire : module->wires())\n\t\t{\n\t\t\tif (wire->attributes.count(ID::init) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tSigSpec wirebits = (*sigmap)(wire);\n\t\t\tConst initval = wire->attributes.at(ID::init);\n\n\t\t\tfor (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)\n\t\t\t{\n\t\t\t\tSigBit bit = wirebits[i];\n\t\t\t\tState val = initval[i];\n\n\t\t\t\tif (val != State::S0 && val != State::S1 && bit.wire != nullptr)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (initbits.count(bit)) {\n\t\t\t\t\tif (initbits.at(bit).first != val)\n\t\t\t\t\t\tlog_error(\"Conflicting init values for signal %s (%s = %s != %s).\\n\",\n\t\t\t\t\t\t\t\tlog_signal(bit), log_signal(SigBit(wire, i)),\n\t\t\t\t\t\t\t\tlog_signal(val), log_signal(initbits.at(bit).first));\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tinitbits[bit] = std::make_pair(val,SigBit(wire,i));\n\t\t\t}\n\t\t}\n\t}\n\n\tRTLIL::State operator()(RTLIL::SigBit bit) const\n\t{\n\t\tauto it = initbits.find((*sigmap)(bit));\n\t\tif (it != initbits.end())\n\t\t\treturn it->second.first;\n\t\telse\n\t\t\treturn State::Sx;\n\t}\n\n\tRTLIL::Const operator()(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::Const res;\n\t\tfor (auto bit : sig)\n\t\t\tres.bits().push_back((*this)(bit));\n\t\treturn res;\n\t}\n\n\tvoid set_init(RTLIL::SigBit bit, RTLIL::State val)\n\t{\n\t\tSigBit mbit = (*sigmap)(bit);\n\t\tSigBit abit = bit;\n\t\tauto it = initbits.find(mbit);\n\t\tif (it != initbits.end())\n\t\t\tabit = it->second.second;\n\t\telse if (val == State::Sx)\n\t\t\treturn;\n\t\tlog_assert(abit.wire);\n\t\tinitbits[mbit] = std::make_pair(val,abit);\n\t\tauto it2 = abit.wire->attributes.find(ID::init);\n\t\tif (it2 != abit.wire->attributes.end()) {\n\t\t\tit2->second.bits()[abit.offset] = val;\n\t\t\tif (it2->second.is_fully_undef())\n\t\t\t\tabit.wire->attributes.erase(it2);\n\t\t} else if (val != State::Sx) {\n\t\t\tConst cval(State::Sx, GetSize(abit.wire));\n\t\t\tcval.bits()[abit.offset] = val;\n\t\t\tabit.wire->attributes[ID::init] = cval;\n\t\t}\n\t}\n\n\tvoid set_init(const RTLIL::SigSpec &sig, RTLIL::Const val)\n\t{\n\t\tlog_assert(GetSize(sig) == GetSize(val));\n\t\tfor (int i = 0; i < GetSize(sig); i++)\n\t\t\tset_init(sig[i], val[i]);\n\t}\n\n\tvoid remove_init(RTLIL::SigBit bit)\n\t{\n\t\tset_init(bit, State::Sx);\n\t}\n\n\tvoid remove_init(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto bit : sig)\n\t\t\tremove_init(bit);\n\t}\n\n\tvoid clear()\n\t{\n\t\tinitbits.clear();\n\t}\n\n\tFfInitVals (const SigMap *sigmap, RTLIL::Module *module)\n\t{\n\t\tset(sigmap, module);\n\t}\n\n\tFfInitVals () {}\n};\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "ffmerge.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFMERGE_H\n#define FFMERGE_H\n\n#include \"kernel/ffinit.h\"\n#include \"kernel/ff.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// A helper class for passes that want to merge FFs on the input or output\n// of a cell into the cell itself.\n//\n// The procedure is:\n//\n// 1. Construct this class (at beginning of processing for a given module).\n// 2. For every considered cell:\n//\n// a. Call find_output_ff for every considered output.\n// b. Call find_input_ff for every considered input.\n// c. Look at the FF description returned (if any) from each call, reject\n// results that cannot be merged into given cell for any reason.\n// If both inputs and outputs are being merged, take care of FF bits that\n// are returned in both input and output results (a FF bit cannot be\n// merged to both). Decide on the final set of FF bits to merge.\n// d. Call remove_output_ff for every find_output_ff result that will be used\n// for merging. This removes the actual FF bits from design and from index.\n// e. Call mark_input_ff for every find_input_ff result that will be used\n// for merging. This updates the index disallowing further usage of these\n// FF bits for output FF merging, if they were eligible before. The actual\n// FF bits are still left in the design and can be merged into other inputs.\n// If the FF bits are not otherwise used, they will be removed by later\n// opt passes.\n// f. Merge the FFs into the cell.\n//\n// Note that, if both inputs and outputs are being considered for merging in\n// a single pass, the result may be nondeterministic (depending on cell iteration\n// order) because a given FF bit could be eligible for both input and output merge,\n// perhaps in different cells. For this reason, it may be a good idea to separate\n// input and output merging.\n\nstruct FfMergeHelper\n{\n\tconst SigMap *sigmap;\n\tRTLIL::Module *module;\n\tFfInitVals *initvals;\n\n\tdict<SigBit, std::pair<Cell*, int>> dff_driver;\n\tdict<SigBit, pool<std::pair<Cell*, int>>> dff_sink;\n\tdict<SigBit, int> sigbit_users_count;\n\n\t// Returns true if all bits in sig are completely unused.\n\tbool is_output_unused(RTLIL::SigSpec sig);\n\n\t// Finds the FF to merge into a given cell output. Takes sig, which\n\t// is the current cell output — it will be the sig_d of the found FF.\n\t// If found, returns true, and fills the two output arguments.\n\t//\n\t// For every bit of sig, this function finds a FF bit that has\n\t// the same sig_d, and fills the output FfData according to the FF\n\t// bits found. This function will only consider FF bits that are\n\t// the only user of the given sig bits — if any bit in sig is used\n\t// by anything other than a single FF, this function will return false.\n\t//\n\t// The returned FfData structure does not correspond to any actual FF\n\t// cell in the design — it is the amalgamation of extracted FF bits,\n\t// possibly coming from several FF cells.\n\t//\n\t// If some of the bits in sig have no users at all, this function\n\t// will accept them as well (and fill returned FfData with dummy values\n\t// for the given bit, effectively synthesizing an unused FF bit of the\n\t// appropriate type). However, if all bits in sig are completely\n\t// unused, this function will fail and return false (having no idea\n\t// what kind of FF to produce) — use the above helper if that case\n\t// is important to handle.\n\t//\n\t// Note that this function does not remove the FF bits returned from\n\t// the design — this is so that the caller can decide whether to accept\n\t// this FF for merging or not. If the result is accepted,\n\t// remove_output_ff should be called on the second output argument.\n\tbool find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// Like above, but returns a FF to merge into a given cell input. Takes\n\t// sig_q, which is the current cell input — it will search for FFs with\n\t// matching sig_q.\n\t//\n\t// As opposed to find_output_ff, this function doesn't care about usage\n\t// counts, and may return FF bits that also have other fanout. This\n\t// should not be a problem for input FF merging.\n\t//\n\t// As a special case, if some of the bits in sig_q are constant, this\n\t// function will accept them as well, by synthesizing in-place\n\t// a constant-input FF bit (with matching initial value and reset value).\n\t// However, this will not work if the input is all-constant — if the caller\n\t// cares about this case, it needs to check for it explicitely.\n\tbool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_output_ff result that will be merged. This\n\t// marks the given FF bits as used up (and not to be considered for\n\t// further merging as inputs), and reconnects their Q ports to a dummy\n\t// wire (since the wire previously connected there will now be driven\n\t// by the merged-to cell instead).\n\tvoid remove_output_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_input_ff result that will be merged. This\n\t// marks the given FF bits as used, and disallows merging them as\n\t// outputs. They can, however, still be merged as inputs again\n\t// (perhaps for another cell).\n\tvoid mark_input_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\tvoid set(FfInitVals *initvals_, RTLIL::Module *module_);\n\n\tvoid clear();\n\n\tFfMergeHelper(FfInitVals *initvals, RTLIL::Module *module) {\n\t\tset(initvals, module);\n\t}\n\n\tFfMergeHelper() {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "fmt.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n// $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tTIME = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n// \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tLITERAL \t= 0,\n\t\tINTEGER \t= 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign = MINUS;\n\tbool hex_upper = false;\n\tbool show_base = false;\n\tbool group = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_literal(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <variant>\n#include <vector>\n\n#include <stdint.h>\n\nnamespace hashlib {\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\n// The XOR version of DJB2\ninline unsigned int mkhash(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) ^ b;\n}\n\n// traditionally 5381 is used as starting value for the djb2 hash\nconst unsigned int mkhash_init = 5381;\n\n// The ADD version of DJB2\n// (use this version for cache locality in b)\ninline unsigned int mkhash_add(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) + b;\n}\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\ntemplate<typename T> struct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const T &a) {\n\t\treturn a.hash();\n\t}\n};\n\nstruct hash_int_ops {\n\ttemplate<typename T>\n\tstatic inline bool cmp(T a, T b) {\n\t\treturn a == b;\n\t}\n};\n\ntemplate<> struct hash_ops<bool> : hash_int_ops\n{\n\tstatic inline unsigned int hash(bool a) {\n\t\treturn a ? 1 : 0;\n\t}\n};\ntemplate<> struct hash_ops<int32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<int64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\ntemplate<> struct hash_ops<uint32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<uint64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\n\ntemplate<> struct hash_ops<std::string> {\n\tstatic inline bool cmp(const std::string &a, const std::string &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const std::string &a) {\n\t\tunsigned int v = 0;\n\t\tfor (auto c : a)\n\t\t\tv = mkhash(v, c);\n\t\treturn v;\n\t}\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::pair<P, Q> a) {\n\t\treturn mkhash(hash_ops<P>::hash(a.first), hash_ops<Q>::hash(a.second));\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), unsigned int>::type hash(std::tuple<T...>) {\n\t\treturn mkhash_init;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), unsigned int>::type hash(std::tuple<T...> a) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\treturn mkhash(hash<I+1>(a), element_ops_t::hash(std::get<I>(a)));\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::vector<T> a) {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto k : a)\n\t\t\th = mkhash(h, hash_ops<T>::hash(k));\n\t\treturn h;\n\t}\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\tfor (int i = 0; a[i] || b[i]; i++)\n\t\t\tif (a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\tstatic inline unsigned int hash(const char *a) {\n\t\tunsigned int hash = mkhash_init;\n\t\twhile (*a)\n\t\t\thash = mkhash(hash, *(a++));\n\t\treturn hash;\n\t}\n};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const void *a) {\n\t\treturn (uintptr_t)a;\n\t}\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\tstatic inline unsigned int hash(const T *a) {\n\t\treturn a ? a->hash() : 0;\n\t}\n};\n\ntemplate<typename T>\ninline unsigned int mkhash(const T &v) {\n\treturn hash_ops<T>().hash(v);\n}\n\ntemplate<> struct hash_ops<std::monostate> {\n\tstatic inline bool cmp(std::monostate a, std::monostate b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::monostate) {\n\t\treturn mkhash_init;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::variant<T...>> {\n\tstatic inline bool cmp(std::variant<T...> a, std::variant<T...> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::variant<T...> a) {\n\t\tunsigned int h = std::visit([](const auto &v) { return mkhash(v); }, a);\n\t\treturn mkhash(a.index(), h);\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::optional<T>> {\n\tstatic inline bool cmp(std::optional<T> a, std::optional<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::optional<T> a) {\n\t\tif(a.has_value())\n\t\t\treturn mkhash(*a);\n\t\telse\n\t\t\treturn 0;\n\t}\n};\n\ninline int hashtable_size(int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict\n{\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tint hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto &entry : entries) {\n\t\t\th ^= hash_ops<K>::hash(entry.udata.first);\n\t\t\th ^= hash_ops<T>::hash(entry.udata.second);\n\t\t}\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tint hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int hashval = mkhash_init;\n\t\tfor (auto &it : entries)\n\t\t\thashval ^= ops.hash(it.udata);\n\t\treturn hashval;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0, OPS>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
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  "json.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n enum Scope {\n VALUE,\n OBJECT_FIRST,\n OBJECT,\n ARRAY_FIRST,\n ARRAY,\n };\n\n struct Target {\n virtual void emit(const char *data) = 0;\n virtual void flush() {};\n virtual ~Target() {};\n };\n\n std::string newline_indent = \"\\n\";\n std::vector<std::unique_ptr<Target>> targets;\n std::vector<Scope> state = {VALUE};\n int compact_depth = INT_MAX;\npublic:\n\n void emit_to_log();\n void append_to_string(std::string &target);\n bool write_to_file(const std::string &path);\n\n bool active() { return !targets.empty(); }\n\n void compact() { compact_depth = GetSize(state); }\n\n void line(bool space_if_inline = true);\n void raw(const char *raw_json);\n void flush();\n void begin_object();\n void begin_array();\n void end_object();\n void end_array();\n void name(const char *name);\n void begin_value();\n void end_value();\n void value_json(const Json &value);\n void value(unsigned int value) { value_json(Json((int)value)); }\n template<typename T>\n void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n void entry_json(const char *name, const Json &value);\n void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n template<typename T>\n void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n template<typename T>\n void object(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n entry(item.first, item.second);\n end_object();\n }\n\n template<typename T>\n void array(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n value(item);\n end_object();\n }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\nconst char *log_str(const char *str);\nconst char *log_str(std::string const &str);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T, typename OPS> static inline void log_dump_val_worker(dict<K, T, OPS> &v);\ntemplate<typename K, typename OPS> static inline void log_dump_val_worker(pool<K, OPS> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T, typename OPS>\nstatic inline void log_dump_val_worker(dict<K, T, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K, typename OPS>\nstatic inline void log_dump_val_worker(pool<K, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
174
- "macc.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct port_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\n\tstd::vector<port_t> ports;\n\tRTLIL::SigSpec bit_ports;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<port_t> new_ports;\n\t\tRTLIL::SigSpec new_bit_ports;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {\n\t\t\t\tbit_ports.append(port.in_a);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tfor (auto &bit : bit_ports)\n\t\t\tif (bit == State::S1)\n\t\t\t\toff = const_add(off, RTLIL::Const(1, width), false, false, width);\n\t\t\telse if (bit != State::S0)\n\t\t\t\tnew_bit_ports.append(bit);\n\n\t\tif (off.as_bool()) {\n\t\t\tport_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tnew_ports.swap(ports);\n\t\tbit_ports = new_bit_ports;\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tports.clear();\n\t\tbit_ports = cell->getPort(ID::B);\n\n\t\tstd::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tport_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tports.push_back(this_port);\n\t\t}\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell) const\n\t{\n\t\tRTLIL::SigSpec port_a;\n\t\tstd::vector<RTLIL::State> config_bits;\n\t\tint max_size = 0, num_bits = 0;\n\n\t\tfor (auto &port : ports) {\n\t\t\tmax_size = max(max_size, GetSize(port.in_a));\n\t\t\tmax_size = max(max_size, GetSize(port.in_b));\n\t\t}\n\n\t\twhile (max_size)\n\t\t\tnum_bits++, max_size /= 2;\n\n\t\tlog_assert(num_bits < 16);\n\t\tconfig_bits.push_back(num_bits & 1 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 2 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 4 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 8 ? State::S1 : State::S0);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tconfig_bits.push_back(port.is_signed ? State::S1 : State::S0);\n\t\t\tconfig_bits.push_back(port.do_subtract ? State::S1 : State::S0);\n\n\t\t\tint size_a = GetSize(port.in_a);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tint size_b = GetSize(port.in_b);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tport_a.append(port.in_a);\n\t\t\tport_a.append(port.in_b);\n\t\t}\n\n\t\tcell->setPort(ID::A, port_a);\n\t\tcell->setPort(ID::B, bit_ports);\n\t\tcell->setParam(ID::CONFIG, config_bits);\n\t\tcell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));\n\t\tcell->setParam(ID::A_WIDTH, GetSize(port_a));\n\t\tcell->setParam(ID::B_WIDTH, GetSize(bit_ports));\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits)\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\tfor (auto bit : bit_ports) {\n\t\t\tif (bit.wire)\n\t\t\t\treturn false;\n\t\t\tresult = const_add(result, bit.data, false, false, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
175
- "mem.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MEM_H\n#define MEM_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n#include \"kernel/utils.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct MemRd : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity, ce_over_srst;\n\tConst arst_value, srst_value, init_value;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will bypass the written data\n\t// to this port's output (default behavior is to read old value).\n\t// Can only be set for write ports that have the same clock domain.\n\tstd::vector<bool> transparency_mask;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will return an all-X (don't care)\n\t// value. Mutually exclusive with transparency_mask.\n\t// Can only be set for write ports that have the same clock domain.\n\t// For optimization purposes, this will also be set if we can\n\t// determine that the two ports can never be active simultanously\n\t// (making the above vacuously true).\n\tstd::vector<bool> collision_x_mask;\n\tSigSpec clk, en, arst, srst, addr, data;\n\n\tMemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n};\n\nstruct MemWr : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity;\n\tstd::vector<bool> priority_mask;\n\tSigSpec clk, en, addr, data;\n\n\tMemWr() : removed(false), cell(nullptr) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n\n\tstd::pair<SigSpec, std::vector<int>> compress_en();\n\tSigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig);\n};\n\nstruct MemInit : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tConst addr;\n\tConst data;\n\tConst en;\n\tMemInit() : removed(false), cell(nullptr) {}\n};\n\nstruct Mem : RTLIL::AttrObject {\n\tModule *module;\n\tIdString memid;\n\tbool packed;\n\tRTLIL::Memory *mem;\n\tCell *cell;\n\tint width, start_offset, size;\n\tstd::vector<MemInit> inits;\n\tstd::vector<MemRd> rd_ports;\n\tstd::vector<MemWr> wr_ports;\n\n\t// Removes this memory from the module. The data in helper structures\n\t// is unaffected except for the cell/mem fields.\n\tvoid remove();\n\n\t// Commits all changes in helper structures into the module — ports and\n\t// inits marked as removed are actually removed, new ports/inits create\n\t// new cells, modified port/inits are commited into their existing\n\t// cells. Note that this reindexes the ports and inits array (actually\n\t// removing the ports/inits marked as removed).\n\tvoid emit();\n\n\t// Marks all inits as removed.\n\tvoid clear_inits();\n\n\t// Coalesces inits: whenever two inits have overlapping or touching\n\t// address ranges, they are combined into one, with the higher-priority\n\t// one's data overwriting the other. Running this results in\n\t// an inits list equivalent to the original, in which all entries\n\t// cover disjoint (and non-touching) address ranges, and all enable\n\t// masks are all-1.\n\tvoid coalesce_inits();\n\n\t// Checks consistency of this memory and all its ports/inits, using\n\t// log_assert.\n\tvoid check();\n\n\t// Gathers all initialization data into a single big const covering\n\t// the whole memory. For all non-initialized bits, Sx will be returned.\n\tConst get_init_data() const;\n\n\t// Constructs and returns the helper structures for all memories\n\t// in a module.\n\tstatic std::vector<Mem> get_all_memories(Module *module);\n\n\t// Constructs and returns the helper structures for all selected\n\t// memories in a module.\n\tstatic std::vector<Mem> get_selected_memories(Module *module);\n\n\t// Converts a synchronous read port into an asynchronous one by\n\t// extracting the data (or, in some rare cases, address) register\n\t// into a separate cell, together with any soft-transparency\n\t// logic necessary to preserve its semantics. Returns the created\n\t// register cell, if any. Note that in some rare cases this function\n\t// may succeed and perform a conversion without creating a new\n\t// register — a nullptr result doesn't imply nothing was done.\n\tCell *extract_rdff(int idx, FfInitVals *initvals);\n\n\t// Splits all wide ports in this memory into equivalent narrow ones.\n\t// This function performs no modifications at all to the actual\n\t// netlist unless and until emit() is called.\n\tvoid narrow();\n\n\t// If write port idx2 currently has priority over write port idx1,\n\t// inserts extra logic on idx1's enable signal to disable writes\n\t// when idx2 is writing to the same address, then removes the priority\n\t// from the priority mask. If there is a memory port that is\n\t// transparent with idx1, but not with idx2, that port is converted\n\t// to use soft transparency logic.\n\tvoid emulate_priority(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Creates soft-transparency logic on read port ridx, bypassing the\n\t// data from write port widx. Should only be called when ridx is\n\t// transparent wrt widx in the first place. Once we're done, the\n\t// transparency_mask bit will be cleared, and the collision_x_mask\n\t// bit will be set instead (since whatever value is read will be\n\t// replaced by the soft transparency logic).\n\tvoid emulate_transparency(int widx, int ridx, FfInitVals *initvals);\n\n\t// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).\n\t// Specifically, takes care of priority masks: any priority relations\n\t// that idx2 had are replicated onto idx1, unless they conflict with\n\t// priorities already present on idx1, in which case emulate_priority\n\t// is called. Likewise, ensures transparency and undefined collision\n\t// masks of all read ports have the same values for both ports,\n\t// calling emulate_transparency if necessary.\n\tvoid prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares for merging read port idx2 into idx1.\n\t// Specifically, makes sure the transparency and undefined collision\n\t// masks of both ports are equal, by changing undefined behavior\n\t// of one port to the other's defined behavior, or by calling\n\t// emulate_transparency if necessary.\n\tvoid prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares the memory for widening a port to a given width. This\n\t// involves ensuring that start_offset and size are aligned to the\n\t// target width.\n\tvoid widen_prep(int wide_log2);\n\n\t// Widens a write port up to a given width. The newly port is\n\t// equivalent to the original, made by replicating enable/data bits\n\t// and masking enable bits with decoders on the low part of the\n\t// original address.\n\tvoid widen_wr_port(int idx, int wide_log2);\n\n\t// Emulates a sync read port's enable functionality in soft logic,\n\t// changing the actual read port's enable to be always-on.\n\tvoid emulate_rden(int idx, FfInitVals *initvals);\n\n\t// Emulates a sync read port's initial/reset value functionality in\n\t// soft logic, removing it from the actual read port.\n\tvoid emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals);\n\n\t// Given a read port with ce_over_srst set, converts it to a port\n\t// with ce_over_srst unset without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_ce_over_srst(int idx);\n\n\t// Given a read port with ce_over_srst unset, converts it to a port\n\t// with ce_over_srst set without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_srst_over_ce(int idx);\n\n\t// Returns true iff emulate_read_first makes sense to call.\n\tbool emulate_read_first_ok();\n\n\t// Emulates all read-first read-write port relationships in terms of\n\t// all-transparent ports, by delaying all write ports by one cycle.\n\t// This can only be used when all read ports and all write ports are\n\t// in the same clock domain.\n\tvoid emulate_read_first(FfInitVals *initvals);\n\n\tMem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}\n};\n\n// MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined\nclass MemContents {\npublic:\n\tclass range; class iterator;\n\tusing addr_t = uint32_t;\nprivate:\n\t// we ban _addr_width == sizeof(addr_t) * 8 because it adds too many cornercases\n\tint _addr_width;\n\tint _data_width;\n\tRTLIL::Const _default_value;\n\t// for each range, store the concatenation of the words at the start address\n\t// invariants:\n\t// - no overlapping or adjacent ranges\n\t// - no empty ranges\n\t// - all Consts are a multiple of the word size\n\tstd::map<addr_t, RTLIL::Const> _values;\n\t// returns an iterator to the range containing addr, if it exists, or the first range past addr\n\tstd::map<addr_t, RTLIL::Const>::iterator _range_at(addr_t addr) const;\n\taddr_t _range_size(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->second.size() / _data_width; }\n\taddr_t _range_begin(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->first; }\n\taddr_t _range_end(std::map<addr_t, RTLIL::Const>::iterator it) const { return _range_begin(it) + _range_size(it); }\n\t// check if the iterator points to a range containing addr\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const;\n\t// check if the iterator points to a range containing [begin_addr, end_addr). assumes end_addr >= begin_addr.\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// check if the iterator points to a range overlapping with [begin_addr, end_addr)\n\tbool _range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// return the offset the addr would have in the range at `it`\n\tsize_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }\n\t// assuming _range_contains(it, addr), return an iterator pointing to the data at addr\n\tstd::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits.begin() + _range_offset(it, addr); }\n\t// internal version of reserve_range that returns an iterator to the range\n\tstd::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);\n\t// write a single word at addr, return iterator to next word\n\tstd::vector<State>::iterator _range_write(std::vector<State>::iterator it, RTLIL::Const const &data);\npublic:\n\tclass range {\n\t\tint _data_width;\n\t\taddr_t _base;\n\t\tRTLIL::Const const &_values;\n\t\tfriend class iterator;\n\t\trange(int data_width, addr_t base, RTLIL::Const const &values)\n\t\t: _data_width(data_width), _base(base), _values(values) {}\n\tpublic:\n\t\taddr_t base() const { return _base; }\n\t\taddr_t size() const { return ((addr_t) _values.size()) / _data_width; }\n\t\taddr_t limit() const { return _base + size(); }\n\t\tRTLIL::Const const &concatenated() const { return _values; }\n\t\tRTLIL::Const operator[](addr_t addr) const {\n\t\t\tlog_assert(addr - _base < size());\n\t\t\treturn _values.extract((addr - _base) * _data_width, _data_width);\n\t\t}\n\t\tRTLIL::Const at_offset(addr_t offset) const { return (*this)[_base + offset]; }\n\t};\n\tclass iterator {\n\t\tMemContents const *_memory;\n\t\t// storing addr instead of an iterator gives more well-defined behaviour under insertions/deletions\n\t\t// use ~0 for end so that all end iterators compare the same\n\t\taddr_t _addr;\n\t\tfriend class MemContents;\n\t\titerator(MemContents const *memory, addr_t addr) : _memory(memory), _addr(addr) {}\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = range;\n\t\tusing pointer = arrow_proxy<range>;\n\t\tusing reference = range;\n\t\tusing difference_type = addr_t;\n\t\treference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); }\n\t\tpointer operator->() const { return arrow_proxy<range>(**this); }\n\t\tbool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; }\n\t\tbool operator ==(iterator const &other) const { return !(*this != other); }\n\t\titerator &operator++();\n\t};\n\tMemContents(int addr_width, int data_width, RTLIL::Const default_value)\n\t\t: _addr_width(addr_width), _data_width(data_width)\n\t\t, _default_value((default_value.extu(data_width), std::move(default_value)))\n\t{ log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); log_assert(_data_width > 0); }\n\tMemContents(int addr_width, int data_width) : MemContents(addr_width, data_width, RTLIL::Const(State::Sx, data_width)) {}\n\texplicit MemContents(Mem *mem);\n\tint addr_width() const { return _addr_width; }\n\tint data_width() const { return _data_width; }\n\tRTLIL::Const const &default_value() const { return _default_value; }\n\t// return the value at the address if it exists, the default_value of the memory otherwise. address must not exceed 2**addr_width.\n\tRTLIL::Const operator [](addr_t addr) const;\n\t// return the number of defined words in the range [begin_addr, end_addr)\n\taddr_t count_range(addr_t begin_addr, addr_t end_addr) const;\n\t// allocate memory for the range [begin_addr, end_addr), but leave the contents undefined.\n\tvoid reserve_range(addr_t begin_addr, addr_t end_addr) { _reserve_range(begin_addr, end_addr); }\n\t// insert multiple words (provided as a single concatenated RTLIL::Const) at the given address, overriding any previous assignment.\n\tvoid insert_concatenated(addr_t addr, RTLIL::Const const &values);\n\t// insert multiple words at the given address, overriding any previous assignment.\n\ttemplate<typename Iterator> void insert_range(addr_t addr, Iterator begin, Iterator end) {\n\t\tauto words = end - begin;\n\t\tlog_assert(addr < (addr_t)(1<<_addr_width)); log_assert(words <= (addr_t)(1<<_addr_width) - addr);\n\t\tauto range = _reserve_range(addr, addr + words);\n\t\tauto it = _range_data(range, addr);\n\t\tfor(; begin != end; ++begin)\n\t\t\tit = _range_write(it, *begin);\n\t}\n\t// undefine all words in the range [begin_addr, end_addr)\n\tvoid clear_range(addr_t begin_addr, addr_t end_addr);\n\t// check invariants, abort if invariants failed\n\tvoid check();\n\titerator end() const { return iterator(nullptr, ~(addr_t) 0); }\n\titerator begin() const { return _values.empty() ? end() : iterator(this, _values.begin()->first); }\n\tbool empty() const { return _values.empty(); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
178
+ "macc.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct port_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\n\tstd::vector<port_t> ports;\n\tRTLIL::SigSpec bit_ports;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<port_t> new_ports;\n\t\tRTLIL::SigSpec new_bit_ports;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {\n\t\t\t\tbit_ports.append(port.in_a);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tfor (auto &bit : bit_ports)\n\t\t\tif (bit == State::S1)\n\t\t\t\toff = const_add(off, RTLIL::Const(1, width), false, false, width);\n\t\t\telse if (bit != State::S0)\n\t\t\t\tnew_bit_ports.append(bit);\n\n\t\tif (off.as_bool()) {\n\t\t\tport_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tnew_ports.swap(ports);\n\t\tbit_ports = new_bit_ports;\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tports.clear();\n\t\tbit_ports = cell->getPort(ID::B);\n\n\t\tauto config_bits = cell->getParam(ID::CONFIG);\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tport_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tports.push_back(this_port);\n\t\t}\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell) const\n\t{\n\t\tRTLIL::SigSpec port_a;\n\t\tstd::vector<RTLIL::State> config_bits;\n\t\tint max_size = 0, num_bits = 0;\n\n\t\tfor (auto &port : ports) {\n\t\t\tmax_size = max(max_size, GetSize(port.in_a));\n\t\t\tmax_size = max(max_size, GetSize(port.in_b));\n\t\t}\n\n\t\twhile (max_size)\n\t\t\tnum_bits++, max_size /= 2;\n\n\t\tlog_assert(num_bits < 16);\n\t\tconfig_bits.push_back(num_bits & 1 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 2 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 4 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 8 ? State::S1 : State::S0);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tconfig_bits.push_back(port.is_signed ? State::S1 : State::S0);\n\t\t\tconfig_bits.push_back(port.do_subtract ? State::S1 : State::S0);\n\n\t\t\tint size_a = GetSize(port.in_a);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tint size_b = GetSize(port.in_b);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tport_a.append(port.in_a);\n\t\t\tport_a.append(port.in_b);\n\t\t}\n\n\t\tcell->setPort(ID::A, port_a);\n\t\tcell->setPort(ID::B, bit_ports);\n\t\tcell->setParam(ID::CONFIG, config_bits);\n\t\tcell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));\n\t\tcell->setParam(ID::A_WIDTH, GetSize(port_a));\n\t\tcell->setParam(ID::B_WIDTH, GetSize(bit_ports));\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits())\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\tfor (auto bit : bit_ports) {\n\t\t\tif (bit.wire)\n\t\t\t\treturn false;\n\t\t\tresult = const_add(result, bit.data, false, false, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool is_simple_product()\n\t{\n\t\treturn bit_ports.empty() &&\n\t\t\t\tports.size() == 1 &&\n\t\t\t\t!ports[0].in_b.empty() &&\n\t\t\t\t!ports[0].do_subtract;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
179
+ "mem.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MEM_H\n#define MEM_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n#include \"kernel/utils.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct MemRd : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity, ce_over_srst;\n\tConst arst_value, srst_value, init_value;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will bypass the written data\n\t// to this port's output (default behavior is to read old value).\n\t// Can only be set for write ports that have the same clock domain.\n\tstd::vector<bool> transparency_mask;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will return an all-X (don't care)\n\t// value. Mutually exclusive with transparency_mask.\n\t// Can only be set for write ports that have the same clock domain.\n\t// For optimization purposes, this will also be set if we can\n\t// determine that the two ports can never be active simultanously\n\t// (making the above vacuously true).\n\tstd::vector<bool> collision_x_mask;\n\tSigSpec clk, en, arst, srst, addr, data;\n\n\tMemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n};\n\nstruct MemWr : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity;\n\tstd::vector<bool> priority_mask;\n\tSigSpec clk, en, addr, data;\n\n\tMemWr() : removed(false), cell(nullptr) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n\n\tstd::pair<SigSpec, std::vector<int>> compress_en();\n\tSigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig);\n};\n\nstruct MemInit : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tConst addr;\n\tConst data;\n\tConst en;\n\tMemInit() : removed(false), cell(nullptr) {}\n};\n\nstruct Mem : RTLIL::AttrObject {\n\tModule *module;\n\tIdString memid;\n\tbool packed;\n\tRTLIL::Memory *mem;\n\tCell *cell;\n\tint width, start_offset, size;\n\tstd::vector<MemInit> inits;\n\tstd::vector<MemRd> rd_ports;\n\tstd::vector<MemWr> wr_ports;\n\n\t// Removes this memory from the module. The data in helper structures\n\t// is unaffected except for the cell/mem fields.\n\tvoid remove();\n\n\t// Commits all changes in helper structures into the module — ports and\n\t// inits marked as removed are actually removed, new ports/inits create\n\t// new cells, modified port/inits are commited into their existing\n\t// cells. Note that this reindexes the ports and inits array (actually\n\t// removing the ports/inits marked as removed).\n\tvoid emit();\n\n\t// Marks all inits as removed.\n\tvoid clear_inits();\n\n\t// Coalesces inits: whenever two inits have overlapping or touching\n\t// address ranges, they are combined into one, with the higher-priority\n\t// one's data overwriting the other. Running this results in\n\t// an inits list equivalent to the original, in which all entries\n\t// cover disjoint (and non-touching) address ranges, and all enable\n\t// masks are all-1.\n\tvoid coalesce_inits();\n\n\t// Checks consistency of this memory and all its ports/inits, using\n\t// log_assert.\n\tvoid check();\n\n\t// Gathers all initialization data into a single big const covering\n\t// the whole memory. For all non-initialized bits, Sx will be returned.\n\tConst get_init_data() const;\n\n\t// Constructs and returns the helper structures for all memories\n\t// in a module.\n\tstatic std::vector<Mem> get_all_memories(Module *module);\n\n\t// Constructs and returns the helper structures for all selected\n\t// memories in a module.\n\tstatic std::vector<Mem> get_selected_memories(Module *module);\n\n\t// Converts a synchronous read port into an asynchronous one by\n\t// extracting the data (or, in some rare cases, address) register\n\t// into a separate cell, together with any soft-transparency\n\t// logic necessary to preserve its semantics. Returns the created\n\t// register cell, if any. Note that in some rare cases this function\n\t// may succeed and perform a conversion without creating a new\n\t// register — a nullptr result doesn't imply nothing was done.\n\tCell *extract_rdff(int idx, FfInitVals *initvals);\n\n\t// Splits all wide ports in this memory into equivalent narrow ones.\n\t// This function performs no modifications at all to the actual\n\t// netlist unless and until emit() is called.\n\tvoid narrow();\n\n\t// If write port idx2 currently has priority over write port idx1,\n\t// inserts extra logic on idx1's enable signal to disable writes\n\t// when idx2 is writing to the same address, then removes the priority\n\t// from the priority mask. If there is a memory port that is\n\t// transparent with idx1, but not with idx2, that port is converted\n\t// to use soft transparency logic.\n\tvoid emulate_priority(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Creates soft-transparency logic on read port ridx, bypassing the\n\t// data from write port widx. Should only be called when ridx is\n\t// transparent wrt widx in the first place. Once we're done, the\n\t// transparency_mask bit will be cleared, and the collision_x_mask\n\t// bit will be set instead (since whatever value is read will be\n\t// replaced by the soft transparency logic).\n\tvoid emulate_transparency(int widx, int ridx, FfInitVals *initvals);\n\n\t// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).\n\t// Specifically, takes care of priority masks: any priority relations\n\t// that idx2 had are replicated onto idx1, unless they conflict with\n\t// priorities already present on idx1, in which case emulate_priority\n\t// is called. Likewise, ensures transparency and undefined collision\n\t// masks of all read ports have the same values for both ports,\n\t// calling emulate_transparency if necessary.\n\tvoid prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares for merging read port idx2 into idx1.\n\t// Specifically, makes sure the transparency and undefined collision\n\t// masks of both ports are equal, by changing undefined behavior\n\t// of one port to the other's defined behavior, or by calling\n\t// emulate_transparency if necessary.\n\tvoid prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares the memory for widening a port to a given width. This\n\t// involves ensuring that start_offset and size are aligned to the\n\t// target width.\n\tvoid widen_prep(int wide_log2);\n\n\t// Widens a write port up to a given width. The newly port is\n\t// equivalent to the original, made by replicating enable/data bits\n\t// and masking enable bits with decoders on the low part of the\n\t// original address.\n\tvoid widen_wr_port(int idx, int wide_log2);\n\n\t// Emulates a sync read port's enable functionality in soft logic,\n\t// changing the actual read port's enable to be always-on.\n\tvoid emulate_rden(int idx, FfInitVals *initvals);\n\n\t// Emulates a sync read port's initial/reset value functionality in\n\t// soft logic, removing it from the actual read port.\n\tvoid emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals);\n\n\t// Given a read port with ce_over_srst set, converts it to a port\n\t// with ce_over_srst unset without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_ce_over_srst(int idx);\n\n\t// Given a read port with ce_over_srst unset, converts it to a port\n\t// with ce_over_srst set without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_srst_over_ce(int idx);\n\n\t// Returns true iff emulate_read_first makes sense to call.\n\tbool emulate_read_first_ok();\n\n\t// Emulates all read-first read-write port relationships in terms of\n\t// all-transparent ports, by delaying all write ports by one cycle.\n\t// This can only be used when all read ports and all write ports are\n\t// in the same clock domain.\n\tvoid emulate_read_first(FfInitVals *initvals);\n\n\tMem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}\n};\n\n// MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined\nclass MemContents {\npublic:\n\tclass range; class iterator;\n\tusing addr_t = uint32_t;\nprivate:\n\t// we ban _addr_width == sizeof(addr_t) * 8 because it adds too many cornercases\n\tint _addr_width;\n\tint _data_width;\n\tRTLIL::Const _default_value;\n\t// for each range, store the concatenation of the words at the start address\n\t// invariants:\n\t// - no overlapping or adjacent ranges\n\t// - no empty ranges\n\t// - all Consts are a multiple of the word size\n\tstd::map<addr_t, RTLIL::Const> _values;\n\t// returns an iterator to the range containing addr, if it exists, or the first range past addr\n\tstd::map<addr_t, RTLIL::Const>::iterator _range_at(addr_t addr) const;\n\taddr_t _range_size(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->second.size() / _data_width; }\n\taddr_t _range_begin(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->first; }\n\taddr_t _range_end(std::map<addr_t, RTLIL::Const>::iterator it) const { return _range_begin(it) + _range_size(it); }\n\t// check if the iterator points to a range containing addr\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const;\n\t// check if the iterator points to a range containing [begin_addr, end_addr). assumes end_addr >= begin_addr.\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// check if the iterator points to a range overlapping with [begin_addr, end_addr)\n\tbool _range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// return the offset the addr would have in the range at `it`\n\tsize_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }\n\t// assuming _range_contains(it, addr), return an iterator pointing to the data at addr\n\tstd::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits().begin() + _range_offset(it, addr); }\n\t// internal version of reserve_range that returns an iterator to the range\n\tstd::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);\n\t// write a single word at addr, return iterator to next word\n\tstd::vector<State>::iterator _range_write(std::vector<State>::iterator it, RTLIL::Const const &data);\npublic:\n\tclass range {\n\t\tint _data_width;\n\t\taddr_t _base;\n\t\tRTLIL::Const const &_values;\n\t\tfriend class iterator;\n\t\trange(int data_width, addr_t base, RTLIL::Const const &values)\n\t\t: _data_width(data_width), _base(base), _values(values) {}\n\tpublic:\n\t\taddr_t base() const { return _base; }\n\t\taddr_t size() const { return ((addr_t) _values.size()) / _data_width; }\n\t\taddr_t limit() const { return _base + size(); }\n\t\tRTLIL::Const const &concatenated() const { return _values; }\n\t\tRTLIL::Const operator[](addr_t addr) const {\n\t\t\tlog_assert(addr - _base < size());\n\t\t\treturn _values.extract((addr - _base) * _data_width, _data_width);\n\t\t}\n\t\tRTLIL::Const at_offset(addr_t offset) const { return (*this)[_base + offset]; }\n\t};\n\tclass iterator {\n\t\tMemContents const *_memory;\n\t\t// storing addr instead of an iterator gives more well-defined behaviour under insertions/deletions\n\t\t// use ~0 for end so that all end iterators compare the same\n\t\taddr_t _addr;\n\t\tfriend class MemContents;\n\t\titerator(MemContents const *memory, addr_t addr) : _memory(memory), _addr(addr) {}\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = range;\n\t\tusing pointer = arrow_proxy<range>;\n\t\tusing reference = range;\n\t\tusing difference_type = addr_t;\n\t\treference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); }\n\t\tpointer operator->() const { return arrow_proxy<range>(**this); }\n\t\tbool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; }\n\t\tbool operator ==(iterator const &other) const { return !(*this != other); }\n\t\titerator &operator++();\n\t};\n\tMemContents(int addr_width, int data_width, RTLIL::Const default_value)\n\t\t: _addr_width(addr_width), _data_width(data_width)\n\t\t, _default_value((default_value.extu(data_width), std::move(default_value)))\n\t{ log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); log_assert(_data_width > 0); }\n\tMemContents(int addr_width, int data_width) : MemContents(addr_width, data_width, RTLIL::Const(State::Sx, data_width)) {}\n\texplicit MemContents(Mem *mem);\n\tint addr_width() const { return _addr_width; }\n\tint data_width() const { return _data_width; }\n\tRTLIL::Const const &default_value() const { return _default_value; }\n\t// return the value at the address if it exists, the default_value of the memory otherwise. address must not exceed 2**addr_width.\n\tRTLIL::Const operator [](addr_t addr) const;\n\t// return the number of defined words in the range [begin_addr, end_addr)\n\taddr_t count_range(addr_t begin_addr, addr_t end_addr) const;\n\t// allocate memory for the range [begin_addr, end_addr), but leave the contents undefined.\n\tvoid reserve_range(addr_t begin_addr, addr_t end_addr) { _reserve_range(begin_addr, end_addr); }\n\t// insert multiple words (provided as a single concatenated RTLIL::Const) at the given address, overriding any previous assignment.\n\tvoid insert_concatenated(addr_t addr, RTLIL::Const const &values);\n\t// insert multiple words at the given address, overriding any previous assignment.\n\ttemplate<typename Iterator> void insert_range(addr_t addr, Iterator begin, Iterator end) {\n\t\tauto words = end - begin;\n\t\tlog_assert(addr < (addr_t)(1<<_addr_width)); log_assert(words <= (addr_t)(1<<_addr_width) - addr);\n\t\tauto range = _reserve_range(addr, addr + words);\n\t\tauto it = _range_data(range, addr);\n\t\tfor(; begin != end; ++begin)\n\t\t\tit = _range_write(it, *begin);\n\t}\n\t// undefine all words in the range [begin_addr, end_addr)\n\tvoid clear_range(addr_t begin_addr, addr_t end_addr);\n\t// check invariants, abort if invariants failed\n\tvoid check();\n\titerator end() const { return iterator(nullptr, ~(addr_t) 0); }\n\titerator begin() const { return _values.empty() ? end() : iterator(this, _values.begin()->first); }\n\tbool empty() const { return _values.empty(); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "modtools.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MODTOOLS_H\n#define MODTOOLS_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ModIndex : public RTLIL::Monitor\n{\n\tstruct PortInfo {\n\t\tRTLIL::Cell* cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tPortInfo() : cell(), port(), offset() { }\n\t\tPortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }\n\n\t\tbool operator<(const PortInfo &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (offset != other.offset)\n\t\t\t\treturn offset < other.offset;\n\t\t\treturn port < other.port;\n\t\t}\n\n\t\tbool operator==(const PortInfo &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t\t}\n\t};\n\n\tstruct SigBitInfo\n\t{\n\t\tbool is_input, is_output;\n\t\tpool<PortInfo> ports;\n\n\t\tSigBitInfo() : is_input(false), is_output(false) { }\n\n\t\tbool operator==(const SigBitInfo &other) const {\n\t\t\treturn is_input == other.is_input && is_output == other.is_output && ports == other.ports;\n\t\t}\n\n\t\tvoid merge(const SigBitInfo &other)\n\t\t{\n\t\t\tis_input = is_input || other.is_input;\n\t\t\tis_output = is_output || other.is_output;\n\t\t\tports.insert(other.ports.begin(), other.ports.end());\n\t\t}\n\t};\n\n\tSigMap sigmap;\n\tRTLIL::Module *module;\n\tstd::map<RTLIL::SigBit, SigBitInfo> database;\n\tint auto_reload_counter;\n\tbool auto_reload_module;\n\n\tvoid port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.insert(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tvoid port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.erase(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tconst SigBitInfo &info(RTLIL::SigBit bit)\n\t{\n\t\treturn database[sigmap(bit)];\n\t}\n\n\tvoid reload_module(bool reset_sigmap = true)\n\t{\n\t\tif (reset_sigmap) {\n\t\t\tsigmap.clear();\n\t\t\tsigmap.set(module);\n\t\t}\n\n\t\tdatabase.clear();\n\t\tfor (auto wire : module->wires())\n\t\t\tif (wire->port_input || wire->port_output)\n\t\t\t\tfor (int i = 0; i < GetSize(wire); i++) {\n\t\t\t\t\tRTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));\n\t\t\t\t\tif (bit.wire && wire->port_input)\n\t\t\t\t\t\tdatabase[bit].is_input = true;\n\t\t\t\t\tif (bit.wire && wire->port_output)\n\t\t\t\t\t\tdatabase[bit].is_output = true;\n\t\t\t\t}\n\t\tfor (auto cell : module->cells())\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tport_add(cell, conn.first, conn.second);\n\n\t\tif (auto_reload_module) {\n\t\t\tif (++auto_reload_counter > 2)\n\t\t\t\tlog_warning(\"Auto-reload in ModIndex -- possible performance bug!\\n\");\n\t\t\tauto_reload_module = false;\n\t\t}\n\t}\n\n\tvoid check()\n\t{\n#ifndef NDEBUG\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (auto it : database)\n\t\t\tlog_assert(it.first == sigmap(it.first));\n\n\t\tauto database_bak = std::move(database);\n\t\treload_module(false);\n\n\t\tif (!(database == database_bak))\n\t\t{\n\t\t\tfor (auto &it : database_bak)\n\t\t\t\tif (!database.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database_bak, not database: %s\\n\", log_signal(it.first));\n\n\t\t\tfor (auto &it : database)\n\t\t\t\tif (!database_bak.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database, not database_bak: %s\\n\", log_signal(it.first));\n\t\t\t\telse if (!(it.second == database_bak.at(it.first)))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Different content for database[%s].\\n\", log_signal(it.first));\n\n\t\t\tlog_assert(database == database_bak);\n\t\t}\n#endif\n\t}\n\n\tvoid notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override\n\t{\n\t\tlog_assert(module == cell->module);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tport_del(cell, port, old_sig);\n\t\tport_add(cell, port, sig);\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override\n\t{\n\t\tlog_assert(module == mod);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (int i = 0; i < GetSize(sigsig.first); i++)\n\t\t{\n\t\t\tRTLIL::SigBit lhs = sigmap(sigsig.first[i]);\n\t\t\tRTLIL::SigBit rhs = sigmap(sigsig.second[i]);\n\t\t\tbool has_lhs = database.count(lhs) != 0;\n\t\t\tbool has_rhs = database.count(rhs) != 0;\n\n\t\t\tif (!has_lhs && !has_rhs) {\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t} else\n\t\t\tif (!has_rhs) {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\tlhs = sigmap(lhs);\n\t\t\t\tif (lhs.wire)\n\t\t\t\t\tdatabase[lhs] = new_info;\n\t\t\t} else\n\t\t\tif (!has_lhs) {\n\t\t\t\tSigBitInfo new_info = database.at(rhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t} else {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tnew_info.merge(database.at(rhs));\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tvoid notify_blackout(RTLIL::Module *mod) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)\n\t{\n\t\tauto_reload_counter = 0;\n\t\tauto_reload_module = true;\n\t\tmodule->monitors.insert(this);\n\t}\n\n\t~ModIndex()\n\t{\n\t\tmodule->monitors.erase(this);\n\t}\n\n\tSigBitInfo *query(RTLIL::SigBit bit)\n\t{\n\t\tif (auto_reload_module)\n\t\t\treload_module();\n\n\t\tauto it = database.find(sigmap(bit));\n\t\tif (it == database.end())\n\t\t\treturn nullptr;\n\t\telse\n\t\t\treturn &it->second;\n\t}\n\n\tbool query_is_input(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_input;\n\t}\n\n\tbool query_is_output(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_output;\n\t}\n\n\tpool<PortInfo> &query_ports(RTLIL::SigBit bit)\n\t{\n\t\tstatic pool<PortInfo> empty_result_set;\n\t\tSigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn empty_result_set;\n\t\treturn info->ports;\n\t}\n\n\tvoid dump_db()\n\t{\n\t\tlog(\"--- ModIndex Dump ---\\n\");\n\n\t\tif (auto_reload_module) {\n\t\t\tlog(\"AUTO-RELOAD\\n\");\n\t\t\treload_module();\n\t\t}\n\n\t\tfor (auto &it : database) {\n\t\t\tlog(\"BIT %s:\\n\", log_signal(it.first));\n\t\t\tif (it.second.is_input)\n\t\t\t\tlog(\" PRIMARY INPUT\\n\");\n\t\t\tif (it.second.is_output)\n\t\t\t\tlog(\" PRIMARY OUTPUT\\n\");\n\t\t\tfor (auto &port : it.second.ports)\n\t\t\t\tlog(\" PORT: %s.%s[%d] (%s)\\n\", log_id(port.cell),\n\t\t\t\t\t\tlog_id(port.port), port.offset, log_id(port.cell->type));\n\t\t}\n\t}\n};\n\nstruct ModWalker\n{\n\tstruct PortBit\n\t{\n\t\tRTLIL::Cell *cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tbool operator<(const PortBit &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (port != other.port)\n\t\t\t\treturn port < other.port;\n\t\t\treturn offset < other.offset;\n\t\t}\n\n\t\tbool operator==(const PortBit &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t\t}\n\t};\n\n\tRTLIL::Design *design;\n\tRTLIL::Module *module;\n\n\tCellTypes ct;\n\tSigMap sigmap;\n\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_drivers;\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_consumers;\n\tpool<RTLIL::SigBit> signal_inputs, signal_outputs;\n\n\tdict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;\n\n\tvoid add_wire(RTLIL::Wire *wire)\n\t{\n\t\tif (wire->port_input) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_inputs.insert(bit);\n\t\t}\n\n\t\tif (wire->port_output) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_outputs.insert(bit);\n\t\t}\n\t}\n\n\tvoid add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)\n\t{\n\t\tfor (int i = 0; i < int(bits.size()); i++)\n\t\t\tif (bits[i].wire != NULL) {\n\t\t\t\tPortBit pbit = { cell, port, i };\n\t\t\t\tif (is_output) {\n\t\t\t\t\tsignal_drivers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_outputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t\tif (is_input) {\n\t\t\t\t\tsignal_consumers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_inputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\tvoid add_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (ct.cell_known(cell->type)) {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second),\n\t\t\t\t\t\tct.cell_output(cell->type, conn.first),\n\t\t\t\t\t\tct.cell_input(cell->type, conn.first));\n\t\t} else {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second), true, true);\n\t\t}\n\t}\n\n\tModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)\n\t{\n\t\tct.setup(design);\n\t\tif (module)\n\t\t\tsetup(module);\n\t}\n\n\tvoid setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)\n\t{\n\t\tthis->module = module;\n\n\t\tsigmap.set(module);\n\n\t\tsignal_drivers.clear();\n\t\tsignal_consumers.clear();\n\t\tsignal_inputs.clear();\n\t\tsignal_outputs.clear();\n\t\tcell_inputs.clear();\n\t\tcell_outputs.clear();\n\n\t\tfor (auto &it : module->wires_)\n\t\t\tadd_wire(it.second);\n\t\tfor (auto &it : module->cells_)\n\t\t\tif (filter_ct == NULL || filter_ct->cell_known(it.second->type))\n\t\t\t\tadd_cell(it.second);\n\t}\n\n\t// get_* methods -- single RTLIL::SigBit\n\n\tinline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_drivers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_consumers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_inputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_outputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- container of RTLIL::SigBit's (always by reference)\n\n\ttemplate<typename T>\n\tinline bool get_drivers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_drivers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_consumers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_consumers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_inputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_outputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- call by RTLIL::SigSpec (always by value)\n\n\tbool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_drivers(result, bits);\n\t}\n\n\tbool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_consumers(result, bits);\n\t}\n\n\tbool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_inputs(result, bits);\n\t}\n\n\tbool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_outputs(result, bits);\n\t}\n\n\t// has_* methods -- call by reference\n\n\ttemplate<typename T>\n\tinline bool has_drivers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_consumers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_inputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_outputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n\n\t// has_* methods -- call by value\n\n\tinline bool has_drivers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\tinline bool has_consumers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\tinline bool has_inputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\tinline bool has_outputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "qcsat.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef QCSAT_H\n#define QCSAT_H\n\n#include \"kernel/satgen.h\"\n#include \"kernel/modtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// This is a helper class meant for easy construction of quick SAT queries\n// to a combinatorial input cone of some set of signals, meant for SAT-based\n// optimizations. Various knobs are provided to set just how much of the\n// cone should be included in the model — since this class is meant for\n// optimization, it should not be a correctness problem when some cells are\n// skipped and the solver spuriously returns SAT with a solution that\n// cannot exist in reality due to skipped constraints (ie. only UNSAT results\n// from this class should be considered binding).\nstruct QuickConeSat {\n\tModWalker &modwalker;\n\tezSatPtr ez;\n\tSatGen satgen;\n\n\t// The effort level knobs.\n\n\t// The maximum \"complexity level\" of cells that will be imported.\n\t// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa\n\t// - 2: addition, subtraction, greater/less than comparisons, lcu\n\t// - 3: shifts\n\t// - 4: multiplication, division, power\n\tint max_cell_complexity = 2;\n\t// The maximum number of cells to import, or 0 for no limit.\n\tint max_cell_count = 0;\n\t// If non-0, skip importing cells with more than this number of output bits.\n\tint max_cell_outs = 0;\n\n\t// Internal state.\n\tpool<RTLIL::Cell*> imported_cells;\n\tpool<RTLIL::Wire*> imported_onehot;\n\tpool<RTLIL::SigBit> bits_queue;\n\n\tQuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}\n\n\t// Imports a signal into the SAT solver, queues its input cone to be\n\t// imported in the next prepare() call.\n\tstd::vector<int> importSig(SigSpec sig);\n\tint importSigBit(SigBit bit);\n\n\t// Imports the input cones of all previously importSig'd signals into\n\t// the SAT solver.\n\tvoid prepare();\n\n\t// Returns the \"complexity level\" of a given cell.\n\tstatic int cell_complexity(RTLIL::Cell *cell);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "register.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
179
- "rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct IdString\n\t{\n\t\t#undef YOSYS_XTRACE_GET_PUT\n\t\t#undef YOSYS_SORT_ID_FREE_LIST\n\t\t#undef YOSYS_USE_STICKY_IDS\n\t\t#undef YOSYS_NO_IDS_REFCNT\n\n\t\t// the global id string cache\n\n\t\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\t\tstatic struct destruct_guard_t {\n\t\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t\t} destruct_guard;\n\n\t\tstatic std::vector<char*> global_id_storage_;\n\t\tstatic dict<char*, int, hash_cstr_ops> global_id_index_;\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic std::vector<int> global_refcount_storage_;\n\t\tstatic std::vector<int> global_free_idx_list_;\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tstatic int last_created_idx_ptr_;\n\t\tstatic int last_created_idx_[8];\n\t#endif\n\n\t\tstatic inline void xtrace_db_dump()\n\t\t{\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t\t{\n\t\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\t\telse\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\t\t}\n\n\t\tstatic inline void checkpoint()\n\t\t{\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\tlast_created_idx_ptr_ = 0;\n\t\t\tfor (int i = 0; i < 8; i++) {\n\t\t\t\tif (last_created_idx_[i])\n\t\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\t\tlast_created_idx_[i] = 0;\n\t\t\t}\n\t\t#endif\n\t\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t\t#endif\n\t\t}\n\n\t\tstatic inline int get_reference(int idx)\n\t\t{\n\t\t\tif (idx) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_[idx]++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\t\t\t}\n\t\t\treturn idx;\n\t\t}\n\n\t\tstatic int get_reference(const char *p)\n\t\t{\n\t\t\tlog_assert(destruct_guard_ok);\n\n\t\t\tif (!p[0])\n\t\t\t\treturn 0;\n\n\t\t\tauto it = global_id_index_.find((char*)p);\n\t\t\tif (it != global_id_index_.end()) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t\t#endif\n\t\t\t\treturn it->second;\n\t\t\t}\n\n\t\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\t\tlog_assert(p[1] != 0);\n\t\t\tfor (const char *c = p; *c; c++)\n\t\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tif (global_free_idx_list_.empty()) {\n\t\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t\t}\n\t\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t}\n\n\t\t\tint idx = global_free_idx_list_.back();\n\t\t\tglobal_free_idx_list_.pop_back();\n\t\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\t\tglobal_refcount_storage_.at(idx)++;\n\t\t#else\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tint idx = global_id_storage_.size();\n\t\t\tglobal_id_storage_.push_back(strdup(p));\n\t\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t\t#endif\n\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\t// Avoid Create->Delete->Create pattern\n\t\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t\t#endif\n\n\t\t\treturn idx;\n\t\t}\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic inline void put_reference(int idx)\n\t\t{\n\t\t\t// put_reference() may be called from destructors after the destructor of\n\t\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\t\tif (!destruct_guard_ok || !idx)\n\t\t\t\treturn;\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\n\t\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\t\tif (--refcount > 0)\n\t\t\t\treturn;\n\n\t\t\tlog_assert(refcount == 0);\n\t\t\tfree_reference(idx);\n\t\t}\n\t\tstatic inline void free_reference(int idx)\n\t\t{\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\t\tfree(global_id_storage_.at(idx));\n\t\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\t\tglobal_free_idx_list_.push_back(idx);\n\t\t}\n\t#else\n\t\tstatic inline void put_reference(int) { }\n\t#endif\n\n\t\t// the actual IdString object is just is a single int\n\n\t\tint index_;\n\n\t\tinline IdString() : index_(0) { }\n\t\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\t\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\t\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\t\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\t\tinline ~IdString() { put_reference(index_); }\n\n\t\tinline void operator=(const IdString &rhs) {\n\t\t\tput_reference(index_);\n\t\t\tindex_ = get_reference(rhs.index_);\n\t\t}\n\n\t\tinline void operator=(const char *rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline void operator=(const std::string &rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline const char *c_str() const {\n\t\t\treturn global_id_storage_.at(index_);\n\t\t}\n\n\t\tinline std::string str() const {\n\t\t\treturn std::string(global_id_storage_.at(index_));\n\t\t}\n\n\t\tinline bool operator<(const IdString &rhs) const {\n\t\t\treturn index_ < rhs.index_;\n\t\t}\n\n\t\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\t\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\t\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\t\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\t\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\t\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\t\tchar operator[](size_t i) const {\n const char *p = c_str();\n#ifndef NDEBUG\n\t\t\tfor (; i != 0; i--, p++)\n\t\t\t\tlog_assert(*p != 0);\n\t\t\treturn *p;\n#else\n\t\t\treturn *(p + i);\n#endif\n\t\t}\n\n\t\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\t\treturn std::string(c_str() + pos);\n\t\t\telse\n\t\t\t\treturn std::string(c_str() + pos, len);\n\t\t}\n\n\t\tint compare(size_t pos, size_t len, const char* s) const {\n\t\t\treturn strncmp(c_str()+pos, s, len);\n\t\t}\n\n\t\tbool begins_with(const char* prefix) const {\n\t\t\tsize_t len = strlen(prefix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(0, len, prefix) == 0;\n\t\t}\n\n\t\tbool ends_with(const char* suffix) const {\n\t\t\tsize_t len = strlen(suffix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(size()-len, len, suffix) == 0;\n\t\t}\n\n\t\tbool contains(const char* str) const {\n\t\t\treturn strstr(c_str(), str);\n\t\t}\n\n\t\tsize_t size() const {\n\t\t\treturn strlen(c_str());\n\t\t}\n\n\t\tbool empty() const {\n\t\t\treturn c_str()[0] == 0;\n\t\t}\n\n\t\tvoid clear() {\n\t\t\t*this = IdString();\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn index_;\n\t\t}\n\n\t\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t\t// set has an influence on the algorithm.\n\n\t\ttemplate<typename T> struct compare_ptr_by_name {\n\t\t\tbool operator()(const T *a, const T *b) const {\n\t\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t\t}\n\t\t};\n\n\t\t// often one needs to check if a given IdString is part of a list (for example a list\n\t\t// of cell types). the following functions helps with that.\n\n\t\ttemplate<typename... Args>\n\t\tbool in(Args... args) const {\n\t\t\t// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html\n\t\t\tbool result = false;\n\t\t\t(void) std::initializer_list<int>{ (result = result || in(args), 0)... };\n\t\t\treturn result;\n\t\t}\n\n\t\tbool in(const IdString &rhs) const { return *this == rhs; }\n\t\tbool in(const char *rhs) const { return *this == rhs; }\n\t\tbool in(const std::string &rhs) const { return *this == rhs; }\n\t\tbool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n\n\t\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\t};\n\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tint flags;\n\tstd::vector<RTLIL::State> bits;\n\n\tConst() : flags(RTLIL::CONST_FLAG_NONE) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &c) = default;\n\tRTLIL::Const &operator =(const RTLIL::Const &other) = default;\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tstatic Const from_string(const std::string &str);\n\n\tstd::string decode_string() const;\n\n\tinline int size() const { return bits.size(); }\n\tinline bool empty() const { return bits.empty(); }\n\tinline RTLIL::State &operator[](int index) { return bits.at(index); }\n\tinline const RTLIL::State &operator[](int index) const { return bits.at(index); }\n\tinline decltype(bits)::iterator begin() { return bits.begin(); }\n\tinline decltype(bits)::iterator end() { return bits.end(); }\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tinline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {\n\t\tRTLIL::Const ret;\n\t\tret.bits.reserve(len);\n\t\tfor (int i = offset; i < offset + len; i++)\n\t\t\tret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);\n\t\treturn ret;\n\t}\n\n\tvoid extu(int width) {\n\t\tbits.resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());\n\t}\n\n\tinline unsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto b : bits)\n\t\t\th = mkhash(h, b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\tunsigned int hash() const;\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tunsigned long hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tsize_t get_hash() const {\n\t\tif (!hash_) hash();\n\t\treturn hash_;\n\t}\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\tunsigned int hash() const { if (!hash_) updhash(); return hash_; };\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline unsigned int RTLIL::SigBit::hash() const {\n\tif (wire)\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\treturn data;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
183
+ "rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\t// Semantic metadata - how can this constant be interpreted?\n\t// Values may be generally non-exclusive\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct IdString\n\t{\n\t\t#undef YOSYS_XTRACE_GET_PUT\n\t\t#undef YOSYS_SORT_ID_FREE_LIST\n\t\t#undef YOSYS_USE_STICKY_IDS\n\t\t#undef YOSYS_NO_IDS_REFCNT\n\n\t\t// the global id string cache\n\n\t\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\t\tstatic struct destruct_guard_t {\n\t\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t\t} destruct_guard;\n\n\t\tstatic std::vector<char*> global_id_storage_;\n\t\tstatic dict<char*, int, hash_cstr_ops> global_id_index_;\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic std::vector<int> global_refcount_storage_;\n\t\tstatic std::vector<int> global_free_idx_list_;\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tstatic int last_created_idx_ptr_;\n\t\tstatic int last_created_idx_[8];\n\t#endif\n\n\t\tstatic inline void xtrace_db_dump()\n\t\t{\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t\t{\n\t\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\t\telse\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\t\t}\n\n\t\tstatic inline void checkpoint()\n\t\t{\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\tlast_created_idx_ptr_ = 0;\n\t\t\tfor (int i = 0; i < 8; i++) {\n\t\t\t\tif (last_created_idx_[i])\n\t\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\t\tlast_created_idx_[i] = 0;\n\t\t\t}\n\t\t#endif\n\t\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t\t#endif\n\t\t}\n\n\t\tstatic inline int get_reference(int idx)\n\t\t{\n\t\t\tif (idx) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_[idx]++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\t\t\t}\n\t\t\treturn idx;\n\t\t}\n\n\t\tstatic int get_reference(const char *p)\n\t\t{\n\t\t\tlog_assert(destruct_guard_ok);\n\n\t\t\tif (!p[0])\n\t\t\t\treturn 0;\n\n\t\t\tauto it = global_id_index_.find((char*)p);\n\t\t\tif (it != global_id_index_.end()) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t\t#endif\n\t\t\t\treturn it->second;\n\t\t\t}\n\n\t\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\t\tlog_assert(p[1] != 0);\n\t\t\tfor (const char *c = p; *c; c++)\n\t\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tif (global_free_idx_list_.empty()) {\n\t\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t\t}\n\t\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t}\n\n\t\t\tint idx = global_free_idx_list_.back();\n\t\t\tglobal_free_idx_list_.pop_back();\n\t\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\t\tglobal_refcount_storage_.at(idx)++;\n\t\t#else\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tint idx = global_id_storage_.size();\n\t\t\tglobal_id_storage_.push_back(strdup(p));\n\t\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t\t#endif\n\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\t// Avoid Create->Delete->Create pattern\n\t\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t\t#endif\n\n\t\t\treturn idx;\n\t\t}\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic inline void put_reference(int idx)\n\t\t{\n\t\t\t// put_reference() may be called from destructors after the destructor of\n\t\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\t\tif (!destruct_guard_ok || !idx)\n\t\t\t\treturn;\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\n\t\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\t\tif (--refcount > 0)\n\t\t\t\treturn;\n\n\t\t\tlog_assert(refcount == 0);\n\t\t\tfree_reference(idx);\n\t\t}\n\t\tstatic inline void free_reference(int idx)\n\t\t{\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\t\tfree(global_id_storage_.at(idx));\n\t\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\t\tglobal_free_idx_list_.push_back(idx);\n\t\t}\n\t#else\n\t\tstatic inline void put_reference(int) { }\n\t#endif\n\n\t\t// the actual IdString object is just is a single int\n\n\t\tint index_;\n\n\t\tinline IdString() : index_(0) { }\n\t\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\t\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\t\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\t\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\t\tinline ~IdString() { put_reference(index_); }\n\n\t\tinline void operator=(const IdString &rhs) {\n\t\t\tput_reference(index_);\n\t\t\tindex_ = get_reference(rhs.index_);\n\t\t}\n\n\t\tinline void operator=(const char *rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline void operator=(const std::string &rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline const char *c_str() const {\n\t\t\treturn global_id_storage_.at(index_);\n\t\t}\n\n\t\tinline std::string str() const {\n\t\t\treturn std::string(global_id_storage_.at(index_));\n\t\t}\n\n\t\tinline bool operator<(const IdString &rhs) const {\n\t\t\treturn index_ < rhs.index_;\n\t\t}\n\n\t\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\t\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\t\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\t\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\t\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\t\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\t\tchar operator[](size_t i) const {\n const char *p = c_str();\n#ifndef NDEBUG\n\t\t\tfor (; i != 0; i--, p++)\n\t\t\t\tlog_assert(*p != 0);\n\t\t\treturn *p;\n#else\n\t\t\treturn *(p + i);\n#endif\n\t\t}\n\n\t\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\t\treturn std::string(c_str() + pos);\n\t\t\telse\n\t\t\t\treturn std::string(c_str() + pos, len);\n\t\t}\n\n\t\tint compare(size_t pos, size_t len, const char* s) const {\n\t\t\treturn strncmp(c_str()+pos, s, len);\n\t\t}\n\n\t\tbool begins_with(const char* prefix) const {\n\t\t\tsize_t len = strlen(prefix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(0, len, prefix) == 0;\n\t\t}\n\n\t\tbool ends_with(const char* suffix) const {\n\t\t\tsize_t len = strlen(suffix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(size()-len, len, suffix) == 0;\n\t\t}\n\n\t\tbool contains(const char* str) const {\n\t\t\treturn strstr(c_str(), str);\n\t\t}\n\n\t\tsize_t size() const {\n\t\t\treturn strlen(c_str());\n\t\t}\n\n\t\tbool empty() const {\n\t\t\treturn c_str()[0] == 0;\n\t\t}\n\n\t\tvoid clear() {\n\t\t\t*this = IdString();\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn index_;\n\t\t}\n\n\t\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t\t// set has an influence on the algorithm.\n\n\t\ttemplate<typename T> struct compare_ptr_by_name {\n\t\t\tbool operator()(const T *a, const T *b) const {\n\t\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t\t}\n\t\t};\n\n\t\t// often one needs to check if a given IdString is part of a list (for example a list\n\t\t// of cell types). the following functions helps with that.\n\n\t\ttemplate<typename... Args>\n\t\tbool in(Args... args) const {\n\t\t\t// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html\n\t\t\tbool result = false;\n\t\t\t(void) std::initializer_list<int>{ (result = result || in(args), 0)... };\n\t\t\treturn result;\n\t\t}\n\n\t\tbool in(const IdString &rhs) const { return *this == rhs; }\n\t\tbool in(const char *rhs) const { return *this == rhs; }\n\t\tbool in(const std::string &rhs) const { return *this == rhs; }\n\t\tbool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n\n\t\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\t};\n\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tshort int flags;\nprivate:\n\tfriend class KernelRtlilTest;\n\tFRIEND_TEST(KernelRtlilTest, ConstStr);\n\tusing bitvectype = std::vector<RTLIL::State>;\n\tenum class backing_tag: bool { bits, string };\n\t// Do not access the union or tag even in Const methods unless necessary\n\tmutable backing_tag tag;\n\tunion {\n\t\tmutable bitvectype bits_;\n\t\tmutable std::string str_;\n\t};\n\n\t// Use these private utilities instead\n\tbool is_bits() const { return tag == backing_tag::bits; }\n\tbool is_str() const { return tag == backing_tag::string; }\n\n\tbitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }\n\tstd::string* get_if_str() const { return is_str() ? &str_ : NULL; }\n\n\tbitvectype& get_bits() const;\n\tstd::string& get_str() const;\npublic:\n\tConst() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &other);\n\tConst(RTLIL::Const &&other);\n\tRTLIL::Const &operator =(const RTLIL::Const &other);\n\t~Const();\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tstd::vector<RTLIL::State>& bits();\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string(const char* any = \"-\") const;\n\tstatic Const from_string(const std::string &str);\n\tstd::vector<RTLIL::State> to_bits() const;\n\n\tstd::string decode_string() const;\n\tint size() const;\n\tbool empty() const;\n\tvoid bitvectorize() const;\n\n\tclass const_iterator {\n\tprivate:\n\t\tconst Const& parent;\n\t\tsize_t idx;\n\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = State;\n\t\tusing difference_type = std::ptrdiff_t;\n\t\tusing pointer = const State*;\n\t\tusing reference = const State&;\n\n\t\tconst_iterator(const Const& c, size_t i) : parent(c), idx(i) {}\n\n\t\tState operator*() const;\n\n\t\tconst_iterator& operator++() { ++idx; return *this; }\n\t\tconst_iterator& operator--() { --idx; return *this; }\n\t\tconst_iterator& operator++(int) { ++idx; return *this; }\n\t\tconst_iterator& operator--(int) { --idx; return *this; }\n\t\tconst_iterator& operator+=(int i) { idx += i; return *this; }\n\n\t\tconst_iterator operator+(int add) {\n\t\t\treturn const_iterator(parent, idx + add);\n\t\t}\n\t\tconst_iterator operator-(int sub) {\n\t\t\treturn const_iterator(parent, idx - sub);\n\t\t}\n\t\tint operator-(const const_iterator& other) {\n\t\t\treturn idx - other.idx;\n\t\t}\n\n\t\tbool operator==(const const_iterator& other) const {\n\t\t\treturn idx == other.idx;\n\t\t}\n\n\t\tbool operator!=(const const_iterator& other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\t};\n\n\tconst_iterator begin() const {\n\t\treturn const_iterator(*this, 0);\n\t}\n\tconst_iterator end() const {\n\t\treturn const_iterator(*this, size());\n\t}\n\tState back() const {\n\t\treturn *(end() - 1);\n\t}\n\tState front() const {\n\t\treturn *begin();\n\t}\n\tState at(size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\tState operator[](size_t i) const {\n\t\treturn *const_iterator(*this, i);\n\t}\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tRTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;\n\n\t// find the MSB without redundant leading bits\n\tint get_min_size(bool is_signed) const;\n\n\t// compress representation to the minimum required bits\n\tvoid compress(bool is_signed = false);\n\n\tstd::optional<int> as_int_compress(bool is_signed) const;\n\n\tvoid extu(int width) {\n\t\tbits().resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbitvectype& bv = bits();\n\t\tbv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());\n\t}\n\n\tinline unsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\n\t\tfor (State b : *this)\n\t\t\th = mkhash(h, b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\t[[deprecated(\"Use Module::get_blackbox_attribute() instead.\")]]\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\tunsigned int hash() const;\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tunsigned long hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tsize_t get_hash() const {\n\t\tif (!hash_) hash();\n\t\treturn hash_;\n\t}\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\tunsigned int hash() const { if (!hash_) updhash(); return hash_; };\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline unsigned int RTLIL::SigBit::hash() const {\n\tif (wire)\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\treturn data;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "satgen.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tSigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string name = pf + (bit.wire->width == 1 ? stringf(\"%s\", log_id(bit.wire)) : stringf(\"%s [%d]\", log_id(bit.wire->name), bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
181
- "scopeinfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\tunsigned int hash() const { return (uintptr_t)ptr; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tif (!object->name.isPublic())\n\t\treturn path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty())\n\t\tpath.push_back(object->name);\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic()) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
185
+ "scopeinfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\tint hash() const {\n\t\t\treturn mkhash(scope_name.hash(), hash_ptr_ops::hash(target));\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\tunsigned int hash() const { return (uintptr_t)ptr; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tif (!object->name.isPublic())\n\t\treturn path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty())\n\t\tpath.push_back(object->name);\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic()) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "sexpr.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Emily Schmidt <emily@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SEXPR_H\n#define SEXPR_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nclass SExpr {\npublic:\n\tstd::variant<std::vector<SExpr>, std::string> _v;\npublic:\n\tSExpr(std::string a) : _v(std::move(a)) {}\n SExpr(const char *a) : _v(a) {}\n // FIXME: should maybe be defined for all integral types\n\tSExpr(int n) : _v(std::to_string(n)) {}\n\tSExpr(std::vector<SExpr> const &l) : _v(l) {}\n\tSExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}\n // It would be nicer to have an std::initializer_list constructor,\n // but that causes confusing issues with overload resolution sometimes.\n template<typename... Args> static SExpr list(Args&&... args) {\n\t return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n }\n bool is_atom() const { return std::holds_alternative<std::string>(_v); }\n std::string const &atom() const { return std::get<std::string>(_v); }\n bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }\n std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }\n\tstd::string to_string() const;\n};\n\nstd::ostream &operator<<(std::ostream &os, SExpr const &sexpr);\n\nnamespace SExprUtil {\n // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list`\n template<typename... Args> SExpr list(Args&&... args) {\n\t return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n }\n}\n\n// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout.\nclass SExprWriter {\n std::ostream &os;\n int _max_line_width;\n int _indent = 0;\n int _pos = 0;\n // If _pending_nl is set, print a newline before the next character.\n // This lets us \"undo\" the last newline so we can put\n // closing parentheses or a hanging comment on the same line.\n bool _pending_nl = false;\n // Unclosed parentheses (boolean stored is indent_rest)\n\tvector<bool> _unclosed;\n // Used only for push() and pop() (stores _unclosed.size())\n\tvector<size_t> _unclosed_stack;\n\tvoid nl_if_pending();\n void puts(std::string_view s);\n int check_fit(SExpr const &sexpr, int space);\n void print(SExpr const &sexpr, bool close = true, bool indent_rest = true);\npublic:\n SExprWriter(std::ostream &os, int max_line_width = 80)\n : os(os)\n , _max_line_width(max_line_width)\n {}\n // Print an s-expr.\n SExprWriter &operator <<(SExpr const &sexpr) {\n print(sexpr);\n _pending_nl = true;\n return *this;\n }\n // Print an s-expr (which must be a list), but leave room for extra elements\n // which may be printed using either << or further calls to open.\n // If indent_rest = false, the remaining elements are not intended\n // (for avoiding unreasonable indentation on deeply nested structures).\n void open(SExpr const &sexpr, bool indent_rest = true) {\n log_assert(sexpr.is_list());\n print(sexpr, false, indent_rest);\n }\n // Close the s-expr opened with the last call to open\n // (if an argument is given, close that many s-exprs).\n void close(size_t n = 1);\n // push() remembers how many s-exprs are currently open\n\tvoid push() {\n\t\t_unclosed_stack.push_back(_unclosed.size());\n\t}\n // pop() closes all s-expr opened since the corresponding call to push()\n\tvoid pop() {\n\t\tauto t = _unclosed_stack.back();\n\t\tlog_assert(_unclosed.size() >= t);\n\t\tclose(_unclosed.size() - t);\n\t\t_unclosed_stack.pop_back();\n\t}\n // Print a comment.\n // If hanging = true, append it to the end of the last printed s-expr.\n\tvoid comment(std::string const &str, bool hanging = false);\n // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses.\n void flush() {\n nl_if_pending();\n }\n // Destructor closes any unclosed parentheses and flushes.\n ~SExprWriter();\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "sigtools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SIGTOOLS_H\n#define SIGTOOLS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct SigPool\n{\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tpool<bitDef_t> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.insert(bit);\n\t}\n\n\tvoid add(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.insert(bit);\n\t}\n\n\tvoid del(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.erase(bit);\n\t}\n\n\tvoid del(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.erase(bit);\n\t}\n\n\tvoid expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\t\tfor (int i = 0; i < GetSize(from); i++) {\n\t\t\tbitDef_t bit_from(from[i]), bit_to(to[i]);\n\t\t\tif (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)\n\t\t\t\tbits.insert(bit_to);\n\t\t}\n\t}\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tRTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tbool check(const RTLIL::SigBit &bit) const\n\t{\n\t\treturn bit.wire != NULL && bits.count(bit);\n\t}\n\n\tbool check_any(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool check_all(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tRTLIL::SigSpec export_one() const\n\t{\n\t\tfor (auto &bit : bits)\n\t\t\treturn RTLIL::SigSpec(bit.first, bit.second);\n\t\treturn RTLIL::SigSpec();\n\t}\n\n\tRTLIL::SigSpec export_all() const\n\t{\n\t\tpool<RTLIL::SigBit> sig;\n\t\tfor (auto &bit : bits)\n\t\t\tsig.insert(RTLIL::SigBit(bit.first, bit.second));\n\t\treturn sig;\n\t}\n\n\tsize_t size() const\n\t{\n\t\treturn bits.size();\n\t}\n};\n\ntemplate <typename T, class Compare = void>\nstruct SigSet\n{\n\tstatic_assert(!std::is_same<Compare,void>::value, \"Default value for `Compare' class not found for SigSet<T>. Please specify.\");\n\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tdict<bitDef_t, std::set<T, Compare>> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid insert(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data);\n\t}\n\n\tvoid insert(const RTLIL::SigSpec& sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data.begin(), data.end());\n\t}\n\n\tvoid erase(const RTLIL::SigSpec& sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].clear();\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data);\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data.begin(), data.end());\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, std::set<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, pool<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tstd::set<T> find(const RTLIL::SigSpec &sig)\n\t{\n\t\tstd::set<T> result;\n\t\tfind(sig, result);\n\t\treturn result;\n\t}\n\n\tbool has(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n};\n\ntemplate<typename T>\nclass SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};\ntemplate<typename T>\nusing sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;\ntemplate<typename T>\nclass SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};\n\n/**\n * SigMap wraps a union-find \"database\"\n * to map SigBits of a module to canonical representative SigBits.\n * SigBits that are connected share a set in the underlying database.\n * If a SigBit has a const state (impl: bit.wire is nullptr),\n * it's promoted to a representative.\n */\nstruct SigMap\n{\n\tmfp<SigBit> database;\n\n\tSigMap(RTLIL::Module *module = NULL)\n\t{\n\t\tif (module != NULL)\n\t\t\tset(module);\n\t}\n\n\tvoid swap(SigMap &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid clear()\n\t{\n\t\tdatabase.clear();\n\t}\n\n\t// Rebuild SigMap for all connections in module\n\tvoid set(RTLIL::Module *module)\n\t{\n\t\tint bitcount = 0;\n\t\tfor (auto &it : module->connections())\n\t\t\tbitcount += it.first.size();\n\n\t\tdatabase.clear();\n\t\tdatabase.reserve(bitcount);\n\n\t\tfor (auto &it : module->connections())\n\t\t\tadd(it.first, it.second);\n\t}\n\n\t// Add connections from \"from\" to \"to\", bit-by-bit\n\tvoid add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\n\t\tfor (int i = 0; i < GetSize(from); i++)\n\t\t{\n\t\t\tint bfi = database.lookup(from[i]);\n\t\t\tint bti = database.lookup(to[i]);\n\n\t\t\tconst RTLIL::SigBit &bf = database[bfi];\n\t\t\tconst RTLIL::SigBit &bt = database[bti];\n\n\t\t\tif (bf.wire || bt.wire)\n\t\t\t{\n\t\t\t\tdatabase.imerge(bfi, bti);\n\n\t\t\t\tif (bf.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bfi);\n\n\t\t\t\tif (bt.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bti);\n\t\t\t}\n\t\t}\n\t}\n\n\t// Add sig as disconnected from anything\n\tvoid add(const RTLIL::SigBit &bit)\n\t{\n\t\tconst auto &b = database.find(bit);\n\t\tif (b.wire != nullptr)\n\t\t\tdatabase.promote(bit);\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tadd(bit);\n\t}\n\n\tinline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }\n\n\t// Modify bit to its representative\n\tvoid apply(RTLIL::SigBit &bit) const\n\t{\n\t\tbit = database.find(bit);\n\t}\n\n\tvoid apply(RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tapply(bit);\n\t}\n\n\tRTLIL::SigBit operator()(RTLIL::SigBit bit) const\n\t{\n\t\tapply(bit);\n\t\treturn bit;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::SigSpec sig) const\n\t{\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::Wire *wire) const\n\t{\n\t\tSigSpec sig(wire);\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\t// All non-const bits\n\tRTLIL::SigSpec allbits() const\n\t{\n\t\tRTLIL::SigSpec sig;\n\t\tfor (const auto &bit : database)\n\t\t\tif (bit.wire != nullptr)\n\t\t\t\tsig.append(bit);\n\t\treturn sig;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif /* SIGTOOLS_H */\n",
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- "timinginfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * (C) 2020 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tunsigned int hash() const { return mkhash_add(name.hash(), offset); }\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\tunsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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+ "timinginfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * (C) 2020 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tunsigned int hash() const { return mkhash_add(name.hash(), offset); }\n\t\tstd::optional<SigBit> get_connection(RTLIL::Cell *cell) {\n\t\t\tif (!cell->hasPort(name))\n\t\t\t\treturn {};\n\t\t\tauto &port = cell->getPort(name);\n\t\t\tif (offset >= port.size())\n\t\t\t\treturn {};\n\t\t\treturn port[offset];\n\t\t}\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\tunsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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189
  "utils.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T, typename OPS = hash_ops<Key>>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*, OPS>> backup_state;\n\tdict<Key, T, OPS> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T, OPS> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T, OPS> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> class TopoSort\n{\n public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n if (rv.second) {\n \t nodes.push_back(n);\n\t\t edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\n// this class is used for implementing operator-> on iterators that return values rather than references\n// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained\ntemplate<class T>\nstruct arrow_proxy {\n\tT v;\n\texplicit arrow_proxy(T const & v) : v(v) {}\n\tT* operator->() { return &v; }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
186
- "yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n//\n// Find more information in the \"guidelines/GettingStarted\" file.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
187
- "yosys_common.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#ifdef YOSYS_ENABLE_TCL\n# include <tcl.h>\n# ifdef YOSYS_MXE_HACKS\nextern Tcl_Command Tcl_CreateCommand(Tcl_Interp *interp, const char *cmdName, Tcl_CmdProc *proc, ClientData clientData, Tcl_CmdDeleteProc *deleteProc);\nextern Tcl_Interp *Tcl_CreateInterp(void);\nextern void Tcl_Preserve(ClientData data);\nextern void Tcl_Release(ClientData clientData);\nextern int Tcl_InterpDeleted(Tcl_Interp *interp);\nextern void Tcl_DeleteInterp(Tcl_Interp *interp);\nextern int Tcl_Eval(Tcl_Interp *interp, const char *script);\nextern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);\nextern void Tcl_Finalize(void);\nextern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);\nextern const char *Tcl_GetStringResult(Tcl_Interp *interp);\nextern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);\nextern Tcl_Obj *Tcl_NewIntObj(int intValue);\nextern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);\nextern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);\n# endif\n# undef CONST\n# undef INLINE\n#endif\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#else\n# error \"C++17 or later compatible compiler is required\"\n#endif\n\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# undef HASHLIB_H\n# include \"kernel/hashlib.h\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\tunsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }\n};\n\nusing hashlib::mkhash;\nusing hashlib::mkhash_init;\nusing hashlib::mkhash_add;\nusing hashlib::mkhash_xorshift;\nusing hashlib::hash_ops;\nusing hashlib::hash_cstr_ops;\nusing hashlib::hash_ptr_ops;\nusing hashlib::hash_obj_ops;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n // For the common case of strings shorter than 128, save a heap\n // allocation by using a stack allocated buffer.\n const int kBufSize = 128;\n char buf[kBufSize];\n buf[0] = '\\0';\n va_list apc;\n va_copy(apc, ap);\n int n = vsnprintf(buf, kBufSize, fmt, apc);\n va_end(apc);\n if (n < kBufSize)\n return std::string(buf);\n\n std::string string;\n char *str = NULL;\n#if defined(_WIN32 )|| defined(__CYGWIN__)\n int sz = 2 * kBufSize, rc;\n while (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char*)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n if (vasprintf(&str, fmt, ap) < 0)\n str = NULL;\n if (str != NULL) {\n string = str;\n free(str);\n }\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n// sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::State> : hash_ops<int> {};\n}\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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+ "yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\n#ifdef YOSYS_ENABLE_TCL\nstruct Tcl_Interp;\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
191
+ "yosys_common.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#define FRIEND_TEST(test_case_name, test_name) \\\n friend class test_case_name##_##test_name##_Test\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#else\n# error \"C++17 or later compatible compiler is required\"\n#endif\n\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# undef HASHLIB_H\n# include \"kernel/hashlib.h\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\tunsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }\n};\n\nusing hashlib::mkhash;\nusing hashlib::mkhash_init;\nusing hashlib::mkhash_add;\nusing hashlib::mkhash_xorshift;\nusing hashlib::hash_ops;\nusing hashlib::hash_cstr_ops;\nusing hashlib::hash_ptr_ops;\nusing hashlib::hash_obj_ops;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n // For the common case of strings shorter than 128, save a heap\n // allocation by using a stack allocated buffer.\n const int kBufSize = 128;\n char buf[kBufSize];\n buf[0] = '\\0';\n va_list apc;\n va_copy(apc, ap);\n int n = vsnprintf(buf, kBufSize, fmt, apc);\n va_end(apc);\n if (n < kBufSize)\n return std::string(buf);\n\n std::string string;\n char *str = NULL;\n#if defined(_WIN32 )|| defined(__CYGWIN__)\n int sz = 2 * kBufSize, rc;\n while (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char*)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n if (vasprintf(&str, fmt, ap) < 0)\n str = NULL;\n if (str != NULL) {\n string = str;\n free(str);\n }\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n// sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::State> : hash_ops<int> {};\n}\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "yw.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YW_H\n#define YW_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/mem.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct IdPath : public std::vector<RTLIL::IdString>\n{\n\ttemplate<typename... T>\n\tIdPath(T&&... args) : std::vector<RTLIL::IdString>(std::forward<T>(args)...) { }\n\tIdPath prefix() const { return {begin(), end() - !empty()}; }\n\tstd::string str() const;\n\n\tbool has_address() const { int tmp; return get_address(tmp); };\n\tbool get_address(int &addr) const;\n\n\tint hash() const { return hashlib::hash_ops<std::vector<RTLIL::IdString>>::hash(*this); }\n};\n\nstruct WitnessHierarchyItem {\n\tRTLIL::Module *module;\n\tRTLIL::Wire *wire = nullptr;\n\tRTLIL::Cell *cell = nullptr;\n\tMem *mem = nullptr;\n\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Wire *wire) : module(module), wire(wire) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, Mem *mem) : module(module), mem(mem) {}\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback);\n\ntemplate<class T> static std::vector<std::string> witness_path(T *obj) {\n\tstd::vector<std::string> path;\n\tif (obj->name.isPublic()) {\n\t\tauto hdlname = obj->get_string_attribute(ID::hdlname);\n\t\tfor (auto token : split_tokens(hdlname))\n\t\t\tpath.push_back(\"\\\\\" + token);\n\t}\n\tif (path.empty())\n\t\tpath.push_back(obj->name.str());\n\treturn path;\n}\n\nstruct ReadWitness\n{\n\tstruct Clock {\n\t\tIdPath path;\n\t\tint offset;\n\t\tbool is_posedge = false;\n\t\tbool is_negedge = false;\n\t};\n\n\tstruct Signal {\n\t\tIdPath path;\n\t\tint offset;\n\t\tint width;\n\t\tbool init_only;\n\n\t\tint bits_offset;\n\t};\n\n\tstruct Step {\n\t\tstd::string bits;\n\t};\n\n\tstd::string filename;\n\tstd::vector<Clock> clocks;\n\tstd::vector<Signal> signals;\n\tstd::vector<Step> steps;\n\n\tReadWitness(const std::string &filename);\n\n\tRTLIL::Const get_bits(int t, int bits_offset, int width) const;\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *module, D data, T &callback)\n{\n\tauto const &const_path = path;\n\tsize_t path_size = path.size();\n\tfor (auto wire : module->wires())\n\t{\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : wire->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == wire->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty())\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(wire->name);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto cell : module->cells())\n\t{\n\t\tModule *child = module->design->module(cell->type);\n\t\tif (child == nullptr)\n\t\t\tcontinue;\n\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, 1, child, child_data, callback);\n\t\t}\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(cell->name);\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, hdlname.empty() ? hdlname_mode : -1, child, child_data, callback);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto mem : Mem::get_all_memories(module)) {\n\t\tstd::vector<std::string> hdlname;\n\n\t\tif (hdlname_mode >= 0 && mem.cell != nullptr)\n\t\t\thdlname = mem.cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == mem.cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t}\n\t\tpath.resize(path_size);\n\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(mem.memid);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\tpath.pop_back();\n\n\t\t\tif (mem.cell != nullptr && mem.cell->name != mem.memid) {\n\t\t\t\tpath.push_back(mem.cell->name);\n\t\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\t\tpath.pop_back();\n\t\t\t}\n\t\t}\n\t}\n}\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback)\n{\n\tIdPath path;\n\twitness_hierarchy_recursion<D, T>(path, 0, module, data, callback);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  },
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  "libs": {
@@ -201,7 +205,7 @@ export const filesystem = {
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  "passes": {
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  "fsm": {
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- "fsmdata.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FSMDATA_H\n#define FSMDATA_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FsmData\n{\n\tint num_inputs, num_outputs, state_bits, reset_state;\n\tstruct transition_t { int state_in, state_out; RTLIL::Const ctrl_in, ctrl_out; };\n\tstd::vector<transition_t> transition_table;\n\tstd::vector<RTLIL::Const> state_table;\n\n\tvoid copy_to_cell(RTLIL::Cell *cell)\n\t{\n\t\tcell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs);\n\t\tcell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs);\n\n\t\tint state_num_log2 = 0;\n\t\tfor (int i = state_table.size(); i > 0; i = i >> 1)\n\t\t\tstate_num_log2++;\n\t\tstate_num_log2 = max(state_num_log2, 1);\n\n\t\tcell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits);\n\t\tcell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());\n\t\tcell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);\n\t\tcell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);\n\t\tcell->parameters[ID::STATE_TABLE] = RTLIL::Const();\n\n\t\tfor (int i = 0; i < int(state_table.size()); i++) {\n\t\t\tstd::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;\n\t\t\tstd::vector<RTLIL::State> &bits_state = state_table[i].bits;\n\t\t\tbits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());\n\t\t}\n\n\t\tcell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());\n\t\tcell->parameters[ID::TRANS_TABLE] = RTLIL::Const();\n\t\tfor (int i = 0; i < int(transition_table.size()); i++)\n\t\t{\n\t\t\tstd::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;\n\t\t\ttransition_t &tr = transition_table[i];\n\n\t\t\tRTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);\n\t\t\tRTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);\n\t\t\tstd::vector<RTLIL::State> &bits_state_in = const_state_in.bits;\n\t\t\tstd::vector<RTLIL::State> &bits_state_out = const_state_out.bits;\n\n\t\t\tstd::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits;\n\t\t\tstd::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits;\n\n\t\t\t// append lsb first\n\t\t\tbits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());\n\t\t\tbits_table.insert(bits_table.end(), bits_state_out.begin(), bits_state_out.end());\n\t\t\tbits_table.insert(bits_table.end(), bits_ctrl_in.begin(), bits_ctrl_in.end());\n\t\t\tbits_table.insert(bits_table.end(), bits_state_in.begin(), bits_state_in.end());\n\t\t}\n\t}\n\n\tvoid copy_from_cell(RTLIL::Cell *cell)\n\t{\n\t\tnum_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int();\n\t\tnum_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int();\n\n\t\tstate_bits = cell->parameters[ID::STATE_BITS].as_int();\n\t\treset_state = cell->parameters[ID::STATE_RST].as_int();\n\n\t\tint state_num = cell->parameters[ID::STATE_NUM].as_int();\n\t\tint state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int();\n\t\tint trans_num = cell->parameters[ID::TRANS_NUM].as_int();\n\n\t\tif (reset_state < 0 || reset_state >= state_num)\n\t\t\treset_state = -1;\n\n\t\tconst RTLIL::Const &state_table = cell->parameters[ID::STATE_TABLE];\n\t\tconst RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE];\n\n\t\tfor (int i = 0; i < state_num; i++) {\n\t\t\tRTLIL::Const state_code;\n\t\t\tint off_begin = i*state_bits, off_end = off_begin + state_bits;\n\t\t\tstate_code.bits.insert(state_code.bits.begin(), state_table.bits.begin()+off_begin, state_table.bits.begin()+off_end);\n\t\t\tthis->state_table.push_back(state_code);\n\t\t}\n\n\t\tfor (int i = 0; i < trans_num; i++)\n\t\t{\n\t\t\tauto off_ctrl_out = trans_table.bits.begin() + i*(num_inputs+num_outputs+2*state_num_log2);\n\t\t\tauto off_state_out = off_ctrl_out + num_outputs;\n\t\t\tauto off_ctrl_in = off_state_out + state_num_log2;\n\t\t\tauto off_state_in = off_ctrl_in + num_inputs;\n\t\t\tauto off_end = off_state_in + state_num_log2;\n\n\t\t\tRTLIL::Const state_in, state_out, ctrl_in, ctrl_out;\n\t\t\tctrl_out.bits.insert(state_in.bits.begin(), off_ctrl_out, off_state_out);\n\t\t\tstate_out.bits.insert(state_out.bits.begin(), off_state_out, off_ctrl_in);\n\t\t\tctrl_in.bits.insert(ctrl_in.bits.begin(), off_ctrl_in, off_state_in);\n\t\t\tstate_in.bits.insert(state_in.bits.begin(), off_state_in, off_end);\n\n\t\t\ttransition_t tr;\n\t\t\ttr.state_in = state_in.as_int();\n\t\t\ttr.state_out = state_out.as_int();\n\t\t\ttr.ctrl_in = ctrl_in;\n\t\t\ttr.ctrl_out = ctrl_out;\n\n\t\t\tif (tr.state_in < 0 || tr.state_in >= state_num)\n\t\t\t\ttr.state_in = -1;\n\t\t\tif (tr.state_out < 0 || tr.state_out >= state_num)\n\t\t\t\ttr.state_out = -1;\n\n\t\t\ttransition_table.push_back(tr);\n\t\t}\n\t}\n\n\tvoid log_info(RTLIL::Cell *cell)\n\t{\n\t\tlog(\"-------------------------------------\\n\");\n\t\tlog(\"\\n\");\n\t\tlog(\" Information on FSM %s (%s):\\n\", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());\n\t\tlog(\"\\n\");\n\t\tlog(\" Number of input signals: %3d\\n\", num_inputs);\n\t\tlog(\" Number of output signals: %3d\\n\", num_outputs);\n\t\tlog(\" Number of state bits: %3d\\n\", state_bits);\n\n\t\tlog(\"\\n\");\n\t\tlog(\" Input signals:\\n\");\n\t\tRTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);\n\t\tfor (int i = 0; i < GetSize(sig_in); i++)\n\t\t\tlog(\" %3d: %s\\n\", i, log_signal(sig_in[i]));\n\n\t\tlog(\"\\n\");\n\t\tlog(\" Output signals:\\n\");\n\t\tRTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);\n\t\tfor (int i = 0; i < GetSize(sig_out); i++)\n\t\t\tlog(\" %3d: %s\\n\", i, log_signal(sig_out[i]));\n\n\t\tlog(\"\\n\");\n\t\tlog(\" State encoding:\\n\");\n\t\tfor (int i = 0; i < GetSize(state_table); i++)\n\t\t\tlog(\" %3d: %10s%s\\n\", i, log_signal(state_table[i], false),\n\t\t\t\t\tint(i) == reset_state ? \" <RESET STATE>\" : \"\");\n\n\t\tlog(\"\\n\");\n\t\tlog(\" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\\n\");\n\t\tfor (int i = 0; i < GetSize(transition_table); i++) {\n\t\t\ttransition_t &tr = transition_table[i];\n\t\t\tlog(\" %5d: %5d %s -> %5d %s\\n\", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));\n\t\t}\n\n\t\tlog(\"\\n\");\n\t\tlog(\"-------------------------------------\\n\");\n\t}\n\n\t// implemented in fsm_opt.cc\n\tstatic void optimize_fsm(RTLIL::Cell *cell, RTLIL::Module *module);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
208
+ "fsmdata.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FSMDATA_H\n#define FSMDATA_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FsmData\n{\n\tint num_inputs, num_outputs, state_bits, reset_state;\n\tstruct transition_t { int state_in, state_out; RTLIL::Const ctrl_in, ctrl_out; };\n\tstd::vector<transition_t> transition_table;\n\tstd::vector<RTLIL::Const> state_table;\n\n\tvoid copy_to_cell(RTLIL::Cell *cell)\n\t{\n\t\tcell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs);\n\t\tcell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs);\n\n\t\tint state_num_log2 = 0;\n\t\tfor (int i = state_table.size(); i > 0; i = i >> 1)\n\t\t\tstate_num_log2++;\n\t\tstate_num_log2 = max(state_num_log2, 1);\n\n\t\tcell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits);\n\t\tcell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());\n\t\tcell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);\n\t\tcell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);\n\t\tcell->parameters[ID::STATE_TABLE] = RTLIL::Const();\n\n\t\tfor (int i = 0; i < int(state_table.size()); i++) {\n\t\t\tstd::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();\n\t\t\tstd::vector<RTLIL::State> &bits_state = state_table[i].bits();\n\t\t\tbits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());\n\t\t}\n\n\t\tcell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());\n\t\tcell->parameters[ID::TRANS_TABLE] = RTLIL::Const();\n\t\tfor (int i = 0; i < int(transition_table.size()); i++)\n\t\t{\n\t\t\tstd::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();\n\t\t\ttransition_t &tr = transition_table[i];\n\n\t\t\tRTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);\n\t\t\tRTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);\n\t\t\tstd::vector<RTLIL::State> &bits_state_in = const_state_in.bits();\n\t\t\tstd::vector<RTLIL::State> &bits_state_out = const_state_out.bits();\n\n\t\t\tstd::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();\n\t\t\tstd::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();\n\n\t\t\t// append lsb first\n\t\t\tbits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());\n\t\t\tbits_table.insert(bits_table.end(), bits_state_out.begin(), bits_state_out.end());\n\t\t\tbits_table.insert(bits_table.end(), bits_ctrl_in.begin(), bits_ctrl_in.end());\n\t\t\tbits_table.insert(bits_table.end(), bits_state_in.begin(), bits_state_in.end());\n\t\t}\n\t}\n\n\tvoid copy_from_cell(RTLIL::Cell *cell)\n\t{\n\t\tnum_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int();\n\t\tnum_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int();\n\n\t\tstate_bits = cell->parameters[ID::STATE_BITS].as_int();\n\t\treset_state = cell->parameters[ID::STATE_RST].as_int();\n\n\t\tint state_num = cell->parameters[ID::STATE_NUM].as_int();\n\t\tint state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int();\n\t\tint trans_num = cell->parameters[ID::TRANS_NUM].as_int();\n\n\t\tif (reset_state < 0 || reset_state >= state_num)\n\t\t\treset_state = -1;\n\n\t\tconst RTLIL::Const &state_table = cell->parameters[ID::STATE_TABLE];\n\t\tconst RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE];\n\n\t\tfor (int i = 0; i < state_num; i++) {\n\t\t\tRTLIL::Const state_code;\n\t\t\tint off_begin = i*state_bits, off_end = off_begin + state_bits;\n\t\t\tstate_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end);\n\t\t\tthis->state_table.push_back(state_code);\n\t\t}\n\n\t\tfor (int i = 0; i < trans_num; i++)\n\t\t{\n\t\t\tauto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2);\n\t\t\tauto off_state_out = off_ctrl_out + num_outputs;\n\t\t\tauto off_ctrl_in = off_state_out + state_num_log2;\n\t\t\tauto off_state_in = off_ctrl_in + num_inputs;\n\t\t\tauto off_end = off_state_in + state_num_log2;\n\n\t\t\tRTLIL::Const state_in, state_out, ctrl_in, ctrl_out;\n\t\t\tctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out);\n\t\t\tstate_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);\n\t\t\tctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);\n\t\t\tstate_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);\n\n\t\t\ttransition_t tr;\n\t\t\ttr.state_in = state_in.as_int();\n\t\t\ttr.state_out = state_out.as_int();\n\t\t\ttr.ctrl_in = ctrl_in;\n\t\t\ttr.ctrl_out = ctrl_out;\n\n\t\t\tif (tr.state_in < 0 || tr.state_in >= state_num)\n\t\t\t\ttr.state_in = -1;\n\t\t\tif (tr.state_out < 0 || tr.state_out >= state_num)\n\t\t\t\ttr.state_out = -1;\n\n\t\t\ttransition_table.push_back(tr);\n\t\t}\n\t}\n\n\tvoid log_info(RTLIL::Cell *cell)\n\t{\n\t\tlog(\"-------------------------------------\\n\");\n\t\tlog(\"\\n\");\n\t\tlog(\" Information on FSM %s (%s):\\n\", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());\n\t\tlog(\"\\n\");\n\t\tlog(\" Number of input signals: %3d\\n\", num_inputs);\n\t\tlog(\" Number of output signals: %3d\\n\", num_outputs);\n\t\tlog(\" Number of state bits: %3d\\n\", state_bits);\n\n\t\tlog(\"\\n\");\n\t\tlog(\" Input signals:\\n\");\n\t\tRTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);\n\t\tfor (int i = 0; i < GetSize(sig_in); i++)\n\t\t\tlog(\" %3d: %s\\n\", i, log_signal(sig_in[i]));\n\n\t\tlog(\"\\n\");\n\t\tlog(\" Output signals:\\n\");\n\t\tRTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);\n\t\tfor (int i = 0; i < GetSize(sig_out); i++)\n\t\t\tlog(\" %3d: %s\\n\", i, log_signal(sig_out[i]));\n\n\t\tlog(\"\\n\");\n\t\tlog(\" State encoding:\\n\");\n\t\tfor (int i = 0; i < GetSize(state_table); i++)\n\t\t\tlog(\" %3d: %10s%s\\n\", i, log_signal(state_table[i], false),\n\t\t\t\t\tint(i) == reset_state ? \" <RESET STATE>\" : \"\");\n\n\t\tlog(\"\\n\");\n\t\tlog(\" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\\n\");\n\t\tfor (int i = 0; i < GetSize(transition_table); i++) {\n\t\t\ttransition_t &tr = transition_table[i];\n\t\t\tlog(\" %5d: %5d %s -> %5d %s\\n\", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));\n\t\t}\n\n\t\tlog(\"\\n\");\n\t\tlog(\"-------------------------------------\\n\");\n\t}\n\n\t// implemented in fsm_opt.cc\n\tstatic void optimize_fsm(RTLIL::Cell *cell, RTLIL::Module *module);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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@@ -375,8 +379,8 @@ export const filesystem = {
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  "cells_map.v": "module \\$_DFFE_PN0P_ (input D, C, R, E, output Q);\n SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));\nendmodule\n\nmodule \\$_DFFE_PN1P_ (input D, C, R, E, output Q);\n SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));\nendmodule\n\nmodule \\$_SDFFCE_PN0P_ (input D, C, R, E, output Q);\n SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1'b1), .ADn(1'b0), .SLn(R), .SD(1'b0), .LAT(1'b0), .Q(Q));\nendmodule\n\nmodule \\$_SDFFCE_PN1P_ (input D, C, R, E, output Q);\n SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1'b1), .ADn(1'b0), .SLn(R), .SD(1'b1), .LAT(1'b0), .Q(Q));\nendmodule\n\nmodule \\$_DLATCH_PN0_ (input D, R, E, output Q);\n SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));\nendmodule\n\nmodule \\$_DLATCH_PN1_ (input D, R, E, output Q);\n SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));\nendmodule\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n parameter WIDTH = 0;\n parameter LUT = 0;\n\n (* force_downto *)\n input [WIDTH-1:0] A;\n output Y;\n\n generate\n if (WIDTH == 1) begin\n CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));\n end else\n if (WIDTH == 2) begin\n CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));\n end else\n if (WIDTH == 3) begin\n CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));\n end else\n if (WIDTH == 4) begin\n CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n end else begin\n wire _TECHMAP_FAIL_ = 1;\n end\n endgenerate\nendmodule\n`endif\n",
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  "cells_sim.v": "// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf\n\nmodule AND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A & B;\nendmodule\n\nmodule AND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A & B & C;\nendmodule\n\nmodule AND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A & B & C & D;\nendmodule\n\nmodule CFG1 (\n\toutput Y,\n\tinput A\n);\n\tparameter [1:0] INIT = 2'h0;\n\tassign Y = INIT >> A;\nendmodule\n\nmodule CFG2 (\n\toutput Y,\n\tinput A,\n\tinput B\n);\n\tparameter [3:0] INIT = 4'h0;\n\tassign Y = INIT >> {B, A};\nendmodule\n\nmodule CFG3 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C\n);\n\tparameter [7:0] INIT = 8'h0;\n\tassign Y = INIT >> {C, B, A};\nendmodule\n\nmodule CFG4 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C,\n\tinput D\n);\n\tparameter [15:0] INIT = 16'h0;\n\tassign Y = INIT >> {D, C, B, A};\nendmodule\n\nmodule BUFF (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule BUFD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT_PRESERVE (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule GCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule RCLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule RGCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule SLE (\n\toutput Q,\n\tinput ADn,\n\tinput ALn,\n\t(* clkbuf_sink *)\n\tinput CLK,\n\tinput D,\n\tinput LAT,\n\tinput SD,\n\tinput EN,\n\tinput SLn\n);\n\treg q_latch, q_ff;\n\n\talways @(posedge CLK, negedge ALn) begin\n\t\tif (!ALn) begin\n\t\t\tq_ff <= !ADn;\n\t\tend else if (EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\talways @* begin\n\t\tif (!ALn) begin\n\t\t\tq_latch <= !ADn;\n\t\tend else if (CLK && EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\tassign Q = LAT ? q_latch : q_ff;\nendmodule\n\nmodule ARI1 (\n\tinput A, B, C, D, FCI,\n\toutput Y, S, FCO\n);\n\tparameter [19:0] INIT = 20'h0;\n\twire [2:0] Fsel = {D, C, B};\n\twire F0 = INIT[Fsel];\n\twire F1 = INIT[8 + Fsel];\n\twire Yout = A ? F1 : F0;\n\tassign Y = Yout;\n\tassign S = FCI ^ Yout;\n\twire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];\n\twire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);\n\tassign FCO = P ? FCI : G;\nendmodule\n\n// module FCEND_BUFF\n// module FCINIT_BUFF\n// module FLASH_FREEZE\n// module OSCILLATOR\n// module SYSCTRL_RESET_STATUS\n// module LIVE_PROBE_FB\n\n(* blackbox *)\nmodule GCLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBIBUF (\n\tinput D,\n\tinput E,\n\tinput EN,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n// module DFN1\n// module DFN1C0\n// module DFN1E1\n// module DFN1E1C0\n// module DFN1E1P0\n// module DFN1P0\n// module DLN1\n// module DLN1C0\n// module DLN1P0\n\nmodule INV (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule INVD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule MX2 (\n\tinput A, B, S,\n\toutput Y\n);\n\tassign Y = S ? B : A;\nendmodule\n\nmodule MX4 (\n\tinput D0, D1, D2, D3, S0, S1,\n\toutput Y\n);\n\tassign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);\nendmodule\n\nmodule NAND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A & B);\nendmodule\n\nmodule NAND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A & B & C);\nendmodule\n\nmodule NAND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A & B & C & D);\nendmodule\n\nmodule NOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A | B);\nendmodule\n\nmodule NOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A | B | C);\nendmodule\n\nmodule NOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A | B | C | D);\nendmodule\n\nmodule OR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A | B;\nendmodule\n\nmodule OR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A | B | C;\nendmodule\n\nmodule OR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A | B | C | D;\nendmodule\n\nmodule XOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A ^ B;\nendmodule\n\nmodule XOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C;\nendmodule\n\nmodule XOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D;\nendmodule\n\nmodule XOR8 (\n\tinput A, B, C, D, E, F, G, H,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;\nendmodule\n\n// module UJTAG\n\nmodule BIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule BIBUF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PADP,\n\t(* iopad_external_pin *)\n\tinout PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule CLKBIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\nmodule CLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule CLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule INBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule INBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule OUTBUF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = D;\nendmodule\n\n(* blackbox *)\nmodule OUTBUF_DIFF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule TRIBUFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\nendmodule\n\n(* blackbox *)\nmodule TRIBUFF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\n// module DDR_IN\n// module DDR_OUT\n// module RAM1K18\n// module RAM64x18\n// module MACC\n\n(* blackbox *)\nmodule SYSRESET (\n\t(* iopad_external_pin *)\n\tinput DEVRST_N,\n\toutput POWER_ON_RESET_N);\nendmodule\n\n\n(* blackbox *)\nmodule XTLOSC (\n\t(* iopad_external_pin *)\n\tinput XTL,\n\toutput CLKOUT);\n\tparameter [1:0] MODE = 2'h3;\n\tparameter real FREQUENCY = 20.0;\nendmodule\n\n(* blackbox *)\nmodule RAM1K18 (\n\tinput [13:0] A_ADDR,\n\tinput [2:0] A_BLK,\n\t(* clkbuf_sink *)\n\tinput\t A_CLK,\n\tinput [17:0] A_DIN,\n\toutput [17:0] A_DOUT,\n\tinput [1:0] A_WEN,\n\tinput [2:0] A_WIDTH,\n\tinput\t A_WMODE,\n\tinput\t A_ARST_N,\n\tinput\t A_DOUT_LAT,\n\tinput\t A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_DOUT_CLK,\n\tinput\t A_DOUT_EN,\n\tinput\t A_DOUT_SRST_N,\n\n\tinput [13:0] B_ADDR,\n\tinput [2:0] B_BLK,\n\t(* clkbuf_sink *)\n\tinput\t B_CLK,\n\tinput [17:0] B_DIN,\n\toutput [17:0] B_DOUT,\n\tinput [1:0] B_WEN,\n\tinput [2:0] B_WIDTH,\n\tinput\t B_WMODE,\n\tinput\t B_ARST_N,\n\tinput\t B_DOUT_LAT,\n\tinput\t B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_DOUT_CLK,\n\tinput\t B_DOUT_EN,\n\tinput\t B_DOUT_SRST_N,\n\n\tinput\t A_EN,\n\tinput\t B_EN,\n\tinput\t SII_LOCK,\n\toutput\t BUSY);\nendmodule\n\n(* blackbox *)\nmodule RAM64x18 (\n\tinput [9:0] A_ADDR,\n\tinput [1:0] A_BLK,\n\tinput [2:0] A_WIDTH,\n\toutput [17:0] A_DOUT,\n\tinput\t A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_DOUT_CLK,\n\tinput\t A_DOUT_EN,\n\tinput\t A_DOUT_LAT,\n\tinput\t A_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_ADDR_CLK,\n\tinput\t A_ADDR_EN,\n\tinput\t A_ADDR_LAT,\n\tinput\t A_ADDR_SRST_N,\n\tinput\t A_ADDR_ARST_N,\n\n\tinput [9:0] B_ADDR,\n\tinput [1:0] B_BLK,\n\tinput [2:0] B_WIDTH,\n\toutput [17:0] B_DOUT,\n\tinput\t B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_DOUT_CLK,\n\tinput\t B_DOUT_EN,\n\tinput\t B_DOUT_LAT,\n\tinput\t B_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_ADDR_CLK,\n\tinput\t B_ADDR_EN,\n\tinput\t B_ADDR_LAT,\n\tinput\t B_ADDR_SRST_N,\n\tinput\t B_ADDR_ARST_N,\n\n\tinput [9:0] C_ADDR,\n\t(* clkbuf_sink *)\n\tinput\t C_CLK,\n\tinput [17:0] C_DIN,\n\tinput\t C_WEN,\n\tinput [1:0] C_BLK,\n\tinput [2:0] C_WIDTH,\n\n\tinput\t A_EN,\n\tinput\t B_EN,\n\tinput\t C_EN,\n\tinput\t SII_LOCK,\n\toutput\t BUSY);\nendmodule\n",
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- "simcells.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell simulation library.\n *\n * This Verilog library contains simple simulation models for the internal\n * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology\n * mapper (see \"techmap.v\" in this directory) and expected by the \"abc\" pass.\n *\n */\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_BUF_ (A, Y)\n//-\n//- A buffer. This cell type is always optimized away by the opt_clean pass.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 0\n//- 1 | 1\n//-\nmodule \\$_BUF_ (A, Y);\ninput A;\noutput Y;\nassign Y = A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOT_ (A, Y)\n//-\n//- An inverter gate.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 1\n//- 1 | 0\n//-\nmodule \\$_NOT_ (A, Y);\ninput A;\noutput Y;\nassign Y = ~A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AND_ (A, B, Y)\n//-\n//- A 2-input AND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_AND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NAND_ (A, B, Y)\n//-\n//- A 2-input NAND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_NAND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A & B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OR_ (A, B, Y)\n//-\n//- A 2-input OR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_OR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOR_ (A, B, Y)\n//-\n//- A 2-input NOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 0\n//-\nmodule \\$_NOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A | B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XOR_ (A, B, Y)\n//-\n//- A 2-input XOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_XOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A ^ B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XNOR_ (A, B, Y)\n//-\n//- A 2-input XNOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_XNOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A ^ B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ANDNOT_ (A, B, Y)\n//-\n//- A 2-input AND-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_ANDNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ORNOT_ (A, B, Y)\n//-\n//- A 2-input OR-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_ORNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX_ (A, B, S, Y)\n//-\n//- A 2-input MUX gate.\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- a - 0 | a\n//- - b 1 | b\n//-\nmodule \\$_MUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? B : A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NMUX_ (A, B, S, Y)\n//-\n//- A 2-input inverting MUX gate.\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- 0 - 0 | 1\n//- 1 - 0 | 0\n//- - 0 1 | 1\n//- - 1 1 | 0\n//-\nmodule \\$_NMUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? !B : !A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX4_ (A, B, C, D, S, T, Y)\n//-\n//- A 4-input MUX gate.\n//-\n//- Truth table: A B C D S T | Y\n//- -------------+---\n//- a - - - 0 0 | a\n//- - b - - 1 0 | b\n//- - - c - 0 1 | c\n//- - - - d 1 1 | d\n//-\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\ninput A, B, C, D, S, T;\noutput Y;\nassign Y = T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y)\n//-\n//- An 8-input MUX gate.\n//-\n//- Truth table: A B C D E F G H S T U | Y\n//- -----------------------+---\n//- a - - - - - - - 0 0 0 | a\n//- - b - - - - - - 1 0 0 | b\n//- - - c - - - - - 0 1 0 | c\n//- - - - d - - - - 1 1 0 | d\n//- - - - - e - - - 0 0 1 | e\n//- - - - - - f - - 1 0 1 | f\n//- - - - - - - g - 0 1 1 | g\n//- - - - - - - - h 1 1 1 | h\n//-\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\ninput A, B, C, D, E, F, G, H, S, T, U;\noutput Y;\nassign Y = U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)\n//-\n//- A 16-input MUX gate.\n//-\n//- Truth table: A B C D E F G H I J K L M N O P S T U V | Y\n//- -----------------------------------------+---\n//- a - - - - - - - - - - - - - - - 0 0 0 0 | a\n//- - b - - - - - - - - - - - - - - 1 0 0 0 | b\n//- - - c - - - - - - - - - - - - - 0 1 0 0 | c\n//- - - - d - - - - - - - - - - - - 1 1 0 0 | d\n//- - - - - e - - - - - - - - - - - 0 0 1 0 | e\n//- - - - - - f - - - - - - - - - - 1 0 1 0 | f\n//- - - - - - - g - - - - - - - - - 0 1 1 0 | g\n//- - - - - - - - h - - - - - - - - 1 1 1 0 | h\n//- - - - - - - - - i - - - - - - - 0 0 0 1 | i\n//- - - - - - - - - - j - - - - - - 1 0 0 1 | j\n//- - - - - - - - - - - k - - - - - 0 1 0 1 | k\n//- - - - - - - - - - - - l - - - - 1 1 0 1 | l\n//- - - - - - - - - - - - - m - - - 0 0 1 1 | m\n//- - - - - - - - - - - - - - n - - 1 0 1 1 | n\n//- - - - - - - - - - - - - - - o - 0 1 1 1 | o\n//- - - - - - - - - - - - - - - - p 1 1 1 1 | p\n//-\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\ninput A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\noutput Y;\nassign Y = V ? U ? T ? (S ? P : O) :\n (S ? N : M) :\n T ? (S ? L : K) :\n (S ? J : I) :\n U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI3_ (A, B, C, Y)\n//-\n//- A 3-input And-Or-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 0\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 0\n//- 1 1 1 | 0\n//-\nmodule \\$_AOI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A & B) | C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI3_ (A, B, C, Y)\n//-\n//- A 3-input Or-And-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 1\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 1\n//- 1 1 1 | 0\n//-\nmodule \\$_OAI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A | B) & C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI4_ (A, B, C, Y)\n//-\n//- A 4-input And-Or-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 0\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 1\n//- 0 1 1 0 | 1\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 1\n//- 1 0 1 0 | 1\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 0\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_AOI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A & B) | (C & D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI4_ (A, B, C, Y)\n//-\n//- A 4-input Or-And-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 1\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 0\n//- 0 1 1 0 | 0\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 0\n//- 1 0 1 0 | 0\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 1\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_OAI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A | B) & (C | D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_TBUF_ (A, E, Y)\n//-\n//- A tri-state buffer.\n//-\n//- Truth table: A E | Y\n//- -----+---\n//- a 1 | a\n//- - 0 | z\n//-\nmodule \\$_TBUF_ (A, E, Y);\ninput A, E;\noutput Y;\nassign Y = E ? A : 1'bz;\nendmodule\n\n// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually,\n// instead edit the templates in gen_ff_types.py and rerun it.\n\n// START AUTOGENERATED CELL TYPES\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NN_ (S, R, Q)\n//-\n//- A set-reset latch with negative polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NP_ (S, R, Q)\n//-\n//- A set-reset latch with negative polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PN_ (S, R, Q)\n//-\n//- A set-reset latch with positive polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PP_ (S, R, Q)\n//-\n//- A set-reset latch with positive polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n`ifdef SIMCELLS_FF\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_FF_ (D, Q)\n//-\n//- A D-type flip-flop that is clocked from the implicit global clock. (This cell\n//- type is usually only used in netlists for formal verification.)\n//-\nmodule \\$_FF_ (D, Q);\ninput D;\noutput reg Q;\nalways @($global_clock) begin\n\tQ <= D;\nend\nendmodule\n`endif\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_N_ (D, C, Q)\n//-\n//- A negative edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d \\ | d\n//- - - | q\n//-\nmodule \\$_DFF_N_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(negedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_P_ (D, C, Q)\n//-\n//- A positive edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d / | d\n//- - - | q\n//-\nmodule \\$_DFF_P_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(posedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN_ (D, C, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP_ (D, C, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN_ (D, C, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP_ (D, C, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NN_ (D, C, L, AD, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NP_ (D, C, L, AD, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PN_ (D, C, L, AD, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PP_ (D, C, L, AD, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNN_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNP_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPN_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPP_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNN_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNP_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPN_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPP_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNN_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNP_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPN_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPP_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNN_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNP_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPN_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPP_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_N_ (E, D, Q)\n//-\n//- A negative enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 0 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_N_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_P_ (E, D, Q)\n//-\n//- A positive enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 1 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_P_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN0_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN1_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP0_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP1_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN0_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN1_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP0_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP1_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNN_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNP_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPN_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPP_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNN_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNP_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPN_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPP_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n",
379
- "simlib.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The Simulation Library.\n *\n * This Verilog library contains simple simulation models for the internal\n * cells ($not, ...) generated by the frontends and used in most passes.\n *\n * This library can be used to verify the internal netlists as generated\n * by the different frontends and passes.\n *\n * Note that memory can only be simulated when all $memrd and $memwr cells\n * have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n * pass is doing).\n *\n */\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $not (A, Y)\n//-\n//- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pos (A, Y)\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $buf (A, Y)\n//-\n//- A simple coarse-grain buffer cell type for the experimental buffered-normalized\n//- mode. Note this cell does't get removed by 'opt_clean' and is not recommended\n//- for general use.\n//-\nmodule \\$buf (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $neg (A, Y)\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $and (A, B, Y)\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $or (A, B, Y)\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xor (A, B, Y)\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xnor (A, B, Y)\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_and (A, Y)\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_or (A, Y)\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xor (A, Y)\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xnor (A, Y)\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_bool (A, Y)\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $shl (A, B, Y)\n//-\n//- A logical shift-left operation. This corresponds to the Verilog '<<' operator.\n//-\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $shr (A, B, Y)\n//-\n//- A logical shift-right operation. This corresponds to the Verilog '>>' operator.\n//-\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sshl (A, B, Y)\n//-\n//- An arithmatic shift-left operation. \n//- This corresponds to the Verilog '<<<' operator.\n//-\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sshr (A, B, Y)\n//-\n//- An arithmatic shift-right operation.\n//- This corresponds to the Verilog '>>>' operator.\n//-\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P; // Propagate\ninput [WIDTH-1:0] G; // Generate\ninput CI; // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $alu (A, B, CI, BI, X, Y, CO)\n//-\n//- Arithmetic logic unit.\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex\n//- cells into this $alu cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A; // Input operand\ninput [B_WIDTH-1:0] B; // Input operand\noutput [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,\n // used in combination with\n // reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y; // Sum\n\ninput CI; // Carry-in (set for $sub)\ninput BI; // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO; // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lt (A, B, Y)\n//-\n//- A less-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<' operator.\n//-\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $le (A, B, Y)\n//-\n//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<=' operator.\n//-\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $eq (A, B, Y)\n//-\n//- An equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '==' operator.\n//-\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $ne (A, B, Y)\n//-\n//- An inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!=' operator.\n//-\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $eqx (A, B, Y)\n//-\n//- An exact equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '===' operator.\n//- Unlike equality comparison that can give 'x' as output, \n//- an exact equality comparison will strictly give '0' or '1' as output.\n//-\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $nex (A, B, Y)\n//-\n//- An exact inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!==' operator.\n//- Unlike inequality comparison that can give 'x' as output, \n//- an exact inequality comparison will strictly give '0' or '1' as output.\n//-\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $ge (A, B, Y)\n//-\n//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '>=' operator.\n//-\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $gt (A, B, Y)\n//-\n//- A greater-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '>' operator.\n//-\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $add (A, B, Y)\n//-\n//- Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator.\n//-\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sub (A, B, Y)\n//-\n//- Subtraction between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '-' operator.\n//-\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mul (A, B, Y)\n//-\n//- Multiplication of inputs 'A' and 'B'.\n//- This corresponds to the Verilog '*' operator.\n//-\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $macc (A, B, Y)\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n// * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $div (A, B, Y)\n//-\n//- Division with truncated result (rounded towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mod (A, B, Y)\n//-\n//- Modulo/remainder of division with truncated result (rounded towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $divfloor (A, B, Y)\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $modfloor (A, B, Y)\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pow (A, B, Y)\n//-\n//- Exponentiation of an input (Y = A ** B). \n//- This corresponds to the Verilog '**' operator.\n//-\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_not (A, Y)\n//-\n//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.\n//-\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_and (A, B, Y)\n//-\n//- A logical AND. This corresponds to the Verilog '&&' operator.\n//-\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_or (A, B, Y)\n//-\n//- A logical OR. This corresponds to the Verilog '||' operator.\n//-\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $concat (A, B, Y)\n//-\n//- Concatenation of inputs into a single output ( Y = {B, A} ).\n//-\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mux (A, B, S, Y)\n//-\n//- Multiplexer i.e selecting between two inputs based on select signal.\n//-\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $demux (A, S, Y)\n//-\n//- Demultiplexer i.e routing single input to several outputs based on select signal.\n//- Unselected outputs are driven to zero.\n//-\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $tribuf (A, EN, Y)\n//-\n//- A tri-state buffer. \n//- This buffer conditionally drives the output with the value of the input\n//- based on the enable signal.\n//-\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <- MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
382
+ "simcells.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell simulation library.\n *\n * This Verilog library contains simple simulation models for the internal\n * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology\n * mapper (see \"techmap.v\" in this directory) and expected by the \"abc\" pass.\n *\n */\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_BUF_ (A, Y)\n//* group comb_simple\n//-\n//- A buffer. This cell type is always optimized away by the opt_clean pass.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 0\n//- 1 | 1\n//-\nmodule \\$_BUF_ (A, Y);\ninput A;\noutput Y;\nassign Y = A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOT_ (A, Y)\n//* group comb_simple\n//-\n//- An inverter gate.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 1\n//- 1 | 0\n//-\nmodule \\$_NOT_ (A, Y);\ninput A;\noutput Y;\nassign Y = ~A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AND_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input AND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_AND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NAND_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input NAND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_NAND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A & B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input OR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_OR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input NOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 0\n//-\nmodule \\$_NOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A | B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input XOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_XOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A ^ B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XNOR_ (A, B, Y)\n//* group comb_simple\n//-\n//- A 2-input XNOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_XNOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A ^ B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ANDNOT_ (A, B, Y)\n//* group comb_combined\n//-\n//- A 2-input AND-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_ANDNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ORNOT_ (A, B, Y)\n//* group comb_combined\n//-\n//- A 2-input OR-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_ORNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX_ (A, B, S, Y)\n//* group comb_simple\n//-\n//- A 2-input MUX gate.\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- a - 0 | a\n//- - b 1 | b\n//-\nmodule \\$_MUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? B : A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NMUX_ (A, B, S, Y)\n//-\n//- A 2-input inverting MUX gate.\n//* group comb_combined\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- 0 - 0 | 1\n//- 1 - 0 | 0\n//- - 0 1 | 1\n//- - 1 1 | 0\n//-\nmodule \\$_NMUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? !B : !A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX4_ (A, B, C, D, S, T, Y)\n//* group comb_combined\n//-\n//- A 4-input MUX gate.\n//-\n//- Truth table: A B C D S T | Y\n//- -------------+---\n//- a - - - 0 0 | a\n//- - b - - 1 0 | b\n//- - - c - 0 1 | c\n//- - - - d 1 1 | d\n//-\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\ninput A, B, C, D, S, T;\noutput Y;\nassign Y = T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y)\n//* group comb_combined\n//-\n//- An 8-input MUX gate.\n//-\n//- Truth table: A B C D E F G H S T U | Y\n//- -----------------------+---\n//- a - - - - - - - 0 0 0 | a\n//- - b - - - - - - 1 0 0 | b\n//- - - c - - - - - 0 1 0 | c\n//- - - - d - - - - 1 1 0 | d\n//- - - - - e - - - 0 0 1 | e\n//- - - - - - f - - 1 0 1 | f\n//- - - - - - - g - 0 1 1 | g\n//- - - - - - - - h 1 1 1 | h\n//-\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\ninput A, B, C, D, E, F, G, H, S, T, U;\noutput Y;\nassign Y = U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)\n//* group comb_combined\n//-\n//- A 16-input MUX gate.\n//-\n//- Truth table: A B C D E F G H I J K L M N O P S T U V | Y\n//- -----------------------------------------+---\n//- a - - - - - - - - - - - - - - - 0 0 0 0 | a\n//- - b - - - - - - - - - - - - - - 1 0 0 0 | b\n//- - - c - - - - - - - - - - - - - 0 1 0 0 | c\n//- - - - d - - - - - - - - - - - - 1 1 0 0 | d\n//- - - - - e - - - - - - - - - - - 0 0 1 0 | e\n//- - - - - - f - - - - - - - - - - 1 0 1 0 | f\n//- - - - - - - g - - - - - - - - - 0 1 1 0 | g\n//- - - - - - - - h - - - - - - - - 1 1 1 0 | h\n//- - - - - - - - - i - - - - - - - 0 0 0 1 | i\n//- - - - - - - - - - j - - - - - - 1 0 0 1 | j\n//- - - - - - - - - - - k - - - - - 0 1 0 1 | k\n//- - - - - - - - - - - - l - - - - 1 1 0 1 | l\n//- - - - - - - - - - - - - m - - - 0 0 1 1 | m\n//- - - - - - - - - - - - - - n - - 1 0 1 1 | n\n//- - - - - - - - - - - - - - - o - 0 1 1 1 | o\n//- - - - - - - - - - - - - - - - p 1 1 1 1 | p\n//-\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\ninput A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\noutput Y;\nassign Y = V ? U ? T ? (S ? P : O) :\n (S ? N : M) :\n T ? (S ? L : K) :\n (S ? J : I) :\n U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI3_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 3-input And-Or-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 0\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 0\n//- 1 1 1 | 0\n//-\nmodule \\$_AOI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A & B) | C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI3_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 3-input Or-And-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 1\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 1\n//- 1 1 1 | 0\n//-\nmodule \\$_OAI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A | B) & C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI4_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 4-input And-Or-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 0\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 1\n//- 0 1 1 0 | 1\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 1\n//- 1 0 1 0 | 1\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 0\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_AOI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A & B) | (C & D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI4_ (A, B, C, Y)\n//* group comb_combined\n//-\n//- A 4-input Or-And-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 1\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 0\n//- 0 1 1 0 | 0\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 0\n//- 1 0 1 0 | 0\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 1\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_OAI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A | B) & (C | D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_TBUF_ (A, E, Y)\n//* group gate_other\n//-\n//- A tri-state buffer.\n//-\n//- Truth table: A E | Y\n//- -----+---\n//- a 1 | a\n//- - 0 | z\n//-\nmodule \\$_TBUF_ (A, E, Y);\ninput A, E;\noutput Y;\nassign Y = E ? A : 1'bz;\nendmodule\n\n// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually,\n// instead edit the templates in gen_ff_types.py and rerun it.\n\n// START AUTOGENERATED CELL TYPES\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NN_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with negative polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NP_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with negative polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PN_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with positive polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PP_ (S, R, Q)\n//* group reg_latch\n//-\n//- A set-reset latch with positive polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n`ifdef SIMCELLS_FF\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_FF_ (D, Q)\n//* group reg_ff\n//-\n//- A D-type flip-flop that is clocked from the implicit global clock. (This cell\n//- type is usually only used in netlists for formal verification.)\n//-\nmodule \\$_FF_ (D, Q);\ninput D;\noutput reg Q;\nalways @($global_clock) begin\n\tQ <= D;\nend\nendmodule\n`endif\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_N_ (D, C, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d \\ | d\n//- - - | q\n//-\nmodule \\$_DFF_N_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(negedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_P_ (D, C, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d / | d\n//- - - | q\n//-\nmodule \\$_DFF_P_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(posedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP_ (D, C, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NN_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NP_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PN_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PP_ (D, C, L, AD, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPN_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPP_ (D, C, L, AD, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPN_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPP_ (C, S, R, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPN_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPP_ (C, S, R, E, D, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP0_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP1_ (D, C, R, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1N_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1P_ (D, C, R, E, Q)\n//* group reg_ff\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_N_ (E, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 0 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_N_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_P_ (E, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 1 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_P_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP0_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP1_ (E, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A negative enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPN_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPP_ (E, S, R, D, Q)\n//* group reg_latch\n//-\n//- A positive enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n",
383
+ "simlib.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The Simulation Library.\n *\n * This Verilog library contains simple simulation models for the internal\n * cells ($not, ...) generated by the frontends and used in most passes.\n *\n * This library can be used to verify the internal netlists as generated\n * by the different frontends and passes.\n *\n * Note that memory can only be simulated when all $memrd and $memwr cells\n * have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n * pass is doing).\n *\n */\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise inverter\n//* group unary\n//- This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pos (A, Y)\n//* group unary\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $buf (A, Y)\n//* group unary\n//-\n//- A simple coarse-grain buffer cell type for the experimental buffered-normalized\n//- mode. Note this cell does't get removed by 'opt_clean' and is not recommended\n//- for general use.\n//-\nmodule \\$buf (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $neg (A, Y)\n//* group unary\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $and (A, B, Y)\n//* group binary\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $or (A, B, Y)\n//* group binary\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xnor (A, B, Y)\n//* group binary\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_and (A, Y)\n//* group unary\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_or (A, Y)\n//* group unary\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xor (A, Y)\n//* group unary\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xnor (A, Y)\n//* group unary\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_bool (A, Y)\n//* group unary\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $shl (A, B, Y)\n//* group binary\n//-\n//- A logical shift-left operation. This corresponds to the Verilog '<<' operator.\n//-\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $shr (A, B, Y)\n//* group binary\n//-\n//- A logical shift-right operation. This corresponds to the Verilog '>>' operator.\n//-\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sshl (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-left operation. \n//- This corresponds to the Verilog '<<<' operator.\n//-\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sshr (A, B, Y)\n//* group binary\n//-\n//- An arithmatic shift-right operation.\n//- This corresponds to the Verilog '>>>' operator.\n//-\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Variable shifter\n//* group binary\n//- Performs a right logical shift if the second operand is positive (or\n//- unsigned), and a left logical shift if it is negative.\n//-\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Indexed part-select\n//* group binary\n//* tags x-output\n//- Same as the `$shift` cell, but fills with 'x'.\n//-\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n//* group arith\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P; // Propagate\ninput [WIDTH-1:0] G; // Generate\ninput CI; // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Arithmetic logic unit\n//* group arith\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- `$add`, `$sub`, `$lt`, `$le`, `$ge`, `$gt`, `$eq`, `$eqx`, `$ne`, `$nex`\n//- cells into this `$alu` cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A; // Input operand\ninput [B_WIDTH-1:0] B; // Input operand\noutput [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,\n // used in combination with\n // reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y; // Sum\n\ninput CI; // Carry-in (set for $sub)\ninput BI; // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO; // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lt (A, B, Y)\n//* group binary\n//-\n//- A less-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<' operator.\n//-\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $le (A, B, Y)\n//* group binary\n//-\n//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<=' operator.\n//-\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $eq (A, B, Y)\n//* group binary\n//-\n//- An equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '==' operator.\n//-\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $ne (A, B, Y)\n//* group binary\n//-\n//- An inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!=' operator.\n//-\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case equality\n//* group binary\n//* tags x-aware\n//- An exact equality comparison between inputs 'A' and 'B'. Also known as the\n//- case equality operator. This corresponds to the Verilog '===' operator.\n//- Unlike equality comparison that can give 'x' as output, an exact equality\n//- comparison will strictly give '0' or '1' as output, even if input includes\n//- 'x' or 'z' values.\n//-\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Case inequality\n//* group binary\n//* tags x-aware\n//- This corresponds to the Verilog '!==' operator.\n//-\n//- Refer to `$eqx` for more details.\n//-\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $ge (A, B, Y)\n//* group binary\n//-\n//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '>=' operator.\n//-\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $gt (A, B, Y)\n//* group binary\n//-\n//- A greater-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '>' operator.\n//-\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $add (A, B, Y)\n//* group binary\n//-\n//- Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator.\n//-\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sub (A, B, Y)\n//* group binary\n//-\n//- Subtraction between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '-' operator.\n//-\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mul (A, B, Y)\n//* group binary\n//-\n//- Multiplication of inputs 'A' and 'B'.\n//- This corresponds to the Verilog '*' operator.\n//-\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $macc (A, B, Y)\n//* group arith\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n// * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Divider\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '/' operator, performing division and\n//- truncating the result (rounding towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Modulo\n//* group binary\n//* tags x-output\n//- This corresponds to the Verilog '%' operator, giving the module (or\n//- remainder) of division and truncating the result (rounding towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $divfloor (A, B, Y)\n//* group binary\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $modfloor (A, B, Y)\n//* group binary\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pow (A, B, Y)\n//* group binary\n//-\n//- Exponentiation of an input (Y = A ** B). \n//- This corresponds to the Verilog '**' operator.\n//-\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_not (A, Y)\n//* group unary\n//-\n//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.\n//-\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_and (A, B, Y)\n//* group binary\n//-\n//- A logical AND. This corresponds to the Verilog '&&' operator.\n//-\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_or (A, B, Y)\n//* group binary\n//-\n//- A logical OR. This corresponds to the Verilog '||' operator.\n//-\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group wire\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $concat (A, B, Y)\n//* group wire\n//-\n//- Concatenation of inputs into a single output ( Y = {B, A} ).\n//-\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mux (A, B, S, Y)\n//-\n//- Multiplexer i.e selecting between two inputs based on select signal.\n//-\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Binary-encoded multiplexer\n//* group mux\n//- Selects between 'slices' of A where each value of S corresponds to a unique\n//- slice.\n//-\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Priority-encoded multiplexer\n//* group mux\n//* tags x-output\n//- Selects between 'slices' of B where each slice corresponds to a single bit\n//- of S. Outputs A when all bits of S are low.\n//-\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $demux (A, S, Y)\n//-\n//- Demultiplexer i.e routing single input to several outputs based on select signal.\n//- Unselected outputs are driven to zero.\n//-\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n//* group logic\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group logic\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mux\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $tribuf (A, EN, Y)\n//-\n//- A tri-state buffer. \n//- This buffer conditionally drives the output with the value of the input\n//- based on the enable signal.\n//-\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group spec\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise case equality\n//* group binary\n//* tags x-aware\n//- A bit-wise version of `$eqx`.\n//-\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* ver 2\n//* title Bit-wise multiplexer\n//* group mux\n//- Equivalent to a series of 1-bit wide `$mux` cells.\n//-\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n//* group formal\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group reg\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n//* group reg\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n//* group fsm\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <- MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n//* group mem\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n//* group mem\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n//* group mem\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n//* group mem\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group formal_tag\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n//* group debug\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
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  "smtmap.v": "(* techmap_celltype = \"$pmux\" *)\nmodule smt_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*(S_WIDTH+1)-1:0] C;\n\n\t\tassign C[WIDTH-1:0] = A;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1)\n\t\t\tassign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i];\n\t\tassign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH];\n\tendgenerate\nendmodule\n",
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  "techmap.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell technology mapper.\n *\n * This Verilog library contains the mapping of internal cells (e.g. $not with\n * variable bit width) to the internal logic cells (such as the single bit $_NOT_\n * gate). Usually this logic network is then mapped to the actual technology\n * using e.g. the \"abc\" pass.\n *\n * Note that this library does not map $mem cells. They must be mapped to logic\n * and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n * which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\n`ifndef NODIV\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n`endif\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
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  "xilinx": {