@yowasp/yosys 0.44.759 → 0.46.789

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Files changed (4) hide show
  1. package/gen/resources-yosys.js +44 -14
  2. package/gen/share/quicklogic/qlf_k6n10f/bram_types_sim.v +1 -1
  3. package/gen/yosys.core.wasm +0 -0
  4. package/package.json +1 -1
package/gen/resources-yosys.js CHANGED
@@ -95,8 +95,8 @@ export const filesystem = {
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  "brams.txt": "ram block $__GOWIN_SP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_DP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_SDP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\tclock posedge;\n\t\tclken;\n\t}\n}\n",
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  "brams_map.v": "`define DEF_FUNCS \\\n\tfunction [255:0] init_slice_x8; \\\n\t\tinput integer idx; \\\n\t\tinteger i; \\\n\t\tfor (i = 0; i < 32; i = i + 1) begin \\\n\t\t\tinit_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \\\n\t\tend \\\n\tendfunction \\\n\tfunction [287:0] init_slice_x9; \\\n\t\tinput integer idx; \\\n\t\tinit_slice_x9 = INIT[idx * 288+:288]; \\\n\tendfunction \\\n\n`define x8_width(width) (width / 9 * 8 + width % 9)\n`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}\n`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}\n`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})\n\n\n`define INIT(func) \\\n\t.INIT_RAM_00(func('h00)), \\\n\t.INIT_RAM_01(func('h01)), \\\n\t.INIT_RAM_02(func('h02)), \\\n\t.INIT_RAM_03(func('h03)), \\\n\t.INIT_RAM_04(func('h04)), \\\n\t.INIT_RAM_05(func('h05)), \\\n\t.INIT_RAM_06(func('h06)), \\\n\t.INIT_RAM_07(func('h07)), \\\n\t.INIT_RAM_08(func('h08)), \\\n\t.INIT_RAM_09(func('h09)), \\\n\t.INIT_RAM_0A(func('h0a)), \\\n\t.INIT_RAM_0B(func('h0b)), \\\n\t.INIT_RAM_0C(func('h0c)), \\\n\t.INIT_RAM_0D(func('h0d)), \\\n\t.INIT_RAM_0E(func('h0e)), \\\n\t.INIT_RAM_0F(func('h0f)), \\\n\t.INIT_RAM_10(func('h10)), \\\n\t.INIT_RAM_11(func('h11)), \\\n\t.INIT_RAM_12(func('h12)), \\\n\t.INIT_RAM_13(func('h13)), \\\n\t.INIT_RAM_14(func('h14)), \\\n\t.INIT_RAM_15(func('h15)), \\\n\t.INIT_RAM_16(func('h16)), \\\n\t.INIT_RAM_17(func('h17)), \\\n\t.INIT_RAM_18(func('h18)), \\\n\t.INIT_RAM_19(func('h19)), \\\n\t.INIT_RAM_1A(func('h1a)), \\\n\t.INIT_RAM_1B(func('h1b)), \\\n\t.INIT_RAM_1C(func('h1c)), \\\n\t.INIT_RAM_1D(func('h1d)), \\\n\t.INIT_RAM_1E(func('h1e)), \\\n\t.INIT_RAM_1F(func('h1f)), \\\n\t.INIT_RAM_20(func('h20)), \\\n\t.INIT_RAM_21(func('h21)), \\\n\t.INIT_RAM_22(func('h22)), \\\n\t.INIT_RAM_23(func('h23)), \\\n\t.INIT_RAM_24(func('h24)), \\\n\t.INIT_RAM_25(func('h25)), \\\n\t.INIT_RAM_26(func('h26)), \\\n\t.INIT_RAM_27(func('h27)), \\\n\t.INIT_RAM_28(func('h28)), \\\n\t.INIT_RAM_29(func('h29)), \\\n\t.INIT_RAM_2A(func('h2a)), \\\n\t.INIT_RAM_2B(func('h2b)), \\\n\t.INIT_RAM_2C(func('h2c)), \\\n\t.INIT_RAM_2D(func('h2d)), \\\n\t.INIT_RAM_2E(func('h2e)), \\\n\t.INIT_RAM_2F(func('h2f)), \\\n\t.INIT_RAM_30(func('h30)), \\\n\t.INIT_RAM_31(func('h31)), \\\n\t.INIT_RAM_32(func('h32)), \\\n\t.INIT_RAM_33(func('h33)), \\\n\t.INIT_RAM_34(func('h34)), \\\n\t.INIT_RAM_35(func('h35)), \\\n\t.INIT_RAM_36(func('h36)), \\\n\t.INIT_RAM_37(func('h37)), \\\n\t.INIT_RAM_38(func('h38)), \\\n\t.INIT_RAM_39(func('h39)), \\\n\t.INIT_RAM_3A(func('h3a)), \\\n\t.INIT_RAM_3B(func('h3b)), \\\n\t.INIT_RAM_3C(func('h3c)), \\\n\t.INIT_RAM_3D(func('h3d)), \\\n\t.INIT_RAM_3E(func('h3e)), \\\n\t.INIT_RAM_3F(func('h3f)),\n\nmodule $__GOWIN_SP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 36;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DO);\n\n\tSP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_A_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_A_RD_DATA = DO;\n\n\tSPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(PORT_A_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_DP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;\n\n`DEF_FUNCS\n\nwire RSTA = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire RSTB = OPTION_RESET_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST;\nwire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\nwire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin\n\n\twire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);\n\twire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);\n\twire [15:0] DOA;\n\twire [15:0] DOB;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DOA);\n\tassign PORT_B_RD_DATA = `x8_rd_data(DOB);\n\n\tDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend else begin\n\n\twire [17:0] DIA = PORT_A_WR_DATA;\n\twire [17:0] DIB = PORT_B_WR_DATA;\n\twire [17:0] DOA;\n\twire [17:0] DOB;\n\n\tassign PORT_A_RD_DATA = DOA;\n\tassign PORT_B_RD_DATA = DOB;\n\n\tDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(PORT_A_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_B_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 18;\nparameter PORT_W_WIDTH = 18;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput PORT_W_WR_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST;\nwire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);\nwire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;\n\ngenerate\n\nif (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_R_RD_DATA = `x8_rd_data(DO);\n\n\tSDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_W_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_R_RD_DATA = DO;\n\n\tSDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(PORT_W_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_R_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n",
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  "cells_map.v": "`default_nettype none\n//All DFF* have INIT, but the hardware is always initialised to the reset\n//value regardless. The parameter is ignored.\n\n// DFFN\t\t\t D Flip-Flop with Negative-Edge Clock\nmodule\t\\$_DFF_N_ (input D, C, output Q);\n\tDFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFF\t\t\t D Flip-Flop\nmodule\t\\$_DFF_P_ (input D, C, output Q);\n\tDFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFE\t\t\t D Flip-Flop with Clock Enable\nmodule\t\\$_DFFE_PP_ (input D, C, E, output Q);\n\tDFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNE\t\t D Flip-Flop with Negative-Edge Clock and Clock Enable\nmodule\t\\$_DFFE_NP_ (input D, C, E, output Q);\n\tDFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFR\t\t\t D Flip-Flop with Synchronous Reset\nmodule\t\\$_SDFF_PP0_ (input D, C, R, output Q);\n\tDFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNR\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Reset\nmodule\t\\$_SDFF_NP0_ (input D, C, R, output Q);\n\tDFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFRE\t\t D Flip-Flop with Clock Enable and Synchronous Reset\nmodule\t\\$_SDFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNRE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset\nmodule\t\\$_SDFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFS\t\t\t D Flip-Flop with Synchronous Set\nmodule\t\\$_SDFF_PP1_ (input D, C, R, output Q);\n\tDFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNS\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Set\nmodule\t\\$_SDFF_NP1_ (input D, C, R, output Q);\n\tDFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFSE\t\t D Flip-Flop with Clock Enable and Synchronous Set\nmodule\t\\$_SDFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNSE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set\nmodule\t\\$_SDFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFP\t\t\t D Flip-Flop with Asynchronous Preset\nmodule\t\\$_DFF_PP1_ (input D, C, R, output Q);\n\tDFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNP\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Preset\nmodule\t\\$_DFF_NP1_ (input D, C, R, output Q);\n\tDFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFC\t\t\t D Flip-Flop with Asynchronous Clear\nmodule\t\\$_DFF_PP0_ (input D, C, R, output Q);\n\tDFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNC\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Clear\nmodule\t\\$_DFF_NP0_ (input D, C, R, output Q);\n\tDFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFPE\t\t D Flip-Flop with Clock Enable and Asynchronous Preset\nmodule\t\\$_DFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNPE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset\nmodule\t\\$_DFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFCE\t\t D Flip-Flop with Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNCE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\t\tLUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]));\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tLUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tLUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tLUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\n\t\tend else\n\t\tif (WIDTH == 5) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));\n\t\t\tMUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 6) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));\n\t\t\tMUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 7) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));\n\t\t\tMUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 8) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));\n\t\t\tMUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));\n\t\tend else begin\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\tend\n\tendgenerate\nendmodule\n",
98
- "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n specify\n (negedge CLK => (Q : D)) = (480, 660);\n $setup(D, negedge CLK, 576);\n endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n input I, OEN;\n output O;\n assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n input I,OEN;\n output O;\n inout IO;\n assign IO = OEN ? 1'bz : I;\n assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox, keep *)\nmodule GSR (input GSRI);\nendmodule\n\n(* blackbox, keep *)\nmodule BANDGAP (input BGEN);\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0 => COUT) = (1010, 1380);\n\t(I1 => COUT) = (1021, 1505);\n\t(I3 => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = I0 & I1;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\"; // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\"; // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nparameter DCS_MODE = \"RISING\";\nendmodule\n\n\n\n",
99
- "cells_xtra.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n \t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule FLASH128K (...);\ninput [31:0] DIN;\ninput [14:0] ADDR;\ninput CS,AE,OE;\ninput PCLK;\ninput PROG, SERA, MASE;\ninput NVSTR;\ninput IFREN;\ninput RESETN;\noutput [31:0] DOUT;\noutput TBIT;\nparameter IDLE = 4'd0,\n READ_S1 = 4'd1,\n READ_S2 = 4'd2,\n PROG_S1 = 4'd3,\n PROG_S2 = 4'd4,\n PROG_S3 = 4'd5,\n PROG_S4 = 4'd6,\n SERA_S1 = 4'd7,\n SERA_S2 = 4'd8,\n SERA_S3 = 4'd9,\n SERA_S4 = 4'd10,\n MASE_S1 = 4'd11,\n MASE_S2 = 4'd12,\n MASE_S3 = 4'd13,\n MASE_S4 = 4'd14;\nendmodule\n\nmodule MCU (...);\nendmodule\n\nmodule USB20_PHY (...);\nparameter DATABUS16_8 = 1'b0;\nparameter ADP_PRBEN = 1'b0;\nparameter TEST_MODE = 5'b00000;\nparameter HSDRV1 = 1'b0; \nparameter HSDRV0 = 1'b0; \nparameter CLK_SEL = 1'b0;\nparameter M = 4'b0000; \nparameter N = 6'b101000; \nparameter C = 2'b01; \nparameter FOC_LOCK = 1'b0;\ninput [15:0] DATAIN;\ninput TXVLD;\ninput TXVLDH;\ninput RESET;\ninput SUSPENDM;\ninput [1:0] XCVRSEL;\ninput TERMSEL;\ninput [1:0] OPMODE;\noutput [15:0] DATAOUT;\noutput TXREADY;\noutput RXACTIVE;\noutput RXVLD;\noutput RXVLDH;\noutput CLK; \noutput RXERROR;\ninout DP;\ninout DM;\noutput [1:0] LINESTATE;\ninput IDPULLUP;\ninput DPPD;\ninput DMPD;\ninput CHARGVBUS;\ninput DISCHARGVBUS;\ninput TXBITSTUFFEN;\ninput TXBITSTUFFENH;\ninput TXENN;\ninput TXDAT;\ninput TXSE0;\ninput FSLSSERIAL;\noutput HOSTDIS;\noutput IDDIG;\noutput ADPPRB;\noutput ADPSNS;\noutput SESSVLD;\noutput VBUSVLD;\noutput RXDP;\noutput RXDM;\noutput RXRCV;\noutput LBKERR;\noutput CLKRDY;\ninput INTCLK;\ninout ID;\ninout VBUS;\ninout REXT;\ninput XIN;\ninout XOUT;\ninput\tTEST;\noutput\tCLK480PAD;\ninput SCANCLK; \ninput SCANEN; \ninput SCANMODE; \ninput TRESETN; \ninput SCANIN1; \noutput SCANOUT1; \ninput SCANIN2; \noutput SCANOUT2; \ninput SCANIN3; \noutput SCANOUT3; \ninput SCANIN4; \noutput SCANOUT4; \ninput SCANIN5; \noutput SCANOUT5; \ninput SCANIN6; \noutput SCANOUT6; \nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule EMCU (...);\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK; \ninput HS_8BIT_MODE; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput LALIGN_EN; \ninput WALIGN_BY; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN; \ninput HSRX_STOP; \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON; \ninput RESET; \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH; \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ; \ninput DRST_N; \ninput ONE_BYTE0_MATCH; \ninput WORD_LENDIAN; \ninput [2:0] FIFO_RD_STD; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b1;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n",
98
+ "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n specify\n (negedge CLK => (Q : D)) = (480, 660);\n $setup(D, negedge CLK, 576);\n endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n input I, OEN;\n output O;\n assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n input I,OEN;\n output O;\n inout IO;\n assign IO = OEN ? 1'bz : I;\n assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET) ;\n parameter GSREN = \"\";\n parameter LSREN = \"\";\n parameter HWL = \"\";\n parameter TCLK_SOURCE = \"\";\n parameter TXCLK_POL = \"\";\n\n input D0, D1, D2, D3;\n input TX0, TX1;\n input PCLK, FCLK, TCLK, RESET;\n output Q0, Q1;\n\n parameter ID = \"\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR,\nRADDR, CALIB, PCLK, FCLK, ICLK, RESET) ;\nparameter GSREN = \"\";\nparameter LSREN = \"\";\n\ninput D, ICLK, FCLK, PCLK;\ninput [2:0] WADDR;\ninput [2:0] RADDR;\ninput CALIB, RESET;\n\noutput Q0,Q1,Q2,Q3;\n\nparameter ID = \"\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG,\nWFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR,\nHOLD, RCLKSEL, PCLK, FCLK, RESET) ;\n input DQSIN,PCLK,FCLK,RESET;\n input [3:0] READ;\n input [2:0] RCLKSEL;\n input [7:0] DLLSTEP;\n input [7:0] WSTEP;\n input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;\n\n output DQSR90, DQSW0, DQSW270;\n output [2:0] RPOINT, WPOINT;\n output RVALID,RBURST, RFLAG, WFLAG;\n\n parameter FIFO_MODE_SEL = \"\";\n parameter RD_PNTR = \"\";\n parameter DQS_MODE = \"\";\n parameter HWL = \"\";\n parameter GSREN = \"\";\n parameter ID = \"\";\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox, keep *)\nmodule GSR (input GSRI);\nendmodule\n\n(* blackbox, keep *)\nmodule BANDGAP (input BGEN);\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0 => COUT) = (1010, 1380);\n\t(I1 => COUT) = (1021, 1505);\n\t(I3 => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = I0 & I1;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\"; // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\"; // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nparameter DCS_MODE = \"RISING\";\nendmodule\n\n(* blackbox *)\nmodule EMCU (\n input FCLK,\n input PORESETN,\n input SYSRESETN,\n input RTCSRCCLK,\n output [15:0] IOEXPOUTPUTO,\n output [15:0] IOEXPOUTPUTENO,\n input [15:0] IOEXPINPUTI,\n output UART0TXDO,\n output UART1TXDO,\n output UART0BAUDTICK,\n output UART1BAUDTICK,\n input UART0RXDI,\n input UART1RXDI,\n output INTMONITOR,\n output MTXHRESETN,\n output [12:0] SRAM0ADDR,\n output [3:0] SRAM0WREN,\n output [31:0] SRAM0WDATA,\n output SRAM0CS,\n input [31:0] SRAM0RDATA,\n output TARGFLASH0HSEL,\n output [28:0] TARGFLASH0HADDR,\n output [1:0] TARGFLASH0HTRANS,\n output [2:0] TARGFLASH0HSIZE,\n output [2:0] TARGFLASH0HBURST,\n output TARGFLASH0HREADYMUX,\n input [31:0] TARGFLASH0HRDATA,\n input [2:0] TARGFLASH0HRUSER,\n input TARGFLASH0HRESP,\n input TARGFLASH0EXRESP,\n input TARGFLASH0HREADYOUT,\n output TARGEXP0HSEL,\n output [31:0] TARGEXP0HADDR,\n output [1:0] TARGEXP0HTRANS,\n output TARGEXP0HWRITE,\n output [2:0] TARGEXP0HSIZE,\n output [2:0] TARGEXP0HBURST,\n output [3:0] TARGEXP0HPROT,\n output [1:0] TARGEXP0MEMATTR,\n output TARGEXP0EXREQ,\n output [3:0] TARGEXP0HMASTER,\n output [31:0] TARGEXP0HWDATA,\n output TARGEXP0HMASTLOCK,\n output TARGEXP0HREADYMUX,\n output TARGEXP0HAUSER,\n output [3:0] TARGEXP0HWUSER,\n input [31:0] TARGEXP0HRDATA,\n input TARGEXP0HREADYOUT,\n input TARGEXP0HRESP,\n input TARGEXP0EXRESP,\n input [2:0] TARGEXP0HRUSER,\n output [31:0] INITEXP0HRDATA,\n output INITEXP0HREADY,\n output INITEXP0HRESP,\n output INITEXP0EXRESP,\n output [2:0] INITEXP0HRUSER,\n input INITEXP0HSEL,\n input [31:0] INITEXP0HADDR,\n input [1:0] INITEXP0HTRANS,\n input INITEXP0HWRITE,\n input [2:0] INITEXP0HSIZE,\n input [2:0] INITEXP0HBURST,\n input [3:0] INITEXP0HPROT,\n input [1:0] INITEXP0MEMATTR,\n input INITEXP0EXREQ,\n input [3:0] INITEXP0HMASTER,\n input [31:0] INITEXP0HWDATA,\n input INITEXP0HMASTLOCK,\n input INITEXP0HAUSER,\n input [3:0] INITEXP0HWUSER,\n output [3:0] APBTARGEXP2PSTRB,\n output [2:0] APBTARGEXP2PPROT,\n output APBTARGEXP2PSEL,\n output APBTARGEXP2PENABLE,\n output [11:0] APBTARGEXP2PADDR,\n output APBTARGEXP2PWRITE,\n output [31:0] APBTARGEXP2PWDATA,\n input [31:0] APBTARGEXP2PRDATA,\n input APBTARGEXP2PREADY,\n input APBTARGEXP2PSLVERR,\n input [3:0] MTXREMAP,\n output DAPTDO,\n output DAPJTAGNSW,\n output DAPNTDOEN,\n input DAPSWDITMS,\n input DAPTDI,\n input DAPNTRST,\n input DAPSWCLKTCK,\n output [3:0] TPIUTRACEDATA,\n output TPIUTRACECLK,\n input [4:0] GPINT,\n input FLASHERR,\n input FLASHINT\n\n );\nendmodule\n\n\n",
99
+ "cells_xtra.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n \t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule FLASH128K (...);\ninput [31:0] DIN;\ninput [14:0] ADDR;\ninput CS,AE,OE;\ninput PCLK;\ninput PROG, SERA, MASE;\ninput NVSTR;\ninput IFREN;\ninput RESETN;\noutput [31:0] DOUT;\noutput TBIT;\nparameter IDLE = 4'd0,\n READ_S1 = 4'd1,\n READ_S2 = 4'd2,\n PROG_S1 = 4'd3,\n PROG_S2 = 4'd4,\n PROG_S3 = 4'd5,\n PROG_S4 = 4'd6,\n SERA_S1 = 4'd7,\n SERA_S2 = 4'd8,\n SERA_S3 = 4'd9,\n SERA_S4 = 4'd10,\n MASE_S1 = 4'd11,\n MASE_S2 = 4'd12,\n MASE_S3 = 4'd13,\n MASE_S4 = 4'd14;\nendmodule\n\nmodule MCU (...);\nendmodule\n\nmodule USB20_PHY (...);\nparameter DATABUS16_8 = 1'b0;\nparameter ADP_PRBEN = 1'b0;\nparameter TEST_MODE = 5'b00000;\nparameter HSDRV1 = 1'b0; \nparameter HSDRV0 = 1'b0; \nparameter CLK_SEL = 1'b0;\nparameter M = 4'b0000; \nparameter N = 6'b101000; \nparameter C = 2'b01; \nparameter FOC_LOCK = 1'b0;\ninput [15:0] DATAIN;\ninput TXVLD;\ninput TXVLDH;\ninput RESET;\ninput SUSPENDM;\ninput [1:0] XCVRSEL;\ninput TERMSEL;\ninput [1:0] OPMODE;\noutput [15:0] DATAOUT;\noutput TXREADY;\noutput RXACTIVE;\noutput RXVLD;\noutput RXVLDH;\noutput CLK; \noutput RXERROR;\ninout DP;\ninout DM;\noutput [1:0] LINESTATE;\ninput IDPULLUP;\ninput DPPD;\ninput DMPD;\ninput CHARGVBUS;\ninput DISCHARGVBUS;\ninput TXBITSTUFFEN;\ninput TXBITSTUFFENH;\ninput TXENN;\ninput TXDAT;\ninput TXSE0;\ninput FSLSSERIAL;\noutput HOSTDIS;\noutput IDDIG;\noutput ADPPRB;\noutput ADPSNS;\noutput SESSVLD;\noutput VBUSVLD;\noutput RXDP;\noutput RXDM;\noutput RXRCV;\noutput LBKERR;\noutput CLKRDY;\ninput INTCLK;\ninout ID;\ninout VBUS;\ninout REXT;\ninput XIN;\ninout XOUT;\ninput\tTEST;\noutput\tCLK480PAD;\ninput SCANCLK; \ninput SCANEN; \ninput SCANMODE; \ninput TRESETN; \ninput SCANIN1; \noutput SCANOUT1; \ninput SCANIN2; \noutput SCANOUT2; \ninput SCANIN3; \noutput SCANOUT3; \ninput SCANIN4; \noutput SCANOUT4; \ninput SCANIN5; \noutput SCANOUT5; \ninput SCANIN6; \noutput SCANOUT6; \nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK; \ninput HS_8BIT_MODE; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput LALIGN_EN; \ninput WALIGN_BY; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN; \ninput HSRX_STOP; \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON; \ninput RESET; \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH; \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ; \ninput DRST_N; \ninput ONE_BYTE0_MATCH; \ninput WORD_LENDIAN; \ninput [2:0] FIFO_RD_STD; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b1;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n",
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  "lutrams.txt": "ram distributed $__GOWIN_LUTRAM_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\twidthscale;\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
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  "lutrams_map.v": "module $__GOWIN_LUTRAM_(...);\n\nparameter INIT = 64'bx;\nparameter BITS_USED = 0;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput PORT_W_WR_EN;\ninput [3:0] PORT_W_WR_DATA;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nfunction [15:0] init_slice;\ninput integer idx;\ninteger i;\nfor (i = 0; i < 16; i = i + 1)\n\tinit_slice[i] = INIT[4*i+idx];\nendfunction\n\ngenerate\n\ncasez(BITS_USED)\n4'b000z:\nRAM16SDP1 #(\n\t.INIT_0(init_slice(0)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[0]),\n\t.DO(PORT_R_RD_DATA[0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n4'b00zz:\nRAM16SDP2 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[1:0]),\n\t.DO(PORT_R_RD_DATA[1:0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\ndefault:\nRAM16SDP4 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n\t.INIT_2(init_slice(2)),\n\t.INIT_3(init_slice(3)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.DO(PORT_R_RD_DATA),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\nendcase\n\nendgenerate\n\nendmodule\n",
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  },
@@ -147,7 +147,7 @@ export const filesystem = {
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  },
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  "frontends": {
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  "ast": {
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- "ast.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The AST frontend library is not a frontend on its own but provides an\n * abstract syntax tree (AST) abstraction for the open source Verilog frontend\n * at frontends/verilog.\n *\n */\n\n#ifndef AST_H\n#define AST_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/fmt.h\"\n#include <stdint.h>\n#include <set>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace AST\n{\n\t// all node types, type2str() must be extended\n\t// whenever a new node type is added here\n\tenum AstNodeType\n\t{\n\t\tAST_NONE,\n\t\tAST_DESIGN,\n\t\tAST_MODULE,\n\t\tAST_TASK,\n\t\tAST_FUNCTION,\n\t\tAST_DPI_FUNCTION,\n\n\t\tAST_WIRE,\n\t\tAST_MEMORY,\n\t\tAST_AUTOWIRE,\n\t\tAST_PARAMETER,\n\t\tAST_LOCALPARAM,\n\t\tAST_DEFPARAM,\n\t\tAST_PARASET,\n\t\tAST_ARGUMENT,\n\t\tAST_RANGE,\n\t\tAST_MULTIRANGE,\n\t\tAST_CONSTANT,\n\t\tAST_REALVALUE,\n\t\tAST_CELLTYPE,\n\t\tAST_IDENTIFIER,\n\t\tAST_PREFIX,\n\t\tAST_ASSERT,\n\t\tAST_ASSUME,\n\t\tAST_LIVE,\n\t\tAST_FAIR,\n\t\tAST_COVER,\n\t\tAST_ENUM,\n\t\tAST_ENUM_ITEM,\n\n\t\tAST_FCALL,\n\t\tAST_TO_BITS,\n\t\tAST_TO_SIGNED,\n\t\tAST_TO_UNSIGNED,\n\t\tAST_SELFSZ,\n\t\tAST_CAST_SIZE,\n\t\tAST_CONCAT,\n\t\tAST_REPLICATE,\n\t\tAST_BIT_NOT,\n\t\tAST_BIT_AND,\n\t\tAST_BIT_OR,\n\t\tAST_BIT_XOR,\n\t\tAST_BIT_XNOR,\n\t\tAST_REDUCE_AND,\n\t\tAST_REDUCE_OR,\n\t\tAST_REDUCE_XOR,\n\t\tAST_REDUCE_XNOR,\n\t\tAST_REDUCE_BOOL,\n\t\tAST_SHIFT_LEFT,\n\t\tAST_SHIFT_RIGHT,\n\t\tAST_SHIFT_SLEFT,\n\t\tAST_SHIFT_SRIGHT,\n\t\tAST_SHIFTX,\n\t\tAST_SHIFT,\n\t\tAST_LT,\n\t\tAST_LE,\n\t\tAST_EQ,\n\t\tAST_NE,\n\t\tAST_EQX,\n\t\tAST_NEX,\n\t\tAST_GE,\n\t\tAST_GT,\n\t\tAST_ADD,\n\t\tAST_SUB,\n\t\tAST_MUL,\n\t\tAST_DIV,\n\t\tAST_MOD,\n\t\tAST_POW,\n\t\tAST_POS,\n\t\tAST_NEG,\n\t\tAST_LOGIC_AND,\n\t\tAST_LOGIC_OR,\n\t\tAST_LOGIC_NOT,\n\t\tAST_TERNARY,\n\t\tAST_MEMRD,\n\t\tAST_MEMWR,\n\t\tAST_MEMINIT,\n\n\t\tAST_TCALL,\n\t\tAST_ASSIGN,\n\t\tAST_CELL,\n\t\tAST_PRIMITIVE,\n\t\tAST_CELLARRAY,\n\t\tAST_ALWAYS,\n\t\tAST_INITIAL,\n\t\tAST_BLOCK,\n\t\tAST_ASSIGN_EQ,\n\t\tAST_ASSIGN_LE,\n\t\tAST_CASE,\n\t\tAST_COND,\n\t\tAST_CONDX,\n\t\tAST_CONDZ,\n\t\tAST_DEFAULT,\n\t\tAST_FOR,\n\t\tAST_WHILE,\n\t\tAST_REPEAT,\n\n\t\tAST_GENVAR,\n\t\tAST_GENFOR,\n\t\tAST_GENIF,\n\t\tAST_GENCASE,\n\t\tAST_GENBLOCK,\n\t\tAST_TECALL,\n\n\t\tAST_POSEDGE,\n\t\tAST_NEGEDGE,\n\t\tAST_EDGE,\n\n\t\tAST_INTERFACE,\n\t\tAST_INTERFACEPORT,\n\t\tAST_INTERFACEPORTTYPE,\n\t\tAST_MODPORT,\n\t\tAST_MODPORTMEMBER,\n\t\tAST_PACKAGE,\n\n\t\tAST_WIRETYPE,\n\t\tAST_TYPEDEF,\n\t\tAST_STRUCT,\n\t\tAST_UNION,\n\t\tAST_STRUCT_ITEM,\n\t\tAST_BIND\n\t};\n\n\tstruct AstSrcLocType {\n\t\tunsigned int first_line, last_line;\n\t\tunsigned int first_column, last_column;\n\t\tAstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}\n\t\tAstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}\n\t};\n\n\t// convert an node type to a string (e.g. for debug output)\n\tstd::string type2str(AstNodeType type);\n\n\t// The AST is built using instances of this struct\n\tstruct AstNode\n\t{\n\t\t// for dict<> and pool<>\n\t\tunsigned int hashidx_;\n\t\tunsigned int hash() const { return hashidx_; }\n\n\t\t// this nodes type\n\t\tAstNodeType type;\n\n\t\t// the list of child nodes for this node\n\t\tstd::vector<AstNode*> children;\n\n\t\t// the list of attributes assigned to this node\n\t\tstd::map<RTLIL::IdString, AstNode*> attributes;\n\t\tbool get_bool_attribute(RTLIL::IdString id);\n\n\t\t// node content - most of it is unused in most node types\n\t\tstd::string str;\n\t\tstd::vector<RTLIL::State> bits;\n\t\tbool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized, is_custom_type;\n\t\tint port_id, range_left, range_right;\n\t\tuint32_t integer;\n\t\tdouble realvalue;\n\t\t// set for IDs typed to an enumeration, not used\n\t\tbool is_enum;\n\n\t\t// Declared range for array dimension.\n\t\tstruct dimension_t {\n\t\t\tint range_right; // lsb in [msb:lsb]\n\t\t\tint range_width; // msb - lsb + 1\n\t\t\tbool range_swapped; // if the declared msb < lsb, msb and lsb above are swapped\n\t\t};\n\t\t// Packed and unpacked dimensions for arrays.\n\t\t// Unpacked dimensions go first, to follow the order of indexing.\n\t\tstd::vector<dimension_t> dimensions;\n\t\t// Number of unpacked dimensions.\n\t\tint unpacked_dimensions;\n\n\t\t// this is set by simplify and used during RTLIL generation\n\t\tAstNode *id2ast;\n\n\t\t// this is used by simplify to detect if basic analysis has been performed already on the node\n\t\tbool basic_prep;\n\n\t\t// this is used for ID references in RHS expressions that should use the \"new\" value for non-blocking assignments\n\t\tbool lookahead;\n\n\t\t// this is the original sourcecode location that resulted in this AST node\n\t\t// it is automatically set by the constructor using AST::current_filename and\n\t\t// the AST::get_line_num() callback function.\n\t\tstd::string filename;\n\t\tAstSrcLocType location;\n\n\t\t// are we embedded in an lvalue, param?\n\t\t// (see fixup_hierarchy_flags)\n\t\tbool in_lvalue;\n\t\tbool in_param;\n\t\tbool in_lvalue_from_above;\n\t\tbool in_param_from_above;\n\n\t\t// creating and deleting nodes\n\t\tAstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr);\n\t\tAstNode *clone() const;\n\t\tvoid cloneInto(AstNode *other) const;\n\t\tvoid delete_children();\n\t\t~AstNode();\n\n\t\tenum mem2reg_flags\n\t\t{\n\t\t\t/* status flags */\n\t\t\tMEM2REG_FL_ALL = 0x00000001,\n\t\t\tMEM2REG_FL_ASYNC = 0x00000002,\n\t\t\tMEM2REG_FL_INIT = 0x00000004,\n\n\t\t\t/* candidate flags */\n\t\t\tMEM2REG_FL_FORCED = 0x00000100,\n\t\t\tMEM2REG_FL_SET_INIT = 0x00000200,\n\t\t\tMEM2REG_FL_SET_ELSE = 0x00000400,\n\t\t\tMEM2REG_FL_SET_ASYNC = 0x00000800,\n\t\t\tMEM2REG_FL_EQ2 = 0x00001000,\n\t\t\tMEM2REG_FL_CMPLX_LHS = 0x00002000,\n\t\t\tMEM2REG_FL_CONST_LHS = 0x00004000,\n\t\t\tMEM2REG_FL_VAR_LHS = 0x00008000,\n\n\t\t\t/* proc flags */\n\t\t\tMEM2REG_FL_EQ1 = 0x01000000,\n\t\t};\n\n\t\t// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.\n\t\t// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()\n\t\tbool simplify(bool const_fold, int stage, int width_hint, bool sign_hint);\n\t\tvoid replace_result_wire_name_in_function(const std::string &from, const std::string &to);\n\t\tAstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);\n\t\tvoid expand_genblock(const std::string &prefix);\n\t\tvoid label_genblks(std::set<std::string>& existing, int &counter);\n\t\tvoid mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,\n\t\t\t\tdict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);\n\t\tbool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);\n\t\tbool mem2reg_check(pool<AstNode*> &mem2reg_set);\n\t\tvoid mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);\n\t\tvoid meminfo(int &mem_width, int &mem_size, int &addr_bits);\n\t\tbool detect_latch(const std::string &var);\n\t\tconst RTLIL::Module* lookup_cell_module();\n\n\t\t// additional functionality for evaluating constant functions\n\t\tstruct varinfo_t {\n\t\t\tRTLIL::Const val;\n\t\t\tint offset;\n\t\t\tbool range_swapped;\n\t\t\tbool is_signed;\n\t\t\tAstNode *arg = nullptr;\n\t\t\tbool explicitly_sized;\n\t\t};\n\t\tbool has_const_only_constructs();\n\t\tbool replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall, bool must_succeed);\n\t\tAstNode *eval_const_function(AstNode *fcall, bool must_succeed);\n\t\tbool is_simple_const_expr();\n\n\t\t// helper for parsing format strings\n\t\tFmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0, bool may_fail = false);\n\n\t\tbool is_recursive_function() const;\n\t\tstd::pair<AstNode*, AstNode*> get_tern_choice();\n\n\t\t// create a human-readable text representation of the AST (for debugging)\n\t\tvoid dumpAst(FILE *f, std::string indent) const;\n\t\tvoid dumpVlog(FILE *f, std::string indent) const;\n\n\t\t// Generate RTLIL for a bind construct\n\t\tstd::vector<RTLIL::Binding *> genBindings() const;\n\n\t\t// used by genRTLIL() for detecting expression width and sign\n\t\tvoid detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\t\tvoid detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\n\t\t// create RTLIL code for this AST node\n\t\t// for expressions the resulting signal vector is returned\n\t\t// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module\n\t\tRTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);\n\t\tRTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);\n\n\t\t// compare AST nodes\n\t\tbool operator==(const AstNode &other) const;\n\t\tbool operator!=(const AstNode &other) const;\n\t\tbool contains(const AstNode *other) const;\n\n\t\t// helper functions for creating AST nodes for constants\n\t\tstatic AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);\n\t\tstatic AstNode *mkconst_str(const std::vector<RTLIL::State> &v);\n\t\tstatic AstNode *mkconst_str(const std::string &str);\n\n\t\t// helper function to create an AST node for a temporary register\n\t\tAstNode *mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed);\n\n\t\t// helper function for creating sign-extended const objects\n\t\tRTLIL::Const bitsAsConst(int width, bool is_signed);\n\t\tRTLIL::Const bitsAsConst(int width = -1);\n\t\tRTLIL::Const bitsAsUnsizedConst(int width);\n\t\tRTLIL::Const asAttrConst() const;\n\t\tRTLIL::Const asParaConst() const;\n\t\tuint64_t asInt(bool is_signed);\n\t\tbool bits_only_01() const;\n\t\tbool asBool() const;\n\n\t\t// helper functions for real valued const eval\n\t\tint isConst() const; // return '1' for AST_CONSTANT and '2' for AST_REALVALUE\n\t\tdouble asReal(bool is_signed);\n\t\tRTLIL::Const realAsConst(int width);\n\n\t\t// helpers for enum\n\t\tvoid allocateDefaultEnumValues();\n\t\tvoid annotateTypedEnums(AstNode *template_node);\n\n\t\t// helpers for locations\n\t\tstd::string loc_string() const;\n\n\t\t// Helper for looking up identifiers which are prefixed with the current module name\n\t\tstd::string try_pop_module_prefix() const;\n\n\t\t// helper to clone the node with some of its subexpressions replaced with zero (this is used\n\t\t// to evaluate widths of dynamic ranges)\n\t\tAstNode *clone_at_zero();\n\n\t\tvoid set_attribute(RTLIL::IdString key, AstNode *node)\n\t\t{\n\t\t\tattributes[key] = node;\n\t\t\tnode->set_in_param_flag(true);\n\t\t}\n\n\t\t// helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag\n\t\t// can be overridden based on the intrinsic properties of this node, i.e. based on its type)\n\t\tvoid set_in_lvalue_flag(bool flag, bool no_descend = false);\n\t\tvoid set_in_param_flag(bool flag, bool no_descend = false);\n\n\t\t// fix up the hierarchy flags (in_lvalue/in_param) of this node and its children\n\t\t//\n\t\t// to keep the flags in sync, fixup_hierarchy_flags(true) needs to be called once after\n\t\t// parsing the AST to walk the full tree, then plain fixup_hierarchy_flags() performs\n\t\t// localized fixups after modifying children/attributes of a particular node\n\t\tvoid fixup_hierarchy_flags(bool force_descend = false);\n\n\t\t// helpers for indexing\n\t\tAstNode *make_index_range(AstNode *node, bool unpacked_range = false);\n\t\tAstNode *get_struct_member() const;\n\n\t\t// helper to print errors from simplify/genrtlil code\n\t\t[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));\n\t};\n\n\t// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code\n\tvoid process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,\n\t\t\tbool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire);\n\n\t// parametric modules are supported directly by the AST library\n\t// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions\n\tstruct AstModule : RTLIL::Module {\n\t\tAstNode *ast;\n\t\tbool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;\n\t\t~AstModule() override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;\n\t\tstd::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);\n\t\tvoid expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;\n\t\tbool reprocess_if_necessary(RTLIL::Design *design) override;\n\t\tRTLIL::Module *clone() const override;\n\t\tvoid loadconfig() const;\n\t};\n\n\t// this must be set by the language frontend before parsing the sources\n\t// the AstNode constructor then uses current_filename and get_line_num()\n\t// to initialize the filename and linenum properties of new nodes\n\textern std::string current_filename;\n\textern void (*set_line_num)(int);\n\textern int (*get_line_num)();\n\n\t// set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive\n\t// to control the filename and linenum properties of new nodes not generated by a frontend parser)\n\tvoid use_internal_line_num();\n\n\t// call a DPI function\n\tAstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);\n\n\t// Helper functions related to handling SystemVerilog interfaces\n\tstd::pair<std::string,std::string> split_modport_from_type(std::string name_type);\n\tAstNode * find_modport(AstNode *intf, std::string name);\n\tvoid explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);\n\n\t// Helper for setting the src attribute.\n\tvoid set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);\n\n\t// generate standard $paramod... derived module name; parameters should be\n\t// in the order they are declared in the instantiated module\n\tstd::string derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters);\n\n\t// used to provide simplify() access to the current design for looking up\n\t// modules, ports, wires, etc.\n\tvoid set_simplify_design_context(const RTLIL::Design *design);\n}\n\nnamespace AST_INTERNAL\n{\n\t// internal state variables\n\textern bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;\n\textern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_pwires, flag_autowire;\n\textern AST::AstNode *current_ast, *current_ast_mod;\n\textern std::map<std::string, AST::AstNode*> current_scope;\n\textern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;\n\textern RTLIL::SigSpec ignoreThisSignalsInInitial;\n\textern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;\n\textern RTLIL::Module *current_module;\n\textern bool current_always_clocked;\n\textern dict<std::string, int> current_memwr_count;\n\textern dict<std::string, pool<int>> current_memwr_visible;\n\tstruct LookaheadRewriter;\n\tstruct ProcessGenerator;\n\n\t// Create and add a new AstModule from new_ast, then use it to replace\n\t// old_module in design, renaming old_module to move it out of the way.\n\t// Return the new module.\n\t//\n\t// If original_ast is not null, it will be used as the AST node for the\n\t// new module. Otherwise, new_ast will be used.\n\tRTLIL::Module *\n\tprocess_and_replace_module(RTLIL::Design *design,\n\t RTLIL::Module *old_module,\n\t AST::AstNode *new_ast,\n\t AST::AstNode *original_ast = nullptr);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
150
+ "ast.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The AST frontend library is not a frontend on its own but provides an\n * abstract syntax tree (AST) abstraction for the open source Verilog frontend\n * at frontends/verilog.\n *\n */\n\n#ifndef AST_H\n#define AST_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/fmt.h\"\n#include <stdint.h>\n#include <set>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace AST\n{\n\t// all node types, type2str() must be extended\n\t// whenever a new node type is added here\n\tenum AstNodeType\n\t{\n\t\tAST_NONE,\n\t\tAST_DESIGN,\n\t\tAST_MODULE,\n\t\tAST_TASK,\n\t\tAST_FUNCTION,\n\t\tAST_DPI_FUNCTION,\n\n\t\tAST_WIRE,\n\t\tAST_MEMORY,\n\t\tAST_AUTOWIRE,\n\t\tAST_PARAMETER,\n\t\tAST_LOCALPARAM,\n\t\tAST_DEFPARAM,\n\t\tAST_PARASET,\n\t\tAST_ARGUMENT,\n\t\tAST_RANGE,\n\t\tAST_MULTIRANGE,\n\t\tAST_CONSTANT,\n\t\tAST_REALVALUE,\n\t\tAST_CELLTYPE,\n\t\tAST_IDENTIFIER,\n\t\tAST_PREFIX,\n\t\tAST_ASSERT,\n\t\tAST_ASSUME,\n\t\tAST_LIVE,\n\t\tAST_FAIR,\n\t\tAST_COVER,\n\t\tAST_ENUM,\n\t\tAST_ENUM_ITEM,\n\n\t\tAST_FCALL,\n\t\tAST_TO_BITS,\n\t\tAST_TO_SIGNED,\n\t\tAST_TO_UNSIGNED,\n\t\tAST_SELFSZ,\n\t\tAST_CAST_SIZE,\n\t\tAST_CONCAT,\n\t\tAST_REPLICATE,\n\t\tAST_BIT_NOT,\n\t\tAST_BIT_AND,\n\t\tAST_BIT_OR,\n\t\tAST_BIT_XOR,\n\t\tAST_BIT_XNOR,\n\t\tAST_REDUCE_AND,\n\t\tAST_REDUCE_OR,\n\t\tAST_REDUCE_XOR,\n\t\tAST_REDUCE_XNOR,\n\t\tAST_REDUCE_BOOL,\n\t\tAST_SHIFT_LEFT,\n\t\tAST_SHIFT_RIGHT,\n\t\tAST_SHIFT_SLEFT,\n\t\tAST_SHIFT_SRIGHT,\n\t\tAST_SHIFTX,\n\t\tAST_SHIFT,\n\t\tAST_LT,\n\t\tAST_LE,\n\t\tAST_EQ,\n\t\tAST_NE,\n\t\tAST_EQX,\n\t\tAST_NEX,\n\t\tAST_GE,\n\t\tAST_GT,\n\t\tAST_ADD,\n\t\tAST_SUB,\n\t\tAST_MUL,\n\t\tAST_DIV,\n\t\tAST_MOD,\n\t\tAST_POW,\n\t\tAST_POS,\n\t\tAST_NEG,\n\t\tAST_LOGIC_AND,\n\t\tAST_LOGIC_OR,\n\t\tAST_LOGIC_NOT,\n\t\tAST_TERNARY,\n\t\tAST_MEMRD,\n\t\tAST_MEMWR,\n\t\tAST_MEMINIT,\n\n\t\tAST_TCALL,\n\t\tAST_ASSIGN,\n\t\tAST_CELL,\n\t\tAST_PRIMITIVE,\n\t\tAST_CELLARRAY,\n\t\tAST_ALWAYS,\n\t\tAST_INITIAL,\n\t\tAST_BLOCK,\n\t\tAST_ASSIGN_EQ,\n\t\tAST_ASSIGN_LE,\n\t\tAST_CASE,\n\t\tAST_COND,\n\t\tAST_CONDX,\n\t\tAST_CONDZ,\n\t\tAST_DEFAULT,\n\t\tAST_FOR,\n\t\tAST_WHILE,\n\t\tAST_REPEAT,\n\n\t\tAST_GENVAR,\n\t\tAST_GENFOR,\n\t\tAST_GENIF,\n\t\tAST_GENCASE,\n\t\tAST_GENBLOCK,\n\t\tAST_TECALL,\n\n\t\tAST_POSEDGE,\n\t\tAST_NEGEDGE,\n\t\tAST_EDGE,\n\n\t\tAST_INTERFACE,\n\t\tAST_INTERFACEPORT,\n\t\tAST_INTERFACEPORTTYPE,\n\t\tAST_MODPORT,\n\t\tAST_MODPORTMEMBER,\n\t\tAST_PACKAGE,\n\n\t\tAST_WIRETYPE,\n\t\tAST_TYPEDEF,\n\t\tAST_STRUCT,\n\t\tAST_UNION,\n\t\tAST_STRUCT_ITEM,\n\t\tAST_BIND\n\t};\n\n\tstruct AstSrcLocType {\n\t\tunsigned int first_line, last_line;\n\t\tunsigned int first_column, last_column;\n\t\tAstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}\n\t\tAstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}\n\t};\n\n\t// convert an node type to a string (e.g. for debug output)\n\tstd::string type2str(AstNodeType type);\n\n\t// The AST is built using instances of this struct\n\tstruct AstNode\n\t{\n\t\t// for dict<> and pool<>\n\t\tunsigned int hashidx_;\n\t\tunsigned int hash() const { return hashidx_; }\n\n\t\t// this nodes type\n\t\tAstNodeType type;\n\n\t\t// the list of child nodes for this node\n\t\tstd::vector<AstNode*> children;\n\n\t\t// the list of attributes assigned to this node\n\t\tstd::map<RTLIL::IdString, AstNode*> attributes;\n\t\tbool get_bool_attribute(RTLIL::IdString id);\n\n\t\t// node content - most of it is unused in most node types\n\t\tstd::string str;\n\t\tstd::vector<RTLIL::State> bits;\n\t\tbool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized, is_custom_type;\n\t\tint port_id, range_left, range_right;\n\t\tuint32_t integer;\n\t\tdouble realvalue;\n\t\t// set for IDs typed to an enumeration, not used\n\t\tbool is_enum;\n\n\t\t// Declared range for array dimension.\n\t\tstruct dimension_t {\n\t\t\tint range_right; // lsb in [msb:lsb]\n\t\t\tint range_width; // msb - lsb + 1\n\t\t\tbool range_swapped; // if the declared msb < lsb, msb and lsb above are swapped\n\t\t};\n\t\t// Packed and unpacked dimensions for arrays.\n\t\t// Unpacked dimensions go first, to follow the order of indexing.\n\t\tstd::vector<dimension_t> dimensions;\n\t\t// Number of unpacked dimensions.\n\t\tint unpacked_dimensions;\n\n\t\t// this is set by simplify and used during RTLIL generation\n\t\tAstNode *id2ast;\n\n\t\t// this is used by simplify to detect if basic analysis has been performed already on the node\n\t\tbool basic_prep;\n\n\t\t// this is used for ID references in RHS expressions that should use the \"new\" value for non-blocking assignments\n\t\tbool lookahead;\n\n\t\t// this is the original sourcecode location that resulted in this AST node\n\t\t// it is automatically set by the constructor using AST::current_filename and\n\t\t// the AST::get_line_num() callback function.\n\t\tstd::string filename;\n\t\tAstSrcLocType location;\n\n\t\t// are we embedded in an lvalue, param?\n\t\t// (see fixup_hierarchy_flags)\n\t\tbool in_lvalue;\n\t\tbool in_param;\n\t\tbool in_lvalue_from_above;\n\t\tbool in_param_from_above;\n\n\t\t// creating and deleting nodes\n\t\tAstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr);\n\t\tAstNode *clone() const;\n\t\tvoid cloneInto(AstNode *other) const;\n\t\tvoid delete_children();\n\t\t~AstNode();\n\n\t\tenum mem2reg_flags\n\t\t{\n\t\t\t/* status flags */\n\t\t\tMEM2REG_FL_ALL = 0x00000001,\n\t\t\tMEM2REG_FL_ASYNC = 0x00000002,\n\t\t\tMEM2REG_FL_INIT = 0x00000004,\n\n\t\t\t/* candidate flags */\n\t\t\tMEM2REG_FL_FORCED = 0x00000100,\n\t\t\tMEM2REG_FL_SET_INIT = 0x00000200,\n\t\t\tMEM2REG_FL_SET_ELSE = 0x00000400,\n\t\t\tMEM2REG_FL_SET_ASYNC = 0x00000800,\n\t\t\tMEM2REG_FL_EQ2 = 0x00001000,\n\t\t\tMEM2REG_FL_CMPLX_LHS = 0x00002000,\n\t\t\tMEM2REG_FL_CONST_LHS = 0x00004000,\n\t\t\tMEM2REG_FL_VAR_LHS = 0x00008000,\n\n\t\t\t/* proc flags */\n\t\t\tMEM2REG_FL_EQ1 = 0x01000000,\n\t\t};\n\n\t\t// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.\n\t\t// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()\n\t\tbool simplify(bool const_fold, int stage, int width_hint, bool sign_hint);\n\t\tvoid replace_result_wire_name_in_function(const std::string &from, const std::string &to);\n\t\tAstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);\n\t\tvoid expand_genblock(const std::string &prefix);\n\t\tvoid label_genblks(std::set<std::string>& existing, int &counter);\n\t\tvoid mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,\n\t\t\t\tdict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);\n\t\tbool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);\n\t\tbool mem2reg_check(pool<AstNode*> &mem2reg_set);\n\t\tvoid mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);\n\t\tvoid meminfo(int &mem_width, int &mem_size, int &addr_bits);\n\t\tbool detect_latch(const std::string &var);\n\t\tconst RTLIL::Module* lookup_cell_module();\n\n\t\t// additional functionality for evaluating constant functions\n\t\tstruct varinfo_t {\n\t\t\tRTLIL::Const val;\n\t\t\tint offset;\n\t\t\tbool range_swapped;\n\t\t\tbool is_signed;\n\t\t\tAstNode *arg = nullptr;\n\t\t\tbool explicitly_sized;\n\t\t};\n\t\tbool has_const_only_constructs();\n\t\tbool replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall, bool must_succeed);\n\t\tAstNode *eval_const_function(AstNode *fcall, bool must_succeed);\n\t\tbool is_simple_const_expr();\n\n\t\t// helper for parsing format strings\n\t\tFmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0, bool may_fail = false);\n\n\t\tbool is_recursive_function() const;\n\t\tstd::pair<AstNode*, AstNode*> get_tern_choice();\n\n\t\t// create a human-readable text representation of the AST (for debugging)\n\t\tvoid dumpAst(FILE *f, std::string indent) const;\n\t\tvoid dumpVlog(FILE *f, std::string indent) const;\n\n\t\t// Generate RTLIL for a bind construct\n\t\tstd::vector<RTLIL::Binding *> genBindings() const;\n\n\t\t// used by genRTLIL() for detecting expression width and sign\n\t\tvoid detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\t\tvoid detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\n\t\t// create RTLIL code for this AST node\n\t\t// for expressions the resulting signal vector is returned\n\t\t// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module\n\t\tRTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);\n\t\tRTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);\n\n\t\t// compare AST nodes\n\t\tbool operator==(const AstNode &other) const;\n\t\tbool operator!=(const AstNode &other) const;\n\t\tbool contains(const AstNode *other) const;\n\n\t\t// helper functions for creating AST nodes for constants\n\t\tstatic AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);\n\t\tstatic AstNode *mkconst_str(const std::vector<RTLIL::State> &v);\n\t\tstatic AstNode *mkconst_str(const std::string &str);\n\n\t\t// helper function to create an AST node for a temporary register\n\t\tAstNode *mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed);\n\n\t\t// helper function for creating sign-extended const objects\n\t\tRTLIL::Const bitsAsConst(int width, bool is_signed);\n\t\tRTLIL::Const bitsAsConst(int width = -1);\n\t\tRTLIL::Const bitsAsUnsizedConst(int width);\n\t\tRTLIL::Const asAttrConst() const;\n\t\tRTLIL::Const asParaConst() const;\n\t\tuint64_t asInt(bool is_signed);\n\t\tbool bits_only_01() const;\n\t\tbool asBool() const;\n\n\t\t// helper functions for real valued const eval\n\t\tint isConst() const; // return '1' for AST_CONSTANT and '2' for AST_REALVALUE\n\t\tdouble asReal(bool is_signed);\n\t\tRTLIL::Const realAsConst(int width);\n\n\t\t// helpers for enum\n\t\tvoid allocateDefaultEnumValues();\n\t\tvoid annotateTypedEnums(AstNode *template_node);\n\n\t\t// helpers for locations\n\t\tstd::string loc_string() const;\n\n\t\t// Helper for looking up identifiers which are prefixed with the current module name\n\t\tstd::string try_pop_module_prefix() const;\n\n\t\t// helper to clone the node with some of its subexpressions replaced with zero (this is used\n\t\t// to evaluate widths of dynamic ranges)\n\t\tAstNode *clone_at_zero();\n\n\t\tvoid set_attribute(RTLIL::IdString key, AstNode *node)\n\t\t{\n\t\t\tattributes[key] = node;\n\t\t\tnode->set_in_param_flag(true);\n\t\t}\n\n\t\t// helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag\n\t\t// can be overridden based on the intrinsic properties of this node, i.e. based on its type)\n\t\tvoid set_in_lvalue_flag(bool flag, bool no_descend = false);\n\t\tvoid set_in_param_flag(bool flag, bool no_descend = false);\n\n\t\t// fix up the hierarchy flags (in_lvalue/in_param) of this node and its children\n\t\t//\n\t\t// to keep the flags in sync, fixup_hierarchy_flags(true) needs to be called once after\n\t\t// parsing the AST to walk the full tree, then plain fixup_hierarchy_flags() performs\n\t\t// localized fixups after modifying children/attributes of a particular node\n\t\tvoid fixup_hierarchy_flags(bool force_descend = false);\n\n\t\t// helpers for indexing\n\t\tAstNode *make_index_range(AstNode *node, bool unpacked_range = false);\n\t\tAstNode *get_struct_member() const;\n\n\t\t// helper to print errors from simplify/genrtlil code\n\t\t[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));\n\t};\n\n\t// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code\n\tvoid process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,\n\t\t\tbool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire);\n\n\t// parametric modules are supported directly by the AST library\n\t// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions\n\tstruct AstModule : RTLIL::Module {\n\t\tAstNode *ast;\n\t\tbool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;\n\t\t~AstModule() override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;\n\t\tstd::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);\n\t\tvoid expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;\n\t\tbool reprocess_if_necessary(RTLIL::Design *design) override;\n\t\tRTLIL::Module *clone() const override;\n\t\tvoid loadconfig() const;\n\t};\n\n\t// this must be set by the language frontend before parsing the sources\n\t// the AstNode constructor then uses current_filename and get_line_num()\n\t// to initialize the filename and linenum properties of new nodes\n\textern std::string current_filename;\n\textern void (*set_line_num)(int);\n\textern int (*get_line_num)();\n\n\t// for stats\n\tunsigned long long astnode_count();\n\n\t// set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive\n\t// to control the filename and linenum properties of new nodes not generated by a frontend parser)\n\tvoid use_internal_line_num();\n\n\t// call a DPI function\n\tAstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);\n\n\t// Helper functions related to handling SystemVerilog interfaces\n\tstd::pair<std::string,std::string> split_modport_from_type(std::string name_type);\n\tAstNode * find_modport(AstNode *intf, std::string name);\n\tvoid explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);\n\n\t// Helper for setting the src attribute.\n\tvoid set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);\n\n\t// generate standard $paramod... derived module name; parameters should be\n\t// in the order they are declared in the instantiated module\n\tstd::string derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters);\n\n\t// used to provide simplify() access to the current design for looking up\n\t// modules, ports, wires, etc.\n\tvoid set_simplify_design_context(const RTLIL::Design *design);\n}\n\nnamespace AST_INTERNAL\n{\n\t// internal state variables\n\textern bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;\n\textern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_pwires, flag_autowire;\n\textern AST::AstNode *current_ast, *current_ast_mod;\n\textern std::map<std::string, AST::AstNode*> current_scope;\n\textern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;\n\textern RTLIL::SigSpec ignoreThisSignalsInInitial;\n\textern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;\n\textern RTLIL::Module *current_module;\n\textern bool current_always_clocked;\n\textern dict<std::string, int> current_memwr_count;\n\textern dict<std::string, pool<int>> current_memwr_visible;\n\tstruct LookaheadRewriter;\n\tstruct ProcessGenerator;\n\n\t// Create and add a new AstModule from new_ast, then use it to replace\n\t// old_module in design, renaming old_module to move it out of the way.\n\t// Return the new module.\n\t//\n\t// If original_ast is not null, it will be used as the AST node for the\n\t// new module. Otherwise, new_ast will be used.\n\tRTLIL::Module *\n\tprocess_and_replace_module(RTLIL::Design *design,\n\t RTLIL::Module *old_module,\n\t AST::AstNode *new_ast,\n\t AST::AstNode *original_ast = nullptr);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "ast_binding.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * This header declares the AST::Binding class\n *\n * This is used to support the bind directive and is to RTLIL::Binding as\n * AST::AstModule is to RTLIL::Module, holding a syntax-level representation of\n * cells until we get to a stage where they make sense. In the case of a bind\n * directive, this is when we elaborate the design in the hierarchy pass.\n *\n */\n\n#ifndef AST_BINDING_H\n#define AST_BINDING_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/binding.h\"\n\n#include <memory>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace AST\n{\n\tclass Binding : public RTLIL::Binding\n\t{\n\tpublic:\n\t\tBinding(RTLIL::IdString target_type,\n\t\t RTLIL::IdString target_name,\n\t\t const AstNode &cell);\n\n\t\tstd::string describe() const override;\n\n\tprivate:\n\t\t// The syntax-level representation of the cell to be bound.\n\t\tstd::unique_ptr<AstNode> ast_node;\n\t};\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  },
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  "blif": {
@@ -159,30 +159,32 @@ export const filesystem = {
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  "bitpattern.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef BITPATTERN_H\n#define BITPATTERN_H\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct BitPatternPool\n{\n\tint width;\n\tstruct bits_t {\n\t\tstd::vector<RTLIL::State> bitdata;\n\t\tmutable unsigned int cached_hash;\n\t\tbits_t(int width = 0) : bitdata(width), cached_hash(0) { }\n\t\tRTLIL::State &operator[](int index) {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tconst RTLIL::State &operator[](int index) const {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tbool operator==(const bits_t &other) const {\n\t\t\tif (hash() != other.hash())\n\t\t\t\treturn false;\n\t\t\treturn bitdata == other.bitdata;\n\t\t}\n\t\tunsigned int hash() const {\n\t\t\tif (!cached_hash)\n\t\t\t\tcached_hash = hash_ops<std::vector<RTLIL::State>>::hash(bitdata);\n\t\t\treturn cached_hash;\n\t\t}\n\t};\n\tpool<bits_t> database;\n\n\tBitPatternPool(RTLIL::SigSpec sig)\n\t{\n\t\twidth = sig.size();\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\tif (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)\n\t\t\t\t\tpattern[i] = sig[i].data;\n\t\t\t\telse\n\t\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\t}\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tBitPatternPool(int width)\n\t{\n\t\tthis->width = width;\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tbits_t sig2bits(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits;\n\t\tbits.bitdata = sig.as_const().bits;\n\t\tfor (auto &b : bits.bitdata)\n\t\t\tif (b > RTLIL::State::S1)\n\t\t\t\tb = RTLIL::State::Sa;\n\t\treturn bits;\n\t}\n\n\tbool match(bits_t a, bits_t b)\n\t{\n\t\tlog_assert(int(a.bitdata.size()) == width);\n\t\tlog_assert(int(b.bitdata.size()) == width);\n\t\tfor (int i = 0; i < width; i++)\n\t\t\tif (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool has_any(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool has_all(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\t\tif (bits[i] > RTLIL::State::S1 && it[i] <= RTLIL::State::S1)\n\t\t\t\t\t\tgoto next_database_entry;\n\t\t\t\treturn true;\n\tnext_database_entry:;\n\t\t\t}\n\t\treturn false;\n\t}\n\n\tbool take(RTLIL::SigSpec sig)\n\t{\n\t\tbool status = false;\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto it = database.begin(); it != database.end();)\n\t\t\tif (match(*it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\t\tif ((*it)[i] != RTLIL::State::Sa || bits[i] == RTLIL::State::Sa)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbits_t new_pattern;\n\t\t\t\t\tnew_pattern.bitdata = it->bitdata;\n\t\t\t\t\tnew_pattern[i] = bits[i] == RTLIL::State::S1 ? RTLIL::State::S0 : RTLIL::State::S1;\n\t\t\t\t\tdatabase.insert(new_pattern);\n\t\t\t\t}\n\t\t\t\tit = database.erase(it);\n\t\t\t\tstatus = true;\n\t\t\t\tcontinue;\n\t\t\t} else\n\t\t\t\t++it;\n\t\treturn status;\n\t}\n\n\tbool take_all()\n\t{\n\t\tif (database.empty())\n\t\t\treturn false;\n\t\tdatabase.clear();\n\t\treturn true;\n\t}\n\n\tbool empty()\n\t{\n\t\treturn database.empty();\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "cellaigs.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLAIGS_H\n#define CELLAIGS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AigNode\n{\n\tIdString portname;\n\tint portbit;\n\tbool inverter;\n\tint left_parent, right_parent;\n\tvector<pair<IdString, int>> outports;\n\n\tAigNode();\n\tbool operator==(const AigNode &other) const;\n\tunsigned int hash() const;\n};\n\nstruct Aig\n{\n\tstring name;\n\tvector<AigNode> nodes;\n\tAig(Cell *cell);\n\n\tbool operator==(const Aig &other) const;\n\tunsigned int hash() const;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "celledges.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLEDGES_H\n#define CELLEDGES_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AbstractCellEdgesDatabase\n{\n\tvirtual ~AbstractCellEdgesDatabase() { }\n\tvirtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;\n\tbool add_edges_from_cell(RTLIL::Cell *cell);\n};\n\nstruct FwdCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tFwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[from_sigbit].insert(to_sigbit);\n\t}\n};\n\nstruct RevCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tRevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[to_sigbit].insert(from_sigbit);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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- "celltypes.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits)\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type == ID($_BUF_))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.bits.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
162
+ "celltypes.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($buf), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits)\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type.in(ID($_BUF_), ID($buf)))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.bits.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
163
163
  "consteval.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).bits;\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y.bits[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($macc))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tif (!eval(macc.bit_ports, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (auto &port : macc.ports) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
164
- "constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(qwp_position)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\n",
164
+ "constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(chain)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(qwp_position)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\n",
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  "cost.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef COST_H\n#define COST_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellCosts\n{\n\n\tprivate:\n\tdict<RTLIL::IdString, int> mod_cost_cache_;\n\tDesign *design_ = nullptr;\n\n\tpublic:\n\tCellCosts(RTLIL::Design *design) : design_(design) { }\n\n\tstatic const dict<RTLIL::IdString, int>& default_gate_cost() {\n\t\t// Default size heuristics for several common PDK standard cells\n\t\t// used by abc and stat\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 4 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 4 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 4 },\n\t\t\t{ ID($_ORNOT_), 4 },\n\t\t\t{ ID($_XOR_), 5 },\n\t\t\t{ ID($_XNOR_), 5 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 7 },\n\t\t\t{ ID($_OAI4_), 7 },\n\t\t\t{ ID($_MUX_), 4 },\n\t\t\t{ ID($_NMUX_), 4 },\n\t\t};\n\t\treturn db;\n\t}\n\n\tstatic const dict<RTLIL::IdString, int>& cmos_gate_cost() {\n\t\t// Estimated CMOS transistor counts for several common PDK standard cells\n\t\t// used by stat and optionally by abc\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 6 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 6 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 6 },\n\t\t\t{ ID($_ORNOT_), 6 },\n\t\t\t{ ID($_XOR_), 12 },\n\t\t\t{ ID($_XNOR_), 12 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 8 },\n\t\t\t{ ID($_OAI4_), 8 },\n\t\t\t{ ID($_MUX_), 12 },\n\t\t\t{ ID($_NMUX_), 10 },\n\t\t\t{ ID($_DFF_P_), 16 },\n\t\t\t{ ID($_DFF_N_), 16 },\n\t\t};\n\t\treturn db;\n\t}\n\n\t// Get the cell cost for a cell based on its parameters.\n\t// This cost is an *approximate* upper bound for the number of gates that\n\t// the cell will get mapped to with \"opt -fast; techmap\"\n\t// The intended usage is for flattening heuristics and similar situations\n\tunsigned int get(RTLIL::Cell *cell);\n\t// Sum up the cell costs of all cells in the module\n\t// and all its submodules recursively\n\tunsigned int get(RTLIL::Module *mod);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
166
- "ff.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FF_H\n#define FF_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Describes a flip-flop or a latch.\n//\n// If has_gclk, this is a formal verification FF with implicit global clock:\n// Q is simply previous cycle's D. Additionally if is_anyinit is true, this is\n// an $anyinit cell which always has an undefined initialization value. Note\n// that $anyinit is not considered to be among the FF celltypes, so a pass has\n// to explicitly opt-in to process $anyinit cells with FfData.\n//\n// Otherwise, the FF/latch can have any number of features selected by has_*\n// attributes that determine Q's value (in order of decreasing priority):\n//\n// - on start, register is initialized to val_init\n// - if has_sr is present:\n// - sig_clr is per-bit async clear, and sets the corresponding bit to 0\n// if active\n// - sig_set is per-bit async set, and sets the corresponding bit to 1\n// if active\n// - if has_arst is present:\n// - sig_arst is whole-reg async reset, and sets the whole register to val_arst\n// - if has_aload is present:\n// - sig_aload is whole-reg async load (aka latch gate enable), and sets the whole\n// register to sig_ad\n// - if has_clk is present, and we're currently on a clock edge:\n// - if has_ce is present and ce_over_srst is true:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - if has_srst is present:\n// - sig_srst is whole-reg sync reset and sets the register to val_srst\n// - if has_ce is present and ce_over_srst is false:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - set whole reg to sig_d\n// - if nothing of the above applies, the reg value remains unchanged\n//\n// Since the yosys FF cell library isn't fully generic, not all combinations\n// of the features above can be supported:\n//\n// - only one of has_srst, has_arst, has_sr can be used\n// - if has_clk is used together with has_aload, then has_srst, has_arst,\n// has_sr cannot be used\n//\n// The valid feature combinations are thus:\n//\n// - has_clk + optional has_ce [dff/dffe]\n// - has_clk + optional has_ce + has_arst [adff/adffe]\n// - has_clk + optional has_ce + has_aload [aldff/aldffe]\n// - has_clk + optional has_ce + has_sr [dffsr/dffsre]\n// - has_clk + optional has_ce + has_srst [sdff/sdffe/sdffce]\n// - has_aload [dlatch]\n// - has_aload + has_arst [adlatch]\n// - has_aload + has_sr [dlatchsr]\n// - has_sr [sr]\n// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]\n// - empty set [not a cell — will be emitted as a simple direct connection]\n\nstruct FfData {\n\tModule *module;\n\tFfInitVals *initvals;\n\tCell *cell;\n\tIdString name;\n\t// The FF output.\n\tSigSpec sig_q;\n\t// The sync data input, present if has_clk or has_gclk.\n\tSigSpec sig_d;\n\t// The async data input, present if has_aload.\n\tSigSpec sig_ad;\n\t// The sync clock, present if has_clk.\n\tSigSpec sig_clk;\n\t// The clock enable, present if has_ce.\n\tSigSpec sig_ce;\n\t// The async load enable, present if has_aload.\n\tSigSpec sig_aload;\n\t// The async reset, preset if has_arst.\n\tSigSpec sig_arst;\n\t// The sync reset, preset if has_srst.\n\tSigSpec sig_srst;\n\t// The async clear (per-lane), present if has_sr.\n\tSigSpec sig_clr;\n\t// The async set (per-lane), present if has_sr.\n\tSigSpec sig_set;\n\t// True if this is a clocked (edge-sensitive) flip-flop.\n\tbool has_clk;\n\t// True if this is a $ff, exclusive with every other has_*.\n\tbool has_gclk;\n\t// True if this FF has a clock enable. Depends on has_clk.\n\tbool has_ce;\n\t// True if this FF has async load function — this includes D latches.\n\t// If this and has_clk are both set, has_arst and has_sr cannot be set.\n\tbool has_aload;\n\t// True if this FF has sync set/reset. Depends on has_clk, exclusive\n\t// with has_arst, has_sr, has_aload.\n\tbool has_srst;\n\t// True if this FF has async set/reset. Exclusive with has_srst,\n\t// has_sr. If this and has_clk are both set, has_aload cannot be set.\n\tbool has_arst;\n\t// True if this FF has per-bit async set + clear. Exclusive with\n\t// has_srst, has_arst. If this and has_clk are both set, has_aload\n\t// cannot be set.\n\tbool has_sr;\n\t// If has_ce and has_srst are both set, determines their relative\n\t// priorities: if true, inactive ce disables srst; if false, srst\n\t// operates independent of ce.\n\tbool ce_over_srst;\n\t// True if this FF is a fine cell, false if it is a coarse cell.\n\t// If true, width must be 1.\n\tbool is_fine;\n\t// True if this FF is an $anyinit cell. Depends on has_gclk.\n\tbool is_anyinit;\n\t// Polarities, corresponding to sig_*. True means active-high, false\n\t// means active-low.\n\tbool pol_clk;\n\tbool pol_ce;\n\tbool pol_aload;\n\tbool pol_arst;\n\tbool pol_srst;\n\tbool pol_clr;\n\tbool pol_set;\n\t// The value loaded by sig_arst.\n\tConst val_arst;\n\t// The value loaded by sig_srst.\n\tConst val_srst;\n\t// The initial value at power-up.\n\tConst val_init;\n\t// The FF data width in bits.\n\tint width;\n\tdict<IdString, Const> attributes;\n\n\tFfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {\n\t\twidth = 0;\n\t\thas_clk = false;\n\t\thas_gclk = false;\n\t\thas_ce = false;\n\t\thas_aload = false;\n\t\thas_srst = false;\n\t\thas_arst = false;\n\t\thas_sr = false;\n\t\tce_over_srst = false;\n\t\tis_fine = false;\n\t\tis_anyinit = false;\n\t\tpol_clk = false;\n\t\tpol_aload = false;\n\t\tpol_ce = false;\n\t\tpol_arst = false;\n\t\tpol_srst = false;\n\t\tpol_clr = false;\n\t\tpol_set = false;\n\t}\n\n\tFfData(FfInitVals *initvals, Cell *cell_);\n\n\t// Returns a FF identical to this one, but only keeping bit indices from the argument.\n\tFfData slice(const std::vector<int> &bits);\n\n\tvoid add_dummy_ce();\n\tvoid add_dummy_srst();\n\tvoid add_dummy_arst();\n\tvoid add_dummy_aload();\n\tvoid add_dummy_sr();\n\tvoid add_dummy_clk();\n\n\tvoid arst_to_aload();\n\tvoid arst_to_sr();\n\n\tvoid aload_to_sr();\n\n\t// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and\n\t// fixes up control signals appropriately to preserve semantics.\n\tvoid convert_ce_over_srst(bool val);\n\n\tvoid unmap_ce();\n\tvoid unmap_srst();\n\n\tvoid unmap_ce_srst() {\n\t\tunmap_ce();\n\t\tunmap_srst();\n\t}\n\n\tCell *emit();\n\n\t// Removes init attribute from the Q output, but keeps val_init unchanged.\n\t// It will be automatically reattached on emit. Use this before changing sig_q.\n\tvoid remove_init() {\n\t\tif (initvals)\n\t\t\tinitvals->remove_init(sig_q);\n\t}\n\n\tvoid remove();\n\n\t// Flip the sense of the given bit slices of the FF: insert inverters on data\n\t// inputs and output, flip the corresponding init/reset bits, swap clr/set\n\t// inputs with proper priority fix.\n\tvoid flip_bits(const pool<int> &bits);\n\n\tvoid flip_rst_bits(const pool<int> &bits);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
166
+ "drivertools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef DRIVERTOOLS_H\n#define DRIVERTOOLS_H\n\n#include <type_traits>\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// TODO move implementation into a .cc file\n\nstruct DriveBit;\n\nstruct DriveChunkWire;\nstruct DriveChunkPort;\nstruct DriveChunkMarker;\nstruct DriveChunk;\n\nstruct DriveSpec;\n\nconst char *log_signal(DriveChunkWire const &chunk);\nconst char *log_signal(DriveChunkPort const &chunk);\nconst char *log_signal(DriveChunkMarker const &chunk);\nconst char *log_signal(DriveChunk const &chunk);\nconst char *log_signal(DriveSpec const &chunk);\n\nenum class DriveType : unsigned char\n{\n\tNONE,\n\tCONSTANT,\n\tWIRE,\n\tPORT,\n\tMULTIPLE,\n\tMARKER,\n};\n\nstruct DriveBitWire\n{\n\tWire *wire;\n\tint offset;\n\n\tDriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {}\n\n\tbool operator==(const DriveBitWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\t}\n\n\toperator SigBit() const\n\t{\n\t\treturn SigBit(wire, offset);\n\t}\n};\n\nstruct DriveBitPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\n\tDriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {}\n\n\tbool operator==(const DriveBitPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t}\n};\n\n\nstruct DriveBitMarker\n{\n\tint marker;\n\tint offset;\n\n\tDriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {}\n\n\tbool operator==(const DriveBitMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset;\n\t}\n\n\tbool operator<(const DriveBitMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(marker, offset);\n\t}\n\n};\n\nstruct DriveBitMultiple\n{\nprivate:\n\tpool<DriveBit> multiple_;\n\npublic:\n\tDriveBitMultiple();\n\tDriveBitMultiple(DriveBit const &single);\n\n\tpool<DriveBit> const &multiple() const { return multiple_; }\n\n\tvoid merge(DriveBitMultiple const &other)\n\t{\n\t\tfor (DriveBit const &single : other.multiple_)\n\t\t\tmerge(single);\n\t}\n\n\tvoid merge(DriveBitMultiple &&other)\n\t{\n\t\tfor (DriveBit &single : other.multiple_)\n\t\t\tmerge(std::move(single));\n\t}\n\n\tvoid merge(DriveBit const &single);\n\tvoid merge(DriveBit &&single);\n\n\tbool operator==(const DriveBitMultiple &other) const\n\t{\n\t\treturn multiple_ == other.multiple_;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t return multiple_.hash();\n\t}\n};\n\nstruct DriveBit\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tState constant_;\n\t\tDriveBitWire wire_;\n\t\tDriveBitPort port_;\n\t\tDriveBitMarker marker_;\n\t\tDriveBitMultiple multiple_;\n\t};\npublic:\n\tDriveBit() {}\n\n\tDriveBit(SigBit const &bit);\n\n\tDriveBit(DriveBit const &other) { *this = other; }\n\tDriveBit(DriveBit &&other) { *this = other; }\n\n\n\tDriveBit(State constant) { *this = constant; }\n\tDriveBit(DriveBitWire const &wire) { *this = wire; }\n\tDriveBit(DriveBitWire &&wire) { *this = wire; }\n\tDriveBit(DriveBitPort const &port) { *this = port; }\n\tDriveBit(DriveBitPort &&port) { *this = port; }\n\tDriveBit(DriveBitMarker const &marker) { *this = marker; }\n\tDriveBit(DriveBitMarker &&marker) { *this = marker; }\n\tDriveBit(DriveBitMultiple const &multiple) { *this = multiple; }\n\tDriveBit(DriveBitMultiple &&multiple) { *this = multiple; }\n\n\t~DriveBit() { set_none(); }\n\n\tvoid set_none()\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveBitWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveBitPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveBitMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveBitMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t}\n\n\tDriveBit &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBit &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(State constant)\n\t{\n\t\tset_none();\n\t\tconstant_ = constant;\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveBitWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveBitPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveBitMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple const &multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveBit &operator=(DriveBitMultiple &&multiple)\n\t{\n\t\tset_none();\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveBitMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\tunsigned int inner;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tinner = 0;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tinner = constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\tinner = wire_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tinner = port_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tinner = marker_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tinner = multiple_.hash();\n\t\t\t\tbreak;\n\t\t}\n\t\treturn mkhash((unsigned int)type_, inner);\n\t}\n\n\tbool operator==(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveBit &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveBit &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tlog_assert(!\"TODO\");\n\t\t}\n\t\tlog_abort();\n\t}\n\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tState &constant() { log_assert(is_constant()); return constant_; }\n\tState const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveBitWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveBitWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveBitPort &port() { log_assert(is_port()); return port_; }\n\tDriveBitPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveBitMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\tvoid merge(DriveBit const &other);\n\n};\n\ninline DriveBitMultiple::DriveBitMultiple() {}\ninline DriveBitMultiple::DriveBitMultiple(DriveBit const &single)\n{\n\tmultiple_.emplace(single);\n}\n\nstruct DriveChunkWire\n{\n\tWire *wire;\n\tint offset;\n\tint width;\n\n\tDriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {}\n\tDriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitWire operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitWire(wire, offset + i);\n\t}\n\n\tbool can_append(DriveBitWire const &bit) const;\n\tbool try_append(DriveBitWire const &bit);\n\tbool try_append(DriveChunkWire const &chunk);\n\n\t// Whether this chunk is a whole wire\n\tbool is_whole() const { return offset == 0 && width == wire->width; }\n\n\tbool operator==(const DriveChunkWire &other) const\n\t{\n\t\treturn wire == other.wire && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkWire &other) const\n\t{\n\t\tif (wire != other.wire)\n\t\t\treturn wire->name < other.wire->name;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(wire->name.hash(), width), offset);\n\t}\n\n\texplicit operator SigChunk() const\n\t{\n\t\treturn SigChunk(wire, offset, width);\n\t}\n};\n\nstruct DriveChunkPort\n{\n\tCell *cell;\n\tIdString port;\n\tint offset;\n\tint width;\n\n\tDriveChunkPort(Cell *cell, IdString port, int offset, int width) :\n\t\tcell(cell), port(port), offset(offset), width(width) { }\n\tDriveChunkPort(Cell *cell, IdString port) :\n\t\tcell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { }\n\tDriveChunkPort(Cell *cell, std::pair<IdString, SigSpec> const &conn) :\n\t\tcell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { }\n\tDriveChunkPort(DriveBitPort const &bit) :\n\t\tcell(bit.cell), port(bit.port), offset(bit.offset), width(1) { }\n\n\tint size() const { return width; }\n\n\tDriveBitPort operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitPort(cell, port, offset + i);\n\t}\n\n\tbool can_append(DriveBitPort const &bit) const;\n\tbool try_append(DriveBitPort const &bit);\n\tbool try_append(DriveChunkPort const &chunk);\n\n\t// Whether this chunk is a whole port\n\tbool is_whole() const\n\t{\n\t\treturn offset == 0 && width == cell->connections().at(port).size();\n\t}\n\n\tbool operator==(const DriveChunkPort &other) const\n\t{\n\t\treturn cell == other.cell && port == other.port && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkPort &other) const\n\t{\n\t\tif (cell != other.cell)\n\t\t\treturn cell->name < other.cell->name;\n\t\tif (port != other.port)\n\t\t\treturn port < other.port;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset);\n\t}\n};\n\n\nstruct DriveChunkMarker\n{\n\tint marker;\n\tint offset;\n\tint width;\n\n\tDriveChunkMarker(int marker, int offset, int width) :\n\t\tmarker(marker), offset(offset), width(width) {}\n\tDriveChunkMarker(DriveBitMarker const &bit) :\n\t\tmarker(bit.marker), offset(bit.offset), width(1) {}\n\n\tint size() const { return width; }\n\n\tDriveBitMarker operator[](int i) const\n\t{\n\t\tlog_assert(i >= 0 && i < width);\n\t\treturn DriveBitMarker(marker, offset + i);\n\t}\n\n\tbool can_append(DriveBitMarker const &bit) const;\n\tbool try_append(DriveBitMarker const &bit);\n\tbool try_append(DriveChunkMarker const &chunk);\n\n\tbool operator==(const DriveChunkMarker &other) const\n\t{\n\t\treturn marker == other.marker && offset == other.offset && width == other.width;\n\t}\n\n\tbool operator<(const DriveChunkMarker &other) const\n\t{\n\t\tif (marker != other.marker)\n\t\t\treturn marker < other.marker;\n\t\tif (width != other.width)\n\t\t\treturn width < other.width;\n\t\treturn offset < other.offset;\n\t}\n\n\tunsigned int hash() const\n\t{\n\t\treturn mkhash_add(mkhash(marker, width), offset);\n\t}\n};\n\nstruct DriveChunkMultiple\n{\nprivate:\n\tmutable pool<DriveChunk> multiple_;\n\tint width_;\n\npublic:\n\tpool<DriveChunk> const &multiple() const { return multiple_; }\n\n\tDriveChunkMultiple(DriveBitMultiple const &bit);\n\n\tint size() const { return width_; }\n\n\tDriveBitMultiple operator[](int i) const;\n\n\tbool can_append(DriveBitMultiple const &bit) const;\n\n\tbool try_append(DriveBitMultiple const &bit);\n\n\n\tbool can_append(DriveChunkMultiple const &bit) const;\n\n\tbool try_append(DriveChunkMultiple const &bit);\n\n\tbool operator==(const DriveChunkMultiple &other) const\n\t{\n\t\treturn width_ == other.width_ && multiple_ == other.multiple_;\n\t}\n\n\tbool operator<(const DriveChunkMultiple &other) const\n\t{\n\t\tif (multiple_.size() < other.multiple_.size())\n\n\t\tmultiple_.sort();\n\t\treturn false; // TODO implement, canonicalize order\n\t}\n\n\tunsigned int hash() const\n\t{\n\t return mkhash(width_, multiple_.hash());\n\t}\n};\n\nstruct DriveChunk\n{\nprivate:\n\tDriveType type_ = DriveType::NONE;\n\tunion\n\t{\n\t\tint none_;\n\t\tConst constant_;\n\t\tDriveChunkWire wire_;\n\t\tDriveChunkPort port_;\n\t\tDriveChunkMarker marker_;\n\t\tDriveChunkMultiple multiple_;\n\t};\n\npublic:\n\tDriveChunk() { set_none(); }\n\n\tDriveChunk(DriveChunk const &other) { *this = other; }\n\tDriveChunk(DriveChunk &&other) { *this = other; }\n\n\tDriveChunk(DriveBit const &other) { *this = other; }\n\n\tDriveChunk(Const const &constant) { *this = constant; }\n\tDriveChunk(Const &&constant) { *this = constant; }\n\tDriveChunk(DriveChunkWire const &wire) { *this = wire; }\n\tDriveChunk(DriveChunkWire &&wire) { *this = wire; }\n\tDriveChunk(DriveChunkPort const &port) { *this = port; }\n\tDriveChunk(DriveChunkPort &&port) { *this = port; }\n\tDriveChunk(DriveChunkMarker const &marker) { *this = marker; }\n\tDriveChunk(DriveChunkMarker &&marker) { *this = marker; }\n\tDriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; }\n\tDriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; }\n\n\t~DriveChunk() { set_none(); }\n\n\tDriveBit operator[](int i) const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn DriveBit();\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_[i];\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_[i];\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_[i];\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_[i];\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_[i];\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tvoid set_none(int width = 0)\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tnone_ = width;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tconstant_.~Const();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\twire_.~DriveChunkWire();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tport_.~DriveChunkPort();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tmarker_.~DriveChunkMarker();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tmultiple_.~DriveChunkMultiple();\n\t\t\t\tbreak;\n\t\t}\n\t\ttype_ = DriveType::NONE;\n\t\tnone_ = width;\n\t}\n\n\tDriveChunk &operator=(DriveChunk const &other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = other.constant_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = other.wire_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = other.port_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = other.marker_;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = other.multiple_;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunk &&other)\n\t{\n\t\tswitch (other.type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(other.none_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = std::move(other.constant_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = std::move(other.wire_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = std::move(other.port_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = std::move(other.marker_);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = std::move(other.multiple_);\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const const &constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(constant);\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(Const &&constant)\n\t{\n\t\tset_none();\n\t\tnew (&constant_) Const(std::move(constant));\n\t\ttype_ = DriveType::CONSTANT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire const &wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkWire &&wire)\n\t{\n\t\tset_none();\n\t\tnew (&wire_) DriveChunkWire(wire);\n\t\ttype_ = DriveType::WIRE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort const &port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkPort &&port)\n\t{\n\t\tset_none();\n\t\tnew (&port_) DriveChunkPort(port);\n\t\ttype_ = DriveType::PORT;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker const &marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMarker &&marker)\n\t{\n\t\tset_none();\n\t\tnew (&marker_) DriveChunkMarker(marker);\n\t\ttype_ = DriveType::MARKER;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple const &multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveChunkMultiple &&multiple)\n\t{\n\t\tset_none(multiple.size());\n\t\tif (multiple.multiple().empty())\n\t\t\treturn *this;\n\t\tnew (&multiple_) DriveChunkMultiple(multiple);\n\t\ttype_ = DriveType::MULTIPLE;\n\t\treturn *this;\n\t}\n\n\tDriveChunk &operator=(DriveBit const &other)\n\t{\n\t\tswitch (other.type())\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tset_none(1);\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\t*this = Const(other.constant());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\t*this = DriveChunkWire(other.wire());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\t*this = DriveChunkPort(other.port());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\t*this = DriveChunkMarker(other.marker());\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\t*this = DriveChunkMultiple(other.multiple());\n\t\t\t\tbreak;\n\t\t}\n\t\treturn *this;\n\t}\n\n\tbool can_append(DriveBit const &bit) const;\n\tbool try_append(DriveBit const &bit);\n\tbool try_append(DriveChunk const &chunk);\n\n\tunsigned int hash() const\n\t{\n\t\tunsigned int inner;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\tinner = 0;\n\t\t\t\tbreak;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\tinner = constant_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\tinner = wire_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::PORT:\n\t\t\t\tinner = port_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\tinner = marker_.hash();\n\t\t\t\tbreak;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\tinner = multiple_.hash();\n\t\t\t\tbreak;\n\t\t}\n\t\treturn mkhash((unsigned int)type_, inner);\n\t}\n\n\tbool operator==(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn false;\n\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn true;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ == other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ == other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ == other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ == other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ == other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tbool operator!=(const DriveChunk &other) const\n\t{\n\t\treturn !(*this == other);\n\t}\n\n\tbool operator<(const DriveChunk &other) const\n\t{\n\t\tif (type_ != other.type_)\n\t\t\treturn type_ < other.type_;\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn false;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_ < other.constant_;\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_ < other.wire_;\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_ < other.port_;\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_ < other.marker_;\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_ < other.multiple_;\n\t\t}\n\t\tlog_abort();\n\t}\n\n\tDriveType type() const { return type_; }\n\n\tbool is_none() const { return type_ == DriveType::NONE; }\n\tbool is_constant() const { return type_ == DriveType::CONSTANT; }\n\tbool is_wire() const { return type_ == DriveType::WIRE; }\n\tbool is_port() const { return type_ == DriveType::PORT; }\n\tbool is_marker() const { return type_ == DriveType::MARKER; }\n\tbool is_multiple() const { return type_ == DriveType::MULTIPLE; }\n\n\tConst &constant() { log_assert(is_constant()); return constant_; }\n\tConst const &constant() const { log_assert(is_constant()); return constant_; }\n\tDriveChunkWire &wire() { log_assert(is_wire()); return wire_; }\n\tDriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; }\n\tDriveChunkPort &port() { log_assert(is_port()); return port_; }\n\tDriveChunkPort const &port() const { log_assert(is_port()); return port_; }\n\tDriveChunkMarker &marker() { log_assert(is_marker()); return marker_; }\n\tDriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; }\n\tDriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; }\n\tDriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; }\n\n\n\tint size() const\n\t{\n\t\tswitch (type_)\n\t\t{\n\t\t\tcase DriveType::NONE:\n\t\t\t\treturn none_;\n\t\t\tcase DriveType::CONSTANT:\n\t\t\t\treturn constant_.size();\n\t\t\tcase DriveType::WIRE:\n\t\t\t\treturn wire_.size();\n\t\t\tcase DriveType::PORT:\n\t\t\t\treturn port_.size();\n\t\t\tcase DriveType::MARKER:\n\t\t\t\treturn marker_.size();\n\t\t\tcase DriveType::MULTIPLE:\n\t\t\t\treturn multiple_.size();\n\t\t}\n\t\tlog_abort();\n\t}\n};\n\ninline DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit)\n\t: width_(1)\n{\n\tfor (auto const &bit : bit.multiple())\n\t\tmultiple_.emplace(bit);\n}\n\nstruct DriveSpec\n{\nprivate:\n\tint width_ = 0;\n\tmutable std::vector<DriveChunk> chunks_;\n\tmutable std::vector<DriveBit> bits_;\n\tmutable unsigned int hash_ = 0;\npublic:\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tDriveSpec() {}\n\n\tDriveSpec(DriveChunk const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkWire const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkPort const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMarker const &chunk) { *this = chunk; }\n\tDriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; }\n\n\tDriveSpec(DriveBit const &bit) { *this = bit; }\n\tDriveSpec(DriveBitWire const &bit) { *this = bit; }\n\tDriveSpec(DriveBitPort const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMarker const &bit) { *this = bit; }\n\tDriveSpec(DriveBitMultiple const &bit) { *this = bit; }\n\n\tDriveSpec(std::vector<DriveChunk> const &chunks) : chunks_(chunks) { compute_width(); }\n\n\tDriveSpec(std::vector<DriveBit> const &bits)\n\t{\n\t\tfor (auto const &bit : bits)\n\t\t\tappend(bit);\n\t}\n\n\tDriveSpec(SigSpec const &sig)\n\t{\n\t\t// TODO: converting one chunk at a time would be faster\n\t\tfor (auto const &bit : sig.bits())\n\t\t\tappend(bit);\n\t}\n\n\tstd::vector<DriveChunk> const &chunks() const { pack(); return chunks_; }\n\tstd::vector<DriveBit> const &bits() const { unpack(); return bits_; }\n\n\tint size() const { return width_; }\n\n\tvoid append(DriveBit const &bit);\n\n\tvoid append(DriveChunk const &chunk);\n\n\tvoid pack() const;\n\n\tvoid unpack() const;\n\n\tDriveBit &operator[](int index)\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tconst DriveBit &operator[](int index) const\n\t{\n\t\tlog_assert(index >= 0 && index < size());\n\t\tunpack();\n\t\treturn bits_[index];\n\t}\n\n\tvoid clear()\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\twidth_ = 0;\n\t}\n\n\tDriveSpec &operator=(DriveChunk const &chunk)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(chunk);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); }\n\tDriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); }\n\n\tDriveSpec &operator=(DriveBit const &bit)\n\t{\n\t\tchunks_.clear();\n\t\tbits_.clear();\n\t\tappend(bit);\n\t\treturn *this;\n\t}\n\n\tDriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); }\n\tDriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); }\n\n\tunsigned int hash() const {\n\t\tif (hash_ != 0) return hash_;\n\n\t\tpack();\n\t\thash_ = hash_ops<std::vector<DriveChunk>>().hash(chunks_);\n\t\thash_ |= (hash_ == 0);\n\t\treturn hash_;\n\t}\n\n\tbool operator==(DriveSpec const &other) const {\n\t\tif (size() != other.size() || hash() != other.hash())\n\t\t\treturn false;\n\t\treturn chunks() == other.chunks();\n\t}\n\nprivate:\n\tvoid compute_width();\n};\n\n\n\nstruct DriverMap\n{\n\tCellTypes celltypes;\n\n\tDriverMap() { celltypes.setup(); }\n\tDriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); }\n\nprivate:\n\n\t// Internally we represent all DriveBits by mapping them to DriveBitIds\n\t// which use less memory and are cheaper to compare.\n\tstruct DriveBitId\n\t{\n\t\tint id = -1;\n\n\t\tDriveBitId() {};\n\n\t\tDriveBitId(int id) : id(id) { }\n\n\t\tbool operator==(const DriveBitId &other) const { return id == other.id; }\n\t\tbool operator!=(const DriveBitId &other) const { return id != other.id; }\n\t\tbool operator<(const DriveBitId &other) const { return id < other.id; }\n\t\tunsigned int hash() const { return id; }\n\t};\n\t// Essentially a dict<DriveBitId, pool<DriveBitId>> but using less memory\n\t// and fewer allocations\n\tstruct DriveBitGraph {\n\t\tdict<DriveBitId, DriveBitId> first_edges;\n\t\tdict<DriveBitId, DriveBitId> second_edges;\n\t\tdict<DriveBitId, pool<DriveBitId>> more_edges;\n\n\t\tvoid add_edge(DriveBitId src, DriveBitId dst);\n\t\tDriveBitId pop_edge(DriveBitId src);\n\t\tvoid clear(DriveBitId src);\n\t\tbool contains(DriveBitId src);\n\t\tint count(DriveBitId src);\n\n\t\tDriveBitId at(DriveBitId src, int index);\n\t};\n\n\t// The following two maps maintain a sparse DriveBit to DriveBitId mapping.\n\t// This saves a lot of memory compared to a `dict<DriveBit, DriveBitId>` or\n\t// `idict<DriveBit>`.\n\n\t// Maps wires to the first DriveBitId of the consecutive range used for\n\t// that wire.\n\tdict<Wire *, DriveBitId> wire_offsets;\n\n\t// Maps cell ports to a the first DriveBitId of the consecutive range used\n\t// for that cell port.\n\tdict<pair<Cell *, IdString>, DriveBitId> port_offsets;\n\n\t// For the inverse map that maps DriveBitIds back to DriveBits we use a\n\t// sorted map containing only the first DriveBit for each wire and cell\n\t// port.\n\tstd::map<DriveBitId, DriveBit> drive_bits;\n\n\t// As a memory optimization for gate level net lists we store single-bit\n\t// wires and cell ports in a `dict` which requires less memory and fewer\n\t// allocations than `std::map` but doesn't support the kind of lookups we\n\t// need for a sparse coarse grained mapping.\n\tdict<DriveBitId, DriveBit> isolated_drive_bits;\n\n\t// Used for allocating DriveBitIds, none and constant states use a fixewd\n\t// mapping to the first few ids, which we need to skip.\n\tint next_offset = 1 + (int)State::Sm;\n\n\t// Union-Find over directly connected bits that share the same single\n\t// driver or are undriven. We never merge connections between drivers\n\t// and/or kept wires.\n\tmfp<DriveBitId> same_driver;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally unambiguous (one side only drives or requires a driven value).\n\tDriveBitGraph connected_drivers;\n\n\t// For each bit, store a set of connected driver bits for which the\n\t// explicit connection should be preserved and the driving direction is\n\t// locally ambiguous. Every such ambiguous connection is also present in\n\t// the reverse direction and has to be resolved when querying drivers.\n\tDriveBitGraph connected_undirected;\n\n\t// Subset of `connected_undirected` for caching the resolved driving\n\t// direction. In case multiple drivers are present this can still contain\n\t// both orientations of a single connection, but for a single driver only\n\t// one will be present.\n\tDriveBitGraph connected_oriented;\n\n\t// Stores for which bits we already resolved the orientation (cached in\n\t// `connected_oriented`).\n\tpool<DriveBitId> oriented_present;\n\n\n\tenum class BitMode {\n\t\tNONE = 0, // Not driven, no need to keep wire\n\t\tDRIVEN = 1, // Not driven, uses a value driven elsewhere\n\t\tDRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection\n\t\tKEEP = 3, // Wire that should be kept\n\t\tTRISTATE = 4, // Can drive a value but can also use a value driven elsewhere\n\t\tDRIVER = 5, // Drives a value\n\t};\n\n\tBitMode bit_mode(DriveBit const &bit);\n\tDriveBitId id_from_drive_bit(DriveBit const &bit);\n\tDriveBit drive_bit_from_id(DriveBitId id);\n\n\tvoid connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id);\n\tvoid connect_undirected(DriveBitId a_id, DriveBitId b_id);\n\npublic:\n\n\tvoid add(Module *module);\n\n\t// Add a single bit connection to the driver map.\n\tvoid add(DriveBit const &a, DriveBit const &b);\n\n\ttemplate<typename T>\n\tstatic constexpr bool is_sig_type() {\n\t\treturn\n\t\t\tstd::is_same<T, SigSpec>::value ||\n\t\t\tstd::is_same<T, SigChunk>::value ||\n\t\t\tstd::is_same<T, DriveSpec>::value ||\n\t\t\tstd::is_same<T, DriveChunk>::value ||\n\t\t\tstd::is_same<T, DriveChunkPort>::value ||\n\t\t\tstd::is_same<T, DriveChunkWire>::value ||\n\t\t\tstd::is_same<T, Const>::value;\n\t}\n\n\t// We use the enable_if to produce better compiler errors when unsupported\n\t// types are used\n\ttemplate<typename T, typename U>\n\ttypename std::enable_if<is_sig_type<T>() && is_sig_type<U>()>::type\n\tadd(T const &a, U const &b)\n\t{\n\t\tlog_assert(a.size() == b.size());\n\t\tfor (int i = 0; i != GetSize(a); ++i)\n\t\t\tadd(DriveBit(a[i]), DriveBit(b[i]));\n\t}\n\n\n\t// Specialized version that avoids unpacking\n\tvoid add(SigSpec const &a, SigSpec const &b);\n\nprivate:\n\tvoid add_port(Cell *cell, IdString const &port, SigSpec const &b);\n\n\t// Only used a local variables in `orient_undirected`, always cleared, only\n\t// stored to reduce allocations.\n\tpool<DriveBitId> orient_undirected_seen;\n\tpool<DriveBitId> orient_undirected_drivers;\n\tdict<DriveBitId, int> orient_undirected_distance;\n\n\tvoid orient_undirected(DriveBitId id);\n\npublic:\n\tDriveBit operator()(DriveBit const &bit);\n\n\tDriveSpec operator()(DriveSpec spec);\n\nprivate:\n\tbool keep_wire(Wire *wire) {\n\t\t// TODO configurable\n\t\treturn wire->has_attribute(ID(keep));\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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+ "ff.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FF_H\n#define FF_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Describes a flip-flop or a latch.\n//\n// If has_gclk, this is a formal verification FF with implicit global clock:\n// Q is simply previous cycle's D. Additionally if is_anyinit is true, this is\n// an $anyinit cell which always has an undefined initialization value. Note\n// that $anyinit is not considered to be among the FF celltypes, so a pass has\n// to explicitly opt-in to process $anyinit cells with FfData.\n//\n// Otherwise, the FF/latch can have any number of features selected by has_*\n// attributes that determine Q's value (in order of decreasing priority):\n//\n// - on start, register is initialized to val_init\n// - if has_sr is present:\n// - sig_clr is per-bit async clear, and sets the corresponding bit to 0\n// if active\n// - sig_set is per-bit async set, and sets the corresponding bit to 1\n// if active\n// - if has_arst is present:\n// - sig_arst is whole-reg async reset, and sets the whole register to val_arst\n// - if has_aload is present:\n// - sig_aload is whole-reg async load (aka latch gate enable), and sets the whole\n// register to sig_ad\n// - if has_clk is present, and we're currently on a clock edge:\n// - if has_ce is present and ce_over_srst is true:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - if has_srst is present:\n// - sig_srst is whole-reg sync reset and sets the register to val_srst\n// - if has_ce is present and ce_over_srst is false:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - set whole reg to sig_d\n// - if nothing of the above applies, the reg value remains unchanged\n//\n// Since the yosys FF cell library isn't fully generic, not all combinations\n// of the features above can be supported:\n//\n// - only one of has_srst, has_arst, has_sr can be used\n// - if has_clk is used together with has_aload, then has_srst, has_arst,\n// has_sr cannot be used\n//\n// The valid feature combinations are thus:\n//\n// - has_clk + optional has_ce [dff/dffe]\n// - has_clk + optional has_ce + has_arst [adff/adffe]\n// - has_clk + optional has_ce + has_aload [aldff/aldffe]\n// - has_clk + optional has_ce + has_sr [dffsr/dffsre]\n// - has_clk + optional has_ce + has_srst [sdff/sdffe/sdffce]\n// - has_aload [dlatch]\n// - has_aload + has_arst [adlatch]\n// - has_aload + has_sr [dlatchsr]\n// - has_sr [sr]\n// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]\n// - empty set [not a cell — will be emitted as a simple direct connection]\n\nstruct FfData {\n\tModule *module;\n\tFfInitVals *initvals;\n\tCell *cell;\n\tIdString name;\n\t// The FF output.\n\tSigSpec sig_q;\n\t// The sync data input, present if has_clk or has_gclk.\n\tSigSpec sig_d;\n\t// The async data input, present if has_aload.\n\tSigSpec sig_ad;\n\t// The sync clock, present if has_clk.\n\tSigSpec sig_clk;\n\t// The clock enable, present if has_ce.\n\tSigSpec sig_ce;\n\t// The async load enable, present if has_aload.\n\tSigSpec sig_aload;\n\t// The async reset, preset if has_arst.\n\tSigSpec sig_arst;\n\t// The sync reset, preset if has_srst.\n\tSigSpec sig_srst;\n\t// The async clear (per-lane), present if has_sr.\n\tSigSpec sig_clr;\n\t// The async set (per-lane), present if has_sr.\n\tSigSpec sig_set;\n\t// True if this is a clocked (edge-sensitive) flip-flop.\n\tbool has_clk;\n\t// True if this is a $ff, exclusive with every other has_*.\n\tbool has_gclk;\n\t// True if this FF has a clock enable. Depends on has_clk.\n\tbool has_ce;\n\t// True if this FF has async load function — this includes D latches.\n\t// If this and has_clk are both set, has_arst and has_sr cannot be set.\n\tbool has_aload;\n\t// True if this FF has sync set/reset. Depends on has_clk, exclusive\n\t// with has_arst, has_sr, has_aload.\n\tbool has_srst;\n\t// True if this FF has async set/reset. Exclusive with has_srst,\n\t// has_sr. If this and has_clk are both set, has_aload cannot be set.\n\tbool has_arst;\n\t// True if this FF has per-bit async set + clear. Exclusive with\n\t// has_srst, has_arst. If this and has_clk are both set, has_aload\n\t// cannot be set.\n\tbool has_sr;\n\t// If has_ce and has_srst are both set, determines their relative\n\t// priorities: if true, inactive ce disables srst; if false, srst\n\t// operates independent of ce.\n\tbool ce_over_srst;\n\t// True if this FF is a fine cell, false if it is a coarse cell.\n\t// If true, width must be 1.\n\tbool is_fine;\n\t// True if this FF is an $anyinit cell. Depends on has_gclk.\n\tbool is_anyinit;\n\t// Polarities, corresponding to sig_*.\n\t// True means rising edge, false means falling edge.\n\tbool pol_clk;\n\t// True means active-high, false\n\t// means active-low.\n\tbool pol_ce;\n\tbool pol_aload;\n\tbool pol_arst;\n\tbool pol_srst;\n\tbool pol_clr;\n\tbool pol_set;\n\t// The value loaded by sig_arst.\n\tConst val_arst;\n\t// The value loaded by sig_srst.\n\tConst val_srst;\n\t// The initial value at power-up.\n\tConst val_init;\n\t// The FF data width in bits.\n\tint width;\n\tdict<IdString, Const> attributes;\n\n\tFfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {\n\t\twidth = 0;\n\t\thas_clk = false;\n\t\thas_gclk = false;\n\t\thas_ce = false;\n\t\thas_aload = false;\n\t\thas_srst = false;\n\t\thas_arst = false;\n\t\thas_sr = false;\n\t\tce_over_srst = false;\n\t\tis_fine = false;\n\t\tis_anyinit = false;\n\t\tpol_clk = false;\n\t\tpol_aload = false;\n\t\tpol_ce = false;\n\t\tpol_arst = false;\n\t\tpol_srst = false;\n\t\tpol_clr = false;\n\t\tpol_set = false;\n\t}\n\n\tFfData(FfInitVals *initvals, Cell *cell_);\n\n\t// Returns a FF identical to this one, but only keeping bit indices from the argument.\n\tFfData slice(const std::vector<int> &bits);\n\n\tvoid add_dummy_ce();\n\tvoid add_dummy_srst();\n\tvoid add_dummy_arst();\n\tvoid add_dummy_aload();\n\tvoid add_dummy_sr();\n\tvoid add_dummy_clk();\n\n\tvoid arst_to_aload();\n\tvoid arst_to_sr();\n\n\tvoid aload_to_sr();\n\n\t// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and\n\t// fixes up control signals appropriately to preserve semantics.\n\tvoid convert_ce_over_srst(bool val);\n\n\tvoid unmap_ce();\n\tvoid unmap_srst();\n\n\tvoid unmap_ce_srst() {\n\t\tunmap_ce();\n\t\tunmap_srst();\n\t}\n\n\tCell *emit();\n\n\t// Removes init attribute from the Q output, but keeps val_init unchanged.\n\t// It will be automatically reattached on emit. Use this before changing sig_q.\n\tvoid remove_init() {\n\t\tif (initvals)\n\t\t\tinitvals->remove_init(sig_q);\n\t}\n\n\tvoid remove();\n\n\t// Flip the sense of the given bit slices of the FF: insert inverters on data\n\t// inputs and output, flip the corresponding init/reset bits, swap clr/set\n\t// inputs with proper priority fix.\n\tvoid flip_bits(const pool<int> &bits);\n\n\tvoid flip_rst_bits(const pool<int> &bits);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "ffinit.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFINIT_H\n#define FFINIT_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FfInitVals\n{\n\tconst SigMap *sigmap;\n\tdict<SigBit, std::pair<State,SigBit>> initbits;\n\n\tvoid set(const SigMap *sigmap_, RTLIL::Module *module)\n\t{\n\t\tsigmap = sigmap_;\n\t\tinitbits.clear();\n\t\tfor (auto wire : module->wires())\n\t\t{\n\t\t\tif (wire->attributes.count(ID::init) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tSigSpec wirebits = (*sigmap)(wire);\n\t\t\tConst initval = wire->attributes.at(ID::init);\n\n\t\t\tfor (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)\n\t\t\t{\n\t\t\t\tSigBit bit = wirebits[i];\n\t\t\t\tState val = initval[i];\n\n\t\t\t\tif (val != State::S0 && val != State::S1 && bit.wire != nullptr)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (initbits.count(bit)) {\n\t\t\t\t\tif (initbits.at(bit).first != val)\n\t\t\t\t\t\tlog_error(\"Conflicting init values for signal %s (%s = %s != %s).\\n\",\n\t\t\t\t\t\t\t\tlog_signal(bit), log_signal(SigBit(wire, i)),\n\t\t\t\t\t\t\t\tlog_signal(val), log_signal(initbits.at(bit).first));\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tinitbits[bit] = std::make_pair(val,SigBit(wire,i));\n\t\t\t}\n\t\t}\n\t}\n\n\tRTLIL::State operator()(RTLIL::SigBit bit) const\n\t{\n\t\tauto it = initbits.find((*sigmap)(bit));\n\t\tif (it != initbits.end())\n\t\t\treturn it->second.first;\n\t\telse\n\t\t\treturn State::Sx;\n\t}\n\n\tRTLIL::Const operator()(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::Const res;\n\t\tfor (auto bit : sig)\n\t\t\tres.bits.push_back((*this)(bit));\n\t\treturn res;\n\t}\n\n\tvoid set_init(RTLIL::SigBit bit, RTLIL::State val)\n\t{\n\t\tSigBit mbit = (*sigmap)(bit);\n\t\tSigBit abit = bit;\n\t\tauto it = initbits.find(mbit);\n\t\tif (it != initbits.end())\n\t\t\tabit = it->second.second;\n\t\telse if (val == State::Sx)\n\t\t\treturn;\n\t\tlog_assert(abit.wire);\n\t\tinitbits[mbit] = std::make_pair(val,abit);\n\t\tauto it2 = abit.wire->attributes.find(ID::init);\n\t\tif (it2 != abit.wire->attributes.end()) {\n\t\t\tit2->second[abit.offset] = val;\n\t\t\tif (it2->second.is_fully_undef())\n\t\t\t\tabit.wire->attributes.erase(it2);\n\t\t} else if (val != State::Sx) {\n\t\t\tConst cval(State::Sx, GetSize(abit.wire));\n\t\t\tcval[abit.offset] = val;\n\t\t\tabit.wire->attributes[ID::init] = cval;\n\t\t}\n\t}\n\n\tvoid set_init(const RTLIL::SigSpec &sig, RTLIL::Const val)\n\t{\n\t\tlog_assert(GetSize(sig) == GetSize(val));\n\t\tfor (int i = 0; i < GetSize(sig); i++)\n\t\t\tset_init(sig[i], val[i]);\n\t}\n\n\tvoid remove_init(RTLIL::SigBit bit)\n\t{\n\t\tset_init(bit, State::Sx);\n\t}\n\n\tvoid remove_init(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto bit : sig)\n\t\t\tremove_init(bit);\n\t}\n\n\tvoid clear()\n\t{\n\t\tinitbits.clear();\n\t}\n\n\tFfInitVals (const SigMap *sigmap, RTLIL::Module *module)\n\t{\n\t\tset(sigmap, module);\n\t}\n\n\tFfInitVals () {}\n};\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "ffmerge.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFMERGE_H\n#define FFMERGE_H\n\n#include \"kernel/ffinit.h\"\n#include \"kernel/ff.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// A helper class for passes that want to merge FFs on the input or output\n// of a cell into the cell itself.\n//\n// The procedure is:\n//\n// 1. Construct this class (at beginning of processing for a given module).\n// 2. For every considered cell:\n//\n// a. Call find_output_ff for every considered output.\n// b. Call find_input_ff for every considered input.\n// c. Look at the FF description returned (if any) from each call, reject\n// results that cannot be merged into given cell for any reason.\n// If both inputs and outputs are being merged, take care of FF bits that\n// are returned in both input and output results (a FF bit cannot be\n// merged to both). Decide on the final set of FF bits to merge.\n// d. Call remove_output_ff for every find_output_ff result that will be used\n// for merging. This removes the actual FF bits from design and from index.\n// e. Call mark_input_ff for every find_input_ff result that will be used\n// for merging. This updates the index disallowing further usage of these\n// FF bits for output FF merging, if they were eligible before. The actual\n// FF bits are still left in the design and can be merged into other inputs.\n// If the FF bits are not otherwise used, they will be removed by later\n// opt passes.\n// f. Merge the FFs into the cell.\n//\n// Note that, if both inputs and outputs are being considered for merging in\n// a single pass, the result may be nondeterministic (depending on cell iteration\n// order) because a given FF bit could be eligible for both input and output merge,\n// perhaps in different cells. For this reason, it may be a good idea to separate\n// input and output merging.\n\nstruct FfMergeHelper\n{\n\tconst SigMap *sigmap;\n\tRTLIL::Module *module;\n\tFfInitVals *initvals;\n\n\tdict<SigBit, std::pair<Cell*, int>> dff_driver;\n\tdict<SigBit, pool<std::pair<Cell*, int>>> dff_sink;\n\tdict<SigBit, int> sigbit_users_count;\n\n\t// Returns true if all bits in sig are completely unused.\n\tbool is_output_unused(RTLIL::SigSpec sig);\n\n\t// Finds the FF to merge into a given cell output. Takes sig, which\n\t// is the current cell output — it will be the sig_d of the found FF.\n\t// If found, returns true, and fills the two output arguments.\n\t//\n\t// For every bit of sig, this function finds a FF bit that has\n\t// the same sig_d, and fills the output FfData according to the FF\n\t// bits found. This function will only consider FF bits that are\n\t// the only user of the given sig bits — if any bit in sig is used\n\t// by anything other than a single FF, this function will return false.\n\t//\n\t// The returned FfData structure does not correspond to any actual FF\n\t// cell in the design — it is the amalgamation of extracted FF bits,\n\t// possibly coming from several FF cells.\n\t//\n\t// If some of the bits in sig have no users at all, this function\n\t// will accept them as well (and fill returned FfData with dummy values\n\t// for the given bit, effectively synthesizing an unused FF bit of the\n\t// appropriate type). However, if all bits in sig are completely\n\t// unused, this function will fail and return false (having no idea\n\t// what kind of FF to produce) — use the above helper if that case\n\t// is important to handle.\n\t//\n\t// Note that this function does not remove the FF bits returned from\n\t// the design — this is so that the caller can decide whether to accept\n\t// this FF for merging or not. If the result is accepted,\n\t// remove_output_ff should be called on the second output argument.\n\tbool find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// Like above, but returns a FF to merge into a given cell input. Takes\n\t// sig_q, which is the current cell input — it will search for FFs with\n\t// matching sig_q.\n\t//\n\t// As opposed to find_output_ff, this function doesn't care about usage\n\t// counts, and may return FF bits that also have other fanout. This\n\t// should not be a problem for input FF merging.\n\t//\n\t// As a special case, if some of the bits in sig_q are constant, this\n\t// function will accept them as well, by synthesizing in-place\n\t// a constant-input FF bit (with matching initial value and reset value).\n\t// However, this will not work if the input is all-constant — if the caller\n\t// cares about this case, it needs to check for it explicitely.\n\tbool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_output_ff result that will be merged. This\n\t// marks the given FF bits as used up (and not to be considered for\n\t// further merging as inputs), and reconnects their Q ports to a dummy\n\t// wire (since the wire previously connected there will now be driven\n\t// by the merged-to cell instead).\n\tvoid remove_output_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_input_ff result that will be merged. This\n\t// marks the given FF bits as used, and disallows merging them as\n\t// outputs. They can, however, still be merged as inputs again\n\t// (perhaps for another cell).\n\tvoid mark_input_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\tvoid set(FfInitVals *initvals_, RTLIL::Module *module_);\n\n\tvoid clear();\n\n\tFfMergeHelper(FfInitVals *initvals, RTLIL::Module *module) {\n\t\tset(initvals, module);\n\t}\n\n\tFfMergeHelper() {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "fmt.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n// $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tTIME = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n// \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tLITERAL \t= 0,\n\t\tINTEGER \t= 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign = MINUS;\n\tbool hex_upper = false;\n\tbool show_base = false;\n\tbool group = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_literal(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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- "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <vector>\n\n#include <stdint.h>\n\nnamespace hashlib {\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\n// The XOR version of DJB2\ninline unsigned int mkhash(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) ^ b;\n}\n\n// traditionally 5381 is used as starting value for the djb2 hash\nconst unsigned int mkhash_init = 5381;\n\n// The ADD version of DJB2\n// (use this version for cache locality in b)\ninline unsigned int mkhash_add(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) + b;\n}\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\ntemplate<typename T> struct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const T &a) {\n\t\treturn a.hash();\n\t}\n};\n\nstruct hash_int_ops {\n\ttemplate<typename T>\n\tstatic inline bool cmp(T a, T b) {\n\t\treturn a == b;\n\t}\n};\n\ntemplate<> struct hash_ops<bool> : hash_int_ops\n{\n\tstatic inline unsigned int hash(bool a) {\n\t\treturn a ? 1 : 0;\n\t}\n};\ntemplate<> struct hash_ops<int32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<int64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\ntemplate<> struct hash_ops<uint32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<uint64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\n\ntemplate<> struct hash_ops<std::string> {\n\tstatic inline bool cmp(const std::string &a, const std::string &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const std::string &a) {\n\t\tunsigned int v = 0;\n\t\tfor (auto c : a)\n\t\t\tv = mkhash(v, c);\n\t\treturn v;\n\t}\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::pair<P, Q> a) {\n\t\treturn mkhash(hash_ops<P>::hash(a.first), hash_ops<Q>::hash(a.second));\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), unsigned int>::type hash(std::tuple<T...>) {\n\t\treturn mkhash_init;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), unsigned int>::type hash(std::tuple<T...> a) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\treturn mkhash(hash<I+1>(a), element_ops_t::hash(std::get<I>(a)));\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::vector<T> a) {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto k : a)\n\t\t\th = mkhash(h, hash_ops<T>::hash(k));\n\t\treturn h;\n\t}\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\tfor (int i = 0; a[i] || b[i]; i++)\n\t\t\tif (a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\tstatic inline unsigned int hash(const char *a) {\n\t\tunsigned int hash = mkhash_init;\n\t\twhile (*a)\n\t\t\thash = mkhash(hash, *(a++));\n\t\treturn hash;\n\t}\n};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const void *a) {\n\t\treturn (uintptr_t)a;\n\t}\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\tstatic inline unsigned int hash(const T *a) {\n\t\treturn a ? a->hash() : 0;\n\t}\n};\n\ntemplate<typename T>\ninline unsigned int mkhash(const T &v) {\n\treturn hash_ops<T>().hash(v);\n}\n\ninline int hashtable_size(int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict\n{\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tint hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto &entry : entries) {\n\t\t\th ^= hash_ops<K>::hash(entry.udata.first);\n\t\t\th ^= hash_ops<T>::hash(entry.udata.second);\n\t\t}\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tint hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int hashval = mkhash_init;\n\t\tfor (auto &it : entries)\n\t\t\thashval ^= ops.hash(it.udata);\n\t\treturn hashval;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0, OPS>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
171
+ "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <variant>\n#include <vector>\n\n#include <stdint.h>\n\nnamespace hashlib {\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\n// The XOR version of DJB2\ninline unsigned int mkhash(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) ^ b;\n}\n\n// traditionally 5381 is used as starting value for the djb2 hash\nconst unsigned int mkhash_init = 5381;\n\n// The ADD version of DJB2\n// (use this version for cache locality in b)\ninline unsigned int mkhash_add(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) + b;\n}\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\ntemplate<typename T> struct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const T &a) {\n\t\treturn a.hash();\n\t}\n};\n\nstruct hash_int_ops {\n\ttemplate<typename T>\n\tstatic inline bool cmp(T a, T b) {\n\t\treturn a == b;\n\t}\n};\n\ntemplate<> struct hash_ops<bool> : hash_int_ops\n{\n\tstatic inline unsigned int hash(bool a) {\n\t\treturn a ? 1 : 0;\n\t}\n};\ntemplate<> struct hash_ops<int32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<int64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\ntemplate<> struct hash_ops<uint32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<uint64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\n\ntemplate<> struct hash_ops<std::string> {\n\tstatic inline bool cmp(const std::string &a, const std::string &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const std::string &a) {\n\t\tunsigned int v = 0;\n\t\tfor (auto c : a)\n\t\t\tv = mkhash(v, c);\n\t\treturn v;\n\t}\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::pair<P, Q> a) {\n\t\treturn mkhash(hash_ops<P>::hash(a.first), hash_ops<Q>::hash(a.second));\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), unsigned int>::type hash(std::tuple<T...>) {\n\t\treturn mkhash_init;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), unsigned int>::type hash(std::tuple<T...> a) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\treturn mkhash(hash<I+1>(a), element_ops_t::hash(std::get<I>(a)));\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::vector<T> a) {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto k : a)\n\t\t\th = mkhash(h, hash_ops<T>::hash(k));\n\t\treturn h;\n\t}\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\tfor (int i = 0; a[i] || b[i]; i++)\n\t\t\tif (a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\tstatic inline unsigned int hash(const char *a) {\n\t\tunsigned int hash = mkhash_init;\n\t\twhile (*a)\n\t\t\thash = mkhash(hash, *(a++));\n\t\treturn hash;\n\t}\n};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const void *a) {\n\t\treturn (uintptr_t)a;\n\t}\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\tstatic inline unsigned int hash(const T *a) {\n\t\treturn a ? a->hash() : 0;\n\t}\n};\n\ntemplate<typename T>\ninline unsigned int mkhash(const T &v) {\n\treturn hash_ops<T>().hash(v);\n}\n\ntemplate<> struct hash_ops<std::monostate> {\n\tstatic inline bool cmp(std::monostate a, std::monostate b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::monostate) {\n\t\treturn mkhash_init;\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::variant<T...>> {\n\tstatic inline bool cmp(std::variant<T...> a, std::variant<T...> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::variant<T...> a) {\n\t\tunsigned int h = std::visit([](const auto &v) { return mkhash(v); }, a);\n\t\treturn mkhash(a.index(), h);\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::optional<T>> {\n\tstatic inline bool cmp(std::optional<T> a, std::optional<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::optional<T> a) {\n\t\tif(a.has_value())\n\t\t\treturn mkhash(*a);\n\t\telse\n\t\t\treturn 0;\n\t}\n};\n\ninline int hashtable_size(int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict\n{\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tint hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto &entry : entries) {\n\t\t\th ^= hash_ops<K>::hash(entry.udata.first);\n\t\t\th ^= hash_ops<T>::hash(entry.udata.second);\n\t\t}\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tint hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int hashval = mkhash_init;\n\t\tfor (auto &it : entries)\n\t\t\thashval ^= ops.hash(it.udata);\n\t\treturn hashval;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0, OPS>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
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  "json.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n enum Scope {\n VALUE,\n OBJECT_FIRST,\n OBJECT,\n ARRAY_FIRST,\n ARRAY,\n };\n\n struct Target {\n virtual void emit(const char *data) = 0;\n virtual void flush() {};\n virtual ~Target() {};\n };\n\n std::string newline_indent = \"\\n\";\n std::vector<std::unique_ptr<Target>> targets;\n std::vector<Scope> state = {VALUE};\n int compact_depth = INT_MAX;\npublic:\n\n void emit_to_log();\n void append_to_string(std::string &target);\n bool write_to_file(const std::string &path);\n\n bool active() { return !targets.empty(); }\n\n void compact() { compact_depth = GetSize(state); }\n\n void line(bool space_if_inline = true);\n void raw(const char *raw_json);\n void flush();\n void begin_object();\n void begin_array();\n void end_object();\n void end_array();\n void name(const char *name);\n void begin_value();\n void end_value();\n void value_json(const Json &value);\n void value(unsigned int value) { value_json(Json((int)value)); }\n template<typename T>\n void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n void entry_json(const char *name, const Json &value);\n void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n template<typename T>\n void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n template<typename T>\n void object(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n entry(item.first, item.second);\n end_object();\n }\n\n template<typename T>\n void array(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n value(item);\n end_object();\n }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
172
- "log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T, typename OPS> static inline void log_dump_val_worker(dict<K, T, OPS> &v);\ntemplate<typename K, typename OPS> static inline void log_dump_val_worker(pool<K, OPS> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T, typename OPS>\nstatic inline void log_dump_val_worker(dict<K, T, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K, typename OPS>\nstatic inline void log_dump_val_worker(pool<K, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
173
+ "log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\nconst char *log_str(const char *str);\nconst char *log_str(std::string const &str);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T, typename OPS> static inline void log_dump_val_worker(dict<K, T, OPS> &v);\ntemplate<typename K, typename OPS> static inline void log_dump_val_worker(pool<K, OPS> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T, typename OPS>\nstatic inline void log_dump_val_worker(dict<K, T, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K, typename OPS>\nstatic inline void log_dump_val_worker(pool<K, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
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  "macc.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct port_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\n\tstd::vector<port_t> ports;\n\tRTLIL::SigSpec bit_ports;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<port_t> new_ports;\n\t\tRTLIL::SigSpec new_bit_ports;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {\n\t\t\t\tbit_ports.append(port.in_a);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tfor (auto &bit : bit_ports)\n\t\t\tif (bit == State::S1)\n\t\t\t\toff = const_add(off, RTLIL::Const(1, width), false, false, width);\n\t\t\telse if (bit != State::S0)\n\t\t\t\tnew_bit_ports.append(bit);\n\n\t\tif (off.as_bool()) {\n\t\t\tport_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tnew_ports.swap(ports);\n\t\tbit_ports = new_bit_ports;\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tports.clear();\n\t\tbit_ports = cell->getPort(ID::B);\n\n\t\tstd::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tport_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tports.push_back(this_port);\n\t\t}\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell) const\n\t{\n\t\tRTLIL::SigSpec port_a;\n\t\tstd::vector<RTLIL::State> config_bits;\n\t\tint max_size = 0, num_bits = 0;\n\n\t\tfor (auto &port : ports) {\n\t\t\tmax_size = max(max_size, GetSize(port.in_a));\n\t\t\tmax_size = max(max_size, GetSize(port.in_b));\n\t\t}\n\n\t\twhile (max_size)\n\t\t\tnum_bits++, max_size /= 2;\n\n\t\tlog_assert(num_bits < 16);\n\t\tconfig_bits.push_back(num_bits & 1 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 2 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 4 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 8 ? State::S1 : State::S0);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tconfig_bits.push_back(port.is_signed ? State::S1 : State::S0);\n\t\t\tconfig_bits.push_back(port.do_subtract ? State::S1 : State::S0);\n\n\t\t\tint size_a = GetSize(port.in_a);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tint size_b = GetSize(port.in_b);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tport_a.append(port.in_a);\n\t\t\tport_a.append(port.in_b);\n\t\t}\n\n\t\tcell->setPort(ID::A, port_a);\n\t\tcell->setPort(ID::B, bit_ports);\n\t\tcell->setParam(ID::CONFIG, config_bits);\n\t\tcell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));\n\t\tcell->setParam(ID::A_WIDTH, GetSize(port_a));\n\t\tcell->setParam(ID::B_WIDTH, GetSize(bit_ports));\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits)\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\tfor (auto bit : bit_ports) {\n\t\t\tif (bit.wire)\n\t\t\t\treturn false;\n\t\t\tresult = const_add(result, bit.data, false, false, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
174
- "mem.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MEM_H\n#define MEM_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct MemRd : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity, ce_over_srst;\n\tConst arst_value, srst_value, init_value;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will bypass the written data\n\t// to this port's output (default behavior is to read old value).\n\t// Can only be set for write ports that have the same clock domain.\n\tstd::vector<bool> transparency_mask;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will return an all-X (don't care)\n\t// value. Mutually exclusive with transparency_mask.\n\t// Can only be set for write ports that have the same clock domain.\n\t// For optimization purposes, this will also be set if we can\n\t// determine that the two ports can never be active simultanously\n\t// (making the above vacuously true).\n\tstd::vector<bool> collision_x_mask;\n\tSigSpec clk, en, arst, srst, addr, data;\n\n\tMemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n};\n\nstruct MemWr : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity;\n\tstd::vector<bool> priority_mask;\n\tSigSpec clk, en, addr, data;\n\n\tMemWr() : removed(false), cell(nullptr) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n\n\tstd::pair<SigSpec, std::vector<int>> compress_en();\n\tSigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig);\n};\n\nstruct MemInit : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tConst addr;\n\tConst data;\n\tConst en;\n\tMemInit() : removed(false), cell(nullptr) {}\n};\n\nstruct Mem : RTLIL::AttrObject {\n\tModule *module;\n\tIdString memid;\n\tbool packed;\n\tRTLIL::Memory *mem;\n\tCell *cell;\n\tint width, start_offset, size;\n\tstd::vector<MemInit> inits;\n\tstd::vector<MemRd> rd_ports;\n\tstd::vector<MemWr> wr_ports;\n\n\t// Removes this memory from the module. The data in helper structures\n\t// is unaffected except for the cell/mem fields.\n\tvoid remove();\n\n\t// Commits all changes in helper structures into the module — ports and\n\t// inits marked as removed are actually removed, new ports/inits create\n\t// new cells, modified port/inits are commited into their existing\n\t// cells. Note that this reindexes the ports and inits array (actually\n\t// removing the ports/inits marked as removed).\n\tvoid emit();\n\n\t// Marks all inits as removed.\n\tvoid clear_inits();\n\n\t// Coalesces inits: whenever two inits have overlapping or touching\n\t// address ranges, they are combined into one, with the higher-priority\n\t// one's data overwriting the other. Running this results in\n\t// an inits list equivalent to the original, in which all entries\n\t// cover disjoint (and non-touching) address ranges, and all enable\n\t// masks are all-1.\n\tvoid coalesce_inits();\n\n\t// Checks consistency of this memory and all its ports/inits, using\n\t// log_assert.\n\tvoid check();\n\n\t// Gathers all initialization data into a single big const covering\n\t// the whole memory. For all non-initialized bits, Sx will be returned.\n\tConst get_init_data() const;\n\n\t// Constructs and returns the helper structures for all memories\n\t// in a module.\n\tstatic std::vector<Mem> get_all_memories(Module *module);\n\n\t// Constructs and returns the helper structures for all selected\n\t// memories in a module.\n\tstatic std::vector<Mem> get_selected_memories(Module *module);\n\n\t// Converts a synchronous read port into an asynchronous one by\n\t// extracting the data (or, in some rare cases, address) register\n\t// into a separate cell, together with any soft-transparency\n\t// logic necessary to preserve its semantics. Returns the created\n\t// register cell, if any. Note that in some rare cases this function\n\t// may succeed and perform a conversion without creating a new\n\t// register — a nullptr result doesn't imply nothing was done.\n\tCell *extract_rdff(int idx, FfInitVals *initvals);\n\n\t// Splits all wide ports in this memory into equivalent narrow ones.\n\t// This function performs no modifications at all to the actual\n\t// netlist unless and until emit() is called.\n\tvoid narrow();\n\n\t// If write port idx2 currently has priority over write port idx1,\n\t// inserts extra logic on idx1's enable signal to disable writes\n\t// when idx2 is writing to the same address, then removes the priority\n\t// from the priority mask. If there is a memory port that is\n\t// transparent with idx1, but not with idx2, that port is converted\n\t// to use soft transparency logic.\n\tvoid emulate_priority(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Creates soft-transparency logic on read port ridx, bypassing the\n\t// data from write port widx. Should only be called when ridx is\n\t// transparent wrt widx in the first place. Once we're done, the\n\t// transparency_mask bit will be cleared, and the collision_x_mask\n\t// bit will be set instead (since whatever value is read will be\n\t// replaced by the soft transparency logic).\n\tvoid emulate_transparency(int widx, int ridx, FfInitVals *initvals);\n\n\t// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).\n\t// Specifically, takes care of priority masks: any priority relations\n\t// that idx2 had are replicated onto idx1, unless they conflict with\n\t// priorities already present on idx1, in which case emulate_priority\n\t// is called. Likewise, ensures transparency and undefined collision\n\t// masks of all read ports have the same values for both ports,\n\t// calling emulate_transparency if necessary.\n\tvoid prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares for merging read port idx2 into idx1.\n\t// Specifically, makes sure the transparency and undefined collision\n\t// masks of both ports are equal, by changing undefined behavior\n\t// of one port to the other's defined behavior, or by calling\n\t// emulate_transparency if necessary.\n\tvoid prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares the memory for widening a port to a given width. This\n\t// involves ensuring that start_offset and size are aligned to the\n\t// target width.\n\tvoid widen_prep(int wide_log2);\n\n\t// Widens a write port up to a given width. The newly port is\n\t// equivalent to the original, made by replicating enable/data bits\n\t// and masking enable bits with decoders on the low part of the\n\t// original address.\n\tvoid widen_wr_port(int idx, int wide_log2);\n\n\t// Emulates a sync read port's enable functionality in soft logic,\n\t// changing the actual read port's enable to be always-on.\n\tvoid emulate_rden(int idx, FfInitVals *initvals);\n\n\t// Emulates a sync read port's initial/reset value functionality in\n\t// soft logic, removing it from the actual read port.\n\tvoid emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals);\n\n\t// Given a read port with ce_over_srst set, converts it to a port\n\t// with ce_over_srst unset without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_ce_over_srst(int idx);\n\n\t// Given a read port with ce_over_srst unset, converts it to a port\n\t// with ce_over_srst set without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_srst_over_ce(int idx);\n\n\t// Returns true iff emulate_read_first makes sense to call.\n\tbool emulate_read_first_ok();\n\n\t// Emulates all read-first read-write port relationships in terms of\n\t// all-transparent ports, by delaying all write ports by one cycle.\n\t// This can only be used when all read ports and all write ports are\n\t// in the same clock domain.\n\tvoid emulate_read_first(FfInitVals *initvals);\n\n\tMem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
175
+ "mem.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MEM_H\n#define MEM_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n#include \"kernel/utils.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct MemRd : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity, ce_over_srst;\n\tConst arst_value, srst_value, init_value;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will bypass the written data\n\t// to this port's output (default behavior is to read old value).\n\t// Can only be set for write ports that have the same clock domain.\n\tstd::vector<bool> transparency_mask;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will return an all-X (don't care)\n\t// value. Mutually exclusive with transparency_mask.\n\t// Can only be set for write ports that have the same clock domain.\n\t// For optimization purposes, this will also be set if we can\n\t// determine that the two ports can never be active simultanously\n\t// (making the above vacuously true).\n\tstd::vector<bool> collision_x_mask;\n\tSigSpec clk, en, arst, srst, addr, data;\n\n\tMemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n};\n\nstruct MemWr : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity;\n\tstd::vector<bool> priority_mask;\n\tSigSpec clk, en, addr, data;\n\n\tMemWr() : removed(false), cell(nullptr) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n\n\tstd::pair<SigSpec, std::vector<int>> compress_en();\n\tSigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig);\n};\n\nstruct MemInit : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tConst addr;\n\tConst data;\n\tConst en;\n\tMemInit() : removed(false), cell(nullptr) {}\n};\n\nstruct Mem : RTLIL::AttrObject {\n\tModule *module;\n\tIdString memid;\n\tbool packed;\n\tRTLIL::Memory *mem;\n\tCell *cell;\n\tint width, start_offset, size;\n\tstd::vector<MemInit> inits;\n\tstd::vector<MemRd> rd_ports;\n\tstd::vector<MemWr> wr_ports;\n\n\t// Removes this memory from the module. The data in helper structures\n\t// is unaffected except for the cell/mem fields.\n\tvoid remove();\n\n\t// Commits all changes in helper structures into the module — ports and\n\t// inits marked as removed are actually removed, new ports/inits create\n\t// new cells, modified port/inits are commited into their existing\n\t// cells. Note that this reindexes the ports and inits array (actually\n\t// removing the ports/inits marked as removed).\n\tvoid emit();\n\n\t// Marks all inits as removed.\n\tvoid clear_inits();\n\n\t// Coalesces inits: whenever two inits have overlapping or touching\n\t// address ranges, they are combined into one, with the higher-priority\n\t// one's data overwriting the other. Running this results in\n\t// an inits list equivalent to the original, in which all entries\n\t// cover disjoint (and non-touching) address ranges, and all enable\n\t// masks are all-1.\n\tvoid coalesce_inits();\n\n\t// Checks consistency of this memory and all its ports/inits, using\n\t// log_assert.\n\tvoid check();\n\n\t// Gathers all initialization data into a single big const covering\n\t// the whole memory. For all non-initialized bits, Sx will be returned.\n\tConst get_init_data() const;\n\n\t// Constructs and returns the helper structures for all memories\n\t// in a module.\n\tstatic std::vector<Mem> get_all_memories(Module *module);\n\n\t// Constructs and returns the helper structures for all selected\n\t// memories in a module.\n\tstatic std::vector<Mem> get_selected_memories(Module *module);\n\n\t// Converts a synchronous read port into an asynchronous one by\n\t// extracting the data (or, in some rare cases, address) register\n\t// into a separate cell, together with any soft-transparency\n\t// logic necessary to preserve its semantics. Returns the created\n\t// register cell, if any. Note that in some rare cases this function\n\t// may succeed and perform a conversion without creating a new\n\t// register — a nullptr result doesn't imply nothing was done.\n\tCell *extract_rdff(int idx, FfInitVals *initvals);\n\n\t// Splits all wide ports in this memory into equivalent narrow ones.\n\t// This function performs no modifications at all to the actual\n\t// netlist unless and until emit() is called.\n\tvoid narrow();\n\n\t// If write port idx2 currently has priority over write port idx1,\n\t// inserts extra logic on idx1's enable signal to disable writes\n\t// when idx2 is writing to the same address, then removes the priority\n\t// from the priority mask. If there is a memory port that is\n\t// transparent with idx1, but not with idx2, that port is converted\n\t// to use soft transparency logic.\n\tvoid emulate_priority(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Creates soft-transparency logic on read port ridx, bypassing the\n\t// data from write port widx. Should only be called when ridx is\n\t// transparent wrt widx in the first place. Once we're done, the\n\t// transparency_mask bit will be cleared, and the collision_x_mask\n\t// bit will be set instead (since whatever value is read will be\n\t// replaced by the soft transparency logic).\n\tvoid emulate_transparency(int widx, int ridx, FfInitVals *initvals);\n\n\t// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).\n\t// Specifically, takes care of priority masks: any priority relations\n\t// that idx2 had are replicated onto idx1, unless they conflict with\n\t// priorities already present on idx1, in which case emulate_priority\n\t// is called. Likewise, ensures transparency and undefined collision\n\t// masks of all read ports have the same values for both ports,\n\t// calling emulate_transparency if necessary.\n\tvoid prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares for merging read port idx2 into idx1.\n\t// Specifically, makes sure the transparency and undefined collision\n\t// masks of both ports are equal, by changing undefined behavior\n\t// of one port to the other's defined behavior, or by calling\n\t// emulate_transparency if necessary.\n\tvoid prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares the memory for widening a port to a given width. This\n\t// involves ensuring that start_offset and size are aligned to the\n\t// target width.\n\tvoid widen_prep(int wide_log2);\n\n\t// Widens a write port up to a given width. The newly port is\n\t// equivalent to the original, made by replicating enable/data bits\n\t// and masking enable bits with decoders on the low part of the\n\t// original address.\n\tvoid widen_wr_port(int idx, int wide_log2);\n\n\t// Emulates a sync read port's enable functionality in soft logic,\n\t// changing the actual read port's enable to be always-on.\n\tvoid emulate_rden(int idx, FfInitVals *initvals);\n\n\t// Emulates a sync read port's initial/reset value functionality in\n\t// soft logic, removing it from the actual read port.\n\tvoid emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals);\n\n\t// Given a read port with ce_over_srst set, converts it to a port\n\t// with ce_over_srst unset without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_ce_over_srst(int idx);\n\n\t// Given a read port with ce_over_srst unset, converts it to a port\n\t// with ce_over_srst set without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_srst_over_ce(int idx);\n\n\t// Returns true iff emulate_read_first makes sense to call.\n\tbool emulate_read_first_ok();\n\n\t// Emulates all read-first read-write port relationships in terms of\n\t// all-transparent ports, by delaying all write ports by one cycle.\n\t// This can only be used when all read ports and all write ports are\n\t// in the same clock domain.\n\tvoid emulate_read_first(FfInitVals *initvals);\n\n\tMem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}\n};\n\n// MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined\nclass MemContents {\npublic:\n\tclass range; class iterator;\n\tusing addr_t = uint32_t;\nprivate:\n\t// we ban _addr_width == sizeof(addr_t) * 8 because it adds too many cornercases\n\tint _addr_width;\n\tint _data_width;\n\tRTLIL::Const _default_value;\n\t// for each range, store the concatenation of the words at the start address\n\t// invariants:\n\t// - no overlapping or adjacent ranges\n\t// - no empty ranges\n\t// - all Consts are a multiple of the word size\n\tstd::map<addr_t, RTLIL::Const> _values;\n\t// returns an iterator to the range containing addr, if it exists, or the first range past addr\n\tstd::map<addr_t, RTLIL::Const>::iterator _range_at(addr_t addr) const;\n\taddr_t _range_size(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->second.size() / _data_width; }\n\taddr_t _range_begin(std::map<addr_t, RTLIL::Const>::iterator it) const { return it->first; }\n\taddr_t _range_end(std::map<addr_t, RTLIL::Const>::iterator it) const { return _range_begin(it) + _range_size(it); }\n\t// check if the iterator points to a range containing addr\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const;\n\t// check if the iterator points to a range containing [begin_addr, end_addr). assumes end_addr >= begin_addr.\n\tbool _range_contains(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// check if the iterator points to a range overlapping with [begin_addr, end_addr)\n\tbool _range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, addr_t begin_addr, addr_t end_addr) const;\n\t// return the offset the addr would have in the range at `it`\n\tsize_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }\n\t// assuming _range_contains(it, addr), return an iterator pointing to the data at addr\n\tstd::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits.begin() + _range_offset(it, addr); }\n\t// internal version of reserve_range that returns an iterator to the range\n\tstd::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);\n\t// write a single word at addr, return iterator to next word\n\tstd::vector<State>::iterator _range_write(std::vector<State>::iterator it, RTLIL::Const const &data);\npublic:\n\tclass range {\n\t\tint _data_width;\n\t\taddr_t _base;\n\t\tRTLIL::Const const &_values;\n\t\tfriend class iterator;\n\t\trange(int data_width, addr_t base, RTLIL::Const const &values)\n\t\t: _data_width(data_width), _base(base), _values(values) {}\n\tpublic:\n\t\taddr_t base() const { return _base; }\n\t\taddr_t size() const { return ((addr_t) _values.size()) / _data_width; }\n\t\taddr_t limit() const { return _base + size(); }\n\t\tRTLIL::Const const &concatenated() const { return _values; }\n\t\tRTLIL::Const operator[](addr_t addr) const {\n\t\t\tlog_assert(addr - _base < size());\n\t\t\treturn _values.extract((addr - _base) * _data_width, _data_width);\n\t\t}\n\t\tRTLIL::Const at_offset(addr_t offset) const { return (*this)[_base + offset]; }\n\t};\n\tclass iterator {\n\t\tMemContents const *_memory;\n\t\t// storing addr instead of an iterator gives more well-defined behaviour under insertions/deletions\n\t\t// use ~0 for end so that all end iterators compare the same\n\t\taddr_t _addr;\n\t\tfriend class MemContents;\n\t\titerator(MemContents const *memory, addr_t addr) : _memory(memory), _addr(addr) {}\n\tpublic:\n\t\tusing iterator_category = std::input_iterator_tag;\n\t\tusing value_type = range;\n\t\tusing pointer = arrow_proxy<range>;\n\t\tusing reference = range;\n\t\tusing difference_type = addr_t;\n\t\treference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); }\n\t\tpointer operator->() const { return arrow_proxy<range>(**this); }\n\t\tbool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; }\n\t\tbool operator ==(iterator const &other) const { return !(*this != other); }\n\t\titerator &operator++();\n\t};\n\tMemContents(int addr_width, int data_width, RTLIL::Const default_value)\n\t\t: _addr_width(addr_width), _data_width(data_width)\n\t\t, _default_value((default_value.extu(data_width), std::move(default_value)))\n\t{ log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); log_assert(_data_width > 0); }\n\tMemContents(int addr_width, int data_width) : MemContents(addr_width, data_width, RTLIL::Const(State::Sx, data_width)) {}\n\texplicit MemContents(Mem *mem);\n\tint addr_width() const { return _addr_width; }\n\tint data_width() const { return _data_width; }\n\tRTLIL::Const const &default_value() const { return _default_value; }\n\t// return the value at the address if it exists, the default_value of the memory otherwise. address must not exceed 2**addr_width.\n\tRTLIL::Const operator [](addr_t addr) const;\n\t// return the number of defined words in the range [begin_addr, end_addr)\n\taddr_t count_range(addr_t begin_addr, addr_t end_addr) const;\n\t// allocate memory for the range [begin_addr, end_addr), but leave the contents undefined.\n\tvoid reserve_range(addr_t begin_addr, addr_t end_addr) { _reserve_range(begin_addr, end_addr); }\n\t// insert multiple words (provided as a single concatenated RTLIL::Const) at the given address, overriding any previous assignment.\n\tvoid insert_concatenated(addr_t addr, RTLIL::Const const &values);\n\t// insert multiple words at the given address, overriding any previous assignment.\n\ttemplate<typename Iterator> void insert_range(addr_t addr, Iterator begin, Iterator end) {\n\t\tauto words = end - begin;\n\t\tlog_assert(addr < (addr_t)(1<<_addr_width)); log_assert(words <= (addr_t)(1<<_addr_width) - addr);\n\t\tauto range = _reserve_range(addr, addr + words);\n\t\tauto it = _range_data(range, addr);\n\t\tfor(; begin != end; ++begin)\n\t\t\tit = _range_write(it, *begin);\n\t}\n\t// undefine all words in the range [begin_addr, end_addr)\n\tvoid clear_range(addr_t begin_addr, addr_t end_addr);\n\t// check invariants, abort if invariants failed\n\tvoid check();\n\titerator end() const { return iterator(nullptr, ~(addr_t) 0); }\n\titerator begin() const { return _values.empty() ? end() : iterator(this, _values.begin()->first); }\n\tbool empty() const { return _values.empty(); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "modtools.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MODTOOLS_H\n#define MODTOOLS_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ModIndex : public RTLIL::Monitor\n{\n\tstruct PortInfo {\n\t\tRTLIL::Cell* cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tPortInfo() : cell(), port(), offset() { }\n\t\tPortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }\n\n\t\tbool operator<(const PortInfo &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (offset != other.offset)\n\t\t\t\treturn offset < other.offset;\n\t\t\treturn port < other.port;\n\t\t}\n\n\t\tbool operator==(const PortInfo &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t\t}\n\t};\n\n\tstruct SigBitInfo\n\t{\n\t\tbool is_input, is_output;\n\t\tpool<PortInfo> ports;\n\n\t\tSigBitInfo() : is_input(false), is_output(false) { }\n\n\t\tbool operator==(const SigBitInfo &other) const {\n\t\t\treturn is_input == other.is_input && is_output == other.is_output && ports == other.ports;\n\t\t}\n\n\t\tvoid merge(const SigBitInfo &other)\n\t\t{\n\t\t\tis_input = is_input || other.is_input;\n\t\t\tis_output = is_output || other.is_output;\n\t\t\tports.insert(other.ports.begin(), other.ports.end());\n\t\t}\n\t};\n\n\tSigMap sigmap;\n\tRTLIL::Module *module;\n\tstd::map<RTLIL::SigBit, SigBitInfo> database;\n\tint auto_reload_counter;\n\tbool auto_reload_module;\n\n\tvoid port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.insert(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tvoid port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.erase(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tconst SigBitInfo &info(RTLIL::SigBit bit)\n\t{\n\t\treturn database[sigmap(bit)];\n\t}\n\n\tvoid reload_module(bool reset_sigmap = true)\n\t{\n\t\tif (reset_sigmap) {\n\t\t\tsigmap.clear();\n\t\t\tsigmap.set(module);\n\t\t}\n\n\t\tdatabase.clear();\n\t\tfor (auto wire : module->wires())\n\t\t\tif (wire->port_input || wire->port_output)\n\t\t\t\tfor (int i = 0; i < GetSize(wire); i++) {\n\t\t\t\t\tRTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));\n\t\t\t\t\tif (bit.wire && wire->port_input)\n\t\t\t\t\t\tdatabase[bit].is_input = true;\n\t\t\t\t\tif (bit.wire && wire->port_output)\n\t\t\t\t\t\tdatabase[bit].is_output = true;\n\t\t\t\t}\n\t\tfor (auto cell : module->cells())\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tport_add(cell, conn.first, conn.second);\n\n\t\tif (auto_reload_module) {\n\t\t\tif (++auto_reload_counter > 2)\n\t\t\t\tlog_warning(\"Auto-reload in ModIndex -- possible performance bug!\\n\");\n\t\t\tauto_reload_module = false;\n\t\t}\n\t}\n\n\tvoid check()\n\t{\n#ifndef NDEBUG\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (auto it : database)\n\t\t\tlog_assert(it.first == sigmap(it.first));\n\n\t\tauto database_bak = std::move(database);\n\t\treload_module(false);\n\n\t\tif (!(database == database_bak))\n\t\t{\n\t\t\tfor (auto &it : database_bak)\n\t\t\t\tif (!database.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database_bak, not database: %s\\n\", log_signal(it.first));\n\n\t\t\tfor (auto &it : database)\n\t\t\t\tif (!database_bak.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database, not database_bak: %s\\n\", log_signal(it.first));\n\t\t\t\telse if (!(it.second == database_bak.at(it.first)))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Different content for database[%s].\\n\", log_signal(it.first));\n\n\t\t\tlog_assert(database == database_bak);\n\t\t}\n#endif\n\t}\n\n\tvoid notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override\n\t{\n\t\tlog_assert(module == cell->module);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tport_del(cell, port, old_sig);\n\t\tport_add(cell, port, sig);\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override\n\t{\n\t\tlog_assert(module == mod);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (int i = 0; i < GetSize(sigsig.first); i++)\n\t\t{\n\t\t\tRTLIL::SigBit lhs = sigmap(sigsig.first[i]);\n\t\t\tRTLIL::SigBit rhs = sigmap(sigsig.second[i]);\n\t\t\tbool has_lhs = database.count(lhs) != 0;\n\t\t\tbool has_rhs = database.count(rhs) != 0;\n\n\t\t\tif (!has_lhs && !has_rhs) {\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t} else\n\t\t\tif (!has_rhs) {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\tlhs = sigmap(lhs);\n\t\t\t\tif (lhs.wire)\n\t\t\t\t\tdatabase[lhs] = new_info;\n\t\t\t} else\n\t\t\tif (!has_lhs) {\n\t\t\t\tSigBitInfo new_info = database.at(rhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t} else {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tnew_info.merge(database.at(rhs));\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tvoid notify_blackout(RTLIL::Module *mod) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)\n\t{\n\t\tauto_reload_counter = 0;\n\t\tauto_reload_module = true;\n\t\tmodule->monitors.insert(this);\n\t}\n\n\t~ModIndex()\n\t{\n\t\tmodule->monitors.erase(this);\n\t}\n\n\tSigBitInfo *query(RTLIL::SigBit bit)\n\t{\n\t\tif (auto_reload_module)\n\t\t\treload_module();\n\n\t\tauto it = database.find(sigmap(bit));\n\t\tif (it == database.end())\n\t\t\treturn nullptr;\n\t\telse\n\t\t\treturn &it->second;\n\t}\n\n\tbool query_is_input(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_input;\n\t}\n\n\tbool query_is_output(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_output;\n\t}\n\n\tpool<PortInfo> &query_ports(RTLIL::SigBit bit)\n\t{\n\t\tstatic pool<PortInfo> empty_result_set;\n\t\tSigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn empty_result_set;\n\t\treturn info->ports;\n\t}\n\n\tvoid dump_db()\n\t{\n\t\tlog(\"--- ModIndex Dump ---\\n\");\n\n\t\tif (auto_reload_module) {\n\t\t\tlog(\"AUTO-RELOAD\\n\");\n\t\t\treload_module();\n\t\t}\n\n\t\tfor (auto &it : database) {\n\t\t\tlog(\"BIT %s:\\n\", log_signal(it.first));\n\t\t\tif (it.second.is_input)\n\t\t\t\tlog(\" PRIMARY INPUT\\n\");\n\t\t\tif (it.second.is_output)\n\t\t\t\tlog(\" PRIMARY OUTPUT\\n\");\n\t\t\tfor (auto &port : it.second.ports)\n\t\t\t\tlog(\" PORT: %s.%s[%d] (%s)\\n\", log_id(port.cell),\n\t\t\t\t\t\tlog_id(port.port), port.offset, log_id(port.cell->type));\n\t\t}\n\t}\n};\n\nstruct ModWalker\n{\n\tstruct PortBit\n\t{\n\t\tRTLIL::Cell *cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tbool operator<(const PortBit &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (port != other.port)\n\t\t\t\treturn port < other.port;\n\t\t\treturn offset < other.offset;\n\t\t}\n\n\t\tbool operator==(const PortBit &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t\t}\n\t};\n\n\tRTLIL::Design *design;\n\tRTLIL::Module *module;\n\n\tCellTypes ct;\n\tSigMap sigmap;\n\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_drivers;\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_consumers;\n\tpool<RTLIL::SigBit> signal_inputs, signal_outputs;\n\n\tdict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;\n\n\tvoid add_wire(RTLIL::Wire *wire)\n\t{\n\t\tif (wire->port_input) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_inputs.insert(bit);\n\t\t}\n\n\t\tif (wire->port_output) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_outputs.insert(bit);\n\t\t}\n\t}\n\n\tvoid add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)\n\t{\n\t\tfor (int i = 0; i < int(bits.size()); i++)\n\t\t\tif (bits[i].wire != NULL) {\n\t\t\t\tPortBit pbit = { cell, port, i };\n\t\t\t\tif (is_output) {\n\t\t\t\t\tsignal_drivers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_outputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t\tif (is_input) {\n\t\t\t\t\tsignal_consumers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_inputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\tvoid add_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (ct.cell_known(cell->type)) {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second),\n\t\t\t\t\t\tct.cell_output(cell->type, conn.first),\n\t\t\t\t\t\tct.cell_input(cell->type, conn.first));\n\t\t} else {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second), true, true);\n\t\t}\n\t}\n\n\tModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)\n\t{\n\t\tct.setup(design);\n\t\tif (module)\n\t\t\tsetup(module);\n\t}\n\n\tvoid setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)\n\t{\n\t\tthis->module = module;\n\n\t\tsigmap.set(module);\n\n\t\tsignal_drivers.clear();\n\t\tsignal_consumers.clear();\n\t\tsignal_inputs.clear();\n\t\tsignal_outputs.clear();\n\t\tcell_inputs.clear();\n\t\tcell_outputs.clear();\n\n\t\tfor (auto &it : module->wires_)\n\t\t\tadd_wire(it.second);\n\t\tfor (auto &it : module->cells_)\n\t\t\tif (filter_ct == NULL || filter_ct->cell_known(it.second->type))\n\t\t\t\tadd_cell(it.second);\n\t}\n\n\t// get_* methods -- single RTLIL::SigBit\n\n\tinline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_drivers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_consumers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_inputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_outputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- container of RTLIL::SigBit's (always by reference)\n\n\ttemplate<typename T>\n\tinline bool get_drivers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_drivers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_consumers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_consumers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_inputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_outputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- call by RTLIL::SigSpec (always by value)\n\n\tbool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_drivers(result, bits);\n\t}\n\n\tbool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_consumers(result, bits);\n\t}\n\n\tbool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_inputs(result, bits);\n\t}\n\n\tbool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_outputs(result, bits);\n\t}\n\n\t// has_* methods -- call by reference\n\n\ttemplate<typename T>\n\tinline bool has_drivers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_consumers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_inputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_outputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n\n\t// has_* methods -- call by value\n\n\tinline bool has_drivers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\tinline bool has_consumers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\tinline bool has_inputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\tinline bool has_outputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "qcsat.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef QCSAT_H\n#define QCSAT_H\n\n#include \"kernel/satgen.h\"\n#include \"kernel/modtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// This is a helper class meant for easy construction of quick SAT queries\n// to a combinatorial input cone of some set of signals, meant for SAT-based\n// optimizations. Various knobs are provided to set just how much of the\n// cone should be included in the model — since this class is meant for\n// optimization, it should not be a correctness problem when some cells are\n// skipped and the solver spuriously returns SAT with a solution that\n// cannot exist in reality due to skipped constraints (ie. only UNSAT results\n// from this class should be considered binding).\nstruct QuickConeSat {\n\tModWalker &modwalker;\n\tezSatPtr ez;\n\tSatGen satgen;\n\n\t// The effort level knobs.\n\n\t// The maximum \"complexity level\" of cells that will be imported.\n\t// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa\n\t// - 2: addition, subtraction, greater/less than comparisons, lcu\n\t// - 3: shifts\n\t// - 4: multiplication, division, power\n\tint max_cell_complexity = 2;\n\t// The maximum number of cells to import, or 0 for no limit.\n\tint max_cell_count = 0;\n\t// If non-0, skip importing cells with more than this number of output bits.\n\tint max_cell_outs = 0;\n\n\t// Internal state.\n\tpool<RTLIL::Cell*> imported_cells;\n\tpool<RTLIL::Wire*> imported_onehot;\n\tpool<RTLIL::SigBit> bits_queue;\n\n\tQuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}\n\n\t// Imports a signal into the SAT solver, queues its input cone to be\n\t// imported in the next prepare() call.\n\tstd::vector<int> importSig(SigSpec sig);\n\tint importSigBit(SigBit bit);\n\n\t// Imports the input cones of all previously importSig'd signals into\n\t// the SAT solver.\n\tvoid prepare();\n\n\t// Returns the \"complexity level\" of a given cell.\n\tstatic int cell_complexity(RTLIL::Cell *cell);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "register.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
178
- "rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct IdString\n\t{\n\t\t#undef YOSYS_XTRACE_GET_PUT\n\t\t#undef YOSYS_SORT_ID_FREE_LIST\n\t\t#undef YOSYS_USE_STICKY_IDS\n\t\t#undef YOSYS_NO_IDS_REFCNT\n\n\t\t// the global id string cache\n\n\t\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\t\tstatic struct destruct_guard_t {\n\t\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t\t} destruct_guard;\n\n\t\tstatic std::vector<char*> global_id_storage_;\n\t\tstatic dict<char*, int, hash_cstr_ops> global_id_index_;\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic std::vector<int> global_refcount_storage_;\n\t\tstatic std::vector<int> global_free_idx_list_;\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tstatic int last_created_idx_ptr_;\n\t\tstatic int last_created_idx_[8];\n\t#endif\n\n\t\tstatic inline void xtrace_db_dump()\n\t\t{\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t\t{\n\t\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\t\telse\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\t\t}\n\n\t\tstatic inline void checkpoint()\n\t\t{\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\tlast_created_idx_ptr_ = 0;\n\t\t\tfor (int i = 0; i < 8; i++) {\n\t\t\t\tif (last_created_idx_[i])\n\t\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\t\tlast_created_idx_[i] = 0;\n\t\t\t}\n\t\t#endif\n\t\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t\t#endif\n\t\t}\n\n\t\tstatic inline int get_reference(int idx)\n\t\t{\n\t\t\tif (idx) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_[idx]++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\t\t\t}\n\t\t\treturn idx;\n\t\t}\n\n\t\tstatic int get_reference(const char *p)\n\t\t{\n\t\t\tlog_assert(destruct_guard_ok);\n\n\t\t\tif (!p[0])\n\t\t\t\treturn 0;\n\n\t\t\tauto it = global_id_index_.find((char*)p);\n\t\t\tif (it != global_id_index_.end()) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t\t#endif\n\t\t\t\treturn it->second;\n\t\t\t}\n\n\t\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\t\tlog_assert(p[1] != 0);\n\t\t\tfor (const char *c = p; *c; c++)\n\t\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tif (global_free_idx_list_.empty()) {\n\t\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t\t}\n\t\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t}\n\n\t\t\tint idx = global_free_idx_list_.back();\n\t\t\tglobal_free_idx_list_.pop_back();\n\t\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\t\tglobal_refcount_storage_.at(idx)++;\n\t\t#else\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tint idx = global_id_storage_.size();\n\t\t\tglobal_id_storage_.push_back(strdup(p));\n\t\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t\t#endif\n\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\t// Avoid Create->Delete->Create pattern\n\t\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t\t#endif\n\n\t\t\treturn idx;\n\t\t}\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic inline void put_reference(int idx)\n\t\t{\n\t\t\t// put_reference() may be called from destructors after the destructor of\n\t\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\t\tif (!destruct_guard_ok || !idx)\n\t\t\t\treturn;\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\n\t\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\t\tif (--refcount > 0)\n\t\t\t\treturn;\n\n\t\t\tlog_assert(refcount == 0);\n\t\t\tfree_reference(idx);\n\t\t}\n\t\tstatic inline void free_reference(int idx)\n\t\t{\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\t\tfree(global_id_storage_.at(idx));\n\t\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\t\tglobal_free_idx_list_.push_back(idx);\n\t\t}\n\t#else\n\t\tstatic inline void put_reference(int) { }\n\t#endif\n\n\t\t// the actual IdString object is just is a single int\n\n\t\tint index_;\n\n\t\tinline IdString() : index_(0) { }\n\t\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\t\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\t\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\t\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\t\tinline ~IdString() { put_reference(index_); }\n\n\t\tinline void operator=(const IdString &rhs) {\n\t\t\tput_reference(index_);\n\t\t\tindex_ = get_reference(rhs.index_);\n\t\t}\n\n\t\tinline void operator=(const char *rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline void operator=(const std::string &rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline const char *c_str() const {\n\t\t\treturn global_id_storage_.at(index_);\n\t\t}\n\n\t\tinline std::string str() const {\n\t\t\treturn std::string(global_id_storage_.at(index_));\n\t\t}\n\n\t\tinline bool operator<(const IdString &rhs) const {\n\t\t\treturn index_ < rhs.index_;\n\t\t}\n\n\t\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\t\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\t\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\t\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\t\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\t\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\t\tchar operator[](size_t i) const {\n const char *p = c_str();\n#ifndef NDEBUG\n\t\t\tfor (; i != 0; i--, p++)\n\t\t\t\tlog_assert(*p != 0);\n\t\t\treturn *p;\n#else\n\t\t\treturn *(p + i);\n#endif\n\t\t}\n\n\t\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\t\treturn std::string(c_str() + pos);\n\t\t\telse\n\t\t\t\treturn std::string(c_str() + pos, len);\n\t\t}\n\n\t\tint compare(size_t pos, size_t len, const char* s) const {\n\t\t\treturn strncmp(c_str()+pos, s, len);\n\t\t}\n\n\t\tbool begins_with(const char* prefix) const {\n\t\t\tsize_t len = strlen(prefix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(0, len, prefix) == 0;\n\t\t}\n\n\t\tbool ends_with(const char* suffix) const {\n\t\t\tsize_t len = strlen(suffix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(size()-len, len, suffix) == 0;\n\t\t}\n\n\t\tbool contains(const char* str) const {\n\t\t\treturn strstr(c_str(), str);\n\t\t}\n\n\t\tsize_t size() const {\n\t\t\treturn strlen(c_str());\n\t\t}\n\n\t\tbool empty() const {\n\t\t\treturn c_str()[0] == 0;\n\t\t}\n\n\t\tvoid clear() {\n\t\t\t*this = IdString();\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn index_;\n\t\t}\n\n\t\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t\t// set has an influence on the algorithm.\n\n\t\ttemplate<typename T> struct compare_ptr_by_name {\n\t\t\tbool operator()(const T *a, const T *b) const {\n\t\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t\t}\n\t\t};\n\n\t\t// often one needs to check if a given IdString is part of a list (for example a list\n\t\t// of cell types). the following functions helps with that.\n\n\t\ttemplate<typename... Args>\n\t\tbool in(Args... args) const {\n\t\t\t// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html\n\t\t\tbool result = false;\n\t\t\t(void) std::initializer_list<int>{ (result = result || in(args), 0)... };\n\t\t\treturn result;\n\t\t}\n\n\t\tbool in(const IdString &rhs) const { return *this == rhs; }\n\t\tbool in(const char *rhs) const { return *this == rhs; }\n\t\tbool in(const std::string &rhs) const { return *this == rhs; }\n\t\tbool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n\n\t\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\t};\n\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tint flags;\n\tstd::vector<RTLIL::State> bits;\n\n\tConst() : flags(RTLIL::CONST_FLAG_NONE) {}\n\tConst(const std::string &str);\n\tConst(int val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &c) = default;\n\tRTLIL::Const &operator =(const RTLIL::Const &other) = default;\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tstatic Const from_string(const std::string &str);\n\n\tstd::string decode_string() const;\n\n\tinline int size() const { return bits.size(); }\n\tinline bool empty() const { return bits.empty(); }\n\tinline RTLIL::State &operator[](int index) { return bits.at(index); }\n\tinline const RTLIL::State &operator[](int index) const { return bits.at(index); }\n\tinline decltype(bits)::iterator begin() { return bits.begin(); }\n\tinline decltype(bits)::iterator end() { return bits.end(); }\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tinline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {\n\t\tRTLIL::Const ret;\n\t\tret.bits.reserve(len);\n\t\tfor (int i = offset; i < offset + len; i++)\n\t\t\tret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);\n\t\treturn ret;\n\t}\n\n\tvoid extu(int width) {\n\t\tbits.resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());\n\t}\n\n\tinline unsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto b : bits)\n\t\t\th = mkhash(h, b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\tunsigned int hash() const;\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tunsigned long hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tsize_t get_hash() const {\n\t\tif (!hash_) hash();\n\t\treturn hash_;\n\t}\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\tunsigned int hash() const { if (!hash_) updhash(); return hash_; };\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline unsigned int RTLIL::SigBit::hash() const {\n\tif (wire)\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\treturn data;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
179
+ "rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct IdString\n\t{\n\t\t#undef YOSYS_XTRACE_GET_PUT\n\t\t#undef YOSYS_SORT_ID_FREE_LIST\n\t\t#undef YOSYS_USE_STICKY_IDS\n\t\t#undef YOSYS_NO_IDS_REFCNT\n\n\t\t// the global id string cache\n\n\t\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\t\tstatic struct destruct_guard_t {\n\t\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t\t} destruct_guard;\n\n\t\tstatic std::vector<char*> global_id_storage_;\n\t\tstatic dict<char*, int, hash_cstr_ops> global_id_index_;\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic std::vector<int> global_refcount_storage_;\n\t\tstatic std::vector<int> global_free_idx_list_;\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tstatic int last_created_idx_ptr_;\n\t\tstatic int last_created_idx_[8];\n\t#endif\n\n\t\tstatic inline void xtrace_db_dump()\n\t\t{\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t\t{\n\t\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\t\telse\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\t\t}\n\n\t\tstatic inline void checkpoint()\n\t\t{\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\tlast_created_idx_ptr_ = 0;\n\t\t\tfor (int i = 0; i < 8; i++) {\n\t\t\t\tif (last_created_idx_[i])\n\t\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\t\tlast_created_idx_[i] = 0;\n\t\t\t}\n\t\t#endif\n\t\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t\t#endif\n\t\t}\n\n\t\tstatic inline int get_reference(int idx)\n\t\t{\n\t\t\tif (idx) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_[idx]++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\t\t\t}\n\t\t\treturn idx;\n\t\t}\n\n\t\tstatic int get_reference(const char *p)\n\t\t{\n\t\t\tlog_assert(destruct_guard_ok);\n\n\t\t\tif (!p[0])\n\t\t\t\treturn 0;\n\n\t\t\tauto it = global_id_index_.find((char*)p);\n\t\t\tif (it != global_id_index_.end()) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t\t#endif\n\t\t\t\treturn it->second;\n\t\t\t}\n\n\t\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\t\tlog_assert(p[1] != 0);\n\t\t\tfor (const char *c = p; *c; c++)\n\t\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tif (global_free_idx_list_.empty()) {\n\t\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t\t}\n\t\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t}\n\n\t\t\tint idx = global_free_idx_list_.back();\n\t\t\tglobal_free_idx_list_.pop_back();\n\t\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\t\tglobal_refcount_storage_.at(idx)++;\n\t\t#else\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tint idx = global_id_storage_.size();\n\t\t\tglobal_id_storage_.push_back(strdup(p));\n\t\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t\t#endif\n\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\t// Avoid Create->Delete->Create pattern\n\t\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t\t#endif\n\n\t\t\treturn idx;\n\t\t}\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic inline void put_reference(int idx)\n\t\t{\n\t\t\t// put_reference() may be called from destructors after the destructor of\n\t\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\t\tif (!destruct_guard_ok || !idx)\n\t\t\t\treturn;\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\n\t\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\t\tif (--refcount > 0)\n\t\t\t\treturn;\n\n\t\t\tlog_assert(refcount == 0);\n\t\t\tfree_reference(idx);\n\t\t}\n\t\tstatic inline void free_reference(int idx)\n\t\t{\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\t\tfree(global_id_storage_.at(idx));\n\t\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\t\tglobal_free_idx_list_.push_back(idx);\n\t\t}\n\t#else\n\t\tstatic inline void put_reference(int) { }\n\t#endif\n\n\t\t// the actual IdString object is just is a single int\n\n\t\tint index_;\n\n\t\tinline IdString() : index_(0) { }\n\t\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\t\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\t\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\t\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\t\tinline ~IdString() { put_reference(index_); }\n\n\t\tinline void operator=(const IdString &rhs) {\n\t\t\tput_reference(index_);\n\t\t\tindex_ = get_reference(rhs.index_);\n\t\t}\n\n\t\tinline void operator=(const char *rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline void operator=(const std::string &rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline const char *c_str() const {\n\t\t\treturn global_id_storage_.at(index_);\n\t\t}\n\n\t\tinline std::string str() const {\n\t\t\treturn std::string(global_id_storage_.at(index_));\n\t\t}\n\n\t\tinline bool operator<(const IdString &rhs) const {\n\t\t\treturn index_ < rhs.index_;\n\t\t}\n\n\t\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\t\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\t\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\t\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\t\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\t\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\t\tchar operator[](size_t i) const {\n const char *p = c_str();\n#ifndef NDEBUG\n\t\t\tfor (; i != 0; i--, p++)\n\t\t\t\tlog_assert(*p != 0);\n\t\t\treturn *p;\n#else\n\t\t\treturn *(p + i);\n#endif\n\t\t}\n\n\t\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\t\treturn std::string(c_str() + pos);\n\t\t\telse\n\t\t\t\treturn std::string(c_str() + pos, len);\n\t\t}\n\n\t\tint compare(size_t pos, size_t len, const char* s) const {\n\t\t\treturn strncmp(c_str()+pos, s, len);\n\t\t}\n\n\t\tbool begins_with(const char* prefix) const {\n\t\t\tsize_t len = strlen(prefix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(0, len, prefix) == 0;\n\t\t}\n\n\t\tbool ends_with(const char* suffix) const {\n\t\t\tsize_t len = strlen(suffix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(size()-len, len, suffix) == 0;\n\t\t}\n\n\t\tbool contains(const char* str) const {\n\t\t\treturn strstr(c_str(), str);\n\t\t}\n\n\t\tsize_t size() const {\n\t\t\treturn strlen(c_str());\n\t\t}\n\n\t\tbool empty() const {\n\t\t\treturn c_str()[0] == 0;\n\t\t}\n\n\t\tvoid clear() {\n\t\t\t*this = IdString();\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn index_;\n\t\t}\n\n\t\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t\t// set has an influence on the algorithm.\n\n\t\ttemplate<typename T> struct compare_ptr_by_name {\n\t\t\tbool operator()(const T *a, const T *b) const {\n\t\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t\t}\n\t\t};\n\n\t\t// often one needs to check if a given IdString is part of a list (for example a list\n\t\t// of cell types). the following functions helps with that.\n\n\t\ttemplate<typename... Args>\n\t\tbool in(Args... args) const {\n\t\t\t// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html\n\t\t\tbool result = false;\n\t\t\t(void) std::initializer_list<int>{ (result = result || in(args), 0)... };\n\t\t\treturn result;\n\t\t}\n\n\t\tbool in(const IdString &rhs) const { return *this == rhs; }\n\t\tbool in(const char *rhs) const { return *this == rhs; }\n\t\tbool in(const std::string &rhs) const { return *this == rhs; }\n\t\tbool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n\n\t\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\t};\n\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_buf (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tint flags;\n\tstd::vector<RTLIL::State> bits;\n\n\tConst() : flags(RTLIL::CONST_FLAG_NONE) {}\n\tConst(const std::string &str);\n\tConst(long long val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &c) = default;\n\tRTLIL::Const &operator =(const RTLIL::Const &other) = default;\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tstatic Const from_string(const std::string &str);\n\n\tstd::string decode_string() const;\n\n\tinline int size() const { return bits.size(); }\n\tinline bool empty() const { return bits.empty(); }\n\tinline RTLIL::State &operator[](int index) { return bits.at(index); }\n\tinline const RTLIL::State &operator[](int index) const { return bits.at(index); }\n\tinline decltype(bits)::iterator begin() { return bits.begin(); }\n\tinline decltype(bits)::iterator end() { return bits.end(); }\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tinline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {\n\t\tRTLIL::Const ret;\n\t\tret.bits.reserve(len);\n\t\tfor (int i = offset; i < offset + len; i++)\n\t\t\tret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);\n\t\treturn ret;\n\t}\n\n\tvoid extu(int width) {\n\t\tbits.resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());\n\t}\n\n\tinline unsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto b : bits)\n\t\t\th = mkhash(h, b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tRTLIL::SigBit operator[](int offset) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\tunsigned int hash() const;\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tunsigned long hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tsize_t get_hash() const {\n\t\tif (!hash_) hash();\n\t\treturn hash_;\n\t}\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\tunsigned int hash() const { if (!hash_) updhash(); return hash_; };\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tbool flagBufferedNormalized = false;\n\tvoid bufNormalize(bool enable=true);\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\tpool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;\n\tvoid bufNormalize();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nnamespace RTLIL_BACKEND {\nvoid dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n}\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\n\tfriend struct RTLIL::Design;\n\tfriend struct RTLIL::Cell;\n\tfriend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);\n\tRTLIL::Cell *driverCell_ = nullptr;\n\tRTLIL::IdString driverPort_;\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n\tRTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };\n\tRTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline unsigned int RTLIL::SigBit::hash() const {\n\tif (wire)\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\treturn data;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "satgen.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tSigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string name = pf + (bit.wire->width == 1 ? stringf(\"%s\", log_id(bit.wire)) : stringf(\"%s [%d]\", log_id(bit.wire->name), bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "scopeinfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\tunsigned int hash() const { return (uintptr_t)ptr; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tif (!object->name.isPublic())\n\t\treturn path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty())\n\t\tpath.push_back(object->name);\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic()) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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+ "sexpr.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Emily Schmidt <emily@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SEXPR_H\n#define SEXPR_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nclass SExpr {\npublic:\n\tstd::variant<std::vector<SExpr>, std::string> _v;\npublic:\n\tSExpr(std::string a) : _v(std::move(a)) {}\n SExpr(const char *a) : _v(a) {}\n // FIXME: should maybe be defined for all integral types\n\tSExpr(int n) : _v(std::to_string(n)) {}\n\tSExpr(std::vector<SExpr> const &l) : _v(l) {}\n\tSExpr(std::vector<SExpr> &&l) : _v(std::move(l)) {}\n // It would be nicer to have an std::initializer_list constructor,\n // but that causes confusing issues with overload resolution sometimes.\n template<typename... Args> static SExpr list(Args&&... args) {\n\t return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n }\n bool is_atom() const { return std::holds_alternative<std::string>(_v); }\n std::string const &atom() const { return std::get<std::string>(_v); }\n bool is_list() const { return std::holds_alternative<std::vector<SExpr>>(_v); }\n std::vector<SExpr> const &list() const { return std::get<std::vector<SExpr>>(_v); }\n\tstd::string to_string() const;\n};\n\nstd::ostream &operator<<(std::ostream &os, SExpr const &sexpr);\n\nnamespace SExprUtil {\n // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list`\n template<typename... Args> SExpr list(Args&&... args) {\n\t return SExpr(std::vector<SExpr>{std::forward<Args>(args)...});\n }\n}\n\n// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout.\nclass SExprWriter {\n std::ostream &os;\n int _max_line_width;\n int _indent = 0;\n int _pos = 0;\n // If _pending_nl is set, print a newline before the next character.\n // This lets us \"undo\" the last newline so we can put\n // closing parentheses or a hanging comment on the same line.\n bool _pending_nl = false;\n // Unclosed parentheses (boolean stored is indent_rest)\n\tvector<bool> _unclosed;\n // Used only for push() and pop() (stores _unclosed.size())\n\tvector<size_t> _unclosed_stack;\n\tvoid nl_if_pending();\n void puts(std::string_view s);\n int check_fit(SExpr const &sexpr, int space);\n void print(SExpr const &sexpr, bool close = true, bool indent_rest = true);\npublic:\n SExprWriter(std::ostream &os, int max_line_width = 80)\n : os(os)\n , _max_line_width(max_line_width)\n {}\n // Print an s-expr.\n SExprWriter &operator <<(SExpr const &sexpr) {\n print(sexpr);\n _pending_nl = true;\n return *this;\n }\n // Print an s-expr (which must be a list), but leave room for extra elements\n // which may be printed using either << or further calls to open.\n // If indent_rest = false, the remaining elements are not intended\n // (for avoiding unreasonable indentation on deeply nested structures).\n void open(SExpr const &sexpr, bool indent_rest = true) {\n log_assert(sexpr.is_list());\n print(sexpr, false, indent_rest);\n }\n // Close the s-expr opened with the last call to open\n // (if an argument is given, close that many s-exprs).\n void close(size_t n = 1);\n // push() remembers how many s-exprs are currently open\n\tvoid push() {\n\t\t_unclosed_stack.push_back(_unclosed.size());\n\t}\n // pop() closes all s-expr opened since the corresponding call to push()\n\tvoid pop() {\n\t\tauto t = _unclosed_stack.back();\n\t\tlog_assert(_unclosed.size() >= t);\n\t\tclose(_unclosed.size() - t);\n\t\t_unclosed_stack.pop_back();\n\t}\n // Print a comment.\n // If hanging = true, append it to the end of the last printed s-expr.\n\tvoid comment(std::string const &str, bool hanging = false);\n // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses.\n void flush() {\n nl_if_pending();\n }\n // Destructor closes any unclosed parentheses and flushes.\n ~SExprWriter();\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "sigtools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SIGTOOLS_H\n#define SIGTOOLS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct SigPool\n{\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tpool<bitDef_t> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.insert(bit);\n\t}\n\n\tvoid add(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.insert(bit);\n\t}\n\n\tvoid del(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.erase(bit);\n\t}\n\n\tvoid del(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.erase(bit);\n\t}\n\n\tvoid expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\t\tfor (int i = 0; i < GetSize(from); i++) {\n\t\t\tbitDef_t bit_from(from[i]), bit_to(to[i]);\n\t\t\tif (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)\n\t\t\t\tbits.insert(bit_to);\n\t\t}\n\t}\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tRTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tbool check(const RTLIL::SigBit &bit) const\n\t{\n\t\treturn bit.wire != NULL && bits.count(bit);\n\t}\n\n\tbool check_any(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool check_all(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tRTLIL::SigSpec export_one() const\n\t{\n\t\tfor (auto &bit : bits)\n\t\t\treturn RTLIL::SigSpec(bit.first, bit.second);\n\t\treturn RTLIL::SigSpec();\n\t}\n\n\tRTLIL::SigSpec export_all() const\n\t{\n\t\tpool<RTLIL::SigBit> sig;\n\t\tfor (auto &bit : bits)\n\t\t\tsig.insert(RTLIL::SigBit(bit.first, bit.second));\n\t\treturn sig;\n\t}\n\n\tsize_t size() const\n\t{\n\t\treturn bits.size();\n\t}\n};\n\ntemplate <typename T, class Compare = void>\nstruct SigSet\n{\n\tstatic_assert(!std::is_same<Compare,void>::value, \"Default value for `Compare' class not found for SigSet<T>. Please specify.\");\n\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tdict<bitDef_t, std::set<T, Compare>> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid insert(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data);\n\t}\n\n\tvoid insert(const RTLIL::SigSpec& sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data.begin(), data.end());\n\t}\n\n\tvoid erase(const RTLIL::SigSpec& sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].clear();\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data);\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data.begin(), data.end());\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, std::set<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, pool<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tstd::set<T> find(const RTLIL::SigSpec &sig)\n\t{\n\t\tstd::set<T> result;\n\t\tfind(sig, result);\n\t\treturn result;\n\t}\n\n\tbool has(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n};\n\ntemplate<typename T>\nclass SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};\ntemplate<typename T>\nusing sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;\ntemplate<typename T>\nclass SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};\n\n/**\n * SigMap wraps a union-find \"database\"\n * to map SigBits of a module to canonical representative SigBits.\n * SigBits that are connected share a set in the underlying database.\n * If a SigBit has a const state (impl: bit.wire is nullptr),\n * it's promoted to a representative.\n */\nstruct SigMap\n{\n\tmfp<SigBit> database;\n\n\tSigMap(RTLIL::Module *module = NULL)\n\t{\n\t\tif (module != NULL)\n\t\t\tset(module);\n\t}\n\n\tvoid swap(SigMap &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid clear()\n\t{\n\t\tdatabase.clear();\n\t}\n\n\t// Rebuild SigMap for all connections in module\n\tvoid set(RTLIL::Module *module)\n\t{\n\t\tint bitcount = 0;\n\t\tfor (auto &it : module->connections())\n\t\t\tbitcount += it.first.size();\n\n\t\tdatabase.clear();\n\t\tdatabase.reserve(bitcount);\n\n\t\tfor (auto &it : module->connections())\n\t\t\tadd(it.first, it.second);\n\t}\n\n\t// Add connections from \"from\" to \"to\", bit-by-bit\n\tvoid add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\n\t\tfor (int i = 0; i < GetSize(from); i++)\n\t\t{\n\t\t\tint bfi = database.lookup(from[i]);\n\t\t\tint bti = database.lookup(to[i]);\n\n\t\t\tconst RTLIL::SigBit &bf = database[bfi];\n\t\t\tconst RTLIL::SigBit &bt = database[bti];\n\n\t\t\tif (bf.wire || bt.wire)\n\t\t\t{\n\t\t\t\tdatabase.imerge(bfi, bti);\n\n\t\t\t\tif (bf.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bfi);\n\n\t\t\t\tif (bt.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bti);\n\t\t\t}\n\t\t}\n\t}\n\n\t// Add sig as disconnected from anything\n\tvoid add(const RTLIL::SigBit &bit)\n\t{\n\t\tconst auto &b = database.find(bit);\n\t\tif (b.wire != nullptr)\n\t\t\tdatabase.promote(bit);\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tadd(bit);\n\t}\n\n\tinline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }\n\n\t// Modify bit to its representative\n\tvoid apply(RTLIL::SigBit &bit) const\n\t{\n\t\tbit = database.find(bit);\n\t}\n\n\tvoid apply(RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tapply(bit);\n\t}\n\n\tRTLIL::SigBit operator()(RTLIL::SigBit bit) const\n\t{\n\t\tapply(bit);\n\t\treturn bit;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::SigSpec sig) const\n\t{\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::Wire *wire) const\n\t{\n\t\tSigSpec sig(wire);\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\t// All non-const bits\n\tRTLIL::SigSpec allbits() const\n\t{\n\t\tRTLIL::SigSpec sig;\n\t\tfor (const auto &bit : database)\n\t\t\tif (bit.wire != nullptr)\n\t\t\t\tsig.append(bit);\n\t\treturn sig;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif /* SIGTOOLS_H */\n",
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  "timinginfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * (C) 2020 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tunsigned int hash() const { return mkhash_add(name.hash(), offset); }\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\tunsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
183
- "utils.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T, typename OPS = hash_ops<Key>>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*, OPS>> backup_state;\n\tdict<Key, T, OPS> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T, OPS> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T, OPS> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> class TopoSort\n{\n public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n if (rv.second) {\n \t nodes.push_back(n);\n\t\t edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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+ "utils.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T, typename OPS = hash_ops<Key>>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*, OPS>> backup_state;\n\tdict<Key, T, OPS> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T, OPS> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T, OPS> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> class TopoSort\n{\n public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n if (rv.second) {\n \t nodes.push_back(n);\n\t\t edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\n// this class is used for implementing operator-> on iterators that return values rather than references\n// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained\ntemplate<class T>\nstruct arrow_proxy {\n\tT v;\n\texplicit arrow_proxy(T const & v) : v(v) {}\n\tT* operator->() { return &v; }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n//\n// Find more information in the \"guidelines/GettingStarted\" file.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
185
- "yosys_common.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#ifdef YOSYS_ENABLE_TCL\n# include <tcl.h>\n# ifdef YOSYS_MXE_HACKS\nextern Tcl_Command Tcl_CreateCommand(Tcl_Interp *interp, const char *cmdName, Tcl_CmdProc *proc, ClientData clientData, Tcl_CmdDeleteProc *deleteProc);\nextern Tcl_Interp *Tcl_CreateInterp(void);\nextern void Tcl_Preserve(ClientData data);\nextern void Tcl_Release(ClientData clientData);\nextern int Tcl_InterpDeleted(Tcl_Interp *interp);\nextern void Tcl_DeleteInterp(Tcl_Interp *interp);\nextern int Tcl_Eval(Tcl_Interp *interp, const char *script);\nextern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);\nextern void Tcl_Finalize(void);\nextern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);\nextern const char *Tcl_GetStringResult(Tcl_Interp *interp);\nextern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);\nextern Tcl_Obj *Tcl_NewIntObj(int intValue);\nextern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);\nextern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);\n# endif\n# undef CONST\n# undef INLINE\n#endif\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#else\n# error \"C++17 or later compatible compiler is required\"\n#endif\n\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# undef HASHLIB_H\n# include \"kernel/hashlib.h\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\tunsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }\n};\n\nusing hashlib::mkhash;\nusing hashlib::mkhash_init;\nusing hashlib::mkhash_add;\nusing hashlib::mkhash_xorshift;\nusing hashlib::hash_ops;\nusing hashlib::hash_cstr_ops;\nusing hashlib::hash_ptr_ops;\nusing hashlib::hash_obj_ops;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n // For the common case of strings shorter than 128, save a heap\n // allocation by using a stack allocated buffer.\n const int kBufSize = 128;\n char buf[kBufSize];\n buf[0] = '\\0';\n va_list apc;\n va_copy(apc, ap);\n int n = vsnprintf(buf, kBufSize, fmt, apc);\n va_end(apc);\n if (n < kBufSize)\n return std::string(buf);\n\n std::string string;\n char *str = NULL;\n#if defined(_WIN32 )|| defined(__CYGWIN__)\n int sz = 2 * kBufSize, rc;\n while (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char*)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n if (vasprintf(&str, fmt, ap) < 0)\n str = NULL;\n if (str != NULL) {\n string = str;\n free(str);\n }\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n// sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::State> : hash_ops<int> {};\n}\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
187
+ "yosys_common.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <variant>\n#include <optional>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#ifdef YOSYS_ENABLE_TCL\n# include <tcl.h>\n# ifdef YOSYS_MXE_HACKS\nextern Tcl_Command Tcl_CreateCommand(Tcl_Interp *interp, const char *cmdName, Tcl_CmdProc *proc, ClientData clientData, Tcl_CmdDeleteProc *deleteProc);\nextern Tcl_Interp *Tcl_CreateInterp(void);\nextern void Tcl_Preserve(ClientData data);\nextern void Tcl_Release(ClientData clientData);\nextern int Tcl_InterpDeleted(Tcl_Interp *interp);\nextern void Tcl_DeleteInterp(Tcl_Interp *interp);\nextern int Tcl_Eval(Tcl_Interp *interp, const char *script);\nextern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);\nextern void Tcl_Finalize(void);\nextern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);\nextern const char *Tcl_GetStringResult(Tcl_Interp *interp);\nextern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);\nextern Tcl_Obj *Tcl_NewIntObj(int intValue);\nextern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);\nextern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);\n# endif\n# undef CONST\n# undef INLINE\n#endif\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#else\n# error \"C++17 or later compatible compiler is required\"\n#endif\n\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# undef HASHLIB_H\n# include \"kernel/hashlib.h\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\tunsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }\n};\n\nusing hashlib::mkhash;\nusing hashlib::mkhash_init;\nusing hashlib::mkhash_add;\nusing hashlib::mkhash_xorshift;\nusing hashlib::hash_ops;\nusing hashlib::hash_cstr_ops;\nusing hashlib::hash_ptr_ops;\nusing hashlib::hash_obj_ops;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n // For the common case of strings shorter than 128, save a heap\n // allocation by using a stack allocated buffer.\n const int kBufSize = 128;\n char buf[kBufSize];\n buf[0] = '\\0';\n va_list apc;\n va_copy(apc, ap);\n int n = vsnprintf(buf, kBufSize, fmt, apc);\n va_end(apc);\n if (n < kBufSize)\n return std::string(buf);\n\n std::string string;\n char *str = NULL;\n#if defined(_WIN32 )|| defined(__CYGWIN__)\n int sz = 2 * kBufSize, rc;\n while (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char*)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n if (vasprintf(&str, fmt, ap) < 0)\n str = NULL;\n if (str != NULL) {\n string = str;\n free(str);\n }\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n// sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::State> : hash_ops<int> {};\n}\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "yw.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YW_H\n#define YW_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/mem.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct IdPath : public std::vector<RTLIL::IdString>\n{\n\ttemplate<typename... T>\n\tIdPath(T&&... args) : std::vector<RTLIL::IdString>(std::forward<T>(args)...) { }\n\tIdPath prefix() const { return {begin(), end() - !empty()}; }\n\tstd::string str() const;\n\n\tbool has_address() const { int tmp; return get_address(tmp); };\n\tbool get_address(int &addr) const;\n\n\tint hash() const { return hashlib::hash_ops<std::vector<RTLIL::IdString>>::hash(*this); }\n};\n\nstruct WitnessHierarchyItem {\n\tRTLIL::Module *module;\n\tRTLIL::Wire *wire = nullptr;\n\tRTLIL::Cell *cell = nullptr;\n\tMem *mem = nullptr;\n\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Wire *wire) : module(module), wire(wire) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, Mem *mem) : module(module), mem(mem) {}\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback);\n\ntemplate<class T> static std::vector<std::string> witness_path(T *obj) {\n\tstd::vector<std::string> path;\n\tif (obj->name.isPublic()) {\n\t\tauto hdlname = obj->get_string_attribute(ID::hdlname);\n\t\tfor (auto token : split_tokens(hdlname))\n\t\t\tpath.push_back(\"\\\\\" + token);\n\t}\n\tif (path.empty())\n\t\tpath.push_back(obj->name.str());\n\treturn path;\n}\n\nstruct ReadWitness\n{\n\tstruct Clock {\n\t\tIdPath path;\n\t\tint offset;\n\t\tbool is_posedge = false;\n\t\tbool is_negedge = false;\n\t};\n\n\tstruct Signal {\n\t\tIdPath path;\n\t\tint offset;\n\t\tint width;\n\t\tbool init_only;\n\n\t\tint bits_offset;\n\t};\n\n\tstruct Step {\n\t\tstd::string bits;\n\t};\n\n\tstd::string filename;\n\tstd::vector<Clock> clocks;\n\tstd::vector<Signal> signals;\n\tstd::vector<Step> steps;\n\n\tReadWitness(const std::string &filename);\n\n\tRTLIL::Const get_bits(int t, int bits_offset, int width) const;\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *module, D data, T &callback)\n{\n\tauto const &const_path = path;\n\tsize_t path_size = path.size();\n\tfor (auto wire : module->wires())\n\t{\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : wire->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == wire->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty())\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(wire->name);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto cell : module->cells())\n\t{\n\t\tModule *child = module->design->module(cell->type);\n\t\tif (child == nullptr)\n\t\t\tcontinue;\n\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, 1, child, child_data, callback);\n\t\t}\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(cell->name);\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, hdlname.empty() ? hdlname_mode : -1, child, child_data, callback);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto mem : Mem::get_all_memories(module)) {\n\t\tstd::vector<std::string> hdlname;\n\n\t\tif (hdlname_mode >= 0 && mem.cell != nullptr)\n\t\t\thdlname = mem.cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == mem.cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t}\n\t\tpath.resize(path_size);\n\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(mem.memid);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\tpath.pop_back();\n\n\t\t\tif (mem.cell != nullptr && mem.cell->name != mem.memid) {\n\t\t\t\tpath.push_back(mem.cell->name);\n\t\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\t\tpath.pop_back();\n\t\t\t}\n\t\t}\n\t}\n}\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback)\n{\n\tIdPath path;\n\twitness_hierarchy_recursion<D, T>(path, 0, module, data, callback);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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@@ -289,6 +291,34 @@ export const filesystem = {
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  "uSRAM_map.v": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\n// See document PolarFire Family Fabric User Guide\n// section 4.2 for port list.\n\n// Asynchronous read\nmodule $__uSRAM_AR_ (...);\n\nparameter INIT = 0;\nparameter ADDR_BITS = 6;\n\nparameter PORT_W_WIDTH = 12;\nparameter PORT_R_WIDTH = 12;\nparameter PORT_R_USED = 0;\nparameter PORT_W_USED = 0;\n\ninput PORT_W_CLK;\ninput [ADDR_BITS-1:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\ninput [ADDR_BITS-1:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\n`include \"brams_defs.vh\"\n\nRAM64x12 #(\n\t`PARAMS_INIT_uSRAM\n) _TECHMAP_REPLACE_ (\n\t.R_ADDR(PORT_R_ADDR),\n\t.R_ADDR_BYPASS(1'b1),\n\t.R_ADDR_EN(1'b0),\n\t.R_ADDR_SL_N(1'b1),\n\t.R_ADDR_SD(1'b0),\n\t.R_ADDR_AL_N(1'b1), \n\t.R_ADDR_AD_N(1'b0),\n\t.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),\n\t.R_DATA(PORT_R_RD_DATA),\n\t.R_DATA_BYPASS(1'b1),\n\t.R_DATA_EN(1'b0),\n\t.R_DATA_SL_N(1'b1),\n\t.R_DATA_SD(1'b0),\n\t.R_DATA_AL_N(1'b1),\n\t.R_DATA_AD_N(1'b0),\n\n\t.W_CLK(PORT_W_CLK),\n\t.W_ADDR(PORT_W_ADDR),\n\t.W_DATA(PORT_W_WR_DATA),\n\t.W_EN(PORT_W_WR_EN),\n\n\t.BUSY_FB(1'b0)\n);\n\nendmodule\n\n// Synchronous read\nmodule $__uSRAM_SR_ (...);\n\nparameter INIT = 0;\nparameter ADDR_BITS = 6;\n\nparameter PORT_W_WIDTH = 12;\nparameter PORT_R_WIDTH = 12;\nparameter PORT_R_USED = 0;\nparameter PORT_W_USED = 0;\n\ninput PORT_W_CLK;\ninput [ADDR_BITS-1:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\n// Read port clock and enable signal\n// that async read uSRAM doesn't have\ninput PORT_R_CLK;\ninput PORT_R_RD_EN;\ninput [ADDR_BITS-1:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\n`include \"brams_defs.vh\"\n\nRAM64x12 #(\n\t`PARAMS_INIT_uSRAM\n) _TECHMAP_REPLACE_ (\n\t.R_CLK(PORT_R_CLK),\n\t.R_ADDR(PORT_R_ADDR),\n\t.R_ADDR_BYPASS(1'b0),\n\t.R_ADDR_EN(PORT_R_RD_EN),\n\t.R_ADDR_SL_N(1'b1),\n\t.R_ADDR_SD(1'b0),\n\t.R_ADDR_AL_N(1'b1), \n\t.R_ADDR_AD_N(1'b0),\n\t.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),\n\t.R_DATA(PORT_R_RD_DATA),\n\t.R_DATA_BYPASS(1'b1),\n\t.R_DATA_EN(1'b0),\n\t.R_DATA_SL_N(1'b1),\n\t.R_DATA_SD(1'b0),\n\t.R_DATA_AL_N(1'b1),\n\t.R_DATA_AD_N(1'b0),\n\n\t.W_CLK(PORT_W_CLK),\n\t.W_ADDR(PORT_W_ADDR),\n\t.W_DATA(PORT_W_WR_DATA),\n\t.W_EN(PORT_W_WR_EN),\n\n\t.BUSY_FB(1'b0)\n);\n\nendmodule\n\n",
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  "mul2dsp.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * 2019 Eddie Hung <eddie@fpgeh.com>\n * 2019 gatecat <gatecat@ds0.me>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * Tech-mapping rules for decomposing arbitrarily-sized $mul cells\n * into an equivalent collection of smaller `DSP_NAME cells (with the \n * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached \n * to $shl and $add cells.\n *\n */\n\n`ifndef DSP_A_MAXWIDTH\n$fatal(1, \"Macro DSP_A_MAXWIDTH must be defined\");\n`endif\n`ifndef DSP_B_MAXWIDTH\n$fatal(1, \"Macro DSP_B_MAXWIDTH must be defined\");\n`endif\n`ifndef DSP_B_MAXWIDTH\n$fatal(1, \"Macro DSP_B_MAXWIDTH must be defined\");\n`endif\n`ifndef DSP_A_MAXWIDTH_PARTIAL\n`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH\n`endif\n`ifndef DSP_B_MAXWIDTH_PARTIAL\n`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH\n`endif\n\n`ifndef DSP_NAME\n$fatal(1, \"Macro DSP_NAME must be defined\");\n`endif\n\n`define MAX(a,b) (a > b ? a : b)\n`define MIN(a,b) (a < b ? a : b)\n\n(* techmap_celltype = \"$mul $__mul\" *)\nmodule _80_mul (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\n\tgenerate\n\tif (0) begin end\n`ifdef DSP_A_MINWIDTH\n\telse if (A_WIDTH < `DSP_A_MINWIDTH)\n\t\twire _TECHMAP_FAIL_ = 1;\n`endif\n`ifdef DSP_B_MINWIDTH\n\telse if (B_WIDTH < `DSP_B_MINWIDTH)\n\t\twire _TECHMAP_FAIL_ = 1;\n`endif\n`ifdef DSP_Y_MINWIDTH\n\telse if (Y_WIDTH < `DSP_Y_MINWIDTH)\n\t\twire _TECHMAP_FAIL_ = 1;\n`endif\n`ifdef DSP_SIGNEDONLY\n\telse if (_TECHMAP_CELLTYPE_ == \"$mul\" && !A_SIGNED && !B_SIGNED)\n\t\t\\$mul #(\n\t\t\t.A_SIGNED(1),\n\t\t\t.B_SIGNED(1),\n\t\t\t.A_WIDTH(A_WIDTH + 1),\n\t\t\t.B_WIDTH(B_WIDTH + 1),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A({1'b0, A}),\n\t\t\t.B({1'b0, B}),\n\t\t\t.Y(Y)\n\t\t);\n`endif\n\telse if (_TECHMAP_CELLTYPE_ == \"$mul\" && A_WIDTH < B_WIDTH)\n\t\t\\$mul #(\n\t\t\t.A_SIGNED(B_SIGNED),\n\t\t\t.B_SIGNED(A_SIGNED),\n\t\t\t.A_WIDTH(B_WIDTH),\n\t\t\t.B_WIDTH(A_WIDTH),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(B),\n\t\t\t.B(A),\n\t\t\t.Y(Y)\n\t\t);\n\telse begin\n\t\twire [1023:0] _TECHMAP_DO_ = \"proc; clean\";\n\n`ifdef DSP_SIGNEDONLY\n\t\tlocalparam sign_headroom = 1;\n`else\n\t\tlocalparam sign_headroom = 0;\n`endif\n\n\t\tgenvar i;\n\t\tif (A_WIDTH > `DSP_A_MAXWIDTH) begin\n\t\t\tlocalparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);\n\t\t\tlocalparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;\n\t\t\tif (A_SIGNED && B_SIGNED) begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\t\t\telse begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\n\t\t\tfor (i = 0; i < n; i=i+1) begin:sliceA\n\t\t\t\t\\$__mul #(\n\t\t\t\t\t.A_SIGNED(sign_headroom),\n\t\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t\t.A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),\n\t\t\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t\t\t.Y_WIDTH(partial_Y_WIDTH)\n\t\t\t\t) mul (\n\t\t\t\t\t.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),\n\t\t\t\t\t.B(B),\n\t\t\t\t\t.Y(blk.partial[i])\n\t\t\t\t);\n\t\t\t\t// TODO: Currently a 'cascade' approach to summing the partial\n\t\t\t\t// products is taken here, but a more efficient 'binary\n\t\t\t\t// reduction' approach also exists...\n\t\t\t\tif (i == 0)\n\t\t\t\t\tassign blk.partial_sum[i] = blk.partial[i];\n\t\t\t\telse\n\t\t\t\t\tassign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\n\t\t\tend\n\n\t\t\t\\$__mul #(\n\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t.A_WIDTH(last_A_WIDTH),\n\t\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t\t.Y_WIDTH(last_Y_WIDTH)\n\t\t\t) sliceA.last (\n\t\t\t\t.A(A[A_WIDTH-1 -: last_A_WIDTH]),\n\t\t\t\t.B(B),\n\t\t\t\t.Y(blk.last_partial)\n\t\t\t);\n\t\t\tassign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\n\t\t\tassign Y = blk.partial_sum[n];\n\t\tend\n\t\telse if (B_WIDTH > `DSP_B_MAXWIDTH) begin\n\t\t\tlocalparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);\n\t\t\tlocalparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;\n\t\t\tif (A_SIGNED && B_SIGNED) begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\t\t\telse begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\n\t\t\tfor (i = 0; i < n; i=i+1) begin:sliceB\n\t\t\t\t\\$__mul #(\n\t\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t\t.B_SIGNED(sign_headroom),\n\t\t\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t\t\t.B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),\n\t\t\t\t\t.Y_WIDTH(partial_Y_WIDTH)\n\t\t\t\t) mul (\n\t\t\t\t\t.A(A),\n\t\t\t\t\t.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),\n\t\t\t\t\t.Y(blk.partial[i])\n\t\t\t\t);\n\t\t\t\t// TODO: Currently a 'cascade' approach to summing the partial\n\t\t\t\t// products is taken here, but a more efficient 'binary\n\t\t\t\t// reduction' approach also exists...\n\t\t\t\tif (i == 0)\n\t\t\t\t\tassign blk.partial_sum[i] = blk.partial[i];\n\t\t\t\telse\n\t\t\t\t\tassign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\n\t\t\tend\n\n\t\t\t\\$__mul #(\n\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t\t.B_WIDTH(last_B_WIDTH),\n\t\t\t\t.Y_WIDTH(last_Y_WIDTH)\n\t\t\t) mul_sliceB_last (\n\t\t\t\t.A(A),\n\t\t\t\t.B(B[B_WIDTH-1 -: last_B_WIDTH]),\n\t\t\t\t.Y(blk.last_partial)\n\t\t\t);\n\t\t\tassign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\n\t\t\tassign Y = blk.partial_sum[n];\n\t\tend\n\t\telse begin\n\t\t\tif (A_SIGNED) begin : blkA\n\t\t\t\twire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);\n\t\t\tend\n\t\t\telse begin : blkA\n\t\t\t\twire [`DSP_A_MAXWIDTH-1:0] Aext = A;\n\t\t\tend\n\t\t\tif (B_SIGNED) begin : blkB\n\t\t\t\twire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);\n\t\t\tend\n\t\t\telse begin : blkB\n\t\t\t\twire [`DSP_B_MAXWIDTH-1:0] Bext = B;\n\t\t\tend\n\n\t\t\t`DSP_NAME #(\n\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t.A_WIDTH(`DSP_A_MAXWIDTH),\n\t\t\t\t.B_WIDTH(`DSP_B_MAXWIDTH),\n\t\t\t\t.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.A(blkA.Aext),\n\t\t\t\t.B(blkB.Bext),\n\t\t\t\t.Y(Y)\n\t\t\t);\n\t\tend\n\tend\n\tendgenerate\nendmodule\n\n(* techmap_celltype = \"$mul $__mul\" *)\nmodule _90_soft_mul (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t// Indirection necessary since mapping\n\t// back to $mul will cause recursion\n\tgenerate\n\tif (A_SIGNED && !B_SIGNED)\n\t\t\\$__soft_mul #(\n\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t.B_SIGNED(1),\n\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t.B_WIDTH(B_WIDTH+1),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(A),\n\t\t\t.B({1'b0,B}),\n\t\t\t.Y(Y)\n\t\t);\n\telse if (!A_SIGNED && B_SIGNED)\n\t\t\\$__soft_mul #(\n\t\t\t.A_SIGNED(1),\n\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t.A_WIDTH(A_WIDTH+1),\n\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A({1'b0,A}),\n\t\t\t.B(B),\n\t\t\t.Y(Y)\n\t\t);\n\telse\n\t\t\\$__soft_mul #(\n\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(A),\n\t\t\t.B(B),\n\t\t\t.Y(Y)\n\t\t);\n\tendgenerate\nendmodule\n",
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+ "nanoxplore": {
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+ "arith_map.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n (* force_downto *)\n wire [Y_WIDTH-1:0] COx;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice\n\t\tNX_CY_1BIT #(.first(i==0))\n\t\t\talu_i (\n\t\t\t.CI(i==0 ? CI : COx[i-1]),\n\t\t\t.A(AA[i]),\n\t\t\t.B(BB[i]),\n\t\t\t.S(Y[i]),\n\t\t\t.CO(COx[i])\n\t\t);\n\n\tend: slice\n\tendgenerate\n\n\tNX_CY_1BIT alu_cout(\n\t\t.CI(COx[Y_WIDTH-1]),\n\t\t.A(1'b0),\n\t\t.B(1'b0),\n\t\t.S(CO[Y_WIDTH-1])\n\t);\n\n /* End implementation */\n assign X = AA ^ BB;\nendmodule\n",
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+ "brams.txt": "ram block $__NX_RAM_ {\n\toption \"STD_MODE\" \"NOECC_48kx1\" {\n\t\t# only 32k used\n\t\tabits 15;\n\t\twidths 1 per_port;\n\t}\n\toption \"STD_MODE\" \"NOECC_24kx2\" {\n\t\t# only 16k used\n\t\tabits 14;\n\t\twidths 2 per_port;\n\t}\n\tifndef IS_NG_MEDIUM {\n\t\toption \"STD_MODE\" \"NOECC_16kx3\" {\n\t\t\tabits 14;\n\t\t\twidths 3 per_port;\n\t\t}\n\t}\n\toption \"STD_MODE\" \"NOECC_12kx4\" {\n\t\t# only 8k used\n\t\tabits 13;\n\t\twidths 4 per_port;\n\t}\n\tifndef IS_NG_MEDIUM {\n\t\toption \"STD_MODE\" \"NOECC_8kx6\" {\n\t\t\tabits 13;\n\t\t\twidths 6 per_port;\n\t\t}\n\t}\n\toption \"STD_MODE\" \"NOECC_6kx8\" {\n\t\t# only 4k used\n\t\tabits 12;\n\t\twidths 8 per_port;\n\t}\n\toption \"STD_MODE\" \"NOECC_4kx12\" {\n\t\tabits 12;\n\t\twidths 12 per_port;\n\t}\n\toption \"STD_MODE\" \"NOECC_2kx24\" {\n\t\tabits 11;\n\t\twidths 24 per_port;\n\t}\n\tcost 64;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock anyedge;\n\t\tclken;\n\t\trdwr no_change;\n\t\trdinit none;\n\t}\n}",
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+ "brams_init.vh": "function [409600-1:0] bram_init_to_string;\n input [49152-1:0] array;\n input integer blocks;\n input integer width;\n reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas\n reg [24-1:0] temp2; \n integer i;\n integer j;\nbegin\n temp = \"\";\n for (i = 0; i < 2048; i = i + 1) begin\n if (i != 0) begin\n temp = {temp, \",\"};\n end\n temp2 = 24'b0;\n for (j = 0; j < blocks; j = j + 1) begin\n temp2[j*width +: width] = array[{j, i[10:0]}*width +: width];\n end\n temp = {temp, $sformatf(\"%b\",temp2[23:0])};\n end\n bram_init_to_string = temp;\nend\nendfunction\n",
298
+ "brams_map.v": "module $__NX_RAM_ (...);\n\nparameter INIT = 0;\nparameter OPTION_STD_MODE = \"NOECC_24kx2\";\n\nparameter PORT_A_WIDTH = 24;\nparameter PORT_B_WIDTH = 24;\n\nparameter PORT_A_CLK_POL = 1;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput [15:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\nwire [24-1:0] A_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\nparameter PORT_B_CLK_POL = 1;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput [15:0] PORT_B_ADDR;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\nwire [24-1:0] B_DATA;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\n\n`include \"brams_init.vh\"\n\nlocalparam raw_config1_val = OPTION_STD_MODE == \"NOECC_48kx1\" ? 16'b0000000000000000:\n OPTION_STD_MODE == \"NOECC_24kx2\" ? 16'b0000001001001001:\n OPTION_STD_MODE == \"NOECC_16kx3\" ? 16'b0000110110110110:\n OPTION_STD_MODE == \"NOECC_12kx4\" ? 16'b0000010010010010:\n OPTION_STD_MODE == \"NOECC_8kx6\" ? 16'b0000111111111111:\n OPTION_STD_MODE == \"NOECC_6kx8\" ? 16'b0000011011011011:\n OPTION_STD_MODE == \"NOECC_4kx12\" ? 16'b0000100100100100:\n OPTION_STD_MODE == \"NOECC_2kx24\" ? 16'b0000101101101101:\n 16'bx;\n\nlocalparam A_REPEAT = 24 / PORT_A_WIDTH;\nlocalparam B_REPEAT = 24 / PORT_B_WIDTH;\n\nassign A_DATA = {A_REPEAT{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};\nassign B_DATA = {B_REPEAT{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};\n\nNX_RAM_WRAP #(\n .std_mode(OPTION_STD_MODE),\n .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),\n .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),\n .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),\n .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),\n .raw_config0(4'b0000),\n .raw_config1(raw_config1_val[15:0]),\n .mem_ctxt($sformatf(\"%s\",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))),\n) _TECHMAP_REPLACE_ (\n .ACK(PORT_A_CLK),\n //.ACKS(PORT_A_CLK),\n //.ACKD(), // Not used in Non-ECC modes\n //.ACKR(),\n //.AR(),\n //.ACOR(),\n //.AERR(),\n .ACS(PORT_A_CLK_EN),\n .AWE(PORT_A_WR_EN),\n\n .AA(PORT_A_ADDR),\n .AI(A_DATA),\n .AO(PORT_A_RD_DATA),\n\n .BCK(PORT_B_CLK),\n //.BCKC(PORT_B_CLK),\n //.BCKD(), // Not used in Non-ECC modes\n //.BCKR()\n //.BR(),\n //.BCOR(),\n //.BERR(),\n .BCS(PORT_B_CLK_EN),\n .BWE(PORT_B_WR_EN),\n .BA(PORT_B_ADDR),\n .BI(B_DATA),\n .BO(PORT_B_RD_DATA)\n);\nendmodule\n",
299
+ "cells_bb.v": "// NX_RAM related\n(* blackbox *)\nmodule NX_ECC(CKD, CHK, COR, ERR);\n input CHK;\n input CKD;\n output COR;\n output ERR;\nendmodule\n\n//TODO\n(* blackbox *)\nmodule NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);\n input [1:0] DS;\n input GS;\n output [2:0] GVDN;\n output [2:0] GVIN;\n output [2:0] GVON;\n input [5:0] LA;\n output [3:0] PA;\nendmodule\n\n//TODO\n(* blackbox *)\nmodule NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);\n input DCK;\n output [5:0] DID;\n input [5:0] DRA;\n input [5:0] DRI;\n input DRL;\n output [5:0] DRO;\n input [1:0] DS;\n input FCK;\n input [4:0] I;\n output IO;\n input R;\n input SCK;\n parameter data_size = 5;\n parameter differential = \"\";\n parameter drive = \"\";\n parameter location = \"\";\n parameter locked = 1'b0;\n parameter outputCapacity = \"\";\n parameter outputDelayLine = \"\";\n parameter slewRate = \"\";\n parameter spath_dynamic = 1'b0;\n parameter standard = \"\";\nendmodule\n\n//TODO\n(* blackbox *)\nmodule NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);\n input DCK;\n output [5:0] DID;\n input DIG;\n input [5:0] DRA;\n input [5:0] DRI;\n input DRL;\n output [5:0] DRO;\n input [1:0] DS;\n input FCK;\n output FLD;\n output FLG;\n input FZ;\n input IO;\n output [4:0] O;\n input R;\n input SCK;\n parameter data_size = 5;\n parameter differential = \"\";\n parameter dpath_dynamic = 1'b0;\n parameter drive = \"\";\n parameter inputDelayLine = \"\";\n parameter inputSignalSlope = \"\";\n parameter location = \"\";\n parameter locked = 1'b0;\n parameter standard = \"\";\n parameter termination = \"\";\n parameter terminationReference = \"\";\n parameter turbo = \"\";\n parameter weakTermination = \"\";\nendmodule\n\n//TODO\n(* blackbox *)\nmodule NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO\n, DID);\n input CCK;\n input CI;\n input CL;\n input CR;\n input DCK;\n output [5:0] DID;\n input DIG;\n input [5:0] DRA;\n input [5:0] DRI;\n input DRL;\n output [5:0] DRO;\n input [1:0] DS;\n input FCK;\n output FLD;\n output FLG;\n input FZ;\n input [4:0] I;\n inout IO;\n output [4:0] O;\n input RRX;\n input RTX;\n input SCK;\n parameter cpath_registered = 1'b0;\n parameter data_size = 5;\n parameter differential = \"\";\n parameter dpath_dynamic = 1'b0;\n parameter drive = \"\";\n parameter inputDelayLine = \"\";\n parameter inputSignalSlope = \"\";\n parameter location = \"\";\n parameter locked = 1'b0;\n parameter outputCapacity = \"\";\n parameter outputDelayLine = \"\";\n parameter slewRate = \"\";\n parameter spath_dynamic = 1'b0;\n parameter standard = \"\";\n parameter termination = \"\";\n parameter terminationReference = \"\";\n parameter turbo = \"\";\n parameter weakTermination = \"\";\nendmodule\n",
300
+ "cells_bb_l.v": "(* blackbox *)\nmodule NX_CKS(CKI, CMD, CKO);\n input CKI;\n output CKO;\n input CMD;\n parameter ck_edge = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1\n, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4\n, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6);\n input AI1;\n input AI2;\n input AI3;\n input AI4;\n input AI5;\n input AI6;\n output AO1;\n output AO2;\n output AO3;\n output AO4;\n output AO5;\n output AO6;\n input BI1;\n input BI2;\n input BI3;\n input BI4;\n input BI5;\n input BI6;\n output BO1;\n output BO2;\n output BO3;\n output BO4;\n output BO5;\n output BO6;\n input CI1;\n input CI2;\n input CI3;\n input CI4;\n input CI5;\n input CI6;\n input CK1;\n input CK2;\n output CO1;\n output CO2;\n output CO3;\n output CO4;\n output CO5;\n output CO6;\n input DI1;\n input DI2;\n input DI3;\n input DI4;\n input DI5;\n input DI6;\n output DO1;\n output DO2;\n output DO3;\n output DO4;\n output DO5;\n output DO6;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter cck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter dck_sel = 1'b0;\n parameter gt0_bypass_reg1 = 1'b0;\n parameter gt0_bypass_reg2 = 1'b0;\n parameter gt1_bypass_reg1 = 1'b0;\n parameter gt1_bypass_reg2 = 1'b0;\n parameter link_BA = 1'b0;\n parameter link_CB = 1'b0;\n parameter link_DC = 1'b0;\n parameter mode = 0;\n parameter use_adest_arst = 2'b00;\n parameter use_asrc_arst = 2'b00;\n parameter use_bdest_arst = 2'b00;\n parameter use_bsrc_arst = 2'b00;\n parameter use_cdest_arst = 2'b00;\n parameter use_csrc_arst = 2'b00;\n parameter use_ddest_arst = 2'b00;\n parameter use_dsrc_arst = 2'b00;\nendmodule\n\n(* blackbox *)\nmodule NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21\n, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18\n, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21\n, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6\n, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3\n, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24\n, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3\n, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37\n, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20\n, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41\n, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6\n, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27\n, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48\n, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13\n, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12\n, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33\n, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54\n, Z55, Z56);\n input A1;\n input A10;\n input A11;\n input A12;\n input A13;\n input A14;\n input A15;\n input A16;\n input A17;\n input A18;\n input A19;\n input A2;\n input A20;\n input A21;\n input A22;\n input A23;\n input A24;\n input A3;\n input A4;\n input A5;\n input A6;\n input A7;\n input A8;\n input A9;\n input B1;\n input B10;\n input B11;\n input B12;\n input B13;\n input B14;\n input B15;\n input B16;\n input B17;\n input B18;\n input B2;\n input B3;\n input B4;\n input B5;\n input B6;\n input B7;\n input B8;\n input B9;\n input C1;\n input C10;\n input C11;\n input C12;\n input C13;\n input C14;\n input C15;\n input C16;\n input C17;\n input C18;\n input C19;\n input C2;\n input C20;\n input C21;\n input C22;\n input C23;\n input C24;\n input C25;\n input C26;\n input C27;\n input C28;\n input C29;\n input C3;\n input C30;\n input C31;\n input C32;\n input C33;\n input C34;\n input C35;\n input C36;\n input C4;\n input C5;\n input C6;\n input C7;\n input C8;\n input C9;\n input CAI1;\n input CAI10;\n input CAI11;\n input CAI12;\n input CAI13;\n input CAI14;\n input CAI15;\n input CAI16;\n input CAI17;\n input CAI18;\n input CAI19;\n input CAI2;\n input CAI20;\n input CAI21;\n input CAI22;\n input CAI23;\n input CAI24;\n input CAI3;\n input CAI4;\n input CAI5;\n input CAI6;\n input CAI7;\n input CAI8;\n input CAI9;\n output CAO1;\n output CAO10;\n output CAO11;\n output CAO12;\n output CAO13;\n output CAO14;\n output CAO15;\n output CAO16;\n output CAO17;\n output CAO18;\n output CAO19;\n output CAO2;\n output CAO20;\n output CAO21;\n output CAO22;\n output CAO23;\n output CAO24;\n output CAO3;\n output CAO4;\n output CAO5;\n output CAO6;\n output CAO7;\n output CAO8;\n output CAO9;\n input CBI1;\n input CBI10;\n input CBI11;\n input CBI12;\n input CBI13;\n input CBI14;\n input CBI15;\n input CBI16;\n input CBI17;\n input CBI18;\n input CBI2;\n input CBI3;\n input CBI4;\n input CBI5;\n input CBI6;\n input CBI7;\n input CBI8;\n input CBI9;\n output CBO1;\n output CBO10;\n output CBO11;\n output CBO12;\n output CBO13;\n output CBO14;\n output CBO15;\n output CBO16;\n output CBO17;\n output CBO18;\n output CBO2;\n output CBO3;\n output CBO4;\n output CBO5;\n output CBO6;\n output CBO7;\n output CBO8;\n output CBO9;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO;\n output CO37;\n output CO57;\n input CZI1;\n input CZI10;\n input CZI11;\n input CZI12;\n input CZI13;\n input CZI14;\n input CZI15;\n input CZI16;\n input CZI17;\n input CZI18;\n input CZI19;\n input CZI2;\n input CZI20;\n input CZI21;\n input CZI22;\n input CZI23;\n input CZI24;\n input CZI25;\n input CZI26;\n input CZI27;\n input CZI28;\n input CZI29;\n input CZI3;\n input CZI30;\n input CZI31;\n input CZI32;\n input CZI33;\n input CZI34;\n input CZI35;\n input CZI36;\n input CZI37;\n input CZI38;\n input CZI39;\n input CZI4;\n input CZI40;\n input CZI41;\n input CZI42;\n input CZI43;\n input CZI44;\n input CZI45;\n input CZI46;\n input CZI47;\n input CZI48;\n input CZI49;\n input CZI5;\n input CZI50;\n input CZI51;\n input CZI52;\n input CZI53;\n input CZI54;\n input CZI55;\n input CZI56;\n input CZI6;\n input CZI7;\n input CZI8;\n input CZI9;\n output CZO1;\n output CZO10;\n output CZO11;\n output CZO12;\n output CZO13;\n output CZO14;\n output CZO15;\n output CZO16;\n output CZO17;\n output CZO18;\n output CZO19;\n output CZO2;\n output CZO20;\n output CZO21;\n output CZO22;\n output CZO23;\n output CZO24;\n output CZO25;\n output CZO26;\n output CZO27;\n output CZO28;\n output CZO29;\n output CZO3;\n output CZO30;\n output CZO31;\n output CZO32;\n output CZO33;\n output CZO34;\n output CZO35;\n output CZO36;\n output CZO37;\n output CZO38;\n output CZO39;\n output CZO4;\n output CZO40;\n output CZO41;\n output CZO42;\n output CZO43;\n output CZO44;\n output CZO45;\n output CZO46;\n output CZO47;\n output CZO48;\n output CZO49;\n output CZO5;\n output CZO50;\n output CZO51;\n output CZO52;\n output CZO53;\n output CZO54;\n output CZO55;\n output CZO56;\n output CZO6;\n output CZO7;\n output CZO8;\n output CZO9;\n input D1;\n input D10;\n input D11;\n input D12;\n input D13;\n input D14;\n input D15;\n input D16;\n input D17;\n input D18;\n input D2;\n input D3;\n input D4;\n input D5;\n input D6;\n input D7;\n input D8;\n input D9;\n output OVF;\n input R;\n input RZ;\n input WE;\n output Z1;\n output Z10;\n output Z11;\n output Z12;\n output Z13;\n output Z14;\n output Z15;\n output Z16;\n output Z17;\n output Z18;\n output Z19;\n output Z2;\n output Z20;\n output Z21;\n output Z22;\n output Z23;\n output Z24;\n output Z25;\n output Z26;\n output Z27;\n output Z28;\n output Z29;\n output Z3;\n output Z30;\n output Z31;\n output Z32;\n output Z33;\n output Z34;\n output Z35;\n output Z36;\n output Z37;\n output Z38;\n output Z39;\n output Z4;\n output Z40;\n output Z41;\n output Z42;\n output Z43;\n output Z44;\n output Z45;\n output Z46;\n output Z47;\n output Z48;\n output Z49;\n output Z5;\n output Z50;\n output Z51;\n output Z52;\n output Z53;\n output Z54;\n output Z55;\n output Z56;\n output Z6;\n output Z7;\n output Z8;\n output Z9;\n parameter raw_config0 = 20'b00000000000000000000;\n parameter raw_config1 = 19'b0000000000000000000;\n parameter raw_config2 = 13'b0000000000000;\n parameter raw_config3 = 7'b0000000;\n parameter std_mode = \"\";\nendmodule\n\n(* blackbox *)\nmodule NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);\n output CAL_LOCKED;\n output DIVO1;\n output DIVO2;\n output DIVP1;\n output DIVP2;\n output DIVP3;\n input FBK;\n output LDFO;\n output OSC;\n output PLL_LOCKED;\n input R;\n input REF;\n output REFO;\n output VCO;\n parameter cfg_use_pll = 1'b1;\n parameter clk_outdivo1 = 0;\n parameter clk_outdivp1 = 0;\n parameter clk_outdivp2 = 0;\n parameter clk_outdivp3o2 = 0;\n parameter ext_fbk_on = 1'b0;\n parameter fbk_delay = 0;\n parameter fbk_delay_on = 1'b0;\n parameter fbk_intdiv = 2;\n parameter location = \"\";\n parameter pll_cpump = 3'b010;\n parameter ref_intdiv = 0;\n parameter ref_osc_on = 1'b0;\n parameter wfg_sync_cal_lock = 1'b0;\n parameter wfg_sync_pll_lock = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_WFG_L(R, SI, ZI, RDY, SO, ZO);\n input R;\n input RDY;\n input SI;\n output SO;\n input ZI;\n output ZO;\n parameter delay = 0;\n parameter delay_on = 1'b0;\n parameter location = \"\";\n parameter mode = 1'b0;\n parameter pattern = 16'b0000000000000000;\n parameter pattern_end = 1;\n parameter wfg_edge = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3\n, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24\n, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45\n, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2\n, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7\n, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4\n, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK);\n input ALIGN_E_I;\n output ALIGN_O;\n input ALIGN_S_I;\n input BUF_FE_I;\n input BUF_R_I;\n output BUSY_O;\n input CDR_R_I;\n output CH_A_O1;\n output CH_A_O2;\n output CH_A_O3;\n output CH_A_O4;\n output CH_A_O5;\n output CH_A_O6;\n output CH_A_O7;\n output CH_A_O8;\n output CH_COM_O1;\n output CH_COM_O2;\n output CH_COM_O3;\n output CH_COM_O4;\n output CH_COM_O5;\n output CH_COM_O6;\n output CH_COM_O7;\n output CH_COM_O8;\n output CH_F_O1;\n output CH_F_O2;\n output CH_F_O3;\n output CH_F_O4;\n output CH_F_O5;\n output CH_F_O6;\n output CH_F_O7;\n output CH_F_O8;\n output CH_K_O1;\n output CH_K_O2;\n output CH_K_O3;\n output CH_K_O4;\n output CH_K_O5;\n output CH_K_O6;\n output CH_K_O7;\n output CH_K_O8;\n input CKG_RN_I;\n output DATA_O1;\n output DATA_O10;\n output DATA_O11;\n output DATA_O12;\n output DATA_O13;\n output DATA_O14;\n output DATA_O15;\n output DATA_O16;\n output DATA_O17;\n output DATA_O18;\n output DATA_O19;\n output DATA_O2;\n output DATA_O20;\n output DATA_O21;\n output DATA_O22;\n output DATA_O23;\n output DATA_O24;\n output DATA_O25;\n output DATA_O26;\n output DATA_O27;\n output DATA_O28;\n output DATA_O29;\n output DATA_O3;\n output DATA_O30;\n output DATA_O31;\n output DATA_O32;\n output DATA_O33;\n output DATA_O34;\n output DATA_O35;\n output DATA_O36;\n output DATA_O37;\n output DATA_O38;\n output DATA_O39;\n output DATA_O4;\n output DATA_O40;\n output DATA_O41;\n output DATA_O42;\n output DATA_O43;\n output DATA_O44;\n output DATA_O45;\n output DATA_O46;\n output DATA_O47;\n output DATA_O48;\n output DATA_O49;\n output DATA_O5;\n output DATA_O50;\n output DATA_O51;\n output DATA_O52;\n output DATA_O53;\n output DATA_O54;\n output DATA_O55;\n output DATA_O56;\n output DATA_O57;\n output DATA_O58;\n output DATA_O59;\n output DATA_O6;\n output DATA_O60;\n output DATA_O61;\n output DATA_O62;\n output DATA_O63;\n output DATA_O64;\n output DATA_O7;\n output DATA_O8;\n output DATA_O9;\n input DEC_E_I;\n input DSCR_E_I;\n output D_ERR_O1;\n output D_ERR_O2;\n output D_ERR_O3;\n output D_ERR_O4;\n output D_ERR_O5;\n output D_ERR_O6;\n output D_ERR_O7;\n output D_ERR_O8;\n inout [9:0] LINK;\n output LOCK_O;\n output LOS_O;\n output NIT_O1;\n output NIT_O2;\n output NIT_O3;\n output NIT_O4;\n output NIT_O5;\n output NIT_O6;\n output NIT_O7;\n output NIT_O8;\n input OVS_BS_I1;\n input OVS_BS_I2;\n input PLL_RN_I;\n input REP_E_I;\n input RST_N_I;\n input RX_I;\n input TST_I1;\n input TST_I2;\n input TST_I3;\n input TST_I4;\n output TST_O1;\n output TST_O2;\n output TST_O3;\n output TST_O4;\n output TST_O5;\n output TST_O6;\n output TST_O7;\n output TST_O8;\n parameter location = \"\";\n parameter pcs_8b_dscr_sel = 1'b0;\n parameter pcs_align_bypass = 1'b0;\n parameter pcs_buffers_bypass = 1'b0;\n parameter pcs_buffers_use_cdc = 1'b0;\n parameter pcs_bypass_pma_cdc = 1'b0;\n parameter pcs_bypass_usr_cdc = 1'b0;\n parameter pcs_comma_mask = 10'b0000000000;\n parameter pcs_debug_en = 1'b0;\n parameter pcs_dec_bypass = 1'b0;\n parameter pcs_dscr_bypass = 1'b0;\n parameter pcs_el_buff_diff_bef_comp = 3'b000;\n parameter pcs_el_buff_max_comp = 3'b000;\n parameter pcs_el_buff_only_one_skp = 1'b0;\n parameter pcs_el_buff_skp_char_0 = 9'b000000000;\n parameter pcs_el_buff_skp_char_1 = 9'b000000000;\n parameter pcs_el_buff_skp_char_2 = 9'b000000000;\n parameter pcs_el_buff_skp_char_3 = 9'b000000000;\n parameter pcs_el_buff_skp_header_0 = 9'b000000000;\n parameter pcs_el_buff_skp_header_1 = 9'b000000000;\n parameter pcs_el_buff_skp_header_2 = 9'b000000000;\n parameter pcs_el_buff_skp_header_3 = 9'b000000000;\n parameter pcs_el_buff_skp_header_size = 2'b00;\n parameter pcs_el_buff_skp_seq_size = 2'b00;\n parameter pcs_el_buff_underflow_handle = 1'b0;\n parameter pcs_fsm_sel = 2'b00;\n parameter pcs_fsm_watchdog_en = 1'b0;\n parameter pcs_loopback = 1'b0;\n parameter pcs_m_comma_en = 1'b0;\n parameter pcs_m_comma_val = 10'b0000000000;\n parameter pcs_nb_comma_bef_realign = 2'b00;\n parameter pcs_p_comma_en = 1'b0;\n parameter pcs_p_comma_val = 10'b0000000000;\n parameter pcs_polarity = 1'b0;\n parameter pcs_protocol_size = 1'b0;\n parameter pcs_replace_bypass = 1'b0;\n parameter pcs_sync_supported = 1'b0;\n parameter pma_cdr_cp = 4'b0000;\n parameter pma_clk_pos = 1'b0;\n parameter pma_ctrl_term = 6'b000000;\n parameter pma_loopback = 1'b0;\n parameter pma_pll_cpump_n = 3'b000;\n parameter pma_pll_divf = 2'b00;\n parameter pma_pll_divf_en_n = 1'b0;\n parameter pma_pll_divm = 2'b00;\n parameter pma_pll_divm_en_n = 1'b0;\n parameter pma_pll_divn = 1'b0;\n parameter pma_pll_divn_en_n = 1'b0;\n parameter test = 2'b00;\nendmodule\n\n(* blackbox *)\nmodule NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5\n, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I\n, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17\n, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38\n, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59\n, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK);\n output BUSY_O;\n input CH_K_I1;\n input CH_K_I2;\n input CH_K_I3;\n input CH_K_I4;\n input CH_K_I5;\n input CH_K_I6;\n input CH_K_I7;\n input CH_K_I8;\n input CLK_E_I;\n input DATA_I1;\n input DATA_I10;\n input DATA_I11;\n input DATA_I12;\n input DATA_I13;\n input DATA_I14;\n input DATA_I15;\n input DATA_I16;\n input DATA_I17;\n input DATA_I18;\n input DATA_I19;\n input DATA_I2;\n input DATA_I20;\n input DATA_I21;\n input DATA_I22;\n input DATA_I23;\n input DATA_I24;\n input DATA_I25;\n input DATA_I26;\n input DATA_I27;\n input DATA_I28;\n input DATA_I29;\n input DATA_I3;\n input DATA_I30;\n input DATA_I31;\n input DATA_I32;\n input DATA_I33;\n input DATA_I34;\n input DATA_I35;\n input DATA_I36;\n input DATA_I37;\n input DATA_I38;\n input DATA_I39;\n input DATA_I4;\n input DATA_I40;\n input DATA_I41;\n input DATA_I42;\n input DATA_I43;\n input DATA_I44;\n input DATA_I45;\n input DATA_I46;\n input DATA_I47;\n input DATA_I48;\n input DATA_I49;\n input DATA_I5;\n input DATA_I50;\n input DATA_I51;\n input DATA_I52;\n input DATA_I53;\n input DATA_I54;\n input DATA_I55;\n input DATA_I56;\n input DATA_I57;\n input DATA_I58;\n input DATA_I59;\n input DATA_I6;\n input DATA_I60;\n input DATA_I61;\n input DATA_I62;\n input DATA_I63;\n input DATA_I64;\n input DATA_I7;\n input DATA_I8;\n input DATA_I9;\n input ENC_E_I1;\n input ENC_E_I2;\n input ENC_E_I3;\n input ENC_E_I4;\n input ENC_E_I5;\n input ENC_E_I6;\n input ENC_E_I7;\n input ENC_E_I8;\n input EOF_I1;\n input EOF_I2;\n input EOF_I3;\n input EOF_I4;\n input EOF_I5;\n input EOF_I6;\n input EOF_I7;\n input EOF_I8;\n input EOMF_I1;\n input EOMF_I2;\n input EOMF_I3;\n input EOMF_I4;\n input EOMF_I5;\n input EOMF_I6;\n input EOMF_I7;\n input EOMF_I8;\n inout [19:0] LINK;\n input REP_E_I;\n input RST_N_I;\n input SCR_E_I1;\n input SCR_E_I2;\n input SCR_E_I3;\n input SCR_E_I4;\n input SCR_E_I5;\n input SCR_E_I6;\n input SCR_E_I7;\n input SCR_E_I8;\n input TST_I1;\n input TST_I2;\n input TST_I3;\n input TST_I4;\n output TST_O1;\n output TST_O2;\n output TST_O3;\n output TST_O4;\n output TX_O;\n parameter location = \"\";\n parameter pcs_8b_scr_sel = 1'b0;\n parameter pcs_bypass_pma_cdc = 1'b0;\n parameter pcs_bypass_usr_cdc = 1'b0;\n parameter pcs_enc_bypass = 1'b0;\n parameter pcs_esistream_fsm_en = 1'b0;\n parameter pcs_loopback = 1'b0;\n parameter pcs_polarity = 1'b0;\n parameter pcs_protocol_size = 1'b0;\n parameter pcs_replace_bypass = 1'b0;\n parameter pcs_scr_bypass = 1'b0;\n parameter pcs_scr_init = 17'b00000000000000000;\n parameter pcs_sync_supported = 1'b0;\n parameter pma_clk_pos = 1'b0;\n parameter pma_loopback = 1'b0;\n parameter test = 2'b00;\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1\n, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3\n, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1\n, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4\n, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1\n, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR\n, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL\n, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI\n, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4\n, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3\n, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2\n, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1\n, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO\n, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI\n, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO\n, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR\n, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL\n, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1\n, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5\n, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4\n, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3\n, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2\n, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1\n, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR\n, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL\n, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI\n, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO\n, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER\n, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL\n, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5\n, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4\n, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3\n, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2\n, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR\n, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL\n, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1\n, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5\n, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4\n, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3\n, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2\n, P34RO3, P34RO4, P34RO5);\n output C1RED;\n input C1RNE;\n input C1RS;\n input C1RW1;\n input C1RW2;\n input C1RW3;\n input C1TS;\n input C1TW;\n output C2RED;\n input C2RNE;\n input C2RS;\n input C2RW1;\n input C2RW2;\n input C2RW3;\n input C2TS;\n input C2TW;\n input CAD1;\n input CAD2;\n input CAD3;\n input CAD4;\n input CAD5;\n input CAD6;\n output CAL;\n input CAN1;\n input CAN2;\n input CAN3;\n input CAN4;\n input CAP1;\n input CAP2;\n input CAP3;\n input CAP4;\n input CAT1;\n input CAT2;\n input CAT3;\n input CAT4;\n input CCK;\n output CKO1;\n output CKO2;\n input CTCK;\n input DC;\n input DCK;\n input DIG;\n input DIS;\n input DOG;\n input DOS;\n input DPAG;\n input DPAS;\n input DQSG;\n input DQSS;\n input DRA1;\n input DRA2;\n input DRA3;\n input DRA4;\n input DRA5;\n input DRA6;\n input DRI1;\n input DRI2;\n input DRI3;\n input DRI4;\n input DRI5;\n input DRI6;\n input DRL;\n output DRO1;\n output DRO2;\n output DRO3;\n output DRO4;\n output DRO5;\n output DRO6;\n input DS1;\n input DS2;\n input FA1;\n input FA2;\n input FA3;\n input FA4;\n input FA5;\n input FA6;\n output FLD;\n output FLG;\n input FZ;\n input P10CI1;\n input P10CL;\n output P10CO;\n input P10CR;\n input P10CTI;\n output P10CTO;\n input P10EI1;\n input P10EI2;\n input P10EI3;\n input P10EI4;\n input P10EI5;\n input P10EL;\n output P10EO;\n input P10ER;\n input P10RI;\n input P10RL;\n output P10RO1;\n output P10RO2;\n output P10RO3;\n output P10RO4;\n output P10RO5;\n input P10RR;\n input P11CI1;\n input P11CL;\n output P11CO;\n input P11CR;\n input P11CTI;\n output P11CTO;\n input P11EI1;\n input P11EI2;\n input P11EI3;\n input P11EI4;\n input P11EI5;\n input P11EL;\n output P11EO;\n input P11ER;\n input P11RI;\n input P11RL;\n output P11RO1;\n output P11RO2;\n output P11RO3;\n output P11RO4;\n output P11RO5;\n input P11RR;\n input P12CI1;\n input P12CL;\n output P12CO;\n input P12CR;\n input P12CTI;\n output P12CTO;\n input P12EI1;\n input P12EI2;\n input P12EI3;\n input P12EI4;\n input P12EI5;\n input P12EL;\n output P12EO;\n input P12ER;\n input P12RI;\n input P12RL;\n output P12RO1;\n output P12RO2;\n output P12RO3;\n output P12RO4;\n output P12RO5;\n input P12RR;\n input P13CI1;\n input P13CL;\n output P13CO;\n input P13CR;\n input P13CTI;\n output P13CTO;\n input P13EI1;\n input P13EI2;\n input P13EI3;\n input P13EI4;\n input P13EI5;\n input P13EL;\n output P13EO;\n input P13ER;\n input P13RI;\n input P13RL;\n output P13RO1;\n output P13RO2;\n output P13RO3;\n output P13RO4;\n output P13RO5;\n input P13RR;\n input P14CI1;\n input P14CL;\n output P14CO;\n input P14CR;\n input P14CTI;\n output P14CTO;\n input P14EI1;\n input P14EI2;\n input P14EI3;\n input P14EI4;\n input P14EI5;\n input P14EL;\n output P14EO;\n input P14ER;\n input P14RI;\n input P14RL;\n output P14RO1;\n output P14RO2;\n output P14RO3;\n output P14RO4;\n output P14RO5;\n input P14RR;\n input P15CI1;\n input P15CL;\n output P15CO;\n input P15CR;\n input P15CTI;\n output P15CTO;\n input P15EI1;\n input P15EI2;\n input P15EI3;\n input P15EI4;\n input P15EI5;\n input P15EL;\n output P15EO;\n input P15ER;\n input P15RI;\n input P15RL;\n output P15RO1;\n output P15RO2;\n output P15RO3;\n output P15RO4;\n output P15RO5;\n input P15RR;\n input P16CI1;\n input P16CL;\n output P16CO;\n input P16CR;\n input P16CTI;\n output P16CTO;\n input P16EI1;\n input P16EI2;\n input P16EI3;\n input P16EI4;\n input P16EI5;\n input P16EL;\n output P16EO;\n input P16ER;\n input P16RI;\n input P16RL;\n output P16RO1;\n output P16RO2;\n output P16RO3;\n output P16RO4;\n output P16RO5;\n input P16RR;\n input P17CI1;\n input P17CL;\n output P17CO;\n input P17CR;\n input P17CTI;\n output P17CTO;\n input P17EI1;\n input P17EI2;\n input P17EI3;\n input P17EI4;\n input P17EI5;\n input P17EL;\n output P17EO;\n input P17ER;\n input P17RI;\n input P17RL;\n output P17RO1;\n output P17RO2;\n output P17RO3;\n output P17RO4;\n output P17RO5;\n input P17RR;\n input P18CI1;\n input P18CL;\n output P18CO;\n input P18CR;\n input P18CTI;\n output P18CTO;\n input P18EI1;\n input P18EI2;\n input P18EI3;\n input P18EI4;\n input P18EI5;\n input P18EL;\n output P18EO;\n input P18ER;\n input P18RI;\n input P18RL;\n output P18RO1;\n output P18RO2;\n output P18RO3;\n output P18RO4;\n output P18RO5;\n input P18RR;\n input P19CI1;\n input P19CL;\n output P19CO;\n input P19CR;\n input P19CTI;\n output P19CTO;\n input P19EI1;\n input P19EI2;\n input P19EI3;\n input P19EI4;\n input P19EI5;\n input P19EL;\n output P19EO;\n input P19ER;\n input P19RI;\n input P19RL;\n output P19RO1;\n output P19RO2;\n output P19RO3;\n output P19RO4;\n output P19RO5;\n input P19RR;\n input P1CI1;\n input P1CL;\n output P1CO;\n input P1CR;\n input P1CTI;\n output P1CTO;\n input P1EI1;\n input P1EI2;\n input P1EI3;\n input P1EI4;\n input P1EI5;\n input P1EL;\n output P1EO;\n input P1ER;\n input P1RI;\n input P1RL;\n output P1RO1;\n output P1RO2;\n output P1RO3;\n output P1RO4;\n output P1RO5;\n input P1RR;\n input P20CI1;\n input P20CL;\n output P20CO;\n input P20CR;\n input P20CTI;\n output P20CTO;\n input P20EI1;\n input P20EI2;\n input P20EI3;\n input P20EI4;\n input P20EI5;\n input P20EL;\n output P20EO;\n input P20ER;\n input P20RI;\n input P20RL;\n output P20RO1;\n output P20RO2;\n output P20RO3;\n output P20RO4;\n output P20RO5;\n input P20RR;\n input P21CI1;\n input P21CL;\n output P21CO;\n input P21CR;\n input P21CTI;\n output P21CTO;\n input P21EI1;\n input P21EI2;\n input P21EI3;\n input P21EI4;\n input P21EI5;\n input P21EL;\n output P21EO;\n input P21ER;\n input P21RI;\n input P21RL;\n output P21RO1;\n output P21RO2;\n output P21RO3;\n output P21RO4;\n output P21RO5;\n input P21RR;\n input P22CI1;\n input P22CL;\n output P22CO;\n input P22CR;\n input P22CTI;\n output P22CTO;\n input P22EI1;\n input P22EI2;\n input P22EI3;\n input P22EI4;\n input P22EI5;\n input P22EL;\n output P22EO;\n input P22ER;\n input P22RI;\n input P22RL;\n output P22RO1;\n output P22RO2;\n output P22RO3;\n output P22RO4;\n output P22RO5;\n input P22RR;\n input P23CI1;\n input P23CL;\n output P23CO;\n input P23CR;\n input P23CTI;\n output P23CTO;\n input P23EI1;\n input P23EI2;\n input P23EI3;\n input P23EI4;\n input P23EI5;\n input P23EL;\n output P23EO;\n input P23ER;\n input P23RI;\n input P23RL;\n output P23RO1;\n output P23RO2;\n output P23RO3;\n output P23RO4;\n output P23RO5;\n input P23RR;\n input P24CI1;\n input P24CL;\n output P24CO;\n input P24CR;\n input P24CTI;\n output P24CTO;\n input P24EI1;\n input P24EI2;\n input P24EI3;\n input P24EI4;\n input P24EI5;\n input P24EL;\n output P24EO;\n input P24ER;\n input P24RI;\n input P24RL;\n output P24RO1;\n output P24RO2;\n output P24RO3;\n output P24RO4;\n output P24RO5;\n input P24RR;\n input P25CI1;\n input P25CL;\n output P25CO;\n input P25CR;\n input P25CTI;\n output P25CTO;\n input P25EI1;\n input P25EI2;\n input P25EI3;\n input P25EI4;\n input P25EI5;\n input P25EL;\n output P25EO;\n input P25ER;\n input P25RI;\n input P25RL;\n output P25RO1;\n output P25RO2;\n output P25RO3;\n output P25RO4;\n output P25RO5;\n input P25RR;\n input P26CI1;\n input P26CL;\n output P26CO;\n input P26CR;\n input P26CTI;\n output P26CTO;\n input P26EI1;\n input P26EI2;\n input P26EI3;\n input P26EI4;\n input P26EI5;\n input P26EL;\n output P26EO;\n input P26ER;\n input P26RI;\n input P26RL;\n output P26RO1;\n output P26RO2;\n output P26RO3;\n output P26RO4;\n output P26RO5;\n input P26RR;\n input P27CI1;\n input P27CL;\n output P27CO;\n input P27CR;\n input P27CTI;\n output P27CTO;\n input P27EI1;\n input P27EI2;\n input P27EI3;\n input P27EI4;\n input P27EI5;\n input P27EL;\n output P27EO;\n input P27ER;\n input P27RI;\n input P27RL;\n output P27RO1;\n output P27RO2;\n output P27RO3;\n output P27RO4;\n output P27RO5;\n input P27RR;\n input P28CI1;\n input P28CL;\n output P28CO;\n input P28CR;\n input P28CTI;\n output P28CTO;\n input P28EI1;\n input P28EI2;\n input P28EI3;\n input P28EI4;\n input P28EI5;\n input P28EL;\n output P28EO;\n input P28ER;\n input P28RI;\n input P28RL;\n output P28RO1;\n output P28RO2;\n output P28RO3;\n output P28RO4;\n output P28RO5;\n input P28RR;\n input P29CI1;\n input P29CI2;\n input P29CI3;\n input P29CI4;\n input P29CI5;\n input P29CL;\n output P29CO;\n input P29CR;\n input P29CTI;\n output P29CTO;\n input P29EI1;\n input P29EI2;\n input P29EI3;\n input P29EI4;\n input P29EI5;\n input P29EL;\n output P29EO;\n input P29ER;\n input P29RI;\n input P29RL;\n output P29RO1;\n output P29RO2;\n output P29RO3;\n output P29RO4;\n output P29RO5;\n input P29RR;\n input P2CI1;\n input P2CL;\n output P2CO;\n input P2CR;\n input P2CTI;\n output P2CTO;\n input P2EI1;\n input P2EI2;\n input P2EI3;\n input P2EI4;\n input P2EI5;\n input P2EL;\n output P2EO;\n input P2ER;\n input P2RI;\n input P2RL;\n output P2RO1;\n output P2RO2;\n output P2RO3;\n output P2RO4;\n output P2RO5;\n input P2RR;\n input P30CI1;\n input P30CL;\n output P30CO;\n input P30CR;\n input P30CTI;\n output P30CTO;\n input P30EI1;\n input P30EI2;\n input P30EI3;\n input P30EI4;\n input P30EI5;\n input P30EL;\n output P30EO;\n input P30ER;\n input P30RI;\n input P30RL;\n output P30RO1;\n output P30RO2;\n output P30RO3;\n output P30RO4;\n output P30RO5;\n input P30RR;\n input P31CI1;\n input P31CL;\n output P31CO;\n input P31CR;\n input P31CTI;\n output P31CTO;\n input P31EI1;\n input P31EI2;\n input P31EI3;\n input P31EI4;\n input P31EI5;\n input P31EL;\n output P31EO;\n input P31ER;\n input P31RI;\n input P31RL;\n output P31RO1;\n output P31RO2;\n output P31RO3;\n output P31RO4;\n output P31RO5;\n input P31RR;\n input P32CI1;\n input P32CL;\n output P32CO;\n input P32CR;\n input P32CTI;\n output P32CTO;\n input P32EI1;\n input P32EI2;\n input P32EI3;\n input P32EI4;\n input P32EI5;\n input P32EL;\n output P32EO;\n input P32ER;\n input P32RI;\n input P32RL;\n output P32RO1;\n output P32RO2;\n output P32RO3;\n output P32RO4;\n output P32RO5;\n input P32RR;\n input P33CI1;\n input P33CL;\n output P33CO;\n input P33CR;\n input P33CTI;\n output P33CTO;\n input P33EI1;\n input P33EI2;\n input P33EI3;\n input P33EI4;\n input P33EI5;\n input P33EL;\n output P33EO;\n input P33ER;\n input P33RI;\n input P33RL;\n output P33RO1;\n output P33RO2;\n output P33RO3;\n output P33RO4;\n output P33RO5;\n input P33RR;\n input P34CI1;\n input P34CL;\n output P34CO;\n input P34CR;\n input P34CTI;\n output P34CTO;\n input P34EI1;\n input P34EI2;\n input P34EI3;\n input P34EI4;\n input P34EI5;\n input P34EL;\n output P34EO;\n input P34ER;\n input P34RI;\n input P34RL;\n output P34RO1;\n output P34RO2;\n output P34RO3;\n output P34RO4;\n output P34RO5;\n input P34RR;\n input P3CI1;\n input P3CL;\n output P3CO;\n input P3CR;\n input P3CTI;\n output P3CTO;\n input P3EI1;\n input P3EI2;\n input P3EI3;\n input P3EI4;\n input P3EI5;\n input P3EL;\n output P3EO;\n input P3ER;\n input P3RI;\n input P3RL;\n output P3RO1;\n output P3RO2;\n output P3RO3;\n output P3RO4;\n output P3RO5;\n input P3RR;\n input P4CI1;\n input P4CL;\n output P4CO;\n input P4CR;\n input P4CTI;\n output P4CTO;\n input P4EI1;\n input P4EI2;\n input P4EI3;\n input P4EI4;\n input P4EI5;\n input P4EL;\n output P4EO;\n input P4ER;\n input P4RI;\n input P4RL;\n output P4RO1;\n output P4RO2;\n output P4RO3;\n output P4RO4;\n output P4RO5;\n input P4RR;\n input P5CI1;\n input P5CI2;\n input P5CI3;\n input P5CI4;\n input P5CI5;\n input P5CL;\n output P5CO;\n input P5CR;\n input P5CTI;\n output P5CTO;\n input P5EI1;\n input P5EI2;\n input P5EI3;\n input P5EI4;\n input P5EI5;\n input P5EL;\n output P5EO;\n input P5ER;\n input P5RI;\n input P5RL;\n output P5RO1;\n output P5RO2;\n output P5RO3;\n output P5RO4;\n output P5RO5;\n input P5RR;\n input P6CI1;\n input P6CL;\n output P6CO;\n input P6CR;\n input P6CTI;\n output P6CTO;\n input P6EI1;\n input P6EI2;\n input P6EI3;\n input P6EI4;\n input P6EI5;\n input P6EL;\n output P6EO;\n input P6ER;\n input P6RI;\n input P6RL;\n output P6RO1;\n output P6RO2;\n output P6RO3;\n output P6RO4;\n output P6RO5;\n input P6RR;\n input P7CI1;\n input P7CL;\n output P7CO;\n input P7CR;\n input P7CTI;\n output P7CTO;\n input P7EI1;\n input P7EI2;\n input P7EI3;\n input P7EI4;\n input P7EI5;\n input P7EL;\n output P7EO;\n input P7ER;\n input P7RI;\n input P7RL;\n output P7RO1;\n output P7RO2;\n output P7RO3;\n output P7RO4;\n output P7RO5;\n input P7RR;\n input P8CI1;\n input P8CL;\n output P8CO;\n input P8CR;\n input P8CTI;\n output P8CTO;\n input P8EI1;\n input P8EI2;\n input P8EI3;\n input P8EI4;\n input P8EI5;\n input P8EL;\n output P8EO;\n input P8ER;\n input P8RI;\n input P8RL;\n output P8RO1;\n output P8RO2;\n output P8RO3;\n output P8RO4;\n output P8RO5;\n input P8RR;\n input P9CI1;\n input P9CL;\n output P9CO;\n input P9CR;\n input P9CTI;\n output P9CTO;\n input P9EI1;\n input P9EI2;\n input P9EI3;\n input P9EI4;\n input P9EI5;\n input P9EL;\n output P9EO;\n input P9ER;\n input P9RI;\n input P9RL;\n output P9RO1;\n output P9RO2;\n output P9RO3;\n output P9RO4;\n output P9RO5;\n input P9RR;\n input RRCK1;\n input RRCK2;\n input RTCK1;\n input RTCK2;\n input WRCK1;\n input WRCK2;\n input WTCK1;\n input WTCK2;\n parameter div_rx1 = 4'b0000;\n parameter div_rx2 = 4'b0000;\n parameter div_tx1 = 4'b0000;\n parameter div_tx2 = 4'b0000;\n parameter mode_io_cal = 1'b0;\n parameter mode_side1 = 0;\n parameter mode_side2 = 0;\n parameter pads_dict = \"\";\n parameter pads_path = \"\";\n parameter sel_clk_out1 = 1'b0;\n parameter sel_clk_out2 = 1'b0;\n parameter sel_clkr_rx1 = 1'b0;\n parameter sel_clkr_rx2 = 1'b0;\n parameter sel_clkw_rx1 = 2'b00;\n parameter sel_clkw_rx2 = 2'b00;\nendmodule\n\n(* blackbox *)\nmodule NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2\n, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3\n, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2\n, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2\n, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7\n, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2\n, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0);\n input CAL_1P_I1;\n input CAL_1P_I2;\n input CAL_1P_I3;\n input CAL_1P_I4;\n input CAL_1P_I5;\n input CAL_1P_I6;\n input CAL_1P_I7;\n input CAL_1P_I8;\n input CAL_2N_I1;\n input CAL_2N_I2;\n input CAL_2N_I3;\n input CAL_2N_I4;\n input CAL_2N_I5;\n input CAL_2N_I6;\n input CAL_2N_I7;\n input CAL_2N_I8;\n input CAL_3N_I1;\n input CAL_3N_I2;\n input CAL_3N_I3;\n input CAL_3N_I4;\n input CAL_3N_I5;\n input CAL_3N_I6;\n input CAL_3N_I7;\n input CAL_3N_I8;\n input CAL_4P_I1;\n input CAL_4P_I2;\n input CAL_4P_I3;\n input CAL_4P_I4;\n input CAL_4P_I5;\n input CAL_4P_I6;\n input CAL_4P_I7;\n input CAL_4P_I8;\n input CAL_E_I;\n output CAL_O;\n input CAL_SEL_I1;\n input CAL_SEL_I2;\n input CAL_SEL_I3;\n input CAL_SEL_I4;\n input CLK_EXT_I;\n output CLK_O;\n input CLK_REF_I;\n input CLK_USER_I;\n input CT_CAP_I1;\n input CT_CAP_I2;\n input CT_CAP_I3;\n input CT_CAP_I4;\n input CT_RESN_I1;\n input CT_RESN_I2;\n input CT_RESN_I3;\n input CT_RESN_I4;\n input CT_RESP_I1;\n input CT_RESP_I2;\n input CT_RESP_I3;\n input CT_RESP_I4;\n inout [9:0] LINK_RX0;\n inout [9:0] LINK_RX1;\n inout [9:0] LINK_RX2;\n inout [9:0] LINK_RX3;\n inout [9:0] LINK_RX4;\n inout [9:0] LINK_RX5;\n inout [19:0] LINK_TX0;\n inout [19:0] LINK_TX1;\n inout [19:0] LINK_TX2;\n inout [19:0] LINK_TX3;\n inout [19:0] LINK_TX4;\n inout [19:0] LINK_TX5;\n input LOCK_E_I;\n output LOCK_O;\n input MAIN_EN_I1;\n input MAIN_EN_I2;\n input MAIN_EN_I3;\n input MAIN_EN_I4;\n input MAIN_EN_I5;\n input MAIN_EN_I6;\n input MAIN_SG_I;\n input MARG_ISV_I1;\n input MARG_ISV_I2;\n input MARG_ISV_I3;\n input MARG_ISV_I4;\n input MARG_ISV_I5;\n input MARG_IS_I1;\n input MARG_IS_I2;\n input MARG_IS_I3;\n input MARG_IS_I4;\n input MARG_SV_I1;\n input MARG_SV_I2;\n input MARG_SV_I3;\n input MARG_SV_I4;\n input MARG_SV_I5;\n input MARG_S_I1;\n input MARG_S_I2;\n input MARG_S_I3;\n input MARG_S_I4;\n input M_EYE_I;\n input OVS_E_I;\n input PLL_RN_I;\n input POST_EN_I1;\n input POST_EN_I2;\n input POST_EN_I3;\n input POST_EN_I4;\n input POST_EN_I5;\n input POST_ISV_I1;\n input POST_ISV_I2;\n input POST_ISV_I3;\n input POST_ISV_I4;\n input POST_IS_I1;\n input POST_IS_I2;\n input POST_IS_I3;\n input POST_IS_I4;\n input POST_SG_I;\n input PRE_EN_I;\n input PRE_IS_I1;\n input PRE_IS_I2;\n input PRE_IS_I3;\n input PRE_IS_I4;\n input PRE_SG_I;\n input RST_N_I;\n input RX_SEL_I1;\n input RX_SEL_I2;\n input RX_SEL_I3;\n input RX_SEL_I4;\n input RX_SEL_I5;\n input RX_SEL_I6;\n input TST_I1;\n input TST_I2;\n input TST_I3;\n input TST_I4;\n input TST_I5;\n input TST_I6;\n input TST_I7;\n input TST_I8;\n output TST_O1;\n output TST_O2;\n output TST_O3;\n output TST_O4;\n output TST_O5;\n output TST_O6;\n output TST_O7;\n output TST_O8;\n input TX_SEL_I1;\n input TX_SEL_I2;\n input TX_SEL_I3;\n input TX_SEL_I4;\n input TX_SEL_I5;\n input TX_SEL_I6;\n parameter location = \"\";\n parameter main_clk_to_fabric_div_en = 1'b0;\n parameter main_clk_to_fabric_div_mode = 1'b0;\n parameter main_clk_to_fabric_sel = 1'b0;\n parameter main_test = 8'b00000000;\n parameter main_use_only_usr_clock = 1'b0;\n parameter main_use_pcs_clk_2 = 1'b0;\n parameter pcs_ovs_mode = 1'b0;\n parameter pcs_pll_lock_count = 3'b000;\n parameter pcs_word_len = 2'b00;\n parameter pll_pma_cpump_n = 3'b000;\n parameter pll_pma_divf = 2'b00;\n parameter pll_pma_divf_en_n = 1'b0;\n parameter pll_pma_divm = 2'b00;\n parameter pll_pma_divm_en_n = 1'b0;\n parameter pll_pma_divn = 1'b0;\n parameter pll_pma_divn_en_n = 1'b0;\n parameter pll_pma_int_data_len = 1'b0;\n parameter pll_pma_lvds_mux = 1'b0;\n parameter pll_pma_mux_ckref = 1'b0;\n parameter rx_pma_half_step = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1\n, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6\n, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);\n output COR;\n output ERR;\n input I1;\n input I10;\n input I11;\n input I12;\n input I13;\n input I14;\n input I15;\n input I16;\n input I2;\n input I3;\n input I4;\n input I5;\n input I6;\n input I7;\n input I8;\n input I9;\n output O1;\n output O10;\n output O11;\n output O12;\n output O13;\n output O14;\n output O15;\n output O16;\n output O2;\n output O3;\n output O4;\n output O5;\n output O6;\n output O7;\n output O8;\n output O9;\n input RA1;\n input RA2;\n input RA3;\n input RA4;\n input RA5;\n input RA6;\n input RCK;\n input RE;\n input WA1;\n input WA2;\n input WA3;\n input WA4;\n input WA5;\n input WA6;\n input WCK;\n input WE;\n parameter mem_ctxt = \"\";\n parameter mode = 0;\n parameter rck_edge = 1'b0;\n parameter wck_edge = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3\n, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3\n, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1\n, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4\n, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19\n, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);\n output C1RED;\n input C1RNE;\n input C1RS;\n input C1RW1;\n input C1RW2;\n input C1RW3;\n input C1TS;\n input C1TW;\n output C2RED;\n input C2RNE;\n input C2RS;\n input C2RW1;\n input C2RW2;\n input C2RW3;\n input C2TS;\n input C2TW;\n input CAD1;\n input CAD2;\n input CAD3;\n input CAD4;\n input CAD5;\n input CAD6;\n output CAL;\n input CAN1;\n input CAN2;\n input CAN3;\n input CAN4;\n input CAP1;\n input CAP2;\n input CAP3;\n input CAP4;\n input CAT1;\n input CAT2;\n input CAT3;\n input CAT4;\n input CCK;\n output CKO1;\n output CKO2;\n input CTCK;\n input DC;\n input DCK;\n input DIG;\n input DIS;\n input DOG;\n input DOS;\n input DPAG;\n input DPAS;\n input DQSG;\n input DQSS;\n input DRA1;\n input DRA2;\n input DRA3;\n input DRA4;\n input DRA5;\n input DRA6;\n input DRI1;\n input DRI2;\n input DRI3;\n input DRI4;\n input DRI5;\n input DRI6;\n input DRL;\n output DRO1;\n output DRO2;\n output DRO3;\n output DRO4;\n output DRO5;\n output DRO6;\n input DS1;\n input DS2;\n input FA1;\n input FA2;\n input FA3;\n input FA4;\n input FA5;\n input FA6;\n output FLD;\n output FLG;\n input FZ;\n inout [41:0] LINK1;\n inout [41:0] LINK10;\n inout [41:0] LINK11;\n inout [41:0] LINK12;\n inout [41:0] LINK13;\n inout [41:0] LINK14;\n inout [41:0] LINK15;\n inout [41:0] LINK16;\n inout [41:0] LINK17;\n inout [41:0] LINK18;\n inout [41:0] LINK19;\n inout [41:0] LINK2;\n inout [41:0] LINK20;\n inout [41:0] LINK21;\n inout [41:0] LINK22;\n inout [41:0] LINK23;\n inout [41:0] LINK24;\n inout [41:0] LINK25;\n inout [41:0] LINK26;\n inout [41:0] LINK27;\n inout [41:0] LINK28;\n inout [41:0] LINK29;\n inout [41:0] LINK3;\n inout [41:0] LINK30;\n inout [41:0] LINK31;\n inout [41:0] LINK32;\n inout [41:0] LINK33;\n inout [41:0] LINK34;\n inout [41:0] LINK4;\n inout [41:0] LINK5;\n inout [41:0] LINK6;\n inout [41:0] LINK7;\n inout [41:0] LINK8;\n inout [41:0] LINK9;\n input RRCK1;\n input RRCK2;\n input RTCK1;\n input RTCK2;\n input WRCK1;\n input WRCK2;\n input WTCK1;\n input WTCK2;\n parameter div_rx1 = 4'b0000;\n parameter div_rx2 = 4'b0000;\n parameter div_tx1 = 4'b0000;\n parameter div_tx2 = 4'b0000;\n parameter inv_di_fclk1 = 1'b0;\n parameter inv_di_fclk2 = 1'b0;\n parameter latency1 = 1'b0;\n parameter latency2 = 1'b0;\n parameter location = \"\";\n parameter mode_cpath = \"\";\n parameter mode_epath = \"\";\n parameter mode_io_cal = 1'b0;\n parameter mode_rpath = \"\";\n parameter mode_side1 = 0;\n parameter mode_side2 = 0;\n parameter mode_tpath = \"\";\n parameter sel_clk_out1 = 1'b0;\n parameter sel_clk_out2 = 1'b0;\n parameter sel_clkr_rx1 = 1'b0;\n parameter sel_clkr_rx2 = 1'b0;\n parameter sel_clkw_rx1 = 2'b00;\n parameter sel_clkw_rx2 = 2'b00;\nendmodule\n\n",
301
+ "cells_bb_m.v": "(* blackbox *)\nmodule NX_CKS(CKI, CMD, CKO);\n input CKI;\n output CKO;\n input CMD;\n parameter ck_edge = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21\n, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18\n, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21\n, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6\n, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9\n, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12\n, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15\n, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11\n, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32\n, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53\n, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18\n, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39\n, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4\n, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3\n, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24\n, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45\n, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56);\n input A1;\n input A10;\n input A11;\n input A12;\n input A13;\n input A14;\n input A15;\n input A16;\n input A17;\n input A18;\n input A19;\n input A2;\n input A20;\n input A21;\n input A22;\n input A23;\n input A24;\n input A3;\n input A4;\n input A5;\n input A6;\n input A7;\n input A8;\n input A9;\n input B1;\n input B10;\n input B11;\n input B12;\n input B13;\n input B14;\n input B15;\n input B16;\n input B17;\n input B18;\n input B2;\n input B3;\n input B4;\n input B5;\n input B6;\n input B7;\n input B8;\n input B9;\n input C1;\n input C10;\n input C11;\n input C12;\n input C13;\n input C14;\n input C15;\n input C16;\n input C17;\n input C18;\n input C19;\n input C2;\n input C20;\n input C21;\n input C22;\n input C23;\n input C24;\n input C25;\n input C26;\n input C27;\n input C28;\n input C29;\n input C3;\n input C30;\n input C31;\n input C32;\n input C33;\n input C34;\n input C35;\n input C36;\n input C4;\n input C5;\n input C6;\n input C7;\n input C8;\n input C9;\n input CAI1;\n input CAI10;\n input CAI11;\n input CAI12;\n input CAI13;\n input CAI14;\n input CAI15;\n input CAI16;\n input CAI17;\n input CAI18;\n input CAI2;\n input CAI3;\n input CAI4;\n input CAI5;\n input CAI6;\n input CAI7;\n input CAI8;\n input CAI9;\n output CAO1;\n output CAO10;\n output CAO11;\n output CAO12;\n output CAO13;\n output CAO14;\n output CAO15;\n output CAO16;\n output CAO17;\n output CAO18;\n output CAO2;\n output CAO3;\n output CAO4;\n output CAO5;\n output CAO6;\n output CAO7;\n output CAO8;\n output CAO9;\n input CBI1;\n input CBI10;\n input CBI11;\n input CBI12;\n input CBI13;\n input CBI14;\n input CBI15;\n input CBI16;\n input CBI17;\n input CBI18;\n input CBI2;\n input CBI3;\n input CBI4;\n input CBI5;\n input CBI6;\n input CBI7;\n input CBI8;\n input CBI9;\n output CBO1;\n output CBO10;\n output CBO11;\n output CBO12;\n output CBO13;\n output CBO14;\n output CBO15;\n output CBO16;\n output CBO17;\n output CBO18;\n output CBO2;\n output CBO3;\n output CBO4;\n output CBO5;\n output CBO6;\n output CBO7;\n output CBO8;\n output CBO9;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO;\n output CO37;\n output CO49;\n input CZI1;\n input CZI10;\n input CZI11;\n input CZI12;\n input CZI13;\n input CZI14;\n input CZI15;\n input CZI16;\n input CZI17;\n input CZI18;\n input CZI19;\n input CZI2;\n input CZI20;\n input CZI21;\n input CZI22;\n input CZI23;\n input CZI24;\n input CZI25;\n input CZI26;\n input CZI27;\n input CZI28;\n input CZI29;\n input CZI3;\n input CZI30;\n input CZI31;\n input CZI32;\n input CZI33;\n input CZI34;\n input CZI35;\n input CZI36;\n input CZI37;\n input CZI38;\n input CZI39;\n input CZI4;\n input CZI40;\n input CZI41;\n input CZI42;\n input CZI43;\n input CZI44;\n input CZI45;\n input CZI46;\n input CZI47;\n input CZI48;\n input CZI49;\n input CZI5;\n input CZI50;\n input CZI51;\n input CZI52;\n input CZI53;\n input CZI54;\n input CZI55;\n input CZI56;\n input CZI6;\n input CZI7;\n input CZI8;\n input CZI9;\n output CZO1;\n output CZO10;\n output CZO11;\n output CZO12;\n output CZO13;\n output CZO14;\n output CZO15;\n output CZO16;\n output CZO17;\n output CZO18;\n output CZO19;\n output CZO2;\n output CZO20;\n output CZO21;\n output CZO22;\n output CZO23;\n output CZO24;\n output CZO25;\n output CZO26;\n output CZO27;\n output CZO28;\n output CZO29;\n output CZO3;\n output CZO30;\n output CZO31;\n output CZO32;\n output CZO33;\n output CZO34;\n output CZO35;\n output CZO36;\n output CZO37;\n output CZO38;\n output CZO39;\n output CZO4;\n output CZO40;\n output CZO41;\n output CZO42;\n output CZO43;\n output CZO44;\n output CZO45;\n output CZO46;\n output CZO47;\n output CZO48;\n output CZO49;\n output CZO5;\n output CZO50;\n output CZO51;\n output CZO52;\n output CZO53;\n output CZO54;\n output CZO55;\n output CZO56;\n output CZO6;\n output CZO7;\n output CZO8;\n output CZO9;\n input D1;\n input D10;\n input D11;\n input D12;\n input D13;\n input D14;\n input D15;\n input D16;\n input D17;\n input D18;\n input D2;\n input D3;\n input D4;\n input D5;\n input D6;\n input D7;\n input D8;\n input D9;\n output OVF;\n input R;\n input RZ;\n input WE;\n output Z1;\n output Z10;\n output Z11;\n output Z12;\n output Z13;\n output Z14;\n output Z15;\n output Z16;\n output Z17;\n output Z18;\n output Z19;\n output Z2;\n output Z20;\n output Z21;\n output Z22;\n output Z23;\n output Z24;\n output Z25;\n output Z26;\n output Z27;\n output Z28;\n output Z29;\n output Z3;\n output Z30;\n output Z31;\n output Z32;\n output Z33;\n output Z34;\n output Z35;\n output Z36;\n output Z37;\n output Z38;\n output Z39;\n output Z4;\n output Z40;\n output Z41;\n output Z42;\n output Z43;\n output Z44;\n output Z45;\n output Z46;\n output Z47;\n output Z48;\n output Z49;\n output Z5;\n output Z50;\n output Z51;\n output Z52;\n output Z53;\n output Z54;\n output Z55;\n output Z56;\n output Z6;\n output Z7;\n output Z8;\n output Z9;\n parameter raw_config0 = 20'b00000000000000000000;\n parameter raw_config1 = 19'b0000000000000000000;\n parameter raw_config2 = 13'b0000000000000;\n parameter raw_config3 = 7'b0000000;\n parameter std_mode = \"\";\nendmodule\n\n(* blackbox *)\nmodule NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);\n output D1;\n output D2;\n output D3;\n input FBK;\n output OSC;\n output RDY;\n input REF;\n output VCO;\n parameter clk_outdiv1 = 0;\n parameter clk_outdiv2 = 0;\n parameter clk_outdiv3 = 0;\n parameter ext_fbk_on = 1'b0;\n parameter fbk_delay = 0;\n parameter fbk_delay_on = 1'b0;\n parameter fbk_div_on = 1'b0;\n parameter fbk_intdiv = 2;\n parameter location = \"\";\n parameter ref_div_on = 1'b0;\n parameter vco_range = 0;\nendmodule\n\n(* blackbox *)\nmodule NX_WFG(SI, ZI, RDY, SO, ZO);\n input RDY;\n input SI;\n output SO;\n input ZI;\n output ZO;\n parameter delay = 0;\n parameter delay_on = 1'b0;\n parameter location = \"\";\n parameter mode = 1'b0;\n parameter pattern = 16'b0000000000000000;\n parameter pattern_end = 1;\n parameter wfg_edge = 1'b0;\nendmodule\n\n\n(* blackbox *)\nmodule NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1\n, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4\n, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3\n, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3\n, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR\n, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL\n, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI\n, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO\n, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3\n, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2\n, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1\n, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO\n, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI\n, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO\n, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR\n, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL\n, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1\n, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5\n, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4\n, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3\n, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2\n, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1\n, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR\n, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL\n, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI\n, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO\n, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER\n, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL\n, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5\n, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO\n, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI\n, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO\n, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR\n, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL\n, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1\n, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5\n);\n output C1RED;\n input C1RNE;\n input C1RS;\n input C1RW1;\n input C1RW2;\n input C1RW3;\n input C1TS;\n input C1TW;\n output C2RED;\n input C2RNE;\n input C2RS;\n input C2RW1;\n input C2RW2;\n input C2RW3;\n input C2TS;\n input C2TW;\n input CAD1;\n input CAD2;\n input CAD3;\n input CAD4;\n input CAD5;\n input CAD6;\n output CAL;\n input CAN1;\n input CAN2;\n input CAN3;\n input CAN4;\n input CAP1;\n input CAP2;\n input CAP3;\n input CAP4;\n input CAT1;\n input CAT2;\n input CAT3;\n input CAT4;\n input CCK;\n output CKO1;\n output CKO2;\n input CTCK;\n input DC;\n input DCK;\n input DIG;\n input DIS;\n input DOG;\n input DOS;\n input DPAG;\n input DPAS;\n input DQSG;\n input DQSS;\n input DRA1;\n input DRA2;\n input DRA3;\n input DRA4;\n input DRA5;\n input DRI1;\n input DRI2;\n input DRI3;\n input DRI4;\n input DRI5;\n input DRI6;\n input DRL;\n output DRO1;\n output DRO2;\n output DRO3;\n output DRO4;\n output DRO5;\n output DRO6;\n input DS1;\n input DS2;\n input FA1;\n input FA2;\n input FA3;\n input FA4;\n input FA5;\n output FLD;\n output FLG;\n input FZ;\n input P10CI1;\n input P10CL;\n output P10CO;\n input P10CR;\n input P10CTI;\n output P10CTO;\n input P10EI1;\n input P10EI2;\n input P10EI3;\n input P10EI4;\n input P10EI5;\n input P10EL;\n output P10EO;\n input P10ER;\n input P10RI;\n input P10RL;\n output P10RO1;\n output P10RO2;\n output P10RO3;\n output P10RO4;\n output P10RO5;\n input P10RR;\n input P11CI1;\n input P11CL;\n output P11CO;\n input P11CR;\n input P11CTI;\n output P11CTO;\n input P11EI1;\n input P11EI2;\n input P11EI3;\n input P11EI4;\n input P11EI5;\n input P11EL;\n output P11EO;\n input P11ER;\n input P11RI;\n input P11RL;\n output P11RO1;\n output P11RO2;\n output P11RO3;\n output P11RO4;\n output P11RO5;\n input P11RR;\n input P12CI1;\n input P12CL;\n output P12CO;\n input P12CR;\n input P12CTI;\n output P12CTO;\n input P12EI1;\n input P12EI2;\n input P12EI3;\n input P12EI4;\n input P12EI5;\n input P12EL;\n output P12EO;\n input P12ER;\n input P12RI;\n input P12RL;\n output P12RO1;\n output P12RO2;\n output P12RO3;\n output P12RO4;\n output P12RO5;\n input P12RR;\n input P13CI1;\n input P13CL;\n output P13CO;\n input P13CR;\n input P13CTI;\n output P13CTO;\n input P13EI1;\n input P13EI2;\n input P13EI3;\n input P13EI4;\n input P13EI5;\n input P13EL;\n output P13EO;\n input P13ER;\n input P13RI;\n input P13RL;\n output P13RO1;\n output P13RO2;\n output P13RO3;\n output P13RO4;\n output P13RO5;\n input P13RR;\n input P14CI1;\n input P14CL;\n output P14CO;\n input P14CR;\n input P14CTI;\n output P14CTO;\n input P14EI1;\n input P14EI2;\n input P14EI3;\n input P14EI4;\n input P14EI5;\n input P14EL;\n output P14EO;\n input P14ER;\n input P14RI;\n input P14RL;\n output P14RO1;\n output P14RO2;\n output P14RO3;\n output P14RO4;\n output P14RO5;\n input P14RR;\n input P15CI1;\n input P15CL;\n output P15CO;\n input P15CR;\n input P15CTI;\n output P15CTO;\n input P15EI1;\n input P15EI2;\n input P15EI3;\n input P15EI4;\n input P15EI5;\n input P15EL;\n output P15EO;\n input P15ER;\n input P15RI;\n input P15RL;\n output P15RO1;\n output P15RO2;\n output P15RO3;\n output P15RO4;\n output P15RO5;\n input P15RR;\n input P16CI1;\n input P16CL;\n output P16CO;\n input P16CR;\n input P16CTI;\n output P16CTO;\n input P16EI1;\n input P16EI2;\n input P16EI3;\n input P16EI4;\n input P16EI5;\n input P16EL;\n output P16EO;\n input P16ER;\n input P16RI;\n input P16RL;\n output P16RO1;\n output P16RO2;\n output P16RO3;\n output P16RO4;\n output P16RO5;\n input P16RR;\n input P17CI1;\n input P17CL;\n output P17CO;\n input P17CR;\n input P17CTI;\n output P17CTO;\n input P17EI1;\n input P17EI2;\n input P17EI3;\n input P17EI4;\n input P17EI5;\n input P17EL;\n output P17EO;\n input P17ER;\n input P17RI;\n input P17RL;\n output P17RO1;\n output P17RO2;\n output P17RO3;\n output P17RO4;\n output P17RO5;\n input P17RR;\n input P18CI1;\n input P18CL;\n output P18CO;\n input P18CR;\n input P18CTI;\n output P18CTO;\n input P18EI1;\n input P18EI2;\n input P18EI3;\n input P18EI4;\n input P18EI5;\n input P18EL;\n output P18EO;\n input P18ER;\n input P18RI;\n input P18RL;\n output P18RO1;\n output P18RO2;\n output P18RO3;\n output P18RO4;\n output P18RO5;\n input P18RR;\n input P19CI1;\n input P19CL;\n output P19CO;\n input P19CR;\n input P19CTI;\n output P19CTO;\n input P19EI1;\n input P19EI2;\n input P19EI3;\n input P19EI4;\n input P19EI5;\n input P19EL;\n output P19EO;\n input P19ER;\n input P19RI;\n input P19RL;\n output P19RO1;\n output P19RO2;\n output P19RO3;\n output P19RO4;\n output P19RO5;\n input P19RR;\n input P1CI1;\n input P1CL;\n output P1CO;\n input P1CR;\n input P1CTI;\n output P1CTO;\n input P1EI1;\n input P1EI2;\n input P1EI3;\n input P1EI4;\n input P1EI5;\n input P1EL;\n output P1EO;\n input P1ER;\n input P1RI;\n input P1RL;\n output P1RO1;\n output P1RO2;\n output P1RO3;\n output P1RO4;\n output P1RO5;\n input P1RR;\n input P20CI1;\n input P20CL;\n output P20CO;\n input P20CR;\n input P20CTI;\n output P20CTO;\n input P20EI1;\n input P20EI2;\n input P20EI3;\n input P20EI4;\n input P20EI5;\n input P20EL;\n output P20EO;\n input P20ER;\n input P20RI;\n input P20RL;\n output P20RO1;\n output P20RO2;\n output P20RO3;\n output P20RO4;\n output P20RO5;\n input P20RR;\n input P21CI1;\n input P21CL;\n output P21CO;\n input P21CR;\n input P21CTI;\n output P21CTO;\n input P21EI1;\n input P21EI2;\n input P21EI3;\n input P21EI4;\n input P21EI5;\n input P21EL;\n output P21EO;\n input P21ER;\n input P21RI;\n input P21RL;\n output P21RO1;\n output P21RO2;\n output P21RO3;\n output P21RO4;\n output P21RO5;\n input P21RR;\n input P22CI1;\n input P22CL;\n output P22CO;\n input P22CR;\n input P22CTI;\n output P22CTO;\n input P22EI1;\n input P22EI2;\n input P22EI3;\n input P22EI4;\n input P22EI5;\n input P22EL;\n output P22EO;\n input P22ER;\n input P22RI;\n input P22RL;\n output P22RO1;\n output P22RO2;\n output P22RO3;\n output P22RO4;\n output P22RO5;\n input P22RR;\n input P23CI1;\n input P23CL;\n output P23CO;\n input P23CR;\n input P23CTI;\n output P23CTO;\n input P23EI1;\n input P23EI2;\n input P23EI3;\n input P23EI4;\n input P23EI5;\n input P23EL;\n output P23EO;\n input P23ER;\n input P23RI;\n input P23RL;\n output P23RO1;\n output P23RO2;\n output P23RO3;\n output P23RO4;\n output P23RO5;\n input P23RR;\n input P24CI1;\n input P24CL;\n output P24CO;\n input P24CR;\n input P24CTI;\n output P24CTO;\n input P24EI1;\n input P24EI2;\n input P24EI3;\n input P24EI4;\n input P24EI5;\n input P24EL;\n output P24EO;\n input P24ER;\n input P24RI;\n input P24RL;\n output P24RO1;\n output P24RO2;\n output P24RO3;\n output P24RO4;\n output P24RO5;\n input P24RR;\n input P25CI1;\n input P25CI2;\n input P25CI3;\n input P25CI4;\n input P25CI5;\n input P25CL;\n output P25CO;\n input P25CR;\n input P25CTI;\n output P25CTO;\n input P25EI1;\n input P25EI2;\n input P25EI3;\n input P25EI4;\n input P25EI5;\n input P25EL;\n output P25EO;\n input P25ER;\n input P25RI;\n input P25RL;\n output P25RO1;\n output P25RO2;\n output P25RO3;\n output P25RO4;\n output P25RO5;\n input P25RR;\n input P26CI1;\n input P26CL;\n output P26CO;\n input P26CR;\n input P26CTI;\n output P26CTO;\n input P26EI1;\n input P26EI2;\n input P26EI3;\n input P26EI4;\n input P26EI5;\n input P26EL;\n output P26EO;\n input P26ER;\n input P26RI;\n input P26RL;\n output P26RO1;\n output P26RO2;\n output P26RO3;\n output P26RO4;\n output P26RO5;\n input P26RR;\n input P27CI1;\n input P27CL;\n output P27CO;\n input P27CR;\n input P27CTI;\n output P27CTO;\n input P27EI1;\n input P27EI2;\n input P27EI3;\n input P27EI4;\n input P27EI5;\n input P27EL;\n output P27EO;\n input P27ER;\n input P27RI;\n input P27RL;\n output P27RO1;\n output P27RO2;\n output P27RO3;\n output P27RO4;\n output P27RO5;\n input P27RR;\n input P28CI1;\n input P28CL;\n output P28CO;\n input P28CR;\n input P28CTI;\n output P28CTO;\n input P28EI1;\n input P28EI2;\n input P28EI3;\n input P28EI4;\n input P28EI5;\n input P28EL;\n output P28EO;\n input P28ER;\n input P28RI;\n input P28RL;\n output P28RO1;\n output P28RO2;\n output P28RO3;\n output P28RO4;\n output P28RO5;\n input P28RR;\n input P29CI1;\n input P29CL;\n output P29CO;\n input P29CR;\n input P29CTI;\n output P29CTO;\n input P29EI1;\n input P29EI2;\n input P29EI3;\n input P29EI4;\n input P29EI5;\n input P29EL;\n output P29EO;\n input P29ER;\n input P29RI;\n input P29RL;\n output P29RO1;\n output P29RO2;\n output P29RO3;\n output P29RO4;\n output P29RO5;\n input P29RR;\n input P2CI1;\n input P2CL;\n output P2CO;\n input P2CR;\n input P2CTI;\n output P2CTO;\n input P2EI1;\n input P2EI2;\n input P2EI3;\n input P2EI4;\n input P2EI5;\n input P2EL;\n output P2EO;\n input P2ER;\n input P2RI;\n input P2RL;\n output P2RO1;\n output P2RO2;\n output P2RO3;\n output P2RO4;\n output P2RO5;\n input P2RR;\n input P30CI1;\n input P30CL;\n output P30CO;\n input P30CR;\n input P30CTI;\n output P30CTO;\n input P30EI1;\n input P30EI2;\n input P30EI3;\n input P30EI4;\n input P30EI5;\n input P30EL;\n output P30EO;\n input P30ER;\n input P30RI;\n input P30RL;\n output P30RO1;\n output P30RO2;\n output P30RO3;\n output P30RO4;\n output P30RO5;\n input P30RR;\n input P3CI1;\n input P3CL;\n output P3CO;\n input P3CR;\n input P3CTI;\n output P3CTO;\n input P3EI1;\n input P3EI2;\n input P3EI3;\n input P3EI4;\n input P3EI5;\n input P3EL;\n output P3EO;\n input P3ER;\n input P3RI;\n input P3RL;\n output P3RO1;\n output P3RO2;\n output P3RO3;\n output P3RO4;\n output P3RO5;\n input P3RR;\n input P4CI1;\n input P4CL;\n output P4CO;\n input P4CR;\n input P4CTI;\n output P4CTO;\n input P4EI1;\n input P4EI2;\n input P4EI3;\n input P4EI4;\n input P4EI5;\n input P4EL;\n output P4EO;\n input P4ER;\n input P4RI;\n input P4RL;\n output P4RO1;\n output P4RO2;\n output P4RO3;\n output P4RO4;\n output P4RO5;\n input P4RR;\n input P5CI1;\n input P5CI2;\n input P5CI3;\n input P5CI4;\n input P5CI5;\n input P5CL;\n output P5CO;\n input P5CR;\n input P5CTI;\n output P5CTO;\n input P5EI1;\n input P5EI2;\n input P5EI3;\n input P5EI4;\n input P5EI5;\n input P5EL;\n output P5EO;\n input P5ER;\n input P5RI;\n input P5RL;\n output P5RO1;\n output P5RO2;\n output P5RO3;\n output P5RO4;\n output P5RO5;\n input P5RR;\n input P6CI1;\n input P6CL;\n output P6CO;\n input P6CR;\n input P6CTI;\n output P6CTO;\n input P6EI1;\n input P6EI2;\n input P6EI3;\n input P6EI4;\n input P6EI5;\n input P6EL;\n output P6EO;\n input P6ER;\n input P6RI;\n input P6RL;\n output P6RO1;\n output P6RO2;\n output P6RO3;\n output P6RO4;\n output P6RO5;\n input P6RR;\n input P7CI1;\n input P7CL;\n output P7CO;\n input P7CR;\n input P7CTI;\n output P7CTO;\n input P7EI1;\n input P7EI2;\n input P7EI3;\n input P7EI4;\n input P7EI5;\n input P7EL;\n output P7EO;\n input P7ER;\n input P7RI;\n input P7RL;\n output P7RO1;\n output P7RO2;\n output P7RO3;\n output P7RO4;\n output P7RO5;\n input P7RR;\n input P8CI1;\n input P8CL;\n output P8CO;\n input P8CR;\n input P8CTI;\n output P8CTO;\n input P8EI1;\n input P8EI2;\n input P8EI3;\n input P8EI4;\n input P8EI5;\n input P8EL;\n output P8EO;\n input P8ER;\n input P8RI;\n input P8RL;\n output P8RO1;\n output P8RO2;\n output P8RO3;\n output P8RO4;\n output P8RO5;\n input P8RR;\n input P9CI1;\n input P9CL;\n output P9CO;\n input P9CR;\n input P9CTI;\n output P9CTO;\n input P9EI1;\n input P9EI2;\n input P9EI3;\n input P9EI4;\n input P9EI5;\n input P9EL;\n output P9EO;\n input P9ER;\n input P9RI;\n input P9RL;\n output P9RO1;\n output P9RO2;\n output P9RO3;\n output P9RO4;\n output P9RO5;\n input P9RR;\n input RRCK1;\n input RRCK2;\n input RTCK1;\n input RTCK2;\n input SPI1;\n input SPI2;\n input SPI3;\n input WRCK1;\n input WRCK2;\n input WTCK1;\n input WTCK2;\n parameter div_rx1 = 4'b0000;\n parameter div_rx2 = 4'b0000;\n parameter div_tx1 = 4'b0000;\n parameter div_tx2 = 4'b0000;\n parameter mode_io_cal = 1'b0;\n parameter mode_side1 = 0;\n parameter mode_side2 = 0;\n parameter pads_dict = \"\";\n parameter pads_path = \"\";\n parameter sel_clk_out1 = 1'b0;\n parameter sel_clk_out2 = 1'b0;\n parameter sel_clkr_rx1 = 1'b0;\n parameter sel_clkr_rx2 = 1'b0;\n parameter sel_clkw_rx1 = 2'b00;\n parameter sel_clkw_rx2 = 2'b00;\nendmodule\n\n(* blackbox *)\nmodule NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1\n, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6\n, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);\n output COR;\n output ERR;\n input I1;\n input I10;\n input I11;\n input I12;\n input I13;\n input I14;\n input I15;\n input I16;\n input I2;\n input I3;\n input I4;\n input I5;\n input I6;\n input I7;\n input I8;\n input I9;\n output O1;\n output O10;\n output O11;\n output O12;\n output O13;\n output O14;\n output O15;\n output O16;\n output O2;\n output O3;\n output O4;\n output O5;\n output O6;\n output O7;\n output O8;\n output O9;\n input RA1;\n input RA2;\n input RA3;\n input RA4;\n input RA5;\n input RA6;\n input RCK;\n input RE;\n input WA1;\n input WA2;\n input WA3;\n input WA4;\n input WA5;\n input WA6;\n input WCK;\n input WE;\n parameter mem_ctxt = \"\";\n parameter rck_edge = 1'b0;\n parameter wck_edge = 1'b0;\nendmodule\n\n\n(* blackbox *)\nmodule NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3\n, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3\n, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1\n, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1\n, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16\n, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);\n output C1RED;\n input C1RNE;\n input C1RS;\n input C1RW1;\n input C1RW2;\n input C1RW3;\n input C1TS;\n input C1TW;\n output C2RED;\n input C2RNE;\n input C2RS;\n input C2RW1;\n input C2RW2;\n input C2RW3;\n input C2TS;\n input C2TW;\n input CAD1;\n input CAD2;\n input CAD3;\n input CAD4;\n input CAD5;\n input CAD6;\n output CAL;\n input CAN1;\n input CAN2;\n input CAN3;\n input CAN4;\n input CAP1;\n input CAP2;\n input CAP3;\n input CAP4;\n input CAT1;\n input CAT2;\n input CAT3;\n input CAT4;\n input CCK;\n output CKO1;\n output CKO2;\n input CTCK;\n input DC;\n input DCK;\n input DIG;\n input DIS;\n input DOG;\n input DOS;\n input DPAG;\n input DPAS;\n input DQSG;\n input DQSS;\n input DRA1;\n input DRA2;\n input DRA3;\n input DRA4;\n input DRA5;\n input DRA6;\n input DRI1;\n input DRI2;\n input DRI3;\n input DRI4;\n input DRI5;\n input DRI6;\n input DRL;\n output DRO1;\n output DRO2;\n output DRO3;\n output DRO4;\n output DRO5;\n output DRO6;\n input DS1;\n input DS2;\n input FA1;\n input FA2;\n input FA3;\n input FA4;\n input FA5;\n input FA6;\n output FLD;\n output FLG;\n input FZ;\n inout [41:0] LINK1;\n inout [41:0] LINK10;\n inout [41:0] LINK11;\n inout [41:0] LINK12;\n inout [41:0] LINK13;\n inout [41:0] LINK14;\n inout [41:0] LINK15;\n inout [41:0] LINK16;\n inout [41:0] LINK17;\n inout [41:0] LINK18;\n inout [41:0] LINK19;\n inout [41:0] LINK2;\n inout [41:0] LINK20;\n inout [41:0] LINK21;\n inout [41:0] LINK22;\n inout [41:0] LINK23;\n inout [41:0] LINK24;\n inout [41:0] LINK25;\n inout [41:0] LINK26;\n inout [41:0] LINK27;\n inout [41:0] LINK28;\n inout [41:0] LINK29;\n inout [41:0] LINK3;\n inout [41:0] LINK30;\n inout [41:0] LINK31;\n inout [41:0] LINK32;\n inout [41:0] LINK33;\n inout [41:0] LINK34;\n inout [41:0] LINK4;\n inout [41:0] LINK5;\n inout [41:0] LINK6;\n inout [41:0] LINK7;\n inout [41:0] LINK8;\n inout [41:0] LINK9;\n input RRCK1;\n input RRCK2;\n input RTCK1;\n input RTCK2;\n input SPI1;\n input SPI2;\n input SPI3;\n input WRCK1;\n input WRCK2;\n input WTCK1;\n input WTCK2;\n parameter div_rx1 = 4'b0000;\n parameter div_rx2 = 4'b0000;\n parameter div_tx1 = 4'b0000;\n parameter div_tx2 = 4'b0000;\n parameter inv_di_fclk1 = 1'b0;\n parameter inv_di_fclk2 = 1'b0;\n parameter latency1 = 1'b0;\n parameter latency2 = 1'b0;\n parameter location = \"\";\n parameter mode_cpath = \"\";\n parameter mode_epath = \"\";\n parameter mode_io_cal = 1'b0;\n parameter mode_rpath = \"\";\n parameter mode_side1 = 0;\n parameter mode_side2 = 0;\n parameter mode_tpath = \"\";\n parameter sel_clk_out1 = 1'b0;\n parameter sel_clk_out2 = 1'b0;\n parameter sel_clkr_rx1 = 1'b0;\n parameter sel_clkr_rx2 = 1'b0;\n parameter sel_clkw_rx1 = 2'b00;\n parameter sel_clkw_rx2 = 2'b00;\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1\n, RO2, RO3, RO4, RO5, CTO, LINK);\n input CI1;\n input CI2;\n input CI3;\n input CI4;\n input CI5;\n input CL;\n output CO;\n input CR;\n input CTI;\n output CTO;\n input EI1;\n input EI2;\n input EI3;\n input EI4;\n input EI5;\n input EL;\n output EO;\n input ER;\n inout [41:0] LINK;\n input RI;\n input RL;\n output RO1;\n output RO2;\n output RO3;\n output RO4;\n output RO5;\n input RR;\n parameter chained = 1'b0;\n parameter cpath_edge = 1'b0;\n parameter cpath_init = 1'b0;\n parameter cpath_inv = 1'b0;\n parameter cpath_load = 1'b0;\n parameter cpath_mode = 4'b0000;\n parameter cpath_sync = 1'b0;\n parameter epath_dynamic = 1'b0;\n parameter epath_edge = 1'b0;\n parameter epath_init = 1'b0;\n parameter epath_load = 1'b0;\n parameter epath_mode = 4'b0000;\n parameter epath_sync = 1'b0;\n parameter location = \"\";\n parameter rpath_dynamic = 1'b0;\n parameter rpath_edge = 1'b0;\n parameter rpath_init = 1'b0;\n parameter rpath_load = 1'b0;\n parameter rpath_mode = 4'b0000;\n parameter rpath_sync = 1'b0;\n parameter symbol = \"\";\n parameter tpath_mode = 2'b00;\n parameter variant = \"\";\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);\n input CTCK;\n input DCK;\n output [5:0] DID;\n input DIG;\n input [5:0] DRA;\n input [5:0] DRI;\n input DRL;\n output [5:0] DRO;\n input [1:0] DS;\n output FLD;\n output FLG;\n input FZ;\n inout [41:0] LINKN;\n inout [41:0] LINKP;\n input RRCK;\n input RRST;\n input RTCK;\n input TRST;\n input WRCK;\n input WTCK;\n parameter data_size = 5;\n parameter location = \"\";\nendmodule\n\n",
302
+ "cells_bb_u.v": "(* blackbox *)\nmodule NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO\n, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4\n, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3\n, DO4, DO5, DO6);\n input ADRSTI;\n output ADRSTO;\n input AI1;\n input AI2;\n input AI3;\n input AI4;\n input AI5;\n input AI6;\n output AO1;\n output AO2;\n output AO3;\n output AO4;\n output AO5;\n output AO6;\n input ASRSTI;\n output ASRSTO;\n input BDRSTI;\n output BDRSTO;\n input BI1;\n input BI2;\n input BI3;\n input BI4;\n input BI5;\n input BI6;\n output BO1;\n output BO2;\n output BO3;\n output BO4;\n output BO5;\n output BO6;\n input BSRSTI;\n output BSRSTO;\n input CDRSTI;\n output CDRSTO;\n input CI1;\n input CI2;\n input CI3;\n input CI4;\n input CI5;\n input CI6;\n input CK1;\n input CK2;\n output CO1;\n output CO2;\n output CO3;\n output CO4;\n output CO5;\n output CO6;\n input CSRSTI;\n output CSRSTO;\n input DDRSTI;\n output DDRSTO;\n input DI1;\n input DI2;\n input DI3;\n input DI4;\n input DI5;\n input DI6;\n output DO1;\n output DO2;\n output DO3;\n output DO4;\n output DO5;\n output DO6;\n input DSRSTI;\n output DSRSTO;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter cck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter dck_sel = 1'b0;\n parameter link_BA = 1'b0;\n parameter link_CB = 1'b0;\n parameter link_DC = 1'b0;\n parameter mode = 0;\n parameter use_adest_arst = 1'b0;\n parameter use_asrc_arst = 1'b0;\n parameter use_bdest_arst = 1'b0;\n parameter use_bsrc_arst = 1'b0;\n parameter use_cdest_arst = 1'b0;\n parameter use_csrc_arst = 1'b0;\n parameter use_ddest_arst = 1'b0;\n parameter use_dsrc_arst = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21\n, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18\n, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21\n, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6\n, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3\n, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24\n, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3\n, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57\n, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20\n, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41\n, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6\n, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27\n, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48\n, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13\n, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11\n, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32\n, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53\n, Z54, Z55, Z56);\n input A1;\n input A10;\n input A11;\n input A12;\n input A13;\n input A14;\n input A15;\n input A16;\n input A17;\n input A18;\n input A19;\n input A2;\n input A20;\n input A21;\n input A22;\n input A23;\n input A24;\n input A3;\n input A4;\n input A5;\n input A6;\n input A7;\n input A8;\n input A9;\n input B1;\n input B10;\n input B11;\n input B12;\n input B13;\n input B14;\n input B15;\n input B16;\n input B17;\n input B18;\n input B2;\n input B3;\n input B4;\n input B5;\n input B6;\n input B7;\n input B8;\n input B9;\n input C1;\n input C10;\n input C11;\n input C12;\n input C13;\n input C14;\n input C15;\n input C16;\n input C17;\n input C18;\n input C19;\n input C2;\n input C20;\n input C21;\n input C22;\n input C23;\n input C24;\n input C25;\n input C26;\n input C27;\n input C28;\n input C29;\n input C3;\n input C30;\n input C31;\n input C32;\n input C33;\n input C34;\n input C35;\n input C36;\n input C4;\n input C5;\n input C6;\n input C7;\n input C8;\n input C9;\n input CAI1;\n input CAI10;\n input CAI11;\n input CAI12;\n input CAI13;\n input CAI14;\n input CAI15;\n input CAI16;\n input CAI17;\n input CAI18;\n input CAI19;\n input CAI2;\n input CAI20;\n input CAI21;\n input CAI22;\n input CAI23;\n input CAI24;\n input CAI3;\n input CAI4;\n input CAI5;\n input CAI6;\n input CAI7;\n input CAI8;\n input CAI9;\n output CAO1;\n output CAO10;\n output CAO11;\n output CAO12;\n output CAO13;\n output CAO14;\n output CAO15;\n output CAO16;\n output CAO17;\n output CAO18;\n output CAO19;\n output CAO2;\n output CAO20;\n output CAO21;\n output CAO22;\n output CAO23;\n output CAO24;\n output CAO3;\n output CAO4;\n output CAO5;\n output CAO6;\n output CAO7;\n output CAO8;\n output CAO9;\n input CBI1;\n input CBI10;\n input CBI11;\n input CBI12;\n input CBI13;\n input CBI14;\n input CBI15;\n input CBI16;\n input CBI17;\n input CBI18;\n input CBI2;\n input CBI3;\n input CBI4;\n input CBI5;\n input CBI6;\n input CBI7;\n input CBI8;\n input CBI9;\n output CBO1;\n output CBO10;\n output CBO11;\n output CBO12;\n output CBO13;\n output CBO14;\n output CBO15;\n output CBO16;\n output CBO17;\n output CBO18;\n output CBO2;\n output CBO3;\n output CBO4;\n output CBO5;\n output CBO6;\n output CBO7;\n output CBO8;\n output CBO9;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO43;\n output CO57;\n input CZI1;\n input CZI10;\n input CZI11;\n input CZI12;\n input CZI13;\n input CZI14;\n input CZI15;\n input CZI16;\n input CZI17;\n input CZI18;\n input CZI19;\n input CZI2;\n input CZI20;\n input CZI21;\n input CZI22;\n input CZI23;\n input CZI24;\n input CZI25;\n input CZI26;\n input CZI27;\n input CZI28;\n input CZI29;\n input CZI3;\n input CZI30;\n input CZI31;\n input CZI32;\n input CZI33;\n input CZI34;\n input CZI35;\n input CZI36;\n input CZI37;\n input CZI38;\n input CZI39;\n input CZI4;\n input CZI40;\n input CZI41;\n input CZI42;\n input CZI43;\n input CZI44;\n input CZI45;\n input CZI46;\n input CZI47;\n input CZI48;\n input CZI49;\n input CZI5;\n input CZI50;\n input CZI51;\n input CZI52;\n input CZI53;\n input CZI54;\n input CZI55;\n input CZI56;\n input CZI6;\n input CZI7;\n input CZI8;\n input CZI9;\n output CZO1;\n output CZO10;\n output CZO11;\n output CZO12;\n output CZO13;\n output CZO14;\n output CZO15;\n output CZO16;\n output CZO17;\n output CZO18;\n output CZO19;\n output CZO2;\n output CZO20;\n output CZO21;\n output CZO22;\n output CZO23;\n output CZO24;\n output CZO25;\n output CZO26;\n output CZO27;\n output CZO28;\n output CZO29;\n output CZO3;\n output CZO30;\n output CZO31;\n output CZO32;\n output CZO33;\n output CZO34;\n output CZO35;\n output CZO36;\n output CZO37;\n output CZO38;\n output CZO39;\n output CZO4;\n output CZO40;\n output CZO41;\n output CZO42;\n output CZO43;\n output CZO44;\n output CZO45;\n output CZO46;\n output CZO47;\n output CZO48;\n output CZO49;\n output CZO5;\n output CZO50;\n output CZO51;\n output CZO52;\n output CZO53;\n output CZO54;\n output CZO55;\n output CZO56;\n output CZO6;\n output CZO7;\n output CZO8;\n output CZO9;\n input D1;\n input D10;\n input D11;\n input D12;\n input D13;\n input D14;\n input D15;\n input D16;\n input D17;\n input D18;\n input D2;\n input D3;\n input D4;\n input D5;\n input D6;\n input D7;\n input D8;\n input D9;\n output OVF;\n input R;\n output RESERVED;\n input RZ;\n input WE;\n input WEZ;\n output Z1;\n output Z10;\n output Z11;\n output Z12;\n output Z13;\n output Z14;\n output Z15;\n output Z16;\n output Z17;\n output Z18;\n output Z19;\n output Z2;\n output Z20;\n output Z21;\n output Z22;\n output Z23;\n output Z24;\n output Z25;\n output Z26;\n output Z27;\n output Z28;\n output Z29;\n output Z3;\n output Z30;\n output Z31;\n output Z32;\n output Z33;\n output Z34;\n output Z35;\n output Z36;\n output Z37;\n output Z38;\n output Z39;\n output Z4;\n output Z40;\n output Z41;\n output Z42;\n output Z43;\n output Z44;\n output Z45;\n output Z46;\n output Z47;\n output Z48;\n output Z49;\n output Z5;\n output Z50;\n output Z51;\n output Z52;\n output Z53;\n output Z54;\n output Z55;\n output Z56;\n output Z6;\n output Z7;\n output Z8;\n output Z9;\n parameter raw_config0 = 27'b000000000000000000000000000;\n parameter raw_config1 = 24'b000000000000000000000000;\n parameter raw_config2 = 14'b00000000000000;\n parameter raw_config3 = 3'b000;\n parameter std_mode = \"\";\nendmodule\n\n(* blackbox *)\nmodule NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV\n, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);\n input ARST_CAL;\n output CAL1;\n output CAL2;\n output CAL3;\n output CAL4;\n output CAL5;\n output CAL_LOCKED;\n input CLK_CAL;\n output CLK_CAL_DIV;\n output CLK_DIV1;\n output CLK_DIV2;\n output CLK_DIV3;\n output CLK_DIV4;\n output CLK_DIVD1;\n output CLK_DIVD2;\n output CLK_DIVD3;\n output CLK_DIVD4;\n output CLK_DIVD5;\n input EXT_CAL1;\n input EXT_CAL2;\n input EXT_CAL3;\n input EXT_CAL4;\n input EXT_CAL5;\n input EXT_CAL_LOCKED;\n input FBK;\n output LDFO;\n output OSC;\n output PLL_LOCKED;\n output PLL_LOCKEDA;\n input R;\n input REF;\n output REFO;\n output VCO;\n parameter cal_delay = 6'b011011;\n parameter cal_div = 4'b0111;\n parameter clk_cal_sel = 2'b01;\n parameter clk_outdiv1 = 3'b000;\n parameter clk_outdiv2 = 3'b000;\n parameter clk_outdiv3 = 3'b000;\n parameter clk_outdiv4 = 3'b000;\n parameter clk_outdivd1 = 4'b0000;\n parameter clk_outdivd2 = 4'b0000;\n parameter clk_outdivd3 = 4'b0000;\n parameter clk_outdivd4 = 4'b0000;\n parameter clk_outdivd5 = 4'b0000;\n parameter ext_fbk_on = 1'b0;\n parameter fbk_delay = 6'b000000;\n parameter fbk_delay_on = 1'b0;\n parameter fbk_intdiv = 7'b0000000;\n parameter location = \"\";\n parameter pll_cpump = 4'b0000;\n parameter pll_lock = 4'b0000;\n parameter pll_lpf_cap = 4'b0000;\n parameter pll_lpf_res = 4'b0000;\n parameter pll_odf = 2'b00;\n parameter ref_intdiv = 5'b00000;\n parameter ref_osc_on = 1'b0;\n parameter use_cal = 1'b0;\n parameter use_pll = 1'b1;\nendmodule\n\n(* blackbox *)\nmodule NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6\n, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27\n, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48\n, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5\n, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2\n, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7\n, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK);\n input ALIGN_E_I;\n output ALIGN_O;\n input ALIGN_S_I;\n input BUF_R_I;\n output BUSY_O;\n output CH_A_O1;\n output CH_A_O2;\n output CH_A_O3;\n output CH_A_O4;\n output CH_A_O5;\n output CH_A_O6;\n output CH_A_O7;\n output CH_A_O8;\n output CH_COM_O1;\n output CH_COM_O2;\n output CH_COM_O3;\n output CH_COM_O4;\n output CH_COM_O5;\n output CH_COM_O6;\n output CH_COM_O7;\n output CH_COM_O8;\n output CH_F_O1;\n output CH_F_O2;\n output CH_F_O3;\n output CH_F_O4;\n output CH_F_O5;\n output CH_F_O6;\n output CH_F_O7;\n output CH_F_O8;\n output CH_K_O1;\n output CH_K_O2;\n output CH_K_O3;\n output CH_K_O4;\n output CH_K_O5;\n output CH_K_O6;\n output CH_K_O7;\n output CH_K_O8;\n output DATA_O1;\n output DATA_O10;\n output DATA_O11;\n output DATA_O12;\n output DATA_O13;\n output DATA_O14;\n output DATA_O15;\n output DATA_O16;\n output DATA_O17;\n output DATA_O18;\n output DATA_O19;\n output DATA_O2;\n output DATA_O20;\n output DATA_O21;\n output DATA_O22;\n output DATA_O23;\n output DATA_O24;\n output DATA_O25;\n output DATA_O26;\n output DATA_O27;\n output DATA_O28;\n output DATA_O29;\n output DATA_O3;\n output DATA_O30;\n output DATA_O31;\n output DATA_O32;\n output DATA_O33;\n output DATA_O34;\n output DATA_O35;\n output DATA_O36;\n output DATA_O37;\n output DATA_O38;\n output DATA_O39;\n output DATA_O4;\n output DATA_O40;\n output DATA_O41;\n output DATA_O42;\n output DATA_O43;\n output DATA_O44;\n output DATA_O45;\n output DATA_O46;\n output DATA_O47;\n output DATA_O48;\n output DATA_O49;\n output DATA_O5;\n output DATA_O50;\n output DATA_O51;\n output DATA_O52;\n output DATA_O53;\n output DATA_O54;\n output DATA_O55;\n output DATA_O56;\n output DATA_O57;\n output DATA_O58;\n output DATA_O59;\n output DATA_O6;\n output DATA_O60;\n output DATA_O61;\n output DATA_O62;\n output DATA_O63;\n output DATA_O64;\n output DATA_O7;\n output DATA_O8;\n output DATA_O9;\n input DBG_S_I1;\n input DBG_S_I2;\n input DBG_S_I3;\n input DEC_E_I;\n input DSCR_E_I;\n output D_ERR_O1;\n output D_ERR_O2;\n output D_ERR_O3;\n output D_ERR_O4;\n output D_ERR_O5;\n output D_ERR_O6;\n output D_ERR_O7;\n output D_ERR_O8;\n inout [9:0] LINK;\n output LL_FLOCK_O;\n output LL_SLOCK_O;\n output LOS_O;\n input MEYE_RST_I;\n output NIT_O1;\n output NIT_O2;\n output NIT_O3;\n output NIT_O4;\n output NIT_O5;\n output NIT_O6;\n output NIT_O7;\n output NIT_O8;\n input OVS_BS_I1;\n input OVS_BS_I2;\n output PLL_LOCKT_O;\n output PLL_LOCK_O;\n input PMA_RSTN_I;\n input PWDN_N_I;\n input REP_E_I;\n input RST_N_I;\n output TST_O1;\n output TST_O2;\n output TST_O3;\n output TST_O4;\n output TST_O5;\n output TST_O6;\n output TST_O7;\n output TST_O8;\n output VREALIGN_O;\n parameter gearbox_en = 1'b0;\n parameter gearbox_mode = 1'b0;\n parameter location = \"\";\n parameter pcs_8b_dscr_sel = 1'b0;\n parameter pcs_align_bypass = 1'b0;\n parameter pcs_buffers_bypass = 1'b0;\n parameter pcs_buffers_use_cdc = 1'b0;\n parameter pcs_bypass_pma_cdc = 1'b0;\n parameter pcs_bypass_usr_cdc = 1'b0;\n parameter pcs_comma_mask = 10'b0000000000;\n parameter pcs_debug_en = 1'b0;\n parameter pcs_dec_bypass = 1'b0;\n parameter pcs_dscr_bypass = 1'b0;\n parameter pcs_el_buff_diff_bef_comp = 4'b0000;\n parameter pcs_el_buff_max_comp = 4'b0000;\n parameter pcs_el_buff_only_one_skp = 1'b0;\n parameter pcs_el_buff_skp_char_0 = 9'b000000000;\n parameter pcs_el_buff_skp_char_1 = 9'b000000000;\n parameter pcs_el_buff_skp_char_2 = 9'b000000000;\n parameter pcs_el_buff_skp_char_3 = 9'b000000000;\n parameter pcs_el_buff_skp_header_0 = 9'b000000000;\n parameter pcs_el_buff_skp_header_1 = 9'b000000000;\n parameter pcs_el_buff_skp_header_2 = 9'b000000000;\n parameter pcs_el_buff_skp_header_3 = 9'b000000000;\n parameter pcs_el_buff_skp_header_size = 2'b00;\n parameter pcs_el_buff_skp_seq_size = 2'b00;\n parameter pcs_fsm_sel = 2'b00;\n parameter pcs_fsm_watchdog_en = 1'b0;\n parameter pcs_loopback = 1'b0;\n parameter pcs_m_comma_en = 1'b0;\n parameter pcs_m_comma_val = 10'b0000000000;\n parameter pcs_nb_comma_bef_realign = 2'b00;\n parameter pcs_p_comma_en = 1'b0;\n parameter pcs_p_comma_val = 10'b0000000000;\n parameter pcs_polarity = 1'b0;\n parameter pcs_protocol_size = 1'b0;\n parameter pcs_replace_bypass = 1'b0;\n parameter pcs_sync_supported = 1'b0;\n parameter pma_cdr_cp = 4'b0000;\n parameter pma_clk_pos = 1'b0;\n parameter pma_coarse_ppm = 3'b000;\n parameter pma_ctrl_term = 6'b000000;\n parameter pma_dco_divl = 2'b00;\n parameter pma_dco_divm = 1'b0;\n parameter pma_dco_divn = 2'b00;\n parameter pma_dco_reg_res = 2'b00;\n parameter pma_dco_vref_sel = 1'b0;\n parameter pma_fine_ppm = 3'b000;\n parameter pma_loopback = 1'b0;\n parameter pma_m_eye_ppm = 3'b000;\n parameter pma_peak_detect_cmd = 2'b00;\n parameter pma_peak_detect_on = 1'b0;\n parameter pma_pll_cpump_n = 3'b000;\n parameter pma_pll_divf = 2'b00;\n parameter pma_pll_divf_en_n = 1'b0;\n parameter pma_pll_divm = 2'b00;\n parameter pma_pll_divm_en_n = 1'b0;\n parameter pma_pll_divn = 1'b0;\n parameter pma_pll_divn_en_n = 1'b0;\nendmodule\n\n\n(* blackbox *)\nmodule NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5\n, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I\n, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21\n, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42\n, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63\n, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK);\n output BUSY_O;\n input CH_K_I1;\n input CH_K_I2;\n input CH_K_I3;\n input CH_K_I4;\n input CH_K_I5;\n input CH_K_I6;\n input CH_K_I7;\n input CH_K_I8;\n input CLK_E_I;\n output CLK_O;\n input DATA_I1;\n input DATA_I10;\n input DATA_I11;\n input DATA_I12;\n input DATA_I13;\n input DATA_I14;\n input DATA_I15;\n input DATA_I16;\n input DATA_I17;\n input DATA_I18;\n input DATA_I19;\n input DATA_I2;\n input DATA_I20;\n input DATA_I21;\n input DATA_I22;\n input DATA_I23;\n input DATA_I24;\n input DATA_I25;\n input DATA_I26;\n input DATA_I27;\n input DATA_I28;\n input DATA_I29;\n input DATA_I3;\n input DATA_I30;\n input DATA_I31;\n input DATA_I32;\n input DATA_I33;\n input DATA_I34;\n input DATA_I35;\n input DATA_I36;\n input DATA_I37;\n input DATA_I38;\n input DATA_I39;\n input DATA_I4;\n input DATA_I40;\n input DATA_I41;\n input DATA_I42;\n input DATA_I43;\n input DATA_I44;\n input DATA_I45;\n input DATA_I46;\n input DATA_I47;\n input DATA_I48;\n input DATA_I49;\n input DATA_I5;\n input DATA_I50;\n input DATA_I51;\n input DATA_I52;\n input DATA_I53;\n input DATA_I54;\n input DATA_I55;\n input DATA_I56;\n input DATA_I57;\n input DATA_I58;\n input DATA_I59;\n input DATA_I6;\n input DATA_I60;\n input DATA_I61;\n input DATA_I62;\n input DATA_I63;\n input DATA_I64;\n input DATA_I7;\n input DATA_I8;\n input DATA_I9;\n input ENC_E_I1;\n input ENC_E_I2;\n input ENC_E_I3;\n input ENC_E_I4;\n input ENC_E_I5;\n input ENC_E_I6;\n input ENC_E_I7;\n input ENC_E_I8;\n input EOF_I1;\n input EOF_I2;\n input EOF_I3;\n input EOF_I4;\n input EOF_I5;\n input EOF_I6;\n input EOF_I7;\n input EOF_I8;\n input EOMF_I1;\n input EOMF_I2;\n input EOMF_I3;\n input EOMF_I4;\n input EOMF_I5;\n input EOMF_I6;\n input EOMF_I7;\n input EOMF_I8;\n output INV_K_O;\n inout [19:0] LINK;\n input PWDN_N_I;\n input REP_E_I;\n input RST_N_I;\n input SCR_E_I1;\n input SCR_E_I2;\n input SCR_E_I3;\n input SCR_E_I4;\n input SCR_E_I5;\n input SCR_E_I6;\n input SCR_E_I7;\n input SCR_E_I8;\n parameter gearbox_en = 1'b0;\n parameter gearbox_mode = 1'b0;\n parameter location = \"\";\n parameter pcs_8b_scr_sel = 1'b0;\n parameter pcs_bypass_pma_cdc = 1'b0;\n parameter pcs_bypass_usr_cdc = 1'b0;\n parameter pcs_enc_bypass = 1'b0;\n parameter pcs_esistream_fsm_en = 1'b0;\n parameter pcs_loopback = 1'b0;\n parameter pcs_polarity = 1'b0;\n parameter pcs_protocol_size = 1'b0;\n parameter pcs_replace_bypass = 1'b0;\n parameter pcs_scr_bypass = 1'b0;\n parameter pcs_scr_init = 17'b00000000000000000;\n parameter pcs_sync_supported = 1'b0;\n parameter pma_clk_pos = 1'b0;\n parameter pma_loopback = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1\n, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6\n, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN\n, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN\n, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1\n, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6\n, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4\n, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL\n, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6\n, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI\n, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6\n, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL\n, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6\n, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI\n, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6\n, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL\n, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6\n, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI\n, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6\n, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL\n, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6\n, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI\n, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6\n, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL\n, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6\n, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI\n, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6\n, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL\n, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6\n, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI\n, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6\n, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL\n, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6\n, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI\n, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6\n, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL\n, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6\n, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI\n, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6\n, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL\n, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6\n, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI\n, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6\n, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL\n, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6\n, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI\n, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6\n, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL\n, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6\n, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI\n, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6\n, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL\n, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8);\n output AL1D;\n output AL1T;\n output AL2D;\n output AL2T;\n output AL3D;\n output AL3T;\n input ALCK1;\n input ALCK2;\n input ALCK3;\n input CA1D1;\n input CA1D2;\n input CA1D3;\n input CA1D4;\n input CA1D5;\n input CA1D6;\n input CA1N1;\n input CA1N2;\n input CA1N3;\n input CA1N4;\n input CA1P1;\n input CA1P2;\n input CA1P3;\n input CA1P4;\n input CA1T1;\n input CA1T2;\n input CA1T3;\n input CA1T4;\n input CA2D1;\n input CA2D2;\n input CA2D3;\n input CA2D4;\n input CA2D5;\n input CA2D6;\n input CA2N1;\n input CA2N2;\n input CA2N3;\n input CA2N4;\n input CA2P1;\n input CA2P2;\n input CA2P3;\n input CA2P4;\n input CA2T1;\n input CA2T2;\n input CA2T3;\n input CA2T4;\n input CCK;\n output CKO1;\n output CKO2;\n output DCL;\n input DCRN;\n input DQ1CI1;\n input DQ1CI2;\n input DQ1CI3;\n input DQ1CI4;\n input DQ1CI5;\n input DQ1CI6;\n input DQ1CI7;\n input DQ1CI8;\n input DQ2CI1;\n input DQ2CI2;\n input DQ2CI3;\n input DQ2CI4;\n input DQ2CI5;\n input DQ2CI6;\n input DQ2CI7;\n input DQ2CI8;\n input DQ3CI1;\n input DQ3CI2;\n input DQ3CI3;\n input DQ3CI4;\n input DQ3CI5;\n input DQ3CI6;\n input DQ3CI7;\n input DQ3CI8;\n input DQS1CI1;\n input DQS1CI2;\n input DQS1CI3;\n input DQS1CI4;\n input DQS1CI5;\n input DQS1CI6;\n input DQS1CI7;\n input DQS1CI8;\n input DQS2CI1;\n input DQS2CI2;\n input DQS2CI3;\n input DQS2CI4;\n input DQS2CI5;\n input DQS2CI6;\n input DQS2CI7;\n input DQS2CI8;\n input DQS3CI1;\n input DQS3CI2;\n input DQS3CI3;\n input DQS3CI4;\n input DQS3CI5;\n input DQS3CI6;\n input DQS3CI7;\n input DQS3CI8;\n input DRA1;\n input DRA2;\n input DRA3;\n input DRA4;\n input DRCCSN;\n input DRDPA1CSN;\n input DRDPA2CSN;\n input DRDPA3CSN;\n input DRE;\n input DRI1;\n input DRI1CSN;\n input DRI2;\n input DRI2CSN;\n input DRI3;\n input DRI3CSN;\n input DRI4;\n input DRI5;\n input DRI6;\n output DRO1;\n input DRO1CSN;\n output DRO2;\n input DRO2CSN;\n output DRO3;\n input DRO3CSN;\n output DRO4;\n output DRO5;\n output DRO6;\n input DRWDS;\n input DRWEN;\n input FA1;\n input FA2;\n input FA3;\n input FA4;\n input FA5;\n input FA6;\n input FCK1;\n input FCK2;\n input FDCK;\n output FLD;\n output FLG;\n input FZ;\n input LD1RN;\n input LD2RN;\n input LD3RN;\n input LDSCK1;\n input LDSCK2;\n input LDSCK3;\n input LE;\n input P10CI1;\n input P10CL;\n output P10CO;\n input P10CR;\n input P10CTI;\n output P10CTO;\n input P10EI1;\n input P10EI2;\n input P10EI3;\n input P10EI4;\n input P10EI5;\n input P10EI6;\n input P10EI7;\n input P10EI8;\n input P10EL;\n output P10EO;\n input P10ER;\n input P10RI;\n input P10RL;\n output P10RO1;\n output P10RO2;\n output P10RO3;\n output P10RO4;\n output P10RO5;\n output P10RO6;\n output P10RO7;\n output P10RO8;\n input P10RR;\n input P11CI1;\n input P11CL;\n output P11CO;\n input P11CR;\n input P11CTI;\n output P11CTO;\n input P11EI1;\n input P11EI2;\n input P11EI3;\n input P11EI4;\n input P11EI5;\n input P11EI6;\n input P11EI7;\n input P11EI8;\n input P11EL;\n output P11EO;\n input P11ER;\n input P11RI;\n input P11RL;\n output P11RO1;\n output P11RO2;\n output P11RO3;\n output P11RO4;\n output P11RO5;\n output P11RO6;\n output P11RO7;\n output P11RO8;\n input P11RR;\n input P12CI1;\n input P12CL;\n output P12CO;\n input P12CR;\n input P12CTI;\n output P12CTO;\n input P12EI1;\n input P12EI2;\n input P12EI3;\n input P12EI4;\n input P12EI5;\n input P12EI6;\n input P12EI7;\n input P12EI8;\n input P12EL;\n output P12EO;\n input P12ER;\n input P12RI;\n input P12RL;\n output P12RO1;\n output P12RO2;\n output P12RO3;\n output P12RO4;\n output P12RO5;\n output P12RO6;\n output P12RO7;\n output P12RO8;\n input P12RR;\n input P13CI1;\n input P13CL;\n output P13CO;\n input P13CR;\n input P13CTI;\n output P13CTO;\n input P13EI1;\n input P13EI2;\n input P13EI3;\n input P13EI4;\n input P13EI5;\n input P13EI6;\n input P13EI7;\n input P13EI8;\n input P13EL;\n output P13EO;\n input P13ER;\n input P13RI;\n input P13RL;\n output P13RO1;\n output P13RO2;\n output P13RO3;\n output P13RO4;\n output P13RO5;\n output P13RO6;\n output P13RO7;\n output P13RO8;\n input P13RR;\n input P14CI1;\n input P14CL;\n output P14CO;\n input P14CR;\n input P14CTI;\n output P14CTO;\n input P14EI1;\n input P14EI2;\n input P14EI3;\n input P14EI4;\n input P14EI5;\n input P14EI6;\n input P14EI7;\n input P14EI8;\n input P14EL;\n output P14EO;\n input P14ER;\n input P14RI;\n input P14RL;\n output P14RO1;\n output P14RO2;\n output P14RO3;\n output P14RO4;\n output P14RO5;\n output P14RO6;\n output P14RO7;\n output P14RO8;\n input P14RR;\n input P15CI1;\n input P15CL;\n output P15CO;\n input P15CR;\n input P15CTI;\n output P15CTO;\n input P15EI1;\n input P15EI2;\n input P15EI3;\n input P15EI4;\n input P15EI5;\n input P15EI6;\n input P15EI7;\n input P15EI8;\n input P15EL;\n output P15EO;\n input P15ER;\n input P15RI;\n input P15RL;\n output P15RO1;\n output P15RO2;\n output P15RO3;\n output P15RO4;\n output P15RO5;\n output P15RO6;\n output P15RO7;\n output P15RO8;\n input P15RR;\n input P16CI1;\n input P16CL;\n output P16CO;\n input P16CR;\n input P16CTI;\n output P16CTO;\n input P16EI1;\n input P16EI2;\n input P16EI3;\n input P16EI4;\n input P16EI5;\n input P16EI6;\n input P16EI7;\n input P16EI8;\n input P16EL;\n output P16EO;\n input P16ER;\n input P16RI;\n input P16RL;\n output P16RO1;\n output P16RO2;\n output P16RO3;\n output P16RO4;\n output P16RO5;\n output P16RO6;\n output P16RO7;\n output P16RO8;\n input P16RR;\n input P17CI1;\n input P17CL;\n output P17CO;\n input P17CR;\n input P17CTI;\n output P17CTO;\n input P17EI1;\n input P17EI2;\n input P17EI3;\n input P17EI4;\n input P17EI5;\n input P17EI6;\n input P17EI7;\n input P17EI8;\n input P17EL;\n output P17EO;\n input P17ER;\n input P17RI;\n input P17RL;\n output P17RO1;\n output P17RO2;\n output P17RO3;\n output P17RO4;\n output P17RO5;\n output P17RO6;\n output P17RO7;\n output P17RO8;\n input P17RR;\n input P18CI1;\n input P18CL;\n output P18CO;\n input P18CR;\n input P18CTI;\n output P18CTO;\n input P18EI1;\n input P18EI2;\n input P18EI3;\n input P18EI4;\n input P18EI5;\n input P18EI6;\n input P18EI7;\n input P18EI8;\n input P18EL;\n output P18EO;\n input P18ER;\n input P18RI;\n input P18RL;\n output P18RO1;\n output P18RO2;\n output P18RO3;\n output P18RO4;\n output P18RO5;\n output P18RO6;\n output P18RO7;\n output P18RO8;\n input P18RR;\n input P19CI1;\n input P19CL;\n output P19CO;\n input P19CR;\n input P19CTI;\n output P19CTO;\n input P19EI1;\n input P19EI2;\n input P19EI3;\n input P19EI4;\n input P19EI5;\n input P19EI6;\n input P19EI7;\n input P19EI8;\n input P19EL;\n output P19EO;\n input P19ER;\n input P19RI;\n input P19RL;\n output P19RO1;\n output P19RO2;\n output P19RO3;\n output P19RO4;\n output P19RO5;\n output P19RO6;\n output P19RO7;\n output P19RO8;\n input P19RR;\n input P1CI1;\n input P1CL;\n output P1CO;\n input P1CR;\n input P1CTI;\n output P1CTO;\n input P1EI1;\n input P1EI2;\n input P1EI3;\n input P1EI4;\n input P1EI5;\n input P1EI6;\n input P1EI7;\n input P1EI8;\n input P1EL;\n output P1EO;\n input P1ER;\n input P1RI;\n input P1RL;\n output P1RO1;\n output P1RO2;\n output P1RO3;\n output P1RO4;\n output P1RO5;\n output P1RO6;\n output P1RO7;\n output P1RO8;\n input P1RR;\n input P20CI1;\n input P20CL;\n output P20CO;\n input P20CR;\n input P20CTI;\n output P20CTO;\n input P20EI1;\n input P20EI2;\n input P20EI3;\n input P20EI4;\n input P20EI5;\n input P20EI6;\n input P20EI7;\n input P20EI8;\n input P20EL;\n output P20EO;\n input P20ER;\n input P20RI;\n input P20RL;\n output P20RO1;\n output P20RO2;\n output P20RO3;\n output P20RO4;\n output P20RO5;\n output P20RO6;\n output P20RO7;\n output P20RO8;\n input P20RR;\n input P21CI1;\n input P21CL;\n output P21CO;\n input P21CR;\n input P21CTI;\n output P21CTO;\n input P21EI1;\n input P21EI2;\n input P21EI3;\n input P21EI4;\n input P21EI5;\n input P21EI6;\n input P21EI7;\n input P21EI8;\n input P21EL;\n output P21EO;\n input P21ER;\n input P21RI;\n input P21RL;\n output P21RO1;\n output P21RO2;\n output P21RO3;\n output P21RO4;\n output P21RO5;\n output P21RO6;\n output P21RO7;\n output P21RO8;\n input P21RR;\n input P22CI1;\n input P22CL;\n output P22CO;\n input P22CR;\n input P22CTI;\n output P22CTO;\n input P22EI1;\n input P22EI2;\n input P22EI3;\n input P22EI4;\n input P22EI5;\n input P22EI6;\n input P22EI7;\n input P22EI8;\n input P22EL;\n output P22EO;\n input P22ER;\n input P22RI;\n input P22RL;\n output P22RO1;\n output P22RO2;\n output P22RO3;\n output P22RO4;\n output P22RO5;\n output P22RO6;\n output P22RO7;\n output P22RO8;\n input P22RR;\n input P23CI1;\n input P23CL;\n output P23CO;\n input P23CR;\n input P23CTI;\n output P23CTO;\n input P23EI1;\n input P23EI2;\n input P23EI3;\n input P23EI4;\n input P23EI5;\n input P23EI6;\n input P23EI7;\n input P23EI8;\n input P23EL;\n output P23EO;\n input P23ER;\n input P23RI;\n input P23RL;\n output P23RO1;\n output P23RO2;\n output P23RO3;\n output P23RO4;\n output P23RO5;\n output P23RO6;\n output P23RO7;\n output P23RO8;\n input P23RR;\n input P24CI1;\n input P24CL;\n output P24CO;\n input P24CR;\n input P24CTI;\n output P24CTO;\n input P24EI1;\n input P24EI2;\n input P24EI3;\n input P24EI4;\n input P24EI5;\n input P24EI6;\n input P24EI7;\n input P24EI8;\n input P24EL;\n output P24EO;\n input P24ER;\n input P24RI;\n input P24RL;\n output P24RO1;\n output P24RO2;\n output P24RO3;\n output P24RO4;\n output P24RO5;\n output P24RO6;\n output P24RO7;\n output P24RO8;\n input P24RR;\n input P25CI1;\n input P25CL;\n output P25CO;\n input P25CR;\n input P25CTI;\n output P25CTO;\n input P25EI1;\n input P25EI2;\n input P25EI3;\n input P25EI4;\n input P25EI5;\n input P25EI6;\n input P25EI7;\n input P25EI8;\n input P25EL;\n output P25EO;\n input P25ER;\n input P25RI;\n input P25RL;\n output P25RO1;\n output P25RO2;\n output P25RO3;\n output P25RO4;\n output P25RO5;\n output P25RO6;\n output P25RO7;\n output P25RO8;\n input P25RR;\n input P26CI1;\n input P26CL;\n output P26CO;\n input P26CR;\n input P26CTI;\n output P26CTO;\n input P26EI1;\n input P26EI2;\n input P26EI3;\n input P26EI4;\n input P26EI5;\n input P26EI6;\n input P26EI7;\n input P26EI8;\n input P26EL;\n output P26EO;\n input P26ER;\n input P26RI;\n input P26RL;\n output P26RO1;\n output P26RO2;\n output P26RO3;\n output P26RO4;\n output P26RO5;\n output P26RO6;\n output P26RO7;\n output P26RO8;\n input P26RR;\n input P27CI1;\n input P27CL;\n output P27CO;\n input P27CR;\n input P27CTI;\n output P27CTO;\n input P27EI1;\n input P27EI2;\n input P27EI3;\n input P27EI4;\n input P27EI5;\n input P27EI6;\n input P27EI7;\n input P27EI8;\n input P27EL;\n output P27EO;\n input P27ER;\n input P27RI;\n input P27RL;\n output P27RO1;\n output P27RO2;\n output P27RO3;\n output P27RO4;\n output P27RO5;\n output P27RO6;\n output P27RO7;\n output P27RO8;\n input P27RR;\n input P28CI1;\n input P28CL;\n output P28CO;\n input P28CR;\n input P28CTI;\n output P28CTO;\n input P28EI1;\n input P28EI2;\n input P28EI3;\n input P28EI4;\n input P28EI5;\n input P28EI6;\n input P28EI7;\n input P28EI8;\n input P28EL;\n output P28EO;\n input P28ER;\n input P28RI;\n input P28RL;\n output P28RO1;\n output P28RO2;\n output P28RO3;\n output P28RO4;\n output P28RO5;\n output P28RO6;\n output P28RO7;\n output P28RO8;\n input P28RR;\n input P29CI1;\n input P29CL;\n output P29CO;\n input P29CR;\n input P29CTI;\n output P29CTO;\n input P29EI1;\n input P29EI2;\n input P29EI3;\n input P29EI4;\n input P29EI5;\n input P29EI6;\n input P29EI7;\n input P29EI8;\n input P29EL;\n output P29EO;\n input P29ER;\n input P29RI;\n input P29RL;\n output P29RO1;\n output P29RO2;\n output P29RO3;\n output P29RO4;\n output P29RO5;\n output P29RO6;\n output P29RO7;\n output P29RO8;\n input P29RR;\n input P2CI1;\n input P2CL;\n output P2CO;\n input P2CR;\n input P2CTI;\n output P2CTO;\n input P2EI1;\n input P2EI2;\n input P2EI3;\n input P2EI4;\n input P2EI5;\n input P2EI6;\n input P2EI7;\n input P2EI8;\n input P2EL;\n output P2EO;\n input P2ER;\n input P2RI;\n input P2RL;\n output P2RO1;\n output P2RO2;\n output P2RO3;\n output P2RO4;\n output P2RO5;\n output P2RO6;\n output P2RO7;\n output P2RO8;\n input P2RR;\n input P30CI1;\n input P30CL;\n output P30CO;\n input P30CR;\n input P30CTI;\n output P30CTO;\n input P30EI1;\n input P30EI2;\n input P30EI3;\n input P30EI4;\n input P30EI5;\n input P30EI6;\n input P30EI7;\n input P30EI8;\n input P30EL;\n output P30EO;\n input P30ER;\n input P30RI;\n input P30RL;\n output P30RO1;\n output P30RO2;\n output P30RO3;\n output P30RO4;\n output P30RO5;\n output P30RO6;\n output P30RO7;\n output P30RO8;\n input P30RR;\n input P31CI1;\n input P31CL;\n output P31CO;\n input P31CR;\n input P31CTI;\n output P31CTO;\n input P31EI1;\n input P31EI2;\n input P31EI3;\n input P31EI4;\n input P31EI5;\n input P31EI6;\n input P31EI7;\n input P31EI8;\n input P31EL;\n output P31EO;\n input P31ER;\n input P31RI;\n input P31RL;\n output P31RO1;\n output P31RO2;\n output P31RO3;\n output P31RO4;\n output P31RO5;\n output P31RO6;\n output P31RO7;\n output P31RO8;\n input P31RR;\n input P32CI1;\n input P32CL;\n output P32CO;\n input P32CR;\n input P32CTI;\n output P32CTO;\n input P32EI1;\n input P32EI2;\n input P32EI3;\n input P32EI4;\n input P32EI5;\n input P32EI6;\n input P32EI7;\n input P32EI8;\n input P32EL;\n output P32EO;\n input P32ER;\n input P32RI;\n input P32RL;\n output P32RO1;\n output P32RO2;\n output P32RO3;\n output P32RO4;\n output P32RO5;\n output P32RO6;\n output P32RO7;\n output P32RO8;\n input P32RR;\n input P33CI1;\n input P33CL;\n output P33CO;\n input P33CR;\n input P33CTI;\n output P33CTO;\n input P33EI1;\n input P33EI2;\n input P33EI3;\n input P33EI4;\n input P33EI5;\n input P33EI6;\n input P33EI7;\n input P33EI8;\n input P33EL;\n output P33EO;\n input P33ER;\n input P33RI;\n input P33RL;\n output P33RO1;\n output P33RO2;\n output P33RO3;\n output P33RO4;\n output P33RO5;\n output P33RO6;\n output P33RO7;\n output P33RO8;\n input P33RR;\n input P34CI1;\n input P34CL;\n output P34CO;\n input P34CR;\n input P34CTI;\n output P34CTO;\n input P34EI1;\n input P34EI2;\n input P34EI3;\n input P34EI4;\n input P34EI5;\n input P34EI6;\n input P34EI7;\n input P34EI8;\n input P34EL;\n output P34EO;\n input P34ER;\n input P34RI;\n input P34RL;\n output P34RO1;\n output P34RO2;\n output P34RO3;\n output P34RO4;\n output P34RO5;\n output P34RO6;\n output P34RO7;\n output P34RO8;\n input P34RR;\n input P3CI1;\n input P3CL;\n output P3CO;\n input P3CR;\n input P3CTI;\n output P3CTO;\n input P3EI1;\n input P3EI2;\n input P3EI3;\n input P3EI4;\n input P3EI5;\n input P3EI6;\n input P3EI7;\n input P3EI8;\n input P3EL;\n output P3EO;\n input P3ER;\n input P3RI;\n input P3RL;\n output P3RO1;\n output P3RO2;\n output P3RO3;\n output P3RO4;\n output P3RO5;\n output P3RO6;\n output P3RO7;\n output P3RO8;\n input P3RR;\n input P4CI1;\n input P4CL;\n output P4CO;\n input P4CR;\n input P4CTI;\n output P4CTO;\n input P4EI1;\n input P4EI2;\n input P4EI3;\n input P4EI4;\n input P4EI5;\n input P4EI6;\n input P4EI7;\n input P4EI8;\n input P4EL;\n output P4EO;\n input P4ER;\n input P4RI;\n input P4RL;\n output P4RO1;\n output P4RO2;\n output P4RO3;\n output P4RO4;\n output P4RO5;\n output P4RO6;\n output P4RO7;\n output P4RO8;\n input P4RR;\n input P5CI1;\n input P5CL;\n output P5CO;\n input P5CR;\n input P5CTI;\n output P5CTO;\n input P5EI1;\n input P5EI2;\n input P5EI3;\n input P5EI4;\n input P5EI5;\n input P5EI6;\n input P5EI7;\n input P5EI8;\n input P5EL;\n output P5EO;\n input P5ER;\n input P5RI;\n input P5RL;\n output P5RO1;\n output P5RO2;\n output P5RO3;\n output P5RO4;\n output P5RO5;\n output P5RO6;\n output P5RO7;\n output P5RO8;\n input P5RR;\n input P6CI1;\n input P6CL;\n output P6CO;\n input P6CR;\n input P6CTI;\n output P6CTO;\n input P6EI1;\n input P6EI2;\n input P6EI3;\n input P6EI4;\n input P6EI5;\n input P6EI6;\n input P6EI7;\n input P6EI8;\n input P6EL;\n output P6EO;\n input P6ER;\n input P6RI;\n input P6RL;\n output P6RO1;\n output P6RO2;\n output P6RO3;\n output P6RO4;\n output P6RO5;\n output P6RO6;\n output P6RO7;\n output P6RO8;\n input P6RR;\n input P7CI1;\n input P7CL;\n output P7CO;\n input P7CR;\n input P7CTI;\n output P7CTO;\n input P7EI1;\n input P7EI2;\n input P7EI3;\n input P7EI4;\n input P7EI5;\n input P7EI6;\n input P7EI7;\n input P7EI8;\n input P7EL;\n output P7EO;\n input P7ER;\n input P7RI;\n input P7RL;\n output P7RO1;\n output P7RO2;\n output P7RO3;\n output P7RO4;\n output P7RO5;\n output P7RO6;\n output P7RO7;\n output P7RO8;\n input P7RR;\n input P8CI1;\n input P8CL;\n output P8CO;\n input P8CR;\n input P8CTI;\n output P8CTO;\n input P8EI1;\n input P8EI2;\n input P8EI3;\n input P8EI4;\n input P8EI5;\n input P8EI6;\n input P8EI7;\n input P8EI8;\n input P8EL;\n output P8EO;\n input P8ER;\n input P8RI;\n input P8RL;\n output P8RO1;\n output P8RO2;\n output P8RO3;\n output P8RO4;\n output P8RO5;\n output P8RO6;\n output P8RO7;\n output P8RO8;\n input P8RR;\n input P9CI1;\n input P9CL;\n output P9CO;\n input P9CR;\n input P9CTI;\n output P9CTO;\n input P9EI1;\n input P9EI2;\n input P9EI3;\n input P9EI4;\n input P9EI5;\n input P9EI6;\n input P9EI7;\n input P9EI8;\n input P9EL;\n output P9EO;\n input P9ER;\n input P9RI;\n input P9RL;\n output P9RO1;\n output P9RO2;\n output P9RO3;\n output P9RO4;\n output P9RO5;\n output P9RO6;\n output P9RO7;\n output P9RO8;\n input P9RR;\n input SE;\n input SWRX1CK;\n input SWRX2CK;\n parameter cal_delay1 = \"\";\n parameter cal_delay2 = \"\";\n parameter div1 = 3'b000;\n parameter div2 = 3'b000;\n parameter div3 = 3'b000;\n parameter div_swrx1 = 3'b000;\n parameter div_swrx2 = 3'b000;\n parameter inv_ld_sck1 = 1'b0;\n parameter inv_ld_sck2 = 1'b0;\n parameter inv_ld_sck3 = 1'b0;\n parameter link_ld_12 = 1'b0;\n parameter link_ld_23 = 1'b0;\n parameter mode_side1 = 0;\n parameter mode_side2 = 0;\n parameter mode_side3 = 0;\n parameter pads_dict = \"\";\n parameter pads_path = \"\";\n parameter sel_clk_out1 = 1'b0;\n parameter sel_clk_out2 = 1'b0;\n parameter sel_dc_clk = 2'b00;\n parameter sel_ld_fck1 = 2'b00;\n parameter sel_ld_fck2 = 2'b00;\n parameter sel_ld_fck3 = 2'b00;\n parameter sel_sw_fck1 = 2'b00;\n parameter sel_sw_fck2 = 2'b00;\n parameter use_dc = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6\n, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8\n, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14\n, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3\n, LINK_TX0);\n output CAL_OUT_O;\n output CLK_O;\n input CLK_REF_I;\n input CLK_RX_I;\n output CLK_RX_O;\n input CLK_TX_I;\n input DBG_A_I;\n output DBG_R_O;\n input DBG_S_I1;\n input DBG_S_I2;\n input DC_ADD_I1;\n input DC_ADD_I2;\n input DC_ADD_I3;\n input DC_ADD_I4;\n input DC_CCSN_I;\n input DC_E_I;\n input DC_LCSN_I1;\n input DC_LCSN_I2;\n input DC_LCSN_I3;\n input DC_LCSN_I4;\n input DC_WDATAS_I;\n input DC_WDATA_I1;\n input DC_WDATA_I10;\n input DC_WDATA_I11;\n input DC_WDATA_I12;\n input DC_WDATA_I2;\n input DC_WDATA_I3;\n input DC_WDATA_I4;\n input DC_WDATA_I5;\n input DC_WDATA_I6;\n input DC_WDATA_I7;\n input DC_WDATA_I8;\n input DC_WDATA_I9;\n input DC_WE_N_I;\n output FB_LOCK_O;\n inout [9:0] LINK_RX0;\n inout [9:0] LINK_RX1;\n inout [9:0] LINK_RX2;\n inout [9:0] LINK_RX3;\n inout [19:0] LINK_TX0;\n inout [19:0] LINK_TX1;\n inout [19:0] LINK_TX2;\n inout [19:0] LINK_TX3;\n output LL_O1;\n output LL_O10;\n output LL_O11;\n output LL_O12;\n output LL_O13;\n output LL_O14;\n output LL_O15;\n output LL_O16;\n output LL_O17;\n output LL_O18;\n output LL_O19;\n output LL_O2;\n output LL_O20;\n output LL_O3;\n output LL_O4;\n output LL_O5;\n output LL_O6;\n output LL_O7;\n output LL_O8;\n output LL_O9;\n output LOCKA_O;\n output LOCK_O;\n input PLL_RN_I;\n input PWDN_N_I;\n input RST_N_I;\n input SCAN_I1;\n input SCAN_I2;\n input SCAN_I3;\n input SCAN_I4;\n input SCAN_I5;\n input SCAN_I6;\n input SCAN_I7;\n input SCAN_I8;\n output SCAN_O1;\n output SCAN_O2;\n output SCAN_O3;\n output SCAN_O4;\n output SCAN_O5;\n output SCAN_O6;\n output SCAN_O7;\n output SCAN_O8;\n input SE_I;\n parameter dyn_all_rx_pma_m_eye = 1'b0;\n parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0;\n parameter dyn_all_rx_pma_m_eye_dn = 1'b0;\n parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0;\n parameter dyn_all_rx_pma_m_eye_step = 4'b0000;\n parameter dyn_all_rx_pma_m_eye_up = 1'b0;\n parameter dyn_all_rx_pma_threshold_1 = 5'b00000;\n parameter dyn_all_rx_pma_threshold_2 = 5'b00000;\n parameter dyn_all_rx_pma_trim_locked = 3'b000;\n parameter dyn_all_rx_pma_trim_mode = 2'b00;\n parameter dyn_all_rx_pma_trim_unlocked = 3'b000;\n parameter dyn_rx0_pma_ctle_cap_p = 4'b0000;\n parameter dyn_rx0_pma_ctle_res_p = 4'b0000;\n parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000;\n parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000;\n parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000;\n parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000;\n parameter dyn_rx0_pma_termination_cmd = 6'b000000;\n parameter dyn_rx1_pma_ctle_cap_p = 4'b0000;\n parameter dyn_rx1_pma_ctle_res_p = 4'b0000;\n parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000;\n parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000;\n parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000;\n parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000;\n parameter dyn_rx1_pma_termination_cmd = 6'b000000;\n parameter dyn_rx2_pma_ctle_cap_p = 4'b0000;\n parameter dyn_rx2_pma_ctle_res_p = 4'b0000;\n parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000;\n parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000;\n parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000;\n parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000;\n parameter dyn_rx2_pma_termination_cmd = 6'b000000;\n parameter dyn_rx3_pma_ctle_cap_p = 4'b0000;\n parameter dyn_rx3_pma_ctle_res_p = 4'b0000;\n parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000;\n parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000;\n parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000;\n parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000;\n parameter dyn_rx3_pma_termination_cmd = 6'b000000;\n parameter dyn_tx0_pma_main_en = 6'b000000;\n parameter dyn_tx0_pma_main_sign = 1'b0;\n parameter dyn_tx0_pma_margin_input = 9'b000000000;\n parameter dyn_tx0_pma_margin_sel = 9'b000000000;\n parameter dyn_tx0_pma_post_en = 5'b00000;\n parameter dyn_tx0_pma_post_sel = 8'b00000000;\n parameter dyn_tx0_pma_post_sign = 1'b0;\n parameter dyn_tx0_pma_pre_en = 1'b0;\n parameter dyn_tx0_pma_pre_sel = 4'b0000;\n parameter dyn_tx0_pma_pre_sign = 1'b0;\n parameter dyn_tx1_pma_main_en = 6'b000000;\n parameter dyn_tx1_pma_main_sign = 1'b0;\n parameter dyn_tx1_pma_margin_input = 9'b000000000;\n parameter dyn_tx1_pma_margin_sel = 9'b000000000;\n parameter dyn_tx1_pma_post_en = 5'b00000;\n parameter dyn_tx1_pma_post_sel = 8'b00000000;\n parameter dyn_tx1_pma_post_sign = 1'b0;\n parameter dyn_tx1_pma_pre_en = 1'b0;\n parameter dyn_tx1_pma_pre_sel = 4'b0000;\n parameter dyn_tx1_pma_pre_sign = 1'b0;\n parameter dyn_tx2_pma_main_en = 6'b000000;\n parameter dyn_tx2_pma_main_sign = 1'b0;\n parameter dyn_tx2_pma_margin_input = 9'b000000000;\n parameter dyn_tx2_pma_margin_sel = 9'b000000000;\n parameter dyn_tx2_pma_post_en = 5'b00000;\n parameter dyn_tx2_pma_post_sel = 8'b00000000;\n parameter dyn_tx2_pma_post_sign = 1'b0;\n parameter dyn_tx2_pma_pre_en = 1'b0;\n parameter dyn_tx2_pma_pre_sel = 4'b0000;\n parameter dyn_tx2_pma_pre_sign = 1'b0;\n parameter dyn_tx3_pma_main_en = 6'b000000;\n parameter dyn_tx3_pma_main_sign = 1'b0;\n parameter dyn_tx3_pma_margin_input = 9'b000000000;\n parameter dyn_tx3_pma_margin_sel = 9'b000000000;\n parameter dyn_tx3_pma_post_en = 5'b00000;\n parameter dyn_tx3_pma_post_sel = 8'b00000000;\n parameter dyn_tx3_pma_post_sign = 1'b0;\n parameter dyn_tx3_pma_pre_en = 1'b0;\n parameter dyn_tx3_pma_pre_sel = 4'b0000;\n parameter dyn_tx3_pma_pre_sign = 1'b0;\n parameter location = \"\";\n parameter main_clk_to_fabric_div_en = 1'b0;\n parameter main_clk_to_fabric_div_mode = 1'b0;\n parameter main_clk_to_fabric_sel = 1'b0;\n parameter main_rclk_to_fabric_sel = 2'b00;\n parameter main_use_only_usr_clock = 1'b0;\n parameter pcs_ovs_en = 1'b0;\n parameter pcs_ovs_mode = 1'b0;\n parameter pcs_pll_lock_ppm = 3'b000;\n parameter pcs_word_len = 2'b00;\n parameter pll_pma_ckref_ext = 1'b0;\n parameter pll_pma_cpump = 4'b0000;\n parameter pll_pma_divl = 2'b00;\n parameter pll_pma_divm = 1'b0;\n parameter pll_pma_divn = 2'b00;\n parameter pll_pma_gbx_en = 1'b0;\n parameter pll_pma_int_data_len = 1'b0;\n parameter pll_pma_lvds_en = 1'b0;\n parameter pll_pma_lvds_mux = 1'b0;\n parameter pll_pma_mux_ckref = 1'b0;\n parameter rx_usrclk_use_pcs_clk_2 = 1'b0;\n parameter test_mode = 2'b00;\n parameter tx_usrclk_use_pcs_clk_2 = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17\n, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2\n, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23\n, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7\n, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2\n, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);\n input I1;\n input I10;\n input I11;\n input I12;\n input I13;\n input I14;\n input I15;\n input I16;\n input I17;\n input I18;\n input I19;\n input I2;\n input I20;\n input I21;\n input I22;\n input I23;\n input I24;\n input I25;\n input I26;\n input I27;\n input I28;\n input I29;\n input I3;\n input I30;\n input I31;\n input I32;\n input I33;\n input I34;\n input I35;\n input I36;\n input I4;\n input I5;\n input I6;\n input I7;\n input I8;\n input I9;\n output O1;\n output O10;\n output O11;\n output O12;\n output O13;\n output O14;\n output O15;\n output O16;\n output O17;\n output O18;\n output O19;\n output O2;\n output O20;\n output O21;\n output O22;\n output O23;\n output O24;\n output O25;\n output O26;\n output O27;\n output O28;\n output O29;\n output O3;\n output O30;\n output O31;\n output O32;\n output O33;\n output O34;\n output O35;\n output O36;\n output O4;\n output O5;\n output O6;\n output O7;\n output O8;\n output O9;\n input RAI1;\n input RAI2;\n input RAI3;\n input RAI4;\n input RAI5;\n input RAI6;\n input RAI7;\n output RAO1;\n output RAO2;\n output RAO3;\n output RAO4;\n output RAO5;\n output RAO6;\n output RAO7;\n input RCK;\n output REQ1;\n output REQ2;\n input RRSTI;\n output RRSTO;\n input WAI1;\n input WAI2;\n input WAI3;\n input WAI4;\n input WAI5;\n input WAI6;\n input WAI7;\n output WAO1;\n output WAO2;\n output WAO3;\n output WAO4;\n output WAO5;\n output WAO6;\n output WAO7;\n input WCK;\n input WE;\n input WEA;\n output WEQ1;\n output WEQ2;\n input WRSTI;\n output WRSTO;\n parameter mode = 0;\n parameter rck_edge = 1'b0;\n parameter read_addr_inv = 7'b0000000;\n parameter use_read_arst = 1'b0;\n parameter use_write_arst = 1'b0;\n parameter wck_edge = 1'b0;\nendmodule\n\n\n(* blackbox *)\nmodule NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1\n, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6\n, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN\n, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN\n, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1\n, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6\n, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4\n, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20\n, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);\n output AL1D;\n output AL1T;\n output AL2D;\n output AL2T;\n output AL3D;\n output AL3T;\n input ALCK1;\n input ALCK2;\n input ALCK3;\n input CA1D1;\n input CA1D2;\n input CA1D3;\n input CA1D4;\n input CA1D5;\n input CA1D6;\n input CA1N1;\n input CA1N2;\n input CA1N3;\n input CA1N4;\n input CA1P1;\n input CA1P2;\n input CA1P3;\n input CA1P4;\n input CA1T1;\n input CA1T2;\n input CA1T3;\n input CA1T4;\n input CA2D1;\n input CA2D2;\n input CA2D3;\n input CA2D4;\n input CA2D5;\n input CA2D6;\n input CA2N1;\n input CA2N2;\n input CA2N3;\n input CA2N4;\n input CA2P1;\n input CA2P2;\n input CA2P3;\n input CA2P4;\n input CA2T1;\n input CA2T2;\n input CA2T3;\n input CA2T4;\n input CCK;\n output CKO1;\n output CKO2;\n output DCL;\n input DCRN;\n input DQ1CI1;\n input DQ1CI2;\n input DQ1CI3;\n input DQ1CI4;\n input DQ1CI5;\n input DQ1CI6;\n input DQ1CI7;\n input DQ1CI8;\n input DQ2CI1;\n input DQ2CI2;\n input DQ2CI3;\n input DQ2CI4;\n input DQ2CI5;\n input DQ2CI6;\n input DQ2CI7;\n input DQ2CI8;\n input DQ3CI1;\n input DQ3CI2;\n input DQ3CI3;\n input DQ3CI4;\n input DQ3CI5;\n input DQ3CI6;\n input DQ3CI7;\n input DQ3CI8;\n input DQS1CI1;\n input DQS1CI2;\n input DQS1CI3;\n input DQS1CI4;\n input DQS1CI5;\n input DQS1CI6;\n input DQS1CI7;\n input DQS1CI8;\n input DQS2CI1;\n input DQS2CI2;\n input DQS2CI3;\n input DQS2CI4;\n input DQS2CI5;\n input DQS2CI6;\n input DQS2CI7;\n input DQS2CI8;\n input DQS3CI1;\n input DQS3CI2;\n input DQS3CI3;\n input DQS3CI4;\n input DQS3CI5;\n input DQS3CI6;\n input DQS3CI7;\n input DQS3CI8;\n input DRA1;\n input DRA2;\n input DRA3;\n input DRA4;\n input DRCCSN;\n input DRDPA1CSN;\n input DRDPA2CSN;\n input DRDPA3CSN;\n input DRE;\n input DRI1;\n input DRI1CSN;\n input DRI2;\n input DRI2CSN;\n input DRI3;\n input DRI3CSN;\n input DRI4;\n input DRI5;\n input DRI6;\n output DRO1;\n input DRO1CSN;\n output DRO2;\n input DRO2CSN;\n output DRO3;\n input DRO3CSN;\n output DRO4;\n output DRO5;\n output DRO6;\n input DRWDS;\n input DRWEN;\n input FA1;\n input FA2;\n input FA3;\n input FA4;\n input FA5;\n input FA6;\n input FCK1;\n input FCK2;\n input FDCK;\n output FLD;\n output FLG;\n input FZ;\n input LD1RN;\n input LD2RN;\n input LD3RN;\n input LDSCK1;\n input LDSCK2;\n input LDSCK3;\n input LE;\n inout [41:0] LINK1;\n inout [41:0] LINK10;\n inout [41:0] LINK11;\n inout [41:0] LINK12;\n inout [41:0] LINK13;\n inout [41:0] LINK14;\n inout [41:0] LINK15;\n inout [41:0] LINK16;\n inout [41:0] LINK17;\n inout [41:0] LINK18;\n inout [41:0] LINK19;\n inout [41:0] LINK2;\n inout [41:0] LINK20;\n inout [41:0] LINK21;\n inout [41:0] LINK22;\n inout [41:0] LINK23;\n inout [41:0] LINK24;\n inout [41:0] LINK25;\n inout [41:0] LINK26;\n inout [41:0] LINK27;\n inout [41:0] LINK28;\n inout [41:0] LINK29;\n inout [41:0] LINK3;\n inout [41:0] LINK30;\n inout [41:0] LINK31;\n inout [41:0] LINK32;\n inout [41:0] LINK33;\n inout [41:0] LINK34;\n inout [41:0] LINK4;\n inout [41:0] LINK5;\n inout [41:0] LINK6;\n inout [41:0] LINK7;\n inout [41:0] LINK8;\n inout [41:0] LINK9;\n input SE;\n input SWRX1CK;\n input SWRX2CK;\n parameter cal_delay1 = \"\";\n parameter cal_delay2 = \"\";\n parameter div1 = 3'b000;\n parameter div2 = 3'b000;\n parameter div3 = 3'b000;\n parameter div_swrx1 = 3'b000;\n parameter div_swrx2 = 3'b000;\n parameter inv_ld_sck1 = 1'b0;\n parameter inv_ld_sck2 = 1'b0;\n parameter inv_ld_sck3 = 1'b0;\n parameter link_ld_12 = 1'b0;\n parameter link_ld_23 = 1'b0;\n parameter location = \"\";\n parameter mode_side1 = 0;\n parameter mode_side2 = 0;\n parameter mode_side3 = 0;\n parameter sel_clk_out1 = 1'b0;\n parameter sel_clk_out2 = 1'b0;\n parameter sel_dc_clk = 2'b00;\n parameter sel_ld_fck1 = 2'b00;\n parameter sel_ld_fck2 = 2'b00;\n parameter sel_ld_fck3 = 2'b00;\n parameter sel_sw_fck1 = 2'b00;\n parameter sel_sw_fck2 = 2'b00;\n parameter use_dc = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1\n, RO2, RO3, RO4, RO5, CTO, LINK);\n input CI1;\n input CI2;\n input CI3;\n input CI4;\n input CI5;\n input CL;\n output CO;\n input CR;\n input CTI;\n output CTO;\n input EI1;\n input EI2;\n input EI3;\n input EI4;\n input EI5;\n input EL;\n output EO;\n input ER;\n inout [41:0] LINK;\n input RI;\n input RL;\n output RO1;\n output RO2;\n output RO3;\n output RO4;\n output RO5;\n input RR;\n parameter chained = 1'b0;\n parameter cpath_edge = 1'b0;\n parameter cpath_init = 1'b0;\n parameter cpath_inv = 1'b0;\n parameter cpath_load = 1'b0;\n parameter cpath_mode = 4'b0000;\n parameter cpath_sync = 1'b0;\n parameter epath_dynamic = 1'b0;\n parameter epath_edge = 1'b0;\n parameter epath_init = 1'b0;\n parameter epath_load = 1'b0;\n parameter epath_mode = 4'b0000;\n parameter epath_sync = 1'b0;\n parameter location = \"\";\n parameter rpath_dynamic = 1'b0;\n parameter rpath_edge = 1'b0;\n parameter rpath_init = 1'b0;\n parameter rpath_load = 1'b0;\n parameter rpath_mode = 4'b0000;\n parameter rpath_sync = 1'b0;\n parameter symbol = \"\";\n parameter tpath_mode = 2'b00;\n parameter variant = \"\";\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1\n, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK);\n input CI1;\n input CL;\n output CO;\n input CR;\n input CTI;\n output CTO;\n input EI1;\n input EI2;\n input EI3;\n input EI4;\n input EI5;\n input EI6;\n input EI7;\n input EI8;\n input EL;\n output EO;\n input ER;\n inout [41:0] LINK;\n input RI;\n input RL;\n output RO1;\n output RO2;\n output RO3;\n output RO4;\n output RO5;\n output RO6;\n output RO7;\n output RO8;\n input RR;\n parameter chained = 1'b0;\n parameter cpath_edge = 1'b0;\n parameter cpath_init = 1'b0;\n parameter cpath_inv = 1'b0;\n parameter cpath_load = 1'b0;\n parameter cpath_mode = 4'b0000;\n parameter cpath_sync = 1'b0;\n parameter cpath_type = 1'b0;\n parameter epath_dynamic = 1'b0;\n parameter epath_edge = 1'b0;\n parameter epath_init = 1'b0;\n parameter epath_load = 1'b0;\n parameter epath_mode = 4'b0000;\n parameter epath_sync = 1'b0;\n parameter epath_type = 1'b0;\n parameter location = \"\";\n parameter rpath_dynamic = 1'b0;\n parameter rpath_edge = 1'b0;\n parameter rpath_init = 1'b0;\n parameter rpath_load = 1'b0;\n parameter rpath_mode = 4'b0000;\n parameter rpath_sync = 1'b0;\n parameter rpath_type = 1'b0;\n parameter symbol = \"\";\n parameter tpath_mode = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON);\n output ALD;\n output ALT;\n output [5:0] DID;\n input [3:0] DRA;\n input [2:0] DRDN;\n input DRE;\n input [5:0] DRI;\n input [2:0] DRIN;\n output [5:0] DRO;\n input [2:0] DRON;\n input DRWDS;\n input DRWEN;\n input [5:0] FA;\n input FCK;\n output FLD;\n output FLG;\n input FZ;\n input LDRN;\n inout [41:0] LINK;\n input SCK;\n parameter data_size = 5;\n parameter location = \"\";\nendmodule\n",
303
+ "cells_map.v": "`default_nettype none\n\nmodule \\$lut (A, Y);\n parameter WIDTH = 0;\n parameter LUT = 0;\n\n (* force_downto *)\n input [WIDTH-1:0] A;\n output Y;\n\n generate\n if (WIDTH == 1) begin\n localparam [15:0] INIT = {{2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}},\n {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}};\n NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),\n .I1(A[0]), .I2(1'b0), .I3(1'b0), .I4(1'b0));\n end else\n if (WIDTH == 2) begin\n localparam [15:0] INIT = {{4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}};\n NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),\n .I1(A[0]), .I2(A[1]), .I3(1'b0), .I4(1'b0), );\n end else\n if (WIDTH == 3) begin\n localparam [15:0] INIT = {{8{LUT[7:0]}}, {8{LUT[7:0]}}};\n NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),\n .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(1'b0));\n end else\n if (WIDTH == 4) begin\n NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y),\n .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3]));\n end else begin\n wire _TECHMAP_FAIL_ = 1;\n end\n endgenerate\nendmodule\n\n(* techmap_celltype = \"$_DFF_[NP]P[01]_\" *)\nmodule \\$_DFF_xxxx_ (input D, C, R, output Q);\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == \"N\";\n localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == \"1\";\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));\nendmodule\n\n(* techmap_celltype = \"$_SDFF_[NP]P[01]_\" *)\nmodule \\$_SDFF_xxxx_ (input D, C, R, output Q);\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == \"N\";\n localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == \"1\";\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));\nendmodule\n\n(* techmap_celltype = \"$_DFFE_[NP]P[01]P_\" *)\nmodule \\$_DFFE_xxxx_ (input D, C, R, E, output Q);\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == \"N\";\n localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == \"1\";\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));\nendmodule\n\n(* techmap_celltype = \"$_SDFFE_[NP]P[01]P_\" *)\nmodule \\$_SDFFE_xxxx_ (input D, C, R, E, output Q);\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == \"N\";\n localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == \"1\";\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));\nendmodule\n\nmodule \\$_DFF_P_ (input D, C, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'b0;\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));\nendmodule\n\nmodule \\$_DFF_N_ (input D, C, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'b0;\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));\nendmodule\n\nmodule \\$_DFFE_PP_ (input D, C, E, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'b0;\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));\nendmodule\n\nmodule \\$_DFFE_NP_ (input D, C, E, output Q);\n parameter _TECHMAP_WIREINIT_Q_ = 1'b0;\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));\nendmodule\n",
304
+ "cells_sim.v": "(* abc9_lut=1 *)\nmodule NX_LUT(input I1, I2, I3, I4, output O);\n\nparameter lut_table = 16'h0000;\n\nwire [7:0] s1 = I4 ? lut_table[15:8] : lut_table[7:0];\nwire [3:0] s2 = I3 ? s1[7:4] : s1[3:0];\nwire [1:0] s3 = I2 ? s2[3:2] : s2[1:0];\nassign O = I1 ? s3[1] : s3[0];\n\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule NX_DFF(input I, CK, L, R, output reg O);\n\nparameter dff_ctxt = 1'bx;\nparameter dff_edge = 1'b0;\nparameter dff_init = 1'b0;\nparameter dff_load = 1'b0;\nparameter dff_sync = 1'b0;\nparameter dff_type = 1'b0;\n\ninitial begin\n\tO = dff_ctxt;\nend\n\nwire clock = CK ^ dff_edge;\nwire load = dff_load ? L : 1'b1;\nwire async_reset = !dff_sync && dff_init && R;\nwire sync_reset = dff_sync && dff_init && R;\n\nalways @(posedge clock, posedge async_reset)\n\tif (async_reset) O <= dff_type;\n\telse if (sync_reset) O <= dff_type;\n\telse if (load) O <= I;\n\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule NX_DFR(input I, CK, L, R, output O);\n\nparameter data_inv = 1'b0;\nparameter dff_edge = 1'b0;\nparameter dff_init = 1'b0;\nparameter dff_load = 1'b0;\nparameter dff_sync = 1'b0;\nparameter dff_type = 1'b0;\nparameter iobname = \"\";\nparameter location = \"\";\nparameter mode = 0;\nparameter path = 0;\nparameter ring = 0;\n\nwire clock = CK ^ dff_edge;\nwire load = dff_load ? L : 1'b1;\nwire async_reset = !dff_sync && dff_init && R;\nwire sync_reset = dff_sync && dff_init && R;\nreg O_reg;\n\nalways @(posedge clock, posedge async_reset)\n\tif (async_reset) O_reg <= dff_type;\n\telse if (sync_reset) O_reg <= dff_type;\n\telse if (load) O_reg <= I;\n\nassign O = data_inv ? O_reg : ~O_reg;\n\nendmodule\n\n\n(* abc9_box, lib_whitebox *)\nmodule NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);\nparameter add_carry = 0;\n\nwire CI_1;\nwire CO1, CO2, CO3;\n\nassign CI_1 = (add_carry==2) ? CI : ((add_carry==1) ? 1'b1 : 1'b0);\n\nassign { CO1, S1 } = A1 + B1 + CI_1;\nassign { CO2, S2 } = A2 + B2 + CO1;\nassign { CO3, S3 } = A3 + B3 + CO2;\nassign { CO, S4 } = A4 + B4 + CO3;\n\nendmodule\n\nmodule NX_IOB(I, C, T, O, IO);\n input C;\n input I;\n\t(* iopad_external_pin *)\n inout IO;\n output O;\n input T;\n parameter differential = \"\";\n parameter drive = \"\";\n parameter dynDrive = \"\";\n parameter dynInput = \"\";\n parameter dynTerm = \"\";\n parameter extra = 3;\n parameter inputDelayLine = \"\";\n parameter inputDelayOn = \"\";\n parameter inputSignalSlope = \"\";\n parameter location = \"\";\n parameter locked = 1'b0;\n parameter outputCapacity = \"\";\n parameter outputDelayLine = \"\";\n parameter outputDelayOn = \"\";\n parameter slewRate = \"\";\n parameter standard = \"\";\n parameter termination = \"\";\n parameter terminationReference = \"\";\n parameter turbo = \"\";\n parameter weakTermination = \"\";\n\n\tassign O = IO;\n\tassign IO = C ? I : 1'bz;\nendmodule\n\nmodule NX_IOB_I(C, T, IO, O);\n input C;\n\t(* iopad_external_pin *)\n input IO;\n output O;\n input T;\n parameter differential = \"\";\n parameter drive = \"\";\n parameter dynDrive = \"\";\n parameter dynInput = \"\";\n parameter dynTerm = \"\";\n parameter extra = 1;\n parameter inputDelayLine = \"\";\n parameter inputDelayOn = \"\";\n parameter inputSignalSlope = \"\";\n parameter location = \"\";\n parameter locked = 1'b0;\n parameter outputCapacity = \"\";\n parameter outputDelayLine = \"\";\n parameter outputDelayOn = \"\";\n parameter slewRate = \"\";\n parameter standard = \"\";\n parameter termination = \"\";\n parameter terminationReference = \"\";\n parameter turbo = \"\";\n parameter weakTermination = \"\";\n\n\tassign O = IO;\nendmodule\n\nmodule NX_IOB_O(I, C, T, IO);\n input C;\n input I;\n\t(* iopad_external_pin *)\n output IO;\n input T;\n parameter differential = \"\";\n parameter drive = \"\";\n parameter dynDrive = \"\";\n parameter dynInput = \"\";\n parameter dynTerm = \"\";\n parameter extra = 2;\n parameter inputDelayLine = \"\";\n parameter inputDelayOn = \"\";\n parameter inputSignalSlope = \"\";\n parameter location = \"\";\n parameter locked = 1'b0;\n parameter outputCapacity = \"\";\n parameter outputDelayLine = \"\";\n parameter outputDelayOn = \"\";\n parameter slewRate = \"\";\n parameter standard = \"\";\n parameter termination = \"\";\n parameter terminationReference = \"\";\n parameter turbo = \"\";\n parameter weakTermination = \"\";\n\n\tassign IO = C ? I : 1'bz;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule NX_CY_1BIT(CI, A, B, S, CO);\n (* abc9_carry *)\n input CI;\n input A;\n input B;\n output S;\n (* abc9_carry *)\n output CO;\n parameter first = 1'b0;\n\n assign {CO, S} = A + B + CI;\nendmodule\n\nmodule NX_BD(I, O);\n input I;\n output O;\n parameter mode = \"global_lowskew\";\n\n assign O = I;\nendmodule\n\nmodule NX_BFF(I, O);\n input I;\n output O;\n\n assign O = I;\nendmodule\n\nmodule NX_BFR(I, O);\n input I;\n output O;\n parameter data_inv = 1'b0;\n parameter iobname = \"\";\n parameter location = \"\";\n parameter mode = 0;\n parameter path = 0;\n parameter ring = 0;\n\n assign O = data_inv ? ~I : I;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13\n, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10\n, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3\n, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24\n, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21\n, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE\n, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);\n input AA1;\n input AA10;\n input AA11;\n input AA12;\n input AA13;\n input AA14;\n input AA15;\n input AA16;\n input AA2;\n input AA3;\n input AA4;\n input AA5;\n input AA6;\n input AA7;\n input AA8;\n input AA9;\n input ACK;\n input ACKC;\n input ACKD;\n input ACKR;\n output ACOR;\n input ACS;\n output AERR;\n input AI1;\n input AI10;\n input AI11;\n input AI12;\n input AI13;\n input AI14;\n input AI15;\n input AI16;\n input AI17;\n input AI18;\n input AI19;\n input AI2;\n input AI20;\n input AI21;\n input AI22;\n input AI23;\n input AI24;\n input AI3;\n input AI4;\n input AI5;\n input AI6;\n input AI7;\n input AI8;\n input AI9;\n output reg AO1;\n output reg AO10;\n output reg AO11;\n output reg AO12;\n output reg AO13;\n output reg AO14;\n output reg AO15;\n output reg AO16;\n output reg AO17;\n output reg AO18;\n output reg AO19;\n output reg AO2;\n output reg AO20;\n output reg AO21;\n output reg AO22;\n output reg AO23;\n output reg AO24;\n output reg AO3;\n output reg AO4;\n output reg AO5;\n output reg AO6;\n output reg AO7;\n output reg AO8;\n output reg AO9;\n input AR;\n input AWE;\n input BA1;\n input BA10;\n input BA11;\n input BA12;\n input BA13;\n input BA14;\n input BA15;\n input BA16;\n input BA2;\n input BA3;\n input BA4;\n input BA5;\n input BA6;\n input BA7;\n input BA8;\n input BA9;\n input BCK;\n input BCKC;\n input BCKD;\n input BCKR;\n output BCOR;\n input BCS;\n output BERR;\n input BI1;\n input BI10;\n input BI11;\n input BI12;\n input BI13;\n input BI14;\n input BI15;\n input BI16;\n input BI17;\n input BI18;\n input BI19;\n input BI2;\n input BI20;\n input BI21;\n input BI22;\n input BI23;\n input BI24;\n input BI3;\n input BI4;\n input BI5;\n input BI6;\n input BI7;\n input BI8;\n input BI9;\n output reg BO1;\n output reg BO10;\n output reg BO11;\n output reg BO12;\n output reg BO13;\n output reg BO14;\n output reg BO15;\n output reg BO16;\n output reg BO17;\n output reg BO18;\n output reg BO19;\n output reg BO2;\n output reg BO20;\n output reg BO21;\n output reg BO22;\n output reg BO23;\n output reg BO24;\n output reg BO3;\n output reg BO4;\n output reg BO5;\n output reg BO6;\n output reg BO7;\n output reg BO8;\n output reg BO9;\n input BR;\n input BWE;\n parameter mcka_edge = 1'b0;\n parameter mckb_edge = 1'b0;\n parameter mem_ctxt = \"\";\n parameter pcka_edge = 1'b0;\n parameter pckb_edge = 1'b0;\n parameter pipe_ia = 1'b0;\n parameter pipe_ib = 1'b0;\n parameter pipe_oa = 1'b0;\n parameter pipe_ob = 1'b0;\n parameter raw_config0 = 4'b0000;\n parameter raw_config1 = 16'b0000000000000000;\n //parameter raw_l_enable = 1'b0;\n //parameter raw_l_extend = 4'b0000;\n //parameter raw_u_enable = 1'b0;\n //parameter raw_u_extend = 8'b00000000;\n parameter std_mode = \"\";\n\n reg [24-1:0] mem [2048-1:0]; // 48 Kbit of memory\n\n /*integer i;\n initial begin\n for (i = 0; i < 2048; i = i + 1)\n mem[i] = 24'b0;\n end*/\n\n wire [15:0] AA = { AA16, AA15, AA14, AA13, AA12, AA11, AA10, AA9, AA8, AA7, AA6, AA5, AA4, AA3, AA2, AA1 };\n wire [23:0] AI = { AI24, AI23, AI22, AI21, AI20, AI19, AI18, AI17, AI16, AI15, AI14, AI13, AI12, AI11, AI10, AI9, AI8, AI7, AI6, AI5, AI4, AI3, AI2, AI1 };\n wire [23:0] AO = { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 };\n wire [15:0] BA = { BA16, BA15, BA14, BA13, BA12, BA11, BA10, BA9, BA8, BA7, BA6, BA5, BA4, BA3, BA2, BA1 };\n wire [23:0] BI = { BI24, BI23, BI22, BI21, BI20, BI19, BI18, BI17, BI16, BI15, BI14, BI13, BI12, BI11, BI10, BI9, BI8, BI7, BI6, BI5, BI4, BI3, BI2, BI1 };\n wire [23:0] BO = { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 };\n\n always @(posedge ACK)\n if (AWE)\n mem[AA[10:0]] <= AI;\n else\n { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 } <= mem[AA[10:0]];\n assign ACOR = 1'b0;\n assign AERR = 1'b0;\n\n always @(posedge BCK)\n if (BWE)\n mem[BA[10:0]] <= BI;\n else\n { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 } <= mem[BA[10:0]];\n assign BCOR = 1'b0;\n assign BERR = 1'b0;\nendmodule\n",
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+ "cells_sim_l.v": "",
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+ "cells_sim_m.v": "",
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+ "cells_sim_u.v": "(* abc9_box, lib_whitebox *)\nmodule NX_GCK_U(SI1, SI2, CMD, SO);\n input CMD;\n input SI1;\n input SI2;\n output SO;\n parameter inv_in = 1'b0;\n parameter inv_out = 1'b0;\n parameter std_mode = \"BYPASS\";\n\n wire SI1_int = inv_in ? ~SI1 : SI1;\n wire SI2_int = inv_in ? ~SI2 : SI2;\n\n wire SO_int;\n generate\n if (std_mode == \"BYPASS\") begin\n assign SO_int = SI1_int;\n end\n else if (std_mode == \"MUX\") begin\n assign SO_int = CMD ? SI1_int : SI2_int;\n end\n else if (std_mode == \"CKS\") begin\n assign SO_int = CMD ? SI1_int : 1'b0;\n end\n else if (std_mode == \"CSC\") begin\n assign SO_int = CMD;\n end\n else\n $error(\"Unrecognised std_mode\");\n endgenerate\n assign SO = inv_out ? ~SO_int : SO_int;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20\n, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5\n, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26\n, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1\n, WA2, WA3, WA4, WA5, WA6, WE, WEA);\n input I1;\n input I10;\n input I11;\n input I12;\n input I13;\n input I14;\n input I15;\n input I16;\n input I17;\n input I18;\n input I19;\n input I2;\n input I20;\n input I21;\n input I22;\n input I23;\n input I24;\n input I25;\n input I26;\n input I27;\n input I28;\n input I29;\n input I3;\n input I30;\n input I31;\n input I32;\n input I33;\n input I34;\n input I35;\n input I36;\n input I4;\n input I5;\n input I6;\n input I7;\n input I8;\n input I9;\n output O1;\n output O10;\n output O11;\n output O12;\n output O13;\n output O14;\n output O15;\n output O16;\n output O17;\n output O18;\n output O19;\n output O2;\n output O20;\n output O21;\n output O22;\n output O23;\n output O24;\n output O25;\n output O26;\n output O27;\n output O28;\n output O29;\n output O3;\n output O30;\n output O31;\n output O32;\n output O33;\n output O34;\n output O35;\n output O36;\n output O4;\n output O5;\n output O6;\n output O7;\n output O8;\n output O9;\n input RA1;\n input RA10;\n input RA2;\n input RA3;\n input RA4;\n input RA5;\n input RA6;\n input RA7;\n input RA8;\n input RA9;\n input WA1;\n input WA2;\n input WA3;\n input WA4;\n input WA5;\n input WA6;\n input WCK;\n input WE;\n input WEA;\n parameter mem_ctxt = \"\";\n parameter mode = 0;\n parameter wck_edge = 1'b0;\n\n wire clock = WCK ^ wck_edge;\n\n localparam MEM_SIZE = mode == 2 ? 64 : 32;\n localparam MEM_WIDTH = mode == 3 ? 36 : 18;\n localparam ADDR_WIDTH = mode == 2 ? 6 : 5;\n localparam DATA_SIZE = MEM_SIZE * MEM_WIDTH;\n localparam MAX_SIZE = DATA_SIZE + MEM_SIZE + 1;\n\n reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0];\n\n\tfunction [DATA_SIZE-1:0] convert_initval;\n\t\tinput [8*MAX_SIZE-1:0] hex_initval;\n\t\treg done;\n\t\treg [DATA_SIZE-1:0] temp;\n\t\treg [7:0] char;\n\t\tinteger i,j;\n\t\tbegin\n\t\t\tdone = 1'b0;\n\t\t\ttemp = 0;\n j = 0;\n\t\t\tfor (i = 0; i < MAX_SIZE; i = i + 1) begin\n char = hex_initval[8*i +: 8];\n if (char >= \"0\" && char <= \"1\") begin\n temp[j] = char - \"0\";\n j = j + 1;\n end\n\t\t\tend\n\t\t\tconvert_initval = temp;\n\t\tend\n\tendfunction\n\n integer i;\n reg [DATA_SIZE-1:0] mem_data;\n initial begin\n mem_data = convert_initval(mem_ctxt);\n for (i = 0; i < MEM_SIZE; i = i + 1)\n mem[i] = mem_data[MEM_WIDTH*(MEM_SIZE-i-1) +: MEM_WIDTH];\n end\n\n wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };\n wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28, \n O27, O26, O25, O24, O23, O22, O21, O20, O19, \n O18, O17, O16, O15, O14, O13, O12, O11, O10,\n O9, O8, O7, O6, O5, O4, O3, O2, O1 };\n wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28,\n I27, I26, I25, I24, I23, I22, I21, I20, I19,\n I18, I17, I16, I15, I14, I13, I12, I11, I10,\n I9, I8, I7, I6, I5, I4, I3, I2, I1 };\n generate \n if (mode==0) begin\n assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];\n end\n else if (mode==1) begin\n assign O = mem[{ WA5, WA4, WA3, WA2, WA1 }];\n end\n else if (mode==2) begin\n assign O = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }];\n end\n else if (mode==3) begin\n assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];\n end\n else if (mode==4) begin\n assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };\n end\n else \n $error(\"Unknown NX_RFB_U mode\");\n endgenerate\n\n always @(posedge clock)\n if (WE)\n mem[WA] <= I[MEM_WIDTH-1:0];\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule NX_WFG_U(R, SI, ZI, SO, ZO);\n input R;\n input SI;\n output SO;\n input ZI;\n output ZO;\n parameter delay = 0;\n parameter delay_on = 1'b0;\n parameter div_phase = 1'b0;\n parameter div_ratio = 0;\n parameter location = \"\";\n parameter mode = 0;\n parameter pattern = 16'b0000000000000000;\n parameter pattern_end = 0;\n parameter reset_on_cal_lock_n = 1'b0;\n parameter reset_on_pll_lock_n = 1'b0;\n parameter reset_on_pll_locka_n = 1'b0;\n parameter wfg_edge = 1'b0;\n\n generate\n if (mode==0) begin\n assign SO = SI;\n end\n else if (mode==1) begin\n wire clock = ZI ^ wfg_edge;\n wire reset = R || SI;\n reg [3:0] counter = 0;\n reg [15:0] rom = pattern;\n\n always @(posedge clock)\n begin\n if (reset)\n counter <= 4'b0;\n else\n counter <= counter + 1;\n end\n assign SO = counter == pattern_end;\n assign ZO = rom[counter];\n end\n else if (mode==2) begin\n end\n else\n $error(\"Unknown NX_WFG_U mode\");\n endgenerate\nendmodule\n\nmodule NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);\n input CK;\n input CKF;\n input R;\n input I;\n input I2;\n input L;\n output O;\n output O2;\n\n parameter location = \"\";\n parameter path = 0;\n parameter dff_type = 1'b0;\n parameter dff_sync = 1'b0;\n parameter dff_load = 1'b0;\n\n wire load = dff_load ? 1'b1 : L; // reversed when compared to DFF\n wire async_reset = !dff_sync && R;\n wire sync_reset = dff_sync && R;\n\n generate\n if (path==1) begin\n // IDDFR\n always @(posedge CK, posedge async_reset)\n if (async_reset) O <= dff_type;\n else if (sync_reset) O <= dff_type;\n else if (load) O <= I;\n\n always @(posedge CKF, posedge async_reset)\n if (async_reset) O2 <= dff_type;\n else if (sync_reset) O2 <= dff_type;\n else if (load) O2 <= I;\n end\n else if (path==0 || path==2) begin\n reg q1, q2;\n // ODDFR\n always @(posedge CK, posedge async_reset)\n if (async_reset) q1 <= dff_type;\n else if (sync_reset) q1 <= dff_type;\n else if (load) q1 <= I;\n\n always @(posedge CKF, posedge async_reset)\n if (async_reset) q2 <= dff_type;\n else if (sync_reset) q2 <= dff_type;\n else if (load) q2 <= I2;\n\n assign O = CK ? q1 : q2;\n end\n else\n $error(\"Unknown NX_DDFR_U path\");\n endgenerate\nendmodule\n",
308
+ "cells_wrap.v": "module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA\n, BA);\n input [15:0] AA;\n input ACK;\n input ACKD;\n input ACKR;\n output ACOR;\n input ACS;\n output AERR;\n input [23:0] AI;\n output [23:0] AO;\n input AR;\n input AWE;\n input [15:0] BA;\n input BCK;\n input BCKD;\n input BCKR;\n output BCOR;\n input BCS;\n output BERR;\n input [23:0] BI;\n output [23:0] BO;\n input BR;\n input BWE;\n parameter mcka_edge = 1'b0;\n parameter mckb_edge = 1'b0;\n parameter mem_ctxt = \"\";\n parameter pcka_edge = 1'b0;\n parameter pckb_edge = 1'b0;\n parameter pipe_ia = 1'b0;\n parameter pipe_ib = 1'b0;\n parameter pipe_oa = 1'b0;\n parameter pipe_ob = 1'b0;\n parameter raw_config0 = 4'b0000;\n parameter raw_config1 = 16'b0000000000000000;\n parameter std_mode = \"\";\n\n NX_RAM #(\n .mcka_edge(mcka_edge),\n .mckb_edge(mckb_edge),\n .mem_ctxt(mem_ctxt),\n .pcka_edge(pcka_edge),\n .pckb_edge(pckb_edge),\n .pipe_ia(pipe_ia),\n .pipe_ib(pipe_ib),\n .pipe_oa(pipe_oa),\n .pipe_ob(pipe_ob),\n .raw_config0(raw_config0),\n .raw_config1(raw_config1),\n .std_mode(std_mode)\n ) ram (\n .AA1(AA[0]),\n .AA10(AA[9]),\n .AA11(AA[10]),\n .AA12(AA[11]),\n .AA13(AA[12]),\n .AA14(AA[13]),\n .AA15(AA[14]),\n .AA16(AA[15]),\n .AA2(AA[1]),\n .AA3(AA[2]),\n .AA4(AA[3]),\n .AA5(AA[4]),\n .AA6(AA[5]),\n .AA7(AA[6]),\n .AA8(AA[7]),\n .AA9(AA[8]),\n .ACK(ACK),\n .ACKC(ACK),\n .ACKD(ACKD),\n .ACKR(ACKR),\n .ACOR(ACOR),\n .ACS(ACS),\n .AERR(AERR),\n .AI1(AI[0]),\n .AI10(AI[9]),\n .AI11(AI[10]),\n .AI12(AI[11]),\n .AI13(AI[12]),\n .AI14(AI[13]),\n .AI15(AI[14]),\n .AI16(AI[15]),\n .AI17(AI[16]),\n .AI18(AI[17]),\n .AI19(AI[18]),\n .AI2(AI[1]),\n .AI20(AI[19]),\n .AI21(AI[20]),\n .AI22(AI[21]),\n .AI23(AI[22]),\n .AI24(AI[23]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AI7(AI[6]),\n .AI8(AI[7]),\n .AI9(AI[8]),\n .AO1(AO[0]),\n .AO10(AO[9]),\n .AO11(AO[10]),\n .AO12(AO[11]),\n .AO13(AO[12]),\n .AO14(AO[13]),\n .AO15(AO[14]),\n .AO16(AO[15]),\n .AO17(AO[16]),\n .AO18(AO[17]),\n .AO19(AO[18]),\n .AO2(AO[1]),\n .AO20(AO[19]),\n .AO21(AO[20]),\n .AO22(AO[21]),\n .AO23(AO[22]),\n .AO24(AO[23]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .AO7(AO[6]),\n .AO8(AO[7]),\n .AO9(AO[8]),\n .AR(AR),\n .AWE(AWE),\n .BA1(BA[0]),\n .BA10(BA[9]),\n .BA11(BA[10]),\n .BA12(BA[11]),\n .BA13(BA[12]),\n .BA14(BA[13]),\n .BA15(BA[14]),\n .BA16(BA[15]),\n .BA2(BA[1]),\n .BA3(BA[2]),\n .BA4(BA[3]),\n .BA5(BA[4]),\n .BA6(BA[5]),\n .BA7(BA[6]),\n .BA8(BA[7]),\n .BA9(BA[8]),\n .BCK(BCK),\n .BCKC(BCK),\n .BCKD(BCKD),\n .BCKR(BCKR),\n .BCOR(BCOR),\n .BCS(BCS),\n .BERR(BERR),\n .BI1(BI[0]),\n .BI10(BI[9]),\n .BI11(BI[10]),\n .BI12(BI[11]),\n .BI13(BI[12]),\n .BI14(BI[13]),\n .BI15(BI[14]),\n .BI16(BI[15]),\n .BI17(BI[16]),\n .BI18(BI[17]),\n .BI19(BI[18]),\n .BI2(BI[1]),\n .BI20(BI[19]),\n .BI21(BI[20]),\n .BI22(BI[21]),\n .BI23(BI[22]),\n .BI24(BI[23]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BI7(BI[6]),\n .BI8(BI[7]),\n .BI9(BI[8]),\n .BO1(BO[0]),\n .BO10(BO[9]),\n .BO11(BO[10]),\n .BO12(BO[11]),\n .BO13(BO[12]),\n .BO14(BO[13]),\n .BO15(BO[14]),\n .BO16(BO[15]),\n .BO17(BO[16]),\n .BO18(BO[17]),\n .BO19(BO[18]),\n .BO2(BO[1]),\n .BO20(BO[19]),\n .BO21(BO[20]),\n .BO22(BO[21]),\n .BO23(BO[22]),\n .BO24(BO[23]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .BO7(BO[6]),\n .BO8(BO[7]),\n .BO9(BO[8]),\n .BR(BR),\n .BWE(BWE)\n );\n\nendmodule\n\n",
309
+ "cells_wrap_l.v": "module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI);\n input ADRSTI;\n input [5:0] AI;\n output [5:0] AO;\n input BDRSTI;\n input [5:0] BI;\n output [5:0] BO;\n input CK1;\n input CK2;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter gt0_bypass_reg1 = 1'b0;\n parameter gt0_bypass_reg2 = 1'b0;\n parameter gt1_bypass_reg1 = 1'b0;\n parameter gt1_bypass_reg2 = 1'b0;\n parameter use_adest_arst = 2'b00;\n parameter use_bdest_arst = 2'b00;\n\n NX_CDC_L #(\n .mode(0), // -- 0: 2DFF\n .ck0_edge(ck0_edge),\n .ck1_edge(ck1_edge),\n .ack_sel(ack_sel),\n .bck_sel(bck_sel),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(2'b00),\n .use_adest_arst(use_adest_arst),\n .use_bsrc_arst(2'b00),\n .use_bdest_arst(use_bdest_arst),\n .use_csrc_arst(2'b00),\n .use_cdest_arst(2'b00),\n .use_dsrc_arst(2'b00),\n .use_ddest_arst(2'b00),\n .gt0_bypass_reg1(gt0_bypass_reg1),\n .gt0_bypass_reg2(gt0_bypass_reg2),\n .gt1_bypass_reg1(gt1_bypass_reg2),\n .gt1_bypass_reg2(gt1_bypass_reg2),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0)\n );\nendmodule\n\nmodule NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);\n input ADRSTI;\n input [5:0] AI;\n output [5:0] AO;\n input ASRSTI;\n input BDRSTI;\n input [5:0] BI;\n output [5:0] BO;\n input BSRSTI;\n input CK1;\n input CK2;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter gt0_bypass_reg1 = 1'b0;\n parameter gt0_bypass_reg2 = 1'b0;\n parameter gt1_bypass_reg1 = 1'b0;\n parameter gt1_bypass_reg2 = 1'b0;\n parameter use_adest_arst = 2'b00;\n parameter use_asrc_arst = 2'b00;\n parameter use_bdest_arst = 2'b00;\n parameter use_bsrc_arst = 2'b00;\n\n NX_CDC_L #(\n .mode(1), // -- 1: 3DFF\n .ck0_edge(ck0_edge),\n .ck1_edge(ck1_edge),\n .ack_sel(ack_sel),\n .bck_sel(bck_sel),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(use_asrc_arst),\n .use_adest_arst(use_adest_arst),\n .use_bsrc_arst(use_bsrc_arst),\n .use_bdest_arst(use_bdest_arst),\n .use_csrc_arst(2'b00),\n .use_cdest_arst(2'b00),\n .use_dsrc_arst(2'b00),\n .use_ddest_arst(2'b00),\n .gt0_bypass_reg1(gt0_bypass_reg1),\n .gt0_bypass_reg2(gt0_bypass_reg2),\n .gt1_bypass_reg1(gt1_bypass_reg2),\n .gt1_bypass_reg2(gt1_bypass_reg2),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0)\n );\nendmodule\n\nmodule NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);\n input ADRSTI;\n input [5:0] AI;\n output [5:0] AO;\n input ASRSTI;\n input BDRSTI;\n input [5:0] BI;\n output [5:0] BO;\n input BSRSTI;\n input CK1;\n input CK2;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter gt0_bypass_reg1 = 1'b0;\n parameter gt0_bypass_reg2 = 1'b0;\n parameter gt1_bypass_reg1 = 1'b0;\n parameter gt1_bypass_reg2 = 1'b0;\n parameter use_adest_arst = 2'b00;\n parameter use_asrc_arst = 2'b00;\n parameter use_bdest_arst = 2'b00;\n parameter use_bsrc_arst = 2'b00;\n\n NX_CDC_L #(\n .mode(2), // -- 2: B2G_3DFF_G2B\n .ck0_edge(ck0_edge),\n .ck1_edge(ck1_edge),\n .ack_sel(ack_sel),\n .bck_sel(bck_sel),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(use_asrc_arst),\n .use_adest_arst(use_adest_arst),\n .use_bsrc_arst(use_bsrc_arst),\n .use_bdest_arst(use_bdest_arst),\n .use_csrc_arst(2'b00),\n .use_cdest_arst(2'b00),\n .use_dsrc_arst(2'b00),\n .use_ddest_arst(2'b00),\n .gt0_bypass_reg1(gt0_bypass_reg1),\n .gt0_bypass_reg2(gt0_bypass_reg2),\n .gt1_bypass_reg1(gt1_bypass_reg2),\n .gt1_bypass_reg2(gt1_bypass_reg2),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0)\n );\nendmodule\n\nmodule NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI);\n input [5:0] AI;\n output [5:0] AO;\n input [5:0] BI;\n output [5:0] BO;\n input CK1;\n input CK2;\n\n NX_CDC_L #(\n .mode(3), // -- 3: bin2gray\n .ck0_edge(1'b0),\n .ck1_edge(1'b0),\n .ack_sel(1'b0),\n .bck_sel(1'b0),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(2'b00),\n .use_adest_arst(2'b00),\n .use_bsrc_arst(2'b00),\n .use_bdest_arst(2'b00),\n .use_csrc_arst(2'b00),\n .use_cdest_arst(2'b00),\n .use_dsrc_arst(2'b00),\n .use_ddest_arst(2'b00),\n .gt0_bypass_reg1(1'b0),\n .gt0_bypass_reg2(1'b0),\n .gt1_bypass_reg1(1'b0),\n .gt1_bypass_reg2(1'b0),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0)\n );\nendmodule\n\nmodule NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO\n, CZO);\n input [23:0] A;\n input [17:0] B;\n input [35:0] C;\n input [23:0] CAI;\n output [23:0] CAO;\n input [17:0] CBI;\n output [17:0] CBO;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO;\n output CO36;\n output CO56;\n input [55:0] CZI;\n output [55:0] CZO;\n input [17:0] D;\n output OVF;\n input R;\n input RZ;\n input WE;\n output [55:0] Z;\n parameter ALU_DYNAMIC_OP = 1'b0;\n parameter ALU_MUX = 1'b0;\n parameter ALU_OP = 6'b000000;\n parameter CO_SEL = 1'b0;\n parameter ENABLE_PR_ALU_RST = 1'b0;\n parameter ENABLE_PR_A_RST = 1'b0;\n parameter ENABLE_PR_B_RST = 1'b0;\n parameter ENABLE_PR_CI_RST = 1'b0;\n parameter ENABLE_PR_CO_RST = 1'b0;\n parameter ENABLE_PR_C_RST = 1'b0;\n parameter ENABLE_PR_D_RST = 1'b0;\n parameter ENABLE_PR_MULT_RST = 1'b0;\n parameter ENABLE_PR_OV_RST = 1'b0;\n parameter ENABLE_PR_P_RST = 1'b0;\n parameter ENABLE_PR_X_RST = 1'b0;\n parameter ENABLE_PR_Y_RST = 1'b0;\n parameter ENABLE_PR_Z_RST = 1'b0;\n parameter ENABLE_SATURATION = 1'b0;\n parameter MUX_A = 1'b0;\n parameter MUX_B = 1'b0;\n parameter MUX_CI = 1'b0;\n parameter MUX_P = 1'b0;\n parameter MUX_X = 2'b00;\n parameter MUX_Y = 1'b0;\n parameter MUX_Z = 1'b0;\n parameter PRE_ADDER_OP = 1'b0;\n parameter PR_ALU_MUX = 1'b0;\n parameter PR_A_CASCADE_MUX = 2'b00;\n parameter PR_A_MUX = 2'b00;\n parameter PR_B_CASCADE_MUX = 2'b00;\n parameter PR_B_MUX = 2'b00;\n parameter PR_CI_MUX = 1'b0;\n parameter PR_CO_MUX = 1'b0;\n parameter PR_C_MUX = 1'b0;\n parameter PR_D_MUX = 1'b0;\n parameter PR_MULT_MUX = 1'b0;\n parameter PR_OV_MUX = 1'b0;\n parameter PR_P_MUX = 1'b0;\n parameter PR_X_MUX = 1'b0;\n parameter PR_Y_MUX = 1'b0;\n parameter PR_Z_MUX = 1'b0;\n parameter SATURATION_RANK = 6'b000000;\n parameter SIGNED_MODE = 1'b0;\n parameter Z_FEEDBACK_SHL12 = 1'b0;\n\nlocalparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z,\n MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };\n\nlocalparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX,\n PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };\n\nlocalparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST,\n ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,\n ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };\n\nlocalparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP };\n\n NX_DSP_L #(\n .std_mode(\"\"),\n .raw_config0(RAW_CONFIG0_GEN),\n .raw_config1(RAW_CONFIG1_GEN),\n .raw_config2(RAW_CONFIG2_GEN),\n .raw_config3(RAW_CONFIG3_GEN),\n ) _TECHMAP_REPLACE_ (\n .A1(A[0]),\n .A2(A[1]),\n .A3(A[2]),\n .A4(A[3]),\n .A5(A[4]),\n .A6(A[5]),\n .A7(A[6]),\n .A8(A[7]),\n .A9(A[8]),\n .A10(A[9]),\n .A11(A[10]),\n .A12(A[11]),\n .A13(A[12]),\n .A14(A[13]),\n .A15(A[14]),\n .A16(A[15]),\n .A17(A[16]),\n .A18(A[17]),\n .A19(A[18]),\n .A20(A[19]),\n .A21(A[20]),\n .A22(A[21]),\n .A23(A[22]),\n .A24(A[23]),\n\n .B1(B[0]),\n .B2(B[1]),\n .B3(B[2]),\n .B4(B[3]),\n .B5(B[4]),\n .B6(B[5]),\n .B7(B[6]),\n .B8(B[7]),\n .B9(B[8]),\n .B10(B[9]),\n .B11(B[10]),\n .B12(B[11]),\n .B13(B[12]),\n .B14(B[13]),\n .B15(B[14]),\n .B16(B[15]),\n .B17(B[16]),\n .B18(B[17]),\n\n .C1(C[0]),\n .C2(C[1]),\n .C3(C[2]),\n .C4(C[3]),\n .C5(C[4]),\n .C6(C[5]),\n .C7(C[6]),\n .C8(C[7]),\n .C9(C[8]),\n .C10(C[9]),\n .C11(C[10]),\n .C12(C[11]),\n .C13(C[12]),\n .C14(C[13]),\n .C15(C[14]),\n .C16(C[15]),\n .C17(C[16]),\n .C18(C[17]),\n .C19(C[18]),\n .C20(C[19]),\n .C21(C[20]),\n .C22(C[21]),\n .C23(C[22]),\n .C24(C[23]),\n .C25(C[24]),\n .C26(C[25]),\n .C27(C[26]),\n .C28(C[27]),\n .C29(C[28]),\n .C30(C[29]),\n .C31(C[30]),\n .C32(C[31]),\n .C33(C[32]),\n .C34(C[33]),\n .C35(C[34]),\n .C36(C[35]),\n\n .CAI1(CAI[0]),\n .CAI2(CAI[1]),\n .CAI3(CAI[2]),\n .CAI4(CAI[3]),\n .CAI5(CAI[4]),\n .CAI6(CAI[5]),\n .CAI7(CAI[6]),\n .CAI8(CAI[7]),\n .CAI9(CAI[8]),\n .CAI10(CAI[9]),\n .CAI11(CAI[10]),\n .CAI12(CAI[11]),\n .CAI13(CAI[12]),\n .CAI14(CAI[13]),\n .CAI15(CAI[14]),\n .CAI16(CAI[15]),\n .CAI17(CAI[16]),\n .CAI18(CAI[17]),\n .CAI19(CAI[18]),\n .CAI20(CAI[19]),\n .CAI21(CAI[20]),\n .CAI22(CAI[21]),\n .CAI23(CAI[22]),\n .CAI24(CAI[23]),\n\n .CAO1(CAO[0]),\n .CAO2(CAO[1]),\n .CAO3(CAO[2]),\n .CAO4(CAO[3]),\n .CAO5(CAO[4]),\n .CAO6(CAO[5]),\n .CAO7(CAO[6]),\n .CAO8(CAO[7]),\n .CAO9(CAO[8]),\n .CAO10(CAO[9]),\n .CAO11(CAO[10]),\n .CAO12(CAO[11]),\n .CAO13(CAO[12]),\n .CAO14(CAO[13]),\n .CAO15(CAO[14]),\n .CAO16(CAO[15]),\n .CAO17(CAO[16]),\n .CAO18(CAO[17]),\n .CAO19(CAO[18]),\n .CAO20(CAO[19]),\n .CAO21(CAO[20]),\n .CAO22(CAO[21]),\n .CAO23(CAO[22]),\n .CAO24(CAO[23]),\n\n .CBI1(CBI[0]),\n .CBI2(CBI[1]),\n .CBI3(CBI[2]),\n .CBI4(CBI[3]),\n .CBI5(CBI[4]),\n .CBI6(CBI[5]),\n .CBI7(CBI[6]),\n .CBI8(CBI[7]),\n .CBI9(CBI[8]),\n .CBI10(CBI[9]),\n .CBI11(CBI[10]),\n .CBI12(CBI[11]),\n .CBI13(CBI[12]),\n .CBI14(CBI[13]),\n .CBI15(CBI[14]),\n .CBI16(CBI[15]),\n .CBI17(CBI[16]),\n .CBI18(CBI[17]),\n\n .CBO1(CBO[0]),\n .CBO2(CBO[1]),\n .CBO3(CBO[2]),\n .CBO4(CBO[3]),\n .CBO5(CBO[4]),\n .CBO6(CBO[5]),\n .CBO7(CBO[6]),\n .CBO8(CBO[7]),\n .CBO9(CBO[8]),\n .CBO10(CBO[9]),\n .CBO11(CBO[10]),\n .CBO12(CBO[11]),\n .CBO13(CBO[12]),\n .CBO14(CBO[13]),\n .CBO15(CBO[14]),\n .CBO16(CBO[15]),\n .CBO17(CBO[16]),\n .CBO18(CBO[17]),\n\n .CCI(CCI),\n .CCO(CCO),\n .CI(CI),\n .CK(CK),\n .CO(CO),\n .CO37(CO36),\n .CO57(CO56),\n\n .CZI1(CZI[0]),\n .CZI2(CZI[1]),\n .CZI3(CZI[2]),\n .CZI4(CZI[3]),\n .CZI5(CZI[4]),\n .CZI6(CZI[5]),\n .CZI7(CZI[6]),\n .CZI8(CZI[7]),\n .CZI9(CZI[8]),\n .CZI10(CZI[9]),\n .CZI11(CZI[10]),\n .CZI12(CZI[11]),\n .CZI13(CZI[12]),\n .CZI14(CZI[13]),\n .CZI15(CZI[14]),\n .CZI16(CZI[15]),\n .CZI17(CZI[16]),\n .CZI18(CZI[17]),\n .CZI19(CZI[18]),\n .CZI20(CZI[19]),\n .CZI21(CZI[20]),\n .CZI22(CZI[21]),\n .CZI23(CZI[22]),\n .CZI24(CZI[23]),\n .CZI25(CZI[24]),\n .CZI26(CZI[25]),\n .CZI27(CZI[26]),\n .CZI28(CZI[27]),\n .CZI29(CZI[28]),\n .CZI30(CZI[29]),\n .CZI31(CZI[30]),\n .CZI32(CZI[31]),\n .CZI33(CZI[32]),\n .CZI34(CZI[33]),\n .CZI35(CZI[34]),\n .CZI36(CZI[35]),\n .CZI37(CZI[36]),\n .CZI38(CZI[37]),\n .CZI39(CZI[38]),\n .CZI40(CZI[39]),\n .CZI41(CZI[40]),\n .CZI42(CZI[41]),\n .CZI43(CZI[42]),\n .CZI44(CZI[43]),\n .CZI45(CZI[44]),\n .CZI46(CZI[45]),\n .CZI47(CZI[46]),\n .CZI48(CZI[47]),\n .CZI49(CZI[48]),\n .CZI50(CZI[49]),\n .CZI51(CZI[50]),\n .CZI52(CZI[51]),\n .CZI53(CZI[52]),\n .CZI54(CZI[53]),\n .CZI55(CZI[54]),\n .CZI56(CZI[55]),\n\n .CZO1(CZO[0]),\n .CZO2(CZO[1]),\n .CZO3(CZO[2]),\n .CZO4(CZO[3]),\n .CZO5(CZO[4]),\n .CZO6(CZO[5]),\n .CZO7(CZO[6]),\n .CZO8(CZO[7]),\n .CZO9(CZO[8]),\n .CZO10(CZO[9]),\n .CZO11(CZO[10]),\n .CZO12(CZO[11]),\n .CZO13(CZO[12]),\n .CZO14(CZO[13]),\n .CZO15(CZO[14]),\n .CZO16(CZO[15]),\n .CZO17(CZO[16]),\n .CZO18(CZO[17]),\n .CZO19(CZO[18]),\n .CZO20(CZO[19]),\n .CZO21(CZO[20]),\n .CZO22(CZO[21]),\n .CZO23(CZO[22]),\n .CZO24(CZO[23]),\n .CZO25(CZO[24]),\n .CZO26(CZO[25]),\n .CZO27(CZO[26]),\n .CZO28(CZO[27]),\n .CZO29(CZO[28]),\n .CZO30(CZO[29]),\n .CZO31(CZO[30]),\n .CZO32(CZO[31]),\n .CZO33(CZO[32]),\n .CZO34(CZO[33]),\n .CZO35(CZO[34]),\n .CZO36(CZO[35]),\n .CZO37(CZO[36]),\n .CZO38(CZO[37]),\n .CZO39(CZO[38]),\n .CZO40(CZO[39]),\n .CZO41(CZO[40]),\n .CZO42(CZO[41]),\n .CZO43(CZO[42]),\n .CZO44(CZO[43]),\n .CZO45(CZO[44]),\n .CZO46(CZO[45]),\n .CZO47(CZO[46]),\n .CZO48(CZO[47]),\n .CZO49(CZO[48]),\n .CZO50(CZO[49]),\n .CZO51(CZO[50]),\n .CZO52(CZO[51]),\n .CZO53(CZO[52]),\n .CZO54(CZO[53]),\n .CZO55(CZO[54]),\n .CZO56(CZO[55]),\n\n .D1(D[0]),\n .D2(D[1]),\n .D3(D[2]),\n .D4(D[3]),\n .D5(D[4]),\n .D6(D[5]),\n .D7(D[6]),\n .D8(D[7]),\n .D9(D[8]),\n .D10(D[9]),\n .D11(D[10]),\n .D12(D[11]),\n .D13(D[12]),\n .D14(D[13]),\n .D15(D[14]),\n .D16(D[15]),\n .D17(D[16]),\n .D18(D[17]),\n\n .OVF(OVF),\n .R(R),\n .RZ(RZ),\n .WE(WE),\n\n .Z1(Z[0]),\n .Z2(Z[1]),\n .Z3(Z[2]),\n .Z4(Z[3]),\n .Z5(Z[4]),\n .Z6(Z[5]),\n .Z7(Z[6]),\n .Z8(Z[7]),\n .Z9(Z[8]),\n .Z10(Z[9]),\n .Z11(Z[10]),\n .Z12(Z[11]),\n .Z13(Z[12]),\n .Z14(Z[13]),\n .Z15(Z[14]),\n .Z16(Z[15]),\n .Z17(Z[16]),\n .Z18(Z[17]),\n .Z19(Z[18]),\n .Z20(Z[19]),\n .Z21(Z[20]),\n .Z22(Z[21]),\n .Z23(Z[22]),\n .Z24(Z[23]),\n .Z25(Z[24]),\n .Z26(Z[25]),\n .Z27(Z[26]),\n .Z28(Z[27]),\n .Z29(Z[28]),\n .Z30(Z[29]),\n .Z31(Z[30]),\n .Z32(Z[31]),\n .Z33(Z[32]),\n .Z34(Z[33]),\n .Z35(Z[34]),\n .Z36(Z[35]),\n .Z37(Z[36]),\n .Z38(Z[37]),\n .Z39(Z[38]),\n .Z40(Z[39]),\n .Z41(Z[40]),\n .Z42(Z[41]),\n .Z43(Z[42]),\n .Z44(Z[43]),\n .Z45(Z[44]),\n .Z46(Z[45]),\n .Z47(Z[46]),\n .Z48(Z[47]),\n .Z49(Z[48]),\n .Z50(Z[49]),\n .Z51(Z[50]),\n .Z52(Z[51]),\n .Z53(Z[52]),\n .Z54(Z[53]),\n .Z55(Z[54]),\n .Z56(Z[55])\n );\nendmodule\n\nmodule NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO\n, CZO);\n input [23:0] A;\n input [17:0] B;\n input [35:0] C;\n input [23:0] CAI;\n output [23:0] CAO;\n input [17:0] CBI;\n output [17:0] CBO;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO;\n output CO37;\n output CO57;\n input [55:0] CZI;\n output [55:0] CZO;\n input [17:0] D;\n output OVF;\n input R;\n input RZ;\n input WE;\n output [55:0] Z;\n parameter raw_config0 = 20'b00000000000000000000;\n parameter raw_config1 = 19'b0000000000000000000;\n parameter raw_config2 = 13'b0000000000000;\n parameter raw_config3 = 7'b0000000;\n parameter std_mode = \"\";\n\n NX_DSP_L #(\n .std_mode(std_mode),\n .raw_config0(raw_config0),\n .raw_config1(raw_config1),\n .raw_config2(raw_config2),\n .raw_config3(raw_config3),\n ) _TECHMAP_REPLACE_ (\n .A1(A[0]),\n .A2(A[1]),\n .A3(A[2]),\n .A4(A[3]),\n .A5(A[4]),\n .A6(A[5]),\n .A7(A[6]),\n .A8(A[7]),\n .A9(A[8]),\n .A10(A[9]),\n .A11(A[10]),\n .A12(A[11]),\n .A13(A[12]),\n .A14(A[13]),\n .A15(A[14]),\n .A16(A[15]),\n .A17(A[16]),\n .A18(A[17]),\n .A19(A[18]),\n .A20(A[19]),\n .A21(A[20]),\n .A22(A[21]),\n .A23(A[22]),\n .A24(A[23]),\n\n .B1(B[0]),\n .B2(B[1]),\n .B3(B[2]),\n .B4(B[3]),\n .B5(B[4]),\n .B6(B[5]),\n .B7(B[6]),\n .B8(B[7]),\n .B9(B[8]),\n .B10(B[9]),\n .B11(B[10]),\n .B12(B[11]),\n .B13(B[12]),\n .B14(B[13]),\n .B15(B[14]),\n .B16(B[15]),\n .B17(B[16]),\n .B18(B[17]),\n\n .C1(C[0]),\n .C2(C[1]),\n .C3(C[2]),\n .C4(C[3]),\n .C5(C[4]),\n .C6(C[5]),\n .C7(C[6]),\n .C8(C[7]),\n .C9(C[8]),\n .C10(C[9]),\n .C11(C[10]),\n .C12(C[11]),\n .C13(C[12]),\n .C14(C[13]),\n .C15(C[14]),\n .C16(C[15]),\n .C17(C[16]),\n .C18(C[17]),\n .C19(C[18]),\n .C20(C[19]),\n .C21(C[20]),\n .C22(C[21]),\n .C23(C[22]),\n .C24(C[23]),\n .C25(C[24]),\n .C26(C[25]),\n .C27(C[26]),\n .C28(C[27]),\n .C29(C[28]),\n .C30(C[29]),\n .C31(C[30]),\n .C32(C[31]),\n .C33(C[32]),\n .C34(C[33]),\n .C35(C[34]),\n .C36(C[35]),\n\n .CAI1(CAI[0]),\n .CAI2(CAI[1]),\n .CAI3(CAI[2]),\n .CAI4(CAI[3]),\n .CAI5(CAI[4]),\n .CAI6(CAI[5]),\n .CAI7(CAI[6]),\n .CAI8(CAI[7]),\n .CAI9(CAI[8]),\n .CAI10(CAI[9]),\n .CAI11(CAI[10]),\n .CAI12(CAI[11]),\n .CAI13(CAI[12]),\n .CAI14(CAI[13]),\n .CAI15(CAI[14]),\n .CAI16(CAI[15]),\n .CAI17(CAI[16]),\n .CAI18(CAI[17]),\n .CAI19(CAI[18]),\n .CAI20(CAI[19]),\n .CAI21(CAI[20]),\n .CAI22(CAI[21]),\n .CAI23(CAI[22]),\n .CAI24(CAI[23]),\n\n .CAO1(CAO[0]),\n .CAO2(CAO[1]),\n .CAO3(CAO[2]),\n .CAO4(CAO[3]),\n .CAO5(CAO[4]),\n .CAO6(CAO[5]),\n .CAO7(CAO[6]),\n .CAO8(CAO[7]),\n .CAO9(CAO[8]),\n .CAO10(CAO[9]),\n .CAO11(CAO[10]),\n .CAO12(CAO[11]),\n .CAO13(CAO[12]),\n .CAO14(CAO[13]),\n .CAO15(CAO[14]),\n .CAO16(CAO[15]),\n .CAO17(CAO[16]),\n .CAO18(CAO[17]),\n .CAO19(CAO[18]),\n .CAO20(CAO[19]),\n .CAO21(CAO[20]),\n .CAO22(CAO[21]),\n .CAO23(CAO[22]),\n .CAO24(CAO[23]),\n\n .CBI1(CBI[0]),\n .CBI2(CBI[1]),\n .CBI3(CBI[2]),\n .CBI4(CBI[3]),\n .CBI5(CBI[4]),\n .CBI6(CBI[5]),\n .CBI7(CBI[6]),\n .CBI8(CBI[7]),\n .CBI9(CBI[8]),\n .CBI10(CBI[9]),\n .CBI11(CBI[10]),\n .CBI12(CBI[11]),\n .CBI13(CBI[12]),\n .CBI14(CBI[13]),\n .CBI15(CBI[14]),\n .CBI16(CBI[15]),\n .CBI17(CBI[16]),\n .CBI18(CBI[17]),\n\n .CBO1(CBO[0]),\n .CBO2(CBO[1]),\n .CBO3(CBO[2]),\n .CBO4(CBO[3]),\n .CBO5(CBO[4]),\n .CBO6(CBO[5]),\n .CBO7(CBO[6]),\n .CBO8(CBO[7]),\n .CBO9(CBO[8]),\n .CBO10(CBO[9]),\n .CBO11(CBO[10]),\n .CBO12(CBO[11]),\n .CBO13(CBO[12]),\n .CBO14(CBO[13]),\n .CBO15(CBO[14]),\n .CBO16(CBO[15]),\n .CBO17(CBO[16]),\n .CBO18(CBO[17]),\n\n .CCI(CCI),\n .CCO(CCO),\n .CI(CI),\n .CK(CK),\n .CO(CO),\n .CO37(CO37),\n .CO57(CO57),\n\n .CZI1(CZI[0]),\n .CZI2(CZI[1]),\n .CZI3(CZI[2]),\n .CZI4(CZI[3]),\n .CZI5(CZI[4]),\n .CZI6(CZI[5]),\n .CZI7(CZI[6]),\n .CZI8(CZI[7]),\n .CZI9(CZI[8]),\n .CZI10(CZI[9]),\n .CZI11(CZI[10]),\n .CZI12(CZI[11]),\n .CZI13(CZI[12]),\n .CZI14(CZI[13]),\n .CZI15(CZI[14]),\n .CZI16(CZI[15]),\n .CZI17(CZI[16]),\n .CZI18(CZI[17]),\n .CZI19(CZI[18]),\n .CZI20(CZI[19]),\n .CZI21(CZI[20]),\n .CZI22(CZI[21]),\n .CZI23(CZI[22]),\n .CZI24(CZI[23]),\n .CZI25(CZI[24]),\n .CZI26(CZI[25]),\n .CZI27(CZI[26]),\n .CZI28(CZI[27]),\n .CZI29(CZI[28]),\n .CZI30(CZI[29]),\n .CZI31(CZI[30]),\n .CZI32(CZI[31]),\n .CZI33(CZI[32]),\n .CZI34(CZI[33]),\n .CZI35(CZI[34]),\n .CZI36(CZI[35]),\n .CZI37(CZI[36]),\n .CZI38(CZI[37]),\n .CZI39(CZI[38]),\n .CZI40(CZI[39]),\n .CZI41(CZI[40]),\n .CZI42(CZI[41]),\n .CZI43(CZI[42]),\n .CZI44(CZI[43]),\n .CZI45(CZI[44]),\n .CZI46(CZI[45]),\n .CZI47(CZI[46]),\n .CZI48(CZI[47]),\n .CZI49(CZI[48]),\n .CZI50(CZI[49]),\n .CZI51(CZI[50]),\n .CZI52(CZI[51]),\n .CZI53(CZI[52]),\n .CZI54(CZI[53]),\n .CZI55(CZI[54]),\n .CZI56(CZI[55]),\n\n .CZO1(CZO[0]),\n .CZO2(CZO[1]),\n .CZO3(CZO[2]),\n .CZO4(CZO[3]),\n .CZO5(CZO[4]),\n .CZO6(CZO[5]),\n .CZO7(CZO[6]),\n .CZO8(CZO[7]),\n .CZO9(CZO[8]),\n .CZO10(CZO[9]),\n .CZO11(CZO[10]),\n .CZO12(CZO[11]),\n .CZO13(CZO[12]),\n .CZO14(CZO[13]),\n .CZO15(CZO[14]),\n .CZO16(CZO[15]),\n .CZO17(CZO[16]),\n .CZO18(CZO[17]),\n .CZO19(CZO[18]),\n .CZO20(CZO[19]),\n .CZO21(CZO[20]),\n .CZO22(CZO[21]),\n .CZO23(CZO[22]),\n .CZO24(CZO[23]),\n .CZO25(CZO[24]),\n .CZO26(CZO[25]),\n .CZO27(CZO[26]),\n .CZO28(CZO[27]),\n .CZO29(CZO[28]),\n .CZO30(CZO[29]),\n .CZO31(CZO[30]),\n .CZO32(CZO[31]),\n .CZO33(CZO[32]),\n .CZO34(CZO[33]),\n .CZO35(CZO[34]),\n .CZO36(CZO[35]),\n .CZO37(CZO[36]),\n .CZO38(CZO[37]),\n .CZO39(CZO[38]),\n .CZO40(CZO[39]),\n .CZO41(CZO[40]),\n .CZO42(CZO[41]),\n .CZO43(CZO[42]),\n .CZO44(CZO[43]),\n .CZO45(CZO[44]),\n .CZO46(CZO[45]),\n .CZO47(CZO[46]),\n .CZO48(CZO[47]),\n .CZO49(CZO[48]),\n .CZO50(CZO[49]),\n .CZO51(CZO[50]),\n .CZO52(CZO[51]),\n .CZO53(CZO[52]),\n .CZO54(CZO[53]),\n .CZO55(CZO[54]),\n .CZO56(CZO[55]),\n\n .D1(D[0]),\n .D2(D[1]),\n .D3(D[2]),\n .D4(D[3]),\n .D5(D[4]),\n .D6(D[5]),\n .D7(D[6]),\n .D8(D[7]),\n .D9(D[8]),\n .D10(D[9]),\n .D11(D[10]),\n .D12(D[11]),\n .D13(D[12]),\n .D14(D[13]),\n .D15(D[14]),\n .D16(D[15]),\n .D17(D[16]),\n .D18(D[17]),\n\n .OVF(OVF),\n .R(R),\n .RZ(RZ),\n .WE(WE),\n\n .Z1(Z[0]),\n .Z2(Z[1]),\n .Z3(Z[2]),\n .Z4(Z[3]),\n .Z5(Z[4]),\n .Z6(Z[5]),\n .Z7(Z[6]),\n .Z8(Z[7]),\n .Z9(Z[8]),\n .Z10(Z[9]),\n .Z11(Z[10]),\n .Z12(Z[11]),\n .Z13(Z[12]),\n .Z14(Z[13]),\n .Z15(Z[14]),\n .Z16(Z[15]),\n .Z17(Z[16]),\n .Z18(Z[17]),\n .Z19(Z[18]),\n .Z20(Z[19]),\n .Z21(Z[20]),\n .Z22(Z[21]),\n .Z23(Z[22]),\n .Z24(Z[23]),\n .Z25(Z[24]),\n .Z26(Z[25]),\n .Z27(Z[26]),\n .Z28(Z[27]),\n .Z29(Z[28]),\n .Z30(Z[29]),\n .Z31(Z[30]),\n .Z32(Z[31]),\n .Z33(Z[32]),\n .Z34(Z[33]),\n .Z35(Z[34]),\n .Z36(Z[35]),\n .Z37(Z[36]),\n .Z38(Z[37]),\n .Z39(Z[38]),\n .Z40(Z[39]),\n .Z41(Z[40]),\n .Z42(Z[41]),\n .Z43(Z[42]),\n .Z44(Z[43]),\n .Z45(Z[44]),\n .Z46(Z[45]),\n .Z47(Z[46]),\n .Z48(Z[47]),\n .Z49(Z[48]),\n .Z50(Z[49]),\n .Z51(Z[50]),\n .Z52(Z[51]),\n .Z53(Z[52]),\n .Z54(Z[53]),\n .Z55(Z[54]),\n .Z56(Z[55])\n );\nendmodule\n\nmodule NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);\n output COR;\n output ERR;\n input [15:0] I;\n output [15:0] O;\n input [5:0] RA;\n input RCK;\n input RE;\n input [5:0] WA;\n input WCK;\n input WE;\n parameter mem_ctxt = \"\";\n parameter mode = 0;\n parameter rck_edge = 1'b0;\n parameter wck_edge = 1'b0;\n\n NX_RFB_L #(\n .mode(mode),\n .rck_edge(rck_edge),\n .wck_edge(wck_edge),\n .mem_ctxt(mem_ctxt)\n ) _TECHMAP_REPLACE_ (\n .RCK(RCK),\n .WCK(WCK),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .COR(COR),\n .ERR(ERR),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .RA1(RA[0]),\n .RA2(RA[1]),\n .RA3(RA[2]),\n .RA4(RA[3]),\n .RA5(RA[4]),\n .RA6(RA[5]),\n .RE(RE),\n .WA1(WA[0]),\n .WA2(WA[1]),\n .WA3(WA[2]),\n .WA4(WA[3]),\n .WA5(WA[4]),\n .WA6(WA[5]),\n .WE(WE)\n );\nendmodule\n\nmodule NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1\n, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6\n, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);\n output COR;\n output ERR;\n input I1;\n input I10;\n input I11;\n input I12;\n input I13;\n input I14;\n input I15;\n input I16;\n input I2;\n input I3;\n input I4;\n input I5;\n input I6;\n input I7;\n input I8;\n input I9;\n output O1;\n output O10;\n output O11;\n output O12;\n output O13;\n output O14;\n output O15;\n output O16;\n output O2;\n output O3;\n output O4;\n output O5;\n output O6;\n output O7;\n output O8;\n output O9;\n input RA1;\n input RA2;\n input RA3;\n input RA4;\n input RA5;\n input RA6;\n input RCK;\n input RE;\n input WA1;\n input WA2;\n input WA3;\n input WA4;\n input WA5;\n input WA6;\n input WCK;\n input WE;\n parameter addr_mask = 5'b00000;\n parameter mem_ctxt = \"\";\n parameter rck_edge = 1'b0;\n parameter wck_edge = 1'b0;\n parameter we_mask = 1'b0;\n parameter wea_mask = 1'b0;\n\n NX_RFB_L #(\n .mode(0),\n .mem_ctxt(mem_ctxt),\n .rck_edge(rck_edge),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .RCK(RCK),\n .WCK(WCK),\n .I1(I1),\n .I2(I2),\n .I3(I3),\n .I4(I4),\n .I5(I5),\n .I6(I6),\n .I7(I7),\n .I8(I8),\n .I9(I9),\n .I10(I10),\n .I11(I11),\n .I12(I12),\n .I13(I13),\n .I14(I14),\n .I15(I15),\n .I16(I16),\n .COR(COR),\n .ERR(ERR),\n .O1(O1),\n .O2(O2),\n .O3(O3),\n .O4(O4),\n .O5(O5),\n .O6(O6),\n .O7(O7),\n .O8(O8),\n .O9(O9),\n .O10(O10),\n .O11(O11),\n .O12(O12),\n .O13(O13),\n .O14(O14),\n .O15(O15),\n .O16(O16),\n .RA1(RA1),\n .RA2(RA2),\n .RA3(RA3),\n .RA4(RA4),\n .RA5(RA5),\n .RA6(RA6),\n .RE(RE),\n .WA1(WA1),\n .WA2(WA2),\n .WA3(WA3),\n .WA4(WA4),\n .WA5(WA5),\n .WA6(WA6),\n .WE(WE)\n );\nendmodule\n\n//TODO\nmodule SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);\n input [23:0] A;\n input [31:0] B;\n output [91:0] Z;\n input clk;\n input rst;\n input we;\nendmodule\n\n//TODO\nmodule NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o\n, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o\n, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o\n, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o\n, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o\n, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o\n, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i\n, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i\n, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o\n, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o\n, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o\n, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o\n, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i);\n input hssl_clk_ref_i;\n input hssl_clk_user_i;\n output hssl_clock_o;\n input pma_clk_ext_i;\n input pma_rx0_i;\n input pma_rx1_i;\n input pma_rx2_i;\n input pma_rx3_i;\n input pma_rx4_i;\n input pma_rx5_i;\n output pma_tx0_o;\n output pma_tx1_o;\n output pma_tx2_o;\n output pma_tx3_o;\n output pma_tx4_o;\n output pma_tx5_o;\n input usr_calibrate_pma_en_i;\n output usr_calibrate_pma_out_o;\n input [7:0] usr_calibrate_pma_res_n2_i;\n input [7:0] usr_calibrate_pma_res_n3_i;\n input [7:0] usr_calibrate_pma_res_p1_i;\n input [7:0] usr_calibrate_pma_res_p4_i;\n input [3:0] usr_calibrate_pma_sel_i;\n input [5:0] usr_com_ctrl_rx_sel_i;\n input [5:0] usr_com_ctrl_tx_sel_i;\n input [3:0] usr_com_rx_pma_ctle_cap_i;\n input [3:0] usr_com_rx_pma_ctle_resn_i;\n input [3:0] usr_com_rx_pma_ctle_resp_i;\n input usr_com_rx_pma_m_eye_i;\n input [5:0] usr_com_tx_pma_main_en_i;\n input usr_com_tx_pma_main_sign_i;\n input [3:0] usr_com_tx_pma_margin_input_sel_i;\n input [4:0] usr_com_tx_pma_margin_input_sel_var_i;\n input [3:0] usr_com_tx_pma_margin_sel_i;\n input [4:0] usr_com_tx_pma_margin_sel_var_i;\n input [4:0] usr_com_tx_pma_post_en_i;\n input [3:0] usr_com_tx_pma_post_input_sel_i;\n input [3:0] usr_com_tx_pma_post_input_sel_var_i;\n input usr_com_tx_pma_post_sign_i;\n input usr_com_tx_pma_pre_en_i;\n input [3:0] usr_com_tx_pma_pre_input_sel_i;\n input usr_com_tx_pma_pre_sign_i;\n input usr_main_rst_n_i;\n input [7:0] usr_main_test_i;\n output [7:0] usr_main_test_o;\n input usr_pcs_ctrl_ovs_en_i;\n input usr_pcs_ctrl_pll_lock_en_i;\n output usr_pll_lock_o;\n input usr_pll_pma_rst_n_i;\n output usr_rx0_busy_o;\n input usr_rx0_ctrl_align_en_i;\n input usr_rx0_ctrl_align_sync_i;\n output [7:0] usr_rx0_ctrl_char_is_a_o;\n output usr_rx0_ctrl_char_is_aligned_o;\n output [7:0] usr_rx0_ctrl_char_is_comma_o;\n output [7:0] usr_rx0_ctrl_char_is_f_o;\n output [7:0] usr_rx0_ctrl_char_is_k_o;\n input usr_rx0_ctrl_dec_en_i;\n output [7:0] usr_rx0_ctrl_disp_err_o;\n input usr_rx0_ctrl_dscr_en_i;\n input usr_rx0_ctrl_el_buff_fifo_en_i;\n input usr_rx0_ctrl_el_buff_rst_i;\n output [7:0] usr_rx0_ctrl_not_in_table_o;\n input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;\n input usr_rx0_ctrl_replace_en_i;\n output [63:0] usr_rx0_data_o;\n output usr_rx0_pll_lock_o;\n input usr_rx0_pma_cdr_rst_i;\n input usr_rx0_pma_ckgen_rst_n_i;\n output usr_rx0_pma_loss_of_signal_o;\n input usr_rx0_pma_pll_rst_n_i;\n input usr_rx0_rst_n_i;\n input [3:0] usr_rx0_test_i;\n output [7:0] usr_rx0_test_o;\n output usr_rx1_busy_o;\n input usr_rx1_ctrl_align_en_i;\n input usr_rx1_ctrl_align_sync_i;\n output [7:0] usr_rx1_ctrl_char_is_a_o;\n output usr_rx1_ctrl_char_is_aligned_o;\n output [7:0] usr_rx1_ctrl_char_is_comma_o;\n output [7:0] usr_rx1_ctrl_char_is_f_o;\n output [7:0] usr_rx1_ctrl_char_is_k_o;\n input usr_rx1_ctrl_dec_en_i;\n output [7:0] usr_rx1_ctrl_disp_err_o;\n input usr_rx1_ctrl_dscr_en_i;\n input usr_rx1_ctrl_el_buff_fifo_en_i;\n input usr_rx1_ctrl_el_buff_rst_i;\n output [7:0] usr_rx1_ctrl_not_in_table_o;\n input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;\n input usr_rx1_ctrl_replace_en_i;\n output [63:0] usr_rx1_data_o;\n output usr_rx1_pll_lock_o;\n input usr_rx1_pma_cdr_rst_i;\n input usr_rx1_pma_ckgen_rst_n_i;\n output usr_rx1_pma_loss_of_signal_o;\n input usr_rx1_pma_pll_rst_n_i;\n input usr_rx1_rst_n_i;\n input [3:0] usr_rx1_test_i;\n output [7:0] usr_rx1_test_o;\n output usr_rx2_busy_o;\n input usr_rx2_ctrl_align_en_i;\n input usr_rx2_ctrl_align_sync_i;\n output [7:0] usr_rx2_ctrl_char_is_a_o;\n output usr_rx2_ctrl_char_is_aligned_o;\n output [7:0] usr_rx2_ctrl_char_is_comma_o;\n output [7:0] usr_rx2_ctrl_char_is_f_o;\n output [7:0] usr_rx2_ctrl_char_is_k_o;\n input usr_rx2_ctrl_dec_en_i;\n output [7:0] usr_rx2_ctrl_disp_err_o;\n input usr_rx2_ctrl_dscr_en_i;\n input usr_rx2_ctrl_el_buff_fifo_en_i;\n input usr_rx2_ctrl_el_buff_rst_i;\n output [7:0] usr_rx2_ctrl_not_in_table_o;\n input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;\n input usr_rx2_ctrl_replace_en_i;\n output [63:0] usr_rx2_data_o;\n output usr_rx2_pll_lock_o;\n input usr_rx2_pma_cdr_rst_i;\n input usr_rx2_pma_ckgen_rst_n_i;\n output usr_rx2_pma_loss_of_signal_o;\n input usr_rx2_pma_pll_rst_n_i;\n input usr_rx2_rst_n_i;\n input [3:0] usr_rx2_test_i;\n output [7:0] usr_rx2_test_o;\n output usr_rx3_busy_o;\n input usr_rx3_ctrl_align_en_i;\n input usr_rx3_ctrl_align_sync_i;\n output [7:0] usr_rx3_ctrl_char_is_a_o;\n output usr_rx3_ctrl_char_is_aligned_o;\n output [7:0] usr_rx3_ctrl_char_is_comma_o;\n output [7:0] usr_rx3_ctrl_char_is_f_o;\n output [7:0] usr_rx3_ctrl_char_is_k_o;\n input usr_rx3_ctrl_dec_en_i;\n output [7:0] usr_rx3_ctrl_disp_err_o;\n input usr_rx3_ctrl_dscr_en_i;\n input usr_rx3_ctrl_el_buff_fifo_en_i;\n input usr_rx3_ctrl_el_buff_rst_i;\n output [7:0] usr_rx3_ctrl_not_in_table_o;\n input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;\n input usr_rx3_ctrl_replace_en_i;\n output [63:0] usr_rx3_data_o;\n output usr_rx3_pll_lock_o;\n input usr_rx3_pma_cdr_rst_i;\n input usr_rx3_pma_ckgen_rst_n_i;\n output usr_rx3_pma_loss_of_signal_o;\n input usr_rx3_pma_pll_rst_n_i;\n input usr_rx3_rst_n_i;\n input [3:0] usr_rx3_test_i;\n output [7:0] usr_rx3_test_o;\n output usr_rx4_busy_o;\n input usr_rx4_ctrl_align_en_i;\n input usr_rx4_ctrl_align_sync_i;\n output [7:0] usr_rx4_ctrl_char_is_a_o;\n output usr_rx4_ctrl_char_is_aligned_o;\n output [7:0] usr_rx4_ctrl_char_is_comma_o;\n output [7:0] usr_rx4_ctrl_char_is_f_o;\n output [7:0] usr_rx4_ctrl_char_is_k_o;\n input usr_rx4_ctrl_dec_en_i;\n output [7:0] usr_rx4_ctrl_disp_err_o;\n input usr_rx4_ctrl_dscr_en_i;\n input usr_rx4_ctrl_el_buff_fifo_en_i;\n input usr_rx4_ctrl_el_buff_rst_i;\n output [7:0] usr_rx4_ctrl_not_in_table_o;\n input [1:0] usr_rx4_ctrl_ovs_bit_sel_i;\n input usr_rx4_ctrl_replace_en_i;\n output [63:0] usr_rx4_data_o;\n output usr_rx4_pll_lock_o;\n input usr_rx4_pma_cdr_rst_i;\n input usr_rx4_pma_ckgen_rst_n_i;\n output usr_rx4_pma_loss_of_signal_o;\n input usr_rx4_pma_pll_rst_n_i;\n input usr_rx4_rst_n_i;\n input [3:0] usr_rx4_test_i;\n output [7:0] usr_rx4_test_o;\n output usr_rx5_busy_o;\n input usr_rx5_ctrl_align_en_i;\n input usr_rx5_ctrl_align_sync_i;\n output [7:0] usr_rx5_ctrl_char_is_a_o;\n output usr_rx5_ctrl_char_is_aligned_o;\n output [7:0] usr_rx5_ctrl_char_is_comma_o;\n output [7:0] usr_rx5_ctrl_char_is_f_o;\n output [7:0] usr_rx5_ctrl_char_is_k_o;\n input usr_rx5_ctrl_dec_en_i;\n output [7:0] usr_rx5_ctrl_disp_err_o;\n input usr_rx5_ctrl_dscr_en_i;\n input usr_rx5_ctrl_el_buff_fifo_en_i;\n input usr_rx5_ctrl_el_buff_rst_i;\n output [7:0] usr_rx5_ctrl_not_in_table_o;\n input [1:0] usr_rx5_ctrl_ovs_bit_sel_i;\n input usr_rx5_ctrl_replace_en_i;\n output [63:0] usr_rx5_data_o;\n output usr_rx5_pll_lock_o;\n input usr_rx5_pma_cdr_rst_i;\n input usr_rx5_pma_ckgen_rst_n_i;\n output usr_rx5_pma_loss_of_signal_o;\n input usr_rx5_pma_pll_rst_n_i;\n input usr_rx5_rst_n_i;\n input [3:0] usr_rx5_test_i;\n output [7:0] usr_rx5_test_o;\n output usr_tx0_busy_o;\n input [7:0] usr_tx0_ctrl_char_is_k_i;\n input [7:0] usr_tx0_ctrl_enc_en_i;\n input [7:0] usr_tx0_ctrl_end_of_frame_i;\n input [7:0] usr_tx0_ctrl_end_of_multiframe_i;\n input usr_tx0_ctrl_replace_en_i;\n input [7:0] usr_tx0_ctrl_scr_en_i;\n input [63:0] usr_tx0_data_i;\n input usr_tx0_pma_clk_en_i;\n input usr_tx0_rst_n_i;\n input [3:0] usr_tx0_test_i;\n output [3:0] usr_tx0_test_o;\n output usr_tx1_busy_o;\n input [7:0] usr_tx1_ctrl_char_is_k_i;\n input [7:0] usr_tx1_ctrl_enc_en_i;\n input [7:0] usr_tx1_ctrl_end_of_frame_i;\n input [7:0] usr_tx1_ctrl_end_of_multiframe_i;\n input usr_tx1_ctrl_replace_en_i;\n input [7:0] usr_tx1_ctrl_scr_en_i;\n input [63:0] usr_tx1_data_i;\n input usr_tx1_pma_clk_en_i;\n input usr_tx1_rst_n_i;\n input [3:0] usr_tx1_test_i;\n output [3:0] usr_tx1_test_o;\n output usr_tx2_busy_o;\n input [7:0] usr_tx2_ctrl_char_is_k_i;\n input [7:0] usr_tx2_ctrl_enc_en_i;\n input [7:0] usr_tx2_ctrl_end_of_frame_i;\n input [7:0] usr_tx2_ctrl_end_of_multiframe_i;\n input usr_tx2_ctrl_replace_en_i;\n input [7:0] usr_tx2_ctrl_scr_en_i;\n input [63:0] usr_tx2_data_i;\n input usr_tx2_pma_clk_en_i;\n input usr_tx2_rst_n_i;\n input [3:0] usr_tx2_test_i;\n output [3:0] usr_tx2_test_o;\n output usr_tx3_busy_o;\n input [7:0] usr_tx3_ctrl_char_is_k_i;\n input [7:0] usr_tx3_ctrl_enc_en_i;\n input [7:0] usr_tx3_ctrl_end_of_frame_i;\n input [7:0] usr_tx3_ctrl_end_of_multiframe_i;\n input usr_tx3_ctrl_replace_en_i;\n input [7:0] usr_tx3_ctrl_scr_en_i;\n input [63:0] usr_tx3_data_i;\n input usr_tx3_pma_clk_en_i;\n input usr_tx3_rst_n_i;\n input [3:0] usr_tx3_test_i;\n output [3:0] usr_tx3_test_o;\n output usr_tx4_busy_o;\n input [7:0] usr_tx4_ctrl_char_is_k_i;\n input [7:0] usr_tx4_ctrl_enc_en_i;\n input [7:0] usr_tx4_ctrl_end_of_frame_i;\n input [7:0] usr_tx4_ctrl_end_of_multiframe_i;\n input usr_tx4_ctrl_replace_en_i;\n input [7:0] usr_tx4_ctrl_scr_en_i;\n input [63:0] usr_tx4_data_i;\n input usr_tx4_pma_clk_en_i;\n input usr_tx4_rst_n_i;\n input [3:0] usr_tx4_test_i;\n output [3:0] usr_tx4_test_o;\n output usr_tx5_busy_o;\n input [7:0] usr_tx5_ctrl_char_is_k_i;\n input [7:0] usr_tx5_ctrl_enc_en_i;\n input [7:0] usr_tx5_ctrl_end_of_frame_i;\n input [7:0] usr_tx5_ctrl_end_of_multiframe_i;\n input usr_tx5_ctrl_replace_en_i;\n input [7:0] usr_tx5_ctrl_scr_en_i;\n input [63:0] usr_tx5_data_i;\n input usr_tx5_pma_clk_en_i;\n input usr_tx5_rst_n_i;\n input [3:0] usr_tx5_test_i;\n output [3:0] usr_tx5_test_o;\n parameter cfg_main_i = 34'b0000000000000000000000000000000000;\n parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;\n parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;\n parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;\n parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;\n parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;\n parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;\n parameter cfg_tx0_i = 0;\n parameter cfg_tx1_i = 0;\n parameter cfg_tx2_i = 0;\n parameter cfg_tx3_i = 0;\n parameter cfg_tx4_i = 0;\n parameter cfg_tx5_i = 0;\n parameter location = \"\";\nendmodule\n",
310
+ "cells_wrap_m.v": "module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO , CZO);\n input [23:0] A;\n input [17:0] B;\n input [35:0] C;\n input [17:0] CAI;\n output [17:0] CAO;\n input [17:0] CBI;\n output [17:0] CBO;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO;\n output CO36;\n output CO48;\n input [55:0] CZI;\n output [55:0] CZO;\n input [17:0] D;\n output OVF;\n input R;\n input RZ;\n input WE;\n output [55:0] Z;\n parameter ALU_DYNAMIC_OP = 1'b0;\n parameter ALU_MUX = 1'b0;\n parameter ALU_OP = 6'b000000;\n parameter CO_SEL = 1'b0;\n parameter ENABLE_PR_ALU_RST = 1'b0;\n parameter ENABLE_PR_A_RST = 1'b0;\n parameter ENABLE_PR_B_RST = 1'b0;\n parameter ENABLE_PR_CI_RST = 1'b0;\n parameter ENABLE_PR_CO_RST = 1'b0;\n parameter ENABLE_PR_C_RST = 1'b0;\n parameter ENABLE_PR_D_RST = 1'b0;\n parameter ENABLE_PR_MULT_RST = 1'b0;\n parameter ENABLE_PR_OV_RST = 1'b0;\n parameter ENABLE_PR_P_RST = 1'b0;\n parameter ENABLE_PR_X_RST = 1'b0;\n parameter ENABLE_PR_Y_RST = 1'b0;\n parameter ENABLE_PR_Z_RST = 1'b0;\n parameter ENABLE_SATURATION = 1'b0;\n parameter MUX_A = 1'b0;\n parameter MUX_B = 1'b0;\n parameter MUX_CI = 1'b0;\n parameter MUX_P = 1'b0;\n parameter MUX_X = 2'b00;\n parameter MUX_Y = 1'b0;\n parameter MUX_Z = 1'b0;\n parameter PRE_ADDER_OP = 1'b0;\n parameter PR_ALU_MUX = 1'b0;\n parameter PR_A_CASCADE_MUX = 2'b00;\n parameter PR_A_MUX = 2'b00;\n parameter PR_B_CASCADE_MUX = 2'b00;\n parameter PR_B_MUX = 2'b00;\n parameter PR_CI_MUX = 1'b0;\n parameter PR_CO_MUX = 1'b0;\n parameter PR_C_MUX = 1'b0;\n parameter PR_D_MUX = 1'b0;\n parameter PR_MULT_MUX = 1'b0;\n parameter PR_OV_MUX = 1'b0;\n parameter PR_P_MUX = 1'b0;\n parameter PR_X_MUX = 1'b0;\n parameter PR_Y_MUX = 1'b0;\n parameter PR_Z_MUX = 1'b0;\n parameter SATURATION_RANK = 6'b000000;\n parameter SIGNED_MODE = 1'b0;\n parameter Z_FEEDBACK_SHL12 = 1'b0;\n\nlocalparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z,\n MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };\n\nlocalparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX,\n PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };\n\nlocalparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST,\n ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,\n ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };\n\nlocalparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP };\n\n NX_DSP #(\n .std_mode(\"\"),\n .raw_config0(RAW_CONFIG0_GEN),\n .raw_config1(RAW_CONFIG1_GEN),\n .raw_config2(RAW_CONFIG2_GEN),\n .raw_config3(RAW_CONFIG3_GEN),\n ) _TECHMAP_REPLACE_ (\n .A1(A[0]),\n .A2(A[1]),\n .A3(A[2]),\n .A4(A[3]),\n .A5(A[4]),\n .A6(A[5]),\n .A7(A[6]),\n .A8(A[7]),\n .A9(A[8]),\n .A10(A[9]),\n .A11(A[10]),\n .A12(A[11]),\n .A13(A[12]),\n .A14(A[13]),\n .A15(A[14]),\n .A16(A[15]),\n .A17(A[16]),\n .A18(A[17]),\n .A19(A[18]),\n .A20(A[19]),\n .A21(A[20]),\n .A22(A[21]),\n .A23(A[22]),\n .A24(A[23]),\n\n .B1(B[0]),\n .B2(B[1]),\n .B3(B[2]),\n .B4(B[3]),\n .B5(B[4]),\n .B6(B[5]),\n .B7(B[6]),\n .B8(B[7]),\n .B9(B[8]),\n .B10(B[9]),\n .B11(B[10]),\n .B12(B[11]),\n .B13(B[12]),\n .B14(B[13]),\n .B15(B[14]),\n .B16(B[15]),\n .B17(B[16]),\n .B18(B[17]),\n\n .C1(C[0]),\n .C2(C[1]),\n .C3(C[2]),\n .C4(C[3]),\n .C5(C[4]),\n .C6(C[5]),\n .C7(C[6]),\n .C8(C[7]),\n .C9(C[8]),\n .C10(C[9]),\n .C11(C[10]),\n .C12(C[11]),\n .C13(C[12]),\n .C14(C[13]),\n .C15(C[14]),\n .C16(C[15]),\n .C17(C[16]),\n .C18(C[17]),\n .C19(C[18]),\n .C20(C[19]),\n .C21(C[20]),\n .C22(C[21]),\n .C23(C[22]),\n .C24(C[23]),\n .C25(C[24]),\n .C26(C[25]),\n .C27(C[26]),\n .C28(C[27]),\n .C29(C[28]),\n .C30(C[29]),\n .C31(C[30]),\n .C32(C[31]),\n .C33(C[32]),\n .C34(C[33]),\n .C35(C[34]),\n .C36(C[35]),\n\n .CAI1(CAI[0]),\n .CAI2(CAI[1]),\n .CAI3(CAI[2]),\n .CAI4(CAI[3]),\n .CAI5(CAI[4]),\n .CAI6(CAI[5]),\n .CAI7(CAI[6]),\n .CAI8(CAI[7]),\n .CAI9(CAI[8]),\n .CAI10(CAI[9]),\n .CAI11(CAI[10]),\n .CAI12(CAI[11]),\n .CAI13(CAI[12]),\n .CAI14(CAI[13]),\n .CAI15(CAI[14]),\n .CAI16(CAI[15]),\n .CAI17(CAI[16]),\n .CAI18(CAI[17]),\n\n .CAO1(CAO[0]),\n .CAO2(CAO[1]),\n .CAO3(CAO[2]),\n .CAO4(CAO[3]),\n .CAO5(CAO[4]),\n .CAO6(CAO[5]),\n .CAO7(CAO[6]),\n .CAO8(CAO[7]),\n .CAO9(CAO[8]),\n .CAO10(CAO[9]),\n .CAO11(CAO[10]),\n .CAO12(CAO[11]),\n .CAO13(CAO[12]),\n .CAO14(CAO[13]),\n .CAO15(CAO[14]),\n .CAO16(CAO[15]),\n .CAO17(CAO[16]),\n .CAO18(CAO[17]),\n\n .CBI1(CBI[0]),\n .CBI2(CBI[1]),\n .CBI3(CBI[2]),\n .CBI4(CBI[3]),\n .CBI5(CBI[4]),\n .CBI6(CBI[5]),\n .CBI7(CBI[6]),\n .CBI8(CBI[7]),\n .CBI9(CBI[8]),\n .CBI10(CBI[9]),\n .CBI11(CBI[10]),\n .CBI12(CBI[11]),\n .CBI13(CBI[12]),\n .CBI14(CBI[13]),\n .CBI15(CBI[14]),\n .CBI16(CBI[15]),\n .CBI17(CBI[16]),\n .CBI18(CBI[17]),\n\n .CBO1(CBO[0]),\n .CBO2(CBO[1]),\n .CBO3(CBO[2]),\n .CBO4(CBO[3]),\n .CBO5(CBO[4]),\n .CBO6(CBO[5]),\n .CBO7(CBO[6]),\n .CBO8(CBO[7]),\n .CBO9(CBO[8]),\n .CBO10(CBO[9]),\n .CBO11(CBO[10]),\n .CBO12(CBO[11]),\n .CBO13(CBO[12]),\n .CBO14(CBO[13]),\n .CBO15(CBO[14]),\n .CBO16(CBO[15]),\n .CBO17(CBO[16]),\n .CBO18(CBO[17]),\n\n .CCI(CCI),\n .CCO(CCO),\n .CI(CI),\n .CK(CK),\n .CO(CO),\n .CO37(CO36),\n .CO49(CO48),\n\n .CZI1(CZI[0]),\n .CZI2(CZI[1]),\n .CZI3(CZI[2]),\n .CZI4(CZI[3]),\n .CZI5(CZI[4]),\n .CZI6(CZI[5]),\n .CZI7(CZI[6]),\n .CZI8(CZI[7]),\n .CZI9(CZI[8]),\n .CZI10(CZI[9]),\n .CZI11(CZI[10]),\n .CZI12(CZI[11]),\n .CZI13(CZI[12]),\n .CZI14(CZI[13]),\n .CZI15(CZI[14]),\n .CZI16(CZI[15]),\n .CZI17(CZI[16]),\n .CZI18(CZI[17]),\n .CZI19(CZI[18]),\n .CZI20(CZI[19]),\n .CZI21(CZI[20]),\n .CZI22(CZI[21]),\n .CZI23(CZI[22]),\n .CZI24(CZI[23]),\n .CZI25(CZI[24]),\n .CZI26(CZI[25]),\n .CZI27(CZI[26]),\n .CZI28(CZI[27]),\n .CZI29(CZI[28]),\n .CZI30(CZI[29]),\n .CZI31(CZI[30]),\n .CZI32(CZI[31]),\n .CZI33(CZI[32]),\n .CZI34(CZI[33]),\n .CZI35(CZI[34]),\n .CZI36(CZI[35]),\n .CZI37(CZI[36]),\n .CZI38(CZI[37]),\n .CZI39(CZI[38]),\n .CZI40(CZI[39]),\n .CZI41(CZI[40]),\n .CZI42(CZI[41]),\n .CZI43(CZI[42]),\n .CZI44(CZI[43]),\n .CZI45(CZI[44]),\n .CZI46(CZI[45]),\n .CZI47(CZI[46]),\n .CZI48(CZI[47]),\n .CZI49(CZI[48]),\n .CZI50(CZI[49]),\n .CZI51(CZI[50]),\n .CZI52(CZI[51]),\n .CZI53(CZI[52]),\n .CZI54(CZI[53]),\n .CZI55(CZI[54]),\n .CZI56(CZI[55]),\n\n .CZO1(CZO[0]),\n .CZO2(CZO[1]),\n .CZO3(CZO[2]),\n .CZO4(CZO[3]),\n .CZO5(CZO[4]),\n .CZO6(CZO[5]),\n .CZO7(CZO[6]),\n .CZO8(CZO[7]),\n .CZO9(CZO[8]),\n .CZO10(CZO[9]),\n .CZO11(CZO[10]),\n .CZO12(CZO[11]),\n .CZO13(CZO[12]),\n .CZO14(CZO[13]),\n .CZO15(CZO[14]),\n .CZO16(CZO[15]),\n .CZO17(CZO[16]),\n .CZO18(CZO[17]),\n .CZO19(CZO[18]),\n .CZO20(CZO[19]),\n .CZO21(CZO[20]),\n .CZO22(CZO[21]),\n .CZO23(CZO[22]),\n .CZO24(CZO[23]),\n .CZO25(CZO[24]),\n .CZO26(CZO[25]),\n .CZO27(CZO[26]),\n .CZO28(CZO[27]),\n .CZO29(CZO[28]),\n .CZO30(CZO[29]),\n .CZO31(CZO[30]),\n .CZO32(CZO[31]),\n .CZO33(CZO[32]),\n .CZO34(CZO[33]),\n .CZO35(CZO[34]),\n .CZO36(CZO[35]),\n .CZO37(CZO[36]),\n .CZO38(CZO[37]),\n .CZO39(CZO[38]),\n .CZO40(CZO[39]),\n .CZO41(CZO[40]),\n .CZO42(CZO[41]),\n .CZO43(CZO[42]),\n .CZO44(CZO[43]),\n .CZO45(CZO[44]),\n .CZO46(CZO[45]),\n .CZO47(CZO[46]),\n .CZO48(CZO[47]),\n .CZO49(CZO[48]),\n .CZO50(CZO[49]),\n .CZO51(CZO[50]),\n .CZO52(CZO[51]),\n .CZO53(CZO[52]),\n .CZO54(CZO[53]),\n .CZO55(CZO[54]),\n .CZO56(CZO[55]),\n\n .D1(D[0]),\n .D2(D[1]),\n .D3(D[2]),\n .D4(D[3]),\n .D5(D[4]),\n .D6(D[5]),\n .D7(D[6]),\n .D8(D[7]),\n .D9(D[8]),\n .D10(D[9]),\n .D11(D[10]),\n .D12(D[11]),\n .D13(D[12]),\n .D14(D[13]),\n .D15(D[14]),\n .D16(D[15]),\n .D17(D[16]),\n .D18(D[17]),\n\n .OVF(OVF),\n .R(R),\n .RZ(RZ),\n .WE(WE),\n\n .Z1(Z[0]),\n .Z2(Z[1]),\n .Z3(Z[2]),\n .Z4(Z[3]),\n .Z5(Z[4]),\n .Z6(Z[5]),\n .Z7(Z[6]),\n .Z8(Z[7]),\n .Z9(Z[8]),\n .Z10(Z[9]),\n .Z11(Z[10]),\n .Z12(Z[11]),\n .Z13(Z[12]),\n .Z14(Z[13]),\n .Z15(Z[14]),\n .Z16(Z[15]),\n .Z17(Z[16]),\n .Z18(Z[17]),\n .Z19(Z[18]),\n .Z20(Z[19]),\n .Z21(Z[20]),\n .Z22(Z[21]),\n .Z23(Z[22]),\n .Z24(Z[23]),\n .Z25(Z[24]),\n .Z26(Z[25]),\n .Z27(Z[26]),\n .Z28(Z[27]),\n .Z29(Z[28]),\n .Z30(Z[29]),\n .Z31(Z[30]),\n .Z32(Z[31]),\n .Z33(Z[32]),\n .Z34(Z[33]),\n .Z35(Z[34]),\n .Z36(Z[35]),\n .Z37(Z[36]),\n .Z38(Z[37]),\n .Z39(Z[38]),\n .Z40(Z[39]),\n .Z41(Z[40]),\n .Z42(Z[41]),\n .Z43(Z[42]),\n .Z44(Z[43]),\n .Z45(Z[44]),\n .Z46(Z[45]),\n .Z47(Z[46]),\n .Z48(Z[47]),\n .Z49(Z[48]),\n .Z50(Z[49]),\n .Z51(Z[50]),\n .Z52(Z[51]),\n .Z53(Z[52]),\n .Z54(Z[53]),\n .Z55(Z[54]),\n .Z56(Z[55])\n );\nendmodule\n\nmodule NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO\n, CZO);\n input [23:0] A;\n input [17:0] B;\n input [35:0] C;\n input [17:0] CAI;\n output [17:0] CAO;\n input [17:0] CBI;\n output [17:0] CBO;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO;\n output CO37;\n output CO49;\n input [55:0] CZI;\n output [55:0] CZO;\n input [17:0] D;\n output OVF;\n input R;\n input RZ;\n input WE;\n output [55:0] Z;\n parameter raw_config0 = 20'b00000000000000000000;\n parameter raw_config1 = 19'b0000000000000000000;\n parameter raw_config2 = 13'b0000000000000;\n parameter raw_config3 = 7'b0000000;\n parameter std_mode = \"\";\n\n NX_DSP #(\n .std_mode(std_mode),\n .raw_config0(raw_config0),\n .raw_config1(raw_config1),\n .raw_config2(raw_config2),\n .raw_config3(raw_config3),\n ) _TECHMAP_REPLACE_ (\n .A1(A[0]),\n .A2(A[1]),\n .A3(A[2]),\n .A4(A[3]),\n .A5(A[4]),\n .A6(A[5]),\n .A7(A[6]),\n .A8(A[7]),\n .A9(A[8]),\n .A10(A[9]),\n .A11(A[10]),\n .A12(A[11]),\n .A13(A[12]),\n .A14(A[13]),\n .A15(A[14]),\n .A16(A[15]),\n .A17(A[16]),\n .A18(A[17]),\n .A19(A[18]),\n .A20(A[19]),\n .A21(A[20]),\n .A22(A[21]),\n .A23(A[22]),\n .A24(A[23]),\n\n .B1(B[0]),\n .B2(B[1]),\n .B3(B[2]),\n .B4(B[3]),\n .B5(B[4]),\n .B6(B[5]),\n .B7(B[6]),\n .B8(B[7]),\n .B9(B[8]),\n .B10(B[9]),\n .B11(B[10]),\n .B12(B[11]),\n .B13(B[12]),\n .B14(B[13]),\n .B15(B[14]),\n .B16(B[15]),\n .B17(B[16]),\n .B18(B[17]),\n\n .C1(C[0]),\n .C2(C[1]),\n .C3(C[2]),\n .C4(C[3]),\n .C5(C[4]),\n .C6(C[5]),\n .C7(C[6]),\n .C8(C[7]),\n .C9(C[8]),\n .C10(C[9]),\n .C11(C[10]),\n .C12(C[11]),\n .C13(C[12]),\n .C14(C[13]),\n .C15(C[14]),\n .C16(C[15]),\n .C17(C[16]),\n .C18(C[17]),\n .C19(C[18]),\n .C20(C[19]),\n .C21(C[20]),\n .C22(C[21]),\n .C23(C[22]),\n .C24(C[23]),\n .C25(C[24]),\n .C26(C[25]),\n .C27(C[26]),\n .C28(C[27]),\n .C29(C[28]),\n .C30(C[29]),\n .C31(C[30]),\n .C32(C[31]),\n .C33(C[32]),\n .C34(C[33]),\n .C35(C[34]),\n .C36(C[35]),\n\n .CAI1(CAI[0]),\n .CAI2(CAI[1]),\n .CAI3(CAI[2]),\n .CAI4(CAI[3]),\n .CAI5(CAI[4]),\n .CAI6(CAI[5]),\n .CAI7(CAI[6]),\n .CAI8(CAI[7]),\n .CAI9(CAI[8]),\n .CAI10(CAI[9]),\n .CAI11(CAI[10]),\n .CAI12(CAI[11]),\n .CAI13(CAI[12]),\n .CAI14(CAI[13]),\n .CAI15(CAI[14]),\n .CAI16(CAI[15]),\n .CAI17(CAI[16]),\n .CAI18(CAI[17]),\n\n .CAO1(CAO[0]),\n .CAO2(CAO[1]),\n .CAO3(CAO[2]),\n .CAO4(CAO[3]),\n .CAO5(CAO[4]),\n .CAO6(CAO[5]),\n .CAO7(CAO[6]),\n .CAO8(CAO[7]),\n .CAO9(CAO[8]),\n .CAO10(CAO[9]),\n .CAO11(CAO[10]),\n .CAO12(CAO[11]),\n .CAO13(CAO[12]),\n .CAO14(CAO[13]),\n .CAO15(CAO[14]),\n .CAO16(CAO[15]),\n .CAO17(CAO[16]),\n .CAO18(CAO[17]),\n\n .CBI1(CBI[0]),\n .CBI2(CBI[1]),\n .CBI3(CBI[2]),\n .CBI4(CBI[3]),\n .CBI5(CBI[4]),\n .CBI6(CBI[5]),\n .CBI7(CBI[6]),\n .CBI8(CBI[7]),\n .CBI9(CBI[8]),\n .CBI10(CBI[9]),\n .CBI11(CBI[10]),\n .CBI12(CBI[11]),\n .CBI13(CBI[12]),\n .CBI14(CBI[13]),\n .CBI15(CBI[14]),\n .CBI16(CBI[15]),\n .CBI17(CBI[16]),\n .CBI18(CBI[17]),\n\n .CBO1(CBO[0]),\n .CBO2(CBO[1]),\n .CBO3(CBO[2]),\n .CBO4(CBO[3]),\n .CBO5(CBO[4]),\n .CBO6(CBO[5]),\n .CBO7(CBO[6]),\n .CBO8(CBO[7]),\n .CBO9(CBO[8]),\n .CBO10(CBO[9]),\n .CBO11(CBO[10]),\n .CBO12(CBO[11]),\n .CBO13(CBO[12]),\n .CBO14(CBO[13]),\n .CBO15(CBO[14]),\n .CBO16(CBO[15]),\n .CBO17(CBO[16]),\n .CBO18(CBO[17]),\n\n .CCI(CCI),\n .CCO(CCO),\n .CI(CI),\n .CK(CK),\n .CO(CO),\n .CO37(CO37),\n .CO49(CO49),\n\n .CZI1(CZI[0]),\n .CZI2(CZI[1]),\n .CZI3(CZI[2]),\n .CZI4(CZI[3]),\n .CZI5(CZI[4]),\n .CZI6(CZI[5]),\n .CZI7(CZI[6]),\n .CZI8(CZI[7]),\n .CZI9(CZI[8]),\n .CZI10(CZI[9]),\n .CZI11(CZI[10]),\n .CZI12(CZI[11]),\n .CZI13(CZI[12]),\n .CZI14(CZI[13]),\n .CZI15(CZI[14]),\n .CZI16(CZI[15]),\n .CZI17(CZI[16]),\n .CZI18(CZI[17]),\n .CZI19(CZI[18]),\n .CZI20(CZI[19]),\n .CZI21(CZI[20]),\n .CZI22(CZI[21]),\n .CZI23(CZI[22]),\n .CZI24(CZI[23]),\n .CZI25(CZI[24]),\n .CZI26(CZI[25]),\n .CZI27(CZI[26]),\n .CZI28(CZI[27]),\n .CZI29(CZI[28]),\n .CZI30(CZI[29]),\n .CZI31(CZI[30]),\n .CZI32(CZI[31]),\n .CZI33(CZI[32]),\n .CZI34(CZI[33]),\n .CZI35(CZI[34]),\n .CZI36(CZI[35]),\n .CZI37(CZI[36]),\n .CZI38(CZI[37]),\n .CZI39(CZI[38]),\n .CZI40(CZI[39]),\n .CZI41(CZI[40]),\n .CZI42(CZI[41]),\n .CZI43(CZI[42]),\n .CZI44(CZI[43]),\n .CZI45(CZI[44]),\n .CZI46(CZI[45]),\n .CZI47(CZI[46]),\n .CZI48(CZI[47]),\n .CZI49(CZI[48]),\n .CZI50(CZI[49]),\n .CZI51(CZI[50]),\n .CZI52(CZI[51]),\n .CZI53(CZI[52]),\n .CZI54(CZI[53]),\n .CZI55(CZI[54]),\n .CZI56(CZI[55]),\n\n .CZO1(CZO[0]),\n .CZO2(CZO[1]),\n .CZO3(CZO[2]),\n .CZO4(CZO[3]),\n .CZO5(CZO[4]),\n .CZO6(CZO[5]),\n .CZO7(CZO[6]),\n .CZO8(CZO[7]),\n .CZO9(CZO[8]),\n .CZO10(CZO[9]),\n .CZO11(CZO[10]),\n .CZO12(CZO[11]),\n .CZO13(CZO[12]),\n .CZO14(CZO[13]),\n .CZO15(CZO[14]),\n .CZO16(CZO[15]),\n .CZO17(CZO[16]),\n .CZO18(CZO[17]),\n .CZO19(CZO[18]),\n .CZO20(CZO[19]),\n .CZO21(CZO[20]),\n .CZO22(CZO[21]),\n .CZO23(CZO[22]),\n .CZO24(CZO[23]),\n .CZO25(CZO[24]),\n .CZO26(CZO[25]),\n .CZO27(CZO[26]),\n .CZO28(CZO[27]),\n .CZO29(CZO[28]),\n .CZO30(CZO[29]),\n .CZO31(CZO[30]),\n .CZO32(CZO[31]),\n .CZO33(CZO[32]),\n .CZO34(CZO[33]),\n .CZO35(CZO[34]),\n .CZO36(CZO[35]),\n .CZO37(CZO[36]),\n .CZO38(CZO[37]),\n .CZO39(CZO[38]),\n .CZO40(CZO[39]),\n .CZO41(CZO[40]),\n .CZO42(CZO[41]),\n .CZO43(CZO[42]),\n .CZO44(CZO[43]),\n .CZO45(CZO[44]),\n .CZO46(CZO[45]),\n .CZO47(CZO[46]),\n .CZO48(CZO[47]),\n .CZO49(CZO[48]),\n .CZO50(CZO[49]),\n .CZO51(CZO[50]),\n .CZO52(CZO[51]),\n .CZO53(CZO[52]),\n .CZO54(CZO[53]),\n .CZO55(CZO[54]),\n .CZO56(CZO[55]),\n\n .D1(D[0]),\n .D2(D[1]),\n .D3(D[2]),\n .D4(D[3]),\n .D5(D[4]),\n .D6(D[5]),\n .D7(D[6]),\n .D8(D[7]),\n .D9(D[8]),\n .D10(D[9]),\n .D11(D[10]),\n .D12(D[11]),\n .D13(D[12]),\n .D14(D[13]),\n .D15(D[14]),\n .D16(D[15]),\n .D17(D[16]),\n .D18(D[17]),\n\n .OVF(OVF),\n .R(R),\n .RZ(RZ),\n .WE(WE),\n\n .Z1(Z[0]),\n .Z2(Z[1]),\n .Z3(Z[2]),\n .Z4(Z[3]),\n .Z5(Z[4]),\n .Z6(Z[5]),\n .Z7(Z[6]),\n .Z8(Z[7]),\n .Z9(Z[8]),\n .Z10(Z[9]),\n .Z11(Z[10]),\n .Z12(Z[11]),\n .Z13(Z[12]),\n .Z14(Z[13]),\n .Z15(Z[14]),\n .Z16(Z[15]),\n .Z17(Z[16]),\n .Z18(Z[17]),\n .Z19(Z[18]),\n .Z20(Z[19]),\n .Z21(Z[20]),\n .Z22(Z[21]),\n .Z23(Z[22]),\n .Z24(Z[23]),\n .Z25(Z[24]),\n .Z26(Z[25]),\n .Z27(Z[26]),\n .Z28(Z[27]),\n .Z29(Z[28]),\n .Z30(Z[29]),\n .Z31(Z[30]),\n .Z32(Z[31]),\n .Z33(Z[32]),\n .Z34(Z[33]),\n .Z35(Z[34]),\n .Z36(Z[35]),\n .Z37(Z[36]),\n .Z38(Z[37]),\n .Z39(Z[38]),\n .Z40(Z[39]),\n .Z41(Z[40]),\n .Z42(Z[41]),\n .Z43(Z[42]),\n .Z44(Z[43]),\n .Z45(Z[44]),\n .Z46(Z[45]),\n .Z47(Z[46]),\n .Z48(Z[47]),\n .Z49(Z[48]),\n .Z50(Z[49]),\n .Z51(Z[50]),\n .Z52(Z[51]),\n .Z53(Z[52]),\n .Z54(Z[53]),\n .Z55(Z[54]),\n .Z56(Z[55])\n );\nendmodule\n\nmodule NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);\n output COR;\n output ERR;\n input [15:0] I;\n output [15:0] O;\n input [5:0] RA;\n input RCK;\n input RE;\n input [5:0] WA;\n input WCK;\n input WE;\n parameter mem_ctxt = \"\";\n parameter rck_edge = 1'b0;\n parameter wck_edge = 1'b0;\n\n NX_RFB_M #(\n .mem_ctxt(mem_ctxt),\n .rck_edge(rck_edge),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .RCK(RCK),\n .WCK(WCK),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .COR(COR),\n .ERR(ERR),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .RA1(RA[0]),\n .RA2(RA[1]),\n .RA3(RA[2]),\n .RA4(RA[3]),\n .RA5(RA[4]),\n .RA6(RA[5]),\n .RE(RE),\n .WA1(WA[0]),\n .WA2(WA[1]),\n .WA3(WA[2]),\n .WA4(WA[3]),\n .WA5(WA[4]),\n .WA6(WA[5]),\n .WE(WE)\n );\nendmodule\n\nmodule NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1\n, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6\n, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);\n output COR;\n output ERR;\n input I1;\n input I10;\n input I11;\n input I12;\n input I13;\n input I14;\n input I15;\n input I16;\n input I2;\n input I3;\n input I4;\n input I5;\n input I6;\n input I7;\n input I8;\n input I9;\n output O1;\n output O10;\n output O11;\n output O12;\n output O13;\n output O14;\n output O15;\n output O16;\n output O2;\n output O3;\n output O4;\n output O5;\n output O6;\n output O7;\n output O8;\n output O9;\n input RA1;\n input RA2;\n input RA3;\n input RA4;\n input RA5;\n input RA6;\n input RCK;\n input RE;\n input WA1;\n input WA2;\n input WA3;\n input WA4;\n input WA5;\n input WA6;\n input WCK;\n input WE;\n parameter addr_mask = 5'b00000;\n parameter mem_ctxt = \"\";\n parameter rck_edge = 1'b0;\n parameter wck_edge = 1'b0;\n parameter we_mask = 1'b0;\n parameter wea_mask = 1'b0;\n\n NX_RFB_M #(\n .mem_ctxt(mem_ctxt),\n .rck_edge(rck_edge),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .RCK(RCK),\n .WCK(WCK),\n .I1(I1),\n .I2(I2),\n .I3(I3),\n .I4(I4),\n .I5(I5),\n .I6(I6),\n .I7(I7),\n .I8(I8),\n .I9(I9),\n .I10(I10),\n .I11(I11),\n .I12(I12),\n .I13(I13),\n .I14(I14),\n .I15(I15),\n .I16(I16),\n .COR(COR),\n .ERR(ERR),\n .O1(O1),\n .O2(O2),\n .O3(O3),\n .O4(O4),\n .O5(O5),\n .O6(O6),\n .O7(O7),\n .O8(O8),\n .O9(O9),\n .O10(O10),\n .O11(O11),\n .O12(O12),\n .O13(O13),\n .O14(O14),\n .O15(O15),\n .O16(O16),\n .RA1(RA1),\n .RA2(RA2),\n .RA3(RA3),\n .RA4(RA4),\n .RA5(RA5),\n .RA6(RA6),\n .RE(RE),\n .WA1(WA1),\n .WA2(WA2),\n .WA3(WA3),\n .WA4(WA4),\n .WA5(WA5),\n .WA6(WA6),\n .WE(WE)\n );\nendmodule\n\nmodule NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3\n, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3\n, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1\n, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1\n, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16\n, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);\n output C1RED;\n input C1RNE;\n input C1RS;\n input C1RW1;\n input C1RW2;\n input C1RW3;\n input C1TS;\n input C1TW;\n output C2RED;\n input C2RNE;\n input C2RS;\n input C2RW1;\n input C2RW2;\n input C2RW3;\n input C2TS;\n input C2TW;\n input CAD1;\n input CAD2;\n input CAD3;\n input CAD4;\n input CAD5;\n input CAD6;\n output CAL;\n input CAN1;\n input CAN2;\n input CAN3;\n input CAN4;\n input CAP1;\n input CAP2;\n input CAP3;\n input CAP4;\n input CAT1;\n input CAT2;\n input CAT3;\n input CAT4;\n input CCK;\n output CKO1;\n output CKO2;\n input CTCK;\n input DC;\n input DCK;\n input DIG;\n input DIS;\n input DOG;\n input DOS;\n input DPAG;\n input DPAS;\n input DQSG;\n input DQSS;\n input DRA1;\n input DRA2;\n input DRA3;\n input DRA4;\n input DRA5;\n input DRA6;\n input DRI1;\n input DRI2;\n input DRI3;\n input DRI4;\n input DRI5;\n input DRI6;\n input DRL;\n output DRO1;\n output DRO2;\n output DRO3;\n output DRO4;\n output DRO5;\n output DRO6;\n input DS1;\n input DS2;\n input FA1;\n input FA2;\n input FA3;\n input FA4;\n input FA5;\n input FA6;\n output FLD;\n output FLG;\n input FZ;\n inout [41:0] LINK1;\n inout [41:0] LINK10;\n inout [41:0] LINK11;\n inout [41:0] LINK12;\n inout [41:0] LINK13;\n inout [41:0] LINK14;\n inout [41:0] LINK15;\n inout [41:0] LINK16;\n inout [41:0] LINK17;\n inout [41:0] LINK18;\n inout [41:0] LINK19;\n inout [41:0] LINK2;\n inout [41:0] LINK20;\n inout [41:0] LINK21;\n inout [41:0] LINK22;\n inout [41:0] LINK23;\n inout [41:0] LINK24;\n inout [41:0] LINK25;\n inout [41:0] LINK26;\n inout [41:0] LINK27;\n inout [41:0] LINK28;\n inout [41:0] LINK29;\n inout [41:0] LINK3;\n inout [41:0] LINK30;\n inout [41:0] LINK31;\n inout [41:0] LINK32;\n inout [41:0] LINK33;\n inout [41:0] LINK34;\n inout [41:0] LINK4;\n inout [41:0] LINK5;\n inout [41:0] LINK6;\n inout [41:0] LINK7;\n inout [41:0] LINK8;\n inout [41:0] LINK9;\n input RRCK1;\n input RRCK2;\n input RTCK1;\n input RTCK2;\n input SPI1;\n input SPI2;\n input SPI3;\n input WRCK1;\n input WRCK2;\n input WTCK1;\n input WTCK2;\n parameter div_rx1 = 4'b0000;\n parameter div_rx2 = 4'b0000;\n parameter div_tx1 = 4'b0000;\n parameter div_tx2 = 4'b0000;\n parameter inv_di_fclk1 = 1'b0;\n parameter inv_di_fclk2 = 1'b0;\n parameter latency1 = 1'b0;\n parameter latency2 = 1'b0;\n parameter location = \"\";\n parameter mode_cpath = \"\";\n parameter mode_epath = \"\";\n parameter mode_io_cal = 1'b0;\n parameter mode_rpath = \"\";\n parameter mode_side1 = 0;\n parameter mode_side2 = 0;\n parameter mode_tpath = \"\";\n parameter sel_clk_out1 = 1'b0;\n parameter sel_clk_out2 = 1'b0;\n parameter sel_clkr_rx1 = 1'b0;\n parameter sel_clkr_rx2 = 1'b0;\n parameter sel_clkw_rx1 = 2'b00;\n parameter sel_clkw_rx2 = 2'b00;\n\n NX_IOM_CONTROL_M #(\n .div_rx1(div_rx1),\n .div_rx2(div_rx2),\n .div_tx1(div_tx1),\n .div_tx2(div_tx2),\n .inv_di_fclk1(inv_di_fclk1),\n .inv_di_fclk2(inv_di_fclk2),\n .latency1(latency1),\n .latency2(latency2),\n .location(location),\n .mode_cpath(mode_cpath),\n .mode_epath(mode_epath),\n .mode_io_cal(mode_io_cal),\n .mode_rpath(mode_rpath),\n .mode_side1(mode_side1),\n .mode_side2(mode_side2),\n .mode_tpath(mode_tpath),\n .sel_clk_out1(sel_clk_out1),\n .sel_clk_out2(sel_clk_out2),\n .sel_clkr_rx1(sel_clkr_rx1),\n .sel_clkr_rx2(sel_clkr_rx2),\n .sel_clkw_rx1(sel_clkw_rx1),\n .sel_clkw_rx2(sel_clkw_rx2)\n ) _TECHMAP_REPLACE_ (\n .C1RED(C1RED),\n .C1RNE(C1RNE),\n .C1RS(C1RS),\n .C1RW1(C1RW1),\n .C1RW2(C1RW2),\n .C1RW3(C1RW3),\n .C1TS(C1TS),\n .C1TW(C1TW),\n .C2RED(C2RED),\n .C2RNE(C2RNE),\n .C2RS(C2RS),\n .C2RW1(C2RW1),\n .C2RW2(C2RW2),\n .C2RW3(C2RW3),\n .C2TS(C2TS),\n .C2TW(C2TW),\n .CAD1(CAD1),\n .CAD2(CAD2),\n .CAD3(CAD3),\n .CAD4(CAD4),\n .CAD5(CAD5),\n .CAD6(CAD6),\n .CAL(CAL),\n .CAN1(CAN1),\n .CAN2(CAN2),\n .CAN3(CAN3),\n .CAN4(CAN4),\n .CAP1(CAP1),\n .CAP2(CAP2),\n .CAP3(CAP3),\n .CAP4(CAP4),\n .CAT1(CAT1),\n .CAT2(CAT2),\n .CAT3(CAT3),\n .CAT4(CAT4),\n .CCK(CCK),\n .CKO1(CKO1),\n .CKO2(CKO2),\n .CTCK(CTCK),\n .DC(DC),\n .DCK(DCK),\n .DIG(DIG),\n .DIS(DIS),\n .DOG(DOG),\n .DOS(DOS),\n .DPAG(DPAG),\n .DPAS(DPAS),\n .DQSG(DQSG),\n .DQSS(DQSS),\n .DRA1(DRA1),\n .DRA2(DRA2),\n .DRA3(DRA3),\n .DRA4(DRA4),\n .DRA5(DRA5),\n .DRA6(DRA6),\n .DRI1(DRI1),\n .DRI2(DRI2),\n .DRI3(DRI3),\n .DRI4(DRI4),\n .DRI5(DRI5),\n .DRI6(DRI6),\n .DRL(DRL),\n .DRO1(DRO1),\n .DRO2(DRO2),\n .DRO3(DRO3),\n .DRO4(DRO4),\n .DRO5(DRO5),\n .DRO6(DRO6),\n .DS1(DS1),\n .DS2(DS2),\n .FA1(FA1),\n .FA2(FA2),\n .FA3(FA3),\n .FA4(FA4),\n .FA5(FA5),\n .FA6(FA6),\n .FLD(FLD),\n .FLG(FLG),\n .FZ(FZ),\n .LINK1(LINK1),\n .LINK10(LINK10),\n .LINK11(LINK11),\n .LINK12(LINK12),\n .LINK13(LINK13),\n .LINK14(LINK14),\n .LINK15(LINK15),\n .LINK16(LINK16),\n .LINK17(LINK17),\n .LINK18(LINK18),\n .LINK19(LINK19),\n .LINK2(LINK2),\n .LINK20(LINK20),\n .LINK21(LINK21),\n .LINK22(LINK22),\n .LINK23(LINK23),\n .LINK24(LINK24),\n .LINK25(LINK25),\n .LINK26(LINK26),\n .LINK27(LINK27),\n .LINK28(LINK28),\n .LINK29(LINK29),\n .LINK3(LINK3),\n .LINK30(LINK30),\n .LINK31(LINK31),\n .LINK32(LINK32),\n .LINK33(LINK33),\n .LINK34(LINK34),\n .LINK4(LINK4),\n .LINK5(LINK5),\n .LINK6(LINK6),\n .LINK7(LINK7),\n .LINK8(LINK8),\n .LINK9(LINK9),\n .RRCK1(RRCK1),\n .RRCK2(RRCK2),\n .RTCK1(RTCK1),\n .RTCK2(RTCK2),\n .SPI1(SPI1),\n .SPI2(SPI2),\n .SPI3(SPI3),\n .WRCK1(WRCK1),\n .WRCK2(WRCK2),\n .WTCK1(WTCK1),\n .WTCK2(WTCK2)\n );\nendmodule\n\nmodule NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1\n, RO2, RO3, RO4, RO5, CTO, LINK);\n input CI1;\n input CI2;\n input CI3;\n input CI4;\n input CI5;\n input CL;\n output CO;\n input CR;\n input CTI;\n output CTO;\n input EI1;\n input EI2;\n input EI3;\n input EI4;\n input EI5;\n input EL;\n output EO;\n input ER;\n inout [41:0] LINK;\n input RI;\n input RL;\n output RO1;\n output RO2;\n output RO3;\n output RO4;\n output RO5;\n input RR;\n parameter chained = 1'b0;\n parameter cpath_edge = 1'b0;\n parameter cpath_init = 1'b0;\n parameter cpath_inv = 1'b0;\n parameter cpath_load = 1'b0;\n parameter cpath_mode = 4'b0000;\n parameter cpath_sync = 1'b0;\n parameter epath_dynamic = 1'b0;\n parameter epath_edge = 1'b0;\n parameter epath_init = 1'b0;\n parameter epath_load = 1'b0;\n parameter epath_mode = 4'b0000;\n parameter epath_sync = 1'b0;\n parameter location = \"\";\n parameter rpath_dynamic = 1'b0;\n parameter rpath_edge = 1'b0;\n parameter rpath_init = 1'b0;\n parameter rpath_load = 1'b0;\n parameter rpath_mode = 4'b0000;\n parameter rpath_sync = 1'b0;\n parameter symbol = \"\";\n parameter tpath_mode = 2'b00;\n parameter variant = \"\";\n\n NX_IOM_DRIVER_M #(\n .chained(chained),\n .cpath_edge(cpath_edge),\n .cpath_init(cpath_init),\n .cpath_inv(cpath_inv),\n .cpath_load(cpath_load),\n .cpath_mode(cpath_mode),\n .cpath_sync(cpath_sync),\n .epath_dynamic(epath_dynamic),\n .epath_edge(epath_edge),\n .epath_init(epath_init),\n .epath_load(epath_load),\n .epath_mode(epath_mode),\n .epath_sync(epath_sync),\n .location(location),\n .rpath_dynamic(rpath_dynamic),\n .rpath_edge(rpath_edge),\n .rpath_init(rpath_init),\n .rpath_load(rpath_load),\n .rpath_mode(rpath_mode),\n .rpath_sync(rpath_sync),\n .symbol(symbol),\n .tpath_mode(tpath_mode),\n .variant(variant)\n ) _TECHMAP_REPLACE_ (\n .CI1(CI1),\n .CI2(CI2),\n .CI3(CI3),\n .CI4(CI4),\n .CI5(CI5),\n .CL(CL),\n .CO(CO),\n .CR(CR),\n .CTI(CTI),\n .CTO(CTO),\n .EI1(EI1),\n .EI2(EI2),\n .EI3(EI3),\n .EI4(EI4),\n .EI5(EI5),\n .EL(EL),\n .EO(EO),\n .ER(ER),\n .LINK(LINK),\n .RI(RI),\n .RL(RL),\n .RO1(RO1),\n .RO2(RO2),\n .RO3(RO3),\n .RO4(RO4),\n .RO5(RO5),\n .RR(RR)\n );\nendmodule\n\nmodule NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);\n input CTCK;\n input DCK;\n output [5:0] DID;\n input DIG;\n input [5:0] DRA;\n input [5:0] DRI;\n input DRL;\n output [5:0] DRO;\n input [1:0] DS;\n output FLD;\n output FLG;\n input FZ;\n inout [41:0] LINKN;\n inout [41:0] LINKP;\n input RRCK;\n input RRST;\n input RTCK;\n input TRST;\n input WRCK;\n input WTCK;\n parameter data_size = 5;\n parameter location = \"\";\n\n NX_IOM_SERDES_M #(\n .data_size(data_size),\n .location(location)\n ) _TECHMAP_REPLACE_ (\n .CTCK(CTCK),\n .DCK(DCK),\n .DID(DID),\n .DIG(DIG),\n .DRA(DRA),\n .DRI(DRI),\n .DRL(DRL),\n .DRO(DRO),\n .DS(DS),\n .FLD(FLD),\n .FLG(FLG),\n .FZ(FZ),\n .LINKN(LINKN),\n .LINKP(LINKP),\n .RRCK(RRCK),\n .RRST(RRST),\n .RTCK(RTCK),\n .TRST(TRST),\n .WRCK(WRCK),\n .WTCK(WTCK)\n );\nendmodule\n",
311
+ "cells_wrap_u.v": "\nmodule NX_ODDFR_U(CK,R,I1,I2,L,O);\n input CK;\n input R;\n input I1;\n input I2;\n input L;\n output O;\n\n parameter location = \"\";\n parameter path = 0;\n parameter dff_type = 1'b0;\n parameter dff_sync = 1'b0;\n parameter dff_load = 1'b0;\n\n NX_DDFR_U #(\n .location(location),\n .path(path),\n .dff_type(dff_type),\n .dff_sync(dff_sync),\n .dff_load(dff_load)\n ) _TECHMAP_REPLACE_ (\n .CK(CK),\n .CKF(CK),\n .R(R),\n .I(I1),\n .I2(I2),\n .L(L),\n .O(O),\n .O2()\n );\nendmodule\n\nmodule NX_IDDFR_U(CK,R,I,L,O1,O2);\n input CK;\n input R;\n input I;\n input L;\n output O1;\n output O2;\n\n parameter location = \"\";\n parameter dff_type = 1'b0;\n parameter dff_sync = 1'b0;\n parameter dff_load = 1'b0;\n\n NX_DDFR_U #(\n .location(location),\n .path(1),\n .dff_type(dff_type),\n .dff_sync(dff_sync),\n .dff_load(dff_load)\n ) _TECHMAP_REPLACE_ (\n .CK(CK),\n .CKF(CK),\n .R(R),\n .I(I),\n .I2(1'b0),\n .L(L),\n .O(O1),\n .O2(O2)\n );\nendmodule\n\nmodule NX_CKS_U(CKI, CMD, CKO);\n input CKI;\n output CKO;\n input CMD;\n\n NX_GCK_U #(\n .inv_in(1'b0),\n .inv_out(1'b0),\n .std_mode(\"CKS\")\n ) _TECHMAP_REPLACE_ (\n .CMD(CMD),\n .SI1(CKI),\n .SI2(),\n .SO(CKO)\n );\nendmodule\n\nmodule NX_CMUX_U(CKI0, CKI1, SEL, CKO);\n input CKI0;\n input CKI1;\n output CKO;\n input SEL;\n\n NX_GCK_U #(\n .inv_in(1'b0),\n .inv_out(1'b0),\n .std_mode(\"MUX\")\n ) _TECHMAP_REPLACE_ (\n .CMD(SEL),\n .SI1(CKI0),\n .SI2(CKI1),\n .SO(CKO)\n );\nendmodule\n\nmodule NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI);\n input ADRSTI;\n output ADRSTO;\n input [5:0] AI;\n output [5:0] AO;\n input BDRSTI;\n output BDRSTO;\n input [5:0] BI;\n output [5:0] BO;\n input CK1;\n input CK2;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter use_adest_arst = 1'b0;\n parameter use_bdest_arst = 1'b0;\n\n NX_CDC_U #(\n .mode(0), // -- 0: 2DFF\n .ck0_edge(ck0_edge),\n .ck1_edge(ck1_edge),\n .ack_sel(ack_sel),\n .bck_sel(bck_sel),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(1'b0),\n .use_adest_arst(use_adest_arst),\n .use_bsrc_arst(1'b0),\n .use_bdest_arst(use_bdest_arst),\n .use_csrc_arst(1'b0),\n .use_cdest_arst(1'b0),\n .use_dsrc_arst(1'b0),\n .use_ddest_arst(1'b0),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .ASRSTI(1'b0),\n .ADRSTI(ADRSTI),\n .ADRSTO(ADRSTO),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BSRSTI(1'b0),\n .BDRSTI(BDRSTI),\n .BDRSTO(BDRSTO),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CSRSTI(1'b0),\n .CDRSTI(1'b0),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DSRSTI(1'b0),\n .DDRSTI(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0),\n );\nendmodule\n\nmodule NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);\n input ADRSTI;\n output ADRSTO;\n input [5:0] AI;\n output [5:0] AO;\n input ASRSTI;\n output ASRSTO;\n input BDRSTI;\n output BDRSTO;\n input [5:0] BI;\n output [5:0] BO;\n input BSRSTI;\n output BSRSTO;\n input CK1;\n input CK2;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter use_adest_arst = 1'b0;\n parameter use_asrc_arst = 1'b0;\n parameter use_bdest_arst = 1'b0;\n parameter use_bsrc_arst = 1'b0;\n\n NX_CDC_U #(\n .mode(1), // -- 1: 3DFF\n .ck0_edge(ck0_edge),\n .ck1_edge(ck1_edge),\n .ack_sel(ack_sel),\n .bck_sel(bck_sel),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(use_asrc_arst),\n .use_adest_arst(use_adest_arst),\n .use_bsrc_arst(use_bsrc_arst),\n .use_bdest_arst(use_bdest_arst),\n .use_csrc_arst(1'b0),\n .use_cdest_arst(1'b0),\n .use_dsrc_arst(1'b0),\n .use_ddest_arst(1'b0),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .ASRSTI(ASRSTI),\n .ADRSTI(ADRSTI),\n .ASRSTO(ASRSTO),\n .ADRSTO(ADRSTO),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BSRSTI(BSRSTI),\n .BDRSTI(BDRSTI),\n .BSRSTO(BSRSTO),\n .BDRSTO(BDRSTO),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CSRSTI(1'b0),\n .CDRSTI(1'b0),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DSRSTI(1'b0),\n .DDRSTI(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0),\n );\nendmodule\n\nmodule NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);\n input ADRSTI;\n output ADRSTO;\n input [5:0] AI;\n output [5:0] AO;\n input ASRSTI;\n output ASRSTO;\n input BDRSTI;\n output BDRSTO;\n input [5:0] BI;\n output [5:0] BO;\n input BSRSTI;\n output BSRSTO;\n input CK1;\n input CK2;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter use_adest_arst = 1'b0;\n parameter use_asrc_arst = 1'b0;\n parameter use_bdest_arst = 1'b0;\n parameter use_bsrc_arst = 1'b0;\n\n NX_CDC_U #(\n .mode(2), // -- 2: bin2gray + 3DFF + gray2bin\n .ck0_edge(ck0_edge),\n .ck1_edge(ck1_edge),\n .ack_sel(ack_sel),\n .bck_sel(bck_sel),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(use_asrc_arst),\n .use_adest_arst(use_adest_arst),\n .use_bsrc_arst(use_bsrc_arst),\n .use_bdest_arst(use_bdest_arst),\n .use_csrc_arst(1'b0),\n .use_cdest_arst(1'b0),\n .use_dsrc_arst(1'b0),\n .use_ddest_arst(1'b0),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .ASRSTI(ASRSTI),\n .ADRSTI(ADRSTI),\n .ASRSTO(ASRSTO),\n .ADRSTO(ADRSTO),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BSRSTI(BSRSTI),\n .BDRSTI(BDRSTI),\n .BSRSTO(BSRSTO),\n .BDRSTO(BDRSTO),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CSRSTI(1'b0),\n .CDRSTI(1'b0),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DSRSTI(1'b0),\n .DDRSTI(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0),\n );\nendmodule\n\nmodule NX_CDC_U_BIN2GRAY(BI, AO, BO, AI);\n input [5:0] AI;\n output [5:0] AO;\n input [5:0] BI;\n output [5:0] BO;\n\n NX_CDC_U #(\n .mode(3), // -- 3: bin2gray\n .ck0_edge(1'b0),\n .ck1_edge(1'b0),\n .ack_sel(1'b0),\n .bck_sel(1'b0),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(1'b0),\n .use_adest_arst(1'b0),\n .use_bsrc_arst(1'b0),\n .use_bdest_arst(1'b0),\n .use_csrc_arst(1'b0),\n .use_cdest_arst(1'b0),\n .use_dsrc_arst(1'b0),\n .use_ddest_arst(1'b0),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(1'b0),\n .CK2(1'b0),\n .ASRSTI(1'b0),\n .ADRSTI(1'b0),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BSRSTI(1'b0),\n .BDRSTI(1'b0),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CSRSTI(1'b0),\n .CDRSTI(1'b0),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DSRSTI(1'b0),\n .DDRSTI(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0),\n );\nendmodule\n\nmodule NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);\n input [5:0] AI;\n output [5:0] AO;\n input [5:0] BI;\n output [5:0] BO;\n\n NX_CDC_U #(\n .mode(4), // -- 4: gray2bin\n .ck0_edge(1'b0),\n .ck1_edge(1'b0),\n .ack_sel(1'b0),\n .bck_sel(1'b0),\n .cck_sel(1'b0),\n .dck_sel(1'b0),\n .use_asrc_arst(1'b0),\n .use_adest_arst(1'b0),\n .use_bsrc_arst(1'b0),\n .use_bdest_arst(1'b0),\n .use_csrc_arst(1'b0),\n .use_cdest_arst(1'b0),\n .use_dsrc_arst(1'b0),\n .use_ddest_arst(1'b0),\n .link_BA(1'b0),\n .link_CB(1'b0),\n .link_DC(1'b0),\n ) _TECHMAP_REPLACE_ (\n .CK1(1'b0),\n .CK2(1'b0),\n .ASRSTI(1'b0),\n .ADRSTI(1'b0),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BSRSTI(1'b0),\n .BDRSTI(1'b0),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CSRSTI(1'b0),\n .CDRSTI(1'b0),\n .CI1(1'b0),\n .CI2(1'b0),\n .CI3(1'b0),\n .CI4(1'b0),\n .CI5(1'b0),\n .CI6(1'b0),\n .DSRSTI(1'b0),\n .DDRSTI(1'b0),\n .DI1(1'b0),\n .DI2(1'b0),\n .DI3(1'b0),\n .DI4(1'b0),\n .DI5(1'b0),\n .DI6(1'b0),\n );\nendmodule\n\nmodule NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO\n, AO, BO, AI, DI, DO);\n input ADRSTI;\n output ADRSTO;\n input [5:0] AI;\n output [5:0] AO;\n input ASRSTI;\n output ASRSTO;\n input BDRSTI;\n output BDRSTO;\n input [5:0] BI;\n output [5:0] BO;\n input BSRSTI;\n output BSRSTO;\n input CDRSTI;\n output CDRSTO;\n input [5:0] CI;\n input CK1;\n input CK2;\n output [5:0] CO;\n input CSRSTI;\n output CSRSTO;\n input DDRSTI;\n output DDRSTO;\n input [5:0] DI;\n output [5:0] DO;\n input DSRSTI;\n output DSRSTO;\n parameter ack_sel = 1'b0;\n parameter bck_sel = 1'b0;\n parameter cck_sel = 1'b0;\n parameter ck0_edge = 1'b0;\n parameter ck1_edge = 1'b0;\n parameter dck_sel = 1'b0;\n parameter link_BA = 1'b0;\n parameter link_CB = 1'b0;\n parameter link_DC = 1'b0;\n parameter use_adest_arst = 1'b0;\n parameter use_asrc_arst = 1'b0;\n parameter use_bdest_arst = 1'b0;\n parameter use_bsrc_arst = 1'b0;\n parameter use_cdest_arst = 1'b0;\n parameter use_csrc_arst = 1'b0;\n parameter use_ddest_arst = 1'b0;\n parameter use_dsrc_arst = 1'b0;\n\n NX_CDC_U #(\n .mode(5), // -- 5: XCDC\n .ck0_edge(ck0_edge),\n .ck1_edge(ck1_edge),\n .ack_sel(ack_sel),\n .bck_sel(bck_sel),\n .cck_sel(cck_sel),\n .dck_sel(dck_sel),\n .use_asrc_arst(use_asrc_arst),\n .use_adest_arst(use_adest_arst),\n .use_bsrc_arst(use_bsrc_arst),\n .use_bdest_arst(use_bdest_arst),\n .use_csrc_arst(use_csrc_arst),\n .use_cdest_arst(use_cdest_arst),\n .use_dsrc_arst(use_dsrc_arst),\n .use_ddest_arst(use_ddest_arst),\n .link_BA(link_BA),\n .link_CB(link_CB),\n .link_DC(link_DC),\n ) _TECHMAP_REPLACE_ (\n .CK1(CK1),\n .CK2(CK2),\n .ASRSTI(ASRSTI),\n .ADRSTI(ADRSTI),\n .ASRSTO(ASRSTO),\n .ADRSTO(ADRSTO),\n .AI1(AI[0]),\n .AI2(AI[1]),\n .AI3(AI[2]),\n .AI4(AI[3]),\n .AI5(AI[4]),\n .AI6(AI[5]),\n .AO1(AO[0]),\n .AO2(AO[1]),\n .AO3(AO[2]),\n .AO4(AO[3]),\n .AO5(AO[4]),\n .AO6(AO[5]),\n .BSRSTI(BSRSTI),\n .BDRSTI(BDRSTI),\n .BSRSTO(BSRSTO),\n .BDRSTO(BDRSTO),\n .BI1(BI[0]),\n .BI2(BI[1]),\n .BI3(BI[2]),\n .BI4(BI[3]),\n .BI5(BI[4]),\n .BI6(BI[5]),\n .BO1(BO[0]),\n .BO2(BO[1]),\n .BO3(BO[2]),\n .BO4(BO[3]),\n .BO5(BO[4]),\n .BO6(BO[5]),\n .CSRSTI(CSRSTI),\n .CDRSTI(CDRSTI),\n .CSRSTO(CSRSTO),\n .CDRSTO(CDRSTO),\n .CI1(CI[0]),\n .CI2(CI[1]),\n .CI3(CI[2]),\n .CI4(CI[3]),\n .CI5(CI[4]),\n .CI6(CI[5]),\n .CO1(CO[0]),\n .CO2(CO[1]),\n .CO3(CO[2]),\n .CO4(CO[3]),\n .CO5(CO[4]),\n .CO6(CO[5]),\n .DSRSTI(DSRSTI),\n .DDRSTI(DDRSTI),\n .DSRSTO(DSRSTO),\n .DDRSTO(DDRSTO),\n .DI1(DI[0]),\n .DI2(DI[1]),\n .DI3(DI[2]),\n .DI4(DI[3]),\n .DI5(DI[4]),\n .DI6(DI[5]),\n .DO1(DO[0]),\n .DO2(DO[1]),\n .DO3(DO[2]),\n .DO4(DO[3]),\n .DO5(DO[4]),\n .DO6(DO[5]),\n );\nendmodule\n\nmodule NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO, CZO);\n input [23:0] A;\n input [17:0] B;\n input [35:0] C;\n input [23:0] CAI;\n output [23:0] CAO;\n input [17:0] CBI;\n output [17:0] CBO;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO42;\n output CO56;\n input [55:0] CZI;\n output [55:0] CZO;\n input [17:0] D;\n output OVF;\n input R;\n input RZ;\n input WE;\n input WEZ;\n output [55:0] Z;\n parameter ALU_DYNAMIC_OP = 2'b00;\n parameter ALU_OP = 3'b000;\n parameter ENABLE_PR_A_RST = 1'b0;\n parameter ENABLE_PR_B_RST = 1'b0;\n parameter ENABLE_PR_CCO_RST = 1'b0;\n parameter ENABLE_PR_CI_RST = 1'b0;\n parameter ENABLE_PR_CO_RST = 1'b0;\n parameter ENABLE_PR_CZ_RST = 1'b0;\n parameter ENABLE_PR_C_RST = 1'b0;\n parameter ENABLE_PR_D_RST = 1'b0;\n parameter ENABLE_PR_MULT_RST = 1'b0;\n parameter ENABLE_PR_OV_RST = 1'b0;\n parameter ENABLE_PR_P_RST = 1'b0;\n parameter ENABLE_PR_X_RST = 1'b0;\n parameter ENABLE_PR_Y_RST = 1'b0;\n parameter ENABLE_PR_Z_RST = 1'b0;\n parameter ENABLE_SATURATION = 1'b0;\n parameter INV_RST = 1'b0;\n parameter INV_RSTZ = 1'b0;\n parameter INV_WE = 1'b0;\n parameter INV_WEZ = 1'b0;\n parameter MUX_A = 1'b0;\n parameter MUX_B = 1'b0;\n parameter MUX_CCI = 1'b0;\n parameter MUX_CCO = 1'b0;\n parameter MUX_CI = 1'b0;\n parameter MUX_CZ = 1'b0;\n parameter MUX_P = 1'b0;\n parameter MUX_X = 3'b000;\n parameter MUX_Y = 1'b0;\n parameter MUX_Z = 1'b0;\n parameter PRE_ADDER_OP = 1'b0;\n parameter PR_A_CASCADE_MUX = 2'b00;\n parameter PR_A_MUX = 2'b00;\n parameter PR_B_CASCADE_MUX = 2'b00;\n parameter PR_B_MUX = 2'b00;\n parameter PR_CCO_MUX = 1'b0;\n parameter PR_CI_MUX = 1'b0;\n parameter PR_CO_MUX = 1'b0;\n parameter PR_CZ_MUX = 1'b0;\n parameter PR_C_MUX = 1'b0;\n parameter PR_D_MUX = 1'b0;\n parameter PR_MULT_MUX = 1'b0;\n parameter PR_OV_MUX = 1'b0;\n parameter PR_P_MUX = 1'b0;\n parameter PR_RSTZ_MUX = 1'b0;\n parameter PR_RST_MUX = 1'b0;\n parameter PR_WEZ_MUX = 1'b0;\n parameter PR_WE_MUX = 1'b0;\n parameter PR_X_MUX = 1'b0;\n parameter PR_Y_MUX = 1'b0;\n parameter PR_Z_MUX = 1'b0;\n parameter SATURATION_RANK = 6'b000000;\n parameter SIGNED_MODE = 1'b0;\n\n localparam RAW_CONFIG0_GEN = { INV_WE, INV_WEZ, INV_RST, INV_RSTZ, MUX_CCO, ALU_DYNAMIC_OP, SATURATION_RANK,\n ENABLE_SATURATION, MUX_Z, MUX_CCI, MUX_CI, MUX_Y, MUX_CZ, MUX_X, MUX_P,\n MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };\n\n localparam RAW_CONFIG1_GEN = { PR_WE_MUX, PR_WEZ_MUX, PR_RST_MUX, PR_RSTZ_MUX, PR_OV_MUX, PR_CO_MUX, PR_CCO_MUX,\n PR_Z_MUX, PR_CZ_MUX, PR_Y_MUX, PR_X_MUX, PR_CI_MUX, PR_MULT_MUX, PR_P_MUX, PR_D_MUX,\n PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };\n\n localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_CCO_RST, ENABLE_PR_Z_RST, ENABLE_PR_CZ_RST,\n ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,\n ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };\n\n localparam RAW_CONFIG3_GEN = { ALU_OP };\n\n NX_DSP_U #(\n .std_mode(\"\"),\n .raw_config0(RAW_CONFIG0_GEN),\n .raw_config1(RAW_CONFIG1_GEN),\n .raw_config2(RAW_CONFIG2_GEN),\n .raw_config3(RAW_CONFIG3_GEN)\n ) _TECHMAP_REPLACE_ (\n .A1(A[0]),\n .A2(A[1]),\n .A3(A[2]),\n .A4(A[3]),\n .A5(A[4]),\n .A6(A[5]),\n .A7(A[6]),\n .A8(A[7]),\n .A9(A[8]),\n .A10(A[9]),\n .A11(A[10]),\n .A12(A[11]),\n .A13(A[12]),\n .A14(A[13]),\n .A15(A[14]),\n .A16(A[15]),\n .A17(A[16]),\n .A18(A[17]),\n .A19(A[18]),\n .A20(A[19]),\n .A21(A[20]),\n .A22(A[21]),\n .A23(A[22]),\n .A24(A[23]),\n\n .B1(B[0]),\n .B2(B[1]),\n .B3(B[2]),\n .B4(B[3]),\n .B5(B[4]),\n .B6(B[5]),\n .B7(B[6]),\n .B8(B[7]),\n .B9(B[8]),\n .B10(B[9]),\n .B11(B[10]),\n .B12(B[11]),\n .B13(B[12]),\n .B14(B[13]),\n .B15(B[14]),\n .B16(B[15]),\n .B17(B[16]),\n .B18(B[17]),\n\n .C1(C[0]),\n .C2(C[1]),\n .C3(C[2]),\n .C4(C[3]),\n .C5(C[4]),\n .C6(C[5]),\n .C7(C[6]),\n .C8(C[7]),\n .C9(C[8]),\n .C10(C[9]),\n .C11(C[10]),\n .C12(C[11]),\n .C13(C[12]),\n .C14(C[13]),\n .C15(C[14]),\n .C16(C[15]),\n .C17(C[16]),\n .C18(C[17]),\n .C19(C[18]),\n .C20(C[19]),\n .C21(C[20]),\n .C22(C[21]),\n .C23(C[22]),\n .C24(C[23]),\n .C25(C[24]),\n .C26(C[25]),\n .C27(C[26]),\n .C28(C[27]),\n .C29(C[28]),\n .C30(C[29]),\n .C31(C[30]),\n .C32(C[31]),\n .C33(C[32]),\n .C34(C[33]),\n .C35(C[34]),\n .C36(C[35]),\n\n .CAI1(CAI[0]),\n .CAI2(CAI[1]),\n .CAI3(CAI[2]),\n .CAI4(CAI[3]),\n .CAI5(CAI[4]),\n .CAI6(CAI[5]),\n .CAI7(CAI[6]),\n .CAI8(CAI[7]),\n .CAI9(CAI[8]),\n .CAI10(CAI[9]),\n .CAI11(CAI[10]),\n .CAI12(CAI[11]),\n .CAI13(CAI[12]),\n .CAI14(CAI[13]),\n .CAI15(CAI[14]),\n .CAI16(CAI[15]),\n .CAI17(CAI[16]),\n .CAI18(CAI[17]),\n .CAI19(CAI[18]),\n .CAI20(CAI[19]),\n .CAI21(CAI[20]),\n .CAI22(CAI[21]),\n .CAI23(CAI[22]),\n .CAI24(CAI[23]),\n\n .CAO1(CAO[0]),\n .CAO2(CAO[1]),\n .CAO3(CAO[2]),\n .CAO4(CAO[3]),\n .CAO5(CAO[4]),\n .CAO6(CAO[5]),\n .CAO7(CAO[6]),\n .CAO8(CAO[7]),\n .CAO9(CAO[8]),\n .CAO10(CAO[9]),\n .CAO11(CAO[10]),\n .CAO12(CAO[11]),\n .CAO13(CAO[12]),\n .CAO14(CAO[13]),\n .CAO15(CAO[14]),\n .CAO16(CAO[15]),\n .CAO17(CAO[16]),\n .CAO18(CAO[17]),\n .CAO19(CAO[18]),\n .CAO20(CAO[19]),\n .CAO21(CAO[20]),\n .CAO22(CAO[21]),\n .CAO23(CAO[22]),\n .CAO24(CAO[23]),\n\n .CBI1(CBI[0]),\n .CBI2(CBI[1]),\n .CBI3(CBI[2]),\n .CBI4(CBI[3]),\n .CBI5(CBI[4]),\n .CBI6(CBI[5]),\n .CBI7(CBI[6]),\n .CBI8(CBI[7]),\n .CBI9(CBI[8]),\n .CBI10(CBI[9]),\n .CBI11(CBI[10]),\n .CBI12(CBI[11]),\n .CBI13(CBI[12]),\n .CBI14(CBI[13]),\n .CBI15(CBI[14]),\n .CBI16(CBI[15]),\n .CBI17(CBI[16]),\n .CBI18(CBI[17]),\n\n .CBO1(CBO[0]),\n .CBO2(CBO[1]),\n .CBO3(CBO[2]),\n .CBO4(CBO[3]),\n .CBO5(CBO[4]),\n .CBO6(CBO[5]),\n .CBO7(CBO[6]),\n .CBO8(CBO[7]),\n .CBO9(CBO[8]),\n .CBO10(CBO[9]),\n .CBO11(CBO[10]),\n .CBO12(CBO[11]),\n .CBO13(CBO[12]),\n .CBO14(CBO[13]),\n .CBO15(CBO[14]),\n .CBO16(CBO[15]),\n .CBO17(CBO[16]),\n .CBO18(CBO[17]),\n\n .CCI(CCI),\n .CCO(CCO),\n .CI(CI),\n .CK(CK),\n .CO43(CO42),\n .CO57(CO56),\n\n .CZI1(CZI[0]),\n .CZI2(CZI[1]),\n .CZI3(CZI[2]),\n .CZI4(CZI[3]),\n .CZI5(CZI[4]),\n .CZI6(CZI[5]),\n .CZI7(CZI[6]),\n .CZI8(CZI[7]),\n .CZI9(CZI[8]),\n .CZI10(CZI[9]),\n .CZI11(CZI[10]),\n .CZI12(CZI[11]),\n .CZI13(CZI[12]),\n .CZI14(CZI[13]),\n .CZI15(CZI[14]),\n .CZI16(CZI[15]),\n .CZI17(CZI[16]),\n .CZI18(CZI[17]),\n .CZI19(CZI[18]),\n .CZI20(CZI[19]),\n .CZI21(CZI[20]),\n .CZI22(CZI[21]),\n .CZI23(CZI[22]),\n .CZI24(CZI[23]),\n .CZI25(CZI[24]),\n .CZI26(CZI[25]),\n .CZI27(CZI[26]),\n .CZI28(CZI[27]),\n .CZI29(CZI[28]),\n .CZI30(CZI[29]),\n .CZI31(CZI[30]),\n .CZI32(CZI[31]),\n .CZI33(CZI[32]),\n .CZI34(CZI[33]),\n .CZI35(CZI[34]),\n .CZI36(CZI[35]),\n .CZI37(CZI[36]),\n .CZI38(CZI[37]),\n .CZI39(CZI[38]),\n .CZI40(CZI[39]),\n .CZI41(CZI[40]),\n .CZI42(CZI[41]),\n .CZI43(CZI[42]),\n .CZI44(CZI[43]),\n .CZI45(CZI[44]),\n .CZI46(CZI[45]),\n .CZI47(CZI[46]),\n .CZI48(CZI[47]),\n .CZI49(CZI[48]),\n .CZI50(CZI[49]),\n .CZI51(CZI[50]),\n .CZI52(CZI[51]),\n .CZI53(CZI[52]),\n .CZI54(CZI[53]),\n .CZI55(CZI[54]),\n .CZI56(CZI[55]),\n\n .CZO1(CZO[0]),\n .CZO2(CZO[1]),\n .CZO3(CZO[2]),\n .CZO4(CZO[3]),\n .CZO5(CZO[4]),\n .CZO6(CZO[5]),\n .CZO7(CZO[6]),\n .CZO8(CZO[7]),\n .CZO9(CZO[8]),\n .CZO10(CZO[9]),\n .CZO11(CZO[10]),\n .CZO12(CZO[11]),\n .CZO13(CZO[12]),\n .CZO14(CZO[13]),\n .CZO15(CZO[14]),\n .CZO16(CZO[15]),\n .CZO17(CZO[16]),\n .CZO18(CZO[17]),\n .CZO19(CZO[18]),\n .CZO20(CZO[19]),\n .CZO21(CZO[20]),\n .CZO22(CZO[21]),\n .CZO23(CZO[22]),\n .CZO24(CZO[23]),\n .CZO25(CZO[24]),\n .CZO26(CZO[25]),\n .CZO27(CZO[26]),\n .CZO28(CZO[27]),\n .CZO29(CZO[28]),\n .CZO30(CZO[29]),\n .CZO31(CZO[30]),\n .CZO32(CZO[31]),\n .CZO33(CZO[32]),\n .CZO34(CZO[33]),\n .CZO35(CZO[34]),\n .CZO36(CZO[35]),\n .CZO37(CZO[36]),\n .CZO38(CZO[37]),\n .CZO39(CZO[38]),\n .CZO40(CZO[39]),\n .CZO41(CZO[40]),\n .CZO42(CZO[41]),\n .CZO43(CZO[42]),\n .CZO44(CZO[43]),\n .CZO45(CZO[44]),\n .CZO46(CZO[45]),\n .CZO47(CZO[46]),\n .CZO48(CZO[47]),\n .CZO49(CZO[48]),\n .CZO50(CZO[49]),\n .CZO51(CZO[50]),\n .CZO52(CZO[51]),\n .CZO53(CZO[52]),\n .CZO54(CZO[53]),\n .CZO55(CZO[54]),\n .CZO56(CZO[55]),\n\n .D1(D[0]),\n .D2(D[1]),\n .D3(D[2]),\n .D4(D[3]),\n .D5(D[4]),\n .D6(D[5]),\n .D7(D[6]),\n .D8(D[7]),\n .D9(D[8]),\n .D10(D[9]),\n .D11(D[10]),\n .D12(D[11]),\n .D13(D[12]),\n .D14(D[13]),\n .D15(D[14]),\n .D16(D[15]),\n .D17(D[16]),\n .D18(D[17]),\n\n .OVF(OVF),\n .R(R),\n .RZ(RZ),\n .WE(WE),\n .WEZ(WEZ),\n\n .Z1(Z[0]),\n .Z2(Z[1]),\n .Z3(Z[2]),\n .Z4(Z[3]),\n .Z5(Z[4]),\n .Z6(Z[5]),\n .Z7(Z[6]),\n .Z8(Z[7]),\n .Z9(Z[8]),\n .Z10(Z[9]),\n .Z11(Z[10]),\n .Z12(Z[11]),\n .Z13(Z[12]),\n .Z14(Z[13]),\n .Z15(Z[14]),\n .Z16(Z[15]),\n .Z17(Z[16]),\n .Z18(Z[17]),\n .Z19(Z[18]),\n .Z20(Z[19]),\n .Z21(Z[20]),\n .Z22(Z[21]),\n .Z23(Z[22]),\n .Z24(Z[23]),\n .Z25(Z[24]),\n .Z26(Z[25]),\n .Z27(Z[26]),\n .Z28(Z[27]),\n .Z29(Z[28]),\n .Z30(Z[29]),\n .Z31(Z[30]),\n .Z32(Z[31]),\n .Z33(Z[32]),\n .Z34(Z[33]),\n .Z35(Z[34]),\n .Z36(Z[35]),\n .Z37(Z[36]),\n .Z38(Z[37]),\n .Z39(Z[38]),\n .Z40(Z[39]),\n .Z41(Z[40]),\n .Z42(Z[41]),\n .Z43(Z[42]),\n .Z44(Z[43]),\n .Z45(Z[44]),\n .Z46(Z[45]),\n .Z47(Z[46]),\n .Z48(Z[47]),\n .Z49(Z[48]),\n .Z50(Z[49]),\n .Z51(Z[50]),\n .Z52(Z[51]),\n .Z53(Z[52]),\n .Z54(Z[53]),\n .Z55(Z[54]),\n .Z56(Z[55])\n );\nendmodule\n\nmodule NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO\n, CZO);\n input [23:0] A;\n input [17:0] B;\n input [35:0] C;\n input [23:0] CAI;\n output [23:0] CAO;\n input [17:0] CBI;\n output [17:0] CBO;\n input CCI;\n output CCO;\n input CI;\n input CK;\n output CO43;\n output CO57;\n input [55:0] CZI;\n output [55:0] CZO;\n input [17:0] D;\n output OVF;\n input R;\n input RZ;\n input WE;\n input WEZ;\n output [55:0] Z;\n parameter raw_config0 = 27'b000000000000000000000000000;\n parameter raw_config1 = 24'b000000000000000000000000;\n parameter raw_config2 = 14'b00000000000000;\n parameter raw_config3 = 3'b000;\n parameter std_mode = \"\";\n\n NX_DSP_U #(\n .std_mode(std_mode),\n .raw_config0(raw_config0),\n .raw_config1(raw_config1),\n .raw_config2(raw_config2),\n .raw_config3(raw_config3)\n ) _TECHMAP_REPLACE_ (\n .A1(A[0]),\n .A2(A[1]),\n .A3(A[2]),\n .A4(A[3]),\n .A5(A[4]),\n .A6(A[5]),\n .A7(A[6]),\n .A8(A[7]),\n .A9(A[8]),\n .A10(A[9]),\n .A11(A[10]),\n .A12(A[11]),\n .A13(A[12]),\n .A14(A[13]),\n .A15(A[14]),\n .A16(A[15]),\n .A17(A[16]),\n .A18(A[17]),\n .A19(A[18]),\n .A20(A[19]),\n .A21(A[20]),\n .A22(A[21]),\n .A23(A[22]),\n .A24(A[23]),\n\n .B1(B[0]),\n .B2(B[1]),\n .B3(B[2]),\n .B4(B[3]),\n .B5(B[4]),\n .B6(B[5]),\n .B7(B[6]),\n .B8(B[7]),\n .B9(B[8]),\n .B10(B[9]),\n .B11(B[10]),\n .B12(B[11]),\n .B13(B[12]),\n .B14(B[13]),\n .B15(B[14]),\n .B16(B[15]),\n .B17(B[16]),\n .B18(B[17]),\n\n .C1(C[0]),\n .C2(C[1]),\n .C3(C[2]),\n .C4(C[3]),\n .C5(C[4]),\n .C6(C[5]),\n .C7(C[6]),\n .C8(C[7]),\n .C9(C[8]),\n .C10(C[9]),\n .C11(C[10]),\n .C12(C[11]),\n .C13(C[12]),\n .C14(C[13]),\n .C15(C[14]),\n .C16(C[15]),\n .C17(C[16]),\n .C18(C[17]),\n .C19(C[18]),\n .C20(C[19]),\n .C21(C[20]),\n .C22(C[21]),\n .C23(C[22]),\n .C24(C[23]),\n .C25(C[24]),\n .C26(C[25]),\n .C27(C[26]),\n .C28(C[27]),\n .C29(C[28]),\n .C30(C[29]),\n .C31(C[30]),\n .C32(C[31]),\n .C33(C[32]),\n .C34(C[33]),\n .C35(C[34]),\n .C36(C[35]),\n\n .CAI1(CAI[0]),\n .CAI2(CAI[1]),\n .CAI3(CAI[2]),\n .CAI4(CAI[3]),\n .CAI5(CAI[4]),\n .CAI6(CAI[5]),\n .CAI7(CAI[6]),\n .CAI8(CAI[7]),\n .CAI9(CAI[8]),\n .CAI10(CAI[9]),\n .CAI11(CAI[10]),\n .CAI12(CAI[11]),\n .CAI13(CAI[12]),\n .CAI14(CAI[13]),\n .CAI15(CAI[14]),\n .CAI16(CAI[15]),\n .CAI17(CAI[16]),\n .CAI18(CAI[17]),\n .CAI19(CAI[18]),\n .CAI20(CAI[19]),\n .CAI21(CAI[20]),\n .CAI22(CAI[21]),\n .CAI23(CAI[22]),\n .CAI24(CAI[23]),\n\n .CAO1(CAO[0]),\n .CAO2(CAO[1]),\n .CAO3(CAO[2]),\n .CAO4(CAO[3]),\n .CAO5(CAO[4]),\n .CAO6(CAO[5]),\n .CAO7(CAO[6]),\n .CAO8(CAO[7]),\n .CAO9(CAO[8]),\n .CAO10(CAO[9]),\n .CAO11(CAO[10]),\n .CAO12(CAO[11]),\n .CAO13(CAO[12]),\n .CAO14(CAO[13]),\n .CAO15(CAO[14]),\n .CAO16(CAO[15]),\n .CAO17(CAO[16]),\n .CAO18(CAO[17]),\n .CAO19(CAO[18]),\n .CAO20(CAO[19]),\n .CAO21(CAO[20]),\n .CAO22(CAO[21]),\n .CAO23(CAO[22]),\n .CAO24(CAO[23]),\n\n .CBI1(CBI[0]),\n .CBI2(CBI[1]),\n .CBI3(CBI[2]),\n .CBI4(CBI[3]),\n .CBI5(CBI[4]),\n .CBI6(CBI[5]),\n .CBI7(CBI[6]),\n .CBI8(CBI[7]),\n .CBI9(CBI[8]),\n .CBI10(CBI[9]),\n .CBI11(CBI[10]),\n .CBI12(CBI[11]),\n .CBI13(CBI[12]),\n .CBI14(CBI[13]),\n .CBI15(CBI[14]),\n .CBI16(CBI[15]),\n .CBI17(CBI[16]),\n .CBI18(CBI[17]),\n\n .CBO1(CBO[0]),\n .CBO2(CBO[1]),\n .CBO3(CBO[2]),\n .CBO4(CBO[3]),\n .CBO5(CBO[4]),\n .CBO6(CBO[5]),\n .CBO7(CBO[6]),\n .CBO8(CBO[7]),\n .CBO9(CBO[8]),\n .CBO10(CBO[9]),\n .CBO11(CBO[10]),\n .CBO12(CBO[11]),\n .CBO13(CBO[12]),\n .CBO14(CBO[13]),\n .CBO15(CBO[14]),\n .CBO16(CBO[15]),\n .CBO17(CBO[16]),\n .CBO18(CBO[17]),\n\n .CCI(CCI),\n .CCO(CCO),\n .CI(CI),\n .CK(CK),\n .CO43(CO43),\n .CO57(CO57),\n\n .CZI1(CZI[0]),\n .CZI2(CZI[1]),\n .CZI3(CZI[2]),\n .CZI4(CZI[3]),\n .CZI5(CZI[4]),\n .CZI6(CZI[5]),\n .CZI7(CZI[6]),\n .CZI8(CZI[7]),\n .CZI9(CZI[8]),\n .CZI10(CZI[9]),\n .CZI11(CZI[10]),\n .CZI12(CZI[11]),\n .CZI13(CZI[12]),\n .CZI14(CZI[13]),\n .CZI15(CZI[14]),\n .CZI16(CZI[15]),\n .CZI17(CZI[16]),\n .CZI18(CZI[17]),\n .CZI19(CZI[18]),\n .CZI20(CZI[19]),\n .CZI21(CZI[20]),\n .CZI22(CZI[21]),\n .CZI23(CZI[22]),\n .CZI24(CZI[23]),\n .CZI25(CZI[24]),\n .CZI26(CZI[25]),\n .CZI27(CZI[26]),\n .CZI28(CZI[27]),\n .CZI29(CZI[28]),\n .CZI30(CZI[29]),\n .CZI31(CZI[30]),\n .CZI32(CZI[31]),\n .CZI33(CZI[32]),\n .CZI34(CZI[33]),\n .CZI35(CZI[34]),\n .CZI36(CZI[35]),\n .CZI37(CZI[36]),\n .CZI38(CZI[37]),\n .CZI39(CZI[38]),\n .CZI40(CZI[39]),\n .CZI41(CZI[40]),\n .CZI42(CZI[41]),\n .CZI43(CZI[42]),\n .CZI44(CZI[43]),\n .CZI45(CZI[44]),\n .CZI46(CZI[45]),\n .CZI47(CZI[46]),\n .CZI48(CZI[47]),\n .CZI49(CZI[48]),\n .CZI50(CZI[49]),\n .CZI51(CZI[50]),\n .CZI52(CZI[51]),\n .CZI53(CZI[52]),\n .CZI54(CZI[53]),\n .CZI55(CZI[54]),\n .CZI56(CZI[55]),\n\n .CZO1(CZO[0]),\n .CZO2(CZO[1]),\n .CZO3(CZO[2]),\n .CZO4(CZO[3]),\n .CZO5(CZO[4]),\n .CZO6(CZO[5]),\n .CZO7(CZO[6]),\n .CZO8(CZO[7]),\n .CZO9(CZO[8]),\n .CZO10(CZO[9]),\n .CZO11(CZO[10]),\n .CZO12(CZO[11]),\n .CZO13(CZO[12]),\n .CZO14(CZO[13]),\n .CZO15(CZO[14]),\n .CZO16(CZO[15]),\n .CZO17(CZO[16]),\n .CZO18(CZO[17]),\n .CZO19(CZO[18]),\n .CZO20(CZO[19]),\n .CZO21(CZO[20]),\n .CZO22(CZO[21]),\n .CZO23(CZO[22]),\n .CZO24(CZO[23]),\n .CZO25(CZO[24]),\n .CZO26(CZO[25]),\n .CZO27(CZO[26]),\n .CZO28(CZO[27]),\n .CZO29(CZO[28]),\n .CZO30(CZO[29]),\n .CZO31(CZO[30]),\n .CZO32(CZO[31]),\n .CZO33(CZO[32]),\n .CZO34(CZO[33]),\n .CZO35(CZO[34]),\n .CZO36(CZO[35]),\n .CZO37(CZO[36]),\n .CZO38(CZO[37]),\n .CZO39(CZO[38]),\n .CZO40(CZO[39]),\n .CZO41(CZO[40]),\n .CZO42(CZO[41]),\n .CZO43(CZO[42]),\n .CZO44(CZO[43]),\n .CZO45(CZO[44]),\n .CZO46(CZO[45]),\n .CZO47(CZO[46]),\n .CZO48(CZO[47]),\n .CZO49(CZO[48]),\n .CZO50(CZO[49]),\n .CZO51(CZO[50]),\n .CZO52(CZO[51]),\n .CZO53(CZO[52]),\n .CZO54(CZO[53]),\n .CZO55(CZO[54]),\n .CZO56(CZO[55]),\n\n .D1(D[0]),\n .D2(D[1]),\n .D3(D[2]),\n .D4(D[3]),\n .D5(D[4]),\n .D6(D[5]),\n .D7(D[6]),\n .D8(D[7]),\n .D9(D[8]),\n .D10(D[9]),\n .D11(D[10]),\n .D12(D[11]),\n .D13(D[12]),\n .D14(D[13]),\n .D15(D[14]),\n .D16(D[15]),\n .D17(D[16]),\n .D18(D[17]),\n\n .OVF(OVF),\n .R(R),\n .RZ(RZ),\n .WE(WE),\n .WEZ(WEZ),\n\n .Z1(Z[0]),\n .Z2(Z[1]),\n .Z3(Z[2]),\n .Z4(Z[3]),\n .Z5(Z[4]),\n .Z6(Z[5]),\n .Z7(Z[6]),\n .Z8(Z[7]),\n .Z9(Z[8]),\n .Z10(Z[9]),\n .Z11(Z[10]),\n .Z12(Z[11]),\n .Z13(Z[12]),\n .Z14(Z[13]),\n .Z15(Z[14]),\n .Z16(Z[15]),\n .Z17(Z[16]),\n .Z18(Z[17]),\n .Z19(Z[18]),\n .Z20(Z[19]),\n .Z21(Z[20]),\n .Z22(Z[21]),\n .Z23(Z[22]),\n .Z24(Z[23]),\n .Z25(Z[24]),\n .Z26(Z[25]),\n .Z27(Z[26]),\n .Z28(Z[27]),\n .Z29(Z[28]),\n .Z30(Z[29]),\n .Z31(Z[30]),\n .Z32(Z[31]),\n .Z33(Z[32]),\n .Z34(Z[33]),\n .Z35(Z[34]),\n .Z36(Z[35]),\n .Z37(Z[36]),\n .Z38(Z[37]),\n .Z39(Z[38]),\n .Z40(Z[39]),\n .Z41(Z[40]),\n .Z42(Z[41]),\n .Z43(Z[42]),\n .Z44(Z[43]),\n .Z45(Z[44]),\n .Z46(Z[45]),\n .Z47(Z[46]),\n .Z48(Z[47]),\n .Z49(Z[48]),\n .Z50(Z[49]),\n .Z51(Z[50]),\n .Z52(Z[51]),\n .Z53(Z[52]),\n .Z54(Z[53]),\n .Z55(Z[54]),\n .Z56(Z[55])\n );\nendmodule\n\nmodule NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);\n input ARST_CAL;\n output [4:0] CAL;\n output CAL_LOCKED;\n input CLK_CAL;\n output CLK_CAL_DIV;\n output [3:0] CLK_DIV;\n output [4:0] CLK_DIVD;\n input [4:0] EXT_CAL;\n input EXT_CAL_LOCKED;\n input FBK;\n output LDFO;\n output OSC;\n output PLL_LOCKED;\n output PLL_LOCKEDA;\n input R;\n input REF;\n output REFO;\n output VCO;\n parameter cal_delay = 6'b011011;\n parameter cal_div = 4'b0111;\n parameter clk_cal_sel = 2'b01;\n parameter clk_outdiv1 = 3'b000;\n parameter clk_outdiv2 = 3'b000;\n parameter clk_outdiv3 = 3'b000;\n parameter clk_outdiv4 = 3'b000;\n parameter clk_outdivd1 = 4'b0000;\n parameter clk_outdivd2 = 4'b0000;\n parameter clk_outdivd3 = 4'b0000;\n parameter clk_outdivd4 = 4'b0000;\n parameter clk_outdivd5 = 4'b0000;\n parameter ext_fbk_on = 1'b0;\n parameter fbk_delay = 6'b000000;\n parameter fbk_delay_on = 1'b0;\n parameter fbk_intdiv = 7'b0000000;\n parameter location = \"\";\n parameter pll_cpump = 4'b0000;\n parameter pll_lock = 4'b0000;\n parameter pll_lpf_cap = 4'b0000;\n parameter pll_lpf_res = 4'b0000;\n parameter pll_odf = 2'b00;\n parameter ref_intdiv = 5'b00000;\n parameter ref_osc_on = 1'b0;\n parameter use_cal = 1'b0;\n parameter use_pll = 1'b1;\n\n NX_PLL_U #(\n .cal_delay(cal_delay),\n .cal_div(cal_div),\n .clk_cal_sel(clk_cal_sel),\n .clk_outdiv1(clk_outdiv1),\n .clk_outdiv2(clk_outdiv2),\n .clk_outdiv3(clk_outdiv3),\n .clk_outdiv4(clk_outdiv4),\n .clk_outdivd1(clk_outdivd1),\n .clk_outdivd2(clk_outdivd2),\n .clk_outdivd3(clk_outdivd3),\n .clk_outdivd4(clk_outdivd4),\n .clk_outdivd5(clk_outdivd5),\n .ext_fbk_on(ext_fbk_on),\n .fbk_delay(fbk_delay),\n .fbk_delay_on(fbk_delay_on),\n .fbk_intdiv(fbk_intdiv),\n .location(location),\n .pll_cpump(pll_cpump),\n .pll_lock(pll_lock),\n .pll_lpf_cap(pll_lpf_cap),\n .pll_lpf_res(pll_lpf_res),\n .pll_odf(pll_odf),\n .ref_intdiv(ref_intdiv),\n .ref_osc_on(ref_osc_on),\n .use_cal(use_cal),\n .use_pll(use_pll)\n ) _TECHMAP_REPLACE_ (\n .ARST_CAL(ARST_CAL),\n .CAL1(CAL[0]),\n .CAL2(CAL[1]),\n .CAL3(CAL[2]),\n .CAL4(CAL[3]),\n .CAL5(CAL[4]),\n .CAL_LOCKED(CAL_LOCKED),\n .CLK_CAL(CLK_CAL),\n .CLK_CAL_DIV(CLK_CAL_DIV),\n .CLK_DIV1(CLK_DIV[0]),\n .CLK_DIV2(CLK_DIV[1]),\n .CLK_DIV3(CLK_DIV[2]),\n .CLK_DIV4(CLK_DIV[3]),\n .CLK_DIVD1(CLK_DIVD[0]),\n .CLK_DIVD2(CLK_DIVD[1]),\n .CLK_DIVD3(CLK_DIVD[2]),\n .CLK_DIVD4(CLK_DIVD[3]),\n .CLK_DIVD5(CLK_DIVD[4]),\n .EXT_CAL1(EXT_CAL[0]),\n .EXT_CAL2(EXT_CAL[1]),\n .EXT_CAL3(EXT_CAL[2]),\n .EXT_CAL4(EXT_CAL[3]),\n .EXT_CAL5(EXT_CAL[4]),\n .EXT_CAL_LOCKED(EXT_CAL_LOCKED),\n .FBK(FBK),\n .LDFO(LDFO),\n .OSC(OSC),\n .PLL_LOCKED(PLL_LOCKED),\n .PLL_LOCKEDA(PLL_LOCKEDA),\n .R(R),\n .REF(REF),\n .REFO(REFO),\n .VCO(VCO)\n );\nendmodule\n\nmodule NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);\n input [17:0] I;\n output [17:0] O;\n input [4:0] RA;\n input [4:0] WA;\n input WCK;\n input WE;\n input WEA;\n parameter mem_ctxt = \"\";\n parameter wck_edge = 1'b0;\n\n NX_RFB_U #(\n .mode(0),\n .mem_ctxt(mem_ctxt),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .WCK(WCK),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .O17(O[16]),\n .O18(O[17]),\n .RA1(RA[0]),\n .RA2(RA[1]),\n .RA3(RA[2]),\n .RA4(RA[3]),\n .RA5(RA[4]),\n .RA6(),\n .RA7(),\n .RA8(),\n .RA9(),\n .RA10(),\n .WA1(WA[0]),\n .WA2(WA[1]),\n .WA3(WA[2]),\n .WA4(WA[3]),\n .WA5(WA[4]),\n .WA6(),\n .WE(WE),\n .WEA(WEA)\n );\n\nendmodule\n\nmodule NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);\n input [17:0] I;\n output [17:0] O;\n input [4:0] WA;\n input WCK;\n input WE;\n input WEA;\n parameter mem_ctxt = \"\";\n parameter wck_edge = 1'b0;\n\n NX_RFB_U #(\n .mode(1),\n .mem_ctxt(mem_ctxt),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .WCK(WCK),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .O17(O[16]),\n .O18(O[17]),\n .RA1(),\n .RA2(),\n .RA3(),\n .RA4(),\n .RA5(),\n .RA6(),\n .RA7(),\n .RA8(),\n .RA9(),\n .RA10(),\n .WA1(WA[0]),\n .WA2(WA[1]),\n .WA3(WA[2]),\n .WA4(WA[3]),\n .WA5(WA[4]),\n .WA6(),\n .WE(WE),\n .WEA(WEA)\n );\nendmodule\n\nmodule NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);\n input [17:0] I;\n output [17:0] O;\n input [5:0] RA;\n input [5:0] WA;\n input WCK;\n input WE;\n input WEA;\n parameter mem_ctxt = \"\";\n parameter wck_edge = 1'b0;\n\n NX_RFB_U #(\n .mode(2),\n .mem_ctxt(mem_ctxt),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .WCK(WCK),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .O17(O[16]),\n .O18(O[17]),\n .RA1(RA[0]),\n .RA2(RA[1]),\n .RA3(RA[2]),\n .RA4(RA[3]),\n .RA5(RA[4]),\n .RA6(RA[5]),\n .RA7(),\n .RA8(),\n .RA9(),\n .RA10(),\n .WA1(WA[0]),\n .WA2(WA[1]),\n .WA3(WA[2]),\n .WA4(WA[3]),\n .WA5(WA[4]),\n .WA6(WA[5]),\n .WE(WE),\n .WEA(WEA)\n );\nendmodule\n\nmodule NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);\n input [35:0] I;\n output [35:0] O;\n input [4:0] RA;\n input [4:0] WA;\n input WCK;\n input WE;\n input WEA;\n parameter mem_ctxt = \"\";\n parameter wck_edge = 1'b0;\n\n NX_RFB_U #(\n .mode(3),\n .mem_ctxt(mem_ctxt),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .WCK(WCK),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(I[18]),\n .I20(I[19]),\n .I21(I[20]),\n .I22(I[21]),\n .I23(I[22]),\n .I24(I[23]),\n .I25(I[24]),\n .I26(I[25]),\n .I27(I[26]),\n .I28(I[27]),\n .I29(I[28]),\n .I30(I[29]),\n .I31(I[30]),\n .I32(I[31]),\n .I33(I[32]),\n .I34(I[33]),\n .I35(I[34]),\n .I36(I[35]),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .O17(O[16]),\n .O18(O[17]),\n .O19(O[18]),\n .O20(O[19]),\n .O21(O[20]),\n .O22(O[21]),\n .O23(O[22]),\n .O24(O[23]),\n .O25(O[24]),\n .O26(O[25]),\n .O27(O[26]),\n .O28(O[27]),\n .O29(O[28]),\n .O30(O[29]),\n .O31(O[30]),\n .O32(O[31]),\n .O33(O[32]),\n .O34(O[33]),\n .O35(O[34]),\n .O36(O[35]),\n .RA1(RA[0]),\n .RA2(RA[1]),\n .RA3(RA[2]),\n .RA4(RA[3]),\n .RA5(RA[4]),\n .RA6(),\n .RA7(),\n .RA8(),\n .RA9(),\n .RA10(),\n .WA1(WA[0]),\n .WA2(WA[1]),\n .WA3(WA[2]),\n .WA4(WA[3]),\n .WA5(WA[4]),\n .WA6(),\n .WE(WE),\n .WEA(WEA)\n );\nendmodule\n\nmodule NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);\n output [17:0] AO;\n input [4:0] ARA;\n output [17:0] BO;\n input [4:0] BRA;\n input [17:0] I;\n input [4:0] WA;\n input WCK;\n input WE;\n input WEA;\n parameter mem_ctxt = \"\";\n parameter wck_edge = 1'b0;\n\n NX_RFB_U #(\n .mode(32'd4),\n .mem_ctxt(mem_ctxt),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .WCK(WCK),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(AO[0]),\n .O2(AO[1]),\n .O3(AO[2]),\n .O4(AO[3]),\n .O5(AO[4]),\n .O6(AO[5]),\n .O7(AO[6]),\n .O8(AO[7]),\n .O9(AO[8]),\n .O10(AO[9]),\n .O11(AO[10]),\n .O12(AO[11]),\n .O13(AO[12]),\n .O14(AO[13]),\n .O15(AO[14]),\n .O16(AO[15]),\n .O17(AO[16]),\n .O18(AO[17]),\n .O19(BO[0]),\n .O20(BO[1]),\n .O21(BO[2]),\n .O22(BO[3]),\n .O23(BO[4]),\n .O24(BO[5]),\n .O25(BO[6]),\n .O26(BO[7]),\n .O27(BO[8]),\n .O28(BO[9]),\n .O29(BO[10]),\n .O30(BO[11]),\n .O31(BO[12]),\n .O32(BO[13]),\n .O33(BO[14]),\n .O34(BO[15]),\n .O35(BO[16]),\n .O36(BO[17]),\n .RA1(ARA[0]),\n .RA2(ARA[1]),\n .RA3(ARA[2]),\n .RA4(ARA[3]),\n .RA5(ARA[4]),\n .RA6(BRA[0]),\n .RA7(BRA[1]),\n .RA8(BRA[2]),\n .RA9(BRA[3]),\n .RA10(BRA[4]),\n .WA1(WA[0]),\n .WA2(WA[1]),\n .WA3(WA[2]),\n .WA4(WA[3]),\n .WA5(WA[4]),\n .WA6(),\n .WE(WE),\n .WEA(WEA)\n );\nendmodule\n\nmodule NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1\n, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6\n, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);\n output COR;\n output ERR;\n input I1;\n input I10;\n input I11;\n input I12;\n input I13;\n input I14;\n input I15;\n input I16;\n input I2;\n input I3;\n input I4;\n input I5;\n input I6;\n input I7;\n input I8;\n input I9;\n output O1;\n output O10;\n output O11;\n output O12;\n output O13;\n output O14;\n output O15;\n output O16;\n output O2;\n output O3;\n output O4;\n output O5;\n output O6;\n output O7;\n output O8;\n output O9;\n input RA1;\n input RA2;\n input RA3;\n input RA4;\n input RA5;\n input RA6;\n input RCK;\n input RE;\n input WA1;\n input WA2;\n input WA3;\n input WA4;\n input WA5;\n input WA6;\n input WCK;\n input WE;\n parameter addr_mask = 5'b00000;\n parameter mem_ctxt = \"\";\n parameter rck_edge = 1'b0;\n parameter wck_edge = 1'b0;\n parameter we_mask = 1'b0;\n parameter wea_mask = 1'b0;\n\n wire [15:0] D;\n wire [15:0] Q;\n\n NX_RFB_U #(\n .mem_ctxt(mem_ctxt),\n .mode(2),\n .wck_edge(wck_edge)\n ) _TECHMAP_REPLACE_ (\n .WCK(WCK),\n .I1(I1),\n .I2(I2),\n .I3(I3),\n .I4(I4),\n .I5(I5),\n .I6(I6),\n .I7(I7),\n .I8(I8),\n .I9(I9),\n .I10(I10),\n .I11(I11),\n .I12(I12),\n .I13(I13),\n .I14(I14),\n .I15(I15),\n .I16(I16),\n .I17(),\n .I18(),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(D[0]),\n .O2(D[1]),\n .O3(D[2]),\n .O4(D[3]),\n .O5(D[4]),\n .O6(D[5]),\n .O7(D[6]),\n .O8(D[7]),\n .O9(D[8]),\n .O10(D[9]),\n .O11(D[10]),\n .O12(D[11]),\n .O13(D[12]),\n .O14(D[13]),\n .O15(D[14]),\n .O16(D[15]),\n .RA1(RA1),\n .RA2(RA2),\n .RA3(RA3),\n .RA4(RA4),\n .RA5(RA5),\n .RA6(RA6),\n .RA7(),\n .RA8(),\n .RA9(),\n .RA10(),\n .WA1(WA1),\n .WA2(WA2),\n .WA3(WA3),\n .WA4(WA4),\n .WA5(WA5),\n .WA6(WA6),\n .WE(WE),\n .WEA()\n );\n\n genvar i;\n generate for (i = 0; i < 16; i = i + 1) begin:q_reg\n NX_DFF #(\n .dff_edge(rck_edge),\n .dff_init(1'b0),\n .dff_load(1'b1)\n ) out_reg_i (\n .CK(RCK),\n .I(D[i]),\n .L(RE),\n .R(),\n .O(Q[i])\n );\n end endgenerate;\n assign O1=Q[0];\n assign O2=Q[1];\n assign O3=Q[2];\n assign O4=Q[3];\n assign O5=Q[4];\n assign O6=Q[5];\n assign O7=Q[6];\n assign O8=Q[7];\n assign O9=Q[8];\n assign O10=Q[9];\n assign O11=Q[10];\n assign O12=Q[11];\n assign O13=Q[12];\n assign O14=Q[13];\n assign O15=Q[14];\n assign O16=Q[15];\n\n assign COR=1'b0;\n assign ERR=1'b0;\nendmodule\n\nmodule NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);\n input [17:0] I;\n output [17:0] O;\n input [5:0] RAI;\n output [5:0] RAO;\n input RCK;\n output REQ;\n input RRSTI;\n output RRSTO;\n input [5:0] WAI;\n output [5:0] WAO;\n input WCK;\n input WE;\n input WEA;\n output WEQ;\n input WRSTI;\n output WRSTO;\n parameter rck_edge = 1'b0;\n parameter read_addr_inv = 6'b000000;\n parameter use_read_arst = 1'b0;\n parameter use_write_arst = 1'b0;\n parameter wck_edge = 1'b0;\n\n NX_FIFO_U #(\n .mode(0),\n .wck_edge(wck_edge),\n .rck_edge(rck_edge),\n .read_addr_inv(read_addr_inv),\n .use_write_arst(use_write_arst),\n .use_read_arst(use_read_arst)\n ) _TECHMAP_REPLACE_ (\n .RCK(RCK),\n .WCK(WCK),\n .WE(WE),\n .WEA(WEA),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .O17(O[16]),\n .O18(O[17]),\n .WRSTI(WRSTI),\n .WAI1(WAI[0]),\n .WAI2(WAI[1]),\n .WAI3(WAI[2]),\n .WAI4(WAI[3]),\n .WAI5(WAI[4]),\n .WAI6(WAI[5]),\n .WAI7(),\n .WRSTO(WRSTO),\n .WAO1(WAO[0]),\n .WAO2(WAO[1]),\n .WAO3(WAO[2]),\n .WAO4(WAO[3]),\n .WAO5(WAO[4]),\n .WAO6(WAO[5]),\n .WEQ1(WEQ),\n .RRSTI(RRSTI),\n .RAI1(RAI[0]),\n .RAI2(RAI[1]),\n .RAI3(RAI[2]),\n .RAI4(RAI[3]),\n .RAI5(RAI[4]),\n .RAI6(RAI[5]),\n .RAI7(),\n .RRSTO(RRSTO),\n .RAO1(RAO[0]),\n .RAO2(RAO[1]),\n .RAO3(RAO[2]),\n .RAO4(RAO[3]),\n .RAO5(RAO[4]),\n .RAO6(RAO[5]),\n .REQ1(REQ)\n );\nendmodule\n\nmodule NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);\n input [17:0] I;\n output [17:0] O;\n input [6:0] RAI;\n output [6:0] RAO;\n input RCK;\n output [1:0] REQ;\n input RRSTI;\n input [6:0] WAI;\n output [6:0] WAO;\n input WCK;\n input WE;\n input WEA;\n output [1:0] WEQ;\n input WRSTI;\n parameter rck_edge = 1'b0;\n parameter read_addr_inv = 7'b0000000;\n parameter use_read_arst = 1'b0;\n parameter use_write_arst = 1'b0;\n parameter wck_edge = 1'b0;\n\n NX_FIFO_U #(\n .mode(1),\n .wck_edge(wck_edge),\n .rck_edge(rck_edge),\n .read_addr_inv(read_addr_inv),\n .use_write_arst(use_write_arst),\n .use_read_arst(use_read_arst)\n ) _TECHMAP_REPLACE_ (\n .RCK(RCK),\n .WCK(WCK),\n .WE(WE),\n .WEA(WEA),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .O17(O[16]),\n .O18(O[17]),\n .WRSTI(WRSTI),\n .WAI1(WAI[0]),\n .WAI2(WAI[1]),\n .WAI3(WAI[2]),\n .WAI4(WAI[3]),\n .WAI5(WAI[4]),\n .WAI6(WAI[5]),\n .WAI7(WAI[6]),\n .WAO1(WAO[0]),\n .WAO2(WAO[1]),\n .WAO3(WAO[2]),\n .WAO4(WAO[3]),\n .WAO5(WAO[4]),\n .WAO6(WAO[5]),\n .WAO7(WAO[6]),\n .WEQ1(WEQ[0]),\n .WEQ2(WEQ[1]),\n .RRSTI(RRSTI),\n .RAI1(RAI[0]),\n .RAI2(RAI[1]),\n .RAI3(RAI[2]),\n .RAI4(RAI[3]),\n .RAI5(RAI[4]),\n .RAI6(RAI[5]),\n .RAI7(RAI[6]),\n .RAO1(RAO[0]),\n .RAO2(RAO[1]),\n .RAO3(RAO[2]),\n .RAO4(RAO[3]),\n .RAO5(RAO[4]),\n .RAO6(RAO[5]),\n .RAO7(RAO[6]),\n .REQ1(REQ[0]),\n .REQ2(REQ[1])\n );\nendmodule\n\nmodule NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);\n input [35:0] I;\n output [35:0] O;\n input [5:0] RAI;\n output [5:0] RAO;\n input RCK;\n output REQ;\n input RRSTI;\n input [5:0] WAI;\n output [5:0] WAO;\n input WCK;\n input WE;\n input WEA;\n output WEQ;\n input WRSTI;\n parameter rck_edge = 1'b0;\n parameter read_addr_inv = 7'b0000000;\n parameter use_read_arst = 1'b0;\n parameter use_write_arst = 1'b0;\n parameter wck_edge = 1'b0;\n\n NX_FIFO_U #(\n .mode(2),\n .wck_edge(wck_edge),\n .rck_edge(rck_edge),\n .read_addr_inv(read_addr_inv),\n .use_write_arst(use_write_arst),\n .use_read_arst(use_read_arst)\n ) _TECHMAP_REPLACE_ (\n .RCK(RCK),\n .WCK(WCK),\n .WE(WE),\n .WEA(WEA),\n .I1(I[0]),\n .I2(I[1]),\n .I3(I[2]),\n .I4(I[3]),\n .I5(I[4]),\n .I6(I[5]),\n .I7(I[6]),\n .I8(I[7]),\n .I9(I[8]),\n .I10(I[9]),\n .I11(I[10]),\n .I12(I[11]),\n .I13(I[12]),\n .I14(I[13]),\n .I15(I[14]),\n .I16(I[15]),\n .I17(I[16]),\n .I18(I[17]),\n .I19(I[18]),\n .I20(I[19]),\n .I21(I[20]),\n .I22(I[21]),\n .I23(I[22]),\n .I24(I[23]),\n .I25(I[24]),\n .I26(I[25]),\n .I27(I[26]),\n .I28(I[27]),\n .I29(I[28]),\n .I30(I[29]),\n .I31(I[30]),\n .I32(I[31]),\n .I33(I[32]),\n .I34(I[33]),\n .I35(I[34]),\n .I36(I[35]),\n .O1(O[0]),\n .O2(O[1]),\n .O3(O[2]),\n .O4(O[3]),\n .O5(O[4]),\n .O6(O[5]),\n .O7(O[6]),\n .O8(O[7]),\n .O9(O[8]),\n .O10(O[9]),\n .O11(O[10]),\n .O12(O[11]),\n .O13(O[12]),\n .O14(O[13]),\n .O15(O[14]),\n .O16(O[15]),\n .O17(O[16]),\n .O18(O[17]),\n .O19(O[18]),\n .O20(O[19]),\n .O21(O[20]),\n .O22(O[21]),\n .O23(O[22]),\n .O24(O[23]),\n .O25(O[24]),\n .O26(O[25]),\n .O27(O[26]),\n .O28(O[27]),\n .O29(O[28]),\n .O30(O[29]),\n .O31(O[30]),\n .O32(O[31]),\n .O33(O[32]),\n .O34(O[33]),\n .O35(O[34]),\n .O36(O[35]),\n .WRSTI(WRSTI),\n .WAI1(WAI[0]),\n .WAI2(WAI[1]),\n .WAI3(WAI[2]),\n .WAI4(WAI[3]),\n .WAI5(WAI[4]),\n .WAI6(WAI[5]),\n .WAI7(),\n .WAO1(WAO[0]),\n .WAO2(WAO[1]),\n .WAO3(WAO[2]),\n .WAO4(WAO[3]),\n .WAO5(WAO[4]),\n .WAO6(WAO[5]),\n .WEQ1(WEQ),\n .RRSTI(RRSTI),\n .RAI1(RAI[0]),\n .RAI2(RAI[1]),\n .RAI3(RAI[2]),\n .RAI4(RAI[3]),\n .RAI5(RAI[4]),\n .RAI6(RAI[5]),\n .RAI7(),\n .RAO1(RAO[0]),\n .RAO2(RAO[1]),\n .RAO3(RAO[2]),\n .RAO4(RAO[3]),\n .RAO5(RAO[4]),\n .RAO6(RAO[5]),\n .REQ1(REQ)\n );\nendmodule\n\n//TODO\nmodule ACC84_2DSP(clk, rst, X, Z);\n input [83:0] X;\n output [84:0] Z;\n input clk;\n input rst;\n parameter g_pipe = 2;\nendmodule\n\n//TODO\nmodule ACC92_2DSP(clk, rst, X, Z);\n input [55:0] X;\n output [91:0] Z;\n input clk;\n input rst;\n parameter g_pipe = 2;\nendmodule\n\n//TODO\nmodule ACC98_2DSP(clk, rst, X, Z);\n input [55:0] X;\n output [97:0] Z;\n input clk;\n input rst;\n parameter g_pipe = 2;\nendmodule\n\n//TODO\nmodule ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z);\n input [41:0] X;\n input [41:0] Y;\n output [84:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule ADD84_2DSP(clk, rst, X, Y, Z);\n input [83:0] X;\n input [83:0] Y;\n output [84:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule SMACC24x18_1DSP(clk, rst, A, B, Z);\n input [23:0] A;\n input [17:0] B;\n output [55:0] Z;\n input clk;\n input rst;\n parameter g_pipe = 1;\nendmodule\n\n//TODO\nmodule SMACC24x32_2DSP(clk, rst, A, B, Z);\n input [23:0] A;\n input [31:0] B;\n output [55:0] Z;\n input clk;\n input rst;\n parameter g_pipe = 1;\nendmodule\n\n//TODO\nmodule SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z);\n input [23:0] A;\n input [31:0] B;\n output [55:0] Z;\n input clk;\n input rst;\n input we;\n parameter STAGE_1 = \"false\";\n parameter STAGE_2 = \"false\";\n parameter STAGE_3 = \"false\";\n parameter STAGE_4 = \"false\";\nendmodule\n\n//TODO\nmodule SMUL24x32_2DSP(clk, rst, A, B, Z);\n input [23:0] A;\n input [31:0] B;\n output [54:0] Z;\n input clk;\n input rst;\n parameter g_pipe = 1;\nendmodule\n\n//TODO\nmodule SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z);\n input [23:0] A;\n input [31:0] B;\n output [97:0] Z;\n input clk;\n input rst;\n input we;\n parameter STAGE_1 = \"false\";\n parameter STAGE_2 = \"false\";\n parameter STAGE_3 = \"false\";\nendmodule\n\n//TODO\nmodule SMUL47x35_4DSP(clk, rst, A, B, Z);\n input [46:0] A;\n input [34:0] B;\n output [80:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule UMADD24_2DSP(clk, rst, A, B, C, Z);\n input [23:0] A;\n input [31:0] B;\n input [55:0] C;\n output [55:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z);\n input [23:0] A;\n input [15:0] B;\n output [55:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule UMUL24x32_2DSP(clk, rst, A, B, Z);\n input [23:0] A;\n input [31:0] B;\n output [55:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z);\n input [23:0] A;\n input [17:0] B;\n output [59:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule UMUL24x36_2DSP(clk, rst, A, B, Z);\n input [23:0] A;\n input [35:0] B;\n output [59:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z);\n input [23:0] A;\n input [17:0] B;\n output [83:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule UMUL48x36_4DSP(clk, rst, A, B, Z);\n input [47:0] A;\n input [35:0] B;\n output [83:0] Z;\n input clk;\n input rst;\n parameter piped = \"true\";\nendmodule\n\n//TODO\nmodule NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i\n, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o\n, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o\n, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i\n, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i\n, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o\n, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o\n, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i\n, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i\n, usr_dyn_cfg_lane_cs_n_i);\n input hssl_clk_ref_i;\n input hssl_clk_user_rx_i;\n input hssl_clk_user_tx_i;\n output hssl_clock_o;\n output hssl_rclock_o;\n input scan_en_i;\n input [7:0] scan_in_i;\n output [7:0] scan_out_o;\n output usr_calibrate_pma_out_o;\n input [3:0] usr_dyn_cfg_addr_i;\n input usr_dyn_cfg_calibration_cs_n_i;\n input usr_dyn_cfg_en_i;\n input [3:0] usr_dyn_cfg_lane_cs_n_i;\n input [11:0] usr_dyn_cfg_wdata_i;\n input usr_dyn_cfg_wdata_sel_i;\n input usr_dyn_cfg_we_n_i;\n input usr_main_async_debug_ack_i;\n input [1:0] usr_main_async_debug_lane_sel_i;\n output usr_main_async_debug_req_o;\n input usr_main_rst_n_i;\n output [19:0] usr_main_rx_pma_ll_out_o;\n output usr_pll_ckfb_lock_o;\n output usr_pll_lock_o;\n output usr_pll_pma_lock_analog_o;\n input usr_pll_pma_pwr_down_n_i;\n input usr_pll_pma_rst_n_i;\n output usr_rx0_busy_o;\n input usr_rx0_ctrl_align_en_i;\n input usr_rx0_ctrl_align_sync_i;\n output [7:0] usr_rx0_ctrl_char_is_a_o;\n output usr_rx0_ctrl_char_is_aligned_o;\n output [7:0] usr_rx0_ctrl_char_is_comma_o;\n output [7:0] usr_rx0_ctrl_char_is_f_o;\n output [7:0] usr_rx0_ctrl_char_is_k_o;\n input [2:0] usr_rx0_ctrl_debug_sel_i;\n input usr_rx0_ctrl_dec_en_i;\n output [7:0] usr_rx0_ctrl_disp_err_o;\n input usr_rx0_ctrl_dscr_en_i;\n input usr_rx0_ctrl_el_buff_rst_i;\n output [7:0] usr_rx0_ctrl_not_in_table_o;\n input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;\n input usr_rx0_ctrl_replace_en_i;\n output usr_rx0_ctrl_valid_realign_o;\n output [63:0] usr_rx0_data_o;\n output usr_rx0_pma_ll_fast_locked_o;\n output usr_rx0_pma_ll_slow_locked_o;\n output usr_rx0_pma_loss_of_signal_o;\n input usr_rx0_pma_m_eye_rst_i;\n output usr_rx0_pma_pll_lock_o;\n output usr_rx0_pma_pll_lock_track_o;\n input usr_rx0_pma_pwr_down_n_i;\n input usr_rx0_pma_rst_n_i;\n input usr_rx0_rst_n_i;\n output [7:0] usr_rx0_test_o;\n output usr_rx1_busy_o;\n input usr_rx1_ctrl_align_en_i;\n input usr_rx1_ctrl_align_sync_i;\n output [7:0] usr_rx1_ctrl_char_is_a_o;\n output usr_rx1_ctrl_char_is_aligned_o;\n output [7:0] usr_rx1_ctrl_char_is_comma_o;\n output [7:0] usr_rx1_ctrl_char_is_f_o;\n output [7:0] usr_rx1_ctrl_char_is_k_o;\n input [2:0] usr_rx1_ctrl_debug_sel_i;\n input usr_rx1_ctrl_dec_en_i;\n output [7:0] usr_rx1_ctrl_disp_err_o;\n input usr_rx1_ctrl_dscr_en_i;\n input usr_rx1_ctrl_el_buff_rst_i;\n output [7:0] usr_rx1_ctrl_not_in_table_o;\n input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;\n input usr_rx1_ctrl_replace_en_i;\n output usr_rx1_ctrl_valid_realign_o;\n output [63:0] usr_rx1_data_o;\n output usr_rx1_pma_ll_fast_locked_o;\n output usr_rx1_pma_ll_slow_locked_o;\n output usr_rx1_pma_loss_of_signal_o;\n input usr_rx1_pma_m_eye_rst_i;\n output usr_rx1_pma_pll_lock_o;\n output usr_rx1_pma_pll_lock_track_o;\n input usr_rx1_pma_pwr_down_n_i;\n input usr_rx1_pma_rst_n_i;\n input usr_rx1_rst_n_i;\n output [7:0] usr_rx1_test_o;\n output usr_rx2_busy_o;\n input usr_rx2_ctrl_align_en_i;\n input usr_rx2_ctrl_align_sync_i;\n output [7:0] usr_rx2_ctrl_char_is_a_o;\n output usr_rx2_ctrl_char_is_aligned_o;\n output [7:0] usr_rx2_ctrl_char_is_comma_o;\n output [7:0] usr_rx2_ctrl_char_is_f_o;\n output [7:0] usr_rx2_ctrl_char_is_k_o;\n input [2:0] usr_rx2_ctrl_debug_sel_i;\n input usr_rx2_ctrl_dec_en_i;\n output [7:0] usr_rx2_ctrl_disp_err_o;\n input usr_rx2_ctrl_dscr_en_i;\n input usr_rx2_ctrl_el_buff_rst_i;\n output [7:0] usr_rx2_ctrl_not_in_table_o;\n input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;\n input usr_rx2_ctrl_replace_en_i;\n output usr_rx2_ctrl_valid_realign_o;\n output [63:0] usr_rx2_data_o;\n output usr_rx2_pma_ll_fast_locked_o;\n output usr_rx2_pma_ll_slow_locked_o;\n output usr_rx2_pma_loss_of_signal_o;\n input usr_rx2_pma_m_eye_rst_i;\n output usr_rx2_pma_pll_lock_o;\n output usr_rx2_pma_pll_lock_track_o;\n input usr_rx2_pma_pwr_down_n_i;\n input usr_rx2_pma_rst_n_i;\n input usr_rx2_rst_n_i;\n output [7:0] usr_rx2_test_o;\n output usr_rx3_busy_o;\n input usr_rx3_ctrl_align_en_i;\n input usr_rx3_ctrl_align_sync_i;\n output [7:0] usr_rx3_ctrl_char_is_a_o;\n output usr_rx3_ctrl_char_is_aligned_o;\n output [7:0] usr_rx3_ctrl_char_is_comma_o;\n output [7:0] usr_rx3_ctrl_char_is_f_o;\n output [7:0] usr_rx3_ctrl_char_is_k_o;\n input [2:0] usr_rx3_ctrl_debug_sel_i;\n input usr_rx3_ctrl_dec_en_i;\n output [7:0] usr_rx3_ctrl_disp_err_o;\n input usr_rx3_ctrl_dscr_en_i;\n input usr_rx3_ctrl_el_buff_rst_i;\n output [7:0] usr_rx3_ctrl_not_in_table_o;\n input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;\n input usr_rx3_ctrl_replace_en_i;\n output usr_rx3_ctrl_valid_realign_o;\n output [63:0] usr_rx3_data_o;\n output usr_rx3_pma_ll_fast_locked_o;\n output usr_rx3_pma_ll_slow_locked_o;\n output usr_rx3_pma_loss_of_signal_o;\n input usr_rx3_pma_m_eye_rst_i;\n output usr_rx3_pma_pll_lock_o;\n output usr_rx3_pma_pll_lock_track_o;\n input usr_rx3_pma_pwr_down_n_i;\n input usr_rx3_pma_rst_n_i;\n input usr_rx3_rst_n_i;\n output [7:0] usr_rx3_test_o;\n output usr_tx0_busy_o;\n input [7:0] usr_tx0_ctrl_char_is_k_i;\n input usr_tx0_ctrl_driver_pwrdwn_n_i;\n input [7:0] usr_tx0_ctrl_enc_en_i;\n input [7:0] usr_tx0_ctrl_end_of_frame_i;\n input [7:0] usr_tx0_ctrl_end_of_multiframe_i;\n output usr_tx0_ctrl_invalid_k_o;\n input usr_tx0_ctrl_replace_en_i;\n input [7:0] usr_tx0_ctrl_scr_en_i;\n input [63:0] usr_tx0_data_i;\n input usr_tx0_pma_clk_en_i;\n output usr_tx0_pma_tx_clk_o;\n input usr_tx0_rst_n_i;\n output usr_tx1_busy_o;\n input [7:0] usr_tx1_ctrl_char_is_k_i;\n input usr_tx1_ctrl_driver_pwrdwn_n_i;\n input [7:0] usr_tx1_ctrl_enc_en_i;\n input [7:0] usr_tx1_ctrl_end_of_frame_i;\n input [7:0] usr_tx1_ctrl_end_of_multiframe_i;\n output usr_tx1_ctrl_invalid_k_o;\n input usr_tx1_ctrl_replace_en_i;\n input [7:0] usr_tx1_ctrl_scr_en_i;\n input [63:0] usr_tx1_data_i;\n input usr_tx1_pma_clk_en_i;\n output usr_tx1_pma_tx_clk_o;\n input usr_tx1_rst_n_i;\n output usr_tx2_busy_o;\n input [7:0] usr_tx2_ctrl_char_is_k_i;\n input usr_tx2_ctrl_driver_pwrdwn_n_i;\n input [7:0] usr_tx2_ctrl_enc_en_i;\n input [7:0] usr_tx2_ctrl_end_of_frame_i;\n input [7:0] usr_tx2_ctrl_end_of_multiframe_i;\n output usr_tx2_ctrl_invalid_k_o;\n input usr_tx2_ctrl_replace_en_i;\n input [7:0] usr_tx2_ctrl_scr_en_i;\n input [63:0] usr_tx2_data_i;\n input usr_tx2_pma_clk_en_i;\n output usr_tx2_pma_tx_clk_o;\n input usr_tx2_rst_n_i;\n output usr_tx3_busy_o;\n input [7:0] usr_tx3_ctrl_char_is_k_i;\n input usr_tx3_ctrl_driver_pwrdwn_n_i;\n input [7:0] usr_tx3_ctrl_enc_en_i;\n input [7:0] usr_tx3_ctrl_end_of_frame_i;\n input [7:0] usr_tx3_ctrl_end_of_multiframe_i;\n output usr_tx3_ctrl_invalid_k_o;\n input usr_tx3_ctrl_replace_en_i;\n input [7:0] usr_tx3_ctrl_scr_en_i;\n input [63:0] usr_tx3_data_i;\n input usr_tx3_pma_clk_en_i;\n output usr_tx3_pma_tx_clk_o;\n input usr_tx3_rst_n_i;\n parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0;\n parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0;\n parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0;\n parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0;\n parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000;\n parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0;\n parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000;\n parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000;\n parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000;\n parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00;\n parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000;\n parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000;\n parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000;\n parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000;\n parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000;\n parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000;\n parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000;\n parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000;\n parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000;\n parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000;\n parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000;\n parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000;\n parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000;\n parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000;\n parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000;\n parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000;\n parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000;\n parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000;\n parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000;\n parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000;\n parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000;\n parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000;\n parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000;\n parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000;\n parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000;\n parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000;\n parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000;\n parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000;\n parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000;\n parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000;\n parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0;\n parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000;\n parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000;\n parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000;\n parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000;\n parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0;\n parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0;\n parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000;\n parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0;\n parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000;\n parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0;\n parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000;\n parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000;\n parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000;\n parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000;\n parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0;\n parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0;\n parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000;\n parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0;\n parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000;\n parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0;\n parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000;\n parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000;\n parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000;\n parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000;\n parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0;\n parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0;\n parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000;\n parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0;\n parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000;\n parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0;\n parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000;\n parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000;\n parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000;\n parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000;\n parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0;\n parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0;\n parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000;\n parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0;\n parameter cfg_main_clk_to_fabric_div_en_i = 1'b0;\n parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0;\n parameter cfg_main_clk_to_fabric_sel_i = 1'b0;\n parameter cfg_main_rclk_to_fabric_sel_i = 2'b00;\n parameter cfg_main_use_only_usr_clock_i = 1'b0;\n parameter cfg_pcs_ovs_en_i = 1'b0;\n parameter cfg_pcs_ovs_mode_i = 1'b0;\n parameter cfg_pcs_pll_lock_ppm_i = 3'b000;\n parameter cfg_pcs_word_len_i = 2'b00;\n parameter cfg_pll_pma_ckref_ext_i = 1'b0;\n parameter cfg_pll_pma_cpump_i = 4'b0000;\n parameter cfg_pll_pma_divl_i = 2'b00;\n parameter cfg_pll_pma_divm_i = 1'b0;\n parameter cfg_pll_pma_divn_i = 2'b00;\n parameter cfg_pll_pma_gbx_en_i = 1'b0;\n parameter cfg_pll_pma_int_data_len_i = 1'b0;\n parameter cfg_pll_pma_lvds_en_i = 1'b0;\n parameter cfg_pll_pma_lvds_mux_i = 1'b0;\n parameter cfg_pll_pma_mux_ckref_i = 1'b0;\n parameter cfg_rx0_gearbox_en_i = 1'b0;\n parameter cfg_rx0_gearbox_mode_i = 1'b0;\n parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0;\n parameter cfg_rx0_pcs_align_bypass_i = 1'b0;\n parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0;\n parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0;\n parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000;\n parameter cfg_rx0_pcs_debug_en_i = 1'b0;\n parameter cfg_rx0_pcs_dec_bypass_i = 1'b0;\n parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0;\n parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000;\n parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000;\n parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0;\n parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000;\n parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00;\n parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00;\n parameter cfg_rx0_pcs_fsm_sel_i = 2'b00;\n parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0;\n parameter cfg_rx0_pcs_loopback_i = 1'b0;\n parameter cfg_rx0_pcs_m_comma_en_i = 1'b0;\n parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000;\n parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00;\n parameter cfg_rx0_pcs_p_comma_en_i = 1'b0;\n parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000;\n parameter cfg_rx0_pcs_polarity_i = 1'b0;\n parameter cfg_rx0_pcs_protocol_size_i = 1'b0;\n parameter cfg_rx0_pcs_replace_bypass_i = 1'b0;\n parameter cfg_rx0_pcs_sync_supported_i = 1'b0;\n parameter cfg_rx0_pma_cdr_cp_i = 4'b0000;\n parameter cfg_rx0_pma_clk_pos_i = 1'b0;\n parameter cfg_rx0_pma_coarse_ppm_i = 3'b000;\n parameter cfg_rx0_pma_ctrl_term_i = 6'b000000;\n parameter cfg_rx0_pma_dco_divl_i = 2'b00;\n parameter cfg_rx0_pma_dco_divm_i = 1'b0;\n parameter cfg_rx0_pma_dco_divn_i = 2'b00;\n parameter cfg_rx0_pma_dco_reg_res_i = 2'b00;\n parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0;\n parameter cfg_rx0_pma_fine_ppm_i = 3'b000;\n parameter cfg_rx0_pma_loopback_i = 1'b0;\n parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000;\n parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00;\n parameter cfg_rx0_pma_peak_detect_on_i = 1'b0;\n parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000;\n parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0;\n parameter cfg_rx0_pma_pll_divf_i = 2'b00;\n parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0;\n parameter cfg_rx0_pma_pll_divm_i = 2'b00;\n parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0;\n parameter cfg_rx0_pma_pll_divn_i = 1'b0;\n parameter cfg_rx1_gearbox_en_i = 1'b0;\n parameter cfg_rx1_gearbox_mode_i = 1'b0;\n parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0;\n parameter cfg_rx1_pcs_align_bypass_i = 1'b0;\n parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0;\n parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0;\n parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000;\n parameter cfg_rx1_pcs_debug_en_i = 1'b0;\n parameter cfg_rx1_pcs_dec_bypass_i = 1'b0;\n parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0;\n parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000;\n parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000;\n parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0;\n parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000;\n parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00;\n parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00;\n parameter cfg_rx1_pcs_fsm_sel_i = 2'b00;\n parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0;\n parameter cfg_rx1_pcs_loopback_i = 1'b0;\n parameter cfg_rx1_pcs_m_comma_en_i = 1'b0;\n parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000;\n parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00;\n parameter cfg_rx1_pcs_p_comma_en_i = 1'b0;\n parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000;\n parameter cfg_rx1_pcs_polarity_i = 1'b0;\n parameter cfg_rx1_pcs_protocol_size_i = 1'b0;\n parameter cfg_rx1_pcs_replace_bypass_i = 1'b0;\n parameter cfg_rx1_pcs_sync_supported_i = 1'b0;\n parameter cfg_rx1_pma_cdr_cp_i = 4'b0000;\n parameter cfg_rx1_pma_clk_pos_i = 1'b0;\n parameter cfg_rx1_pma_coarse_ppm_i = 3'b000;\n parameter cfg_rx1_pma_ctrl_term_i = 6'b000000;\n parameter cfg_rx1_pma_dco_divl_i = 2'b00;\n parameter cfg_rx1_pma_dco_divm_i = 1'b0;\n parameter cfg_rx1_pma_dco_divn_i = 2'b00;\n parameter cfg_rx1_pma_dco_reg_res_i = 2'b00;\n parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0;\n parameter cfg_rx1_pma_fine_ppm_i = 3'b000;\n parameter cfg_rx1_pma_loopback_i = 1'b0;\n parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000;\n parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00;\n parameter cfg_rx1_pma_peak_detect_on_i = 1'b0;\n parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000;\n parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0;\n parameter cfg_rx1_pma_pll_divf_i = 2'b00;\n parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0;\n parameter cfg_rx1_pma_pll_divm_i = 2'b00;\n parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0;\n parameter cfg_rx1_pma_pll_divn_i = 1'b0;\n parameter cfg_rx2_gearbox_en_i = 1'b0;\n parameter cfg_rx2_gearbox_mode_i = 1'b0;\n parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0;\n parameter cfg_rx2_pcs_align_bypass_i = 1'b0;\n parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0;\n parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0;\n parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000;\n parameter cfg_rx2_pcs_debug_en_i = 1'b0;\n parameter cfg_rx2_pcs_dec_bypass_i = 1'b0;\n parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0;\n parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000;\n parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000;\n parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0;\n parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000;\n parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00;\n parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00;\n parameter cfg_rx2_pcs_fsm_sel_i = 2'b00;\n parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0;\n parameter cfg_rx2_pcs_loopback_i = 1'b0;\n parameter cfg_rx2_pcs_m_comma_en_i = 1'b0;\n parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000;\n parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00;\n parameter cfg_rx2_pcs_p_comma_en_i = 1'b0;\n parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000;\n parameter cfg_rx2_pcs_polarity_i = 1'b0;\n parameter cfg_rx2_pcs_protocol_size_i = 1'b0;\n parameter cfg_rx2_pcs_replace_bypass_i = 1'b0;\n parameter cfg_rx2_pcs_sync_supported_i = 1'b0;\n parameter cfg_rx2_pma_cdr_cp_i = 4'b0000;\n parameter cfg_rx2_pma_clk_pos_i = 1'b0;\n parameter cfg_rx2_pma_coarse_ppm_i = 3'b000;\n parameter cfg_rx2_pma_ctrl_term_i = 6'b000000;\n parameter cfg_rx2_pma_dco_divl_i = 2'b00;\n parameter cfg_rx2_pma_dco_divm_i = 1'b0;\n parameter cfg_rx2_pma_dco_divn_i = 2'b00;\n parameter cfg_rx2_pma_dco_reg_res_i = 2'b00;\n parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0;\n parameter cfg_rx2_pma_fine_ppm_i = 3'b000;\n parameter cfg_rx2_pma_loopback_i = 1'b0;\n parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000;\n parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00;\n parameter cfg_rx2_pma_peak_detect_on_i = 1'b0;\n parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000;\n parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0;\n parameter cfg_rx2_pma_pll_divf_i = 2'b00;\n parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0;\n parameter cfg_rx2_pma_pll_divm_i = 2'b00;\n parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0;\n parameter cfg_rx2_pma_pll_divn_i = 1'b0;\n parameter cfg_rx3_gearbox_en_i = 1'b0;\n parameter cfg_rx3_gearbox_mode_i = 1'b0;\n parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0;\n parameter cfg_rx3_pcs_align_bypass_i = 1'b0;\n parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0;\n parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0;\n parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000;\n parameter cfg_rx3_pcs_debug_en_i = 1'b0;\n parameter cfg_rx3_pcs_dec_bypass_i = 1'b0;\n parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0;\n parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000;\n parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000;\n parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0;\n parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000;\n parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00;\n parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00;\n parameter cfg_rx3_pcs_fsm_sel_i = 2'b00;\n parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0;\n parameter cfg_rx3_pcs_loopback_i = 1'b0;\n parameter cfg_rx3_pcs_m_comma_en_i = 1'b0;\n parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000;\n parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00;\n parameter cfg_rx3_pcs_p_comma_en_i = 1'b0;\n parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000;\n parameter cfg_rx3_pcs_polarity_i = 1'b0;\n parameter cfg_rx3_pcs_protocol_size_i = 1'b0;\n parameter cfg_rx3_pcs_replace_bypass_i = 1'b0;\n parameter cfg_rx3_pcs_sync_supported_i = 1'b0;\n parameter cfg_rx3_pma_cdr_cp_i = 4'b0000;\n parameter cfg_rx3_pma_clk_pos_i = 1'b0;\n parameter cfg_rx3_pma_coarse_ppm_i = 3'b000;\n parameter cfg_rx3_pma_ctrl_term_i = 6'b000000;\n parameter cfg_rx3_pma_dco_divl_i = 2'b00;\n parameter cfg_rx3_pma_dco_divm_i = 1'b0;\n parameter cfg_rx3_pma_dco_divn_i = 2'b00;\n parameter cfg_rx3_pma_dco_reg_res_i = 2'b00;\n parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0;\n parameter cfg_rx3_pma_fine_ppm_i = 3'b000;\n parameter cfg_rx3_pma_loopback_i = 1'b0;\n parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000;\n parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00;\n parameter cfg_rx3_pma_peak_detect_on_i = 1'b0;\n parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000;\n parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0;\n parameter cfg_rx3_pma_pll_divf_i = 2'b00;\n parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0;\n parameter cfg_rx3_pma_pll_divm_i = 2'b00;\n parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0;\n parameter cfg_rx3_pma_pll_divn_i = 1'b0;\n parameter cfg_test_mode_i = 2'b00;\n parameter cfg_tx0_gearbox_en_i = 1'b0;\n parameter cfg_tx0_gearbox_mode_i = 1'b0;\n parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0;\n parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_tx0_pcs_enc_bypass_i = 1'b0;\n parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0;\n parameter cfg_tx0_pcs_loopback_i = 1'b0;\n parameter cfg_tx0_pcs_polarity_i = 1'b0;\n parameter cfg_tx0_pcs_protocol_size_i = 1'b0;\n parameter cfg_tx0_pcs_replace_bypass_i = 1'b0;\n parameter cfg_tx0_pcs_scr_bypass_i = 1'b0;\n parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000;\n parameter cfg_tx0_pcs_sync_supported_i = 1'b0;\n parameter cfg_tx0_pma_clk_pos_i = 1'b0;\n parameter cfg_tx0_pma_loopback_i = 1'b0;\n parameter cfg_tx1_gearbox_en_i = 1'b0;\n parameter cfg_tx1_gearbox_mode_i = 1'b0;\n parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0;\n parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_tx1_pcs_enc_bypass_i = 1'b0;\n parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0;\n parameter cfg_tx1_pcs_loopback_i = 1'b0;\n parameter cfg_tx1_pcs_polarity_i = 1'b0;\n parameter cfg_tx1_pcs_protocol_size_i = 1'b0;\n parameter cfg_tx1_pcs_replace_bypass_i = 1'b0;\n parameter cfg_tx1_pcs_scr_bypass_i = 1'b0;\n parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000;\n parameter cfg_tx1_pcs_sync_supported_i = 1'b0;\n parameter cfg_tx1_pma_clk_pos_i = 1'b0;\n parameter cfg_tx1_pma_loopback_i = 1'b0;\n parameter cfg_tx2_gearbox_en_i = 1'b0;\n parameter cfg_tx2_gearbox_mode_i = 1'b0;\n parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0;\n parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_tx2_pcs_enc_bypass_i = 1'b0;\n parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0;\n parameter cfg_tx2_pcs_loopback_i = 1'b0;\n parameter cfg_tx2_pcs_polarity_i = 1'b0;\n parameter cfg_tx2_pcs_protocol_size_i = 1'b0;\n parameter cfg_tx2_pcs_replace_bypass_i = 1'b0;\n parameter cfg_tx2_pcs_scr_bypass_i = 1'b0;\n parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000;\n parameter cfg_tx2_pcs_sync_supported_i = 1'b0;\n parameter cfg_tx2_pma_clk_pos_i = 1'b0;\n parameter cfg_tx2_pma_loopback_i = 1'b0;\n parameter cfg_tx3_gearbox_en_i = 1'b0;\n parameter cfg_tx3_gearbox_mode_i = 1'b0;\n parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0;\n parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0;\n parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0;\n parameter cfg_tx3_pcs_enc_bypass_i = 1'b0;\n parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0;\n parameter cfg_tx3_pcs_loopback_i = 1'b0;\n parameter cfg_tx3_pcs_polarity_i = 1'b0;\n parameter cfg_tx3_pcs_protocol_size_i = 1'b0;\n parameter cfg_tx3_pcs_replace_bypass_i = 1'b0;\n parameter cfg_tx3_pcs_scr_bypass_i = 1'b0;\n parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000;\n parameter cfg_tx3_pcs_sync_supported_i = 1'b0;\n parameter cfg_tx3_pma_clk_pos_i = 1'b0;\n parameter cfg_tx3_pma_loopback_i = 1'b0;\n parameter location = \"\";\n parameter rx_usrclk_use_pcs_clk_2 = 1'b0;\n parameter tx_usrclk_use_pcs_clk_2 = 1'b0;\nendmodule\n",
312
+ "io_map.v": "module \\$__BEYOND_IBUF (input PAD, output O);\n\tNX_IOB_I _TECHMAP_REPLACE_ (.IO(PAD), .O(O), .C(1'b0));\nendmodule\n\nmodule \\$__BEYOND_OBUF (output PAD, input I);\n\tNX_IOB_O _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(1'b1));\nendmodule\n\nmodule \\$__BEYOND_TOBUF (output PAD, input I, input C);\n\tNX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(C));\nendmodule\n\nmodule \\$__BEYOND_IOBUF (output PAD, input I, output O, output C);\n\tNX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .O(O), .C(C));\nendmodule\n",
313
+ "latches_map.v": "module \\$_DLATCH_N_ (E, D, Q);\n wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n input E, D;\n output Q = !E ? D : Q;\nendmodule\n\nmodule \\$_DLATCH_P_ (E, D, Q);\n wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n input E, D;\n output Q = E ? D : Q;\nendmodule\n",
314
+ "rf_init.vh": "function [9728-1:0] rf_init_to_string;\n input [1152-1:0] array;\n input integer blocks;\n input integer width;\n reg [9728-1:0] temp; // (1152+1152/18)*8\n integer i;\nbegin\n temp = \"\";\n for (i = 0; i < blocks; i = i + 1) begin\n if (i != 0) begin\n temp = {temp, \",\"};\n end\n temp = {temp, $sformatf(\"%b\",array[(i+1)*width-1: i*width])};\n end\n rf_init_to_string = temp;\nend\nendfunction\n",
315
+ "rf_rams_l.txt": "ram distributed $__NX_RFB_L_ {\n abits 6;\n width 16;\n cost 10;\n init no_undef;\n prune_rom;\n\n port sw \"W\" {\n clock anyedge;\n }\n port sr \"R\" {\n clock anyedge;\n rden;\n }\n}\n",
316
+ "rf_rams_m.txt": "ram distributed $__NX_RFB_M_ {\n abits 6;\n width 16;\n cost 10;\n init no_undef;\n prune_rom;\n\n port sw \"W\" {\n clock anyedge;\n }\n port sr \"R\" {\n clock anyedge;\n rden;\n }\n}\n",
317
+ "rf_rams_map_l.v": "module $__NX_RFB_L_ (\n input PORT_W_CLK,\n input PORT_W_WR_EN,\n input [5:0] PORT_W_ADDR,\n input [15:0] PORT_W_WR_DATA, \n input PORT_R_CLK,\n input PORT_R_RD_EN,\n input [5:0] PORT_R_ADDR,\n output [15:0] PORT_R_RD_DATA,\n);\n parameter INIT = 1152'bx;\n parameter PORT_W_CLK_POL = 1'b1;\n parameter PORT_R_CLK_POL = 1'b1;\n\n NX_RFB_L_WRAP #(\n .mode(0),\n .mem_ctxt(INIT),\n .rck_edge(~PORT_R_CLK_POL),\n .wck_edge(~PORT_W_CLK_POL)\n ) _TECHMAP_REPLACE_ (\n .RCK(PORT_R_CLK),\n .WCK(PORT_W_CLK),\n .I(PORT_W_WR_DATA),\n .RA(PORT_R_ADDR),\n .WA(PORT_W_ADDR),\n .RE(PORT_R_RD_EN),\n .WE(PORT_W_WR_EN),\n .O(PORT_R_RD_DATA)\n );\nendmodule\n",
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+ "rf_rams_map_m.v": "module $__NX_RFB_M_ (\n input PORT_W_CLK,\n input PORT_W_WR_EN,\n input [5:0] PORT_W_ADDR,\n input [15:0] PORT_W_WR_DATA, \n input PORT_R_CLK,\n input PORT_R_RD_EN,\n input [5:0] PORT_R_ADDR,\n output [15:0] PORT_R_RD_DATA,\n);\n parameter INIT = 1152'bx;\n parameter PORT_W_CLK_POL = 1'b1;\n parameter PORT_R_CLK_POL = 1'b1;\n\n NX_RFB_M_WRAP #(\n .mode(0),\n .mem_ctxt(INIT),\n .rck_edge(~PORT_R_CLK_POL),\n .wck_edge(~PORT_W_CLK_POL)\n ) _TECHMAP_REPLACE_ (\n .RCK(PORT_R_CLK),\n .WCK(PORT_W_CLK),\n .I(PORT_W_WR_DATA),\n .RA(PORT_R_ADDR),\n .WA(PORT_W_ADDR),\n .RE(PORT_R_RD_EN),\n .WE(PORT_W_WR_EN),\n .O(PORT_R_RD_DATA)\n );\nendmodule\n",
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+ "rf_rams_map_u.v": "\nmodule $__NX_RFB_U_DPREG_ (\n input PORT_W_CLK,\n input [6-1:0] PORT_W_ADDR,\n input [6-1:0] PORT_R_ADDR,\n input [36-1:0] PORT_W_WR_DATA,\n input PORT_W_WR_EN,\n output [36-1:0] PORT_R_RD_DATA\n);\n parameter INIT = 1152'bx;\n parameter PORT_W_CLK_POL = 1'b1;\n parameter OPTION_MODE = 0;\n parameter WIDTH = 18;\n parameter BITS_USED = 0;\n localparam BLOCK_NUM = OPTION_MODE == 2 ? 64 : 32;\n localparam BLOCK_SIZE = OPTION_MODE == 3 ? 36 : 18;\n\n`include \"rf_init.vh\"\n\n // mode 0 - DPREG\n // mode 2 - NX_XRFB_64x18\n // mode 3 - NX_XRFB_32x36\n NX_RFB_U #(\n .mode(OPTION_MODE),\n .mem_ctxt($sformatf(\"%s\",rf_init_to_string(INIT, BLOCK_NUM, BLOCK_SIZE))),\n .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)\n ) _TECHMAP_REPLACE_ (\n .WCK(PORT_W_CLK),\n .I1(PORT_W_WR_DATA[0]),\n .I2(PORT_W_WR_DATA[1]),\n .I3(PORT_W_WR_DATA[2]),\n .I4(PORT_W_WR_DATA[3]),\n .I5(PORT_W_WR_DATA[4]),\n .I6(PORT_W_WR_DATA[5]),\n .I7(PORT_W_WR_DATA[6]),\n .I8(PORT_W_WR_DATA[7]),\n .I9(PORT_W_WR_DATA[8]),\n .I10(PORT_W_WR_DATA[9]),\n .I11(PORT_W_WR_DATA[10]),\n .I12(PORT_W_WR_DATA[11]),\n .I13(PORT_W_WR_DATA[12]),\n .I14(PORT_W_WR_DATA[13]),\n .I15(PORT_W_WR_DATA[14]),\n .I16(PORT_W_WR_DATA[15]),\n .I17(PORT_W_WR_DATA[16]),\n .I18(PORT_W_WR_DATA[17]),\n .I19(PORT_W_WR_DATA[18]),\n .I20(PORT_W_WR_DATA[19]),\n .I21(PORT_W_WR_DATA[20]),\n .I22(PORT_W_WR_DATA[21]),\n .I23(PORT_W_WR_DATA[22]),\n .I24(PORT_W_WR_DATA[23]),\n .I25(PORT_W_WR_DATA[24]),\n .I26(PORT_W_WR_DATA[25]),\n .I27(PORT_W_WR_DATA[26]),\n .I28(PORT_W_WR_DATA[27]),\n .I29(PORT_W_WR_DATA[28]),\n .I30(PORT_W_WR_DATA[29]),\n .I31(PORT_W_WR_DATA[30]),\n .I32(PORT_W_WR_DATA[31]),\n .I33(PORT_W_WR_DATA[32]),\n .I34(PORT_W_WR_DATA[33]),\n .I35(PORT_W_WR_DATA[34]),\n .I36(PORT_W_WR_DATA[35]),\n .O1(PORT_R_RD_DATA[0]),\n .O2(PORT_R_RD_DATA[1]),\n .O3(PORT_R_RD_DATA[2]),\n .O4(PORT_R_RD_DATA[3]),\n .O5(PORT_R_RD_DATA[4]),\n .O6(PORT_R_RD_DATA[5]),\n .O7(PORT_R_RD_DATA[6]),\n .O8(PORT_R_RD_DATA[7]),\n .O9(PORT_R_RD_DATA[8]),\n .O10(PORT_R_RD_DATA[9]),\n .O11(PORT_R_RD_DATA[10]),\n .O12(PORT_R_RD_DATA[11]),\n .O13(PORT_R_RD_DATA[12]),\n .O14(PORT_R_RD_DATA[13]),\n .O15(PORT_R_RD_DATA[14]),\n .O16(PORT_R_RD_DATA[15]),\n .O17(PORT_R_RD_DATA[16]),\n .O18(PORT_R_RD_DATA[17]),\n .O19(PORT_R_RD_DATA[18]),\n .O20(PORT_R_RD_DATA[19]),\n .O21(PORT_R_RD_DATA[20]),\n .O22(PORT_R_RD_DATA[21]),\n .O23(PORT_R_RD_DATA[22]),\n .O24(PORT_R_RD_DATA[23]),\n .O25(PORT_R_RD_DATA[24]),\n .O26(PORT_R_RD_DATA[25]),\n .O27(PORT_R_RD_DATA[26]),\n .O28(PORT_R_RD_DATA[27]),\n .O29(PORT_R_RD_DATA[28]),\n .O30(PORT_R_RD_DATA[29]),\n .O31(PORT_R_RD_DATA[30]),\n .O32(PORT_R_RD_DATA[31]),\n .O33(PORT_R_RD_DATA[32]),\n .O34(PORT_R_RD_DATA[33]),\n .O35(PORT_R_RD_DATA[34]),\n .O36(PORT_R_RD_DATA[35]),\n .RA1(PORT_R_ADDR[0]),\n .RA2(PORT_R_ADDR[1]),\n .RA3(PORT_R_ADDR[2]),\n .RA4(PORT_R_ADDR[3]),\n .RA5(PORT_R_ADDR[4]),\n .RA6(PORT_R_ADDR[5]),\n .RA7(),\n .RA8(),\n .RA9(),\n .RA10(),\n .WA1(PORT_W_ADDR[0]),\n .WA2(PORT_W_ADDR[1]),\n .WA3(PORT_W_ADDR[2]),\n .WA4(PORT_W_ADDR[3]),\n .WA5(PORT_W_ADDR[4]),\n .WA6(PORT_W_ADDR[5]),\n .WE(PORT_W_WR_EN),\n .WEA(1'b0)\n );\nendmodule\n\nmodule $__NX_RFB_U_SPREG_ (\n input PORT_RW_CLK,\n input [4:0] PORT_RW_ADDR,\n input [17:0] PORT_RW_WR_DATA,\n input PORT_RW_WR_EN,\n output [17:0] PORT_RW_RD_DATA\n);\n parameter INIT = 576'bx;\n parameter PORT_RW_CLK_POL = 1'b1;\n parameter BITS_USED = 0;\n`include \"rf_init.vh\"\n\n NX_RFB_U #(\n .mode(1),\n .mem_ctxt($sformatf(\"%s\",rf_init_to_string(INIT, 32, 18))),\n .wck_edge(PORT_RW_CLK_POL == 1 ? 1'b0 : 1'b1)\n ) _TECHMAP_REPLACE_ (\n .WCK(PORT_RW_CLK),\n .I1(PORT_RW_WR_DATA[0]),\n .I2(PORT_RW_WR_DATA[1]),\n .I3(PORT_RW_WR_DATA[2]),\n .I4(PORT_RW_WR_DATA[3]),\n .I5(PORT_RW_WR_DATA[4]),\n .I6(PORT_RW_WR_DATA[5]),\n .I7(PORT_RW_WR_DATA[6]),\n .I8(PORT_RW_WR_DATA[7]),\n .I9(PORT_RW_WR_DATA[8]),\n .I10(PORT_RW_WR_DATA[9]),\n .I11(PORT_RW_WR_DATA[10]),\n .I12(PORT_RW_WR_DATA[11]),\n .I13(PORT_RW_WR_DATA[12]),\n .I14(PORT_RW_WR_DATA[13]),\n .I15(PORT_RW_WR_DATA[14]),\n .I16(PORT_RW_WR_DATA[15]),\n .I17(PORT_RW_WR_DATA[16]),\n .I18(PORT_RW_WR_DATA[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(PORT_RW_RD_DATA[0]),\n .O2(PORT_RW_RD_DATA[1]),\n .O3(PORT_RW_RD_DATA[2]),\n .O4(PORT_RW_RD_DATA[3]),\n .O5(PORT_RW_RD_DATA[4]),\n .O6(PORT_RW_RD_DATA[5]),\n .O7(PORT_RW_RD_DATA[6]),\n .O8(PORT_RW_RD_DATA[7]),\n .O9(PORT_RW_RD_DATA[8]),\n .O10(PORT_RW_RD_DATA[9]),\n .O11(PORT_RW_RD_DATA[10]),\n .O12(PORT_RW_RD_DATA[11]),\n .O13(PORT_RW_RD_DATA[12]),\n .O14(PORT_RW_RD_DATA[13]),\n .O15(PORT_RW_RD_DATA[14]),\n .O16(PORT_RW_RD_DATA[15]),\n .O17(PORT_RW_RD_DATA[16]),\n .O18(PORT_RW_RD_DATA[17]),\n .O19(),\n .O20(),\n .O21(),\n .O22(),\n .O23(),\n .O24(),\n .O25(),\n .O26(),\n .O27(),\n .O28(),\n .O29(),\n .O30(),\n .O31(),\n .O32(),\n .O33(),\n .O34(),\n .O35(),\n .O36(),\n .RA1(),\n .RA2(),\n .RA3(),\n .RA4(),\n .RA5(),\n .RA6(),\n .RA7(),\n .RA8(),\n .RA9(),\n .RA10(),\n .WA1(PORT_RW_ADDR[0]),\n .WA2(PORT_RW_ADDR[1]),\n .WA3(PORT_RW_ADDR[2]),\n .WA4(PORT_RW_ADDR[3]),\n .WA5(PORT_RW_ADDR[4]),\n .WA6(),\n .WE(PORT_RW_WR_EN),\n .WEA(1'b0)\n );\nendmodule\n\nmodule $__NX_XRFB_2R_1W_ (\n input PORT_W_CLK,\n input [4:0] PORT_W_ADDR,\n input [4:0] PORT_A_ADDR,\n input [4:0] PORT_B_ADDR,\n input [17:0] PORT_W_WR_DATA,\n input PORT_W_WR_EN,\n output [17:0] PORT_A_RD_DATA,\n output [17:0] PORT_B_RD_DATA\n);\n parameter INIT = 576'bx;\n parameter PORT_W_CLK_POL = 1'b1;\n parameter BITS_USED = 0;\n`include \"rf_init.vh\"\n\n NX_RFB_U #(\n .mode(4),\n .mem_ctxt($sformatf(\"%s\",rf_init_to_string(INIT, 32, 18))),\n .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)\n ) _TECHMAP_REPLACE_ (\n .WCK(PORT_W_CLK),\n .I1(PORT_W_WR_DATA[0]),\n .I2(PORT_W_WR_DATA[1]),\n .I3(PORT_W_WR_DATA[2]),\n .I4(PORT_W_WR_DATA[3]),\n .I5(PORT_W_WR_DATA[4]),\n .I6(PORT_W_WR_DATA[5]),\n .I7(PORT_W_WR_DATA[6]),\n .I8(PORT_W_WR_DATA[7]),\n .I9(PORT_W_WR_DATA[8]),\n .I10(PORT_W_WR_DATA[9]),\n .I11(PORT_W_WR_DATA[10]),\n .I12(PORT_W_WR_DATA[11]),\n .I13(PORT_W_WR_DATA[12]),\n .I14(PORT_W_WR_DATA[13]),\n .I15(PORT_W_WR_DATA[14]),\n .I16(PORT_W_WR_DATA[15]),\n .I17(PORT_W_WR_DATA[16]),\n .I18(PORT_W_WR_DATA[17]),\n .I19(),\n .I20(),\n .I21(),\n .I22(),\n .I23(),\n .I24(),\n .I25(),\n .I26(),\n .I27(),\n .I28(),\n .I29(),\n .I30(),\n .I31(),\n .I32(),\n .I33(),\n .I34(),\n .I35(),\n .I36(),\n .O1(PORT_A_RD_DATA[0]),\n .O2(PORT_A_RD_DATA[1]),\n .O3(PORT_A_RD_DATA[2]),\n .O4(PORT_A_RD_DATA[3]),\n .O5(PORT_A_RD_DATA[4]),\n .O6(PORT_A_RD_DATA[5]),\n .O7(PORT_A_RD_DATA[6]),\n .O8(PORT_A_RD_DATA[7]),\n .O9(PORT_A_RD_DATA[8]),\n .O10(PORT_A_RD_DATA[9]),\n .O11(PORT_A_RD_DATA[10]),\n .O12(PORT_A_RD_DATA[11]),\n .O13(PORT_A_RD_DATA[12]),\n .O14(PORT_A_RD_DATA[13]),\n .O15(PORT_A_RD_DATA[14]),\n .O16(PORT_A_RD_DATA[15]),\n .O17(PORT_A_RD_DATA[16]),\n .O18(PORT_A_RD_DATA[17]),\n .O19(PORT_B_RD_DATA[0]),\n .O20(PORT_B_RD_DATA[1]),\n .O21(PORT_B_RD_DATA[2]),\n .O22(PORT_B_RD_DATA[3]),\n .O23(PORT_B_RD_DATA[4]),\n .O24(PORT_B_RD_DATA[5]),\n .O25(PORT_B_RD_DATA[6]),\n .O26(PORT_B_RD_DATA[7]),\n .O27(PORT_B_RD_DATA[8]),\n .O28(PORT_B_RD_DATA[9]),\n .O29(PORT_B_RD_DATA[10]),\n .O30(PORT_B_RD_DATA[11]),\n .O31(PORT_B_RD_DATA[12]),\n .O32(PORT_B_RD_DATA[13]),\n .O33(PORT_B_RD_DATA[14]),\n .O34(PORT_B_RD_DATA[15]),\n .O35(PORT_B_RD_DATA[16]),\n .O36(PORT_B_RD_DATA[17]),\n .RA1(PORT_A_ADDR[0]),\n .RA2(PORT_A_ADDR[1]),\n .RA3(PORT_A_ADDR[2]),\n .RA4(PORT_A_ADDR[3]),\n .RA5(PORT_A_ADDR[4]),\n .RA6(PORT_B_ADDR[0]),\n .RA7(PORT_B_ADDR[1]),\n .RA8(PORT_B_ADDR[2]),\n .RA9(PORT_B_ADDR[3]),\n .RA10(PORT_B_ADDR[4]),\n .WA1(PORT_W_ADDR[0]),\n .WA2(PORT_W_ADDR[1]),\n .WA3(PORT_W_ADDR[2]),\n .WA4(PORT_W_ADDR[3]),\n .WA5(PORT_W_ADDR[4]),\n .WA6(),\n .WE(PORT_W_WR_EN),\n .WEA(1'b0)\n );\nendmodule",
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+ "rf_rams_u.txt": "# Register-File RAMs for NanoXplore NG-ULTRA\n\n# Dual-port RAMs.\n# NX_RFB_U in mode 0 (DPREG)\n# NX_RFB_U in mode 2 (NX_XRFB_64x18)\n# NX_RFB_U in mode 3 (NX_XRFB_32x36)\n\nram distributed $__NX_RFB_U_DPREG_ {\n\toption \"MODE\" 0 {\n cost 30;\n widthscale 30;\n\t\tabits 5;\n\t\twidths 18 global;\n\t}\n\toption \"MODE\" 2 {\n cost 50;\n widthscale 30;\n\t\tabits 6;\n\t\twidths 18 global;\n\t}\n\toption \"MODE\" 3 {\n cost 50;\n widthscale 30;\n\t\tabits 5;\n\t\twidths 36 global;\n\t}\n init no_undef;\n\n port sw \"W\" {\n clock anyedge;\n }\n port ar \"R\" {\n }\n}\n\n# Single-port RAMs.\n# NX_RFB_U in mode 1 (SPREG)\n\nram distributed $__NX_RFB_U_SPREG_ {\n\tcost 30;\n widthscale;\n abits 5;\n width 18;\n\tinit no_undef;\n\tport arsw \"RW\" {\n\t\tclock anyedge;\n\t}\n}\n\n# Single write dual read RAMs.\n# NX_RFB_U in mode 4 (NX_XRFB_2R_1W)\n\nram distributed $__NX_XRFB_2R_1W_ {\n\tcost 40;\n widthscale 30;\n abits 5;\n width 18;\n\tinit no_undef;\n port sw \"W\" {\n clock anyedge;\n }\n port ar \"A\" {\n }\n port ar \"B\" {\n }\n}\n",
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+ },
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  "nexus": {
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  "arith_map.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * Copyright (C) 2018 gatecat <gatecat@ds0.me>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_nexus_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 4;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\tfunction integer round_up2;\n\t\tinput integer N;\n\t\tbegin\n\t\t\tround_up2 = ((N + 1) / 2) * 2;\n\t\tend\n\tendfunction\n\n\tlocalparam Y_WIDTH2 = round_up2(Y_WIDTH);\n\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BX = B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2+1:0] FCO, Y1;\n\n\tgenvar i;\n\n\t// Carry feed-in\n\tCCU2 #(\n\t\t.INIT0(\"0xFFFF\"),\n\t\t.INIT1(\"0x00AA\"),\n\t\t.INJECT(\"NO\")\n\t) ccu2c_i (\n\t\t.A0(1'b1), .B0(1'b1), .C0(1'b1), .D0(1'b1),\n\t\t.A1(CI), .B1(1'b1), .C1(1'b1), .D1(1'b1),\n\t\t.COUT(FCO[0])\n\t);\n\n\tgenerate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice\n\t\tCCU2 #(\n\t\t\t.INIT0(\"0x96AA\"),\n\t\t\t.INIT1(\"0x96AA\"),\n\t\t\t.INJECT(\"NO\")\n\t\t) ccu2c_i (\n\t\t\t.CIN(FCO[i]),\n\t\t\t.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),\n\t\t\t.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),\n\t\t\t.S0(Y[i]), .S1(Y1[i]),\n\t\t\t.COUT(FCO[i+2])\n\t\t);\n\n\t\tassign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));\n\t\tif (i+1 < Y_WIDTH) begin\n\t\t\tassign CO[i + 1] = (AA[i + 1] && BB[i + 1]) || ((Y[i + 1] ^ AA[i + 1] ^ BB[i + 1]) && (AA[i + 1] || BB[i + 1]));\n\t\t\tassign Y[i+1] = Y1[i];\n\t\tend\n\tend endgenerate\n\n\tassign X = AA ^ BB;\nendmodule\n",
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  "brams.txt": "ram block $__NX_DP16K_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 129;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\trdwr no_change;\n\t\tportoption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\tportoption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n}\n\nram block $__NX_PDP16K_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\toption \"SAME_CLOCK\" 1 cost 128;\n\toption \"SAME_CLOCK\" 0 cost 129;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\toption \"SAME_CLOCK\" 1 clock posedge \"C\";\n\t\toption \"SAME_CLOCK\" 0 clock posedge;\n\t\tclken;\n\t\tportoption \"RESETMODE\" \"SYNC\" {\n\t\t\trdsrst zero gated_clken;\n\t\t}\n\t\tportoption \"RESETMODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\toption \"SAME_CLOCK\" 1 clock posedge \"C\";\n\t\toption \"SAME_CLOCK\" 0 clock posedge;\n\t\tclken;\n\t\toption \"SAME_CLOCK\" 1 wrtrans all old;\n\t}\n}\n",
@@ -346,9 +376,9 @@ export const filesystem = {
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  "cells_sim.v": "// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf\n\nmodule AND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A & B;\nendmodule\n\nmodule AND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A & B & C;\nendmodule\n\nmodule AND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A & B & C & D;\nendmodule\n\nmodule CFG1 (\n\toutput Y,\n\tinput A\n);\n\tparameter [1:0] INIT = 2'h0;\n\tassign Y = INIT >> A;\nendmodule\n\nmodule CFG2 (\n\toutput Y,\n\tinput A,\n\tinput B\n);\n\tparameter [3:0] INIT = 4'h0;\n\tassign Y = INIT >> {B, A};\nendmodule\n\nmodule CFG3 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C\n);\n\tparameter [7:0] INIT = 8'h0;\n\tassign Y = INIT >> {C, B, A};\nendmodule\n\nmodule CFG4 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C,\n\tinput D\n);\n\tparameter [15:0] INIT = 16'h0;\n\tassign Y = INIT >> {D, C, B, A};\nendmodule\n\nmodule BUFF (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule BUFD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT_PRESERVE (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule GCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule RCLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule RGCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule SLE (\n\toutput Q,\n\tinput ADn,\n\tinput ALn,\n\t(* clkbuf_sink *)\n\tinput CLK,\n\tinput D,\n\tinput LAT,\n\tinput SD,\n\tinput EN,\n\tinput SLn\n);\n\treg q_latch, q_ff;\n\n\talways @(posedge CLK, negedge ALn) begin\n\t\tif (!ALn) begin\n\t\t\tq_ff <= !ADn;\n\t\tend else if (EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\talways @* begin\n\t\tif (!ALn) begin\n\t\t\tq_latch <= !ADn;\n\t\tend else if (CLK && EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\tassign Q = LAT ? q_latch : q_ff;\nendmodule\n\nmodule ARI1 (\n\tinput A, B, C, D, FCI,\n\toutput Y, S, FCO\n);\n\tparameter [19:0] INIT = 20'h0;\n\twire [2:0] Fsel = {D, C, B};\n\twire F0 = INIT[Fsel];\n\twire F1 = INIT[8 + Fsel];\n\twire Yout = A ? F1 : F0;\n\tassign Y = Yout;\n\tassign S = FCI ^ Yout;\n\twire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];\n\twire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);\n\tassign FCO = P ? FCI : G;\nendmodule\n\n// module FCEND_BUFF\n// module FCINIT_BUFF\n// module FLASH_FREEZE\n// module OSCILLATOR\n// module SYSCTRL_RESET_STATUS\n// module LIVE_PROBE_FB\n\n(* blackbox *)\nmodule GCLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBIBUF (\n\tinput D,\n\tinput E,\n\tinput EN,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n// module DFN1\n// module DFN1C0\n// module DFN1E1\n// module DFN1E1C0\n// module DFN1E1P0\n// module DFN1P0\n// module DLN1\n// module DLN1C0\n// module DLN1P0\n\nmodule INV (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule INVD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule MX2 (\n\tinput A, B, S,\n\toutput Y\n);\n\tassign Y = S ? B : A;\nendmodule\n\nmodule MX4 (\n\tinput D0, D1, D2, D3, S0, S1,\n\toutput Y\n);\n\tassign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);\nendmodule\n\nmodule NAND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A & B);\nendmodule\n\nmodule NAND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A & B & C);\nendmodule\n\nmodule NAND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A & B & C & D);\nendmodule\n\nmodule NOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A | B);\nendmodule\n\nmodule NOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A | B | C);\nendmodule\n\nmodule NOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A | B | C | D);\nendmodule\n\nmodule OR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A | B;\nendmodule\n\nmodule OR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A | B | C;\nendmodule\n\nmodule OR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A | B | C | D;\nendmodule\n\nmodule XOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A ^ B;\nendmodule\n\nmodule XOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C;\nendmodule\n\nmodule XOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D;\nendmodule\n\nmodule XOR8 (\n\tinput A, B, C, D, E, F, G, H,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;\nendmodule\n\n// module UJTAG\n\nmodule BIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule BIBUF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PADP,\n\t(* iopad_external_pin *)\n\tinout PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule CLKBIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\nmodule CLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule CLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule INBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule INBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule OUTBUF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = D;\nendmodule\n\n(* blackbox *)\nmodule OUTBUF_DIFF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule TRIBUFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\nendmodule\n\n(* blackbox *)\nmodule TRIBUFF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\n// module DDR_IN\n// module DDR_OUT\n// module RAM1K18\n// module RAM64x18\n// module MACC\n\n(* blackbox *)\nmodule SYSRESET (\n\t(* iopad_external_pin *)\n\tinput DEVRST_N,\n\toutput POWER_ON_RESET_N);\nendmodule\n\n\n(* blackbox *)\nmodule XTLOSC (\n\t(* iopad_external_pin *)\n\tinput XTL,\n\toutput CLKOUT);\n\tparameter [1:0] MODE = 2'h3;\n\tparameter real FREQUENCY = 20.0;\nendmodule\n\n(* blackbox *)\nmodule RAM1K18 (\n\tinput [13:0] A_ADDR,\n\tinput [2:0] A_BLK,\n\t(* clkbuf_sink *)\n\tinput\t A_CLK,\n\tinput [17:0] A_DIN,\n\toutput [17:0] A_DOUT,\n\tinput [1:0] A_WEN,\n\tinput [2:0] A_WIDTH,\n\tinput\t A_WMODE,\n\tinput\t A_ARST_N,\n\tinput\t A_DOUT_LAT,\n\tinput\t A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_DOUT_CLK,\n\tinput\t A_DOUT_EN,\n\tinput\t A_DOUT_SRST_N,\n\n\tinput [13:0] B_ADDR,\n\tinput [2:0] B_BLK,\n\t(* clkbuf_sink *)\n\tinput\t B_CLK,\n\tinput [17:0] B_DIN,\n\toutput [17:0] B_DOUT,\n\tinput [1:0] B_WEN,\n\tinput [2:0] B_WIDTH,\n\tinput\t B_WMODE,\n\tinput\t B_ARST_N,\n\tinput\t B_DOUT_LAT,\n\tinput\t B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_DOUT_CLK,\n\tinput\t B_DOUT_EN,\n\tinput\t B_DOUT_SRST_N,\n\n\tinput\t A_EN,\n\tinput\t B_EN,\n\tinput\t SII_LOCK,\n\toutput\t BUSY);\nendmodule\n\n(* blackbox *)\nmodule RAM64x18 (\n\tinput [9:0] A_ADDR,\n\tinput [1:0] A_BLK,\n\tinput [2:0] A_WIDTH,\n\toutput [17:0] A_DOUT,\n\tinput\t A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_DOUT_CLK,\n\tinput\t A_DOUT_EN,\n\tinput\t A_DOUT_LAT,\n\tinput\t A_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_ADDR_CLK,\n\tinput\t A_ADDR_EN,\n\tinput\t A_ADDR_LAT,\n\tinput\t A_ADDR_SRST_N,\n\tinput\t A_ADDR_ARST_N,\n\n\tinput [9:0] B_ADDR,\n\tinput [1:0] B_BLK,\n\tinput [2:0] B_WIDTH,\n\toutput [17:0] B_DOUT,\n\tinput\t B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_DOUT_CLK,\n\tinput\t B_DOUT_EN,\n\tinput\t B_DOUT_LAT,\n\tinput\t B_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_ADDR_CLK,\n\tinput\t B_ADDR_EN,\n\tinput\t B_ADDR_LAT,\n\tinput\t B_ADDR_SRST_N,\n\tinput\t B_ADDR_ARST_N,\n\n\tinput [9:0] C_ADDR,\n\t(* clkbuf_sink *)\n\tinput\t C_CLK,\n\tinput [17:0] C_DIN,\n\tinput\t C_WEN,\n\tinput [1:0] C_BLK,\n\tinput [2:0] C_WIDTH,\n\n\tinput\t A_EN,\n\tinput\t B_EN,\n\tinput\t C_EN,\n\tinput\t SII_LOCK,\n\toutput\t BUSY);\nendmodule\n",
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  "simcells.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell simulation library.\n *\n * This Verilog library contains simple simulation models for the internal\n * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology\n * mapper (see \"techmap.v\" in this directory) and expected by the \"abc\" pass.\n *\n */\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_BUF_ (A, Y)\n//-\n//- A buffer. This cell type is always optimized away by the opt_clean pass.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 0\n//- 1 | 1\n//-\nmodule \\$_BUF_ (A, Y);\ninput A;\noutput Y;\nassign Y = A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOT_ (A, Y)\n//-\n//- An inverter gate.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 1\n//- 1 | 0\n//-\nmodule \\$_NOT_ (A, Y);\ninput A;\noutput Y;\nassign Y = ~A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AND_ (A, B, Y)\n//-\n//- A 2-input AND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_AND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NAND_ (A, B, Y)\n//-\n//- A 2-input NAND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_NAND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A & B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OR_ (A, B, Y)\n//-\n//- A 2-input OR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_OR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOR_ (A, B, Y)\n//-\n//- A 2-input NOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 0\n//-\nmodule \\$_NOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A | B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XOR_ (A, B, Y)\n//-\n//- A 2-input XOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_XOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A ^ B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XNOR_ (A, B, Y)\n//-\n//- A 2-input XNOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_XNOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A ^ B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ANDNOT_ (A, B, Y)\n//-\n//- A 2-input AND-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_ANDNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ORNOT_ (A, B, Y)\n//-\n//- A 2-input OR-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_ORNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX_ (A, B, S, Y)\n//-\n//- A 2-input MUX gate.\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- a - 0 | a\n//- - b 1 | b\n//-\nmodule \\$_MUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? B : A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NMUX_ (A, B, S, Y)\n//-\n//- A 2-input inverting MUX gate.\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- 0 - 0 | 1\n//- 1 - 0 | 0\n//- - 0 1 | 1\n//- - 1 1 | 0\n//-\nmodule \\$_NMUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? !B : !A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX4_ (A, B, C, D, S, T, Y)\n//-\n//- A 4-input MUX gate.\n//-\n//- Truth table: A B C D S T | Y\n//- -------------+---\n//- a - - - 0 0 | a\n//- - b - - 1 0 | b\n//- - - c - 0 1 | c\n//- - - - d 1 1 | d\n//-\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\ninput A, B, C, D, S, T;\noutput Y;\nassign Y = T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y)\n//-\n//- An 8-input MUX gate.\n//-\n//- Truth table: A B C D E F G H S T U | Y\n//- -----------------------+---\n//- a - - - - - - - 0 0 0 | a\n//- - b - - - - - - 1 0 0 | b\n//- - - c - - - - - 0 1 0 | c\n//- - - - d - - - - 1 1 0 | d\n//- - - - - e - - - 0 0 1 | e\n//- - - - - - f - - 1 0 1 | f\n//- - - - - - - g - 0 1 1 | g\n//- - - - - - - - h 1 1 1 | h\n//-\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\ninput A, B, C, D, E, F, G, H, S, T, U;\noutput Y;\nassign Y = U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)\n//-\n//- A 16-input MUX gate.\n//-\n//- Truth table: A B C D E F G H I J K L M N O P S T U V | Y\n//- -----------------------------------------+---\n//- a - - - - - - - - - - - - - - - 0 0 0 0 | a\n//- - b - - - - - - - - - - - - - - 1 0 0 0 | b\n//- - - c - - - - - - - - - - - - - 0 1 0 0 | c\n//- - - - d - - - - - - - - - - - - 1 1 0 0 | d\n//- - - - - e - - - - - - - - - - - 0 0 1 0 | e\n//- - - - - - f - - - - - - - - - - 1 0 1 0 | f\n//- - - - - - - g - - - - - - - - - 0 1 1 0 | g\n//- - - - - - - - h - - - - - - - - 1 1 1 0 | h\n//- - - - - - - - - i - - - - - - - 0 0 0 1 | i\n//- - - - - - - - - - j - - - - - - 1 0 0 1 | j\n//- - - - - - - - - - - k - - - - - 0 1 0 1 | k\n//- - - - - - - - - - - - l - - - - 1 1 0 1 | l\n//- - - - - - - - - - - - - m - - - 0 0 1 1 | m\n//- - - - - - - - - - - - - - n - - 1 0 1 1 | n\n//- - - - - - - - - - - - - - - o - 0 1 1 1 | o\n//- - - - - - - - - - - - - - - - p 1 1 1 1 | p\n//-\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\ninput A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\noutput Y;\nassign Y = V ? U ? T ? (S ? P : O) :\n (S ? N : M) :\n T ? (S ? L : K) :\n (S ? J : I) :\n U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI3_ (A, B, C, Y)\n//-\n//- A 3-input And-Or-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 0\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 0\n//- 1 1 1 | 0\n//-\nmodule \\$_AOI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A & B) | C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI3_ (A, B, C, Y)\n//-\n//- A 3-input Or-And-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 1\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 1\n//- 1 1 1 | 0\n//-\nmodule \\$_OAI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A | B) & C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI4_ (A, B, C, Y)\n//-\n//- A 4-input And-Or-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 0\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 1\n//- 0 1 1 0 | 1\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 1\n//- 1 0 1 0 | 1\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 0\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_AOI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A & B) | (C & D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI4_ (A, B, C, Y)\n//-\n//- A 4-input Or-And-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 1\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 0\n//- 0 1 1 0 | 0\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 0\n//- 1 0 1 0 | 0\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 1\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_OAI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A | B) & (C | D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_TBUF_ (A, E, Y)\n//-\n//- A tri-state buffer.\n//-\n//- Truth table: A E | Y\n//- -----+---\n//- a 1 | a\n//- - 0 | z\n//-\nmodule \\$_TBUF_ (A, E, Y);\ninput A, E;\noutput Y;\nassign Y = E ? A : 1'bz;\nendmodule\n\n// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually,\n// instead edit the templates in gen_ff_types.py and rerun it.\n\n// START AUTOGENERATED CELL TYPES\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NN_ (S, R, Q)\n//-\n//- A set-reset latch with negative polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NP_ (S, R, Q)\n//-\n//- A set-reset latch with negative polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PN_ (S, R, Q)\n//-\n//- A set-reset latch with positive polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PP_ (S, R, Q)\n//-\n//- A set-reset latch with positive polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n`ifdef SIMCELLS_FF\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_FF_ (D, Q)\n//-\n//- A D-type flip-flop that is clocked from the implicit global clock. (This cell\n//- type is usually only used in netlists for formal verification.)\n//-\nmodule \\$_FF_ (D, Q);\ninput D;\noutput reg Q;\nalways @($global_clock) begin\n\tQ <= D;\nend\nendmodule\n`endif\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_N_ (D, C, Q)\n//-\n//- A negative edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d \\ | d\n//- - - | q\n//-\nmodule \\$_DFF_N_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(negedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_P_ (D, C, Q)\n//-\n//- A positive edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d / | d\n//- - - | q\n//-\nmodule \\$_DFF_P_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(posedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN_ (D, C, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP_ (D, C, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN_ (D, C, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP_ (D, C, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NN_ (D, C, L, AD, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NP_ (D, C, L, AD, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PN_ (D, C, L, AD, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PP_ (D, C, L, AD, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNN_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNP_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPN_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPP_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNN_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNP_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPN_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPP_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNN_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNP_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPN_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPP_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNN_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNP_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPN_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPP_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_N_ (E, D, Q)\n//-\n//- A negative enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 0 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_N_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_P_ (E, D, Q)\n//-\n//- A positive enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 1 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_P_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN0_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN1_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP0_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP1_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN0_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN1_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP0_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP1_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNN_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNP_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPN_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPP_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNN_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNP_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPN_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPP_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n",
349
- "simlib.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The Simulation Library.\n *\n * This Verilog library contains simple simulation models for the internal\n * cells ($not, ...) generated by the frontends and used in most passes.\n *\n * This library can be used to verify the internal netlists as generated\n * by the different frontends and passes.\n *\n * Note that memory can only be simulated when all $memrd and $memwr cells\n * have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n * pass is doing).\n *\n */\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $not (A, Y)\n//-\n//- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pos (A, Y)\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $neg (A, Y)\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $and (A, B, Y)\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $or (A, B, Y)\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xor (A, B, Y)\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xnor (A, B, Y)\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_and (A, Y)\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_or (A, Y)\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xor (A, Y)\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xnor (A, Y)\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_bool (A, Y)\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P; // Propagate\ninput [WIDTH-1:0] G; // Generate\ninput CI; // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $alu (A, B, CI, BI, X, Y, CO)\n//-\n//- Arithmetic logic unit.\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex\n//- cells into this $alu cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A; // Input operand\ninput [B_WIDTH-1:0] B; // Input operand\noutput [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,\n // used in combination with\n // reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y; // Sum\n\ninput CI; // Carry-in (set for $sub)\ninput BI; // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO; // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $macc (A, B, Y)\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n// * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $div (A, B, Y)\n//-\n//- Division with truncated result (rounded towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mod (A, B, Y)\n//-\n//- Modulo/remainder of division with truncated result (rounded towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $divfloor (A, B, Y)\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $modfloor (A, B, Y)\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <- MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
379
+ "simlib.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The Simulation Library.\n *\n * This Verilog library contains simple simulation models for the internal\n * cells ($not, ...) generated by the frontends and used in most passes.\n *\n * This library can be used to verify the internal netlists as generated\n * by the different frontends and passes.\n *\n * Note that memory can only be simulated when all $memrd and $memwr cells\n * have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n * pass is doing).\n *\n */\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $not (A, Y)\n//-\n//- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pos (A, Y)\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $buf (A, Y)\n//-\n//- A simple coarse-grain buffer cell type for the experimental buffered-normalized\n//- mode. Note this cell does't get removed by 'opt_clean' and is not recommended\n//- for general use.\n//-\nmodule \\$buf (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $neg (A, Y)\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $and (A, B, Y)\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $or (A, B, Y)\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xor (A, B, Y)\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xnor (A, B, Y)\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_and (A, Y)\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_or (A, Y)\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xor (A, Y)\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xnor (A, Y)\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_bool (A, Y)\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $shl (A, B, Y)\n//-\n//- A logical shift-left operation. This corresponds to the Verilog '<<' operator.\n//-\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $shr (A, B, Y)\n//-\n//- A logical shift-right operation. This corresponds to the Verilog '>>' operator.\n//-\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sshl (A, B, Y)\n//-\n//- An arithmatic shift-left operation. \n//- This corresponds to the Verilog '<<<' operator.\n//-\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sshr (A, B, Y)\n//-\n//- An arithmatic shift-right operation.\n//- This corresponds to the Verilog '>>>' operator.\n//-\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P; // Propagate\ninput [WIDTH-1:0] G; // Generate\ninput CI; // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $alu (A, B, CI, BI, X, Y, CO)\n//-\n//- Arithmetic logic unit.\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex\n//- cells into this $alu cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A; // Input operand\ninput [B_WIDTH-1:0] B; // Input operand\noutput [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,\n // used in combination with\n // reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y; // Sum\n\ninput CI; // Carry-in (set for $sub)\ninput BI; // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO; // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lt (A, B, Y)\n//-\n//- A less-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<' operator.\n//-\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $le (A, B, Y)\n//-\n//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '<=' operator.\n//-\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $eq (A, B, Y)\n//-\n//- An equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '==' operator.\n//-\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $ne (A, B, Y)\n//-\n//- An inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!=' operator.\n//-\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $eqx (A, B, Y)\n//-\n//- An exact equality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '===' operator.\n//- Unlike equality comparison that can give 'x' as output, \n//- an exact equality comparison will strictly give '0' or '1' as output.\n//-\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $nex (A, B, Y)\n//-\n//- An exact inequality comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '!==' operator.\n//- Unlike inequality comparison that can give 'x' as output, \n//- an exact inequality comparison will strictly give '0' or '1' as output.\n//-\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $ge (A, B, Y)\n//-\n//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '>=' operator.\n//-\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $gt (A, B, Y)\n//-\n//- A greater-than comparison between inputs 'A' and 'B'. \n//- This corresponds to the Verilog '>' operator.\n//-\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $add (A, B, Y)\n//-\n//- Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator.\n//-\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $sub (A, B, Y)\n//-\n//- Subtraction between inputs 'A' and 'B'.\n//- This corresponds to the Verilog '-' operator.\n//-\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mul (A, B, Y)\n//-\n//- Multiplication of inputs 'A' and 'B'.\n//- This corresponds to the Verilog '*' operator.\n//-\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $macc (A, B, Y)\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n// * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $div (A, B, Y)\n//-\n//- Division with truncated result (rounded towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mod (A, B, Y)\n//-\n//- Modulo/remainder of division with truncated result (rounded towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $divfloor (A, B, Y)\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $modfloor (A, B, Y)\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pow (A, B, Y)\n//-\n//- Exponentiation of an input (Y = A ** B). \n//- This corresponds to the Verilog '**' operator.\n//-\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_not (A, Y)\n//-\n//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator.\n//-\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_and (A, B, Y)\n//-\n//- A logical AND. This corresponds to the Verilog '&&' operator.\n//-\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $logic_or (A, B, Y)\n//-\n//- A logical OR. This corresponds to the Verilog '||' operator.\n//-\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $concat (A, B, Y)\n//-\n//- Concatenation of inputs into a single output ( Y = {B, A} ).\n//-\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mux (A, B, S, Y)\n//-\n//- Multiplexer i.e selecting between two inputs based on select signal.\n//-\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $demux (A, S, Y)\n//-\n//- Demultiplexer i.e routing single input to several outputs based on select signal.\n//- Unselected outputs are driven to zero.\n//-\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $tribuf (A, EN, Y)\n//-\n//- A tri-state buffer. \n//- This buffer conditionally drives the output with the value of the input\n//- based on the enable signal.\n//-\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <- MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
350
380
  "smtmap.v": "(* techmap_celltype = \"$pmux\" *)\nmodule smt_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*(S_WIDTH+1)-1:0] C;\n\n\t\tassign C[WIDTH-1:0] = A;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1)\n\t\t\tassign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i];\n\t\tassign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH];\n\tendgenerate\nendmodule\n",
351
- "techmap.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell technology mapper.\n *\n * This Verilog library contains the mapping of internal cells (e.g. $not with\n * variable bit width) to the internal logic cells (such as the single bit $_NOT_\n * gate). Usually this logic network is then mapped to the actual technology\n * using e.g. the \"abc\" pass.\n *\n * Note that this library does not map $mem cells. They must be mapped to logic\n * and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n * which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
381
+ "techmap.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell technology mapper.\n *\n * This Verilog library contains the mapping of internal cells (e.g. $not with\n * variable bit width) to the internal logic cells (such as the single bit $_NOT_\n * gate). Usually this logic network is then mapped to the actual technology\n * using e.g. the \"abc\" pass.\n *\n * Note that this library does not map $mem cells. They must be mapped to logic\n * and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n * which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\n`ifndef NODIV\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n`endif\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
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  "xilinx": {
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  "abc9_model.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * 2019 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n\n// Box containing MUXF7.[AB] + MUXF8,\n// Necessary to make these an atomic unit so that\n// ABC cannot optimise just one of the MUXF7 away\n// and expect to save on its delay\n(* abc9_box, lib_whitebox *)\nmodule \\$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);\n assign O = S1 ? (S0 ? I3 : I2)\n : (S0 ? I1 : I0);\n specify\n (I0 => O) = 294;\n (I1 => O) = 297;\n (I2 => O) = 311;\n (I3 => O) = 317;\n (S0 => O) = 390;\n (S1 => O) = 273;\n endspecify\nendmodule\n",
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  "arith_map.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n// LCU\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _80_xilinx_lcu (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = WIDTH <= 2;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [WIDTH-1:0] S = P & ~G;\n\n\tgenerate for (i = 0; i < WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(G[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\tend endgenerate\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH = MAX_WIDTH - WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign CO = C;\n\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI (1'd0),\n\t\t\t.DI (GG[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4]),\n\t\t\t);\n\t\tend else begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI (C [i*4 - 1]),\n\t\t\t.DI (GG[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4]),\n\t\t\t);\n\t\tend\n\tend endgenerate\nend endgenerate\n\nendmodule\n\n\n// ============================================================================\n// ALU\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_xilinx_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\tparameter _TECHMAP_CONSTVAL_CI_ = 0;\n\tparameter _TECHMAP_CONSTMSK_CI_ = 0;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] S = {AA ^ BB};\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(AA[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\t\tXORCY xorcy (\n\t\t\t.CI(C[i]),\n\t\t\t.LI(S[i]),\n\t\t\t.O(Y[i])\n\t\t);\n\tend endgenerate\n\n\tassign X = S;\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] O;\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign Y = O, CO = C;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI (1'd0),\n\t\t\t.DI (DI[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.O (O [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4])\n\t\t\t);\n\t\tend else begin\n\t\t CARRY4 carry4\n\t\t (\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI (C [i*4 - 1]),\n\t\t\t.DI (DI[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.O (O [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4])\n\t\t );\n\t\tend\n\tend endgenerate\n\n\tassign X = S;\n\nend endgenerate\nendmodule\n\n",