@yowasp/yosys 0.43.750 → 0.44.759

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (4) hide show
  1. package/gen/resources-yosys.js +18 -6
  2. package/gen/share/quicklogic/qlf_k6n10f/bram_types_sim.v +1 -1
  3. package/gen/yosys.core.wasm +0 -0
  4. package/package.json +1 -1
package/gen/resources-yosys.js CHANGED
@@ -95,8 +95,8 @@ export const filesystem = {
95
95
  "brams.txt": "ram block $__GOWIN_SP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_DP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_SDP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tcost 128;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\tclock posedge;\n\t\tclken;\n\t}\n}\n",
96
96
  "brams_map.v": "`define DEF_FUNCS \\\n\tfunction [255:0] init_slice_x8; \\\n\t\tinput integer idx; \\\n\t\tinteger i; \\\n\t\tfor (i = 0; i < 32; i = i + 1) begin \\\n\t\t\tinit_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \\\n\t\tend \\\n\tendfunction \\\n\tfunction [287:0] init_slice_x9; \\\n\t\tinput integer idx; \\\n\t\tinit_slice_x9 = INIT[idx * 288+:288]; \\\n\tendfunction \\\n\n`define x8_width(width) (width / 9 * 8 + width % 9)\n`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}\n`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}\n`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})\n\n\n`define INIT(func) \\\n\t.INIT_RAM_00(func('h00)), \\\n\t.INIT_RAM_01(func('h01)), \\\n\t.INIT_RAM_02(func('h02)), \\\n\t.INIT_RAM_03(func('h03)), \\\n\t.INIT_RAM_04(func('h04)), \\\n\t.INIT_RAM_05(func('h05)), \\\n\t.INIT_RAM_06(func('h06)), \\\n\t.INIT_RAM_07(func('h07)), \\\n\t.INIT_RAM_08(func('h08)), \\\n\t.INIT_RAM_09(func('h09)), \\\n\t.INIT_RAM_0A(func('h0a)), \\\n\t.INIT_RAM_0B(func('h0b)), \\\n\t.INIT_RAM_0C(func('h0c)), \\\n\t.INIT_RAM_0D(func('h0d)), \\\n\t.INIT_RAM_0E(func('h0e)), \\\n\t.INIT_RAM_0F(func('h0f)), \\\n\t.INIT_RAM_10(func('h10)), \\\n\t.INIT_RAM_11(func('h11)), \\\n\t.INIT_RAM_12(func('h12)), \\\n\t.INIT_RAM_13(func('h13)), \\\n\t.INIT_RAM_14(func('h14)), \\\n\t.INIT_RAM_15(func('h15)), \\\n\t.INIT_RAM_16(func('h16)), \\\n\t.INIT_RAM_17(func('h17)), \\\n\t.INIT_RAM_18(func('h18)), \\\n\t.INIT_RAM_19(func('h19)), \\\n\t.INIT_RAM_1A(func('h1a)), \\\n\t.INIT_RAM_1B(func('h1b)), \\\n\t.INIT_RAM_1C(func('h1c)), \\\n\t.INIT_RAM_1D(func('h1d)), \\\n\t.INIT_RAM_1E(func('h1e)), \\\n\t.INIT_RAM_1F(func('h1f)), \\\n\t.INIT_RAM_20(func('h20)), \\\n\t.INIT_RAM_21(func('h21)), \\\n\t.INIT_RAM_22(func('h22)), \\\n\t.INIT_RAM_23(func('h23)), \\\n\t.INIT_RAM_24(func('h24)), \\\n\t.INIT_RAM_25(func('h25)), \\\n\t.INIT_RAM_26(func('h26)), \\\n\t.INIT_RAM_27(func('h27)), \\\n\t.INIT_RAM_28(func('h28)), \\\n\t.INIT_RAM_29(func('h29)), \\\n\t.INIT_RAM_2A(func('h2a)), \\\n\t.INIT_RAM_2B(func('h2b)), \\\n\t.INIT_RAM_2C(func('h2c)), \\\n\t.INIT_RAM_2D(func('h2d)), \\\n\t.INIT_RAM_2E(func('h2e)), \\\n\t.INIT_RAM_2F(func('h2f)), \\\n\t.INIT_RAM_30(func('h30)), \\\n\t.INIT_RAM_31(func('h31)), \\\n\t.INIT_RAM_32(func('h32)), \\\n\t.INIT_RAM_33(func('h33)), \\\n\t.INIT_RAM_34(func('h34)), \\\n\t.INIT_RAM_35(func('h35)), \\\n\t.INIT_RAM_36(func('h36)), \\\n\t.INIT_RAM_37(func('h37)), \\\n\t.INIT_RAM_38(func('h38)), \\\n\t.INIT_RAM_39(func('h39)), \\\n\t.INIT_RAM_3A(func('h3a)), \\\n\t.INIT_RAM_3B(func('h3b)), \\\n\t.INIT_RAM_3C(func('h3c)), \\\n\t.INIT_RAM_3D(func('h3d)), \\\n\t.INIT_RAM_3E(func('h3e)), \\\n\t.INIT_RAM_3F(func('h3f)),\n\nmodule $__GOWIN_SP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 36;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DO);\n\n\tSP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_A_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_A_RD_DATA = DO;\n\n\tSPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(PORT_A_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(PORT_A_WR_EN),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_DP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;\n\n`DEF_FUNCS\n\nwire RSTA = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire RSTB = OPTION_RESET_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST;\nwire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);\nwire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);\n\ngenerate\n\nif (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin\n\n\twire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);\n\twire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);\n\twire [15:0] DOA;\n\twire [15:0] DOB;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DOA);\n\tassign PORT_B_RD_DATA = `x8_rd_data(DOB);\n\n\tDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend else begin\n\n\twire [17:0] DIA = PORT_A_WR_DATA;\n\twire [17:0] DIB = PORT_B_WR_DATA;\n\twire [17:0] DOA;\n\twire [17:0] DOB;\n\n\tassign PORT_A_RD_DATA = DOA;\n\tassign PORT_B_RD_DATA = DOB;\n\n\tDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(PORT_A_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_B_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(PORT_A_WR_EN),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(PORT_B_WR_EN),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 18;\nparameter PORT_W_WIDTH = 18;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput PORT_W_WR_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST;\nwire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);\nwire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;\n\ngenerate\n\nif (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_R_RD_DATA = `x8_rd_data(DO);\n\n\tSDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_W_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_R_RD_DATA = DO;\n\n\tSDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(PORT_W_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_R_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n",
97
97
  "cells_map.v": "`default_nettype none\n//All DFF* have INIT, but the hardware is always initialised to the reset\n//value regardless. The parameter is ignored.\n\n// DFFN\t\t\t D Flip-Flop with Negative-Edge Clock\nmodule\t\\$_DFF_N_ (input D, C, output Q);\n\tDFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFF\t\t\t D Flip-Flop\nmodule\t\\$_DFF_P_ (input D, C, output Q);\n\tDFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFE\t\t\t D Flip-Flop with Clock Enable\nmodule\t\\$_DFFE_PP_ (input D, C, E, output Q);\n\tDFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNE\t\t D Flip-Flop with Negative-Edge Clock and Clock Enable\nmodule\t\\$_DFFE_NP_ (input D, C, E, output Q);\n\tDFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFR\t\t\t D Flip-Flop with Synchronous Reset\nmodule\t\\$_SDFF_PP0_ (input D, C, R, output Q);\n\tDFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNR\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Reset\nmodule\t\\$_SDFF_NP0_ (input D, C, R, output Q);\n\tDFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFRE\t\t D Flip-Flop with Clock Enable and Synchronous Reset\nmodule\t\\$_SDFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNRE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset\nmodule\t\\$_SDFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFS\t\t\t D Flip-Flop with Synchronous Set\nmodule\t\\$_SDFF_PP1_ (input D, C, R, output Q);\n\tDFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNS\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Set\nmodule\t\\$_SDFF_NP1_ (input D, C, R, output Q);\n\tDFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFSE\t\t D Flip-Flop with Clock Enable and Synchronous Set\nmodule\t\\$_SDFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNSE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set\nmodule\t\\$_SDFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFP\t\t\t D Flip-Flop with Asynchronous Preset\nmodule\t\\$_DFF_PP1_ (input D, C, R, output Q);\n\tDFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNP\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Preset\nmodule\t\\$_DFF_NP1_ (input D, C, R, output Q);\n\tDFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFC\t\t\t D Flip-Flop with Asynchronous Clear\nmodule\t\\$_DFF_PP0_ (input D, C, R, output Q);\n\tDFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNC\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Clear\nmodule\t\\$_DFF_NP0_ (input D, C, R, output Q);\n\tDFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFPE\t\t D Flip-Flop with Clock Enable and Asynchronous Preset\nmodule\t\\$_DFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNPE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset\nmodule\t\\$_DFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFCE\t\t D Flip-Flop with Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNCE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\t\tLUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]));\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tLUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tLUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tLUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\n\t\tend else\n\t\tif (WIDTH == 5) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));\n\t\t\tMUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 6) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));\n\t\t\tMUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 7) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));\n\t\t\tMUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 8) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));\n\t\t\tMUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));\n\t\tend else begin\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\tend\n\tendgenerate\nendmodule\n",
98
- "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n specify\n (negedge CLK => (Q : D)) = (480, 660);\n $setup(D, negedge CLK, 576);\n endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n input I, OEN;\n output O;\n assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n input I,OEN;\n output O;\n inout IO;\n assign IO = OEN ? 1'bz : I;\n assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\nmodule GSR (input GSRI);\n\twire GSRO = GSRI;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0 => COUT) = (1010, 1380);\n\t(I1 => COUT) = (1021, 1505);\n\t(I3 => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = I0 & I1;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\"; // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\"; // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n",
99
- "cells_xtra.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n \t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\nendmodule\n\nmodule DCS (...);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule FLASH128K (...);\ninput [31:0] DIN;\ninput [14:0] ADDR;\ninput CS,AE,OE;\ninput PCLK;\ninput PROG, SERA, MASE;\ninput NVSTR;\ninput IFREN;\ninput RESETN;\noutput [31:0] DOUT;\noutput TBIT;\nparameter IDLE = 4'd0,\n READ_S1 = 4'd1,\n READ_S2 = 4'd2,\n PROG_S1 = 4'd3,\n PROG_S2 = 4'd4,\n PROG_S3 = 4'd5,\n PROG_S4 = 4'd6,\n SERA_S1 = 4'd7,\n SERA_S2 = 4'd8,\n SERA_S3 = 4'd9,\n SERA_S4 = 4'd10,\n MASE_S1 = 4'd11,\n MASE_S2 = 4'd12,\n MASE_S3 = 4'd13,\n MASE_S4 = 4'd14;\nendmodule\n\nmodule MCU (...);\nendmodule\n\nmodule USB20_PHY (...);\nparameter DATABUS16_8 = 1'b0;\nparameter ADP_PRBEN = 1'b0;\nparameter TEST_MODE = 5'b00000;\nparameter HSDRV1 = 1'b0; \nparameter HSDRV0 = 1'b0; \nparameter CLK_SEL = 1'b0;\nparameter M = 4'b0000; \nparameter N = 6'b101000; \nparameter C = 2'b01; \nparameter FOC_LOCK = 1'b0;\ninput [15:0] DATAIN;\ninput TXVLD;\ninput TXVLDH;\ninput RESET;\ninput SUSPENDM;\ninput [1:0] XCVRSEL;\ninput TERMSEL;\ninput [1:0] OPMODE;\noutput [15:0] DATAOUT;\noutput TXREADY;\noutput RXACTIVE;\noutput RXVLD;\noutput RXVLDH;\noutput CLK; \noutput RXERROR;\ninout DP;\ninout DM;\noutput [1:0] LINESTATE;\ninput IDPULLUP;\ninput DPPD;\ninput DMPD;\ninput CHARGVBUS;\ninput DISCHARGVBUS;\ninput TXBITSTUFFEN;\ninput TXBITSTUFFENH;\ninput TXENN;\ninput TXDAT;\ninput TXSE0;\ninput FSLSSERIAL;\noutput HOSTDIS;\noutput IDDIG;\noutput ADPPRB;\noutput ADPSNS;\noutput SESSVLD;\noutput VBUSVLD;\noutput RXDP;\noutput RXDM;\noutput RXRCV;\noutput LBKERR;\noutput CLKRDY;\ninput INTCLK;\ninout ID;\ninout VBUS;\ninout REXT;\ninput XIN;\ninout XOUT;\ninput\tTEST;\noutput\tCLK480PAD;\ninput SCANCLK; \ninput SCANEN; \ninput SCANMODE; \ninput TRESETN; \ninput SCANIN1; \noutput SCANOUT1; \ninput SCANIN2; \noutput SCANOUT2; \ninput SCANIN3; \noutput SCANOUT3; \ninput SCANIN4; \noutput SCANOUT4; \ninput SCANIN5; \noutput SCANOUT5; \ninput SCANIN6; \noutput SCANOUT6; \nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule BANDGAP (...);\ninput BGEN;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule EMCU (...);\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK; \ninput HS_8BIT_MODE; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput LALIGN_EN; \ninput WALIGN_BY; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN; \ninput HSRX_STOP; \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON; \ninput RESET; \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH; \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ; \ninput DRST_N; \ninput ONE_BYTE0_MATCH; \ninput WORD_LENDIAN; \ninput [2:0] FIFO_RD_STD; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b1;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n",
98
+ "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n specify\n (negedge CLK => (Q : D)) = (480, 660);\n $setup(D, negedge CLK, 576);\n endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n input I, OEN;\n output O;\n assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n input I,OEN;\n output O;\n inout IO;\n assign IO = OEN ? 1'bz : I;\n assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox, keep *)\nmodule GSR (input GSRI);\nendmodule\n\n(* blackbox, keep *)\nmodule BANDGAP (input BGEN);\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0 => COUT) = (1010, 1380);\n\t(I1 => COUT) = (1021, 1505);\n\t(I3 => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = I0 & I1;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\"; // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\"; // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nparameter DCS_MODE = \"RISING\";\nendmodule\n\n\n\n",
99
+ "cells_xtra.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n \t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule FLASH128K (...);\ninput [31:0] DIN;\ninput [14:0] ADDR;\ninput CS,AE,OE;\ninput PCLK;\ninput PROG, SERA, MASE;\ninput NVSTR;\ninput IFREN;\ninput RESETN;\noutput [31:0] DOUT;\noutput TBIT;\nparameter IDLE = 4'd0,\n READ_S1 = 4'd1,\n READ_S2 = 4'd2,\n PROG_S1 = 4'd3,\n PROG_S2 = 4'd4,\n PROG_S3 = 4'd5,\n PROG_S4 = 4'd6,\n SERA_S1 = 4'd7,\n SERA_S2 = 4'd8,\n SERA_S3 = 4'd9,\n SERA_S4 = 4'd10,\n MASE_S1 = 4'd11,\n MASE_S2 = 4'd12,\n MASE_S3 = 4'd13,\n MASE_S4 = 4'd14;\nendmodule\n\nmodule MCU (...);\nendmodule\n\nmodule USB20_PHY (...);\nparameter DATABUS16_8 = 1'b0;\nparameter ADP_PRBEN = 1'b0;\nparameter TEST_MODE = 5'b00000;\nparameter HSDRV1 = 1'b0; \nparameter HSDRV0 = 1'b0; \nparameter CLK_SEL = 1'b0;\nparameter M = 4'b0000; \nparameter N = 6'b101000; \nparameter C = 2'b01; \nparameter FOC_LOCK = 1'b0;\ninput [15:0] DATAIN;\ninput TXVLD;\ninput TXVLDH;\ninput RESET;\ninput SUSPENDM;\ninput [1:0] XCVRSEL;\ninput TERMSEL;\ninput [1:0] OPMODE;\noutput [15:0] DATAOUT;\noutput TXREADY;\noutput RXACTIVE;\noutput RXVLD;\noutput RXVLDH;\noutput CLK; \noutput RXERROR;\ninout DP;\ninout DM;\noutput [1:0] LINESTATE;\ninput IDPULLUP;\ninput DPPD;\ninput DMPD;\ninput CHARGVBUS;\ninput DISCHARGVBUS;\ninput TXBITSTUFFEN;\ninput TXBITSTUFFENH;\ninput TXENN;\ninput TXDAT;\ninput TXSE0;\ninput FSLSSERIAL;\noutput HOSTDIS;\noutput IDDIG;\noutput ADPPRB;\noutput ADPSNS;\noutput SESSVLD;\noutput VBUSVLD;\noutput RXDP;\noutput RXDM;\noutput RXRCV;\noutput LBKERR;\noutput CLKRDY;\ninput INTCLK;\ninout ID;\ninout VBUS;\ninout REXT;\ninput XIN;\ninout XOUT;\ninput\tTEST;\noutput\tCLK480PAD;\ninput SCANCLK; \ninput SCANEN; \ninput SCANMODE; \ninput TRESETN; \ninput SCANIN1; \noutput SCANOUT1; \ninput SCANIN2; \noutput SCANOUT2; \ninput SCANIN3; \noutput SCANOUT3; \ninput SCANIN4; \noutput SCANOUT4; \ninput SCANIN5; \noutput SCANOUT5; \ninput SCANIN6; \noutput SCANOUT6; \nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule EMCU (...);\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK; \ninput HS_8BIT_MODE; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput LALIGN_EN; \ninput WALIGN_BY; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN; \ninput HSRX_STOP; \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON; \ninput RESET; \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH; \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ; \ninput DRST_N; \ninput ONE_BYTE0_MATCH; \ninput WORD_LENDIAN; \ninput [2:0] FIFO_RD_STD; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b1;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n",
100
100
  "lutrams.txt": "ram distributed $__GOWIN_LUTRAM_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\twidthscale;\n\tinit no_undef;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock posedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
101
101
  "lutrams_map.v": "module $__GOWIN_LUTRAM_(...);\n\nparameter INIT = 64'bx;\nparameter BITS_USED = 0;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput PORT_W_WR_EN;\ninput [3:0] PORT_W_WR_DATA;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nfunction [15:0] init_slice;\ninput integer idx;\ninteger i;\nfor (i = 0; i < 16; i = i + 1)\n\tinit_slice[i] = INIT[4*i+idx];\nendfunction\n\ngenerate\n\ncasez(BITS_USED)\n4'b000z:\nRAM16SDP1 #(\n\t.INIT_0(init_slice(0)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[0]),\n\t.DO(PORT_R_RD_DATA[0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n4'b00zz:\nRAM16SDP2 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA[1:0]),\n\t.DO(PORT_R_RD_DATA[1:0]),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\ndefault:\nRAM16SDP4 #(\n\t.INIT_0(init_slice(0)),\n\t.INIT_1(init_slice(1)),\n\t.INIT_2(init_slice(2)),\n\t.INIT_3(init_slice(3)),\n) _TECHMAP_REPLACE_ (\n\t.WAD(PORT_W_ADDR),\n\t.RAD(PORT_R_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.DO(PORT_R_RD_DATA),\n\t.CLK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\nendcase\n\nendgenerate\n\nendmodule\n",
102
102
  },
@@ -147,7 +147,7 @@ export const filesystem = {
147
147
  },
148
148
  "frontends": {
149
149
  "ast": {
150
- "ast.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * This is support code for the Verilog frontend at frontends/verilog\n *\n */\n\n#ifndef AST_H\n#define AST_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/fmt.h\"\n#include <stdint.h>\n#include <set>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace AST\n{\n\t// all node types, type2str() must be extended\n\t// whenever a new node type is added here\n\tenum AstNodeType\n\t{\n\t\tAST_NONE,\n\t\tAST_DESIGN,\n\t\tAST_MODULE,\n\t\tAST_TASK,\n\t\tAST_FUNCTION,\n\t\tAST_DPI_FUNCTION,\n\n\t\tAST_WIRE,\n\t\tAST_MEMORY,\n\t\tAST_AUTOWIRE,\n\t\tAST_PARAMETER,\n\t\tAST_LOCALPARAM,\n\t\tAST_DEFPARAM,\n\t\tAST_PARASET,\n\t\tAST_ARGUMENT,\n\t\tAST_RANGE,\n\t\tAST_MULTIRANGE,\n\t\tAST_CONSTANT,\n\t\tAST_REALVALUE,\n\t\tAST_CELLTYPE,\n\t\tAST_IDENTIFIER,\n\t\tAST_PREFIX,\n\t\tAST_ASSERT,\n\t\tAST_ASSUME,\n\t\tAST_LIVE,\n\t\tAST_FAIR,\n\t\tAST_COVER,\n\t\tAST_ENUM,\n\t\tAST_ENUM_ITEM,\n\n\t\tAST_FCALL,\n\t\tAST_TO_BITS,\n\t\tAST_TO_SIGNED,\n\t\tAST_TO_UNSIGNED,\n\t\tAST_SELFSZ,\n\t\tAST_CAST_SIZE,\n\t\tAST_CONCAT,\n\t\tAST_REPLICATE,\n\t\tAST_BIT_NOT,\n\t\tAST_BIT_AND,\n\t\tAST_BIT_OR,\n\t\tAST_BIT_XOR,\n\t\tAST_BIT_XNOR,\n\t\tAST_REDUCE_AND,\n\t\tAST_REDUCE_OR,\n\t\tAST_REDUCE_XOR,\n\t\tAST_REDUCE_XNOR,\n\t\tAST_REDUCE_BOOL,\n\t\tAST_SHIFT_LEFT,\n\t\tAST_SHIFT_RIGHT,\n\t\tAST_SHIFT_SLEFT,\n\t\tAST_SHIFT_SRIGHT,\n\t\tAST_SHIFTX,\n\t\tAST_SHIFT,\n\t\tAST_LT,\n\t\tAST_LE,\n\t\tAST_EQ,\n\t\tAST_NE,\n\t\tAST_EQX,\n\t\tAST_NEX,\n\t\tAST_GE,\n\t\tAST_GT,\n\t\tAST_ADD,\n\t\tAST_SUB,\n\t\tAST_MUL,\n\t\tAST_DIV,\n\t\tAST_MOD,\n\t\tAST_POW,\n\t\tAST_POS,\n\t\tAST_NEG,\n\t\tAST_LOGIC_AND,\n\t\tAST_LOGIC_OR,\n\t\tAST_LOGIC_NOT,\n\t\tAST_TERNARY,\n\t\tAST_MEMRD,\n\t\tAST_MEMWR,\n\t\tAST_MEMINIT,\n\n\t\tAST_TCALL,\n\t\tAST_ASSIGN,\n\t\tAST_CELL,\n\t\tAST_PRIMITIVE,\n\t\tAST_CELLARRAY,\n\t\tAST_ALWAYS,\n\t\tAST_INITIAL,\n\t\tAST_BLOCK,\n\t\tAST_ASSIGN_EQ,\n\t\tAST_ASSIGN_LE,\n\t\tAST_CASE,\n\t\tAST_COND,\n\t\tAST_CONDX,\n\t\tAST_CONDZ,\n\t\tAST_DEFAULT,\n\t\tAST_FOR,\n\t\tAST_WHILE,\n\t\tAST_REPEAT,\n\n\t\tAST_GENVAR,\n\t\tAST_GENFOR,\n\t\tAST_GENIF,\n\t\tAST_GENCASE,\n\t\tAST_GENBLOCK,\n\t\tAST_TECALL,\n\n\t\tAST_POSEDGE,\n\t\tAST_NEGEDGE,\n\t\tAST_EDGE,\n\n\t\tAST_INTERFACE,\n\t\tAST_INTERFACEPORT,\n\t\tAST_INTERFACEPORTTYPE,\n\t\tAST_MODPORT,\n\t\tAST_MODPORTMEMBER,\n\t\tAST_PACKAGE,\n\n\t\tAST_WIRETYPE,\n\t\tAST_TYPEDEF,\n\t\tAST_STRUCT,\n\t\tAST_UNION,\n\t\tAST_STRUCT_ITEM,\n\t\tAST_BIND\n\t};\n\n\tstruct AstSrcLocType {\n\t\tunsigned int first_line, last_line;\n\t\tunsigned int first_column, last_column;\n\t\tAstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}\n\t\tAstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}\n\t};\n\n\t// convert an node type to a string (e.g. for debug output)\n\tstd::string type2str(AstNodeType type);\n\n\t// The AST is built using instances of this struct\n\tstruct AstNode\n\t{\n\t\t// for dict<> and pool<>\n\t\tunsigned int hashidx_;\n\t\tunsigned int hash() const { return hashidx_; }\n\n\t\t// this nodes type\n\t\tAstNodeType type;\n\n\t\t// the list of child nodes for this node\n\t\tstd::vector<AstNode*> children;\n\n\t\t// the list of attributes assigned to this node\n\t\tstd::map<RTLIL::IdString, AstNode*> attributes;\n\t\tbool get_bool_attribute(RTLIL::IdString id);\n\n\t\t// node content - most of it is unused in most node types\n\t\tstd::string str;\n\t\tstd::vector<RTLIL::State> bits;\n\t\tbool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized, is_custom_type;\n\t\tint port_id, range_left, range_right;\n\t\tuint32_t integer;\n\t\tdouble realvalue;\n\t\t// set for IDs typed to an enumeration, not used\n\t\tbool is_enum;\n\n\t\t// Declared range for array dimension.\n\t\tstruct dimension_t {\n\t\t\tint range_right; // lsb in [msb:lsb]\n\t\t\tint range_width; // msb - lsb + 1\n\t\t\tbool range_swapped; // if the declared msb < lsb, msb and lsb above are swapped\n\t\t};\n\t\t// Packed and unpacked dimensions for arrays.\n\t\t// Unpacked dimensions go first, to follow the order of indexing.\n\t\tstd::vector<dimension_t> dimensions;\n\t\t// Number of unpacked dimensions.\n\t\tint unpacked_dimensions;\n\n\t\t// this is set by simplify and used during RTLIL generation\n\t\tAstNode *id2ast;\n\n\t\t// this is used by simplify to detect if basic analysis has been performed already on the node\n\t\tbool basic_prep;\n\n\t\t// this is used for ID references in RHS expressions that should use the \"new\" value for non-blocking assignments\n\t\tbool lookahead;\n\n\t\t// this is the original sourcecode location that resulted in this AST node\n\t\t// it is automatically set by the constructor using AST::current_filename and\n\t\t// the AST::get_line_num() callback function.\n\t\tstd::string filename;\n\t\tAstSrcLocType location;\n\n\t\t// are we embedded in an lvalue, param?\n\t\t// (see fixup_hierarchy_flags)\n\t\tbool in_lvalue;\n\t\tbool in_param;\n\t\tbool in_lvalue_from_above;\n\t\tbool in_param_from_above;\n\n\t\t// creating and deleting nodes\n\t\tAstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr);\n\t\tAstNode *clone() const;\n\t\tvoid cloneInto(AstNode *other) const;\n\t\tvoid delete_children();\n\t\t~AstNode();\n\n\t\tenum mem2reg_flags\n\t\t{\n\t\t\t/* status flags */\n\t\t\tMEM2REG_FL_ALL = 0x00000001,\n\t\t\tMEM2REG_FL_ASYNC = 0x00000002,\n\t\t\tMEM2REG_FL_INIT = 0x00000004,\n\n\t\t\t/* candidate flags */\n\t\t\tMEM2REG_FL_FORCED = 0x00000100,\n\t\t\tMEM2REG_FL_SET_INIT = 0x00000200,\n\t\t\tMEM2REG_FL_SET_ELSE = 0x00000400,\n\t\t\tMEM2REG_FL_SET_ASYNC = 0x00000800,\n\t\t\tMEM2REG_FL_EQ2 = 0x00001000,\n\t\t\tMEM2REG_FL_CMPLX_LHS = 0x00002000,\n\t\t\tMEM2REG_FL_CONST_LHS = 0x00004000,\n\t\t\tMEM2REG_FL_VAR_LHS = 0x00008000,\n\n\t\t\t/* proc flags */\n\t\t\tMEM2REG_FL_EQ1 = 0x01000000,\n\t\t};\n\n\t\t// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.\n\t\t// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()\n\t\tbool simplify(bool const_fold, int stage, int width_hint, bool sign_hint);\n\t\tvoid replace_result_wire_name_in_function(const std::string &from, const std::string &to);\n\t\tAstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);\n\t\tvoid expand_genblock(const std::string &prefix);\n\t\tvoid label_genblks(std::set<std::string>& existing, int &counter);\n\t\tvoid mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,\n\t\t\t\tdict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);\n\t\tbool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);\n\t\tbool mem2reg_check(pool<AstNode*> &mem2reg_set);\n\t\tvoid mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);\n\t\tvoid meminfo(int &mem_width, int &mem_size, int &addr_bits);\n\t\tbool detect_latch(const std::string &var);\n\t\tconst RTLIL::Module* lookup_cell_module();\n\n\t\t// additional functionality for evaluating constant functions\n\t\tstruct varinfo_t {\n\t\t\tRTLIL::Const val;\n\t\t\tint offset;\n\t\t\tbool range_swapped;\n\t\t\tbool is_signed;\n\t\t\tAstNode *arg = nullptr;\n\t\t\tbool explicitly_sized;\n\t\t};\n\t\tbool has_const_only_constructs();\n\t\tbool replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall, bool must_succeed);\n\t\tAstNode *eval_const_function(AstNode *fcall, bool must_succeed);\n\t\tbool is_simple_const_expr();\n\n\t\t// helper for parsing format strings\n\t\tFmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0, bool may_fail = false);\n\n\t\tbool is_recursive_function() const;\n\t\tstd::pair<AstNode*, AstNode*> get_tern_choice();\n\n\t\t// create a human-readable text representation of the AST (for debugging)\n\t\tvoid dumpAst(FILE *f, std::string indent) const;\n\t\tvoid dumpVlog(FILE *f, std::string indent) const;\n\n\t\t// Generate RTLIL for a bind construct\n\t\tstd::vector<RTLIL::Binding *> genBindings() const;\n\n\t\t// used by genRTLIL() for detecting expression width and sign\n\t\tvoid detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\t\tvoid detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\n\t\t// create RTLIL code for this AST node\n\t\t// for expressions the resulting signal vector is returned\n\t\t// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module\n\t\tRTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);\n\t\tRTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);\n\n\t\t// compare AST nodes\n\t\tbool operator==(const AstNode &other) const;\n\t\tbool operator!=(const AstNode &other) const;\n\t\tbool contains(const AstNode *other) const;\n\n\t\t// helper functions for creating AST nodes for constants\n\t\tstatic AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);\n\t\tstatic AstNode *mkconst_str(const std::vector<RTLIL::State> &v);\n\t\tstatic AstNode *mkconst_str(const std::string &str);\n\n\t\t// helper function to create an AST node for a temporary register\n\t\tAstNode *mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed);\n\n\t\t// helper function for creating sign-extended const objects\n\t\tRTLIL::Const bitsAsConst(int width, bool is_signed);\n\t\tRTLIL::Const bitsAsConst(int width = -1);\n\t\tRTLIL::Const bitsAsUnsizedConst(int width);\n\t\tRTLIL::Const asAttrConst() const;\n\t\tRTLIL::Const asParaConst() const;\n\t\tuint64_t asInt(bool is_signed);\n\t\tbool bits_only_01() const;\n\t\tbool asBool() const;\n\n\t\t// helper functions for real valued const eval\n\t\tint isConst() const; // return '1' for AST_CONSTANT and '2' for AST_REALVALUE\n\t\tdouble asReal(bool is_signed);\n\t\tRTLIL::Const realAsConst(int width);\n\n\t\t// helpers for enum\n\t\tvoid allocateDefaultEnumValues();\n\t\tvoid annotateTypedEnums(AstNode *template_node);\n\n\t\t// helpers for locations\n\t\tstd::string loc_string() const;\n\n\t\t// Helper for looking up identifiers which are prefixed with the current module name\n\t\tstd::string try_pop_module_prefix() const;\n\n\t\t// helper to clone the node with some of its subexpressions replaced with zero (this is used\n\t\t// to evaluate widths of dynamic ranges)\n\t\tAstNode *clone_at_zero();\n\n\t\tvoid set_attribute(RTLIL::IdString key, AstNode *node)\n\t\t{\n\t\t\tattributes[key] = node;\n\t\t\tnode->set_in_param_flag(true);\n\t\t}\n\n\t\t// helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag\n\t\t// can be overridden based on the intrinsic properties of this node, i.e. based on its type)\n\t\tvoid set_in_lvalue_flag(bool flag, bool no_descend = false);\n\t\tvoid set_in_param_flag(bool flag, bool no_descend = false);\n\n\t\t// fix up the hierarchy flags (in_lvalue/in_param) of this node and its children\n\t\t//\n\t\t// to keep the flags in sync, fixup_hierarchy_flags(true) needs to be called once after\n\t\t// parsing the AST to walk the full tree, then plain fixup_hierarchy_flags() performs\n\t\t// localized fixups after modifying children/attributes of a particular node\n\t\tvoid fixup_hierarchy_flags(bool force_descend = false);\n\n\t\t// helpers for indexing\n\t\tAstNode *make_index_range(AstNode *node, bool unpacked_range = false);\n\t\tAstNode *get_struct_member() const;\n\n\t\t// helper to print errors from simplify/genrtlil code\n\t\t[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));\n\t};\n\n\t// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code\n\tvoid process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,\n\t\t\tbool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire);\n\n\t// parametric modules are supported directly by the AST library\n\t// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions\n\tstruct AstModule : RTLIL::Module {\n\t\tAstNode *ast;\n\t\tbool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;\n\t\t~AstModule() override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;\n\t\tstd::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);\n\t\tvoid expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;\n\t\tbool reprocess_if_necessary(RTLIL::Design *design) override;\n\t\tRTLIL::Module *clone() const override;\n\t\tvoid loadconfig() const;\n\t};\n\n\t// this must be set by the language frontend before parsing the sources\n\t// the AstNode constructor then uses current_filename and get_line_num()\n\t// to initialize the filename and linenum properties of new nodes\n\textern std::string current_filename;\n\textern void (*set_line_num)(int);\n\textern int (*get_line_num)();\n\n\t// set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive\n\t// to control the filename and linenum properties of new nodes not generated by a frontend parser)\n\tvoid use_internal_line_num();\n\n\t// call a DPI function\n\tAstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);\n\n\t// Helper functions related to handling SystemVerilog interfaces\n\tstd::pair<std::string,std::string> split_modport_from_type(std::string name_type);\n\tAstNode * find_modport(AstNode *intf, std::string name);\n\tvoid explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);\n\n\t// Helper for setting the src attribute.\n\tvoid set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);\n\n\t// generate standard $paramod... derived module name; parameters should be\n\t// in the order they are declared in the instantiated module\n\tstd::string derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters);\n\n\t// used to provide simplify() access to the current design for looking up\n\t// modules, ports, wires, etc.\n\tvoid set_simplify_design_context(const RTLIL::Design *design);\n}\n\nnamespace AST_INTERNAL\n{\n\t// internal state variables\n\textern bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;\n\textern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_pwires, flag_autowire;\n\textern AST::AstNode *current_ast, *current_ast_mod;\n\textern std::map<std::string, AST::AstNode*> current_scope;\n\textern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;\n\textern RTLIL::SigSpec ignoreThisSignalsInInitial;\n\textern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;\n\textern RTLIL::Module *current_module;\n\textern bool current_always_clocked;\n\textern dict<std::string, int> current_memwr_count;\n\textern dict<std::string, pool<int>> current_memwr_visible;\n\tstruct LookaheadRewriter;\n\tstruct ProcessGenerator;\n\n\t// Create and add a new AstModule from new_ast, then use it to replace\n\t// old_module in design, renaming old_module to move it out of the way.\n\t// Return the new module.\n\t//\n\t// If original_ast is not null, it will be used as the AST node for the\n\t// new module. Otherwise, new_ast will be used.\n\tRTLIL::Module *\n\tprocess_and_replace_module(RTLIL::Design *design,\n\t RTLIL::Module *old_module,\n\t AST::AstNode *new_ast,\n\t AST::AstNode *original_ast = nullptr);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
150
+ "ast.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The AST frontend library is not a frontend on its own but provides an\n * abstract syntax tree (AST) abstraction for the open source Verilog frontend\n * at frontends/verilog.\n *\n */\n\n#ifndef AST_H\n#define AST_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/fmt.h\"\n#include <stdint.h>\n#include <set>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace AST\n{\n\t// all node types, type2str() must be extended\n\t// whenever a new node type is added here\n\tenum AstNodeType\n\t{\n\t\tAST_NONE,\n\t\tAST_DESIGN,\n\t\tAST_MODULE,\n\t\tAST_TASK,\n\t\tAST_FUNCTION,\n\t\tAST_DPI_FUNCTION,\n\n\t\tAST_WIRE,\n\t\tAST_MEMORY,\n\t\tAST_AUTOWIRE,\n\t\tAST_PARAMETER,\n\t\tAST_LOCALPARAM,\n\t\tAST_DEFPARAM,\n\t\tAST_PARASET,\n\t\tAST_ARGUMENT,\n\t\tAST_RANGE,\n\t\tAST_MULTIRANGE,\n\t\tAST_CONSTANT,\n\t\tAST_REALVALUE,\n\t\tAST_CELLTYPE,\n\t\tAST_IDENTIFIER,\n\t\tAST_PREFIX,\n\t\tAST_ASSERT,\n\t\tAST_ASSUME,\n\t\tAST_LIVE,\n\t\tAST_FAIR,\n\t\tAST_COVER,\n\t\tAST_ENUM,\n\t\tAST_ENUM_ITEM,\n\n\t\tAST_FCALL,\n\t\tAST_TO_BITS,\n\t\tAST_TO_SIGNED,\n\t\tAST_TO_UNSIGNED,\n\t\tAST_SELFSZ,\n\t\tAST_CAST_SIZE,\n\t\tAST_CONCAT,\n\t\tAST_REPLICATE,\n\t\tAST_BIT_NOT,\n\t\tAST_BIT_AND,\n\t\tAST_BIT_OR,\n\t\tAST_BIT_XOR,\n\t\tAST_BIT_XNOR,\n\t\tAST_REDUCE_AND,\n\t\tAST_REDUCE_OR,\n\t\tAST_REDUCE_XOR,\n\t\tAST_REDUCE_XNOR,\n\t\tAST_REDUCE_BOOL,\n\t\tAST_SHIFT_LEFT,\n\t\tAST_SHIFT_RIGHT,\n\t\tAST_SHIFT_SLEFT,\n\t\tAST_SHIFT_SRIGHT,\n\t\tAST_SHIFTX,\n\t\tAST_SHIFT,\n\t\tAST_LT,\n\t\tAST_LE,\n\t\tAST_EQ,\n\t\tAST_NE,\n\t\tAST_EQX,\n\t\tAST_NEX,\n\t\tAST_GE,\n\t\tAST_GT,\n\t\tAST_ADD,\n\t\tAST_SUB,\n\t\tAST_MUL,\n\t\tAST_DIV,\n\t\tAST_MOD,\n\t\tAST_POW,\n\t\tAST_POS,\n\t\tAST_NEG,\n\t\tAST_LOGIC_AND,\n\t\tAST_LOGIC_OR,\n\t\tAST_LOGIC_NOT,\n\t\tAST_TERNARY,\n\t\tAST_MEMRD,\n\t\tAST_MEMWR,\n\t\tAST_MEMINIT,\n\n\t\tAST_TCALL,\n\t\tAST_ASSIGN,\n\t\tAST_CELL,\n\t\tAST_PRIMITIVE,\n\t\tAST_CELLARRAY,\n\t\tAST_ALWAYS,\n\t\tAST_INITIAL,\n\t\tAST_BLOCK,\n\t\tAST_ASSIGN_EQ,\n\t\tAST_ASSIGN_LE,\n\t\tAST_CASE,\n\t\tAST_COND,\n\t\tAST_CONDX,\n\t\tAST_CONDZ,\n\t\tAST_DEFAULT,\n\t\tAST_FOR,\n\t\tAST_WHILE,\n\t\tAST_REPEAT,\n\n\t\tAST_GENVAR,\n\t\tAST_GENFOR,\n\t\tAST_GENIF,\n\t\tAST_GENCASE,\n\t\tAST_GENBLOCK,\n\t\tAST_TECALL,\n\n\t\tAST_POSEDGE,\n\t\tAST_NEGEDGE,\n\t\tAST_EDGE,\n\n\t\tAST_INTERFACE,\n\t\tAST_INTERFACEPORT,\n\t\tAST_INTERFACEPORTTYPE,\n\t\tAST_MODPORT,\n\t\tAST_MODPORTMEMBER,\n\t\tAST_PACKAGE,\n\n\t\tAST_WIRETYPE,\n\t\tAST_TYPEDEF,\n\t\tAST_STRUCT,\n\t\tAST_UNION,\n\t\tAST_STRUCT_ITEM,\n\t\tAST_BIND\n\t};\n\n\tstruct AstSrcLocType {\n\t\tunsigned int first_line, last_line;\n\t\tunsigned int first_column, last_column;\n\t\tAstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}\n\t\tAstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}\n\t};\n\n\t// convert an node type to a string (e.g. for debug output)\n\tstd::string type2str(AstNodeType type);\n\n\t// The AST is built using instances of this struct\n\tstruct AstNode\n\t{\n\t\t// for dict<> and pool<>\n\t\tunsigned int hashidx_;\n\t\tunsigned int hash() const { return hashidx_; }\n\n\t\t// this nodes type\n\t\tAstNodeType type;\n\n\t\t// the list of child nodes for this node\n\t\tstd::vector<AstNode*> children;\n\n\t\t// the list of attributes assigned to this node\n\t\tstd::map<RTLIL::IdString, AstNode*> attributes;\n\t\tbool get_bool_attribute(RTLIL::IdString id);\n\n\t\t// node content - most of it is unused in most node types\n\t\tstd::string str;\n\t\tstd::vector<RTLIL::State> bits;\n\t\tbool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized, is_custom_type;\n\t\tint port_id, range_left, range_right;\n\t\tuint32_t integer;\n\t\tdouble realvalue;\n\t\t// set for IDs typed to an enumeration, not used\n\t\tbool is_enum;\n\n\t\t// Declared range for array dimension.\n\t\tstruct dimension_t {\n\t\t\tint range_right; // lsb in [msb:lsb]\n\t\t\tint range_width; // msb - lsb + 1\n\t\t\tbool range_swapped; // if the declared msb < lsb, msb and lsb above are swapped\n\t\t};\n\t\t// Packed and unpacked dimensions for arrays.\n\t\t// Unpacked dimensions go first, to follow the order of indexing.\n\t\tstd::vector<dimension_t> dimensions;\n\t\t// Number of unpacked dimensions.\n\t\tint unpacked_dimensions;\n\n\t\t// this is set by simplify and used during RTLIL generation\n\t\tAstNode *id2ast;\n\n\t\t// this is used by simplify to detect if basic analysis has been performed already on the node\n\t\tbool basic_prep;\n\n\t\t// this is used for ID references in RHS expressions that should use the \"new\" value for non-blocking assignments\n\t\tbool lookahead;\n\n\t\t// this is the original sourcecode location that resulted in this AST node\n\t\t// it is automatically set by the constructor using AST::current_filename and\n\t\t// the AST::get_line_num() callback function.\n\t\tstd::string filename;\n\t\tAstSrcLocType location;\n\n\t\t// are we embedded in an lvalue, param?\n\t\t// (see fixup_hierarchy_flags)\n\t\tbool in_lvalue;\n\t\tbool in_param;\n\t\tbool in_lvalue_from_above;\n\t\tbool in_param_from_above;\n\n\t\t// creating and deleting nodes\n\t\tAstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr);\n\t\tAstNode *clone() const;\n\t\tvoid cloneInto(AstNode *other) const;\n\t\tvoid delete_children();\n\t\t~AstNode();\n\n\t\tenum mem2reg_flags\n\t\t{\n\t\t\t/* status flags */\n\t\t\tMEM2REG_FL_ALL = 0x00000001,\n\t\t\tMEM2REG_FL_ASYNC = 0x00000002,\n\t\t\tMEM2REG_FL_INIT = 0x00000004,\n\n\t\t\t/* candidate flags */\n\t\t\tMEM2REG_FL_FORCED = 0x00000100,\n\t\t\tMEM2REG_FL_SET_INIT = 0x00000200,\n\t\t\tMEM2REG_FL_SET_ELSE = 0x00000400,\n\t\t\tMEM2REG_FL_SET_ASYNC = 0x00000800,\n\t\t\tMEM2REG_FL_EQ2 = 0x00001000,\n\t\t\tMEM2REG_FL_CMPLX_LHS = 0x00002000,\n\t\t\tMEM2REG_FL_CONST_LHS = 0x00004000,\n\t\t\tMEM2REG_FL_VAR_LHS = 0x00008000,\n\n\t\t\t/* proc flags */\n\t\t\tMEM2REG_FL_EQ1 = 0x01000000,\n\t\t};\n\n\t\t// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.\n\t\t// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()\n\t\tbool simplify(bool const_fold, int stage, int width_hint, bool sign_hint);\n\t\tvoid replace_result_wire_name_in_function(const std::string &from, const std::string &to);\n\t\tAstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);\n\t\tvoid expand_genblock(const std::string &prefix);\n\t\tvoid label_genblks(std::set<std::string>& existing, int &counter);\n\t\tvoid mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,\n\t\t\t\tdict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);\n\t\tbool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);\n\t\tbool mem2reg_check(pool<AstNode*> &mem2reg_set);\n\t\tvoid mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);\n\t\tvoid meminfo(int &mem_width, int &mem_size, int &addr_bits);\n\t\tbool detect_latch(const std::string &var);\n\t\tconst RTLIL::Module* lookup_cell_module();\n\n\t\t// additional functionality for evaluating constant functions\n\t\tstruct varinfo_t {\n\t\t\tRTLIL::Const val;\n\t\t\tint offset;\n\t\t\tbool range_swapped;\n\t\t\tbool is_signed;\n\t\t\tAstNode *arg = nullptr;\n\t\t\tbool explicitly_sized;\n\t\t};\n\t\tbool has_const_only_constructs();\n\t\tbool replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall, bool must_succeed);\n\t\tAstNode *eval_const_function(AstNode *fcall, bool must_succeed);\n\t\tbool is_simple_const_expr();\n\n\t\t// helper for parsing format strings\n\t\tFmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0, bool may_fail = false);\n\n\t\tbool is_recursive_function() const;\n\t\tstd::pair<AstNode*, AstNode*> get_tern_choice();\n\n\t\t// create a human-readable text representation of the AST (for debugging)\n\t\tvoid dumpAst(FILE *f, std::string indent) const;\n\t\tvoid dumpVlog(FILE *f, std::string indent) const;\n\n\t\t// Generate RTLIL for a bind construct\n\t\tstd::vector<RTLIL::Binding *> genBindings() const;\n\n\t\t// used by genRTLIL() for detecting expression width and sign\n\t\tvoid detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\t\tvoid detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);\n\n\t\t// create RTLIL code for this AST node\n\t\t// for expressions the resulting signal vector is returned\n\t\t// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module\n\t\tRTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);\n\t\tRTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);\n\n\t\t// compare AST nodes\n\t\tbool operator==(const AstNode &other) const;\n\t\tbool operator!=(const AstNode &other) const;\n\t\tbool contains(const AstNode *other) const;\n\n\t\t// helper functions for creating AST nodes for constants\n\t\tstatic AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized);\n\t\tstatic AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);\n\t\tstatic AstNode *mkconst_str(const std::vector<RTLIL::State> &v);\n\t\tstatic AstNode *mkconst_str(const std::string &str);\n\n\t\t// helper function to create an AST node for a temporary register\n\t\tAstNode *mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed);\n\n\t\t// helper function for creating sign-extended const objects\n\t\tRTLIL::Const bitsAsConst(int width, bool is_signed);\n\t\tRTLIL::Const bitsAsConst(int width = -1);\n\t\tRTLIL::Const bitsAsUnsizedConst(int width);\n\t\tRTLIL::Const asAttrConst() const;\n\t\tRTLIL::Const asParaConst() const;\n\t\tuint64_t asInt(bool is_signed);\n\t\tbool bits_only_01() const;\n\t\tbool asBool() const;\n\n\t\t// helper functions for real valued const eval\n\t\tint isConst() const; // return '1' for AST_CONSTANT and '2' for AST_REALVALUE\n\t\tdouble asReal(bool is_signed);\n\t\tRTLIL::Const realAsConst(int width);\n\n\t\t// helpers for enum\n\t\tvoid allocateDefaultEnumValues();\n\t\tvoid annotateTypedEnums(AstNode *template_node);\n\n\t\t// helpers for locations\n\t\tstd::string loc_string() const;\n\n\t\t// Helper for looking up identifiers which are prefixed with the current module name\n\t\tstd::string try_pop_module_prefix() const;\n\n\t\t// helper to clone the node with some of its subexpressions replaced with zero (this is used\n\t\t// to evaluate widths of dynamic ranges)\n\t\tAstNode *clone_at_zero();\n\n\t\tvoid set_attribute(RTLIL::IdString key, AstNode *node)\n\t\t{\n\t\t\tattributes[key] = node;\n\t\t\tnode->set_in_param_flag(true);\n\t\t}\n\n\t\t// helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag\n\t\t// can be overridden based on the intrinsic properties of this node, i.e. based on its type)\n\t\tvoid set_in_lvalue_flag(bool flag, bool no_descend = false);\n\t\tvoid set_in_param_flag(bool flag, bool no_descend = false);\n\n\t\t// fix up the hierarchy flags (in_lvalue/in_param) of this node and its children\n\t\t//\n\t\t// to keep the flags in sync, fixup_hierarchy_flags(true) needs to be called once after\n\t\t// parsing the AST to walk the full tree, then plain fixup_hierarchy_flags() performs\n\t\t// localized fixups after modifying children/attributes of a particular node\n\t\tvoid fixup_hierarchy_flags(bool force_descend = false);\n\n\t\t// helpers for indexing\n\t\tAstNode *make_index_range(AstNode *node, bool unpacked_range = false);\n\t\tAstNode *get_struct_member() const;\n\n\t\t// helper to print errors from simplify/genrtlil code\n\t\t[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));\n\t};\n\n\t// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code\n\tvoid process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,\n\t\t\tbool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire);\n\n\t// parametric modules are supported directly by the AST library\n\t// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions\n\tstruct AstModule : RTLIL::Module {\n\t\tAstNode *ast;\n\t\tbool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;\n\t\t~AstModule() override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;\n\t\tRTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;\n\t\tstd::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);\n\t\tvoid expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;\n\t\tbool reprocess_if_necessary(RTLIL::Design *design) override;\n\t\tRTLIL::Module *clone() const override;\n\t\tvoid loadconfig() const;\n\t};\n\n\t// this must be set by the language frontend before parsing the sources\n\t// the AstNode constructor then uses current_filename and get_line_num()\n\t// to initialize the filename and linenum properties of new nodes\n\textern std::string current_filename;\n\textern void (*set_line_num)(int);\n\textern int (*get_line_num)();\n\n\t// set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive\n\t// to control the filename and linenum properties of new nodes not generated by a frontend parser)\n\tvoid use_internal_line_num();\n\n\t// call a DPI function\n\tAstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);\n\n\t// Helper functions related to handling SystemVerilog interfaces\n\tstd::pair<std::string,std::string> split_modport_from_type(std::string name_type);\n\tAstNode * find_modport(AstNode *intf, std::string name);\n\tvoid explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);\n\n\t// Helper for setting the src attribute.\n\tvoid set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);\n\n\t// generate standard $paramod... derived module name; parameters should be\n\t// in the order they are declared in the instantiated module\n\tstd::string derived_module_name(std::string stripped_name, const std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> &parameters);\n\n\t// used to provide simplify() access to the current design for looking up\n\t// modules, ports, wires, etc.\n\tvoid set_simplify_design_context(const RTLIL::Design *design);\n}\n\nnamespace AST_INTERNAL\n{\n\t// internal state variables\n\textern bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;\n\textern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_pwires, flag_autowire;\n\textern AST::AstNode *current_ast, *current_ast_mod;\n\textern std::map<std::string, AST::AstNode*> current_scope;\n\textern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;\n\textern RTLIL::SigSpec ignoreThisSignalsInInitial;\n\textern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;\n\textern RTLIL::Module *current_module;\n\textern bool current_always_clocked;\n\textern dict<std::string, int> current_memwr_count;\n\textern dict<std::string, pool<int>> current_memwr_visible;\n\tstruct LookaheadRewriter;\n\tstruct ProcessGenerator;\n\n\t// Create and add a new AstModule from new_ast, then use it to replace\n\t// old_module in design, renaming old_module to move it out of the way.\n\t// Return the new module.\n\t//\n\t// If original_ast is not null, it will be used as the AST node for the\n\t// new module. Otherwise, new_ast will be used.\n\tRTLIL::Module *\n\tprocess_and_replace_module(RTLIL::Design *design,\n\t RTLIL::Module *old_module,\n\t AST::AstNode *new_ast,\n\t AST::AstNode *original_ast = nullptr);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
151
151
  "ast_binding.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * This header declares the AST::Binding class\n *\n * This is used to support the bind directive and is to RTLIL::Binding as\n * AST::AstModule is to RTLIL::Module, holding a syntax-level representation of\n * cells until we get to a stage where they make sense. In the case of a bind\n * directive, this is when we elaborate the design in the hierarchy pass.\n *\n */\n\n#ifndef AST_BINDING_H\n#define AST_BINDING_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/binding.h\"\n\n#include <memory>\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace AST\n{\n\tclass Binding : public RTLIL::Binding\n\t{\n\tpublic:\n\t\tBinding(RTLIL::IdString target_type,\n\t\t RTLIL::IdString target_name,\n\t\t const AstNode &cell);\n\n\t\tstd::string describe() const override;\n\n\tprivate:\n\t\t// The syntax-level representation of the cell to be bound.\n\t\tstd::unique_ptr<AstNode> ast_node;\n\t};\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
152
152
  },
153
153
  "blif": {
@@ -156,17 +156,18 @@ export const filesystem = {
156
156
  },
157
157
  "kernel": {
158
158
  "binding.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef BINDING_H\n#define BINDING_H\n\n#include \"kernel/rtlil.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct RTLIL::Binding\n{\n\t// Represents a bind construct.\n\t//\n\t// The target of the binding is represented by target_type and\n\t// target_name (see comments above the fields).\n\n\tBinding(RTLIL::IdString target_type,\n\t RTLIL::IdString target_name);\n\n\tvirtual ~Binding() {}\n\n\t// Return a string describing the binding\n\tvirtual std::string describe() const = 0;\n\nprotected:\n\t// May be empty. If not, it's the name of the module or interface to\n\t// bind to.\n\tRTLIL::IdString target_type;\n\n\t// If target_type is nonempty (the usual case), this is a hierarchical\n\t// reference to the bind target. If target_type is empty, we have to\n\t// wait until the hierarchy pass to figure out whether this was the name\n\t// of a module/interface type or an instance.\n\tRTLIL::IdString target_name;\n\n\t// An attribute name which contains an ID that's unique across binding\n\t// instances (used to ensure we don't apply a binding twice to a module)\n\tRTLIL::IdString attr_name;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
159
+ "bitpattern.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef BITPATTERN_H\n#define BITPATTERN_H\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct BitPatternPool\n{\n\tint width;\n\tstruct bits_t {\n\t\tstd::vector<RTLIL::State> bitdata;\n\t\tmutable unsigned int cached_hash;\n\t\tbits_t(int width = 0) : bitdata(width), cached_hash(0) { }\n\t\tRTLIL::State &operator[](int index) {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tconst RTLIL::State &operator[](int index) const {\n\t\t\treturn bitdata[index];\n\t\t}\n\t\tbool operator==(const bits_t &other) const {\n\t\t\tif (hash() != other.hash())\n\t\t\t\treturn false;\n\t\t\treturn bitdata == other.bitdata;\n\t\t}\n\t\tunsigned int hash() const {\n\t\t\tif (!cached_hash)\n\t\t\t\tcached_hash = hash_ops<std::vector<RTLIL::State>>::hash(bitdata);\n\t\t\treturn cached_hash;\n\t\t}\n\t};\n\tpool<bits_t> database;\n\n\tBitPatternPool(RTLIL::SigSpec sig)\n\t{\n\t\twidth = sig.size();\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\tif (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)\n\t\t\t\t\tpattern[i] = sig[i].data;\n\t\t\t\telse\n\t\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\t}\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tBitPatternPool(int width)\n\t{\n\t\tthis->width = width;\n\t\tif (width > 0) {\n\t\t\tbits_t pattern(width);\n\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\tpattern[i] = RTLIL::State::Sa;\n\t\t\tdatabase.insert(pattern);\n\t\t}\n\t}\n\n\tbits_t sig2bits(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits;\n\t\tbits.bitdata = sig.as_const().bits;\n\t\tfor (auto &b : bits.bitdata)\n\t\t\tif (b > RTLIL::State::S1)\n\t\t\t\tb = RTLIL::State::Sa;\n\t\treturn bits;\n\t}\n\n\tbool match(bits_t a, bits_t b)\n\t{\n\t\tlog_assert(int(a.bitdata.size()) == width);\n\t\tlog_assert(int(b.bitdata.size()) == width);\n\t\tfor (int i = 0; i < width; i++)\n\t\t\tif (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool has_any(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool has_all(RTLIL::SigSpec sig)\n\t{\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto &it : database)\n\t\t\tif (match(it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++)\n\t\t\t\t\tif (bits[i] > RTLIL::State::S1 && it[i] <= RTLIL::State::S1)\n\t\t\t\t\t\tgoto next_database_entry;\n\t\t\t\treturn true;\n\tnext_database_entry:;\n\t\t\t}\n\t\treturn false;\n\t}\n\n\tbool take(RTLIL::SigSpec sig)\n\t{\n\t\tbool status = false;\n\t\tbits_t bits = sig2bits(sig);\n\t\tfor (auto it = database.begin(); it != database.end();)\n\t\t\tif (match(*it, bits)) {\n\t\t\t\tfor (int i = 0; i < width; i++) {\n\t\t\t\t\tif ((*it)[i] != RTLIL::State::Sa || bits[i] == RTLIL::State::Sa)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbits_t new_pattern;\n\t\t\t\t\tnew_pattern.bitdata = it->bitdata;\n\t\t\t\t\tnew_pattern[i] = bits[i] == RTLIL::State::S1 ? RTLIL::State::S0 : RTLIL::State::S1;\n\t\t\t\t\tdatabase.insert(new_pattern);\n\t\t\t\t}\n\t\t\t\tit = database.erase(it);\n\t\t\t\tstatus = true;\n\t\t\t\tcontinue;\n\t\t\t} else\n\t\t\t\t++it;\n\t\treturn status;\n\t}\n\n\tbool take_all()\n\t{\n\t\tif (database.empty())\n\t\t\treturn false;\n\t\tdatabase.clear();\n\t\treturn true;\n\t}\n\n\tbool empty()\n\t{\n\t\treturn database.empty();\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
159
160
  "cellaigs.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLAIGS_H\n#define CELLAIGS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AigNode\n{\n\tIdString portname;\n\tint portbit;\n\tbool inverter;\n\tint left_parent, right_parent;\n\tvector<pair<IdString, int>> outports;\n\n\tAigNode();\n\tbool operator==(const AigNode &other) const;\n\tunsigned int hash() const;\n};\n\nstruct Aig\n{\n\tstring name;\n\tvector<AigNode> nodes;\n\tAig(Cell *cell);\n\n\tbool operator==(const Aig &other) const;\n\tunsigned int hash() const;\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
160
161
  "celledges.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLEDGES_H\n#define CELLEDGES_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct AbstractCellEdgesDatabase\n{\n\tvirtual ~AbstractCellEdgesDatabase() { }\n\tvirtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;\n\tbool add_edges_from_cell(RTLIL::Cell *cell);\n};\n\nstruct FwdCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tFwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[from_sigbit].insert(to_sigbit);\n\t}\n};\n\nstruct RevCellEdgesDatabase : AbstractCellEdgesDatabase\n{\n\tSigMap &sigmap;\n\tdict<SigBit, pool<SigBit>> db;\n\tRevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }\n\n\tvoid add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {\n\t\tSigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);\n\t\tSigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);\n\t\tdb[to_sigbit].insert(from_sigbit);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
161
162
  "celltypes.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CELLTYPES_H\n#define CELLTYPES_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellType\n{\n\tRTLIL::IdString type;\n\tpool<RTLIL::IdString> inputs, outputs;\n\tbool is_evaluable;\n};\n\nstruct CellTypes\n{\n\tdict<RTLIL::IdString, CellType> cell_types;\n\n\tCellTypes()\n\t{\n\t}\n\n\tCellTypes(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design = NULL)\n\t{\n\t\tif (design)\n\t\t\tsetup_design(design);\n\n\t\tsetup_internals();\n\t\tsetup_internals_mem();\n\t\tsetup_internals_anyinit();\n\t\tsetup_stdcells();\n\t\tsetup_stdcells_mem();\n\t}\n\n\tvoid setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)\n\t{\n\t\tCellType ct = {type, inputs, outputs, is_evaluable};\n\t\tcell_types[ct.type] = ct;\n\t}\n\n\tvoid setup_module(RTLIL::Module *module)\n\t{\n\t\tpool<RTLIL::IdString> inputs, outputs;\n\t\tfor (RTLIL::IdString wire_name : module->ports) {\n\t\t\tRTLIL::Wire *wire = module->wire(wire_name);\n\t\t\tif (wire->port_input)\n\t\t\t\tinputs.insert(wire->name);\n\t\t\tif (wire->port_output)\n\t\t\t\toutputs.insert(wire->name);\n\t\t}\n\t\tsetup_type(module->name, inputs, outputs);\n\t}\n\n\tvoid setup_design(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules())\n\t\t\tsetup_module(module);\n\t}\n\n\tvoid setup_internals()\n\t{\n\t\tsetup_internals_eval();\n\n\t\tsetup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);\n\n\t\tsetup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);\n\t\tsetup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);\n\t\tsetup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});\n\t\tsetup_type(ID($get_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($original_tag), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($future_ff), {ID::A}, {ID::Y});\n\t\tsetup_type(ID($scopeinfo), {}, {});\n\t}\n\n\tvoid setup_internals_eval()\n\t{\n\t\tstd::vector<RTLIL::IdString> unary_ops = {\n\t\t\tID($not), ID($pos), ID($neg),\n\t\t\tID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),\n\t\t\tID($logic_not), ID($slice), ID($lut), ID($sop)\n\t\t};\n\n\t\tstd::vector<RTLIL::IdString> binary_ops = {\n\t\t\tID($and), ID($or), ID($xor), ID($xnor),\n\t\t\tID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),\n\t\t\tID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),\n\t\t\tID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),\n\t\t\tID($logic_and), ID($logic_or), ID($concat), ID($macc),\n\t\t\tID($bweqx)\n\t\t};\n\n\t\tfor (auto type : unary_ops)\n\t\t\tsetup_type(type, {ID::A}, {ID::Y}, true);\n\n\t\tfor (auto type : binary_ops)\n\t\t\tsetup_type(type, {ID::A, ID::B}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))\n\t\t\tsetup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\n\t\tfor (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))\n\t\t\tsetup_type(type, {ID::A, ID::S}, {ID::Y}, true);\n\n\t\tsetup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);\n\t\tsetup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);\n\t\tsetup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);\n\t}\n\n\tvoid setup_internals_ff()\n\t{\n\t\tsetup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});\n\t\tsetup_type(ID($ff), {ID::D}, {ID::Q});\n\t\tsetup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t\tsetup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});\n\t\tsetup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});\n\t\tsetup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});\n\t\tsetup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});\n\t\tsetup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});\n\t\tsetup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_anyinit()\n\t{\n\t\tsetup_type(ID($anyinit), {ID::D}, {ID::Q});\n\t}\n\n\tvoid setup_internals_mem()\n\t{\n\t\tsetup_internals_ff();\n\n\t\tsetup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});\n\t\tsetup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());\n\t\tsetup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\t\tsetup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});\n\n\t\tsetup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});\n\t}\n\n\tvoid setup_stdcells()\n\t{\n\t\tsetup_stdcells_eval();\n\n\t\tsetup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_eval()\n\t{\n\t\tsetup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);\n\t\tsetup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);\n\t\tsetup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);\n\t\tsetup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t\tsetup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);\n\t}\n\n\tvoid setup_stdcells_mem()\n\t{\n\t\tstd::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_SR_%c%c_\", c1, c2), {ID::S, ID::R}, {ID::Q});\n\n\t\tsetup_type(ID($_FF_), {ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFF_%c_\", c1), {ID::C, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c_\", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFF_%c%c_\", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_ALDFFE_%c%c%c_\", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSR_%c%c%c_\", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_DFFSRE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_SDFF_%c%c%c_\", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\tfor (auto c4 : list_np)\n\t\t\tsetup_type(stringf(\"$_SDFFCE_%c%c%c%c_\", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c_\", c1), {ID::E, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_01)\n\t\t\tsetup_type(stringf(\"$_DLATCH_%c%c%c_\", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});\n\n\t\tfor (auto c1 : list_np)\n\t\tfor (auto c2 : list_np)\n\t\tfor (auto c3 : list_np)\n\t\t\tsetup_type(stringf(\"$_DLATCHSR_%c%c%c_\", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});\n\t}\n\n\tvoid clear()\n\t{\n\t\tcell_types.clear();\n\t}\n\n\tbool cell_known(RTLIL::IdString type) const\n\t{\n\t\treturn cell_types.count(type) != 0;\n\t}\n\n\tbool cell_output(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.outputs.count(port) != 0;\n\t}\n\n\tbool cell_input(RTLIL::IdString type, RTLIL::IdString port) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.inputs.count(port) != 0;\n\t}\n\n\tbool cell_evaluable(RTLIL::IdString type) const\n\t{\n\t\tauto it = cell_types.find(type);\n\t\treturn it != cell_types.end() && it->second.is_evaluable;\n\t}\n\n\tstatic RTLIL::Const eval_not(RTLIL::Const v)\n\t{\n\t\tfor (auto &bit : v.bits)\n\t\t\tif (bit == State::S0) bit = State::S1;\n\t\t\telse if (bit == State::S1) bit = State::S0;\n\t\treturn v;\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)\n\t{\n\t\tif (type == ID($sshr) && !signed1)\n\t\t\ttype = ID($shr);\n\t\tif (type == ID($sshl) && !signed1)\n\t\t\ttype = ID($shl);\n\n\t\tif (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&\n\t\t\t\ttype != ID($pos) && type != ID($neg) && type != ID($not)) {\n\t\t\tif (!signed1 || !signed2)\n\t\t\t\tsigned1 = false, signed2 = false;\n\t\t}\n\n#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);\n\t\tHANDLE_CELL_TYPE(not)\n\t\tHANDLE_CELL_TYPE(and)\n\t\tHANDLE_CELL_TYPE(or)\n\t\tHANDLE_CELL_TYPE(xor)\n\t\tHANDLE_CELL_TYPE(xnor)\n\t\tHANDLE_CELL_TYPE(reduce_and)\n\t\tHANDLE_CELL_TYPE(reduce_or)\n\t\tHANDLE_CELL_TYPE(reduce_xor)\n\t\tHANDLE_CELL_TYPE(reduce_xnor)\n\t\tHANDLE_CELL_TYPE(reduce_bool)\n\t\tHANDLE_CELL_TYPE(logic_not)\n\t\tHANDLE_CELL_TYPE(logic_and)\n\t\tHANDLE_CELL_TYPE(logic_or)\n\t\tHANDLE_CELL_TYPE(shl)\n\t\tHANDLE_CELL_TYPE(shr)\n\t\tHANDLE_CELL_TYPE(sshl)\n\t\tHANDLE_CELL_TYPE(sshr)\n\t\tHANDLE_CELL_TYPE(shift)\n\t\tHANDLE_CELL_TYPE(shiftx)\n\t\tHANDLE_CELL_TYPE(lt)\n\t\tHANDLE_CELL_TYPE(le)\n\t\tHANDLE_CELL_TYPE(eq)\n\t\tHANDLE_CELL_TYPE(ne)\n\t\tHANDLE_CELL_TYPE(eqx)\n\t\tHANDLE_CELL_TYPE(nex)\n\t\tHANDLE_CELL_TYPE(ge)\n\t\tHANDLE_CELL_TYPE(gt)\n\t\tHANDLE_CELL_TYPE(add)\n\t\tHANDLE_CELL_TYPE(sub)\n\t\tHANDLE_CELL_TYPE(mul)\n\t\tHANDLE_CELL_TYPE(div)\n\t\tHANDLE_CELL_TYPE(mod)\n\t\tHANDLE_CELL_TYPE(divfloor)\n\t\tHANDLE_CELL_TYPE(modfloor)\n\t\tHANDLE_CELL_TYPE(pow)\n\t\tHANDLE_CELL_TYPE(pos)\n\t\tHANDLE_CELL_TYPE(neg)\n#undef HANDLE_CELL_TYPE\n\n\t\tif (type == ID($_BUF_))\n\t\t\treturn arg1;\n\t\tif (type == ID($_NOT_))\n\t\t\treturn eval_not(arg1);\n\t\tif (type == ID($_AND_))\n\t\t\treturn const_and(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NAND_))\n\t\t\treturn eval_not(const_and(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_OR_))\n\t\t\treturn const_or(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_NOR_))\n\t\t\treturn eval_not(const_or(arg1, arg2, false, false, 1));\n\t\tif (type == ID($_XOR_))\n\t\t\treturn const_xor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_XNOR_))\n\t\t\treturn const_xnor(arg1, arg2, false, false, 1);\n\t\tif (type == ID($_ANDNOT_))\n\t\t\treturn const_and(arg1, eval_not(arg2), false, false, 1);\n\t\tif (type == ID($_ORNOT_))\n\t\t\treturn const_or(arg1, eval_not(arg2), false, false, 1);\n\n\t\tif (errp != nullptr) {\n\t\t\t*errp = true;\n\t\t\treturn State::Sm;\n\t\t}\n\n\t\tlog_abort();\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($slice)) {\n\t\t\tRTLIL::Const ret;\n\t\t\tint width = cell->parameters.at(ID::Y_WIDTH).as_int();\n\t\t\tint offset = cell->parameters.at(ID::OFFSET).as_int();\n\t\t\tret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($concat)) {\n\t\t\tRTLIL::Const ret = arg1;\n\t\t\tret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (cell->type == ID($bmux))\n\t\t{\n\t\t\treturn const_bmux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($demux))\n\t\t{\n\t\t\treturn const_demux(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($bweqx))\n\t\t{\n\t\t\treturn const_bweqx(arg1, arg2);\n\t\t}\n\n\t\tif (cell->type == ID($lut))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;\n\t\t\twhile (GetSize(t) < (1 << width))\n\t\t\t\tt.push_back(State::S0);\n\t\t\tt.resize(1 << width);\n\n\t\t\treturn const_bmux(t, arg1);\n\t\t}\n\n\t\tif (cell->type == ID($sop))\n\t\t{\n\t\t\tint width = cell->parameters.at(ID::WIDTH).as_int();\n\t\t\tint depth = cell->parameters.at(ID::DEPTH).as_int();\n\t\t\tstd::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;\n\n\t\t\twhile (GetSize(t) < width*depth*2)\n\t\t\t\tt.push_back(State::S0);\n\n\t\t\tRTLIL::State default_ret = State::S0;\n\n\t\t\tfor (int i = 0; i < depth; i++)\n\t\t\t{\n\t\t\t\tbool match = true;\n\t\t\t\tbool match_x = true;\n\n\t\t\t\tfor (int j = 0; j < width; j++) {\n\t\t\t\t\tRTLIL::State a = arg1.bits.at(j);\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 0) == State::S1) {\n\t\t\t\t\t\tif (a == State::S1) match_x = false;\n\t\t\t\t\t\tif (a != State::S0) match = false;\n\t\t\t\t\t}\n\t\t\t\t\tif (t.at(2*width*i + 2*j + 1) == State::S1) {\n\t\t\t\t\t\tif (a == State::S0) match_x = false;\n\t\t\t\t\t\tif (a != State::S1) match = false;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif (match)\n\t\t\t\t\treturn State::S1;\n\n\t\t\t\tif (match_x)\n\t\t\t\t\tdefault_ret = State::Sx;\n\t\t\t}\n\n\t\t\treturn default_ret;\n\t\t}\n\n\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\t\tint result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;\n\t\treturn eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)\n\t{\n\t\tif (cell->type.in(ID($mux), ID($_MUX_)))\n\t\t\treturn const_mux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($bwmux))\n\t\t\treturn const_bwmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($pmux))\n\t\t\treturn const_pmux(arg1, arg2, arg3);\n\t\tif (cell->type == ID($_AOI3_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\t\tif (cell->type == ID($_OAI3_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));\n\n\t\tlog_assert(arg3.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, errp);\n\t}\n\n\tstatic RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)\n\t{\n\t\tif (cell->type == ID($_AOI4_))\n\t\t\treturn eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));\n\t\tif (cell->type == ID($_OAI4_))\n\t\t\treturn eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));\n\n\t\tlog_assert(arg4.bits.size() == 0);\n\t\treturn eval(cell, arg1, arg2, arg3, errp);\n\t}\n};\n\n// initialized by yosys_setup()\nextern CellTypes yosys_celltypes;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
162
163
  "consteval.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CONSTEVAL_H\n#define CONSTEVAL_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ConstEval\n{\n\tRTLIL::Module *module;\n\tSigMap assign_map;\n\tSigMap values_map;\n\tSigPool stop_signals;\n\tSigSet<RTLIL::Cell*> sig2driver;\n\tstd::set<RTLIL::Cell*> busy;\n\tstd::vector<SigMap> stack;\n\tRTLIL::State defaultval;\n\n\tConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)\n\t{\n\t\tCellTypes ct;\n\t\tct.setup_internals();\n\t\tct.setup_stdcells();\n\n\t\tfor (auto &it : module->cells_) {\n\t\t\tif (!ct.cell_known(it.second->type))\n\t\t\t\tcontinue;\n\t\t\tfor (auto &it2 : it.second->connections())\n\t\t\t\tif (ct.cell_output(it.second->type, it2.first))\n\t\t\t\t\tsig2driver.insert(assign_map(it2.second), it.second);\n\t\t}\n\t}\n\n\tvoid clear()\n\t{\n\t\tvalues_map.clear();\n\t\tstop_signals.clear();\n\t}\n\n\tvoid push()\n\t{\n\t\tstack.push_back(values_map);\n\t}\n\n\tvoid pop()\n\t{\n\t\tvalues_map.swap(stack.back());\n\t\tstack.pop_back();\n\t}\n\n\tvoid set(RTLIL::SigSpec sig, RTLIL::Const value)\n\t{\n\t\tassign_map.apply(sig);\n#ifndef NDEBUG\n\t\tRTLIL::SigSpec current_val = values_map(sig);\n\t\tfor (int i = 0; i < GetSize(current_val); i++)\n\t\t\tlog_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);\n#endif\n\t\tvalues_map.add(sig, RTLIL::SigSpec(value));\n\t}\n\n\tvoid stop(RTLIL::SigSpec sig)\n\t{\n\t\tassign_map.apply(sig);\n\t\tstop_signals.add(sig);\n\t}\n\n\tbool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)\n\t{\n\t\tif (cell->type == ID($lcu))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_p = cell->getPort(ID::P);\n\t\t\tRTLIL::SigSpec sig_g = cell->getPort(ID::G);\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));\n\n\t\t\tif (sig_co.is_fully_const())\n\t\t\t\treturn true;\n\n\t\t\tif (!eval(sig_p, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_g, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())\n\t\t\t{\n\t\t\t\tRTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));\n\t\t\t\tbool carry = sig_ci.as_bool();\n\n\t\t\t\tfor (int i = 0; i < GetSize(coval); i++) {\n\t\t\t\t\tcarry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);\n\t\t\t\t\tcoval.bits[i] = carry ? State::S1 : State::S0;\n\t\t\t\t}\n\n\t\t\t\tset(sig_co, coval);\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));\n\n\t\t\treturn true;\n\t\t}\n\n\t\tRTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;\n\n\t\tlog_assert(cell->hasPort(ID::Y));\n\t\tsig_y = values_map(assign_map(cell->getPort(ID::Y)));\n\t\tif (sig_y.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (cell->hasPort(ID::S)) {\n\t\t\tsig_s = cell->getPort(ID::S);\n\t\t}\n\n\t\tif (cell->hasPort(ID::A))\n\t\t\tsig_a = cell->getPort(ID::A);\n\n\t\tif (cell->hasPort(ID::B))\n\t\t\tsig_b = cell->getPort(ID::B);\n\n\t\tif (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))\n\t\t{\n\t\t\tstd::vector<RTLIL::SigSpec> y_candidates;\n\t\t\tint count_set_s_bits = 0;\n\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (int i = 0; i < sig_s.size(); i++)\n\t\t\t{\n\t\t\t\tRTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);\n\t\t\t\tRTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());\n\n\t\t\t\tif (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)\n\t\t\t\t\ty_candidates.push_back(b_slice);\n\n\t\t\t\tif (s_bit == RTLIL::State::S1)\n\t\t\t\t\tcount_set_s_bits++;\n\t\t\t}\n\n\t\t\tif (count_set_s_bits == 0)\n\t\t\t\ty_candidates.push_back(sig_a);\n\n\t\t\tstd::vector<RTLIL::Const> y_values;\n\n\t\t\tlog_assert(y_candidates.size() > 0);\n\t\t\tfor (auto &yc : y_candidates) {\n\t\t\t\tif (!eval(yc, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (cell->type == ID($_NMUX_))\n\t\t\t\t\ty_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc)));\n\t\t\t\telse\n\t\t\t\t\ty_values.push_back(yc.as_const());\n\t\t\t}\n\n\t\t\tif (y_values.size() > 1)\n\t\t\t{\n\t\t\t\tstd::vector<RTLIL::State> master_bits = y_values.at(0).bits;\n\n\t\t\t\tfor (size_t i = 1; i < y_values.size(); i++) {\n\t\t\t\t\tstd::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;\n\t\t\t\t\tlog_assert(master_bits.size() == slave_bits.size());\n\t\t\t\t\tfor (size_t j = 0; j < master_bits.size(); j++)\n\t\t\t\t\t\tif (master_bits[j] != slave_bits[j])\n\t\t\t\t\t\t\tmaster_bits[j] = RTLIL::State::Sx;\n\t\t\t\t}\n\n\t\t\t\tset(sig_y, RTLIL::Const(master_bits));\n\t\t\t}\n\t\t\telse\n\t\t\t\tset(sig_y, y_values.front());\n\t\t}\n\t\telse if (cell->type == ID($bmux))\n\t\t{\n\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (sig_s.is_fully_def()) {\n\t\t\t\tint sel = sig_s.as_int();\n\t\t\t\tint width = GetSize(sig_y);\n\t\t\t\tSigSpec res = sig_a.extract(sel * width, width);\n\t\t\t\tif (!eval(res, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, res.as_const());\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($demux))\n\t\t{\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_a.is_fully_zero()) {\n\t\t\t\tset(sig_y, Const(0, GetSize(sig_y)));\n\t\t\t} else {\n\t\t\t\tif (!eval(sig_s, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tset(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($fa))\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c = cell->getPort(ID::C);\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tint width = GetSize(sig_c);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);\n\n\t\t\tRTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);\n\t\t\tRTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);\n\t\t\tRTLIL::Const val_x = const_or(t2, t3, false, false, width);\n\n\t\t\tfor (int i = 0; i < GetSize(val_y); i++)\n\t\t\t\tif (val_y.bits[i] == RTLIL::Sx)\n\t\t\t\t\tval_x.bits[i] = RTLIL::Sx;\n\n\t\t\tset(sig_y, val_y);\n\t\t\tset(sig_x, val_x);\n\t\t}\n\t\telse if (cell->type == ID($alu))\n\t\t{\n\t\t\tbool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();\n\t\t\tbool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();\n\n\t\t\tRTLIL::SigSpec sig_ci = cell->getPort(ID::CI);\n\t\t\tRTLIL::SigSpec sig_bi = cell->getPort(ID::BI);\n\n\t\t\tif (!eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_ci, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tif (!eval(sig_bi, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::SigSpec sig_x = cell->getPort(ID::X);\n\t\t\tRTLIL::SigSpec sig_co = cell->getPort(ID::CO);\n\n\t\t\tbool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());\n\t\t\tsig_a.extend_u0(GetSize(sig_y), signed_a);\n\t\t\tsig_b.extend_u0(GetSize(sig_y), signed_b);\n\n\t\t\tbool carry = sig_ci[0] == State::S1;\n\t\t\tbool b_inv = sig_bi[0] == State::S1;\n\n\t\t\tfor (int i = 0; i < GetSize(sig_y); i++)\n\t\t\t{\n\t\t\t\tRTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };\n\n\t\t\t\tif (!x_inputs.is_fully_def()) {\n\t\t\t\t\tset(sig_x[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_x = bit_a != bit_b;\n\t\t\t\t\tset(sig_x[i], bit_x ? State::S1 : State::S0);\n\t\t\t\t}\n\n\t\t\t\tif (any_input_undef) {\n\t\t\t\t\tset(sig_y[i], RTLIL::Sx);\n\t\t\t\t\tset(sig_co[i], RTLIL::Sx);\n\t\t\t\t} else {\n\t\t\t\t\tbool bit_a = sig_a[i] == State::S1;\n\t\t\t\t\tbool bit_b = (sig_b[i] == State::S1) != b_inv;\n\t\t\t\t\tbool bit_y = (bit_a != bit_b) != carry;\n\t\t\t\t\tcarry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);\n\t\t\t\t\tset(sig_y[i], bit_y ? State::S1 : State::S0);\n\t\t\t\t\tset(sig_co[i], carry ? State::S1 : State::S0);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (cell->type == ID($macc))\n\t\t{\n\t\t\tMacc macc;\n\t\t\tmacc.from_cell(cell);\n\n\t\t\tif (!eval(macc.bit_ports, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tfor (auto &port : macc.ports) {\n\t\t\t\tif (!eval(port.in_a, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t\tif (!eval(port.in_b, undef, cell))\n\t\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tRTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));\n\t\t\tif (!macc.eval(result))\n\t\t\t\tlog_abort();\n\n\t\t\tset(cell->getPort(ID::Y), result);\n\t\t}\n\t\telse\n\t\t{\n\t\t\tRTLIL::SigSpec sig_c, sig_d;\n\n\t\t\tif (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {\n\t\t\t\tif (cell->hasPort(ID::C))\n\t\t\t\t\tsig_c = cell->getPort(ID::C);\n\t\t\t\tif (cell->hasPort(ID::D))\n\t\t\t\t\tsig_d = cell->getPort(ID::D);\n\t\t\t}\n\n\t\t\tif (sig_a.size() > 0 && !eval(sig_a, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_b.size() > 0 && !eval(sig_b, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_c.size() > 0 && !eval(sig_c, undef, cell))\n\t\t\t\treturn false;\n\t\t\tif (sig_d.size() > 0 && !eval(sig_d, undef, cell))\n\t\t\t\treturn false;\n\n\t\t\tbool eval_err = false;\n\t\t\tRTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);\n\n\t\t\tif (eval_err)\n\t\t\t\treturn false;\n\n\t\t\tset(sig_y, eval_ret);\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)\n\t{\n\t\tassign_map.apply(sig);\n\t\tvalues_map.apply(sig);\n\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (stop_signals.check_any(sig)) {\n\t\t\tundef = stop_signals.extract(sig);\n\t\t\treturn false;\n\t\t}\n\n\t\tif (busy_cell) {\n\t\t\tif (busy.count(busy_cell) > 0) {\n\t\t\t\tundef = sig;\n\t\t\t\treturn false;\n\t\t\t}\n\t\t\tbusy.insert(busy_cell);\n\t\t}\n\n\t\tstd::set<RTLIL::Cell*> driver_cells;\n\t\tsig2driver.find(sig, driver_cells);\n\t\tfor (auto cell : driver_cells) {\n\t\t\tif (!eval(cell, undef)) {\n\t\t\t\tif (busy_cell)\n\t\t\t\t\tbusy.erase(busy_cell);\n\t\t\t\treturn false;\n\t\t\t}\n\t\t}\n\n\t\tif (busy_cell)\n\t\t\tbusy.erase(busy_cell);\n\n\t\tvalues_map.apply(sig);\n\t\tif (sig.is_fully_const())\n\t\t\treturn true;\n\n\t\tif (defaultval != RTLIL::State::Sm) {\n\t\t\tfor (auto &bit : sig)\n\t\t\t\tif (bit.wire) bit = defaultval;\n\t\t\treturn true;\n\t\t}\n\n\t\tfor (auto &c : sig.chunks())\n\t\t\tif (c.wire != NULL)\n\t\t\t\tundef.append(c);\n\t\treturn false;\n\t}\n\n\tbool eval(RTLIL::SigSpec &sig)\n\t{\n\t\tRTLIL::SigSpec undef;\n\t\treturn eval(sig, undef);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
163
164
  "constids.inc": "X(A)\nX(abc9_box)\nX(abc9_box_id)\nX(abc9_box_seq)\nX(abc9_bypass)\nX(abc9_carry)\nX(abc9_flop)\nX(abc9_keep)\nX(abc9_lut)\nX(abc9_mergeability)\nX(abc9_scc_id)\nX(abcgroup)\nX(ABITS)\nX(AD)\nX(ADDR)\nX(allconst)\nX(allseq)\nX(ALOAD)\nX(ALOAD_POLARITY)\nX(always_comb)\nX(always_ff)\nX(always_latch)\nX(anyconst)\nX(anyseq)\nX(ARGS)\nX(ARGS_WIDTH)\nX(ARST)\nX(ARST_POLARITY)\nX(ARST_VALUE)\nX(A_SIGNED)\nX(A_WIDTH)\nX(B)\nX(BI)\nX(BITS_USED)\nX(blackbox)\nX(B_SIGNED)\nX(bugpoint_keep)\nX(B_WIDTH)\nX(BYTE)\nX(C)\nX(cells_not_processed)\nX(CE_OVER_SRST)\nX(CFG_ABITS)\nX(CFG_DBITS)\nX(CFG_INIT)\nX(CI)\nX(CLK)\nX(clkbuf_driver)\nX(clkbuf_inhibit)\nX(clkbuf_inv)\nX(clkbuf_sink)\nX(CLK_ENABLE)\nX(CLK_POLARITY)\nX(CLR)\nX(CLR_POLARITY)\nX(CO)\nX(COLLISION_X_MASK)\nX(CONFIG)\nX(CONFIG_WIDTH)\nX(CTRL_IN)\nX(CTRL_IN_WIDTH)\nX(CTRL_OUT)\nX(CTRL_OUT_WIDTH)\nX(D)\nX(DAT)\nX(DATA)\nX(DAT_DST_PEN)\nX(DAT_DST_POL)\nX(defaultvalue)\nX(DELAY)\nX(DEPTH)\nX(DST)\nX(DST_EN)\nX(DST_PEN)\nX(DST_POL)\nX(DST_WIDTH)\nX(dynports)\nX(E)\nX(EDGE_EN)\nX(EDGE_POL)\nX(EN)\nX(EN_DST)\nX(EN_POLARITY)\nX(EN_SRC)\nX(enum_base_type)\nX(enum_type)\nX(equiv_merged)\nX(equiv_region)\nX(extract_order)\nX(F)\nX(FLAVOR)\nX(FORMAT)\nX(force_downto)\nX(force_upto)\nX(fsm_encoding)\nX(fsm_export)\nX(FULL)\nX(full_case)\nX(G)\nX(gclk)\nX(gentb_clock)\nX(gentb_constant)\nX(gentb_skip)\nX(H)\nX(hdlname)\nX(hierconn)\nX(I)\nX(INIT)\nX(INIT_VALUE)\nX(init)\nX(initial_top)\nX(interface_modport)\nX(interfaces_replaced_in_module)\nX(interface_type)\nX(invertible_pin)\nX(iopad_external_pin)\nX(is_interface)\nX(J)\nX(K)\nX(keep)\nX(keep_hierarchy)\nX(L)\nX(lib_whitebox)\nX(localparam)\nX(logic_block)\nX(lram)\nX(LUT)\nX(lut_keep)\nX(M)\nX(maximize)\nX(mem2reg)\nX(MEMID)\nX(minimize)\nX(module_not_derived)\nX(N)\nX(NAME)\nX(noblackbox)\nX(nolatches)\nX(nomem2init)\nX(nomem2reg)\nX(nomeminit)\nX(nosync)\nX(nowrshmsk)\nX(no_ram)\nX(no_rw_check)\nX(O)\nX(OFFSET)\nX(onehot)\nX(P)\nX(parallel_case)\nX(parameter)\nX(PORTID)\nX(PRIORITY)\nX(PRIORITY_MASK)\nX(Q)\nX(qwp_position)\nX(R)\nX(ram_block)\nX(ram_style)\nX(ramstyle)\nX(RD_ADDR)\nX(RD_ARST)\nX(RD_ARST_VALUE)\nX(RD_CE_OVER_SRST)\nX(RD_CLK)\nX(RD_CLK_ENABLE)\nX(RD_CLK_POLARITY)\nX(RD_COLLISION_X_MASK)\nX(RD_DATA)\nX(RD_EN)\nX(RD_INIT_VALUE)\nX(RD_PORTS)\nX(RD_SRST)\nX(RD_SRST_VALUE)\nX(RD_TRANSPARENCY_MASK)\nX(RD_TRANSPARENT)\nX(RD_WIDE_CONTINUATION)\nX(reg)\nX(replaced_by_gclk)\nX(reprocess_after)\nX(rom_block)\nX(rom_style)\nX(romstyle)\nX(S)\nX(SET)\nX(SET_POLARITY)\nX(SIZE)\nX(SRC)\nX(src)\nX(SRC_DST_PEN)\nX(SRC_DST_POL)\nX(SRC_EN)\nX(SRC_PEN)\nX(SRC_POL)\nX(SRC_WIDTH)\nX(SRST)\nX(SRST_POLARITY)\nX(SRST_VALUE)\nX(sta_arrival)\nX(STATE_BITS)\nX(STATE_NUM)\nX(STATE_NUM_LOG2)\nX(STATE_RST)\nX(STATE_TABLE)\nX(smtlib2_module)\nX(smtlib2_comb_expr)\nX(submod)\nX(syn_ramstyle)\nX(syn_romstyle)\nX(S_WIDTH)\nX(T)\nX(TABLE)\nX(TAG)\nX(techmap_autopurge)\nX(_TECHMAP_BITS_CONNMAP_)\nX(_TECHMAP_CELLNAME_)\nX(_TECHMAP_CELLTYPE_)\nX(techmap_celltype)\nX(_TECHMAP_FAIL_)\nX(techmap_maccmap)\nX(_TECHMAP_REPLACE_)\nX(techmap_simplemap)\nX(_techmap_special_)\nX(techmap_wrap)\nX(_TECHMAP_PLACEHOLDER_)\nX(techmap_chtype)\nX(T_FALL_MAX)\nX(T_FALL_MIN)\nX(T_FALL_TYP)\nX(T_LIMIT)\nX(T_LIMIT2)\nX(T_LIMIT2_MAX)\nX(T_LIMIT2_MIN)\nX(T_LIMIT2_TYP)\nX(T_LIMIT_MAX)\nX(T_LIMIT_MIN)\nX(T_LIMIT_TYP)\nX(to_delete)\nX(top)\nX(TRANS_NUM)\nX(TRANSPARENCY_MASK)\nX(TRANSPARENT)\nX(TRANS_TABLE)\nX(TRG)\nX(TRG_ENABLE)\nX(TRG_POLARITY)\nX(TRG_WIDTH)\nX(T_RISE_MAX)\nX(T_RISE_MIN)\nX(T_RISE_TYP)\nX(TYPE)\nX(U)\nX(unique)\nX(unused_bits)\nX(V)\nX(via_celltype)\nX(wand)\nX(whitebox)\nX(WIDTH)\nX(wildcard_port_conns)\nX(wiretype)\nX(wor)\nX(WORDS)\nX(WR_ADDR)\nX(WR_CLK)\nX(WR_CLK_ENABLE)\nX(WR_CLK_POLARITY)\nX(WR_DATA)\nX(WR_EN)\nX(WR_PORTS)\nX(WR_PRIORITY_MASK)\nX(WR_WIDE_CONTINUATION)\nX(X)\nX(xprop_decoder)\nX(Y)\nX(Y_WIDTH)\n",
164
- "cost.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef COST_H\n#define COST_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellCosts\n{\n\tstatic const dict<RTLIL::IdString, int>& default_gate_cost() {\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 4 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 4 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 4 },\n\t\t\t{ ID($_ORNOT_), 4 },\n\t\t\t{ ID($_XOR_), 5 },\n\t\t\t{ ID($_XNOR_), 5 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 7 },\n\t\t\t{ ID($_OAI4_), 7 },\n\t\t\t{ ID($_MUX_), 4 },\n\t\t\t{ ID($_NMUX_), 4 }\n\t\t};\n\t\treturn db;\n\t}\n\n\tstatic const dict<RTLIL::IdString, int>& cmos_gate_cost() {\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 6 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 6 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 6 },\n\t\t\t{ ID($_ORNOT_), 6 },\n\t\t\t{ ID($_XOR_), 12 },\n\t\t\t{ ID($_XNOR_), 12 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 8 },\n\t\t\t{ ID($_OAI4_), 8 },\n\t\t\t{ ID($_MUX_), 12 },\n\t\t\t{ ID($_NMUX_), 10 }\n\t\t};\n\t\treturn db;\n\t}\n\n\tdict<RTLIL::IdString, int> mod_cost_cache;\n\tconst dict<RTLIL::IdString, int> *gate_cost = nullptr;\n\tDesign *design = nullptr;\n\n\tint get(RTLIL::IdString type) const\n\t{\n\t\tif (gate_cost && gate_cost->count(type))\n\t\t\treturn gate_cost->at(type);\n\n\t\tlog_warning(\"Can't determine cost of %s cell.\\n\", log_id(type));\n\t\treturn 1;\n\t}\n\n\tint get(RTLIL::Cell *cell)\n\t{\n\t\tif (gate_cost && gate_cost->count(cell->type))\n\t\t\treturn gate_cost->at(cell->type);\n\n\t\tif (design && design->module(cell->type) && cell->parameters.empty())\n\t\t{\n\t\t\tRTLIL::Module *mod = design->module(cell->type);\n\n\t\t\tif (mod->attributes.count(ID(cost)))\n\t\t\t\treturn mod->attributes.at(ID(cost)).as_int();\n\n\t\t\tif (mod_cost_cache.count(mod->name))\n\t\t\t\treturn mod_cost_cache.at(mod->name);\n\n\t\t\tint module_cost = 1;\n\t\t\tfor (auto c : mod->cells())\n\t\t\t\tmodule_cost += get(c);\n\n\t\t\tmod_cost_cache[mod->name] = module_cost;\n\t\t\treturn module_cost;\n\t\t}\n\n\t\tlog_warning(\"Can't determine cost of %s cell (%d parameters).\\n\", log_id(cell->type), GetSize(cell->parameters));\n\t\treturn 1;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
165
+ "cost.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef COST_H\n#define COST_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct CellCosts\n{\n\n\tprivate:\n\tdict<RTLIL::IdString, int> mod_cost_cache_;\n\tDesign *design_ = nullptr;\n\n\tpublic:\n\tCellCosts(RTLIL::Design *design) : design_(design) { }\n\n\tstatic const dict<RTLIL::IdString, int>& default_gate_cost() {\n\t\t// Default size heuristics for several common PDK standard cells\n\t\t// used by abc and stat\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 4 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 4 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 4 },\n\t\t\t{ ID($_ORNOT_), 4 },\n\t\t\t{ ID($_XOR_), 5 },\n\t\t\t{ ID($_XNOR_), 5 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 7 },\n\t\t\t{ ID($_OAI4_), 7 },\n\t\t\t{ ID($_MUX_), 4 },\n\t\t\t{ ID($_NMUX_), 4 },\n\t\t};\n\t\treturn db;\n\t}\n\n\tstatic const dict<RTLIL::IdString, int>& cmos_gate_cost() {\n\t\t// Estimated CMOS transistor counts for several common PDK standard cells\n\t\t// used by stat and optionally by abc\n\t\tstatic const dict<RTLIL::IdString, int> db = {\n\t\t\t{ ID($_BUF_), 1 },\n\t\t\t{ ID($_NOT_), 2 },\n\t\t\t{ ID($_AND_), 6 },\n\t\t\t{ ID($_NAND_), 4 },\n\t\t\t{ ID($_OR_), 6 },\n\t\t\t{ ID($_NOR_), 4 },\n\t\t\t{ ID($_ANDNOT_), 6 },\n\t\t\t{ ID($_ORNOT_), 6 },\n\t\t\t{ ID($_XOR_), 12 },\n\t\t\t{ ID($_XNOR_), 12 },\n\t\t\t{ ID($_AOI3_), 6 },\n\t\t\t{ ID($_OAI3_), 6 },\n\t\t\t{ ID($_AOI4_), 8 },\n\t\t\t{ ID($_OAI4_), 8 },\n\t\t\t{ ID($_MUX_), 12 },\n\t\t\t{ ID($_NMUX_), 10 },\n\t\t\t{ ID($_DFF_P_), 16 },\n\t\t\t{ ID($_DFF_N_), 16 },\n\t\t};\n\t\treturn db;\n\t}\n\n\t// Get the cell cost for a cell based on its parameters.\n\t// This cost is an *approximate* upper bound for the number of gates that\n\t// the cell will get mapped to with \"opt -fast; techmap\"\n\t// The intended usage is for flattening heuristics and similar situations\n\tunsigned int get(RTLIL::Cell *cell);\n\t// Sum up the cell costs of all cells in the module\n\t// and all its submodules recursively\n\tunsigned int get(RTLIL::Module *mod);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
165
166
  "ff.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FF_H\n#define FF_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Describes a flip-flop or a latch.\n//\n// If has_gclk, this is a formal verification FF with implicit global clock:\n// Q is simply previous cycle's D. Additionally if is_anyinit is true, this is\n// an $anyinit cell which always has an undefined initialization value. Note\n// that $anyinit is not considered to be among the FF celltypes, so a pass has\n// to explicitly opt-in to process $anyinit cells with FfData.\n//\n// Otherwise, the FF/latch can have any number of features selected by has_*\n// attributes that determine Q's value (in order of decreasing priority):\n//\n// - on start, register is initialized to val_init\n// - if has_sr is present:\n// - sig_clr is per-bit async clear, and sets the corresponding bit to 0\n// if active\n// - sig_set is per-bit async set, and sets the corresponding bit to 1\n// if active\n// - if has_arst is present:\n// - sig_arst is whole-reg async reset, and sets the whole register to val_arst\n// - if has_aload is present:\n// - sig_aload is whole-reg async load (aka latch gate enable), and sets the whole\n// register to sig_ad\n// - if has_clk is present, and we're currently on a clock edge:\n// - if has_ce is present and ce_over_srst is true:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - if has_srst is present:\n// - sig_srst is whole-reg sync reset and sets the register to val_srst\n// - if has_ce is present and ce_over_srst is false:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - set whole reg to sig_d\n// - if nothing of the above applies, the reg value remains unchanged\n//\n// Since the yosys FF cell library isn't fully generic, not all combinations\n// of the features above can be supported:\n//\n// - only one of has_srst, has_arst, has_sr can be used\n// - if has_clk is used together with has_aload, then has_srst, has_arst,\n// has_sr cannot be used\n//\n// The valid feature combinations are thus:\n//\n// - has_clk + optional has_ce [dff/dffe]\n// - has_clk + optional has_ce + has_arst [adff/adffe]\n// - has_clk + optional has_ce + has_aload [aldff/aldffe]\n// - has_clk + optional has_ce + has_sr [dffsr/dffsre]\n// - has_clk + optional has_ce + has_srst [sdff/sdffe/sdffce]\n// - has_aload [dlatch]\n// - has_aload + has_arst [adlatch]\n// - has_aload + has_sr [dlatchsr]\n// - has_sr [sr]\n// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]\n// - empty set [not a cell — will be emitted as a simple direct connection]\n\nstruct FfData {\n\tModule *module;\n\tFfInitVals *initvals;\n\tCell *cell;\n\tIdString name;\n\t// The FF output.\n\tSigSpec sig_q;\n\t// The sync data input, present if has_clk or has_gclk.\n\tSigSpec sig_d;\n\t// The async data input, present if has_aload.\n\tSigSpec sig_ad;\n\t// The sync clock, present if has_clk.\n\tSigSpec sig_clk;\n\t// The clock enable, present if has_ce.\n\tSigSpec sig_ce;\n\t// The async load enable, present if has_aload.\n\tSigSpec sig_aload;\n\t// The async reset, preset if has_arst.\n\tSigSpec sig_arst;\n\t// The sync reset, preset if has_srst.\n\tSigSpec sig_srst;\n\t// The async clear (per-lane), present if has_sr.\n\tSigSpec sig_clr;\n\t// The async set (per-lane), present if has_sr.\n\tSigSpec sig_set;\n\t// True if this is a clocked (edge-sensitive) flip-flop.\n\tbool has_clk;\n\t// True if this is a $ff, exclusive with every other has_*.\n\tbool has_gclk;\n\t// True if this FF has a clock enable. Depends on has_clk.\n\tbool has_ce;\n\t// True if this FF has async load function — this includes D latches.\n\t// If this and has_clk are both set, has_arst and has_sr cannot be set.\n\tbool has_aload;\n\t// True if this FF has sync set/reset. Depends on has_clk, exclusive\n\t// with has_arst, has_sr, has_aload.\n\tbool has_srst;\n\t// True if this FF has async set/reset. Exclusive with has_srst,\n\t// has_sr. If this and has_clk are both set, has_aload cannot be set.\n\tbool has_arst;\n\t// True if this FF has per-bit async set + clear. Exclusive with\n\t// has_srst, has_arst. If this and has_clk are both set, has_aload\n\t// cannot be set.\n\tbool has_sr;\n\t// If has_ce and has_srst are both set, determines their relative\n\t// priorities: if true, inactive ce disables srst; if false, srst\n\t// operates independent of ce.\n\tbool ce_over_srst;\n\t// True if this FF is a fine cell, false if it is a coarse cell.\n\t// If true, width must be 1.\n\tbool is_fine;\n\t// True if this FF is an $anyinit cell. Depends on has_gclk.\n\tbool is_anyinit;\n\t// Polarities, corresponding to sig_*. True means active-high, false\n\t// means active-low.\n\tbool pol_clk;\n\tbool pol_ce;\n\tbool pol_aload;\n\tbool pol_arst;\n\tbool pol_srst;\n\tbool pol_clr;\n\tbool pol_set;\n\t// The value loaded by sig_arst.\n\tConst val_arst;\n\t// The value loaded by sig_srst.\n\tConst val_srst;\n\t// The initial value at power-up.\n\tConst val_init;\n\t// The FF data width in bits.\n\tint width;\n\tdict<IdString, Const> attributes;\n\n\tFfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {\n\t\twidth = 0;\n\t\thas_clk = false;\n\t\thas_gclk = false;\n\t\thas_ce = false;\n\t\thas_aload = false;\n\t\thas_srst = false;\n\t\thas_arst = false;\n\t\thas_sr = false;\n\t\tce_over_srst = false;\n\t\tis_fine = false;\n\t\tis_anyinit = false;\n\t\tpol_clk = false;\n\t\tpol_aload = false;\n\t\tpol_ce = false;\n\t\tpol_arst = false;\n\t\tpol_srst = false;\n\t\tpol_clr = false;\n\t\tpol_set = false;\n\t}\n\n\tFfData(FfInitVals *initvals, Cell *cell_);\n\n\t// Returns a FF identical to this one, but only keeping bit indices from the argument.\n\tFfData slice(const std::vector<int> &bits);\n\n\tvoid add_dummy_ce();\n\tvoid add_dummy_srst();\n\tvoid add_dummy_arst();\n\tvoid add_dummy_aload();\n\tvoid add_dummy_sr();\n\tvoid add_dummy_clk();\n\n\tvoid arst_to_aload();\n\tvoid arst_to_sr();\n\n\tvoid aload_to_sr();\n\n\t// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and\n\t// fixes up control signals appropriately to preserve semantics.\n\tvoid convert_ce_over_srst(bool val);\n\n\tvoid unmap_ce();\n\tvoid unmap_srst();\n\n\tvoid unmap_ce_srst() {\n\t\tunmap_ce();\n\t\tunmap_srst();\n\t}\n\n\tCell *emit();\n\n\t// Removes init attribute from the Q output, but keeps val_init unchanged.\n\t// It will be automatically reattached on emit. Use this before changing sig_q.\n\tvoid remove_init() {\n\t\tif (initvals)\n\t\t\tinitvals->remove_init(sig_q);\n\t}\n\n\tvoid remove();\n\n\t// Flip the sense of the given bit slices of the FF: insert inverters on data\n\t// inputs and output, flip the corresponding init/reset bits, swap clr/set\n\t// inputs with proper priority fix.\n\tvoid flip_bits(const pool<int> &bits);\n\n\tvoid flip_rst_bits(const pool<int> &bits);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
166
167
  "ffinit.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFINIT_H\n#define FFINIT_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FfInitVals\n{\n\tconst SigMap *sigmap;\n\tdict<SigBit, std::pair<State,SigBit>> initbits;\n\n\tvoid set(const SigMap *sigmap_, RTLIL::Module *module)\n\t{\n\t\tsigmap = sigmap_;\n\t\tinitbits.clear();\n\t\tfor (auto wire : module->wires())\n\t\t{\n\t\t\tif (wire->attributes.count(ID::init) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tSigSpec wirebits = (*sigmap)(wire);\n\t\t\tConst initval = wire->attributes.at(ID::init);\n\n\t\t\tfor (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)\n\t\t\t{\n\t\t\t\tSigBit bit = wirebits[i];\n\t\t\t\tState val = initval[i];\n\n\t\t\t\tif (val != State::S0 && val != State::S1 && bit.wire != nullptr)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (initbits.count(bit)) {\n\t\t\t\t\tif (initbits.at(bit).first != val)\n\t\t\t\t\t\tlog_error(\"Conflicting init values for signal %s (%s = %s != %s).\\n\",\n\t\t\t\t\t\t\t\tlog_signal(bit), log_signal(SigBit(wire, i)),\n\t\t\t\t\t\t\t\tlog_signal(val), log_signal(initbits.at(bit).first));\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tinitbits[bit] = std::make_pair(val,SigBit(wire,i));\n\t\t\t}\n\t\t}\n\t}\n\n\tRTLIL::State operator()(RTLIL::SigBit bit) const\n\t{\n\t\tauto it = initbits.find((*sigmap)(bit));\n\t\tif (it != initbits.end())\n\t\t\treturn it->second.first;\n\t\telse\n\t\t\treturn State::Sx;\n\t}\n\n\tRTLIL::Const operator()(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::Const res;\n\t\tfor (auto bit : sig)\n\t\t\tres.bits.push_back((*this)(bit));\n\t\treturn res;\n\t}\n\n\tvoid set_init(RTLIL::SigBit bit, RTLIL::State val)\n\t{\n\t\tSigBit mbit = (*sigmap)(bit);\n\t\tSigBit abit = bit;\n\t\tauto it = initbits.find(mbit);\n\t\tif (it != initbits.end())\n\t\t\tabit = it->second.second;\n\t\telse if (val == State::Sx)\n\t\t\treturn;\n\t\tlog_assert(abit.wire);\n\t\tinitbits[mbit] = std::make_pair(val,abit);\n\t\tauto it2 = abit.wire->attributes.find(ID::init);\n\t\tif (it2 != abit.wire->attributes.end()) {\n\t\t\tit2->second[abit.offset] = val;\n\t\t\tif (it2->second.is_fully_undef())\n\t\t\t\tabit.wire->attributes.erase(it2);\n\t\t} else if (val != State::Sx) {\n\t\t\tConst cval(State::Sx, GetSize(abit.wire));\n\t\t\tcval[abit.offset] = val;\n\t\t\tabit.wire->attributes[ID::init] = cval;\n\t\t}\n\t}\n\n\tvoid set_init(const RTLIL::SigSpec &sig, RTLIL::Const val)\n\t{\n\t\tlog_assert(GetSize(sig) == GetSize(val));\n\t\tfor (int i = 0; i < GetSize(sig); i++)\n\t\t\tset_init(sig[i], val[i]);\n\t}\n\n\tvoid remove_init(RTLIL::SigBit bit)\n\t{\n\t\tset_init(bit, State::Sx);\n\t}\n\n\tvoid remove_init(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto bit : sig)\n\t\t\tremove_init(bit);\n\t}\n\n\tvoid clear()\n\t{\n\t\tinitbits.clear();\n\t}\n\n\tFfInitVals (const SigMap *sigmap, RTLIL::Module *module)\n\t{\n\t\tset(sigmap, module);\n\t}\n\n\tFfInitVals () {}\n};\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
167
168
  "ffmerge.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFMERGE_H\n#define FFMERGE_H\n\n#include \"kernel/ffinit.h\"\n#include \"kernel/ff.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// A helper class for passes that want to merge FFs on the input or output\n// of a cell into the cell itself.\n//\n// The procedure is:\n//\n// 1. Construct this class (at beginning of processing for a given module).\n// 2. For every considered cell:\n//\n// a. Call find_output_ff for every considered output.\n// b. Call find_input_ff for every considered input.\n// c. Look at the FF description returned (if any) from each call, reject\n// results that cannot be merged into given cell for any reason.\n// If both inputs and outputs are being merged, take care of FF bits that\n// are returned in both input and output results (a FF bit cannot be\n// merged to both). Decide on the final set of FF bits to merge.\n// d. Call remove_output_ff for every find_output_ff result that will be used\n// for merging. This removes the actual FF bits from design and from index.\n// e. Call mark_input_ff for every find_input_ff result that will be used\n// for merging. This updates the index disallowing further usage of these\n// FF bits for output FF merging, if they were eligible before. The actual\n// FF bits are still left in the design and can be merged into other inputs.\n// If the FF bits are not otherwise used, they will be removed by later\n// opt passes.\n// f. Merge the FFs into the cell.\n//\n// Note that, if both inputs and outputs are being considered for merging in\n// a single pass, the result may be nondeterministic (depending on cell iteration\n// order) because a given FF bit could be eligible for both input and output merge,\n// perhaps in different cells. For this reason, it may be a good idea to separate\n// input and output merging.\n\nstruct FfMergeHelper\n{\n\tconst SigMap *sigmap;\n\tRTLIL::Module *module;\n\tFfInitVals *initvals;\n\n\tdict<SigBit, std::pair<Cell*, int>> dff_driver;\n\tdict<SigBit, pool<std::pair<Cell*, int>>> dff_sink;\n\tdict<SigBit, int> sigbit_users_count;\n\n\t// Returns true if all bits in sig are completely unused.\n\tbool is_output_unused(RTLIL::SigSpec sig);\n\n\t// Finds the FF to merge into a given cell output. Takes sig, which\n\t// is the current cell output — it will be the sig_d of the found FF.\n\t// If found, returns true, and fills the two output arguments.\n\t//\n\t// For every bit of sig, this function finds a FF bit that has\n\t// the same sig_d, and fills the output FfData according to the FF\n\t// bits found. This function will only consider FF bits that are\n\t// the only user of the given sig bits — if any bit in sig is used\n\t// by anything other than a single FF, this function will return false.\n\t//\n\t// The returned FfData structure does not correspond to any actual FF\n\t// cell in the design — it is the amalgamation of extracted FF bits,\n\t// possibly coming from several FF cells.\n\t//\n\t// If some of the bits in sig have no users at all, this function\n\t// will accept them as well (and fill returned FfData with dummy values\n\t// for the given bit, effectively synthesizing an unused FF bit of the\n\t// appropriate type). However, if all bits in sig are completely\n\t// unused, this function will fail and return false (having no idea\n\t// what kind of FF to produce) — use the above helper if that case\n\t// is important to handle.\n\t//\n\t// Note that this function does not remove the FF bits returned from\n\t// the design — this is so that the caller can decide whether to accept\n\t// this FF for merging or not. If the result is accepted,\n\t// remove_output_ff should be called on the second output argument.\n\tbool find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// Like above, but returns a FF to merge into a given cell input. Takes\n\t// sig_q, which is the current cell input — it will search for FFs with\n\t// matching sig_q.\n\t//\n\t// As opposed to find_output_ff, this function doesn't care about usage\n\t// counts, and may return FF bits that also have other fanout. This\n\t// should not be a problem for input FF merging.\n\t//\n\t// As a special case, if some of the bits in sig_q are constant, this\n\t// function will accept them as well, by synthesizing in-place\n\t// a constant-input FF bit (with matching initial value and reset value).\n\t// However, this will not work if the input is all-constant — if the caller\n\t// cares about this case, it needs to check for it explicitely.\n\tbool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_output_ff result that will be merged. This\n\t// marks the given FF bits as used up (and not to be considered for\n\t// further merging as inputs), and reconnects their Q ports to a dummy\n\t// wire (since the wire previously connected there will now be driven\n\t// by the merged-to cell instead).\n\tvoid remove_output_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_input_ff result that will be merged. This\n\t// marks the given FF bits as used, and disallows merging them as\n\t// outputs. They can, however, still be merged as inputs again\n\t// (perhaps for another cell).\n\tvoid mark_input_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\tvoid set(FfInitVals *initvals_, RTLIL::Module *module_);\n\n\tvoid clear();\n\n\tFfMergeHelper(FfInitVals *initvals, RTLIL::Module *module) {\n\t\tset(initvals, module);\n\t}\n\n\tFfMergeHelper() {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
168
169
  "fmt.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n// $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tTIME = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n// \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tLITERAL \t= 0,\n\t\tINTEGER \t= 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign = MINUS;\n\tbool hex_upper = false;\n\tbool show_base = false;\n\tbool group = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_literal(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
169
- "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <vector>\n\n#include <stdint.h>\n\nnamespace hashlib {\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\n// The XOR version of DJB2\ninline unsigned int mkhash(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) ^ b;\n}\n\n// traditionally 5381 is used as starting value for the djb2 hash\nconst unsigned int mkhash_init = 5381;\n\n// The ADD version of DJB2\n// (use this version for cache locality in b)\ninline unsigned int mkhash_add(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) + b;\n}\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\ntemplate<typename T> struct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const T &a) {\n\t\treturn a.hash();\n\t}\n};\n\nstruct hash_int_ops {\n\ttemplate<typename T>\n\tstatic inline bool cmp(T a, T b) {\n\t\treturn a == b;\n\t}\n};\n\ntemplate<> struct hash_ops<bool> : hash_int_ops\n{\n\tstatic inline unsigned int hash(bool a) {\n\t\treturn a ? 1 : 0;\n\t}\n};\ntemplate<> struct hash_ops<int32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<int64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\ntemplate<> struct hash_ops<uint32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<uint64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\n\ntemplate<> struct hash_ops<std::string> {\n\tstatic inline bool cmp(const std::string &a, const std::string &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const std::string &a) {\n\t\tunsigned int v = 0;\n\t\tfor (auto c : a)\n\t\t\tv = mkhash(v, c);\n\t\treturn v;\n\t}\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::pair<P, Q> a) {\n\t\treturn mkhash(hash_ops<P>::hash(a.first), hash_ops<Q>::hash(a.second));\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), unsigned int>::type hash(std::tuple<T...>) {\n\t\treturn mkhash_init;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), unsigned int>::type hash(std::tuple<T...> a) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\treturn mkhash(hash<I+1>(a), element_ops_t::hash(std::get<I>(a)));\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::vector<T> a) {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto k : a)\n\t\t\th = mkhash(h, hash_ops<T>::hash(k));\n\t\treturn h;\n\t}\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\tfor (int i = 0; a[i] || b[i]; i++)\n\t\t\tif (a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\tstatic inline unsigned int hash(const char *a) {\n\t\tunsigned int hash = mkhash_init;\n\t\twhile (*a)\n\t\t\thash = mkhash(hash, *(a++));\n\t\treturn hash;\n\t}\n};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const void *a) {\n\t\treturn (uintptr_t)a;\n\t}\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\tstatic inline unsigned int hash(const T *a) {\n\t\treturn a ? a->hash() : 0;\n\t}\n};\n\ntemplate<typename T>\ninline unsigned int mkhash(const T &v) {\n\treturn hash_ops<T>().hash(v);\n}\n\ninline int hashtable_size(int min_size)\n{\n\tstatic std::vector<int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict\n{\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tint hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto &entry : entries) {\n\t\t\th ^= hash_ops<K>::hash(entry.udata.first);\n\t\t\th ^= hash_ops<T>::hash(entry.udata.second);\n\t\t}\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tint hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int hashval = mkhash_init;\n\t\tfor (auto &it : entries)\n\t\t\thashval ^= ops.hash(it.udata);\n\t\treturn hashval;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0, OPS>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
170
+ "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <vector>\n\n#include <stdint.h>\n\nnamespace hashlib {\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\n// The XOR version of DJB2\ninline unsigned int mkhash(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) ^ b;\n}\n\n// traditionally 5381 is used as starting value for the djb2 hash\nconst unsigned int mkhash_init = 5381;\n\n// The ADD version of DJB2\n// (use this version for cache locality in b)\ninline unsigned int mkhash_add(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) + b;\n}\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\ntemplate<typename T> struct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const T &a) {\n\t\treturn a.hash();\n\t}\n};\n\nstruct hash_int_ops {\n\ttemplate<typename T>\n\tstatic inline bool cmp(T a, T b) {\n\t\treturn a == b;\n\t}\n};\n\ntemplate<> struct hash_ops<bool> : hash_int_ops\n{\n\tstatic inline unsigned int hash(bool a) {\n\t\treturn a ? 1 : 0;\n\t}\n};\ntemplate<> struct hash_ops<int32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<int64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\ntemplate<> struct hash_ops<uint32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<uint64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\n\ntemplate<> struct hash_ops<std::string> {\n\tstatic inline bool cmp(const std::string &a, const std::string &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const std::string &a) {\n\t\tunsigned int v = 0;\n\t\tfor (auto c : a)\n\t\t\tv = mkhash(v, c);\n\t\treturn v;\n\t}\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::pair<P, Q> a) {\n\t\treturn mkhash(hash_ops<P>::hash(a.first), hash_ops<Q>::hash(a.second));\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), unsigned int>::type hash(std::tuple<T...>) {\n\t\treturn mkhash_init;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), unsigned int>::type hash(std::tuple<T...> a) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\treturn mkhash(hash<I+1>(a), element_ops_t::hash(std::get<I>(a)));\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::vector<T> a) {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto k : a)\n\t\t\th = mkhash(h, hash_ops<T>::hash(k));\n\t\treturn h;\n\t}\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\tfor (int i = 0; a[i] || b[i]; i++)\n\t\t\tif (a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\tstatic inline unsigned int hash(const char *a) {\n\t\tunsigned int hash = mkhash_init;\n\t\twhile (*a)\n\t\t\thash = mkhash(hash, *(a++));\n\t\treturn hash;\n\t}\n};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const void *a) {\n\t\treturn (uintptr_t)a;\n\t}\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\tstatic inline unsigned int hash(const T *a) {\n\t\treturn a ? a->hash() : 0;\n\t}\n};\n\ntemplate<typename T>\ninline unsigned int mkhash(const T &v) {\n\treturn hash_ops<T>().hash(v);\n}\n\ninline int hashtable_size(int min_size)\n{\n\t// Primes as generated by https://oeis.org/A175953\n\tstatic std::vector<int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217,\n\t\t463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,\n\t\t1769372713\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict\n{\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tint hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto &entry : entries) {\n\t\t\th ^= hash_ops<K>::hash(entry.udata.first);\n\t\t\th ^= hash_ops<T>::hash(entry.udata.second);\n\t\t}\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tint hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int hashval = mkhash_init;\n\t\tfor (auto &it : entries)\n\t\t\thashval ^= ops.hash(it.udata);\n\t\treturn hashval;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\n/**\n * Union-find data structure with a promotion method\n * mfp stands for \"merge, find, promote\"\n * i-prefixed methods operate on indices in parents\n*/\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0, OPS>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\t// Finds a given element's index. If it isn't in the data structure,\n\t// it is added as its own set\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\t// If the lookup caused the database to grow,\n\t\t// also add a corresponding entry in parents initialized to -1 (no parent)\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\t// Finds an element at given index\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\t// p is now the representative of i\n\t\t// Now we traverse from i up to the representative again\n\t\t// and make p the parent of all the nodes along the way.\n\t\t// This is a side effect and doesn't affect the return value.\n\t\t// It speeds up future find operations\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\t// Merge sets if the given indices belong to different sets\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
170
171
  "json.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n enum Scope {\n VALUE,\n OBJECT_FIRST,\n OBJECT,\n ARRAY_FIRST,\n ARRAY,\n };\n\n struct Target {\n virtual void emit(const char *data) = 0;\n virtual void flush() {};\n virtual ~Target() {};\n };\n\n std::string newline_indent = \"\\n\";\n std::vector<std::unique_ptr<Target>> targets;\n std::vector<Scope> state = {VALUE};\n int compact_depth = INT_MAX;\npublic:\n\n void emit_to_log();\n void append_to_string(std::string &target);\n bool write_to_file(const std::string &path);\n\n bool active() { return !targets.empty(); }\n\n void compact() { compact_depth = GetSize(state); }\n\n void line(bool space_if_inline = true);\n void raw(const char *raw_json);\n void flush();\n void begin_object();\n void begin_array();\n void end_object();\n void end_array();\n void name(const char *name);\n void begin_value();\n void end_value();\n void value_json(const Json &value);\n void value(unsigned int value) { value_json(Json((int)value)); }\n template<typename T>\n void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n void entry_json(const char *name, const Json &value);\n void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n template<typename T>\n void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n template<typename T>\n void object(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n entry(item.first, item.second);\n end_object();\n }\n\n template<typename T>\n void array(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n value(item);\n end_object();\n }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
171
172
  "log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T, typename OPS> static inline void log_dump_val_worker(dict<K, T, OPS> &v);\ntemplate<typename K, typename OPS> static inline void log_dump_val_worker(pool<K, OPS> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T, typename OPS>\nstatic inline void log_dump_val_worker(dict<K, T, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K, typename OPS>\nstatic inline void log_dump_val_worker(pool<K, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
172
173
  "macc.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct port_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\n\tstd::vector<port_t> ports;\n\tRTLIL::SigSpec bit_ports;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<port_t> new_ports;\n\t\tRTLIL::SigSpec new_bit_ports;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {\n\t\t\t\tbit_ports.append(port.in_a);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tfor (auto &bit : bit_ports)\n\t\t\tif (bit == State::S1)\n\t\t\t\toff = const_add(off, RTLIL::Const(1, width), false, false, width);\n\t\t\telse if (bit != State::S0)\n\t\t\t\tnew_bit_ports.append(bit);\n\n\t\tif (off.as_bool()) {\n\t\t\tport_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tnew_ports.swap(ports);\n\t\tbit_ports = new_bit_ports;\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tports.clear();\n\t\tbit_ports = cell->getPort(ID::B);\n\n\t\tstd::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tport_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tports.push_back(this_port);\n\t\t}\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell) const\n\t{\n\t\tRTLIL::SigSpec port_a;\n\t\tstd::vector<RTLIL::State> config_bits;\n\t\tint max_size = 0, num_bits = 0;\n\n\t\tfor (auto &port : ports) {\n\t\t\tmax_size = max(max_size, GetSize(port.in_a));\n\t\t\tmax_size = max(max_size, GetSize(port.in_b));\n\t\t}\n\n\t\twhile (max_size)\n\t\t\tnum_bits++, max_size /= 2;\n\n\t\tlog_assert(num_bits < 16);\n\t\tconfig_bits.push_back(num_bits & 1 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 2 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 4 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 8 ? State::S1 : State::S0);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tconfig_bits.push_back(port.is_signed ? State::S1 : State::S0);\n\t\t\tconfig_bits.push_back(port.do_subtract ? State::S1 : State::S0);\n\n\t\t\tint size_a = GetSize(port.in_a);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tint size_b = GetSize(port.in_b);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tport_a.append(port.in_a);\n\t\t\tport_a.append(port.in_b);\n\t\t}\n\n\t\tcell->setPort(ID::A, port_a);\n\t\tcell->setPort(ID::B, bit_ports);\n\t\tcell->setParam(ID::CONFIG, config_bits);\n\t\tcell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));\n\t\tcell->setParam(ID::A_WIDTH, GetSize(port_a));\n\t\tcell->setParam(ID::B_WIDTH, GetSize(bit_ports));\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits)\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\tfor (auto bit : bit_ports) {\n\t\t\tif (bit.wire)\n\t\t\t\treturn false;\n\t\t\tresult = const_add(result, bit.data, false, false, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
@@ -177,7 +178,7 @@ export const filesystem = {
177
178
  "rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct IdString\n\t{\n\t\t#undef YOSYS_XTRACE_GET_PUT\n\t\t#undef YOSYS_SORT_ID_FREE_LIST\n\t\t#undef YOSYS_USE_STICKY_IDS\n\t\t#undef YOSYS_NO_IDS_REFCNT\n\n\t\t// the global id string cache\n\n\t\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\t\tstatic struct destruct_guard_t {\n\t\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t\t} destruct_guard;\n\n\t\tstatic std::vector<char*> global_id_storage_;\n\t\tstatic dict<char*, int, hash_cstr_ops> global_id_index_;\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic std::vector<int> global_refcount_storage_;\n\t\tstatic std::vector<int> global_free_idx_list_;\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tstatic int last_created_idx_ptr_;\n\t\tstatic int last_created_idx_[8];\n\t#endif\n\n\t\tstatic inline void xtrace_db_dump()\n\t\t{\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t\t{\n\t\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\t\telse\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\t\t}\n\n\t\tstatic inline void checkpoint()\n\t\t{\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\tlast_created_idx_ptr_ = 0;\n\t\t\tfor (int i = 0; i < 8; i++) {\n\t\t\t\tif (last_created_idx_[i])\n\t\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\t\tlast_created_idx_[i] = 0;\n\t\t\t}\n\t\t#endif\n\t\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t\t#endif\n\t\t}\n\n\t\tstatic inline int get_reference(int idx)\n\t\t{\n\t\t\tif (idx) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_[idx]++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\t\t\t}\n\t\t\treturn idx;\n\t\t}\n\n\t\tstatic int get_reference(const char *p)\n\t\t{\n\t\t\tlog_assert(destruct_guard_ok);\n\n\t\t\tif (!p[0])\n\t\t\t\treturn 0;\n\n\t\t\tauto it = global_id_index_.find((char*)p);\n\t\t\tif (it != global_id_index_.end()) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t\t#endif\n\t\t\t\treturn it->second;\n\t\t\t}\n\n\t\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\t\tlog_assert(p[1] != 0);\n\t\t\tfor (const char *c = p; *c; c++)\n\t\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tif (global_free_idx_list_.empty()) {\n\t\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t\t}\n\t\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t}\n\n\t\t\tint idx = global_free_idx_list_.back();\n\t\t\tglobal_free_idx_list_.pop_back();\n\t\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\t\tglobal_refcount_storage_.at(idx)++;\n\t\t#else\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tint idx = global_id_storage_.size();\n\t\t\tglobal_id_storage_.push_back(strdup(p));\n\t\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t\t#endif\n\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\t// Avoid Create->Delete->Create pattern\n\t\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t\t#endif\n\n\t\t\treturn idx;\n\t\t}\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic inline void put_reference(int idx)\n\t\t{\n\t\t\t// put_reference() may be called from destructors after the destructor of\n\t\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\t\tif (!destruct_guard_ok || !idx)\n\t\t\t\treturn;\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\n\t\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\t\tif (--refcount > 0)\n\t\t\t\treturn;\n\n\t\t\tlog_assert(refcount == 0);\n\t\t\tfree_reference(idx);\n\t\t}\n\t\tstatic inline void free_reference(int idx)\n\t\t{\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\t\tfree(global_id_storage_.at(idx));\n\t\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\t\tglobal_free_idx_list_.push_back(idx);\n\t\t}\n\t#else\n\t\tstatic inline void put_reference(int) { }\n\t#endif\n\n\t\t// the actual IdString object is just is a single int\n\n\t\tint index_;\n\n\t\tinline IdString() : index_(0) { }\n\t\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\t\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\t\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\t\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\t\tinline ~IdString() { put_reference(index_); }\n\n\t\tinline void operator=(const IdString &rhs) {\n\t\t\tput_reference(index_);\n\t\t\tindex_ = get_reference(rhs.index_);\n\t\t}\n\n\t\tinline void operator=(const char *rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline void operator=(const std::string &rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline const char *c_str() const {\n\t\t\treturn global_id_storage_.at(index_);\n\t\t}\n\n\t\tinline std::string str() const {\n\t\t\treturn std::string(global_id_storage_.at(index_));\n\t\t}\n\n\t\tinline bool operator<(const IdString &rhs) const {\n\t\t\treturn index_ < rhs.index_;\n\t\t}\n\n\t\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\t\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\t\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\t\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\t\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\t\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\t\tchar operator[](size_t i) const {\n const char *p = c_str();\n#ifndef NDEBUG\n\t\t\tfor (; i != 0; i--, p++)\n\t\t\t\tlog_assert(*p != 0);\n\t\t\treturn *p;\n#else\n\t\t\treturn *(p + i);\n#endif\n\t\t}\n\n\t\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\t\treturn std::string(c_str() + pos);\n\t\t\telse\n\t\t\t\treturn std::string(c_str() + pos, len);\n\t\t}\n\n\t\tint compare(size_t pos, size_t len, const char* s) const {\n\t\t\treturn strncmp(c_str()+pos, s, len);\n\t\t}\n\n\t\tbool begins_with(const char* prefix) const {\n\t\t\tsize_t len = strlen(prefix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(0, len, prefix) == 0;\n\t\t}\n\n\t\tbool ends_with(const char* suffix) const {\n\t\t\tsize_t len = strlen(suffix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(size()-len, len, suffix) == 0;\n\t\t}\n\n\t\tbool contains(const char* str) const {\n\t\t\treturn strstr(c_str(), str);\n\t\t}\n\n\t\tsize_t size() const {\n\t\t\treturn strlen(c_str());\n\t\t}\n\n\t\tbool empty() const {\n\t\t\treturn c_str()[0] == 0;\n\t\t}\n\n\t\tvoid clear() {\n\t\t\t*this = IdString();\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn index_;\n\t\t}\n\n\t\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t\t// set has an influence on the algorithm.\n\n\t\ttemplate<typename T> struct compare_ptr_by_name {\n\t\t\tbool operator()(const T *a, const T *b) const {\n\t\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t\t}\n\t\t};\n\n\t\t// often one needs to check if a given IdString is part of a list (for example a list\n\t\t// of cell types). the following functions helps with that.\n\n\t\ttemplate<typename... Args>\n\t\tbool in(Args... args) const {\n\t\t\t// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html\n\t\t\tbool result = false;\n\t\t\t(void) std::initializer_list<int>{ (result = result || in(args), 0)... };\n\t\t\treturn result;\n\t\t}\n\n\t\tbool in(const IdString &rhs) const { return *this == rhs; }\n\t\tbool in(const char *rhs) const { return *this == rhs; }\n\t\tbool in(const std::string &rhs) const { return *this == rhs; }\n\t\tbool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n\n\t\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\t};\n\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tint flags;\n\tstd::vector<RTLIL::State> bits;\n\n\tConst() : flags(RTLIL::CONST_FLAG_NONE) {}\n\tConst(const std::string &str);\n\tConst(int val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &c) = default;\n\tRTLIL::Const &operator =(const RTLIL::Const &other) = default;\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tstatic Const from_string(const std::string &str);\n\n\tstd::string decode_string() const;\n\n\tinline int size() const { return bits.size(); }\n\tinline bool empty() const { return bits.empty(); }\n\tinline RTLIL::State &operator[](int index) { return bits.at(index); }\n\tinline const RTLIL::State &operator[](int index) const { return bits.at(index); }\n\tinline decltype(bits)::iterator begin() { return bits.begin(); }\n\tinline decltype(bits)::iterator end() { return bits.end(); }\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tinline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {\n\t\tRTLIL::Const ret;\n\t\tret.bits.reserve(len);\n\t\tfor (int i = offset; i < offset + len; i++)\n\t\t\tret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);\n\t\treturn ret;\n\t}\n\n\tvoid extu(int width) {\n\t\tbits.resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());\n\t}\n\n\tinline unsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto b : bits)\n\t\t\th = mkhash(h, b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\tunsigned int hash() const;\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tunsigned long hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tsize_t get_hash() const {\n\t\tif (!hash_) hash();\n\t\treturn hash_;\n\t}\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\tunsigned int hash() const { if (!hash_) updhash(); return hash_; };\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline unsigned int RTLIL::SigBit::hash() const {\n\tif (wire)\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\treturn data;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
178
179
  "satgen.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tSigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string name = pf + (bit.wire->width == 1 ? stringf(\"%s\", log_id(bit.wire)) : stringf(\"%s [%d]\", log_id(bit.wire->name), bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
179
180
  "scopeinfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\tunsigned int hash() const { return (uintptr_t)ptr; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tif (!object->name.isPublic())\n\t\treturn path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty())\n\t\tpath.push_back(object->name);\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic()) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
180
- "sigtools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SIGTOOLS_H\n#define SIGTOOLS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct SigPool\n{\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tpool<bitDef_t> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.insert(bit);\n\t}\n\n\tvoid add(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.insert(bit);\n\t}\n\n\tvoid del(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.erase(bit);\n\t}\n\n\tvoid del(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.erase(bit);\n\t}\n\n\tvoid expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\t\tfor (int i = 0; i < GetSize(from); i++) {\n\t\t\tbitDef_t bit_from(from[i]), bit_to(to[i]);\n\t\t\tif (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)\n\t\t\t\tbits.insert(bit_to);\n\t\t}\n\t}\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tRTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tbool check(const RTLIL::SigBit &bit) const\n\t{\n\t\treturn bit.wire != NULL && bits.count(bit);\n\t}\n\n\tbool check_any(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool check_all(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tRTLIL::SigSpec export_one() const\n\t{\n\t\tfor (auto &bit : bits)\n\t\t\treturn RTLIL::SigSpec(bit.first, bit.second);\n\t\treturn RTLIL::SigSpec();\n\t}\n\n\tRTLIL::SigSpec export_all() const\n\t{\n\t\tpool<RTLIL::SigBit> sig;\n\t\tfor (auto &bit : bits)\n\t\t\tsig.insert(RTLIL::SigBit(bit.first, bit.second));\n\t\treturn sig;\n\t}\n\n\tsize_t size() const\n\t{\n\t\treturn bits.size();\n\t}\n};\n\ntemplate <typename T, class Compare = void>\nstruct SigSet\n{\n\tstatic_assert(!std::is_same<Compare,void>::value, \"Default value for `Compare' class not found for SigSet<T>. Please specify.\");\n\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tdict<bitDef_t, std::set<T, Compare>> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid insert(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data);\n\t}\n\n\tvoid insert(const RTLIL::SigSpec& sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data.begin(), data.end());\n\t}\n\n\tvoid erase(const RTLIL::SigSpec& sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].clear();\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data);\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data.begin(), data.end());\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, std::set<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, pool<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tstd::set<T> find(const RTLIL::SigSpec &sig)\n\t{\n\t\tstd::set<T> result;\n\t\tfind(sig, result);\n\t\treturn result;\n\t}\n\n\tbool has(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n};\n\ntemplate<typename T>\nclass SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};\ntemplate<typename T>\nusing sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;\ntemplate<typename T>\nclass SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};\n\nstruct SigMap\n{\n\tmfp<SigBit> database;\n\n\tSigMap(RTLIL::Module *module = NULL)\n\t{\n\t\tif (module != NULL)\n\t\t\tset(module);\n\t}\n\n\tvoid swap(SigMap &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid clear()\n\t{\n\t\tdatabase.clear();\n\t}\n\n\tvoid set(RTLIL::Module *module)\n\t{\n\t\tint bitcount = 0;\n\t\tfor (auto &it : module->connections())\n\t\t\tbitcount += it.first.size();\n\n\t\tdatabase.clear();\n\t\tdatabase.reserve(bitcount);\n\n\t\tfor (auto &it : module->connections())\n\t\t\tadd(it.first, it.second);\n\t}\n\n\tvoid add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\n\t\tfor (int i = 0; i < GetSize(from); i++)\n\t\t{\n\t\t\tint bfi = database.lookup(from[i]);\n\t\t\tint bti = database.lookup(to[i]);\n\n\t\t\tconst RTLIL::SigBit &bf = database[bfi];\n\t\t\tconst RTLIL::SigBit &bt = database[bti];\n\n\t\t\tif (bf.wire || bt.wire)\n\t\t\t{\n\t\t\t\tdatabase.imerge(bfi, bti);\n\n\t\t\t\tif (bf.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bfi);\n\n\t\t\t\tif (bt.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bti);\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid add(const RTLIL::SigBit &bit)\n\t{\n\t\tconst auto &b = database.find(bit);\n\t\tif (b.wire != nullptr)\n\t\t\tdatabase.promote(bit);\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tadd(bit);\n\t}\n\n\tinline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }\n\n\tvoid apply(RTLIL::SigBit &bit) const\n\t{\n\t\tbit = database.find(bit);\n\t}\n\n\tvoid apply(RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tapply(bit);\n\t}\n\n\tRTLIL::SigBit operator()(RTLIL::SigBit bit) const\n\t{\n\t\tapply(bit);\n\t\treturn bit;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::SigSpec sig) const\n\t{\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::Wire *wire) const\n\t{\n\t\tSigSpec sig(wire);\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec allbits() const\n\t{\n\t\tRTLIL::SigSpec sig;\n\t\tfor (const auto &bit : database)\n\t\t\tif (bit.wire != nullptr)\n\t\t\t\tsig.append(bit);\n\t\treturn sig;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif /* SIGTOOLS_H */\n",
181
+ "sigtools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SIGTOOLS_H\n#define SIGTOOLS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct SigPool\n{\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tpool<bitDef_t> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.insert(bit);\n\t}\n\n\tvoid add(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.insert(bit);\n\t}\n\n\tvoid del(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.erase(bit);\n\t}\n\n\tvoid del(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.erase(bit);\n\t}\n\n\tvoid expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\t\tfor (int i = 0; i < GetSize(from); i++) {\n\t\t\tbitDef_t bit_from(from[i]), bit_to(to[i]);\n\t\t\tif (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)\n\t\t\t\tbits.insert(bit_to);\n\t\t}\n\t}\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tRTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tbool check(const RTLIL::SigBit &bit) const\n\t{\n\t\treturn bit.wire != NULL && bits.count(bit);\n\t}\n\n\tbool check_any(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool check_all(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tRTLIL::SigSpec export_one() const\n\t{\n\t\tfor (auto &bit : bits)\n\t\t\treturn RTLIL::SigSpec(bit.first, bit.second);\n\t\treturn RTLIL::SigSpec();\n\t}\n\n\tRTLIL::SigSpec export_all() const\n\t{\n\t\tpool<RTLIL::SigBit> sig;\n\t\tfor (auto &bit : bits)\n\t\t\tsig.insert(RTLIL::SigBit(bit.first, bit.second));\n\t\treturn sig;\n\t}\n\n\tsize_t size() const\n\t{\n\t\treturn bits.size();\n\t}\n};\n\ntemplate <typename T, class Compare = void>\nstruct SigSet\n{\n\tstatic_assert(!std::is_same<Compare,void>::value, \"Default value for `Compare' class not found for SigSet<T>. Please specify.\");\n\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tdict<bitDef_t, std::set<T, Compare>> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid insert(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data);\n\t}\n\n\tvoid insert(const RTLIL::SigSpec& sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data.begin(), data.end());\n\t}\n\n\tvoid erase(const RTLIL::SigSpec& sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].clear();\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data);\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data.begin(), data.end());\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, std::set<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, pool<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tstd::set<T> find(const RTLIL::SigSpec &sig)\n\t{\n\t\tstd::set<T> result;\n\t\tfind(sig, result);\n\t\treturn result;\n\t}\n\n\tbool has(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n};\n\ntemplate<typename T>\nclass SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};\ntemplate<typename T>\nusing sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;\ntemplate<typename T>\nclass SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};\n\n/**\n * SigMap wraps a union-find \"database\"\n * to map SigBits of a module to canonical representative SigBits.\n * SigBits that are connected share a set in the underlying database.\n * If a SigBit has a const state (impl: bit.wire is nullptr),\n * it's promoted to a representative.\n */\nstruct SigMap\n{\n\tmfp<SigBit> database;\n\n\tSigMap(RTLIL::Module *module = NULL)\n\t{\n\t\tif (module != NULL)\n\t\t\tset(module);\n\t}\n\n\tvoid swap(SigMap &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid clear()\n\t{\n\t\tdatabase.clear();\n\t}\n\n\t// Rebuild SigMap for all connections in module\n\tvoid set(RTLIL::Module *module)\n\t{\n\t\tint bitcount = 0;\n\t\tfor (auto &it : module->connections())\n\t\t\tbitcount += it.first.size();\n\n\t\tdatabase.clear();\n\t\tdatabase.reserve(bitcount);\n\n\t\tfor (auto &it : module->connections())\n\t\t\tadd(it.first, it.second);\n\t}\n\n\t// Add connections from \"from\" to \"to\", bit-by-bit\n\tvoid add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\n\t\tfor (int i = 0; i < GetSize(from); i++)\n\t\t{\n\t\t\tint bfi = database.lookup(from[i]);\n\t\t\tint bti = database.lookup(to[i]);\n\n\t\t\tconst RTLIL::SigBit &bf = database[bfi];\n\t\t\tconst RTLIL::SigBit &bt = database[bti];\n\n\t\t\tif (bf.wire || bt.wire)\n\t\t\t{\n\t\t\t\tdatabase.imerge(bfi, bti);\n\n\t\t\t\tif (bf.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bfi);\n\n\t\t\t\tif (bt.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bti);\n\t\t\t}\n\t\t}\n\t}\n\n\t// Add sig as disconnected from anything\n\tvoid add(const RTLIL::SigBit &bit)\n\t{\n\t\tconst auto &b = database.find(bit);\n\t\tif (b.wire != nullptr)\n\t\t\tdatabase.promote(bit);\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tadd(bit);\n\t}\n\n\tinline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }\n\n\t// Modify bit to its representative\n\tvoid apply(RTLIL::SigBit &bit) const\n\t{\n\t\tbit = database.find(bit);\n\t}\n\n\tvoid apply(RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tapply(bit);\n\t}\n\n\tRTLIL::SigBit operator()(RTLIL::SigBit bit) const\n\t{\n\t\tapply(bit);\n\t\treturn bit;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::SigSpec sig) const\n\t{\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::Wire *wire) const\n\t{\n\t\tSigSpec sig(wire);\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\t// All non-const bits\n\tRTLIL::SigSpec allbits() const\n\t{\n\t\tRTLIL::SigSpec sig;\n\t\tfor (const auto &bit : database)\n\t\t\tif (bit.wire != nullptr)\n\t\t\t\tsig.append(bit);\n\t\treturn sig;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif /* SIGTOOLS_H */\n",
181
182
  "timinginfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * (C) 2020 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tunsigned int hash() const { return mkhash_add(name.hash(), offset); }\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\tunsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
182
183
  "utils.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T, typename OPS = hash_ops<Key>>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*, OPS>> backup_state;\n\tdict<Key, T, OPS> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T, OPS> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T, OPS> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> class TopoSort\n{\n public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n if (rv.second) {\n \t nodes.push_back(n);\n\t\t edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
183
184
  "yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n//\n// Find more information in the \"guidelines/GettingStarted\" file.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
@@ -276,6 +277,17 @@ export const filesystem = {
276
277
  "lutrams.txt": "ram distributed $__TRELLIS_DPR16X4_ {\n\tabits 4;\n\twidth 4;\n\tcost 4;\n\tinit any;\n\tprune_rom;\n\tport sw \"W\" {\n\t\tclock anyedge;\n\t}\n\tport ar \"R\" {\n\t}\n}\n",
277
278
  "lutrams_map.v": "module $__TRELLIS_DPR16X4_(...);\n\nparameter INIT = 64'bx;\nparameter PORT_W_CLK_POL = 1;\n\ninput PORT_W_CLK;\ninput [3:0] PORT_W_ADDR;\ninput [3:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\ninput [3:0] PORT_R_ADDR;\noutput [3:0] PORT_R_RD_DATA;\n\nlocalparam WCKMUX = PORT_W_CLK_POL ? \"WCK\" : \"INV\";\n\nTRELLIS_DPR16X4 #(\n\t.INITVAL(INIT),\n\t.WCKMUX(WCKMUX),\n\t.WREMUX(\"WRE\")\n) _TECHMAP_REPLACE_ (\n\t.RAD(PORT_R_ADDR),\n\t.DO(PORT_R_RD_DATA),\n\n\t.WAD(PORT_W_ADDR),\n\t.DI(PORT_W_WR_DATA),\n\t.WCK(PORT_W_CLK),\n\t.WRE(PORT_W_WR_EN)\n);\n\nendmodule\n",
278
279
  },
280
+ "microchip": {
281
+ "LSRAM.txt": "# ISC License\n# \n# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n# \n# Permission to use, copy, modify, and/or distribute this software for any\n# purpose with or without fee is hereby granted, provided that the above\n# copyright notice and this permission notice appear in all copies.\n# \n# THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n\n\n\n# LSRAM true dual-port\nram block $__LSRAM_TDP_ {\n\n\t# Cost of a given cell is assumed to be:\n\t# (cost-widthscale) + [widthscale * (used_bits/14)]\n\tcost 129;\n\n\t# INIT is supported\n\tinit any;\n\n\t# port A and port B are allowed to have different widths, but they MUST have\n\t# \tWIDTH values of the same set. \n\t# Example: Port A has a Data Width of 1. Then Port B's Data Width must be either\n\t# 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).\t\n\t# \tWIDTH_1 = {1, 2, 4, 8, 16}\n\t# \tWIDTH_2 = {5, 10, 20}\n\n\t# \"byte\" specifies how many data bits correspond to one write enable bit.\n\t#\t\t\"byte\" must be larger than width, or width must be a multipler of \"byte\"\n\t#\t\tif \"byte\" > WIDTH, a single enable wire is inferred\n\t#\t\totherwise, WIDTH/byte number of enable wires are inferred\n\t# \t\t\n\t# \t\tWIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire\n\t# \t\tWIDTH = {16, 20} requires 2 enable wire\n\n\toption \"WIDTH_CONFIG\" \"REGULAR\" {\n\n\t\t# Data-Width| Address bits\n\t\t# 1 \t\t| 14\n\t\t# 2 \t\t| 13\n\t\t# 4 \t\t| 12\n\t\t# 8 \t\t| 11\n\t\t# 16\t\t| 10\n\n\t\t# 14 address bits\n\t\tabits 14;\n\n\t\twidths 1 2 4 8 16 per_port;\n\t\tbyte 8;\n\t}\n\toption \"WIDTH_CONFIG\" \"ALIGN\" {\n\t\t\n\t\t# Data-Width| Address bits\n\t\t# 5 \t\t| 12\n\t\t# 10\t\t| 11\n\t\t# 20\t\t| 10\n\n\t\t# Quick \"hack\" to fix address bit alignment by setting address bits to 12.\n\t\t# If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20\n\t\t# THe LSRAM_map.v file detects if this option is being used, and adjusts the address port alignments accordingly.\n\t\tabits 12;\n\n\t\twidths 5 10 20 per_port;\n\t\tbyte 10;\n\t}\n\t\n\t\n\n\tport srsw \"A\" \"B\" {\n\n\t\t# read & write width must be same\n\t\twidth tied;\n\t\t\n\t\t# clock polarity is rising\n\t\tclock posedge;\n\n\t\t# A/B read-enable\n\t\trden;\n\n\n\t\t# initial value of read port data (not supported)\n\t\trdinit none;\n\n\t\t# write modes (<A/B>_WMODE)\n\t\t# \t1. Simple Write: read-data port holds prev value (similar to \"NO_CHANGE\" for RAMB18E1)\n\t\t# \t2. Feed-through: read-data port takes new write value (similar to \"WRITE_FIRST\" for RAMB18E1)\n\t\t# \t3. Read-Before-Write: read-data port holds old value while being written (similar to \"READ_FIRST\" for RAMB18E1)\n\n\t\tportoption \"WRITE_MODE\" \"NO_CHANGE\" {\n\n\t\t\t# Read-write interaction\n\t\t\trdwr no_change;\n\n\t\t\t# Write transparency:\n\t\t\t# For write ports, define behaviour when another synchronous read port \n\t\t\t# reads from the same memory cell that said write port is writing to at the same time. \n\t\t\twrtrans all old;\n\t\t}\n\t\tportoption \"WRITE_MODE\" \"WRITE_FIRST\" {\n\t\t\t# bits corresponding to high A/B_WEN are updated\n\t\t\trdwr new_only;\n\t\t\twrtrans all new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\trdwr old;\n\n\t\t\twrtrans all old;\n\t\t}\n\n\t\t# generate params to indicate if read or write is used for each port\n\t\toptional_rw;\n\t}\n}\n\n# two-port configuration\nram block $__LSRAM_SDP_ {\n\t\n\t# since two-port configuration is dedicated for wide-read/write,\n\t#\twe want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs \n\t#\tinplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should\n\t#\tbe less than 2 TDP.\n\tcost 129;\n\tinit any;\n\n\toption \"WIDTH_CONFIG\" \"REGULAR\" {\n\n\t\t# Data-Width| Address bits\n\t\t# 1 \t\t| 14\n\t\t# 2 \t\t| 13\n\t\t# 4 \t\t| 12\n\t\t# 8 \t\t| 11\n\t\t# 16\t\t| 10\n\t\t# 32\t\t| 9\n\n\t\tabits 14;\n\n\t\twidths 1 2 4 8 16 32 per_port;\n\n\t\t# width = 32, byte-write size is 8, ignore other widths\n\t\tbyte 8;\n\t\t\n\t}\n\toption \"WIDTH_CONFIG\" \"ALIGN\" {\n\t\t\n\t\t# Data-Width| Address bits\n\t\t# 5 \t\t| 12\n\t\t# 10\t\t| 11\n\t\t# 20\t\t| 10\n\t\t# 40\t\t| 9\n\n\t\t# Same trick as TSP RAM for alignment\n\t\tabits 12;\n\t\twidths 5 10 20 40 per_port;\n\t\tbyte 10;\n\t}\n\n\tport sw \"W\" {\n\n\t\t# only consider wide write\n\t\t\n\t\toption \"WIDTH_CONFIG\" \"REGULAR\" width 32;\n\t\toption \"WIDTH_CONFIG\" \"ALIGN\" width 40;\n\n\t\tclock posedge;\n\n\t\t# only simple write supported for two-port mode\n\t\twrtrans all old;\n\t\t\n\t\toptional;\n\t}\n\tport sr \"R\" {\n\n\t\toption \"WIDTH_CONFIG\" \"REGULAR\" width 32;\n\t\toption \"WIDTH_CONFIG\" \"ALIGN\" width 40;\n\n\n\t\tclock posedge;\n\t\trden;\n\t\trdinit none;\n\t\toptional;\n\t}\n}\n",
282
+ "LSRAM_map.v": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\n// See document PolarFire Family Fabric User Guide\n// section 4.1 for port list.\n\n\n//LSRAM true dual-port\nmodule $__LSRAM_TDP_ (...);\n\nparameter INIT = 0;\nparameter ADDR_BITS = 14;\n\nparameter OPTION_WIDTH_CONFIG = \"A\";\n\nparameter PORT_A_WIDTH = 1;\nparameter PORT_A_WR_EN_WIDTH = 1;\nparameter PORT_A_RD_USED = 0;\nparameter PORT_A_WR_USED = 0;\nparameter PORT_A_OPTION_WRITE_MODE = \"NO_CHANGE\";\n\nparameter PORT_B_WIDTH = 1;\nparameter PORT_B_WR_EN_WIDTH = 1;\nparameter PORT_B_RD_USED = 0;\nparameter PORT_B_WR_USED = 0;\nparameter PORT_B_OPTION_WRITE_MODE = \"NO_CHANGE\";\n\n\ninput PORT_A_CLK;\ninput PORT_A_RD_EN;\ninput [ADDR_BITS-1:0] PORT_A_ADDR;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\ninput [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\n\ninput PORT_B_CLK;\ninput PORT_B_RD_EN;\ninput [ADDR_BITS-1:0] PORT_B_ADDR;\ninput [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;\ninput [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;\noutput [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;\n\n\n`include \"brams_defs.vh\"\n\n// address wires\nwire [ADDR_BITS-1:0] A_address;\nwire [ADDR_BITS-1:0] B_address;\nassign A_address = (OPTION_WIDTH_CONFIG == \"REGULAR\") ? PORT_A_ADDR : {PORT_A_ADDR, 2'b00};\nassign B_address = (OPTION_WIDTH_CONFIG == \"REGULAR\") ? PORT_B_ADDR : {PORT_B_ADDR, 2'b00};\n\n// if port is not used, set block sel to 0 to disable it (read-data output is set to 0)\nparameter PORT_A_RD_USED = 0;\nparameter PORT_A_WR_USED = 0;\nwire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;\nwire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;\n\n// wires for write data \ngenerate\n\twire [19:0] A_write_data;\n\twire [19:0] B_write_data;\n\tif (PORT_A_WIDTH == 16) begin\n\t\tassign A_write_data[7:0] = PORT_A_WR_DATA[7:0];\n\t\tassign A_write_data[17:10] = PORT_A_WR_DATA[15:8];\n\t\tassign A_write_data[9:8] = 2'b0;\n\t\tassign A_write_data[19:18] = 2'b0;\n\tend else begin\n\t\tassign A_write_data[PORT_A_WIDTH-1:0] = PORT_A_WR_DATA;\n\tend\n\n\tif (PORT_B_WIDTH == 16) begin\n\t\tassign B_write_data[7:0] = PORT_B_WR_DATA[7:0];\n\t\tassign B_write_data[17:10] = PORT_B_WR_DATA[15:8];\n\t\tassign B_write_data[9:8] = 2'b0;\n\t\tassign B_write_data[19:18] = 2'b0;\n\tend else begin\n\t\tassign B_write_data[PORT_B_WIDTH-1:0] = PORT_B_WR_DATA;\n\tend\nendgenerate\n\n// wires for read data\nwire [19:0] A_read_data;\nassign PORT_A_RD_DATA = A_read_data[PORT_A_WIDTH-1:0];\nwire [19:0] B_read_data;\nassign PORT_B_RD_DATA = B_read_data[PORT_B_WIDTH-1:0];\n\n// byte-write enables\nwire [1:0] A_write_EN = (PORT_A_WR_EN_WIDTH == 1) ? {1'b0, PORT_A_WR_EN} : PORT_A_WR_EN;\nwire [1:0] B_write_EN = (PORT_B_WR_EN_WIDTH == 1) ? {1'b0, PORT_B_WR_EN} : PORT_B_WR_EN;\n\n// port width\nwire [2:0] A_width = (PORT_A_WIDTH == 1) ? 3'b000 :\n\t\t\t\t\t(PORT_A_WIDTH == 2) ? 3'b001 :\n\t\t\t\t\t(PORT_A_WIDTH == 4 || PORT_A_WIDTH == 5) ? 3'b010 :\n\t\t\t\t\t(PORT_A_WIDTH == 8 || PORT_A_WIDTH == 10) ? 3'b011 : 3'b100;\nwire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :\n\t\t\t\t\t(PORT_B_WIDTH == 2) ? 3'b001 :\n\t\t\t\t\t(PORT_B_WIDTH == 4 || PORT_B_WIDTH == 5) ? 3'b010 :\n\t\t\t\t\t(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;\n\n// write modes\nwire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == \"NO_CHANGE\" ? 2'b00 : \n\t\t\t\t\t\tPORT_A_OPTION_WRITE_MODE == \"WRITE_FIRST\" ? 2'b01 : 2'b10;\nwire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == \"NO_CHANGE\" ? 2'b00 : \n\t\t\t\t\t\tPORT_B_OPTION_WRITE_MODE == \"WRITE_FIRST\" ? 2'b01 : 2'b10;\n\nRAM1K20 #(\n\t`PARAMS_INIT_LSRAM\n) _TECHMAP_REPLACE_ (\n\n\t// port A\n\t.A_ADDR(A_address),\n\t.A_BLK_EN(A_BLK_SEL),\n\t.A_CLK(PORT_A_CLK),\n\t.A_DIN(A_write_data),\n\t.A_DOUT(A_read_data),\n\t.A_WEN(A_write_EN),\n\t.A_REN(PORT_A_RD_EN),\n\t.A_WIDTH(A_width),\n\t.A_WMODE(A_write_mode),\n\t.A_BYPASS(1'b1),\n\t.A_DOUT_EN(1'b1),\n\t.A_DOUT_SRST_N(1'b1),\n\t.A_DOUT_ARST_N(1'b1),\n\n\t// port B\n\t.B_ADDR(B_address),\n\t.B_BLK_EN(B_BLK_SEL),\n\t.B_CLK(PORT_B_CLK),\n\t.B_DIN(B_write_data),\n\t.B_DOUT(B_read_data),\n\t.B_WEN(B_write_EN),\n\t.B_REN(PORT_B_RD_EN),\n\t.B_WIDTH(B_width),\n\t.B_WMODE(B_write_mode),\n\t.B_BYPASS(1'b1),\n\t.B_DOUT_EN(1'b1),\n\t.B_DOUT_SRST_N(1'b1),\n\t.B_DOUT_ARST_N(1'b1),\n\n\t// Disable ECC for TDP\n\t.ECC_EN(1'b0), \n\t.ECC_BYPASS(1'b1),\n\t.BUSY_FB(1'b0)\n\n);\n\nendmodule\n\n// single dual port configuration\nmodule $__LSRAM_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_WIDTH_CONFIG = \"REGULAR\";\nparameter ADDR_BITS = 14;\n\nparameter PORT_W_WIDTH = 1;\nparameter PORT_W_WR_EN_WIDTH = 4;\nparameter PORT_W_USED = 1;\n\nparameter PORT_R_WIDTH = 1;\nparameter PORT_R_USED = 0;\n\ninput PORT_W_CLK;\ninput [ADDR_BITS-1:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\ninput [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;\n\ninput PORT_R_CLK;\ninput PORT_R_RD_EN;\ninput [ADDR_BITS-1:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\ninput PORT_R_RD_SRST;\n\n`include \"brams_defs.vh\"\n\n\n// address wires\nwire [ADDR_BITS-1:0] A_address;\nwire [ADDR_BITS-1:0] B_address;\nassign A_address = (OPTION_WIDTH_CONFIG == \"REGULAR\") ? PORT_R_ADDR : {PORT_R_ADDR, 2'b00};\nassign B_address = (OPTION_WIDTH_CONFIG == \"REGULAR\") ? PORT_W_ADDR : {PORT_W_ADDR, 2'b00};\n\n// if port is not used, set block sel to 0 to disable it (read-data output is set to 0)\n// port A is for read, port B for write\nparameter PORT_W_USED = 0;\nparameter PORT_R_USED = 0;\nwire [2:0] A_BLK_SEL = (PORT_R_USED == 1) ? 3'b111 : 3'b000;\nwire [2:0] B_BLK_SEL = (PORT_W_USED == 1) ? 3'b111 : 3'b000;\n\n// read/write data & write enables\n// Currently support only wide write, width = {32, 40}\ngenerate\n\twire [19:0] A_write_data;\n\twire [19:0] B_write_data;\n\twire [1:0] A_write_EN;\n\twire [1:0] B_write_EN;\n\n\t// write port (A provides MSB) \n\tif (PORT_W_WIDTH == 32) begin\n\n\t\tassign B_write_data[3:0] = PORT_W_WR_DATA[3:0];\n\t\tassign B_write_data[8:5] = PORT_W_WR_DATA[7:4];\n\t\tassign B_write_data[13:10] = PORT_W_WR_DATA[11:8];\n\t\tassign B_write_data[18:15] = PORT_W_WR_DATA[15:12];\n\t\tassign B_write_data[4] = 1'b0;\n\t\tassign B_write_data[9] = 1'b0;\n\t\tassign B_write_data[14] = 1'b0;\n\t\tassign B_write_data[19] = 1'b0;\n\n\t\tassign A_write_data[3:0] = PORT_W_WR_DATA[19:16];\n\t\tassign A_write_data[8:5] = PORT_W_WR_DATA[23:20];\n\t\tassign A_write_data[13:10] = PORT_W_WR_DATA[27:24];\n\t\tassign A_write_data[18:15] = PORT_W_WR_DATA[31:28];\n\t\tassign A_write_data[4] = 1'b0;\n\t\tassign A_write_data[9] = 1'b0;\n\t\tassign A_write_data[14] = 1'b0;\n\t\tassign A_write_data[19] = 1'b0;\n\t\t\n\tend else if (PORT_W_WIDTH == 40) begin\n\t\tassign B_write_data = PORT_W_WR_DATA[19:0];\n\t\tassign A_write_data = PORT_W_WR_DATA[39:20];\n\tend\n\n\t// byte-write enables\n\tassign A_write_EN = PORT_W_WR_EN[1:0];\n\tassign B_write_EN = PORT_W_WR_EN[3:2];\n\n\t// read ports (A provides MSB)\n\twire [19:0] A_read_data;\n\twire [19:0] B_read_data;\n\tif (PORT_R_WIDTH == 32) begin\n\t\tassign PORT_R_RD_DATA[3:0] = B_read_data[3:0];\n\t\tassign PORT_R_RD_DATA[8:5] = B_read_data[7:4];\n\t\tassign PORT_R_RD_DATA[13:10] = B_read_data[11:8];\n\t\tassign PORT_R_RD_DATA[18:15] = B_read_data[15:12];\n\n\t\tassign PORT_R_RD_DATA[19:16] = A_read_data[3:0];\n\t\tassign PORT_R_RD_DATA[23:20] = A_read_data[8:5];\n\t\tassign PORT_R_RD_DATA[27:24] = A_read_data[13:10];\n\t\tassign PORT_R_RD_DATA[31:28] = A_read_data[18:15];\n\tend else if (PORT_R_WIDTH == 40) begin\n\t\tassign PORT_R_RD_DATA[19:0] = B_read_data[19:0];\n\t\tassign PORT_R_RD_DATA[39:20] = A_read_data[19:0];\n\tend\nendgenerate\n\n// port width\nwire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :\n\t\t\t\t\t(PORT_R_WIDTH == 2) ? 3'b001 :\n\t\t\t\t\t(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :\n\t\t\t\t\t(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : \n\t\t\t\t\t(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;\nwire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :\n\t\t\t\t\t(PORT_W_WIDTH == 2) ? 3'b001 :\n\t\t\t\t\t(PORT_W_WIDTH == 4 || PORT_W_WIDTH == 5) ? 3'b010 :\n\t\t\t\t\t(PORT_W_WIDTH == 8 || PORT_W_WIDTH == 10) ? 3'b011 :\n\t\t\t\t\t(PORT_W_WIDTH == 16 || PORT_W_WIDTH == 20) ? 3'b100 : 3'b101;\n\n// write modes\nwire [1:0] A_write_mode = 2'b00;\nwire [1:0] B_write_mode = 2'b00;\n\nRAM1K20 #(\n\t`PARAMS_INIT_LSRAM\n) _TECHMAP_REPLACE_ (\n\t// port A - read\n\t.A_ADDR(A_address),\n\t.A_BLK_EN(A_BLK_SEL),\n\t.A_CLK(PORT_R_CLK),\n\t.A_DIN(A_write_data),\n\t.A_DOUT(A_read_data),\n\t.A_WEN(A_write_EN),\n\t.A_REN(PORT_R_RD_EN),\n\t.A_WIDTH(A_width),\n\t.A_WMODE(A_write_mode),\n\t.A_BYPASS(1'b1),\n\t.A_DOUT_EN(1'b1),\n\t.A_DOUT_SRST_N(1'b1),\n\t.A_DOUT_ARST_N(1'b1),\n\n\t// port B - write\n\t.B_ADDR(B_address),\n\t.B_BLK_EN(B_BLK_SEL),\n\t.B_CLK(PORT_W_CLK),\n\t.B_DIN(B_write_data),\n\t.B_DOUT(B_read_data),\n\t.B_WEN(B_write_EN),\n\t.B_REN(PORT_R_RD_EN),\n\t.B_WIDTH(B_width),\n\t.B_WMODE(B_write_mode),\n\t.B_BYPASS(1'b1),\n\t.B_DOUT_EN(1'b1),\n\t.B_DOUT_SRST_N(1'b1),\n\t.B_DOUT_ARST_N(1'b1),\n\n\t// Disable ECC for SDP\n\t.ECC_EN(1'b0), \n\t.ECC_BYPASS(1'b1),\n\t.BUSY_FB(1'b0)\n);\n\n\nendmodule\n",
283
+ "arith_map.v": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\n// Based on Macro Library for PolarFire https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf\n// NOTE: prefix module names with \\$__ so that mapping prioritizes these cells over internal Yosys cells\n\n\n(* techmap_celltype = \"$_MUX4_\" *)\nmodule \\$__microchip_MUX4_ (A, B, C, D, S, T, Y);\n\tinput A, B, C, D, S, T;\n\toutput Y;\n\tMX4 _TECHMAP_REPLACE_.MUX4(.D3(D), .D2(C), .D1(B), .D0(A), .S1(T), .S0(S), .Y(Y));\n\nendmodule\n\n\n(* techmap_celltype = \"$reduce_xor\" *)\nmodule \\$__microchip_XOR8_ (A, Y);\n\tparameter A_SIGNED = 1;\n\tparameter A_WIDTH = 8;\n\tparameter Y_WIDTH = 1;\n\n\tinput [A_WIDTH-1:0] A;\n\toutput [Y_WIDTH-1:0] Y;\n\n\t// check if mapping should proceed\n\tgenerate\n\t\tif (A_WIDTH != 8 || A_SIGNED || Y_WIDTH != 1) begin\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\tend\n\tendgenerate\n\n\n\tXOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y));\n\n\t\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule \\$__SF2_ALU (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA, BB;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB));\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] C = {CO, CI};\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n\t\tARI1 #(\n\t\t\t// See section 1.4 of PolarFire Macro Library\n\n\t\t\t// G = F1 = A[i] & (B[i]^BI)\n\t\t\t// Y = F0 = A[i]^B[i]^BI\n\t\t\t// P = Y\n\t\t\t//\t\t ADCB\n\t\t\t.INIT(20'b 01_11_0010_1000_1001_0110)\n\t\t) carry (\n\t\t\t.A(1'b0),\n\t\t\t.B(AA[i]),\n\t\t\t.C(BB[i]),\n\t\t\t.D(BI),\n\t\t\t.FCI(C[i]),\n\t\t\t.Y(X[i]),\n\t\t\t.S(Y[i]),\n\t\t\t.FCO(CO[i])\n\t\t);\n\tend endgenerate\nendmodule\n\n",
284
+ "brams_defs.vh": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\n`define PARAMS_INIT_LSRAM \\\n\t.INIT0(slice_init_LSRAM(00)), \\\n\t.INIT1(slice_init_LSRAM(01)), \\\n\t.INIT2(slice_init_LSRAM(02)), \\\n\t.INIT3(slice_init_LSRAM(03)), \\\n\t.INIT4(slice_init_LSRAM(04)), \\\n\t.INIT5(slice_init_LSRAM(05)), \\\n\t.INIT6(slice_init_LSRAM(06)), \\\n\t.INIT7(slice_init_LSRAM(07)), \\\n\t.INIT8(slice_init_LSRAM(08)), \\\n\t.INIT9(slice_init_LSRAM(09)), \\\n\t.INIT10(slice_init_LSRAM(10)), \\\n\t.INIT11(slice_init_LSRAM(11)), \\\n\t.INIT12(slice_init_LSRAM(12)), \\\n\t.INIT13(slice_init_LSRAM(13)), \\\n\t.INIT14(slice_init_LSRAM(14)), \\\n\t.INIT15(slice_init_LSRAM(15)), \\\n\t.INIT16(slice_init_LSRAM(16)), \\\n\t.INIT17(slice_init_LSRAM(17)), \\\n\t.INIT18(slice_init_LSRAM(18)), \\\n\t.INIT19(slice_init_LSRAM(19))\n\n`define PARAMS_INIT_uSRAM \\\n\t.INIT0(slice_init_uSRAM(00)), \\\n\t.INIT1(slice_init_uSRAM(01)), \\\n\t.INIT2(slice_init_uSRAM(02)), \\\n\t.INIT3(slice_init_uSRAM(03)), \\\n\t.INIT4(slice_init_uSRAM(04)), \\\n\t.INIT5(slice_init_uSRAM(05)), \\\n\t.INIT6(slice_init_uSRAM(06)), \\\n\t.INIT7(slice_init_uSRAM(07)), \\\n\t.INIT8(slice_init_uSRAM(08)), \\\n\t.INIT9(slice_init_uSRAM(09)), \\\n\t.INIT10(slice_init_uSRAM(10)), \\\n\t.INIT11(slice_init_uSRAM(11)) \\\n\n// Helper function for initializing the LSRAM\nfunction [1023:0] slice_init_LSRAM;\n\tinput integer slice_idx;\n\tinteger i;\n\tfor (i = 0; i < 1024; i = i + 1)\n\t\tslice_init_LSRAM[i] = INIT[(slice_idx * 1024 + i)];\nendfunction\n\n// Helper function for initializing the uSRAM\nfunction [63:0] slice_init_uSRAM;\n\tinput integer slice_idx;\n\tinteger i;\n\tfor (i = 0; i < 64; i = i + 1)\n\t\tslice_init_uSRAM[i] = INIT[(slice_idx * 64 + i)];\nendfunction",
285
+ "cells_map.v": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\n// DFFs\nmodule \\$_DFFE_PN0P_ (input D, C, R, E, output Q);\n\tSLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));\nendmodule\n\nmodule \\$_DFFE_PN1P_ (input D, C, R, E, output Q);\n\tSLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));\nendmodule\n\n// for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom\n// and map to intermediate cell types\nmodule \\$_SDFFCE_PN0P_ (input D, C, R, E, output Q);\n\tMICROCHIP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));\nendmodule\n\nmodule \\$_SDFFCE_PN1P_ (input D, C, R, E, output Q);\n\tMICROCHIP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));\nendmodule\n\n\n// LATCHES\n\nmodule \\$_DLATCH_PN0_ (input D, R, E, output Q);\n\tSLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));\nendmodule\n\nmodule \\$_DLATCH_PN1_ (input D, R, E, output Q);\n\tSLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));\nendmodule\n\nmodule \\$_DLATCH_P_ (input D, E, output Q);\n\tSLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(1'b1), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));\nendmodule\n\n// map intermediate flops to SLE\n`ifdef FINAL_MAP\nmodule MICROCHIP_SYNC_SET_DFF(\n\tinput D,\n\tinput CLK,\n\tinput Set,\n\tinput En,\n\toutput Q);\n\tSLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));\nendmodule\n\nmodule MICROCHIP_SYNC_RESET_DFF(\n\tinput D,\n\tinput CLK,\n\tinput Reset,\n\tinput En,\n\toutput Q);\n\tSLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Reset), .SD(1'b0), .LAT(1'b0), .Q(Q));\nendmodule\n`endif\n\n\n// LUT\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\tif (WIDTH == 1) begin\n\t\tCFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));\n\tend else\n\tif (WIDTH == 2) begin\n\t\tCFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));\n\tend else\n\tif (WIDTH == 3) begin\n\t\tCFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));\n\tend else\n\tif (WIDTH == 4) begin\n\t\tCFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));\n\tend else begin\n\t\twire _TECHMAP_FAIL_ = 1;\n\tend\n\tendgenerate\nendmodule\n`endif\n\n",
286
+ "cells_sim.v": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\n// Macro Library for PolarFire https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf\n\nmodule AND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A & B;\nendmodule\n\nmodule AND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A & B & C;\nendmodule\n\nmodule AND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A & B & C & D;\nendmodule\n\n(* abc9_lut=1 *)\nmodule CFG1 (\n\toutput Y,\n\tinput A\n);\n\tparameter [1:0] INIT = 2'h0;\n\tassign Y = INIT >> A;\n\tspecify\n\t\t(A => Y) = 127;\n\tendspecify\nendmodule\n\n(* abc9_lut=1 *)\nmodule CFG2 (\n\toutput Y,\n\tinput A,\n\tinput B\n);\n\tparameter [3:0] INIT = 4'h0;\n\tassign Y = INIT >> {B, A};\n\tspecify\n\t\t(A => Y) = 238;\n\t\t(B => Y) = 127;\n\tendspecify\nendmodule\n\n(* abc9_lut=1 *)\nmodule CFG3 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C\n);\n\tparameter [7:0] INIT = 8'h0;\n\tassign Y = INIT >> {C, B, A};\n\tspecify\n\t\t(A => Y) = 407;\n\t\t(B => Y) = 238;\n\t\t(C => Y) = 127;\n\tendspecify\nendmodule\n\n(* abc9_lut=1 *)\nmodule CFG4 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C,\n\tinput D\n);\n\tparameter [15:0] INIT = 16'h0;\n\tassign Y = INIT >> {D, C, B, A};\n\tspecify\n\t\t(A => Y) = 472;\n\t\t(B => Y) = 407;\n\t\t(C => Y) = 238;\n\t\t(D => Y) = 127;\n\tendspecify\nendmodule\n\nmodule BUFF (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule BUFD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT_PRESERVE (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule GCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule RCLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule RGCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\n// sequential elements\n\n// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow \n//\tsee: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html\n\n(* abc9_flop, lib_whitebox *)\nmodule MICROCHIP_SYNC_SET_DFF(\n\tinput D,\n\tinput CLK,\n\tinput Set,\n\tinput En,\n\toutput reg Q);\n\tparameter [0:0] INIT = 1'b0; // unused\n\n\talways @(posedge CLK) begin\n\t\tif (En == 1) begin\n\t\t\tif (Set == 0)\n\t\t\t\tQ <= 1;\n\t\t\telse\n\t\t\t\tQ <= D;\n\t\tend\n\tend\n\n\tspecify\n\t\t$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?\n\t\t$setup(En, posedge CLK, 109);\n\t\t$setup(Set, posedge CLK &&& En, 404);\n\t\tif (En && !Set) (posedge CLK => (Q : 1'b1)) = 303;\n\t\tif (En && Set) (posedge CLK => (Q : D)) = 303;\n\tendspecify\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule MICROCHIP_SYNC_RESET_DFF(\n\tinput D,\n\tinput CLK,\n\tinput Reset,\n\tinput En,\n\toutput reg Q);\n\tparameter [0:0] INIT = 1'b0; // unused\n\n\talways @(posedge CLK) begin\n\t\tif (En == 1) begin\n\t\t\tif (Reset == 0) \n\t\t\t\tQ <= 0;\n\t\t\telse\n\t\t\t\tQ <= D;\n\t\tend\n\tend\n\n\tspecify\n\t\t$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?\n\t\t$setup(En, posedge CLK, 109);\n\t\t$setup(Reset, posedge CLK &&& En, 404);\n\t\tif (En && !Reset) (posedge CLK => (Q : 1'b0)) = 303;\n\t\tif (En && Reset) (posedge CLK => (Q : D)) = 303;\n\tendspecify\nendmodule\n\nmodule SLE (\n\toutput Q,\n\tinput ADn,\n\tinput ALn,\n\t(* clkbuf_sink *)\n\tinput CLK,\n\tinput D,\n\tinput LAT,\n\tinput SD,\n\tinput EN,\n\tinput SLn\n);\n\treg q_latch, q_ff;\n\n\talways @(posedge CLK, negedge ALn) begin\n\t\tif (!ALn) begin\n\t\t\tq_ff <= !ADn;\n\t\tend else if (EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\talways @* begin\n\t\tif (!ALn) begin\n\t\t\tq_latch <= !ADn;\n\t\tend else if (CLK && EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\tassign Q = LAT ? q_latch : q_ff;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ARI1 (\n\t(* abc9_carry *)\n\tinput FCI,\n\t(* abc9_carry *)\n\toutput FCO,\n\n\tinput A, B, C, D, \n\toutput Y, S\n);\n\tparameter [19:0] INIT = 20'h0;\n\twire [2:0] Fsel = {D, C, B};\n\twire F0 = INIT[Fsel];\n\twire F1 = INIT[8 + Fsel];\n\twire Yout = A ? F1 : F0;\n\tassign Y = Yout;\n\tassign S = FCI ^ Yout;\n\twire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];\n\twire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);\n\tassign FCO = P ? FCI : G;\n\t\n\tspecify\n\t\t//pin to pin path delay \n\t\t(A => Y )\t= 472;\n\t\t(B => Y )\t= 407;\n\t\t(C => Y )\t= 238;\n\t\t(D => Y )\t= 127;\n\t\t(A => S )\t= 572;\n\t\t(B => S )\t= 507;\n\t\t(C => S )\t= 338;\n\t\t(D => S )\t= 227;\n\t\t(FCI => S ) = 100;\n\t\t(A => FCO ) = 522;\n\t\t(B => FCO ) = 457;\n\t\t(C => FCO ) = 288;\n\t\t(D => FCO ) = 177;\n\t\t(FCI => FCO ) = 50;\n\tendspecify\nendmodule\n\n(* blackbox *)\nmodule GCLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\nmodule INV (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule INVD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule MX2 (\n\tinput A, B, S,\n\toutput Y\n);\n\tassign Y = S ? B : A;\nendmodule\n\nmodule MX4 (\n\tinput D0, D1, D2, D3, S0, S1,\n\toutput Y\n);\n\tassign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);\nendmodule\n\nmodule NAND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A & B);\nendmodule\n\nmodule NAND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A & B & C);\nendmodule\n\nmodule NAND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A & B & C & D);\nendmodule\n\nmodule NOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A | B);\nendmodule\n\nmodule NOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A | B | C);\nendmodule\n\nmodule NOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A | B | C | D);\nendmodule\n\nmodule OR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A | B;\nendmodule\n\nmodule OR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A | B | C;\nendmodule\n\nmodule OR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A | B | C | D;\nendmodule\n\nmodule XOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A ^ B;\nendmodule\n\nmodule XOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C;\nendmodule\n\nmodule XOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D;\nendmodule\n\nmodule XOR8 (\n\tinput A, B, C, D, E, F, G, H,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;\nendmodule\n\n// module UJTAG\n\nmodule BIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule BIBUF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PADP,\n\t(* iopad_external_pin *)\n\tinout PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule CLKBIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\nmodule CLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\n\tspecify\n\t \t(PAD => Y) = 50;\n\tendspecify\nendmodule\n\n(* blackbox *)\nmodule CLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule INBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule INBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule OUTBUF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = D;\nendmodule\n\n(* blackbox *)\nmodule OUTBUF_DIFF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule TRIBUFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\nendmodule\n\n(* blackbox *)\nmodule TRIBUFF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\n(* blackbox *)\nmodule MACC_PA (\n\tinput DOTP,\n\tinput SIMD,\n\tinput OVFL_CARRYOUT_SEL,\n\tinput CLK,\n\tinput AL_N,\n\tinput [17:0] A,\n\tinput A_BYPASS,\n\tinput A_SRST_N,\n\tinput A_EN,\n\tinput [17:0] B,\n\tinput B_BYPASS,\n\tinput B_SRST_N,\n\tinput B_EN,\n\tinput [17:0] D,\n\tinput D_BYPASS,\n\tinput D_ARST_N,\n\tinput D_SRST_N,\n\tinput D_EN,\n\tinput CARRYIN,\n\tinput [47:0] C,\n\tinput C_BYPASS,\n\tinput C_ARST_N,\n\tinput C_SRST_N,\n\tinput C_EN,\n\tinput [47:0] CDIN,\n\toutput [47:0] P,\n\toutput OVFL_CARRYOUT,\n\tinput P_BYPASS,\n\tinput P_SRST_N,\n\tinput P_EN,\n\toutput [47:0] CDOUT,\n\tinput PASUB,\n\tinput PASUB_BYPASS,\n\tinput PASUB_AD_N,\n\tinput PASUB_SL_N,\n\tinput PASUB_SD_N,\n\tinput PASUB_EN,\n\tinput [1:0] CDIN_FDBK_SEL,\n\tinput CDIN_FDBK_SEL_BYPASS,\n\tinput [1:0] CDIN_FDBK_SEL_AD_N,\n\tinput CDIN_FDBK_SEL_SL_N,\n\tinput [1:0] CDIN_FDBK_SEL_SD_N,\n\tinput CDIN_FDBK_SEL_EN,\n\tinput ARSHFT17,\n\tinput ARSHFT17_BYPASS,\n\tinput ARSHFT17_AD_N,\n\tinput ARSHFT17_SL_N,\n\tinput ARSHFT17_SD_N,\n\tinput ARSHFT17_EN,\n\tinput SUB,\n\tinput SUB_BYPASS,\n\tinput SUB_AD_N,\n\tinput SUB_SL_N,\n\tinput SUB_SD_N,\n\tinput SUB_EN\n);\nendmodule\n\n(* blackbox *)\nmodule RAM1K20 (\n\tinput \t[13:0] \tA_ADDR,\n\tinput \t[2:0]\tA_BLK_EN,\n\tinput\t\t\tA_CLK,\n\tinput \t[19:0]\tA_DIN,\n\toutput\t[19:0]\tA_DOUT,\n\tinput \t[1:0]\tA_WEN,\n\tinput\t\t\tA_REN,\n\tinput \t[2:0]\tA_WIDTH,\n\tinput \t[1:0]\tA_WMODE,\n\tinput \t\t\tA_BYPASS,\n\tinput \t\t\tA_DOUT_EN,\n\tinput \t\t\tA_DOUT_SRST_N,\n\tinput \t\t\tA_DOUT_ARST_N,\n\tinput \t[13:0]\tB_ADDR,\n\tinput \t[2:0]\tB_BLK_EN,\n\tinput\t\t\tB_CLK,\n\tinput \t[19:0] \tB_DIN,\n\toutput\t[19:0]\tB_DOUT,\n\tinput \t[1:0]\tB_WEN,\n\tinput\t\t\tB_REN,\n\tinput \t[2:0]\tB_WIDTH,\n\tinput \t[1:0]\tB_WMODE,\n\tinput\t\t\tB_BYPASS,\n\tinput\t\t\tB_DOUT_EN,\n\tinput\t\t\tB_DOUT_SRST_N,\n\tinput\t\t\tB_DOUT_ARST_N,\n\tinput\t\t\tECC_EN, \n\tinput\t\t\tECC_BYPASS,\n\toutput\t\t\tSB_CORRECT,\n\toutput\t\t\tDB_DETECT,\n\tinput\t\t\tBUSY_FB,\n\toutput\t\t\tACCESS_BUSY\n);\nparameter INIT0 = 1024'h0;\nparameter INIT1 = 1024'h0;\nparameter INIT2 = 1024'h0;\nparameter INIT3 = 1024'h0;\nparameter INIT4 = 1024'h0;\nparameter INIT5 = 1024'h0;\nparameter INIT6 = 1024'h0;\nparameter INIT7 = 1024'h0;\nparameter INIT8 = 1024'h0;\nparameter INIT9 = 1024'h0;\nparameter INIT10 = 1024'h0;\nparameter INIT11 = 1024'h0;\nparameter INIT12 = 1024'h0;\nparameter INIT13 = 1024'h0;\nparameter INIT14 = 1024'h0;\nparameter INIT15 = 1024'h0;\nparameter INIT16 = 1024'h0;\nparameter INIT17 = 1024'h0;\nparameter INIT18 = 1024'h0;\nparameter INIT19 = 1024'h0;\nendmodule\n\n(* blackbox *)\nmodule RAM64x12 (\n\tinput\t\t\tR_CLK,\n\tinput [5:0]\t\tR_ADDR,\n\tinput\t\t\tR_ADDR_BYPASS,\n\tinput\t\t\tR_ADDR_EN,\n\tinput \t\t\tR_ADDR_SL_N,\n\tinput\t\t\tR_ADDR_SD,\n\tinput\t\t\tR_ADDR_AL_N, \n\tinput\t\t\tR_ADDR_AD_N,\n\tinput\t\t\tBLK_EN,\n\toutput [11:0]\tR_DATA,\n\tinput\t\t\tR_DATA_BYPASS,\n\tinput\t \t\tR_DATA_EN,\n\tinput\t \t\tR_DATA_SL_N,\n\tinput\t \t\tR_DATA_SD,\n\tinput\t \t\tR_DATA_AL_N,\n\tinput\t \t\tR_DATA_AD_N,\n\n\tinput\t\tW_CLK,\n\tinput [5:0]\tW_ADDR,\n\tinput [11:0]W_DATA,\n\tinput\t\tW_EN,\n\n\tinput\t\tBUSY_FB,\n\toutput\t\tACCESS_BUSY\n);\nparameter INIT0 = 64'h0;\nparameter INIT1 = 64'h0;\nparameter INIT2 = 64'h0;\nparameter INIT3 = 64'h0;\nparameter INIT4 = 64'h0;\nparameter INIT5 = 64'h0;\nparameter INIT6 = 64'h0;\nparameter INIT7 = 64'h0;\nparameter INIT8 = 64'h0;\nparameter INIT9 = 64'h0;\nparameter INIT10 = 64'h0;\nparameter INIT11 = 64'h0;\n\nendmodule",
287
+ "polarfire_dsp_map.v": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\nmodule \\$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 0;\n\tparameter B_WIDTH = 0;\n\tparameter Y_WIDTH = 0;\n\n\twire [47:0] P_48;\n\t// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:\n\t// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf\n\tMACC_PA _TECHMAP_REPLACE_ (\n\t\t.DOTP(1'b0), \n\t\t.SIMD(1'b0), \n\t\t.OVFL_CARRYOUT_SEL(1'b0), \n\n\t\t.AL_N(1'b1),\n\t\t.A(A),\n\t\t.A_BYPASS(1'b1),\n\t\t.A_SRST_N(1'b1),\n\t\t.A_EN(1'b1),\n\n\t\t.B(B),\n\t\t.B_BYPASS(1'b1),\n\t\t.B_SRST_N(1'b1),\n\t\t.B_EN(1'b1),\n\n\t\t.D(18'b0),\n\t\t.D_BYPASS(1'b1),\n\t\t.D_ARST_N(1'b1),\n\t\t.D_SRST_N(1'b1),\n\t\t.D_EN(1'b1),\n\t\t\n\t\t.CARRYIN(1'b0),\n\t\t.C(48'b0),\n\t\t.C_BYPASS(1'b1),\n\t\t.C_ARST_N(1'b1),\n\t\t.C_SRST_N(1'b1),\n\t\t.C_EN(1'b1),\n\n\t\t\n\t\t.P(P_48),\n\n\t\t.P_BYPASS(1'b1),\n\t\t.P_SRST_N(1'b1),\n\t\t.P_EN(1'b1),\n\n\t\t.PASUB(1'b0),\n\t\t.PASUB_BYPASS(1'b1),\n\t\t.PASUB_AD_N(1'b0),\n\t\t.PASUB_SL_N(1'b1),\n\t\t.PASUB_SD_N(1'b0),\n\t\t.PASUB_EN(1'b1),\n\n\t\t.CDIN_FDBK_SEL(2'b00),\n\t\t.CDIN_FDBK_SEL_BYPASS(1'b1),\n\t\t.CDIN_FDBK_SEL_AD_N(2'b00),\n\t\t.CDIN_FDBK_SEL_SL_N(1'b1),\n\t\t.CDIN_FDBK_SEL_SD_N(2'b00),\n\t\t.CDIN_FDBK_SEL_EN(1'b1),\n\n\t\t.ARSHFT17(1'b0),\n\t\t.ARSHFT17_BYPASS(1'b1),\n\t\t.ARSHFT17_AD_N(1'b0),\n\t\t.ARSHFT17_SL_N(1'b1),\n\t\t.ARSHFT17_SD_N(1'b0),\n\t\t.ARSHFT17_EN(1'b1),\n\n\t\t.SUB(1'b0),\n\t\t.SUB_BYPASS(1'b1),\n\t\t.SUB_AD_N(1'b0),\n\t\t.SUB_SL_N(1'b1),\n\t\t.SUB_SD_N(1'b0),\n\t\t.SUB_EN(1'b1)\n\n\t);\n\tassign Y = P_48;\nendmodule\n",
288
+ "uSRAM.txt": "# ISC License\n# \n# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n# \n# Permission to use, copy, modify, and/or distribute this software for any\n# purpose with or without fee is hereby granted, provided that the above\n# copyright notice and this permission notice appear in all copies.\n# \n# THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n# asynchronous read\nram block $__uSRAM_AR_ {\n\n\t#(LSRAM cost)/3\n\tcost 43;\n\n\t# INIT supported\n\tinit any;\n\n\tabits 6;\n\twidths 12 per_port;\n\n\t# single write enable wire\n\tport sw \"W\" {\n\t\tclock posedge;\n\n\t\t# collision not supported, but write takes precedence and read data is invalid while writing to \n\t\t# the same address\n\t\twrtrans all new;\n\t\t\n\t\toptional;\n\t}\n\tport ar \"R\" {\n\t\toptional;\n\t}\n}\n\n# synchronous read\n# NOTE: synchronous read can be realized by the address pipeline register or data pipeline register.\n#\t\tThis assumes address is synchronized\nram block $__uSRAM_SR_ {\n\n\tcost 42;\n\n\tinit any;\n\tabits 6;\nwidths 12 per_port;\n\n\tport sw \"W\" {\n\t\tclock posedge;\n\n\t\t# collision not supported\n\t\twrtrans all new;\n\t\t\n\t\toptional;\n\t}\n\tport sr \"R\" {\n\t\tclock posedge;\n\t\trden;\n\t\trdinit none;\n\t\toptional;\n\t}\n}\n",
289
+ "uSRAM_map.v": "/*\nISC License\n\nCopyright (C) 2024 Microchip Technology Inc. and its subsidiaries\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n*/\n\n// See document PolarFire Family Fabric User Guide\n// section 4.2 for port list.\n\n// Asynchronous read\nmodule $__uSRAM_AR_ (...);\n\nparameter INIT = 0;\nparameter ADDR_BITS = 6;\n\nparameter PORT_W_WIDTH = 12;\nparameter PORT_R_WIDTH = 12;\nparameter PORT_R_USED = 0;\nparameter PORT_W_USED = 0;\n\ninput PORT_W_CLK;\ninput [ADDR_BITS-1:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\ninput [ADDR_BITS-1:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\n`include \"brams_defs.vh\"\n\nRAM64x12 #(\n\t`PARAMS_INIT_uSRAM\n) _TECHMAP_REPLACE_ (\n\t.R_ADDR(PORT_R_ADDR),\n\t.R_ADDR_BYPASS(1'b1),\n\t.R_ADDR_EN(1'b0),\n\t.R_ADDR_SL_N(1'b1),\n\t.R_ADDR_SD(1'b0),\n\t.R_ADDR_AL_N(1'b1), \n\t.R_ADDR_AD_N(1'b0),\n\t.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),\n\t.R_DATA(PORT_R_RD_DATA),\n\t.R_DATA_BYPASS(1'b1),\n\t.R_DATA_EN(1'b0),\n\t.R_DATA_SL_N(1'b1),\n\t.R_DATA_SD(1'b0),\n\t.R_DATA_AL_N(1'b1),\n\t.R_DATA_AD_N(1'b0),\n\n\t.W_CLK(PORT_W_CLK),\n\t.W_ADDR(PORT_W_ADDR),\n\t.W_DATA(PORT_W_WR_DATA),\n\t.W_EN(PORT_W_WR_EN),\n\n\t.BUSY_FB(1'b0)\n);\n\nendmodule\n\n// Synchronous read\nmodule $__uSRAM_SR_ (...);\n\nparameter INIT = 0;\nparameter ADDR_BITS = 6;\n\nparameter PORT_W_WIDTH = 12;\nparameter PORT_R_WIDTH = 12;\nparameter PORT_R_USED = 0;\nparameter PORT_W_USED = 0;\n\ninput PORT_W_CLK;\ninput [ADDR_BITS-1:0] PORT_W_ADDR;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\ninput PORT_W_WR_EN;\n\n// Read port clock and enable signal\n// that async read uSRAM doesn't have\ninput PORT_R_CLK;\ninput PORT_R_RD_EN;\ninput [ADDR_BITS-1:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\n`include \"brams_defs.vh\"\n\nRAM64x12 #(\n\t`PARAMS_INIT_uSRAM\n) _TECHMAP_REPLACE_ (\n\t.R_CLK(PORT_R_CLK),\n\t.R_ADDR(PORT_R_ADDR),\n\t.R_ADDR_BYPASS(1'b0),\n\t.R_ADDR_EN(PORT_R_RD_EN),\n\t.R_ADDR_SL_N(1'b1),\n\t.R_ADDR_SD(1'b0),\n\t.R_ADDR_AL_N(1'b1), \n\t.R_ADDR_AD_N(1'b0),\n\t.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),\n\t.R_DATA(PORT_R_RD_DATA),\n\t.R_DATA_BYPASS(1'b1),\n\t.R_DATA_EN(1'b0),\n\t.R_DATA_SL_N(1'b1),\n\t.R_DATA_SD(1'b0),\n\t.R_DATA_AL_N(1'b1),\n\t.R_DATA_AD_N(1'b0),\n\n\t.W_CLK(PORT_W_CLK),\n\t.W_ADDR(PORT_W_ADDR),\n\t.W_DATA(PORT_W_WR_DATA),\n\t.W_EN(PORT_W_WR_EN),\n\n\t.BUSY_FB(1'b0)\n);\n\nendmodule\n\n",
290
+ },
279
291
  "mul2dsp.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * 2019 Eddie Hung <eddie@fpgeh.com>\n * 2019 gatecat <gatecat@ds0.me>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * Tech-mapping rules for decomposing arbitrarily-sized $mul cells\n * into an equivalent collection of smaller `DSP_NAME cells (with the \n * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached \n * to $shl and $add cells.\n *\n */\n\n`ifndef DSP_A_MAXWIDTH\n$fatal(1, \"Macro DSP_A_MAXWIDTH must be defined\");\n`endif\n`ifndef DSP_B_MAXWIDTH\n$fatal(1, \"Macro DSP_B_MAXWIDTH must be defined\");\n`endif\n`ifndef DSP_B_MAXWIDTH\n$fatal(1, \"Macro DSP_B_MAXWIDTH must be defined\");\n`endif\n`ifndef DSP_A_MAXWIDTH_PARTIAL\n`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH\n`endif\n`ifndef DSP_B_MAXWIDTH_PARTIAL\n`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH\n`endif\n\n`ifndef DSP_NAME\n$fatal(1, \"Macro DSP_NAME must be defined\");\n`endif\n\n`define MAX(a,b) (a > b ? a : b)\n`define MIN(a,b) (a < b ? a : b)\n\n(* techmap_celltype = \"$mul $__mul\" *)\nmodule _80_mul (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\n\tgenerate\n\tif (0) begin end\n`ifdef DSP_A_MINWIDTH\n\telse if (A_WIDTH < `DSP_A_MINWIDTH)\n\t\twire _TECHMAP_FAIL_ = 1;\n`endif\n`ifdef DSP_B_MINWIDTH\n\telse if (B_WIDTH < `DSP_B_MINWIDTH)\n\t\twire _TECHMAP_FAIL_ = 1;\n`endif\n`ifdef DSP_Y_MINWIDTH\n\telse if (Y_WIDTH < `DSP_Y_MINWIDTH)\n\t\twire _TECHMAP_FAIL_ = 1;\n`endif\n`ifdef DSP_SIGNEDONLY\n\telse if (_TECHMAP_CELLTYPE_ == \"$mul\" && !A_SIGNED && !B_SIGNED)\n\t\t\\$mul #(\n\t\t\t.A_SIGNED(1),\n\t\t\t.B_SIGNED(1),\n\t\t\t.A_WIDTH(A_WIDTH + 1),\n\t\t\t.B_WIDTH(B_WIDTH + 1),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A({1'b0, A}),\n\t\t\t.B({1'b0, B}),\n\t\t\t.Y(Y)\n\t\t);\n`endif\n\telse if (_TECHMAP_CELLTYPE_ == \"$mul\" && A_WIDTH < B_WIDTH)\n\t\t\\$mul #(\n\t\t\t.A_SIGNED(B_SIGNED),\n\t\t\t.B_SIGNED(A_SIGNED),\n\t\t\t.A_WIDTH(B_WIDTH),\n\t\t\t.B_WIDTH(A_WIDTH),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(B),\n\t\t\t.B(A),\n\t\t\t.Y(Y)\n\t\t);\n\telse begin\n\t\twire [1023:0] _TECHMAP_DO_ = \"proc; clean\";\n\n`ifdef DSP_SIGNEDONLY\n\t\tlocalparam sign_headroom = 1;\n`else\n\t\tlocalparam sign_headroom = 0;\n`endif\n\n\t\tgenvar i;\n\t\tif (A_WIDTH > `DSP_A_MAXWIDTH) begin\n\t\t\tlocalparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);\n\t\t\tlocalparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;\n\t\t\tif (A_SIGNED && B_SIGNED) begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\t\t\telse begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\n\t\t\tfor (i = 0; i < n; i=i+1) begin:sliceA\n\t\t\t\t\\$__mul #(\n\t\t\t\t\t.A_SIGNED(sign_headroom),\n\t\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t\t.A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),\n\t\t\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t\t\t.Y_WIDTH(partial_Y_WIDTH)\n\t\t\t\t) mul (\n\t\t\t\t\t.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),\n\t\t\t\t\t.B(B),\n\t\t\t\t\t.Y(blk.partial[i])\n\t\t\t\t);\n\t\t\t\t// TODO: Currently a 'cascade' approach to summing the partial\n\t\t\t\t// products is taken here, but a more efficient 'binary\n\t\t\t\t// reduction' approach also exists...\n\t\t\t\tif (i == 0)\n\t\t\t\t\tassign blk.partial_sum[i] = blk.partial[i];\n\t\t\t\telse\n\t\t\t\t\tassign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\n\t\t\tend\n\n\t\t\t\\$__mul #(\n\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t.A_WIDTH(last_A_WIDTH),\n\t\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t\t.Y_WIDTH(last_Y_WIDTH)\n\t\t\t) sliceA.last (\n\t\t\t\t.A(A[A_WIDTH-1 -: last_A_WIDTH]),\n\t\t\t\t.B(B),\n\t\t\t\t.Y(blk.last_partial)\n\t\t\t);\n\t\t\tassign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\n\t\t\tassign Y = blk.partial_sum[n];\n\t\tend\n\t\telse if (B_WIDTH > `DSP_B_MAXWIDTH) begin\n\t\t\tlocalparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);\n\t\t\tlocalparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);\n\t\t\tlocalparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;\n\t\t\tif (A_SIGNED && B_SIGNED) begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire signed [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\t\t\telse begin : blk\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [partial_Y_WIDTH-1:0] partial [n-1:0];\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [last_Y_WIDTH-1:0] last_partial;\n\t\t\t\t(* force_downto *)\n\t\t\t\twire [Y_WIDTH-1:0] partial_sum [n:0];\n\t\t\tend\n\n\t\t\tfor (i = 0; i < n; i=i+1) begin:sliceB\n\t\t\t\t\\$__mul #(\n\t\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t\t.B_SIGNED(sign_headroom),\n\t\t\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t\t\t.B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),\n\t\t\t\t\t.Y_WIDTH(partial_Y_WIDTH)\n\t\t\t\t) mul (\n\t\t\t\t\t.A(A),\n\t\t\t\t\t.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),\n\t\t\t\t\t.Y(blk.partial[i])\n\t\t\t\t);\n\t\t\t\t// TODO: Currently a 'cascade' approach to summing the partial\n\t\t\t\t// products is taken here, but a more efficient 'binary\n\t\t\t\t// reduction' approach also exists...\n\t\t\t\tif (i == 0)\n\t\t\t\t\tassign blk.partial_sum[i] = blk.partial[i];\n\t\t\t\telse\n\t\t\t\t\tassign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];\n\t\t\tend\n\n\t\t\t\\$__mul #(\n\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t\t.B_WIDTH(last_B_WIDTH),\n\t\t\t\t.Y_WIDTH(last_Y_WIDTH)\n\t\t\t) mul_sliceB_last (\n\t\t\t\t.A(A),\n\t\t\t\t.B(B[B_WIDTH-1 -: last_B_WIDTH]),\n\t\t\t\t.Y(blk.last_partial)\n\t\t\t);\n\t\t\tassign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];\n\t\t\tassign Y = blk.partial_sum[n];\n\t\tend\n\t\telse begin\n\t\t\tif (A_SIGNED) begin : blkA\n\t\t\t\twire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);\n\t\t\tend\n\t\t\telse begin : blkA\n\t\t\t\twire [`DSP_A_MAXWIDTH-1:0] Aext = A;\n\t\t\tend\n\t\t\tif (B_SIGNED) begin : blkB\n\t\t\t\twire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);\n\t\t\tend\n\t\t\telse begin : blkB\n\t\t\t\twire [`DSP_B_MAXWIDTH-1:0] Bext = B;\n\t\t\tend\n\n\t\t\t`DSP_NAME #(\n\t\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t\t.A_WIDTH(`DSP_A_MAXWIDTH),\n\t\t\t\t.B_WIDTH(`DSP_B_MAXWIDTH),\n\t\t\t\t.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),\n\t\t\t) _TECHMAP_REPLACE_ (\n\t\t\t\t.A(blkA.Aext),\n\t\t\t\t.B(blkB.Bext),\n\t\t\t\t.Y(Y)\n\t\t\t);\n\t\tend\n\tend\n\tendgenerate\nendmodule\n\n(* techmap_celltype = \"$mul $__mul\" *)\nmodule _90_soft_mul (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t// Indirection necessary since mapping\n\t// back to $mul will cause recursion\n\tgenerate\n\tif (A_SIGNED && !B_SIGNED)\n\t\t\\$__soft_mul #(\n\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t.B_SIGNED(1),\n\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t.B_WIDTH(B_WIDTH+1),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(A),\n\t\t\t.B({1'b0,B}),\n\t\t\t.Y(Y)\n\t\t);\n\telse if (!A_SIGNED && B_SIGNED)\n\t\t\\$__soft_mul #(\n\t\t\t.A_SIGNED(1),\n\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t.A_WIDTH(A_WIDTH+1),\n\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A({1'b0,A}),\n\t\t\t.B(B),\n\t\t\t.Y(Y)\n\t\t);\n\telse\n\t\t\\$__soft_mul #(\n\t\t\t.A_SIGNED(A_SIGNED),\n\t\t\t.B_SIGNED(B_SIGNED),\n\t\t\t.A_WIDTH(A_WIDTH),\n\t\t\t.B_WIDTH(B_WIDTH),\n\t\t\t.Y_WIDTH(Y_WIDTH)\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(A),\n\t\t\t.B(B),\n\t\t\t.Y(Y)\n\t\t);\n\tendgenerate\nendmodule\n",
280
292
  "nexus": {
281
293
  "arith_map.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * Copyright (C) 2018 gatecat <gatecat@ds0.me>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_nexus_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 4;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\tfunction integer round_up2;\n\t\tinput integer N;\n\t\tbegin\n\t\t\tround_up2 = ((N + 1) / 2) * 2;\n\t\tend\n\tendfunction\n\n\tlocalparam Y_WIDTH2 = round_up2(Y_WIDTH);\n\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2-1:0] BX = B_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH2+1:0] FCO, Y1;\n\n\tgenvar i;\n\n\t// Carry feed-in\n\tCCU2 #(\n\t\t.INIT0(\"0xFFFF\"),\n\t\t.INIT1(\"0x00AA\"),\n\t\t.INJECT(\"NO\")\n\t) ccu2c_i (\n\t\t.A0(1'b1), .B0(1'b1), .C0(1'b1), .D0(1'b1),\n\t\t.A1(CI), .B1(1'b1), .C1(1'b1), .D1(1'b1),\n\t\t.COUT(FCO[0])\n\t);\n\n\tgenerate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice\n\t\tCCU2 #(\n\t\t\t.INIT0(\"0x96AA\"),\n\t\t\t.INIT1(\"0x96AA\"),\n\t\t\t.INJECT(\"NO\")\n\t\t) ccu2c_i (\n\t\t\t.CIN(FCO[i]),\n\t\t\t.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),\n\t\t\t.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),\n\t\t\t.S0(Y[i]), .S1(Y1[i]),\n\t\t\t.COUT(FCO[i+2])\n\t\t);\n\n\t\tassign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));\n\t\tif (i+1 < Y_WIDTH) begin\n\t\t\tassign CO[i + 1] = (AA[i + 1] && BB[i + 1]) || ((Y[i + 1] ^ AA[i + 1] ^ BB[i + 1]) && (AA[i + 1] || BB[i + 1]));\n\t\t\tassign Y[i+1] = Y1[i];\n\t\tend\n\tend endgenerate\n\n\tassign X = AA ^ BB;\nendmodule\n",