@yowasp/yosys 0.41.68-dev.720 → 0.42.733
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
package/gen/resources-yosys.js
CHANGED
|
@@ -233,21 +233,18 @@ export const filesystem = {
|
|
|
233
233
|
"abc9_model.v": "// This is a purely-synchronous flop, that ABC9 can use for sequential synthesis.\n(* abc9_flop, lib_whitebox *)\nmodule $__MISTRAL_FF_SYNCONLY (\n input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,\n output reg Q\n);\n\nMISTRAL_FF ff (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .ACLR(1'b1), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));\n\nendmodule\n",
|
|
234
234
|
"abc9_unmap.v": "// After performing sequential synthesis, map the synchronous flops back to\n// standard MISTRAL_FF flops.\n\nmodule $__MISTRAL_FF_SYNCONLY (\n input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,\n output reg Q\n);\n\nMISTRAL_FF _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ACLR(1'b1), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));\n\nendmodule\n",
|
|
235
235
|
"alm_map.v": "module \\$lut (A, Y);\n\nparameter WIDTH = 1;\nparameter LUT = 0;\n\n(* force_downto *)\ninput [WIDTH-1:0] A;\noutput Y;\n\ngenerate\n if (WIDTH == 1) begin\n generate\n if (LUT == 2'b00) begin\n assign Y = 1'b0;\n end\n else if (LUT == 2'b01) begin\n MISTRAL_NOT _TECHMAP_REPLACE_(\n .A(A[0]), .Q(Y)\n );\n end\n else if (LUT == 2'b10) begin\n assign Y = A;\n end\n else if (LUT == 2'b11) begin\n assign Y = 1'b1;\n end\n endgenerate\n end else\n if (WIDTH == 2) begin\n MISTRAL_ALUT2 #(.LUT(LUT)) _TECHMAP_REPLACE_(\n .A(A[0]), .B(A[1]), .Q(Y)\n );\n end else\n if (WIDTH == 3) begin\n MISTRAL_ALUT3 #(.LUT(LUT)) _TECHMAP_REPLACE_(\n .A(A[0]), .B(A[1]), .C(A[2]), .Q(Y)\n );\n end else\n if (WIDTH == 4) begin\n MISTRAL_ALUT4 #(.LUT(LUT)) _TECHMAP_REPLACE_(\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .Q(Y)\n );\n end else\n if (WIDTH == 5) begin\n MISTRAL_ALUT5 #(.LUT(LUT)) _TECHMAP_REPLACE_ (\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .Q(Y)\n );\n end else\n if (WIDTH == 6) begin\n MISTRAL_ALUT6 #(.LUT(LUT)) _TECHMAP_REPLACE_ (\n .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .Q(Y)\n );\n end else begin\n wire _TECHMAP_FAIL_ = 1'b1;\n end\nendgenerate\nendmodule\n",
|
|
236
|
-
"alm_sim.v": "// The core logic primitive of the Cyclone V/10GX is the Adaptive Logic Module\n// (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered\n// in this file, connected to combinational outputs, a carry chain, and four\n// D flip-flops (which are covered as MISTRAL_FF in dff_sim.v).\n//\n// The ALM is vertically symmetric, so I find it helps to think in terms of\n// half-ALMs, as that's predominantly the unit that synth_intel_alm uses.\n//\n// ALMs are quite flexible, having multiple modes.\n//\n// Normal (combinational) mode\n// ---------------------------\n// The ALM can implement:\n// - a single 6-input function (with the other inputs usable for flip-flop access)\n// - two 5-input functions that share two inputs\n// - a 5-input and a 4-input function that share one input\n// - a 5-input and a 3-or-less-input function that share no inputs\n// - two 4-or-less-input functions that share no inputs\n//\n// Normal-mode functions are represented as MISTRAL_ALUTN cells with N inputs.\n// It would be possible to represent a normal mode function as a single cell -\n// the vendor cyclone{v,10gx}_lcell_comb cell does exactly that - but I felt\n// it was more user-friendly to print out the specific function sizes\n// separately.\n//\n// With the exception of MISTRAL_ALUT6, you can think of two normal-mode cells\n// fitting inside a single ALM.\n//\n// Extended (7-input) mode\n// -----------------------\n// The ALM can also fit a 7-input function made of two 5-input functions that\n// share four inputs, multiplexed by another input.\n//\n// Because this can't accept arbitrary 7-input functions, Yosys can't handle\n// it, so it doesn't have a cell, but I would likely call it MISTRAL_ALUT7(E?)\n// if it did, and it would take up a full ALM.\n//\n// It might be possible to add an extraction pass to examine all ALUT5 cells\n// that feed into ALUT3 cells to see if they can be combined into an extended\n// ALM, but I don't think it will be worth it.\n//\n// Arithmetic mode\n// ---------------\n// In arithmetic mode, each half-ALM uses its carry chain to perform fast addition\n// of two four-input functions that share three inputs. Oddly, the result of\n// one of the functions is inverted before being added (you can see this as\n// the dot on a full-adder input of Figure 1-8 in the Handbook).\n//\n// The cell for an arithmetic-mode half-ALM is MISTRAL_ALM_ARITH. One idea\n// I've had (or rather was suggested by mwk) is that functions that feed into\n// arithmetic-mode cells could be packed directly into the arithmetic-mode\n// cell as a function, which reduces the number of ALMs needed.\n//\n// Shared arithmetic mode\n// ----------------------\n// Shared arithmetic mode looks a lot like arithmetic mode, but here the\n// output of every other four-input function goes to the input of the adder\n// the next bit along. What this means is that adding three bits together can\n// be done in an ALM, because functions can be used to implement addition that\n// then feeds into the carry chain. This means that three bits can be added per\n// ALM, as opposed to two in the arithmetic mode.\n//\n// Shared arithmetic mode doesn't currently have a cell, but I intend to add\n// it as MISTRAL_ALM_SHARED, and have it occupy a full ALM. Because it adds\n// three bits per cell, it makes addition shorter and use less ALMs, but\n// I don't know enough to tell whether it's more efficient to use shared\n// arithmetic mode to shorten the carry chain, or plain arithmetic mode with\n// the functions packed in.\n\n`default_nettype none\n\n// Cyclone V LUT output timings (picoseconds):\n//\n// CARRY A B C D E F G\n// COMBOUT - 605 583 510 512 - 97 400 (LUT6)\n// COMBOUT - 602 583 457 510 302 93 483 (LUT7)\n// SUMOUT 368 1342 1323 887 927 - 785 -\n// CARRYOUT 71 1082 1062 866 813 - 1198 -\n\n// Arria V LUT output timings (picoseconds):\n//\n// CARRY A B C D E F G\n// COMBOUT - 387 375 316 317 - 76 319 (LUT6)\n// COMBOUT - 387 375 316 317 218 76 319 (LUT7)\n// SUMOUT 249 744 732 562 576 - 511 -\n// CARRYOUT 19 629 623 530 514 - 696 -\n\n(* abc9_lut=2, lib_whitebox *)\nmodule MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);\n\nparameter [63:0] LUT = 64'h0000_0000_0000_0000;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 605;\n (B => Q) = 583;\n (C => Q) = 510;\n (D => Q) = 512;\n (E => Q) = 400;\n (F => Q) = 97;\nendspecify\n`endif\n`ifdef arriav\nspecify\n (A => Q) = 387;\n (B => Q) = 375;\n (C => Q) = 316;\n (D => Q) = 317;\n (E => Q) = 319;\n (F => Q) = 76;\nendspecify\n`endif\n`ifdef cyclone10gx\nspecify\n (A => Q) = 275;\n (B => Q) = 272;\n (C => Q) = 175;\n (D => Q) = 165;\n (E => Q) = 162;\n (F => Q) = 53;\nendspecify\n`endif\n\nassign Q = LUT >> {F, E, D, C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT5(input A, B, C, D, E, output Q);\n\nparameter [31:0] LUT = 32'h0000_0000;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 583;\n (B => Q) = 510;\n (C => Q) = 512;\n (D => Q) = 400;\n (E => Q) = 97;\nendspecify\n`endif\n`ifdef arriav\nspecify\n (A => Q) = 375;\n (B => Q) = 316;\n (C => Q) = 317;\n (D => Q) = 319;\n (E => Q) = 76;\nendspecify\n`endif\n`ifdef cyclone10gx\nspecify\n (A => Q) = 272;\n (B => Q) = 175;\n (C => Q) = 165;\n (D => Q) = 162;\n (E => Q) = 53;\nendspecify\n`endif\n\nassign Q = LUT >> {E, D, C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT4(input A, B, C, D, output Q);\n\nparameter [15:0] LUT = 16'h0000;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 510;\n (B => Q) = 512;\n (C => Q) = 400;\n (D => Q) = 97;\nendspecify\n`endif\n`ifdef arriav\nspecify\n (A => Q) = 316;\n (B => Q) = 317;\n (C => Q) = 319;\n (D => Q) = 76;\nendspecify\n`endif\n`ifdef cyclone10gx\nspecify\n (A => Q) = 175;\n (B => Q) = 165;\n (C => Q) = 162;\n (D => Q) = 53;\nendspecify\n`endif\n\nassign Q = LUT >> {D, C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT3(input A, B, C, output Q);\n\nparameter [7:0] LUT = 8'h00;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 510;\n (B => Q) = 400;\n (C => Q) = 97;\nendspecify\n`endif\n`ifdef arriav\nspecify\n (A => Q) = 316;\n (B => Q) = 317;\n (C => Q) = 76;\nendspecify\n`endif\n`ifdef cyclone10gx\nspecify\n (A => Q) = 165;\n (B => Q) = 162;\n (C => Q) = 53;\nendspecify\n`endif\n\nassign Q = LUT >> {C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT2(input A, B, output Q);\n\nparameter [3:0] LUT = 4'h0;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 400;\n (B => Q) = 97;\nendspecify\n`endif\n`ifdef arriav\nspecify\n (A => Q) = 316;\n (B => Q) = 76;\nendspecify\n`endif\n`ifdef cyclone10gx\nspecify\n (A => Q) = 162;\n (B => Q) = 53;\nendspecify\n`endif\n\nassign Q = LUT >> {B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_NOT(input A, output Q);\n\n`ifdef cyclonev\nspecify\n (A => Q) = 97;\nendspecify\n`endif\n`ifdef arriav\nspecify\n (A => Q) = 76;\nendspecify\n`endif\n`ifdef cyclone10gx\nspecify\n (A => Q) = 53;\nendspecify\n`endif\n\nassign Q = ~A;\n\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);\n\nparameter LUT0 = 16'h0000;\nparameter LUT1 = 16'h0000;\n\n`ifdef cyclonev\nspecify\n (A => SO) = 1342;\n (B => SO) = 1323;\n (C => SO) = 927;\n (D0 => SO) = 887;\n (D1 => SO) = 785;\n (CI => SO) = 368;\n\n (A => CO) = 1082;\n (B => CO) = 1062;\n (C => CO) = 813;\n (D0 => CO) = 866;\n (D1 => CO) = 1198;\n (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)\nendspecify\n`endif\n`ifdef arriav\nspecify\n (A => SO) = 744;\n (B => SO) = 732;\n (C => SO) = 562;\n (D0 => SO) = 576;\n (D1 => SO) = 511;\n (CI => SO) = 249;\n\n (A => CO) = 629;\n (B => CO) = 623;\n (C => CO) = 530;\n (D0 => CO) = 514;\n (D1 => CO) = 696;\n (CI => CO) = 10; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)\nendspecify\n`endif\n`ifdef cyclone10gx\nspecify\n (A => SO) = 644;\n (B => SO) = 477;\n (C => SO) = 416;\n (D0 => SO) = 380;\n (D1 => SO) = 431;\n (CI => SO) = 276;\n\n (A => CO) = 525;\n (B => CO) = 433;\n (C => CO) = 712;\n (D0 => CO) = 653;\n (D1 => CO) = 593;\n (CI => CO) = 16;\nendspecify\n`endif\n\nwire q0, q1;\n\nassign q0 = LUT0 >> {D0, C, B, A};\nassign q1 = LUT1 >> {D1, C, B, A};\n\nassign {CO, SO} = q0 + !q1 + CI;\n\nendmodule\n\n\n/*\n// A, B, C0, C1, E0, E1, F0, F1: data inputs\n// CARRYIN: carry input\n// SHAREIN: shared-arithmetic input\n// CLK0, CLK1, CLK2: clock inputs\n//\n// COMB0, COMB1: combinational outputs\n// FF0, FF1, FF2, FF3: DFF outputs\n// SUM0, SUM1: adder outputs\n// CARRYOUT: carry output\n// SHAREOUT: shared-arithmetic output\nmodule MISTRAL_ALM(\n input A, B, C0, C1, E0, E1, F0, F1, CARRYIN, SHAREIN, // LUT path\n input CLK0, CLK1, CLK2, AC0, AC1, // FF path\n output COMB0, COMB1, SUM0, SUM1, CARRYOUT, SHAREOUT,\n output FF0, FF1, FF2, FF3\n);\n\nparameter LUT0 = 16'b0000;\nparameter LUT1 = 16'b0000;\nparameter LUT2 = 16'b0000;\nparameter LUT3 = 16'b0000;\n\nparameter INIT0 = 1'b0;\nparameter INIT1 = 1'b0;\nparameter INIT2 = 1'b0;\nparameter INIT3 = 1'b0;\n\nparameter C0_MUX = \"C0\";\nparameter C1_MUX = \"C1\";\n\nparameter F0_MUX = \"VCC\";\nparameter F1_MUX = \"GND\";\n\nparameter FEEDBACK0 = \"FF0\";\nparameter FEEDBACK1 = \"FF2\";\n\nparameter ADD_MUX = \"LUT\";\n\nparameter DFF01_DATA_MUX = \"COMB\";\nparameter DFF23_DATA_MUX = \"COMB\";\n\nparameter DFF0_CLK = \"CLK0\";\nparameter DFF1_CLK = \"CLK0\";\nparameter DFF2_CLK = \"CLK0\";\nparameter DFF3_CLK = \"CLK0\";\n\nparameter DFF0_AC = \"AC0\";\nparameter DFF1_AC = \"AC0\";\nparameter DFF2_AC = \"AC0\";\nparameter DFF3_AC = \"AC0\";\n\n// Feedback muxes from the flip-flop outputs.\nwire ff_feedback_mux0, ff_feedback_mux1;\n\n// C-input muxes which can be set to also use the F-input.\nwire c0_input_mux, c1_input_mux;\n\n// F-input muxes which can be set to a constant to allow LUT5 use.\nwire f0_input_mux, f1_input_mux;\n\n// Adder input muxes to select between shared-arithmetic mode and arithmetic mode.\nwire add0_input_mux, add1_input_mux;\n\n// Combinational-output muxes for LUT #1 and LUT #3\nwire lut1_comb_mux, lut3_comb_mux;\n\n// Sum-output muxes for LUT #1 and LUT #3\nwire lut1_sum_mux, lut3_sum_mux;\n\n// DFF data-input muxes\nwire dff01_data_mux, dff23_data_mux;\n\n// DFF clock selectors\nwire dff0_clk, dff1_clk, dff2_clk, dff3_clk;\n\n// DFF asynchronous-clear selectors\nwire dff0_ac, dff1_ac, dff2_ac, dff3_ac;\n\n// LUT, DFF and adder output wires for routing.\nwire lut0_out, lut1a_out, lut1b_out, lut2_out, lut3a_out, lut3b_out;\nwire dff0_out, dff1_out, dff2_out, dff3_out;\nwire add0_sum, add1_sum, add0_carry, add1_carry;\n\ngenerate\n if (FEEDBACK0 === \"FF0\")\n assign ff_feedback_mux0 = dff0_out;\n else if (FEEDBACK0 === \"FF1\")\n assign ff_feedback_mux0 = dff1_out;\n else\n $error(\"Invalid FEEDBACK0 setting!\");\n\n if (FEEDBACK1 == \"FF2\")\n assign ff_feedback_mux1 = dff2_out;\n else if (FEEDBACK1 == \"FF3\")\n assign ff_feedback_mux1 = dff3_out;\n else\n $error(\"Invalid FEEDBACK1 setting!\");\n\n if (C0_MUX === \"C0\")\n assign c0_input_mux = C0;\n else if (C0_MUX === \"F1\")\n assign c0_input_mux = F1;\n else if (C0_MUX === \"FEEDBACK1\")\n assign c0_input_mux = ff_feedback_mux1;\n else\n $error(\"Invalid C0_MUX setting!\");\n\n if (C1_MUX === \"C1\")\n assign c1_input_mux = C1;\n else if (C1_MUX === \"F0\")\n assign c1_input_mux = F0;\n else if (C1_MUX === \"FEEDBACK0\")\n assign c1_input_mux = ff_feedback_mux0;\n else\n $error(\"Invalid C1_MUX setting!\");\n\n // F0 == VCC is LUT5\n // F0 == F0 is LUT6\n // F0 == FEEDBACK is unknown\n if (F0_MUX === \"VCC\")\n assign f0_input_mux = 1'b1;\n else if (F0_MUX === \"F0\")\n assign f0_input_mux = F0;\n else if (F0_MUX === \"FEEDBACK0\")\n assign f0_input_mux = ff_feedback_mux0;\n else\n $error(\"Invalid F0_MUX setting!\");\n\n // F1 == GND is LUT5\n // F1 == F1 is LUT6\n // F1 == FEEDBACK is unknown\n if (F1_MUX === \"GND\")\n assign f1_input_mux = 1'b0;\n else if (F1_MUX === \"F1\")\n assign f1_input_mux = F1;\n else if (F1_MUX === \"FEEDBACK1\")\n assign f1_input_mux = ff_feedback_mux1;\n else\n $error(\"Invalid F1_MUX setting!\");\n\n if (ADD_MUX === \"LUT\") begin\n assign add0_input_mux = ~lut1_sum_mux;\n assign add1_input_mux = ~lut3_sum_mux;\n end else if (ADD_MUX === \"SHARE\") begin\n assign add0_input_mux = SHAREIN;\n assign add1_input_mux = lut1_comb_mux;\n end else\n $error(\"Invalid ADD_MUX setting!\");\n\n if (DFF01_DATA_MUX === \"COMB\")\n assign dff01_data_mux = COMB0;\n else if (DFF01_DATA_MUX === \"SUM\")\n assign dff01_data_mux = SUM0;\n else\n $error(\"Invalid DFF01_DATA_MUX setting!\");\n\n if (DFF23_DATA_MUX === \"COMB\")\n assign dff23_data_mux = COMB0;\n else if (DFF23_DATA_MUX === \"SUM\")\n assign dff23_data_mux = SUM0;\n else\n $error(\"Invalid DFF23_DATA_MUX setting!\");\n\n if (DFF0_CLK === \"CLK0\")\n assign dff0_clk = CLK0;\n else if (DFF0_CLK === \"CLK1\")\n assign dff0_clk = CLK1;\n else if (DFF0_CLK === \"CLK2\")\n assign dff0_clk = CLK2;\n else\n $error(\"Invalid DFF0_CLK setting!\");\n\n if (DFF1_CLK === \"CLK0\")\n assign dff1_clk = CLK0;\n else if (DFF1_CLK === \"CLK1\")\n assign dff1_clk = CLK1;\n else if (DFF1_CLK === \"CLK2\")\n assign dff1_clk = CLK2;\n else\n $error(\"Invalid DFF1_CLK setting!\");\n\n if (DFF2_CLK === \"CLK0\")\n assign dff2_clk = CLK0;\n else if (DFF2_CLK === \"CLK1\")\n assign dff2_clk = CLK1;\n else if (DFF2_CLK === \"CLK2\")\n assign dff2_clk = CLK2;\n else\n $error(\"Invalid DFF2_CLK setting!\");\n\n if (DFF3_CLK === \"CLK0\")\n assign dff3_clk = CLK0;\n else if (DFF3_CLK === \"CLK1\")\n assign dff3_clk = CLK1;\n else if (DFF3_CLK === \"CLK2\")\n assign dff3_clk = CLK2;\n else\n $error(\"Invalid DFF3_CLK setting!\");\n\n if (DFF0_AC === \"AC0\")\n assign dff0_ac = AC0;\n else if (DFF0_AC === \"AC1\")\n assign dff0_ac = AC1;\n else\n $error(\"Invalid DFF0_AC setting!\");\n\n if (DFF1_AC === \"AC0\")\n assign dff1_ac = AC0;\n else if (DFF1_AC === \"AC1\")\n assign dff1_ac = AC1;\n else\n $error(\"Invalid DFF1_AC setting!\");\n\n if (DFF2_AC === \"AC0\")\n assign dff2_ac = AC0;\n else if (DFF2_AC === \"AC1\")\n assign dff2_ac = AC1;\n else\n $error(\"Invalid DFF2_AC setting!\");\n\n if (DFF3_AC === \"AC0\")\n assign dff3_ac = AC0;\n else if (DFF3_AC === \"AC1\")\n assign dff3_ac = AC1;\n else\n $error(\"Invalid DFF3_AC setting!\");\n\nendgenerate\n\n// F0 on the Quartus diagram\nMISTRAL_ALUT4 #(.LUT(LUT0)) lut0 (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut0_out));\n\n// F2 on the Quartus diagram\nMISTRAL_ALUT4 #(.LUT(LUT1)) lut1_comb (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut1_comb_mux));\nMISTRAL_ALUT4 #(.LUT(LUT1)) lut1_sum (.A(A), .B(B), .C(C0), .D(E0), .Q(lut1_sum_mux));\n\n// F1 on the Quartus diagram\nMISTRAL_ALUT4 #(.LUT(LUT2)) lut2 (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut2_out));\n\n// F3 on the Quartus diagram\nMISTRAL_ALUT4 #(.LUT(LUT3)) lut3_comb (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut3_comb_mux));\nMISTRAL_ALUT4 #(.LUT(LUT3)) lut3_sum (.A(A), .B(B), .C(C1), .D(E1), .Q(lut3_sum_mux));\n\nMISTRAL_FF #(.INIT(INIT0)) dff0 (.D(dff01_data_mux), .CLK(dff0_clk), .ACn(dff0_ac), .Q(dff0_out));\nMISTRAL_FF #(.INIT(INIT1)) dff1 (.D(dff01_data_mux), .CLK(dff1_clk), .ACn(dff1_ac), .Q(dff1_out));\nMISTRAL_FF #(.INIT(INIT2)) dff2 (.D(dff23_data_mux), .CLK(dff2_clk), .ACn(dff2_ac), .Q(dff2_out));\nMISTRAL_FF #(.INIT(INIT3)) dff3 (.D(dff23_data_mux), .CLK(dff3_clk), .ACn(dff3_ac), .Q(dff3_out));\n\n// Adders\nassign {add0_carry, add0_sum} = CARRYIN + lut0_out + lut1_sum_mux;\nassign {add1_carry, add1_sum} = add0_carry + lut2_out + lut3_sum_mux;\n\n// COMBOUT outputs on the Quartus diagram\nassign COMB0 = E0 ? (f0_input_mux ? lut3_comb_mux : lut1_comb_mux)\n : (f0_input_mux ? lut2_out : lut0_out);\n\nassign COMB1 = E1 ? (f1_input_mux ? lut3_comb_mux : lut1_comb_mux)\n : (f1_input_mux ? lut2_out : lut0_out);\n\n// SUMOUT output on the Quartus diagram\nassign SUM0 = add0_sum;\nassign SUM1 = add1_sum;\n\n// COUT output on the Quartus diagram\nassign CARRYOUT = add1_carry;\n\n// SHAREOUT output on the Quartus diagram\nassign SHAREOUT = lut3_comb_mux;\n\n// REGOUT outputs on the Quartus diagram\nassign FF0 = dff0_out;\nassign FF1 = dff1_out;\nassign FF2 = dff2_out;\nassign FF3 = dff3_out;\n\nendmodule\n*/\n",
|
|
236
|
+
"alm_sim.v": "// The core logic primitive of the Cyclone V is the Adaptive Logic Module\n// (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered\n// in this file, connected to combinational outputs, a carry chain, and four\n// D flip-flops (which are covered as MISTRAL_FF in dff_sim.v).\n//\n// The ALM is vertically symmetric, so I find it helps to think in terms of\n// half-ALMs, as that's predominantly the unit that synth_intel_alm uses.\n//\n// ALMs are quite flexible, having multiple modes.\n//\n// Normal (combinational) mode\n// ---------------------------\n// The ALM can implement:\n// - a single 6-input function (with the other inputs usable for flip-flop access)\n// - two 5-input functions that share two inputs\n// - a 5-input and a 4-input function that share one input\n// - a 5-input and a 3-or-less-input function that share no inputs\n// - two 4-or-less-input functions that share no inputs\n//\n// Normal-mode functions are represented as MISTRAL_ALUTN cells with N inputs.\n// It would be possible to represent a normal mode function as a single cell -\n// the vendor cyclone{v,10gx}_lcell_comb cell does exactly that - but I felt\n// it was more user-friendly to print out the specific function sizes\n// separately.\n//\n// With the exception of MISTRAL_ALUT6, you can think of two normal-mode cells\n// fitting inside a single ALM.\n//\n// Extended (7-input) mode\n// -----------------------\n// The ALM can also fit a 7-input function made of two 5-input functions that\n// share four inputs, multiplexed by another input.\n//\n// Because this can't accept arbitrary 7-input functions, Yosys can't handle\n// it, so it doesn't have a cell, but I would likely call it MISTRAL_ALUT7(E?)\n// if it did, and it would take up a full ALM.\n//\n// It might be possible to add an extraction pass to examine all ALUT5 cells\n// that feed into ALUT3 cells to see if they can be combined into an extended\n// ALM, but I don't think it will be worth it.\n//\n// Arithmetic mode\n// ---------------\n// In arithmetic mode, each half-ALM uses its carry chain to perform fast addition\n// of two four-input functions that share three inputs. Oddly, the result of\n// one of the functions is inverted before being added (you can see this as\n// the dot on a full-adder input of Figure 1-8 in the Handbook).\n//\n// The cell for an arithmetic-mode half-ALM is MISTRAL_ALM_ARITH. One idea\n// I've had (or rather was suggested by mwk) is that functions that feed into\n// arithmetic-mode cells could be packed directly into the arithmetic-mode\n// cell as a function, which reduces the number of ALMs needed.\n//\n// Shared arithmetic mode\n// ----------------------\n// Shared arithmetic mode looks a lot like arithmetic mode, but here the\n// output of every other four-input function goes to the input of the adder\n// the next bit along. What this means is that adding three bits together can\n// be done in an ALM, because functions can be used to implement addition that\n// then feeds into the carry chain. This means that three bits can be added per\n// ALM, as opposed to two in the arithmetic mode.\n//\n// Shared arithmetic mode doesn't currently have a cell, but I intend to add\n// it as MISTRAL_ALM_SHARED, and have it occupy a full ALM. Because it adds\n// three bits per cell, it makes addition shorter and use less ALMs, but\n// I don't know enough to tell whether it's more efficient to use shared\n// arithmetic mode to shorten the carry chain, or plain arithmetic mode with\n// the functions packed in.\n\n`default_nettype none\n\n// Cyclone V LUT output timings (picoseconds):\n//\n// CARRY A B C D E F G\n// COMBOUT - 605 583 510 512 - 97 400 (LUT6)\n// COMBOUT - 602 583 457 510 302 93 483 (LUT7)\n// SUMOUT 368 1342 1323 887 927 - 785 -\n// CARRYOUT 71 1082 1062 866 813 - 1198 -\n\n(* abc9_lut=2, lib_whitebox *)\nmodule MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);\n\nparameter [63:0] LUT = 64'h0000_0000_0000_0000;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 605;\n (B => Q) = 583;\n (C => Q) = 510;\n (D => Q) = 512;\n (E => Q) = 400;\n (F => Q) = 97;\nendspecify\n`endif\n\nassign Q = LUT >> {F, E, D, C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT5(input A, B, C, D, E, output Q);\n\nparameter [31:0] LUT = 32'h0000_0000;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 583;\n (B => Q) = 510;\n (C => Q) = 512;\n (D => Q) = 400;\n (E => Q) = 97;\nendspecify\n`endif\n\nassign Q = LUT >> {E, D, C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT4(input A, B, C, D, output Q);\n\nparameter [15:0] LUT = 16'h0000;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 510;\n (B => Q) = 512;\n (C => Q) = 400;\n (D => Q) = 97;\nendspecify\n`endif\n\nassign Q = LUT >> {D, C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT3(input A, B, C, output Q);\n\nparameter [7:0] LUT = 8'h00;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 510;\n (B => Q) = 400;\n (C => Q) = 97;\nendspecify\n`endif\n\nassign Q = LUT >> {C, B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_ALUT2(input A, B, output Q);\n\nparameter [3:0] LUT = 4'h0;\n\n`ifdef cyclonev\nspecify\n (A => Q) = 400;\n (B => Q) = 97;\nendspecify\n`endif\n\nassign Q = LUT >> {B, A};\n\nendmodule\n\n\n(* abc9_lut=1, lib_whitebox *)\nmodule MISTRAL_NOT(input A, output Q);\n\n`ifdef cyclonev\nspecify\n (A => Q) = 97;\nendspecify\n`endif\n\nassign Q = ~A;\n\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);\n\nparameter LUT0 = 16'h0000;\nparameter LUT1 = 16'h0000;\n\n`ifdef cyclonev\nspecify\n (A => SO) = 1342;\n (B => SO) = 1323;\n (C => SO) = 927;\n (D0 => SO) = 887;\n (D1 => SO) = 785;\n (CI => SO) = 368;\n\n (A => CO) = 1082;\n (B => CO) = 1062;\n (C => CO) = 813;\n (D0 => CO) = 866;\n (D1 => CO) = 1198;\n (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)\nendspecify\n`endif\n\nwire q0, q1;\n\nassign q0 = LUT0 >> {D0, C, B, A};\nassign q1 = LUT1 >> {D1, C, B, A};\n\nassign {CO, SO} = q0 + !q1 + CI;\n\nendmodule\n",
|
|
237
237
|
"arith_alm_map.v": "`default_nettype none\n\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\nparameter _TECHMAP_CONSTMSK_CI_ = 0;\nparameter _TECHMAP_CONSTVAL_CI_ = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\ninput CI, BI;\n(* force_downto *)\noutput [Y_WIDTH-1:0] X, Y, CO;\n\n(* force_downto *)\nwire [Y_WIDTH-1:0] A_buf, B_buf;\n\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n(* force_downto *)\nwire [Y_WIDTH-1:0] AA = A_buf;\n(* force_downto *)\nwire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n(* force_downto *)\nwire [Y_WIDTH-1:0] BX = B_buf;\nwire [Y_WIDTH:0] ALM_CARRY;\n\n// Start of carry chain\ngenerate\n if (_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 1'b0) begin\n assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;\n end else begin\n MISTRAL_ALUT_ARITH #(\n .LUT0(16'b1010_1010_1010_1010), // Q = A\n .LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)\n ) alm_start (\n .A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),\n .CI(1'b0),\n .CO(ALM_CARRY[0])\n );\n end\nendgenerate\n\n// Carry chain\ngenvar i;\ngenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n // TODO: mwk suggests that a pass could merge pre-adder logic into this.\n MISTRAL_ALUT_ARITH #(\n .LUT0(16'b1010_1010_1010_1010), // Q = A\n .LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)\n ) alm_i (\n .A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1),\n .CI(ALM_CARRY[i]),\n .SO(Y[i]),\n .CO(ALM_CARRY[i+1])\n );\n\n // ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.\n assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));\nend endgenerate\n\nassign X = AA ^ BB;\n\nendmodule\n",
|
|
238
238
|
"bram_m10k.txt": "bram $__MISTRAL_M10K\n init 1\n abits 13 @D8192x1\n dbits 1 @D8192x1\n abits 12 @D4096x2\n dbits 2 @D4096x2\n abits 11 @D2048x5\n dbits 5 @D2048x5\n abits 10 @D1024x10\n dbits 10 @D1024x10\n abits 9 @D512x20\n dbits 20 @D512x20\n abits 8 @D256x40\n dbits 40 @D256x40\n groups 2\n ports 1 1\n wrmode 1 0\n # read enable; write enable + byte enables (only for multiples of 8)\n enable 1 1\n transp 0 0\n clocks 1 1\n clkpol 1 1\nendbram\n\n\nmatch $__MISTRAL_M10K\n min efficiency 5\n make_transp\nendmatch\n",
|
|
239
239
|
"bram_m10k_map.v": "// Stub to invert M10K write-enable.\n\nmodule \\$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n\nparameter INIT = 0;\n\nparameter CFG_ABITS = 10;\nparameter CFG_DBITS = 10;\n\ninput CLK1;\ninput [CFG_ABITS-1:0] A1ADDR, B1ADDR;\ninput [CFG_DBITS-1:0] A1DATA;\ninput A1EN, B1EN;\noutput reg [CFG_DBITS-1:0] B1DATA;\n\n// Normal M10K configs use WREN[1], which is negative-true.\n// However, 8x40-bit mode uses WREN[0], which is positive-true.\nwire a1en;\nif (CFG_DBITS == 40)\n assign a1en = A1EN;\nelse\n assign a1en = !A1EN;\n\nMISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(a1en), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));\n\nendmodule\n",
|
|
240
|
-
"bram_m20k.txt": "bram __MISTRAL_M20K_SDP\n init 1 # TODO: Re-enable when I figure out how BRAM init works\n abits 14 @D16384x1\n dbits 1 @D16384x1\n abits 13 @D8192x2\n dbits 2 @D8192x2\n abits 12 @D4096x4 @D4096x5\n dbits 4 @D4096x4\n dbits 5 @D4096x5\n abits 11 @D2048x8 @D2048x10\n dbits 8 @D2048x8\n dbits 10 @D2048x10\n abits 10 @D1024x16 @D1024x20\n dbits 16 @D1024x16\n dbits 20 @D1024x20\n abits 9 @D512x32 @D512x40\n dbits 32 @D512x32\n dbits 40 @D512x40\n groups 2\n ports 1 1\n wrmode 1 0\n # read enable; write enable + byte enables (only for multiples of 8)\n enable 1 1\n transp 0 0\n clocks 1 1\n clkpol 1 1\nendbram\n\n\nmatch __MISTRAL_M20K_SDP\n min efficiency 5\n make_transp\nendmatch\n",
|
|
241
|
-
"bram_m20k_map.v": "module __MISTRAL_M20K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n\nparameter CFG_ABITS = 10;\nparameter CFG_DBITS = 20;\nparameter CFG_ENABLE_A = 1;\nparameter CFG_ENABLE_B = 1;\n\ninput CLK1;\ninput [CFG_ABITS-1:0] A1ADDR, B1ADDR;\ninput [CFG_DBITS-1:0] A1DATA;\noutput [CFG_DBITS-1:0] B1DATA;\ninput [CFG_ENABLE_A-1:0] A1EN, B1EN;\n\naltsyncram #(\n .operation_mode(\"dual_port\"),\n .ram_block_type(\"m20k\"),\n .widthad_a(CFG_ABITS),\n .width_a(CFG_DBITS),\n .widthad_b(CFG_ABITS),\n .width_b(CFG_DBITS),\n) _TECHMAP_REPLACE_ (\n .address_a(A1ADDR),\n .data_a(A1DATA),\n .wren_a(A1EN),\n .address_b(B1ADDR),\n .q_b(B1DATA),\n .clock0(CLK1),\n .clock1(CLK1)\n);\n\nendmodule\n",
|
|
242
240
|
"dff_map.v": "`default_nettype none\n\n// D flip-flop with async reset and enable\nmodule \\$_DFFE_PN0P_ (input D, C, R, E, output Q);\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(R), .ENA(E), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));\nendmodule\n\n// D flip-flop with sync reset and enable (enable has priority)\nmodule \\$_SDFFCE_PP0P_ (input D, C, R, E, output Q);\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(1'b1), .ENA(E), .SCLR(R), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));\nendmodule\n",
|
|
243
|
-
"dff_sim.v": "// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM)\n// act as one-bit memory cells that can be placed very flexibly (wherever there's\n// an ALM); each flop is represented by a MISTRAL_FF cell.\n//\n// The flops in these chips are rather flexible in some ways, but in practice\n// quite crippled by FPGA standards.\n//\n// What the flops can do\n// ---------------------\n// The core flop acts as a single-bit memory that initialises to zero at chip\n// reset. It takes in data on the rising edge of CLK if ENA is high,\n// and outputs it to Q. The ENA (clock enable) pin can therefore be used to\n// capture the input only if a condition is true.\n//\n// The data itself is zero if SCLR (synchronous clear) is high, else it comes\n// from SDATA (synchronous data) if SLOAD (synchronous load) is high, or DATAIN\n// if SLOAD is low.\n//\n// If ACLR (asynchronous clear) is low then Q is forced to zero, regardless of\n// the synchronous inputs or CLK edge. This is most often used for an FPGA-wide\n// power-on reset.\n//\n// An asynchronous set that sets Q to one can be emulated by inverting the input\n// and output of the flop, resulting in ACLR forcing Q to zero, which then gets\n// inverted to produce one. Likewise, logic can operate on the falling edge of\n// CLK if CLK is inverted before being passed as an input.\n//\n// What the flops *can't* do\n// -------------------------\n// The trickiest part of the above capabilities is the lack of configurable\n// initialisation state. For example, it isn't possible to implement a flop with\n// asynchronous clear that initialises to one, because the hardware initialises\n// to zero. Likewise, you can't emulate a flop with asynchronous set that\n// initialises to zero, because the inverters mean the flop initialises to one.\n//\n// If the input design requires one of these cells (which appears to be rare\n// in practice) then synth_intel_alm will fail to synthesize the design where\n// other Yosys synthesis scripts might succeed.\n//\n// This stands in notable contrast to e.g. Xilinx flip-flops, which have\n// configurable initialisation state and native synchronous/asynchronous\n// set/clear (although not at the same time), which means they can generally\n// implement a much wider variety of logic.\n\n// DATAIN: synchronous data input\n// CLK: clock input (positive edge)\n// ACLR: asynchronous clear (negative-true)\n// ENA: clock-enable\n// SCLR: synchronous clear\n// SLOAD: synchronous load\n// SDATA: synchronous load data\n//\n// Q: data output\n//\n// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.\n\n(* abc9_box, lib_whitebox *)\nmodule MISTRAL_FF(\n input DATAIN,\n (* clkbuf_sink *) input CLK,\n input ACLR, ENA, SCLR, SLOAD, SDATA,\n output reg Q\n);\n\n`ifdef cyclonev\nspecify\n if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;\n if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;\n if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;\n\n $setup(DATAIN, posedge CLK, /* -196 */ 0);\n $setup(ENA, posedge CLK, /* -196 */ 0);\n $setup(SCLR, posedge CLK, /* -196 */ 0);\n $setup(SLOAD, posedge CLK, /* -196 */ 0);\n $setup(SDATA, posedge CLK, /* -196 */ 0);\n\n if (ACLR === 1'b0) (ACLR => Q) = 282;\nendspecify\n`endif\n
|
|
241
|
+
"dff_sim.v": "// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM)\n// act as one-bit memory cells that can be placed very flexibly (wherever there's\n// an ALM); each flop is represented by a MISTRAL_FF cell.\n//\n// The flops in these chips are rather flexible in some ways, but in practice\n// quite crippled by FPGA standards.\n//\n// What the flops can do\n// ---------------------\n// The core flop acts as a single-bit memory that initialises to zero at chip\n// reset. It takes in data on the rising edge of CLK if ENA is high,\n// and outputs it to Q. The ENA (clock enable) pin can therefore be used to\n// capture the input only if a condition is true.\n//\n// The data itself is zero if SCLR (synchronous clear) is high, else it comes\n// from SDATA (synchronous data) if SLOAD (synchronous load) is high, or DATAIN\n// if SLOAD is low.\n//\n// If ACLR (asynchronous clear) is low then Q is forced to zero, regardless of\n// the synchronous inputs or CLK edge. This is most often used for an FPGA-wide\n// power-on reset.\n//\n// An asynchronous set that sets Q to one can be emulated by inverting the input\n// and output of the flop, resulting in ACLR forcing Q to zero, which then gets\n// inverted to produce one. Likewise, logic can operate on the falling edge of\n// CLK if CLK is inverted before being passed as an input.\n//\n// What the flops *can't* do\n// -------------------------\n// The trickiest part of the above capabilities is the lack of configurable\n// initialisation state. For example, it isn't possible to implement a flop with\n// asynchronous clear that initialises to one, because the hardware initialises\n// to zero. Likewise, you can't emulate a flop with asynchronous set that\n// initialises to zero, because the inverters mean the flop initialises to one.\n//\n// If the input design requires one of these cells (which appears to be rare\n// in practice) then synth_intel_alm will fail to synthesize the design where\n// other Yosys synthesis scripts might succeed.\n//\n// This stands in notable contrast to e.g. Xilinx flip-flops, which have\n// configurable initialisation state and native synchronous/asynchronous\n// set/clear (although not at the same time), which means they can generally\n// implement a much wider variety of logic.\n\n// DATAIN: synchronous data input\n// CLK: clock input (positive edge)\n// ACLR: asynchronous clear (negative-true)\n// ENA: clock-enable\n// SCLR: synchronous clear\n// SLOAD: synchronous load\n// SDATA: synchronous load data\n//\n// Q: data output\n//\n// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.\n\n(* abc9_box, lib_whitebox *)\nmodule MISTRAL_FF(\n input DATAIN,\n (* clkbuf_sink *) input CLK,\n input ACLR, ENA, SCLR, SLOAD, SDATA,\n output reg Q\n);\n\n`ifdef cyclonev\nspecify\n if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;\n if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;\n if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;\n\n $setup(DATAIN, posedge CLK, /* -196 */ 0);\n $setup(ENA, posedge CLK, /* -196 */ 0);\n $setup(SCLR, posedge CLK, /* -196 */ 0);\n $setup(SLOAD, posedge CLK, /* -196 */ 0);\n $setup(SDATA, posedge CLK, /* -196 */ 0);\n\n if (ACLR === 1'b0) (ACLR => Q) = 282;\nendspecify\n`endif\n\ninitial begin\n // Altera flops initialise to zero.\n\tQ = 0;\nend\n\nalways @(posedge CLK, negedge ACLR) begin\n // Asynchronous clear\n if (!ACLR) Q <= 0;\n // Clock-enable\n\telse if (ENA) begin\n // Synchronous clear\n if (SCLR) Q <= 0;\n // Synchronous load\n else if (SLOAD) Q <= SDATA;\n else Q <= DATAIN;\n end\nend\n\nendmodule\n",
|
|
244
242
|
"dsp_map.v": "`default_nettype none\n\nmodule __MUL27X27(A, B, Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\nparameter A_WIDTH = 27;\nparameter B_WIDTH = 27;\nparameter Y_WIDTH = 54;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\nMISTRAL_MUL27X27 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));\n\nendmodule\n\n\nmodule __MUL18X18(A, B, Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\nparameter A_WIDTH = 18;\nparameter B_WIDTH = 18;\nparameter Y_WIDTH = 36;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\nMISTRAL_MUL18X18 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));\n\nendmodule\n\n\nmodule __MUL9X9(A, B, Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\nparameter A_WIDTH = 9;\nparameter B_WIDTH = 9;\nparameter Y_WIDTH = 18;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\nMISTRAL_MUL9X9 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));\n\nendmodule\n",
|
|
245
243
|
"dsp_sim.v": "`default_nettype none\n\n(* abc9_box *)\nmodule MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\n\n`ifdef cyclonev\nspecify\n (A *> Y) = 3732;\n (B *> Y) = 3928;\nendspecify\n`endif\n`ifdef arriav\n// NOTE: Arria V appears to have only one set of timings for all DSP modes...\nspecify\n (A *> Y) = 1895;\n (B *> Y) = 2053;\nendspecify\n`endif\n`ifdef cyclone10gx\n// TODO: Cyclone 10 GX timings; the below are for Cyclone V\nspecify\n (A *> Y) = 3732;\n (B *> Y) = 3928;\nendspecify\n`endif\n\nwire [53:0] A_, B_;\n\nif (A_SIGNED)\n assign A_ = $signed(A);\nelse\n assign A_ = $unsigned(A);\n\nif (B_SIGNED)\n assign B_ = $signed(B);\nelse\n assign B_ = $unsigned(B);\n\nassign Y = A_ * B_;\n\nendmodule\n\n(* abc9_box *)\nmodule MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\n\n`ifdef cyclonev\nspecify\n (A *> Y) = 3180;\n (B *> Y) = 3982;\nendspecify\n`endif\n`ifdef arriav\n// NOTE: Arria V appears to have only one set of timings for all DSP modes...\nspecify\n (A *> Y) = 1895;\n (B *> Y) = 2053;\nendspecify\n`endif\n`ifdef cyclone10gx\n// TODO: Cyclone 10 GX timings; the below are for Cyclone V\nspecify\n (A *> Y) = 3180;\n (B *> Y) = 3982;\nendspecify\n`endif\n\nwire [35:0] A_, B_;\n\nif (A_SIGNED)\n assign A_ = $signed(A);\nelse\n assign A_ = $unsigned(A);\n\nif (B_SIGNED)\n assign B_ = $signed(B);\nelse\n assign B_ = $unsigned(B);\n\nassign Y = A_ * B_;\n\nendmodule\n\n(* abc9_box *)\nmodule MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\n\n`ifdef cyclonev\nspecify\n (A *> Y) = 2818;\n (B *> Y) = 3051;\nendspecify\n`endif\n`ifdef arriav\n// NOTE: Arria V appears to have only one set of timings for all DSP modes...\nspecify\n (A *> Y) = 1895;\n (B *> Y) = 2053;\nendspecify\n`endif\n`ifdef cyclone10gx\n// TODO: Cyclone 10 GX timings; the below are for Cyclone V\nspecify\n (A *> Y) = 2818;\n (B *> Y) = 3051;\nendspecify\n`endif\n\nwire [17:0] A_, B_;\n\nif (A_SIGNED)\n assign A_ = $signed(A);\nelse\n assign A_ = $unsigned(A);\n\nif (B_SIGNED)\n assign B_ = $signed(B);\nelse\n assign B_ = $unsigned(B);\n\nassign Y = A_ * B_;\n\nendmodule\n",
|
|
246
244
|
"lutram_mlab.txt": "bram MISTRAL_MLAB\n init 0 # TODO: Re-enable when Yosys remembers the original filename.\n abits 5\n dbits 1\n groups 2\n ports 1 1\n wrmode 1 0\n # write enable\n enable 1 0\n transp 0 0\n clocks 1 0\n clkpol 1 1\nendbram\n\nmatch MISTRAL_MLAB\n min efficiency 5\n make_outreg\nendmatch",
|
|
247
245
|
"megafunction_bb.v": "// Intel megafunction declarations, to avoid Yosys complaining.\n`default_nettype none\n\n(* blackbox *)\nmodule altera_pll\n#(\n parameter reference_clock_frequency = \"0 ps\",\n\tparameter fractional_vco_multiplier = \"false\",\n parameter pll_type = \"General\",\n parameter pll_subtype = \"General\",\n parameter number_of_clocks = 1,\n parameter operation_mode = \"internal feedback\",\n parameter deserialization_factor = 4,\n parameter data_rate = 0,\n \n parameter sim_additional_refclk_cycles_to_lock = 0,\n parameter output_clock_frequency0 = \"0 ps\",\n parameter phase_shift0 = \"0 ps\",\n parameter duty_cycle0 = 50,\n \n parameter output_clock_frequency1 = \"0 ps\",\n parameter phase_shift1 = \"0 ps\",\n parameter duty_cycle1 = 50,\n \n parameter output_clock_frequency2 = \"0 ps\",\n parameter phase_shift2 = \"0 ps\",\n parameter duty_cycle2 = 50,\n \n parameter output_clock_frequency3 = \"0 ps\",\n parameter phase_shift3 = \"0 ps\",\n parameter duty_cycle3 = 50,\n \n parameter output_clock_frequency4 = \"0 ps\",\n parameter phase_shift4 = \"0 ps\",\n parameter duty_cycle4 = 50,\n \n parameter output_clock_frequency5 = \"0 ps\",\n parameter phase_shift5 = \"0 ps\",\n parameter duty_cycle5 = 50,\n \n parameter output_clock_frequency6 = \"0 ps\",\n parameter phase_shift6 = \"0 ps\",\n parameter duty_cycle6 = 50,\n \n parameter output_clock_frequency7 = \"0 ps\",\n parameter phase_shift7 = \"0 ps\",\n parameter duty_cycle7 = 50,\n \n parameter output_clock_frequency8 = \"0 ps\",\n parameter phase_shift8 = \"0 ps\",\n parameter duty_cycle8 = 50,\n \n parameter output_clock_frequency9 = \"0 ps\",\n parameter phase_shift9 = \"0 ps\",\n parameter duty_cycle9 = 50, \n\n \n parameter output_clock_frequency10 = \"0 ps\",\n parameter phase_shift10 = \"0 ps\",\n parameter duty_cycle10 = 50,\n \n parameter output_clock_frequency11 = \"0 ps\",\n parameter phase_shift11 = \"0 ps\",\n parameter duty_cycle11 = 50,\n \n parameter output_clock_frequency12 = \"0 ps\",\n parameter phase_shift12 = \"0 ps\",\n parameter duty_cycle12 = 50,\n \n parameter output_clock_frequency13 = \"0 ps\",\n parameter phase_shift13 = \"0 ps\",\n parameter duty_cycle13 = 50,\n \n parameter output_clock_frequency14 = \"0 ps\",\n parameter phase_shift14 = \"0 ps\",\n parameter duty_cycle14 = 50,\n \n parameter output_clock_frequency15 = \"0 ps\",\n parameter phase_shift15 = \"0 ps\",\n parameter duty_cycle15 = 50,\n \n parameter output_clock_frequency16 = \"0 ps\",\n parameter phase_shift16 = \"0 ps\",\n parameter duty_cycle16 = 50,\n \n parameter output_clock_frequency17 = \"0 ps\",\n parameter phase_shift17 = \"0 ps\",\n parameter duty_cycle17 = 50,\n \n parameter clock_name_0 = \"\",\n parameter clock_name_1 = \"\",\n parameter clock_name_2 = \"\",\n parameter clock_name_3 = \"\",\n parameter clock_name_4 = \"\",\n parameter clock_name_5 = \"\",\n parameter clock_name_6 = \"\",\n parameter clock_name_7 = \"\",\n parameter clock_name_8 = \"\",\n\n parameter clock_name_global_0 = \"false\",\n parameter clock_name_global_1 = \"false\",\n parameter clock_name_global_2 = \"false\",\n parameter clock_name_global_3 = \"false\",\n parameter clock_name_global_4 = \"false\",\n parameter clock_name_global_5 = \"false\",\n parameter clock_name_global_6 = \"false\",\n parameter clock_name_global_7 = \"false\",\n parameter clock_name_global_8 = \"false\",\n\n parameter m_cnt_hi_div = 1,\n parameter m_cnt_lo_div = 1,\n parameter m_cnt_bypass_en = \"false\",\n parameter m_cnt_odd_div_duty_en = \"false\",\n parameter n_cnt_hi_div = 1,\n parameter n_cnt_lo_div = 1,\n parameter n_cnt_bypass_en = \"false\",\n parameter n_cnt_odd_div_duty_en = \"false\",\n parameter c_cnt_hi_div0 = 1, \n parameter c_cnt_lo_div0 = 1,\n parameter c_cnt_bypass_en0 = \"false\",\n\tparameter c_cnt_in_src0 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en0 = \"false\",\n parameter c_cnt_prst0 = 1,\n parameter c_cnt_ph_mux_prst0 = 0,\n parameter c_cnt_hi_div1 = 1, \n parameter c_cnt_lo_div1 = 1,\n parameter c_cnt_bypass_en1 = \"false\",\n\tparameter c_cnt_in_src1 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en1 = \"false\",\n parameter c_cnt_prst1 = 1,\n parameter c_cnt_ph_mux_prst1 = 0,\n parameter c_cnt_hi_div2 = 1, \n parameter c_cnt_lo_div2 = 1,\n parameter c_cnt_bypass_en2 = \"false\",\n\tparameter c_cnt_in_src2 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en2 = \"false\",\n parameter c_cnt_prst2 = 1,\n parameter c_cnt_ph_mux_prst2 = 0,\n parameter c_cnt_hi_div3 = 1, \n parameter c_cnt_lo_div3 = 1,\n parameter c_cnt_bypass_en3 = \"false\",\n\tparameter c_cnt_in_src3 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en3 = \"false\",\n parameter c_cnt_prst3 = 1,\n parameter c_cnt_ph_mux_prst3 = 0,\n parameter c_cnt_hi_div4 = 1, \n parameter c_cnt_lo_div4 = 1,\n parameter c_cnt_bypass_en4 = \"false\",\n\tparameter c_cnt_in_src4 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en4 = \"false\",\n parameter c_cnt_prst4 = 1,\n parameter c_cnt_ph_mux_prst4 = 0,\n parameter c_cnt_hi_div5 = 1, \n parameter c_cnt_lo_div5 = 1,\n parameter c_cnt_bypass_en5 = \"false\",\n\tparameter c_cnt_in_src5 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en5 = \"false\",\n parameter c_cnt_prst5 = 1,\n parameter c_cnt_ph_mux_prst5 = 0,\n parameter c_cnt_hi_div6 = 1, \n parameter c_cnt_lo_div6 = 1,\n parameter c_cnt_bypass_en6 = \"false\",\n\tparameter c_cnt_in_src6 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en6 = \"false\",\n parameter c_cnt_prst6 = 1,\n parameter c_cnt_ph_mux_prst6 = 0,\n parameter c_cnt_hi_div7 = 1, \n parameter c_cnt_lo_div7 = 1,\n parameter c_cnt_bypass_en7 = \"false\",\n\tparameter c_cnt_in_src7 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en7 = \"false\",\n parameter c_cnt_prst7 = 1,\n parameter c_cnt_ph_mux_prst7 = 0,\n parameter c_cnt_hi_div8 = 1, \n parameter c_cnt_lo_div8 = 1,\n parameter c_cnt_bypass_en8 = \"false\",\n\tparameter c_cnt_in_src8 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en8 = \"false\",\n parameter c_cnt_prst8 = 1,\n parameter c_cnt_ph_mux_prst8 = 0,\n parameter c_cnt_hi_div9 = 1, \n parameter c_cnt_lo_div9 = 1,\n parameter c_cnt_bypass_en9 = \"false\",\n\tparameter c_cnt_in_src9 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en9 = \"false\",\n parameter c_cnt_prst9 = 1,\n parameter c_cnt_ph_mux_prst9 = 0,\n parameter c_cnt_hi_div10 = 1, \n parameter c_cnt_lo_div10 = 1,\n parameter c_cnt_bypass_en10 = \"false\",\n\tparameter c_cnt_in_src10 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en10 = \"false\",\n parameter c_cnt_prst10 = 1,\n parameter c_cnt_ph_mux_prst10 = 0,\n parameter c_cnt_hi_div11 = 1, \n parameter c_cnt_lo_div11 = 1,\n parameter c_cnt_bypass_en11 = \"false\",\n\tparameter c_cnt_in_src11 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en11 = \"false\",\n parameter c_cnt_prst11 = 1,\n parameter c_cnt_ph_mux_prst11 = 0,\n parameter c_cnt_hi_div12 = 1, \n parameter c_cnt_lo_div12 = 1,\n parameter c_cnt_bypass_en12 = \"false\",\n\tparameter c_cnt_in_src12 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en12 = \"false\",\n parameter c_cnt_prst12 = 1,\n parameter c_cnt_ph_mux_prst12 = 0,\n parameter c_cnt_hi_div13 = 1, \n parameter c_cnt_lo_div13 = 1,\n parameter c_cnt_bypass_en13 = \"false\",\n\tparameter c_cnt_in_src13 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en13 = \"false\",\n parameter c_cnt_prst13 = 1,\n parameter c_cnt_ph_mux_prst13 = 0,\n parameter c_cnt_hi_div14 = 1, \n parameter c_cnt_lo_div14 = 1,\n parameter c_cnt_bypass_en14 = \"false\",\n\tparameter c_cnt_in_src14 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en14 = \"false\",\n parameter c_cnt_prst14 = 1,\n parameter c_cnt_ph_mux_prst14 = 0,\n parameter c_cnt_hi_div15 = 1, \n parameter c_cnt_lo_div15 = 1,\n parameter c_cnt_bypass_en15 = \"false\",\n\tparameter c_cnt_in_src15 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en15 = \"false\",\n parameter c_cnt_prst15 = 1,\n parameter c_cnt_ph_mux_prst15 = 0,\n parameter c_cnt_hi_div16 = 1, \n parameter c_cnt_lo_div16 = 1,\n parameter c_cnt_bypass_en16 = \"false\",\n\tparameter c_cnt_in_src16 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en16 = \"false\",\n parameter c_cnt_prst16 = 1,\n parameter c_cnt_ph_mux_prst16 = 0,\n parameter c_cnt_hi_div17 = 1, \n parameter c_cnt_lo_div17 = 1,\n parameter c_cnt_bypass_en17 = \"false\",\n\tparameter c_cnt_in_src17 = \"ph_mux_clk\",\n parameter c_cnt_odd_div_duty_en17 = \"false\",\n parameter c_cnt_prst17 = 1,\n parameter c_cnt_ph_mux_prst17 = 0,\n parameter pll_vco_div = 1,\n\tparameter pll_slf_rst = \"false\",\n\tparameter pll_bw_sel = \"low\",\n parameter pll_output_clk_frequency = \"0 MHz\",\n parameter pll_cp_current = 0,\n parameter pll_bwctrl = 0,\n parameter pll_fractional_division = 1,\n parameter pll_fractional_cout = 24,\n parameter pll_dsm_out_sel = \"1st_order\",\n parameter mimic_fbclk_type = \"gclk\",\n parameter pll_fbclk_mux_1 = \"glb\",\n parameter pll_fbclk_mux_2 = \"fb_1\",\n parameter pll_m_cnt_in_src = \"ph_mux_clk\",\n\tparameter pll_vcoph_div = 1,\n parameter refclk1_frequency = \"0 MHz\",\n parameter pll_clkin_0_src = \"clk_0\",\n parameter pll_clkin_1_src = \"clk_0\",\n parameter pll_clk_loss_sw_en = \"false\",\n parameter pll_auto_clk_sw_en = \"false\",\n parameter pll_manu_clk_sw_en = \"false\", \n parameter pll_clk_sw_dly = 0,\n parameter pll_extclk_0_cnt_src = \"pll_extclk_cnt_src_vss\",\t\n parameter pll_extclk_1_cnt_src = \"pll_extclk_cnt_src_vss\"\n) (\n //input\n input refclk,\n input refclk1,\n input fbclk,\n input rst,\n input phase_en,\n input updn,\n input [2:0] num_phase_shifts,\n input scanclk,\n input [4:0] cntsel,\n input [63:0] reconfig_to_pll,\n input extswitch,\n input adjpllin,\n input cclk,\n \n //output\n output [ number_of_clocks -1 : 0] outclk,\n output fboutclk,\n output locked,\n output phase_done,\n output [63:0] reconfig_from_pll,\n output activeclk,\n output [1:0] clkbad,\n\toutput [7:0] phout,\n\toutput\t [1:0] lvds_clk,\n\toutput\t [1:0] loaden,\n\toutput [1:0] extclk_out,\n output [ number_of_clocks -1 : 0] cascade_out,\n\n //inout\n inout zdbfbclk\n);\n\nendmodule\n\n\n(* blackbox *)\nmodule altera_std_synchronizer(clk, din, dout, reset_n);\n\nparameter depth = 2;\n\ninput clk;\ninput reset_n;\ninput din;\noutput dout;\n\nendmodule\n\n(* blackbox *)\nmodule altddio_in (\n datain, // required port, DDR input data\n inclock, // required port, input reference clock to sample data by\n inclocken, // enable data clock\n aset, // asynchronous set\n aclr, // asynchronous clear\n sset, // synchronous set\n sclr, // synchronous clear\n dataout_h, // data sampled at the rising edge of inclock\n dataout_l // data sampled at the falling edge of inclock\n);\n\nparameter width = 1;\nparameter power_up_high = \"OFF\";\nparameter invert_input_clocks = \"OFF\";\nparameter intended_device_family = \"Stratix\";\nparameter lpm_type = \"altddio_in\";\nparameter lpm_hint = \"UNUSED\";\n\ninput [width-1:0] datain;\ninput inclock;\ninput inclocken;\ninput aset;\ninput aclr;\ninput sset;\ninput sclr;\n\noutput [width-1:0] dataout_h;\noutput [width-1:0] dataout_l;\n\nendmodule\n\n\n(* blackbox *)\nmodule altddio_out (\n datain_h,\n datain_l,\n outclock,\n outclocken,\n aset,\n aclr,\n sset,\n sclr,\n oe,\n dataout,\n oe_out\n);\n\nparameter width = 1;\nparameter power_up_high = \"OFF\";\nparameter oe_reg = \"UNUSED\";\nparameter extend_oe_disable = \"UNUSED\";\nparameter intended_device_family = \"Stratix\";\nparameter invert_output = \"OFF\";\nparameter lpm_type = \"altddio_out\";\nparameter lpm_hint = \"UNUSED\";\n\ninput [width-1:0] datain_h;\ninput [width-1:0] datain_l;\ninput outclock;\ninput outclocken;\ninput aset;\ninput aclr;\ninput sset;\ninput sclr;\ninput oe;\n\noutput [width-1:0] dataout;\noutput [width-1:0] oe_out;\n\nendmodule\n\n\n(* blackbox *)\nmodule altddio_bidir (\n datain_h,\n datain_l,\n inclock,\n inclocken,\n outclock,\n outclocken,\n aset,\n aclr,\n sset,\n sclr,\n oe,\n dataout_h,\n dataout_l,\n combout,\n oe_out,\n dqsundelayedout,\n padio\n);\n\n// GLOBAL PARAMETER DECLARATION\nparameter width = 1; // required parameter\nparameter power_up_high = \"OFF\";\nparameter oe_reg = \"UNUSED\";\nparameter extend_oe_disable = \"UNUSED\";\nparameter implement_input_in_lcell = \"UNUSED\";\nparameter invert_output = \"OFF\";\nparameter intended_device_family = \"Stratix\";\nparameter lpm_type = \"altddio_bidir\";\nparameter lpm_hint = \"UNUSED\";\n\n// INPUT PORT DECLARATION\ninput [width-1:0] datain_h;\ninput [width-1:0] datain_l;\ninput inclock;\ninput inclocken;\ninput outclock;\ninput outclocken;\ninput aset;\ninput aclr;\ninput sset;\ninput sclr;\ninput oe;\n\n// OUTPUT PORT DECLARATION\noutput [width-1:0] dataout_h;\noutput [width-1:0] dataout_l;\noutput [width-1:0] combout;\noutput [width-1:0] oe_out;\noutput [width-1:0] dqsundelayedout;\n// BIDIRECTIONAL PORT DECLARATION\ninout [width-1:0] padio;\n\nendmodule\n\n\n(* blackbox *)\nmodule altiobuf_in(datain, dataout);\n\nparameter enable_bus_hold = \"FALSE\";\nparameter use_differential_mode = \"FALSE\";\nparameter number_of_channels = 1;\n\ninput [number_of_channels-1:0] datain;\noutput [number_of_channels-1:0] dataout;\n\nendmodule\n\n(* blackbox *)\nmodule altiobuf_out(datain, dataout);\n\nparameter enable_bus_hold = \"FALSE\";\nparameter use_differential_mode = \"FALSE\";\nparameter use_oe = \"FALSE\";\nparameter number_of_channels = 1;\n\ninput [number_of_channels-1:0] datain;\noutput [number_of_channels-1:0] dataout;\n\nendmodule\n\n(* blackbox *)\nmodule altiobuf_bidir(dataio, oe, datain, dataout);\n\nparameter number_of_channels = 1;\nparameter enable_bus_hold = \"OFF\";\n\ninout [number_of_channels-1:0] dataio;\ninput [number_of_channels-1:0] datain;\noutput [number_of_channels-1:0] dataout;\ninput [number_of_channels-1:0] oe;\n\nendmodule\n\n(* blackbox *)\nmodule altsyncram(clock0, clock1, address_a, data_a, rden_a, wren_a, byteena_a, q_a, addressstall_a, address_b, data_b, rden_b, wren_b, byteena_b, q_b, addressstall_b, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, eccstatus);\n\nparameter lpm_type = \"altsyncram\";\nparameter operation_mode = \"dual_port\";\nparameter ram_block_type = \"auto\";\nparameter intended_device_family = \"auto\";\nparameter power_up_uninitialized = \"false\";\nparameter read_during_write_mode_mixed_ports = \"dontcare\";\nparameter byte_size = 8;\nparameter widthad_a = 1;\nparameter width_a = 1;\nparameter width_byteena_a = 1;\nparameter numwords_a = 1;\nparameter clock_enable_input_a = \"clocken0\";\nparameter widthad_b = 1;\nparameter width_b = 1;\nparameter numwords_b = 1;\nparameter address_aclr_b = \"aclr0\";\nparameter address_reg_b = \"\";\nparameter outdata_aclr_b = \"aclr0\";\nparameter outdata_reg_b = \"\";\nparameter clock_enable_input_b = \"clocken0\";\nparameter clock_enable_output_b = \"clocken0\";\n\ninput clock0, clock1;\ninput [widthad_a-1:0] address_a;\ninput [width_a-1:0] data_a;\ninput rden_a;\ninput wren_a;\ninput [(width_a/8)-1:0] byteena_a;\ninput addressstall_a;\n\noutput [width_a-1:0] q_a;\n\ninput wren_b;\ninput rden_b;\ninput [widthad_b-1:0] address_b;\ninput [width_b-1:0] data_b;\ninput [(width_b/8)-1:0] byteena_b;\ninput addressstall_b;\n\noutput [width_b-1:0] q_b;\n\ninput clocken0;\ninput clocken1;\ninput clocken2;\ninput clocken3;\n\ninput aclr0;\ninput aclr1;\n\noutput eccstatus;\n\nendmodule\n\n(* blackbox *)\nmodule cyclonev_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1);\n\nparameter logical_ram_name = \"\";\nparameter logical_ram_depth = 32;\nparameter logical_ram_width = 20;\nparameter mixed_port_feed_through_mode = \"new\";\nparameter first_bit_number = 0;\nparameter first_address = 0;\nparameter last_address = 31;\nparameter address_width = 5;\nparameter data_width = 1;\nparameter byte_enable_mask_width = 1;\nparameter port_b_data_out_clock = \"NONE\";\nparameter [639:0] mem_init0 = 640'b0;\n\ninput [address_width-1:0] portaaddr, portbaddr;\ninput [data_width-1:0] portadatain;\noutput [data_width-1:0] portbdataout;\ninput ena0, clk0, clk1;\n\nendmodule\n\n(* blackbox *)\nmodule cyclonev_mac(ax, ay, resulta);\n\nparameter ax_width = 9;\nparameter signed_max = \"true\";\nparameter ay_scan_in_width = 9;\nparameter signed_may = \"true\";\nparameter result_a_width = 18;\nparameter operation_mode = \"M9x9\";\n\ninput [ax_width-1:0] ax;\ninput [ay_scan_in_width-1:0] ay;\noutput [result_a_width-1:0] resulta;\n\nendmodule\n\n(* blackbox *)\nmodule cyclone10gx_mac(ax, ay, resulta);\n\nparameter ax_width = 18;\nparameter signed_max = \"true\";\nparameter ay_scan_in_width = 18;\nparameter signed_may = \"true\";\nparameter result_a_width = 36;\nparameter operation_mode = \"M18X18_FULL\";\n\ninput [ax_width-1:0] ax;\ninput [ay_scan_in_width-1:0] ay;\noutput [result_a_width-1:0] resulta;\n\nendmodule\n\n(* blackbox *)\nmodule cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);\n\nparameter operation_mode = \"dual_port\";\nparameter logical_ram_name = \"\";\nparameter port_a_address_width = 10;\nparameter port_a_data_width = 10;\nparameter port_a_logical_ram_depth = 1024;\nparameter port_a_logical_ram_width = 10;\nparameter port_a_first_address = 0;\nparameter port_a_last_address = 1023;\nparameter port_a_first_bit_number = 0;\nparameter port_b_address_width = 10;\nparameter port_b_data_width = 10;\nparameter port_b_logical_ram_depth = 1024;\nparameter port_b_logical_ram_width = 10;\nparameter port_b_first_address = 0;\nparameter port_b_last_address = 1023;\nparameter port_b_first_bit_number = 0;\nparameter port_b_address_clock = \"clock0\";\nparameter port_b_read_enable_clock = \"clock0\";\nparameter mem_init0 = \"\";\nparameter mem_init1 = \"\";\nparameter mem_init2 = \"\";\nparameter mem_init3 = \"\";\nparameter mem_init4 = \"\";\n\ninput [port_a_address_width-1:0] portaaddr;\ninput [port_b_address_width-1:0] portbaddr;\ninput [port_a_data_width-1:0] portadatain;\noutput [port_b_data_width-1:0] portbdataout;\ninput clk0, portawe, portbre;\n\nendmodule\n\n(* blackbox *)\nmodule cyclone10gx_io_ibuf(i, ibar, dynamicterminationcontrol, o);\n\nparameter differential_mode =\"false\";\nparameter bus_hold = \"false\";\nparameter simulate_z_as = \"Z\";\nparameter lpm_type = \"cyclone10gx_io_ibuf\";\n\n(* iopad_external_pin *) input i;\n(* iopad_external_pin *) input ibar;\ninput dynamicterminationcontrol;\noutput o;\n\nendmodule\n\n(* blackbox *)\nmodule cyclone10gx_io_obuf(i, oe, dynamicterminationcontrol, seriesterminationcontrol, parallelterminationcontrol, devoe, o, obar);\n\nparameter open_drain_output = \"false\";\nparameter bus_hold = \"false\";\nparameter shift_series_termination_control = \"false\";\nparameter sim_dynamic_termination_control_is_connected = \"false\";\nparameter lpm_type = \"cyclone10gx_io_obuf\";\n\ninput i;\ninput oe;\ninput devoe;\ninput dynamicterminationcontrol;\ninput [15:0] seriesterminationcontrol;\ninput [15:0] parallelterminationcontrol;\n(* iopad_external_pin *) output o;\n(* iopad_external_pin *) output obar;\n\nendmodule\n\n(* blackbox *)\nmodule cyclonev_clkena(inclk, ena, enaout, outclk);\n\nparameter clock_type = \"auto\";\nparameter ena_register_mode = \"always enabled\";\nparameter lpm_type = \"cyclonev_clkena\";\nparameter ena_register_power_up = \"high\";\nparameter disable_mode = \"low\";\nparameter test_syn = \"high\";\n\ninput inclk;\ninput ena;\noutput enaout;\noutput outclk;\n\nendmodule\n\n(* blackbox *)\nmodule cyclone10gx_clkena(inclk, ena, enaout, outclk);\n\nparameter clock_type = \"auto\";\nparameter ena_register_mode = \"always enabled\";\nparameter lpm_type = \"cyclone10gx_clkena\";\nparameter ena_register_power_up = \"high\";\nparameter disable_mode = \"low\";\nparameter test_syn = \"high\";\n\ninput inclk;\ninput ena;\noutput enaout;\noutput outclk;\n\nendmodule\n\n// Internal interfaces\n(* keep *)\nmodule cyclonev_oscillator(oscena, clkout, clkout1);\n\ninput oscena;\noutput clkout;\noutput clkout1;\n\nendmodule\n\n// HPS interfaces\n(* keep *)\nmodule cyclonev_hps_interface_mpu_general_purpose(gp_in, gp_out);\n\ninput [31:0] gp_in;\noutput [31:0] gp_out;\n\nendmodule\n",
|
|
248
|
-
"mem_sim.v": "// The MLAB\n// --------\n// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic\n// Modules (ALMs, see alm_sim.v), the Cyclone V
|
|
246
|
+
"mem_sim.v": "// The MLAB\n// --------\n// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic\n// Modules (ALMs, see alm_sim.v), the Cyclone V also contains\n// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise\n// the memory the ALM uses to store the look-up table data for general usage,\n// producing a 32 address by 20-bit block of memory. MLABs are spread out\n// around the chip, so they can be placed near where they are needed, rather than\n// being comparatively limited in placement for a deep but narrow memory such as\n// the M10K memory block.\n//\n// MLABs are used mainly for shallow but wide memories, such as CPU register\n// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))\n// or shift registers (by using the output of the Nth bit as input for the N+1th\n// bit).\n//\n// For historical reasons a MISTRAL_MLAB cell represents a 32 address by 1-bit cell,\n// and 20 of them represent a physical MLAB.\n//\n// How the MLAB works\n// ------------------\n// MLABs are poorly documented, so the following information is based mainly\n// on the simulation model and my knowledge of how memories like these work.\n// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated\n// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use\n// `techmap` just for the sake of renaming the cell ports.\n//\n// The MLAB can be initialised to any value.\n//\n// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN\n// is high, writes it to the address in A1ADDR. A1EN can therefore be used to\n// conditionally write data to the MLAB.\n//\n// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,\n// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed\n// then the output can be fed to embedded flops.\n\n// The vendor sim model outputs 'x for a very short period (a few\n// combinational delta cycles) after each write. This has been omitted from\n// the following model because it's very difficult to trigger this in practice\n// as clock cycles will be much longer than any potential blip of 'x, so the\n// model can be treated as always returning a defined result.\n\n(* abc9_box, lib_whitebox *)\nmodule MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN,\n (* clkbuf_sink *) input CLK1,\n input [4:0] B1ADDR, output B1DATA);\n\nreg [31:0] mem = 32'b0;\n\n`ifdef cyclonev\nspecify\n $setup(A1ADDR, posedge CLK1, 86);\n $setup(A1DATA, posedge CLK1, 86);\n $setup(A1EN, posedge CLK1, 86);\n\n (B1ADDR[0] => B1DATA) = 487;\n (B1ADDR[1] => B1DATA) = 475;\n (B1ADDR[2] => B1DATA) = 382;\n (B1ADDR[3] => B1DATA) = 284;\n (B1ADDR[4] => B1DATA) = 96;\nendspecify\n`endif\n\nalways @(posedge CLK1)\n if (A1EN) mem[A1ADDR] <= A1DATA;\n\nassign B1DATA = mem[B1ADDR];\n\nendmodule\n\n// The M10K\n// --------\n// TODO\n\nmodule MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n\nparameter INIT = 0;\n\nparameter CFG_ABITS = 10;\nparameter CFG_DBITS = 10;\n\n(* clkbuf_sink *) input CLK1;\ninput [CFG_ABITS-1:0] A1ADDR, B1ADDR;\ninput [CFG_DBITS-1:0] A1DATA;\ninput A1EN, B1EN;\noutput reg [CFG_DBITS-1:0] B1DATA;\n\nreg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = INIT;\n\n`ifdef cyclonev\nspecify\n $setup(A1ADDR, posedge CLK1, 125);\n $setup(A1DATA, posedge CLK1, 97);\n $setup(A1EN, posedge CLK1, 140);\n $setup(B1ADDR, posedge CLK1, 125);\n $setup(B1EN, posedge CLK1, 161);\n\n if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004;\nendspecify\n`endif\n\nalways @(posedge CLK1) begin\n if (!A1EN)\n mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;\n\n if (B1EN)\n B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];\nend\n\nendmodule\n",
|
|
249
247
|
"misc_sim.v": "module MISTRAL_IB((* iopad_external_pin *) input PAD, output O);\n\tassign O = PAD;\nendmodule\n\nmodule MISTRAL_OB((* iopad_external_pin *) output PAD, input I);\n\tassign PAD = I;\nendmodule\n\nmodule MISTRAL_IO((* iopad_external_pin *) inout PAD, input I, input OE, output O);\n\tassign PAD = OE ? I : 1'bz;\n\tassign O = PAD;\nendmodule\n\n// Eventually, we should support clock enables and model them here too.\n// For now, CLKENA is used as a basic entry point to global routing.\nmodule MISTRAL_CLKBUF (\n\tinput A,\n\t(* clkbuf_driver *) output Q\n);\n\tassign Q = A;\nendmodule",
|
|
250
|
-
"quartus_rename.v": "`ifdef cyclonev\n`define LCELL cyclonev_lcell_comb\n`define MAC cyclonev_mac\n`define MLAB cyclonev_mlab_cell\n`define RAM_BLOCK cyclonev_ram_block\n`define IBUF cyclonev_io_ibuf\n`define OBUF cyclonev_io_obuf\n`define CLKENA cyclonev_clkena\n`endif\n`ifdef arriav\n`define LCELL arriav_lcell_comb\n`define MAC arriav_mac\n`define MLAB arriav_mlab_cell\n`define RAM_BLOCK arriav_ram_block\n`define IBUF arriav_io_ibuf\n`define OBUF arriav_io_obuf\n`define CLKENA arriav_clkena\n`endif\n`ifdef cyclone10gx\n`define LCELL cyclone10gx_lcell_comb\n`define MAC cyclone10gx_mac\n`define MLAB cyclone10gx_mlab_cell\n`define RAM_BLOCK cyclone10gx_ram_block\n`define IBUF cyclone10gx_io_ibuf\n`define OBUF cyclone10gx_io_obuf\n`define CLKENA cyclone10gx_clkena\n`endif\n\nmodule __MISTRAL_VCC(output Q);\n\nMISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));\n\nendmodule\n\n\nmodule __MISTRAL_GND(output Q);\n\nMISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));\n\nendmodule\n\n\nmodule MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);\n\ndffeas #(.power_up(\"low\"), .is_wysiwyg(\"true\")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));\n\nendmodule\n\n\nmodule MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);\nparameter [63:0] LUT = 64'h0000_0000_0000_0000;\n\n`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));\n\nendmodule\n\n\nmodule MISTRAL_ALUT5(input A, B, C, D, E, output Q);\nparameter [31:0] LUT = 32'h0000_0000;\n\n`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));\n\nendmodule\n\n\nmodule MISTRAL_ALUT4(input A, B, C, D, output Q);\nparameter [15:0] LUT = 16'h0000;\n\n`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));\n\nendmodule\n\n\nmodule MISTRAL_ALUT3(input A, B, C, output Q);\nparameter [7:0] LUT = 8'h00;\n\n`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));\n\nendmodule\n\n\nmodule MISTRAL_ALUT2(input A, B, output Q);\nparameter [3:0] LUT = 4'h0;\n\n`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));\n\nendmodule\n\n\nmodule MISTRAL_NOT(input A, output Q);\n\nNOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));\n\nendmodule\n\n\nmodule MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);\nparameter LUT0 = 16'h0000;\nparameter LUT1 = 16'h0000;\n\n`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));\n\nendmodule\n\n\nmodule MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);\n\nparameter _TECHMAP_CELLNAME_ = \"\";\n\n// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,\n// which takes in a hexadecimal string that could be used to initialise RAM.\n// In the vendor simulation models, this appears to work fine, but Quartus,\n// either intentionally or not, forgets about this parameter and initialises the\n// RAM to zero.\n//\n// Because of this, RAM initialisation is presently disabled, but the source\n// used to generate mem_init0 is kept (commented out) in case this gets fixed\n// or an undocumented way to get Quartus to initialise from mem_init0 is found.\n\n`MLAB #(\n .logical_ram_name(_TECHMAP_CELLNAME_),\n .logical_ram_depth(32),\n .logical_ram_width(1),\n .mixed_port_feed_through_mode(\"Dont Care\"),\n .first_bit_number(0),\n .first_address(0),\n .last_address(31),\n .address_width(5),\n .data_width(1),\n .byte_enable_mask_width(1),\n .port_b_data_out_clock(\"NONE\"),\n // .mem_init0($sformatf(\"%08x\", INIT))\n) _TECHMAP_REPLACE_ (\n .portaaddr(A1ADDR),\n .portadatain(A1DATA),\n .portbaddr(B1ADDR),\n .portbdataout(B1DATA),\n .ena0(A1EN),\n .clk0(CLK1)\n);\n\nendmodule\n\n\nmodule MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);\n\nparameter CFG_ABITS = 10;\nparameter CFG_DBITS = 10;\n\nparameter _TECHMAP_CELLNAME_ = \"\";\n\ninput [CFG_ABITS-1:0] A1ADDR, B1ADDR;\ninput [CFG_DBITS-1:0] A1DATA;\ninput CLK1, A1EN, B1EN;\noutput [CFG_DBITS-1:0] B1DATA;\n\n// Much like the MLAB, the M10K has mem_init[01234] parameters which would let\n// you initialise the RAM cell via hex literals. If they were implemented.\n\n// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware)\n// but the Quartus primitive expects a normal write-enable, we add an inverter.\nwire A1EN_N;\nNOT wren_inv (.IN(A1EN), .OUT(A1EN_N));\n\n`RAM_BLOCK #(\n .operation_mode(\"dual_port\"),\n .logical_ram_name(_TECHMAP_CELLNAME_),\n .port_a_address_width(CFG_ABITS),\n .port_a_data_width(CFG_DBITS),\n .port_a_logical_ram_depth(2**CFG_ABITS),\n .port_a_logical_ram_width(CFG_DBITS),\n .port_a_first_address(0),\n .port_a_last_address(2**CFG_ABITS - 1),\n .port_a_first_bit_number(0),\n .port_b_address_width(CFG_ABITS),\n .port_b_data_width(CFG_DBITS),\n .port_b_logical_ram_depth(2**CFG_ABITS),\n .port_b_logical_ram_width(CFG_DBITS),\n .port_b_first_address(0),\n .port_b_last_address(2**CFG_ABITS - 1),\n .port_b_first_bit_number(0),\n .port_b_address_clock(\"clock0\"),\n .port_b_read_enable_clock(\"clock0\")\n) ram_block (\n .portaaddr(A1ADDR),\n .portadatain(A1DATA),\n .portawe(A1EN_N),\n .portbaddr(B1ADDR),\n .portbdataout(B1DATA),\n .portbre(B1EN),\n .clk0(CLK1)\n);\n\nendmodule\n\n\nmodule MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\n\n`MAC #(\n .ax_width(27),\n .signed_max(A_SIGNED ? \"true\" : \"false\"),\n .ay_scan_in_width(27),\n .signed_may(B_SIGNED ? \"true\" : \"false\"),\n .result_a_width(54),\n .operation_mode(\"M27x27\")\n) _TECHMAP_REPLACE_ (\n .ax(A),\n .ay(B),\n .resulta(Y)\n);\n\nendmodule\n\n\nmodule MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\n\n`MAC #(\n .ax_width(18),\n .signed_max(A_SIGNED ? \"true\" : \"false\"),\n .ay_scan_in_width(18),\n .signed_may(B_SIGNED ? \"true\" : \"false\"),\n .result_a_width(36),\n .operation_mode(\"M18x18_FULL\")\n) _TECHMAP_REPLACE_ (\n .ax(A),\n .ay(B),\n .resulta(Y)\n);\n\nendmodule\n\n\nmodule MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);\n\nparameter A_SIGNED = 1;\nparameter B_SIGNED = 1;\n\n`MAC #(\n .ax_width(9),\n .signed_max(A_SIGNED ? \"true\" : \"false\"),\n .ay_scan_in_width(9),\n .signed_may(B_SIGNED ? \"true\" : \"false\"),\n .result_a_width(18),\n .operation_mode(\"M9x9\")\n) _TECHMAP_REPLACE_ (\n .ax(A),\n .ay(B),\n .resulta(Y)\n);\n\nendmodule\n\nmodule MISTRAL_IB(input PAD, output O);\n`IBUF #(\n .bus_hold(\"false\"),\n .differential_mode(\"false\")\n) _TECHMAP_REPLACE_ (\n .i(PAD),\n .o(O)\n);\nendmodule\n\nmodule MISTRAL_OB(output PAD, input I, OE);\n`OBUF #(\n .bus_hold(\"false\"),\n .differential_mode(\"false\")\n) _TECHMAP_REPLACE_ (\n .i(I),\n .o(PAD),\n .oe(OE)\n);\nendmodule\n\nmodule MISTRAL_IO(output PAD, input I, OE, output O);\n`IBUF #(\n .bus_hold(\"false\"),\n .differential_mode(\"false\")\n) ibuf (\n .i(PAD),\n .o(O)\n);\n\n`OBUF #(\n .bus_hold(\"false\"),\n .differential_mode(\"false\")\n) obuf (\n .i(I),\n .o(PAD),\n .oe(OE)\n);\nendmodule\n\nmodule MISTRAL_CLKBUF (input A, output Q);\n`CLKENA #(\n .clock_type(\"auto\"),\n .ena_register_mode(\"always enabled\"),\n .ena_register_power_up(\"high\"),\n .disable_mode(\"low\"),\n .test_syn(\"high\")\n) _TECHMAP_REPLACE_ (\n .inclk(A),\n .ena(1'b1),\n .outclk(Q)\n);\nendmodule\n",
|
|
251
248
|
},
|
|
252
249
|
"cyclonev": {
|
|
253
250
|
"cells_sim.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\nmodule VCC (output V);\n assign V = 1'b1;\nendmodule // VCC\n\nmodule GND (output G);\n assign G = 1'b0;\nendmodule // GND\n\n/* Altera Cyclone V devices Input Buffer Primitive */\nmodule cyclonev_io_ibuf\n (output o,\n (* iopad_external_pin *) input i,\n (* iopad_external_pin *) input ibar,\n input dynamicterminationcontrol);\n\n parameter differential_mode = \"false\";\n parameter bus_hold = \"false\";\n parameter simulate_z_as = \"Z\";\n parameter lpm_type = \"cyclonev_io_ibuf\";\n\n assign o = i;\nendmodule // cyclonev_io_ibuf\n\n/* Altera Cyclone V devices Output Buffer Primitive */\nmodule cyclonev_io_obuf\n ((* iopad_external_pin *) output o,\n input i, oe, dynamicterminationcontrol,\n input [15:0] seriesterminationcontrol, parallelterminationcontrol,\n input devoe,\n (* iopad_external_pin *) output obar);\n\n parameter open_drain_output = \"false\";\n parameter bus_hold = \"false\";\n parameter shift_series_termination_control = \"false\";\n parameter sim_dynamic_termination_control_is_connected = \"false\";\n parameter lpm_type = \"cyclonev_io_obuf\";\n\n assign o = oe ? i : 1'bz;\nendmodule // cyclonev_io_obuf\n\n/* Altera Cyclone V LUT Primitive */\nmodule cyclonev_lcell_comb\n (output combout, cout, sumout, shareout,\n input dataa, datab, datac, datad,\n input datae, dataf, datag, cin,\n input sharein);\n\n parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;\n parameter dont_touch = \"off\";\n parameter lpm_type = \"cyclonev_lcell_comb\";\n parameter shared_arith = \"off\";\n parameter extended_lut = \"off\";\n\n // Internal variables\n // Sub mask for fragmented LUTs\n wire [15:0] mask_a, mask_b, mask_c, mask_d;\n // Independent output for fragmented LUTs\n wire output_0, output_1, output_2, output_3;\n // Extended mode uses mux to define the output\n wire mux_0, mux_1;\n // Input for hold the shared LUT mode value\n wire shared_lut_alm;\n\n // Simulation model of 4-input LUT\n function lut4;\n input [15:0] mask;\n input dataa, datab, datac, datad;\n reg [7:0] s3;\n reg [3:0] s2;\n reg [1:0] s1;\n begin\n s3 = datad ? mask[15:8] : mask[7:0];\n s2 = datac ? s3[7:4] : s3[3:0];\n s1 = datab ? s2[3:2] : s2[1:0];\n lut4 = dataa ? s1[1] : s1[0];\n end\n endfunction // lut4\n\n // Simulation model of 5-input LUT\n function lut5;\n input [31:0] mask; // wp-01003.pdf, page 3: \"a 5-LUT can be built with two 4-LUTs and a multiplexer.\n input dataa, datab, datac, datad, datae;\n reg upper_lut_value;\n reg lower_lut_value;\n begin\n upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);\n lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);\n lut5 = (datae) ? upper_lut_value : lower_lut_value;\n end\n endfunction // lut5\n\n // Simulation model of 6-input LUT\n function lut6;\n input [63:0] mask;\n input dataa, datab, datac, datad, datae, dataf;\n reg upper_lut_value;\n reg lower_lut_value;\n reg out_0, out_1, out_2, out_3;\n begin\n upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);\n lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);\n lut6 = (dataf) ? upper_lut_value : lower_lut_value;\n end\n endfunction // lut6\n\n assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};\n`ifdef ADVANCED_ALM\n always @(*) begin\n if(extended_lut == \"on\")\n shared_lut_alm = datag;\n else\n shared_lut_alm = datac;\n // Build the ALM behaviour\n out_0 = lut4(mask_a, dataa, datab, datac, datad);\n out_1 = lut4(mask_b, dataa, datab, shared_lut_alm, datad);\n out_2 = lut4(mask_c, dataa, datab, datac, datad);\n out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);\n end\n`else\n `ifdef DEBUG\n initial $display(\"Advanced ALM lut combine is not implemented yet\");\n `endif\n`endif\nendmodule // cyclonev_lcell_comb\n\n\n/* Altera D Flip-Flop Primitive */\nmodule dffeas\n (output q,\n input d, clk, clrn, prn, ena,\n input asdata, aload, sclr, sload);\n\n // Timing simulation is not covered\n parameter power_up=\"dontcare\";\n parameter is_wysiwyg=\"false\";\n\n reg q_tmp;\n wire reset;\n reg [7:0] debug_net;\n\n assign reset = (prn && sclr && ~clrn && ena);\n assign q = q_tmp & 1'b1;\n\n always @(posedge clk, posedge aload) begin\n if(reset) q_tmp <= 0;\n else q_tmp <= d;\n end\n assign q = q_tmp;\n\nendmodule // dffeas\n",
|
|
@@ -1,5 +1,5 @@
|
|
|
1
1
|
// **AUTOGENERATED FILE** **DO NOT EDIT**
|
|
2
|
-
// Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-
|
|
2
|
+
// Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-06-08 01:06:35.578524+00:00
|
|
3
3
|
`timescale 1ns /10ps
|
|
4
4
|
|
|
5
5
|
module TDP36K_BRAM_A_X1_B_X1_nonsplit (
|
package/gen/yosys.core.wasm
CHANGED
|
Binary file
|