@yowasp/yosys 0.40.165-dev.701 → 0.40.706

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Files changed (4) hide show
  1. package/gen/resources-yosys.js +11 -7
  2. package/gen/share/quicklogic/qlf_k6n10f/bram_types_sim.v +1 -1
  3. package/gen/yosys.core.wasm +0 -0
  4. package/package.json +1 -1
package/gen/resources-yosys.js CHANGED
@@ -27,6 +27,9 @@ export const filesystem = {
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  "lutrams_map.v": "module $__ANLOGIC_DRAM16X4_ (...);\n\tparameter INIT = 64'b0;\n\n\tinput PORT_W_CLK;\n\tinput [3:0] PORT_W_ADDR;\n\tinput [3:0] PORT_W_WR_DATA;\n\tinput PORT_W_WR_EN;\n\n\tinput [3:0] PORT_R_ADDR;\n\toutput [3:0] PORT_R_RD_DATA;\n\n\tfunction [15:0] init_slice;\n\t\tinput integer idx;\n\t\tinteger i;\n\t\tfor (i = 0; i < 16; i = i + 1)\n\t\t\tinit_slice[i] = INIT[i * 4 + idx];\n\tendfunction\n\n\tEG_LOGIC_DRAM16X4 #(\n\t\t.INIT_D0(init_slice(0)),\n\t\t.INIT_D1(init_slice(1)),\n\t\t.INIT_D2(init_slice(2)),\n\t\t.INIT_D3(init_slice(3))\n\t) _TECHMAP_REPLACE_ (\n\t\t.di(PORT_W_WR_DATA),\n\t\t.waddr(PORT_W_ADDR),\n\t\t.wclk(PORT_W_CLK),\n\t\t.we(PORT_W_WR_EN),\n\t\t.raddr(PORT_R_ADDR),\n\t\t.do(PORT_R_RD_DATA)\n\t);\nendmodule\n",
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  },
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  "cells.lib": "library(yosys_cells) {\n\tcell(DFF_N) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_P) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NN0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NN1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NP0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_NP1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"!C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PN0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PN1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"!R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PP0) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tclear: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n\tcell(DFF_PP1) {\n\t\tff(IQ, IQN) {\n\t\t\tclocked_on: \"C\";\n\t\t\tnext_state: \"D\";\n\t\t\tpreset: \"R\";\n\t\t}\n\t\tpin(D) { direction: input; }\n\t\tpin(R) { direction: input; }\n\t\tpin(C) { direction: input; clock: true; }\n\t\tpin(Q) { direction: output; function: \"IQ\"; }\n\t}\n}\n",
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+ "choices": {
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+ "kogge-stone.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Martin Povišer <povik@cutebit.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _80_lcu_kogge_stone (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\tfor (i = 0; i < $clog2(WIDTH); i = i + 1) begin\n\t\t\t// iterate in reverse so we don't confuse a result from this stage and the previous\n\t\t\tfor (j = WIDTH - 1; j >= 2**i; j = j - 1) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**i];\n\t\t\t\tp[j] = p[j] & p[j - 2**i];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n",
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+ },
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  "cmp2lcu.v": "// This pass performs an optimisation that decomposes wide arithmetic\n// comparisons into LUT-size chunks (as guided by the `LUT_WIDTH\n// macro) connected to a single lookahead-carry-unit $lcu cell,\n// which is typically mapped to dedicated (and fast) FPGA\n// carry-chains.\n(* techmap_celltype = \"$lt $le $gt $ge\" *)\nmodule _80_lcu_cmp_ (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\n(* force_downto *)\noutput [Y_WIDTH-1:0] Y;\n\nparameter _TECHMAP_CELLTYPE_ = \"\";\n\ngenerate\n if (_TECHMAP_CELLTYPE_ == \"\" || `LUT_WIDTH < 2)\n wire _TECHMAP_FAIL_ = 1;\n else if (_TECHMAP_CELLTYPE_ == \"$lt\") begin\n // Transform $lt into $gt by swapping A and B\n $gt #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));\n end\n else if (_TECHMAP_CELLTYPE_ == \"$le\") begin\n // Transform $le into $ge by swapping A and B\n $ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));\n end\n else begin\n // Perform sign extension on A and B\n localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;\n (* force_downto *)\n wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n (* force_downto *)\n wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};\n // For $ge operation, start with the assumption that A and B are\n // equal (propagating this equality if A and B turn out to be so)\n localparam CI = _TECHMAP_CELLTYPE_ == \"$ge\";\n $__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))\n _TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));\n end\nendgenerate\nendmodule\n\nmodule $__CMP2LCU (A, B, P, G, Y);\n\nparameter AB_WIDTH = 0;\nparameter AB_SIGNED = 0;\nparameter LCU_WIDTH = 1;\nparameter BUDGET = 0;\nparameter CI = 0;\n\n(* force_downto *)\ninput [AB_WIDTH-1:0] A; // A from original $gt/$ge\n(* force_downto *)\ninput [AB_WIDTH-1:0] B; // B from original $gt/$ge\n(* force_downto *)\ninput [LCU_WIDTH-1:0] P; // P of $lcu\n(* force_downto *)\ninput [LCU_WIDTH-1:0] G; // G of $lcu\noutput Y;\n\nparameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;\nparameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\nparameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;\n\ngenerate\n if (AB_WIDTH == 0) begin\n (* force_downto *)\n wire [LCU_WIDTH-1:0] CO;\n $lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));\n assign Y = CO[LCU_WIDTH-1];\n end\n else begin\n localparam COST =\n _TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]\n ? 0\n : (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]\n ? 1\n : 2);\n\n if (BUDGET < COST)\n $__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))\n _TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, 1'b1}), .G({G, 1'b0}), .Y(Y));\n else begin\n wire PP, GG;\n // Bit-wise equality (xnor) of A and B\n assign PP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1];\n if (AB_SIGNED)\n assign GG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1];\n else if (_TECHMAP_CONSTMSK_P_[LCU_WIDTH-1]) // First compare for LUT if P (and G) is constant\n assign GG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1];\n else\n // Priority \"encoder\" that checks A[i] == 1'b1 && B[i] == 1'b0\n // from MSB down, deferring to less significant bits if the\n // MSBs are equal\n assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);\n (* force_downto *)\n wire [LCU_WIDTH-1:0] P_, G_;\n if (LCU_WIDTH == 1) begin\n // Propagate only if all pairs are equal\n // (inconclusive evidence to say A >= B)\n assign P_ = P[0] & PP;\n // Generate if any comparisons call for it\n assign G_ = G[0] | GG;\n end\n else begin\n // Propagate only if all pairs are equal\n // (inconclusive evidence to say A >= B)\n assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP};\n // Generate if any comparisons call for it\n assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG};\n end\n if (AB_WIDTH == 1)\n $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))\n _TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));\n else\n $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))\n _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));\n end\n end\nendgenerate\nendmodule\n",
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  "cmp2lut.v": "// Certain arithmetic operations between a signal of width n and a constant can be directly mapped\n// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process\n// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often\n// cannot be optimized further.\n//\n// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells\n// with n <= k inputs should be techmapped in this way, because this shortens the critical path\n// from n to 1 by avoiding carry chains.\n\n(* techmap_celltype = \"$lt $le $gt $ge\" *)\nmodule _90_lut_cmp_ (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\n(* force_downto *)\noutput [Y_WIDTH-1:0] Y;\n\nparameter _TECHMAP_CELLTYPE_ = \"\";\n\nparameter _TECHMAP_CONSTMSK_A_ = 0;\nparameter _TECHMAP_CONSTVAL_A_ = 0;\nparameter _TECHMAP_CONSTMSK_B_ = 0;\nparameter _TECHMAP_CONSTVAL_B_ = 0;\n\nfunction automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;\n\tinput integer width;\n\tinput integer operation;\n\tinput integer swap;\n\tinput integer sign;\n\tinput integer operand;\n\tinteger n, i_var, i_cst, lhs, rhs, o_bit;\n\tbegin\n\t\tgen_lut = width'b0;\n\t\tfor (n = 0; n < (1 << width); n++) begin\n\t\t\tif (sign)\n\t\t\t\ti_var = n[width-1:0];\n\t\t\telse\n\t\t\t\ti_var = n;\n\t\t\ti_cst = operand;\n\t\t\tif (swap) begin\n\t\t\t\tlhs = i_cst;\n\t\t\t\trhs = i_var;\n\t\t\tend else begin\n\t\t\t\tlhs = i_var;\n\t\t\t\trhs = i_cst;\n\t\t\tend\n\t\t\tif (operation == 0)\n\t\t\t\to_bit = (lhs < rhs);\n\t\t\tif (operation == 1)\n\t\t\t\to_bit = (lhs <= rhs);\n\t\t\tif (operation == 2)\n\t\t\t\to_bit = (lhs > rhs);\n\t\t\tif (operation == 3)\n\t\t\t\to_bit = (lhs >= rhs);\n\t\t\tgen_lut = gen_lut | (o_bit << n);\n\t\tend\n\tend\nendfunction\n\ngenerate\n\tlocalparam operation =\n\t\t_TECHMAP_CELLTYPE_ == \"$lt\" ? 0 :\n\t\t_TECHMAP_CELLTYPE_ == \"$le\" ? 1 :\n\t\t_TECHMAP_CELLTYPE_ == \"$gt\" ? 2 :\n\t\t_TECHMAP_CELLTYPE_ == \"$ge\" ? 3 :\n\t\t-1;\n\n\tif (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)\n\t\twire _TECHMAP_FAIL_ = 1;\n\telse if (&_TECHMAP_CONSTMSK_B_)\n\t\t\\$lut #(\n\t\t\t.WIDTH(A_WIDTH),\n\t\t\t.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(A),\n\t\t\t.Y(Y)\n\t\t);\n\telse if (&_TECHMAP_CONSTMSK_A_)\n\t\t\\$lut #(\n\t\t\t.WIDTH(B_WIDTH),\n\t\t\t.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })\n\t\t) _TECHMAP_REPLACE_ (\n\t\t\t.A(B),\n\t\t\t.Y(Y)\n\t\t);\n\telse\n\t\twire _TECHMAP_FAIL_ = 1;\nendgenerate\n\nendmodule\n",
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  "cmp2softlogic.v": "module constgtge(C, A, B, Y);\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\noutput Y;\ninput C;\n\nwire [A_WIDTH:0] ch;\ngenvar n;\ngenerate\n\tif (B_WIDTH > A_WIDTH) begin\n\t\t// Fail\n\tend else begin\n\t\tassign ch[0] = C;\n\t\tfor (n = 0; n < A_WIDTH; n = n + 1) begin\n\t\t\tif (n < B_WIDTH) begin\n\t\t\t\tassign ch[n + 1] = B[n] ? (ch[n] && A[n]) : (ch[n] || A[n]);\n\t\t\tend else begin\n\t\t\t\tassign ch[n + 1] = ch[n] || A[n];\n\t\t\tend\n\t\tend\n\t\tassign Y = ch[A_WIDTH];\n\tend\nendgenerate\nendmodule\n\nmodule constltle(C, A, B, Y);\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\noutput Y;\ninput C;\n\nwire [A_WIDTH:0] ch;\ngenvar n;\ngenerate\n\tif (B_WIDTH > A_WIDTH) begin\n\t\t// Fail\n\tend else begin\n\t\tassign ch[0] = C;\n\t\tfor (n = 0; n < A_WIDTH; n = n + 1) begin\n\t\t\tif (n < B_WIDTH) begin\n\t\t\t\tassign ch[n + 1] = !B[n] ? (ch[n] && !A[n]) : (ch[n] || !A[n]);\n\t\t\tend else begin\n\t\t\t\tassign ch[n + 1] = ch[n] && !A[n];\n\t\t\tend\n\t\tend\n\t\tassign Y = ch[A_WIDTH];\n\tend\nendgenerate\nendmodule\n\n(* techmap_celltype = \"$ge $gt $le $lt\" *)\nmodule _map_const_cmp_(A, B, Y);\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\n\n(* force_downto *)\ninput [A_WIDTH-1:0] A;\n(* force_downto *)\ninput [B_WIDTH-1:0] B;\n(* force_downto *)\noutput [Y_WIDTH-1:0] Y;\n\nparameter _TECHMAP_CELLTYPE_ = \"\";\n\nparameter _TECHMAP_CONSTMSK_A_ = 0;\nparameter _TECHMAP_CONSTVAL_A_ = 0;\nparameter _TECHMAP_CONSTMSK_B_ = 0;\nparameter _TECHMAP_CONSTVAL_B_ = 0;\n\nwire [1023:0] _TECHMAP_DO_ = \"opt -fast;\";\n\nwire [A_WIDTH:0] ch;\n\ngenvar n;\ngenerate\n\tif (Y_WIDTH != 1 || A_SIGNED || B_SIGNED)\n\t\twire _TECHMAP_FAIL_ = 1;\n\telse if (&_TECHMAP_CONSTMSK_A_) begin\n\t\tif (A_WIDTH > B_WIDTH)\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\telse if (_TECHMAP_CELLTYPE_ == \"$lt\" || _TECHMAP_CELLTYPE_ == \"$le\")\n\t\t\tconstgtge #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH))\n\t\t\t\t_TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y),\n\t\t\t\t\t.C(_TECHMAP_CELLTYPE_ == \"$lt\"));\n\t\telse\n\t\t\tconstltle #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH))\n\t\t\t\t_TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y),\n\t\t\t\t\t.C(_TECHMAP_CELLTYPE_ == \"$gt\"));\n\tend else if (&_TECHMAP_CONSTMSK_B_) begin\n\t\tif (B_WIDTH > A_WIDTH)\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\telse if (_TECHMAP_CELLTYPE_ == \"$lt\" || _TECHMAP_CELLTYPE_ == \"$le\")\n\t\t\tconstltle #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH))\n\t\t\t\t_TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y),\n\t\t\t\t\t.C(_TECHMAP_CELLTYPE_ == \"$le\"));\n\t\telse\n\t\t\tconstgtge #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH))\n\t\t\t\t_TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y),\n\t\t\t\t\t.C(_TECHMAP_CELLTYPE_ == \"$ge\"));\n\tend else\n\t\twire _TECHMAP_FAIL_ = 1;\nendgenerate\n\nendmodule\n",
@@ -57,7 +60,7 @@ export const filesystem = {
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  "brams.txt": "ram block $__EFINIX_5K_ {\n\tabits 12;\n\twidths 1 2 5 10 20 per_port;\n\tcost 32;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock anyedge;\n\t\trden;\n\t}\n\tport sw \"W\" {\n\t\tclock anyedge;\n\t\toption \"WRITE_MODE\" \"READ_FIRST\" {\n\t\t\twrtrans \"R\" old;\n\t\t}\n\t\toption \"WRITE_MODE\" \"WRITE_FIRST\" {\n\t\t\twrtrans \"R\" new;\n\t\t}\n\t}\n}\n",
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  "brams_map.v": "module $__EFINIX_5K_ (...);\n\tparameter INIT = 0;\n\tparameter OPTION_WRITE_MODE = \"READ_FIRST\";\n\n\tparameter PORT_R_WIDTH = 20;\n\tparameter PORT_R_CLK_POL = 1;\n\tparameter PORT_W_WIDTH = 20;\n\tparameter PORT_W_CLK_POL = 1;\n\n\tinput PORT_R_CLK;\n\tinput PORT_R_RD_EN;\n\tinput [11:0] PORT_R_ADDR;\n\toutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\n\tinput PORT_W_CLK;\n\tinput PORT_W_WR_EN;\n\tinput [11:0] PORT_W_ADDR;\n\tinput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\n\tlocalparam IS_5BIT = PORT_R_WIDTH >= 5 && PORT_W_WIDTH >= 5;\n\n\tlocalparam RADDR_WIDTH =\n\t\tPORT_R_WIDTH == 1 ? 12 :\n\t\tPORT_R_WIDTH == 2 ? 11 :\n\t\tPORT_R_WIDTH == 5 ? 10 :\n\t\tPORT_R_WIDTH == 10 ? 9 :\n\t\t8;\n\n\tlocalparam WADDR_WIDTH =\n\t\tPORT_W_WIDTH == 1 ? 12 :\n\t\tPORT_W_WIDTH == 2 ? 11 :\n\t\tPORT_W_WIDTH == 5 ? 10 :\n\t\tPORT_W_WIDTH == 10 ? 9 :\n\t\t8;\n\n\tlocalparam READ_WIDTH = \n\t\tPORT_R_WIDTH == 1 ? 1 :\n\t\tPORT_R_WIDTH == 2 ? 2 :\n\t\tPORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :\n\t\tPORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :\n\t\t(IS_5BIT ? 20 : 16);\n\n\tlocalparam WRITE_WIDTH = \n\t\tPORT_W_WIDTH == 1 ? 1 :\n\t\tPORT_W_WIDTH == 2 ? 2 :\n\t\tPORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :\n\t\tPORT_W_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :\n\t\t(IS_5BIT ? 20 : 16);\n\n\twire [RADDR_WIDTH-1:0] RADDR = PORT_R_ADDR[11:12-RADDR_WIDTH];\n\twire [WADDR_WIDTH-1:0] WADDR = PORT_W_ADDR[11:12-WADDR_WIDTH];\n\n\twire [WRITE_WIDTH-1:0] WDATA;\n\twire [READ_WIDTH-1:0] RDATA;\n\n\tgenerate\n\t\tcase (WRITE_WIDTH)\n\t\t1:\tassign WDATA = PORT_W_WR_DATA;\n\t\t2:\tassign WDATA = PORT_W_WR_DATA;\n\t\t4:\tassign WDATA = PORT_W_WR_DATA[3:0];\n\t\t5:\tassign WDATA = PORT_W_WR_DATA;\n\t\t8:\tassign WDATA = {\n\t\t\tPORT_W_WR_DATA[8:5],\n\t\t\tPORT_W_WR_DATA[3:0]\n\t\t};\n\t\t10:\tassign WDATA = PORT_W_WR_DATA;\n\t\t16:\tassign WDATA = {\n\t\t\tPORT_W_WR_DATA[18:15],\n\t\t\tPORT_W_WR_DATA[13:10],\n\t\t\tPORT_W_WR_DATA[8:5],\n\t\t\tPORT_W_WR_DATA[3:0]\n\t\t};\n\t\t20:\tassign WDATA = PORT_W_WR_DATA;\n\t\tendcase\n\t\tcase (READ_WIDTH)\n\t\t1:\tassign PORT_R_RD_DATA = RDATA;\n\t\t2:\tassign PORT_R_RD_DATA = RDATA;\n\t\t4:\tassign PORT_R_RD_DATA[3:0] = RDATA;\n\t\t5:\tassign PORT_R_RD_DATA = RDATA;\n\t\t8:\tassign {\n\t\t\tPORT_R_RD_DATA[8:5],\n\t\t\tPORT_R_RD_DATA[3:0]\n\t\t} = RDATA;\n\t\t10:\tassign PORT_R_RD_DATA = RDATA;\n\t\t16:\tassign {\n\t\t\tPORT_R_RD_DATA[18:15],\n\t\t\tPORT_R_RD_DATA[13:10],\n\t\t\tPORT_R_RD_DATA[8:5],\n\t\t\tPORT_R_RD_DATA[3:0]\n\t\t} = RDATA;\n\t\t20:\tassign PORT_R_RD_DATA = RDATA;\n\t\tendcase\n\tendgenerate\n\n\tfunction [255:0] init_slice;\n\t\tinput integer idx;\n\t\tinteger i;\n\t\tif (IS_5BIT)\n\t\t\tinit_slice = INIT[idx * 256 +: 256];\n\t\telse if (idx > 16)\n\t\t\tinit_slice = 0;\n\t\telse\n\t\t\tfor (i = 0; i < 64; i = i + 1)\n\t\t\t\tinit_slice[i*4+:4] = INIT[(idx * 64 + i) * 5+:4];\n\tendfunction\n\n\tEFX_RAM_5K #(\n\t\t.READ_WIDTH(READ_WIDTH),\n\t\t.WRITE_WIDTH(WRITE_WIDTH),\n\t\t.OUTPUT_REG(1'b0),\n\t\t.RCLK_POLARITY(PORT_R_CLK_POL),\n\t\t.RE_POLARITY(1'b1),\n\t\t.WCLK_POLARITY(PORT_W_CLK_POL),\n\t\t.WE_POLARITY(1'b1),\n\t\t.WCLKE_POLARITY(1'b1),\n\t\t.WRITE_MODE(OPTION_WRITE_MODE),\n\t\t.INIT_0(init_slice('h00)),\n\t\t.INIT_1(init_slice('h01)),\n\t\t.INIT_2(init_slice('h02)),\n\t\t.INIT_3(init_slice('h03)),\n\t\t.INIT_4(init_slice('h04)),\n\t\t.INIT_5(init_slice('h05)),\n\t\t.INIT_6(init_slice('h06)),\n\t\t.INIT_7(init_slice('h07)),\n\t\t.INIT_8(init_slice('h08)),\n\t\t.INIT_9(init_slice('h09)),\n\t\t.INIT_A(init_slice('h0a)),\n\t\t.INIT_B(init_slice('h0b)),\n\t\t.INIT_C(init_slice('h0c)),\n\t\t.INIT_D(init_slice('h0d)),\n\t\t.INIT_E(init_slice('h0e)),\n\t\t.INIT_F(init_slice('h0f)),\n\t\t.INIT_10(init_slice('h10)),\n\t\t.INIT_11(init_slice('h11)),\n\t\t.INIT_12(init_slice('h12)),\n\t\t.INIT_13(init_slice('h13)),\n\t) _TECHMAP_REPLACE_ (\n\t\t.WDATA(WDATA),\n\t\t.WADDR(WADDR),\n\t\t.WE(PORT_W_WR_EN),\n\t\t.WCLK(PORT_W_CLK),\n\t\t.WCLKE(1'b1),\n\t\t.RDATA(RDATA),\n\t\t.RADDR(RADDR),\n\t\t.RE(PORT_R_RD_EN),\n\t\t.RCLK(PORT_R_CLK)\n\t);\n\nendmodule\n",
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  "cells_map.v": "(* techmap_celltype = \"$_DFFE_[PN][PN][01][PN]_\" *)\nmodule \\$_DFFE_xxxx_ (input D, C, R, E, output Q);\n\n parameter _TECHMAP_CELLTYPE_ = \"\";\n\n EFX_FF #(\n .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == \"P\"),\n .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == \"P\"),\n .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == \"P\"),\n .D_POLARITY(1'b1),\n .SR_SYNC(1'b0),\n .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == \"1\"),\n .SR_SYNC_PRIORITY(1'b1)\n ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));\n\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n\nendmodule\n\n(* techmap_celltype = \"$_SDFFE_[PN][PN][01][PN]_\" *)\nmodule \\$_SDFFE_xxxx_ (input D, C, R, E, output Q);\n\n parameter _TECHMAP_CELLTYPE_ = \"\";\n\n EFX_FF #(\n .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == \"P\"),\n .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == \"P\"),\n .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == \"P\"),\n .D_POLARITY(1'b1),\n .SR_SYNC(1'b1),\n .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == \"1\"),\n .SR_SYNC_PRIORITY(1'b1)\n ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));\n\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n\nendmodule\n\n(* techmap_celltype = \"$_SDFFCE_[PN][PN][01][PN]_\" *)\nmodule \\$_SDFFCE_xxxx_ (input D, C, R, E, output Q);\n\n parameter _TECHMAP_CELLTYPE_ = \"\";\n\n EFX_FF #(\n .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == \"P\"),\n .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == \"P\"),\n .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == \"P\"),\n .D_POLARITY(1'b1),\n .SR_SYNC(1'b1),\n .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == \"1\"),\n .SR_SYNC_PRIORITY(1'b0)\n ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));\n\n wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;\n\nendmodule\n\nmodule \\$_DLATCH_N_ (E, D, Q);\n wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n input E, D;\n output Q = !E ? D : Q;\nendmodule\n\nmodule \\$_DLATCH_P_ (E, D, Q);\n wire [1023:0] _TECHMAP_DO_ = \"simplemap; opt\";\n input E, D;\n output Q = E ? D : Q;\nendmodule\n\n`ifndef NO_LUT\nmodule \\$lut (A, Y);\n parameter WIDTH = 0;\n parameter LUT = 0;\n\n (* force_downto *)\n input [WIDTH-1:0] A;\n output Y;\n\n generate\n if (WIDTH == 1) begin\n EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));\n end else\n if (WIDTH == 2) begin\n EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));\n end else\n if (WIDTH == 3) begin\n EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));\n end else\n if (WIDTH == 4) begin\n EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\n end else begin\n wire _TECHMAP_FAIL_ = 1;\n end\n endgenerate\nendmodule\n`endif\n",
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- "cells_sim.v": "module EFX_LUT4(\n output O, \n input I0,\n input I1,\n input I2,\n input I3\n);\n\tparameter LUTMASK = 16'h0000;\n\n\twire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];\n\twire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];\n\twire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];\n\tassign O = I0 ? s1[1] : s1[0];\t \nendmodule\n\nmodule EFX_ADD(\n output O,\n output CO,\n input I0,\n input I1,\n input CI\n);\n parameter I0_POLARITY = 1;\n parameter I1_POLARITY = 1;\n\n wire i0;\n wire i1;\n\n assign i0 = I0_POLARITY ? I0 : ~I0;\n assign i1 = I1_POLARITY ? I1 : ~I1;\n\n assign {CO, O} = i0 + i1 + CI;\nendmodule\n\nmodule EFX_FF(\n output reg Q,\n input D,\n input CE,\n (* clkbuf_sink *)\n input CLK,\n input SR\n);\n parameter CLK_POLARITY = 1;\n parameter CE_POLARITY = 1;\n parameter SR_POLARITY = 1;\n parameter SR_SYNC = 0;\n parameter SR_VALUE = 0;\n parameter SR_SYNC_PRIORITY = 0;\n parameter D_POLARITY = 1;\n\n wire clk;\n wire ce;\n wire sr;\n wire d;\n wire prio;\n wire sync;\n wire async;\n\n assign clk = CLK_POLARITY ? CLK : ~CLK;\n assign ce = CE_POLARITY ? CE : ~CE;\n assign sr = SR_POLARITY ? SR : ~SR;\n assign d = D_POLARITY ? D : ~D;\n\n\tinitial Q = 1'b0;\n\n generate\n \tif (SR_SYNC == 1) \n begin\n if (SR_SYNC_PRIORITY == 1) \n begin\n always @(posedge clk)\n if (sr)\n Q <= SR_VALUE;\n else if (ce)\n Q <= d;\n end\n else\n begin\n always @(posedge clk)\n if (ce)\n begin\n if (sr)\n Q <= SR_VALUE;\n else\n Q <= d;\n end\n end\n end\n else\n begin\n always @(posedge clk or posedge sr)\n if (sr)\n Q <= SR_VALUE;\n else if (ce)\n Q <= d;\n \n end\n endgenerate\nendmodule\n\nmodule EFX_GBUFCE(\n input CE,\n input I,\n (* clkbuf_driver *)\n output O\n);\n parameter CE_POLARITY = 1'b1;\n\n wire ce;\n assign ce = CE_POLARITY ? CE : ~CE;\n \n assign O = I & ce;\n \nendmodule\n\nmodule EFX_RAM_5K(\n input [WRITE_WIDTH-1:0] WDATA,\n input [WRITE_ADDR_WIDTH-1:0] WADDR,\n input WE, \n (* clkbuf_sink *)\n input WCLK,\n input WCLKE, \n output [READ_WIDTH-1:0] RDATA, \n input [READ_ADDR_WIDTH-1:0] RADDR,\n input RE, \n (* clkbuf_sink *)\n input RCLK\n);\n parameter READ_WIDTH = 20;\n parameter WRITE_WIDTH = 20;\n parameter OUTPUT_REG = 1'b0;\n parameter RCLK_POLARITY = 1'b1;\n parameter RE_POLARITY = 1'b1;\n parameter WCLK_POLARITY = 1'b1;\n parameter WE_POLARITY = 1'b1;\n parameter WCLKE_POLARITY = 1'b1;\n parameter WRITE_MODE = \"READ_FIRST\";\n parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\n localparam READ_ADDR_WIDTH = \n\t\t\t (READ_WIDTH == 16) ? 8 : // 256x16\n\t\t\t (READ_WIDTH == 8) ? 9 : // 512x8\n\t\t\t (READ_WIDTH == 4) ? 10 : // 1024x4\n\t\t\t (READ_WIDTH == 2) ? 11 : // 2048x2\n\t\t\t (READ_WIDTH == 1) ? 12 : // 4096x1\n\t\t\t (READ_WIDTH == 20) ? 8 : // 256x20\n\t\t\t (READ_WIDTH == 10) ? 9 : // 512x10\n\t\t\t (READ_WIDTH == 5) ? 10 : -1; // 1024x5\n \n localparam WRITE_ADDR_WIDTH = \n\t\t\t (WRITE_WIDTH == 16) ? 8 : // 256x16\n\t\t\t (WRITE_WIDTH == 8) ? 9 : // 512x8\n\t\t\t (WRITE_WIDTH == 4) ? 10 : // 1024x4\n\t\t\t (WRITE_WIDTH == 2) ? 11 : // 2048x2\n\t\t\t (WRITE_WIDTH == 1) ? 12 : // 4096x1\n\t\t\t (WRITE_WIDTH == 20) ? 8 : // 256x20\n\t\t\t (WRITE_WIDTH == 10) ? 9 : // 512x10\n\t\t\t (WRITE_WIDTH == 5) ? 10 : -1; // 1024x5\n \nendmodule\n",
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+ "cells_sim.v": "module EFX_LUT4(\n output O, \n input I0,\n input I1,\n input I2,\n input I3\n);\n\tparameter LUTMASK = 16'h0000;\n\n\twire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];\n\twire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];\n\twire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];\n\tassign O = I0 ? s1[1] : s1[0];\t \nendmodule\n\nmodule EFX_ADD(\n output O,\n output CO,\n input I0,\n input I1,\n input CI\n);\n parameter I0_POLARITY = 1;\n parameter I1_POLARITY = 1;\n\n wire i0;\n wire i1;\n\n assign i0 = I0_POLARITY ? I0 : ~I0;\n assign i1 = I1_POLARITY ? I1 : ~I1;\n\n assign {CO, O} = i0 + i1 + CI;\nendmodule\n\nmodule EFX_FF(\n output reg Q,\n input D,\n input CE,\n (* clkbuf_sink *)\n input CLK,\n input SR\n);\n parameter CLK_POLARITY = 1;\n parameter CE_POLARITY = 1;\n parameter SR_POLARITY = 1;\n parameter SR_SYNC = 0;\n parameter SR_VALUE = 0;\n parameter SR_SYNC_PRIORITY = 0;\n parameter D_POLARITY = 1;\n\n wire clk;\n wire ce;\n wire sr;\n wire d;\n wire prio;\n wire sync;\n wire async;\n\n assign clk = CLK_POLARITY ? CLK : ~CLK;\n assign ce = CE_POLARITY ? CE : ~CE;\n assign sr = SR_POLARITY ? SR : ~SR;\n assign d = D_POLARITY ? D : ~D;\n\n\tinitial Q = 1'b0;\n\n generate\n \tif (SR_SYNC == 1) \n begin\n if (SR_SYNC_PRIORITY == 1) \n begin\n always @(posedge clk)\n if (sr)\n Q <= SR_VALUE;\n else if (ce)\n Q <= d;\n end\n else\n begin\n always @(posedge clk)\n if (ce)\n begin\n if (sr)\n Q <= SR_VALUE;\n else\n Q <= d;\n end\n end\n end\n else\n begin\n always @(posedge clk or posedge sr)\n if (sr)\n Q <= SR_VALUE;\n else if (ce)\n Q <= d;\n \n end\n endgenerate\nendmodule\n\nmodule EFX_GBUFCE(\n input CE,\n input I,\n (* clkbuf_driver *)\n output O\n);\n parameter CE_POLARITY = 1'b1;\n\n wire ce;\n assign ce = CE_POLARITY ? CE : ~CE;\n \n assign O = I & ce;\n \nendmodule\n\nmodule EFX_RAM_5K\n# (\n parameter READ_WIDTH = 20,\n parameter WRITE_WIDTH = 20,\n localparam READ_ADDR_WIDTH = \n\t\t\t (READ_WIDTH == 16) ? 8 : // 256x16\n\t\t\t (READ_WIDTH == 8) ? 9 : // 512x8\n\t\t\t (READ_WIDTH == 4) ? 10 : // 1024x4\n\t\t\t (READ_WIDTH == 2) ? 11 : // 2048x2\n\t\t\t (READ_WIDTH == 1) ? 12 : // 4096x1\n\t\t\t (READ_WIDTH == 20) ? 8 : // 256x20\n\t\t\t (READ_WIDTH == 10) ? 9 : // 512x10\n\t\t\t (READ_WIDTH == 5) ? 10 : -1, // 1024x5\n \n localparam WRITE_ADDR_WIDTH = \n\t\t\t (WRITE_WIDTH == 16) ? 8 : // 256x16\n\t\t\t (WRITE_WIDTH == 8) ? 9 : // 512x8\n\t\t\t (WRITE_WIDTH == 4) ? 10 : // 1024x4\n\t\t\t (WRITE_WIDTH == 2) ? 11 : // 2048x2\n\t\t\t (WRITE_WIDTH == 1) ? 12 : // 4096x1\n\t\t\t (WRITE_WIDTH == 20) ? 8 : // 256x20\n\t\t\t (WRITE_WIDTH == 10) ? 9 : // 512x10\n\t\t\t (WRITE_WIDTH == 5) ? 10 : -1 // 1024x5\n)\n(\n input [WRITE_WIDTH-1:0] WDATA,\n input [WRITE_ADDR_WIDTH-1:0] WADDR,\n input WE, \n (* clkbuf_sink *)\n input WCLK,\n input WCLKE, \n output [READ_WIDTH-1:0] RDATA, \n input [READ_ADDR_WIDTH-1:0] RADDR,\n input RE, \n (* clkbuf_sink *)\n input RCLK\n);\n parameter OUTPUT_REG = 1'b0;\n parameter RCLK_POLARITY = 1'b1;\n parameter RE_POLARITY = 1'b1;\n parameter WCLK_POLARITY = 1'b1;\n parameter WE_POLARITY = 1'b1;\n parameter WCLKE_POLARITY = 1'b1;\n parameter WRITE_MODE = \"READ_FIRST\";\n parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nendmodule\n",
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  "gbuf_map.v": "module \\$__EFX_GBUF (input I, output O);\n EFX_GBUFCE #(.CE_POLARITY(1'b1)) _TECHMAP_REPLACE_ (.I(I), .O(O), .CE(1'b1));\nendmodule\n",
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  },
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  "fabulous": {
@@ -165,19 +168,20 @@ export const filesystem = {
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  "fmt.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n// $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tTIME = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n// \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tLITERAL \t= 0,\n\t\tINTEGER \t= 1,\n\t\tSTRING = 2,\n\t\tUNICHAR = 3,\n\t\tVLOG_TIME = 4,\n\t} type;\n\n\t// LITERAL type\n\tstd::string str;\n\n\t// INTEGER/STRING/UNICHAR types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/STRING/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t\tNUMERIC\t= 2,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tenum {\n\t\tMINUS\t\t= 0,\n\t\tPLUS_MINUS\t= 1,\n\t\tSPACE_MINUS\t= 2,\n\t} sign = MINUS;\n\tbool hex_upper = false;\n\tbool show_base = false;\n\tbool group = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_literal(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <vector>\n\n#include <stdint.h>\n\nnamespace hashlib {\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\n// The XOR version of DJB2\ninline unsigned int mkhash(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) ^ b;\n}\n\n// traditionally 5381 is used as starting value for the djb2 hash\nconst unsigned int mkhash_init = 5381;\n\n// The ADD version of DJB2\n// (use this version for cache locality in b)\ninline unsigned int mkhash_add(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) + b;\n}\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\ntemplate<typename T> struct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const T &a) {\n\t\treturn a.hash();\n\t}\n};\n\nstruct hash_int_ops {\n\ttemplate<typename T>\n\tstatic inline bool cmp(T a, T b) {\n\t\treturn a == b;\n\t}\n};\n\ntemplate<> struct hash_ops<bool> : hash_int_ops\n{\n\tstatic inline unsigned int hash(bool a) {\n\t\treturn a ? 1 : 0;\n\t}\n};\ntemplate<> struct hash_ops<int32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<int64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\ntemplate<> struct hash_ops<uint32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<uint64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\n\ntemplate<> struct hash_ops<std::string> {\n\tstatic inline bool cmp(const std::string &a, const std::string &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const std::string &a) {\n\t\tunsigned int v = 0;\n\t\tfor (auto c : a)\n\t\t\tv = mkhash(v, c);\n\t\treturn v;\n\t}\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::pair<P, Q> a) {\n\t\treturn mkhash(hash_ops<P>::hash(a.first), hash_ops<Q>::hash(a.second));\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), unsigned int>::type hash(std::tuple<T...>) {\n\t\treturn mkhash_init;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), unsigned int>::type hash(std::tuple<T...> a) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\treturn mkhash(hash<I+1>(a), element_ops_t::hash(std::get<I>(a)));\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::vector<T> a) {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto k : a)\n\t\t\th = mkhash(h, hash_ops<T>::hash(k));\n\t\treturn h;\n\t}\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\tfor (int i = 0; a[i] || b[i]; i++)\n\t\t\tif (a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\tstatic inline unsigned int hash(const char *a) {\n\t\tunsigned int hash = mkhash_init;\n\t\twhile (*a)\n\t\t\thash = mkhash(hash, *(a++));\n\t\treturn hash;\n\t}\n};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const void *a) {\n\t\treturn (uintptr_t)a;\n\t}\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\tstatic inline unsigned int hash(const T *a) {\n\t\treturn a ? a->hash() : 0;\n\t}\n};\n\ntemplate<typename T>\ninline unsigned int mkhash(const T &v) {\n\treturn hash_ops<T>().hash(v);\n}\n\ninline int hashtable_size(int min_size)\n{\n\tstatic std::vector<int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict\n{\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tint hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto &entry : entries) {\n\t\t\th ^= hash_ops<K>::hash(entry.udata.first);\n\t\t\th ^= hash_ops<T>::hash(entry.udata.second);\n\t\t}\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tint hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int hashval = mkhash_init;\n\t\tfor (auto &it : entries)\n\t\t\thashval ^= ops.hash(it.udata);\n\t\treturn hashval;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0, OPS>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
167
170
  "json.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n enum Scope {\n VALUE,\n OBJECT_FIRST,\n OBJECT,\n ARRAY_FIRST,\n ARRAY,\n };\n\n struct Target {\n virtual void emit(const char *data) = 0;\n virtual void flush() {};\n virtual ~Target() {};\n };\n\n std::string newline_indent = \"\\n\";\n std::vector<std::unique_ptr<Target>> targets;\n std::vector<Scope> state = {VALUE};\n int compact_depth = INT_MAX;\npublic:\n\n void emit_to_log();\n void append_to_string(std::string &target);\n bool write_to_file(const std::string &path);\n\n bool active() { return !targets.empty(); }\n\n void compact() { compact_depth = GetSize(state); }\n\n void line(bool space_if_inline = true);\n void raw(const char *raw_json);\n void flush();\n void begin_object();\n void begin_array();\n void end_object();\n void end_array();\n void name(const char *name);\n void begin_value();\n void end_value();\n void value_json(const Json &value);\n void value(unsigned int value) { value_json(Json((int)value)); }\n template<typename T>\n void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n void entry_json(const char *name, const Json &value);\n void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n template<typename T>\n void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n template<typename T>\n void object(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n entry(item.first, item.second);\n end_object();\n }\n\n template<typename T>\n void array(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n value(item);\n end_object();\n }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
168
- "log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"kernel/yosys.h\"\n\n#ifndef LOG_H\n#define LOG_H\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T, typename OPS> static inline void log_dump_val_worker(dict<K, T, OPS> &v);\ntemplate<typename K, typename OPS> static inline void log_dump_val_worker(pool<K, OPS> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T, typename OPS>\nstatic inline void log_dump_val_worker(dict<K, T, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K, typename OPS>\nstatic inline void log_dump_val_worker(pool<K, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
171
+ "log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef LOG_H\n#define LOG_H\n\n#include \"kernel/yosys_common.h\"\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T, typename OPS> static inline void log_dump_val_worker(dict<K, T, OPS> &v);\ntemplate<typename K, typename OPS> static inline void log_dump_val_worker(pool<K, OPS> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T, typename OPS>\nstatic inline void log_dump_val_worker(dict<K, T, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K, typename OPS>\nstatic inline void log_dump_val_worker(pool<K, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/yosys.h\"\n\n#endif\n",
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  "macc.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MACC_H\n#define MACC_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Macc\n{\n\tstruct port_t {\n\t\tRTLIL::SigSpec in_a, in_b;\n\t\tbool is_signed, do_subtract;\n\t};\n\n\tstd::vector<port_t> ports;\n\tRTLIL::SigSpec bit_ports;\n\n\tvoid optimize(int width)\n\t{\n\t\tstd::vector<port_t> new_ports;\n\t\tRTLIL::SigSpec new_bit_ports;\n\t\tRTLIL::Const off(0, width);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (GetSize(port.in_a) < GetSize(port.in_b))\n\t\t\t\tstd::swap(port.in_a, port.in_b);\n\n\t\t\tif (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {\n\t\t\t\tbit_ports.append(port.in_a);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {\n\t\t\t\tRTLIL::Const v = port.in_a.as_const();\n\t\t\t\tif (GetSize(port.in_b))\n\t\t\t\t\tv = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);\n\t\t\t\tif (port.do_subtract)\n\t\t\t\t\toff = const_sub(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\telse\n\t\t\t\t\toff = const_add(off, v, port.is_signed, port.is_signed, width);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (port.is_signed) {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t} else {\n\t\t\t\twhile (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)\n\t\t\t\t\tport.in_a.remove(GetSize(port.in_a)-1);\n\t\t\t\twhile (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)\n\t\t\t\t\tport.in_b.remove(GetSize(port.in_b)-1);\n\t\t\t}\n\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tfor (auto &bit : bit_ports)\n\t\t\tif (bit == State::S1)\n\t\t\t\toff = const_add(off, RTLIL::Const(1, width), false, false, width);\n\t\t\telse if (bit != State::S0)\n\t\t\t\tnew_bit_ports.append(bit);\n\n\t\tif (off.as_bool()) {\n\t\t\tport_t port;\n\t\t\tport.in_a = off;\n\t\t\tport.is_signed = false;\n\t\t\tport.do_subtract = false;\n\t\t\tnew_ports.push_back(port);\n\t\t}\n\n\t\tnew_ports.swap(ports);\n\t\tbit_ports = new_bit_ports;\n\t}\n\n\tvoid from_cell(RTLIL::Cell *cell)\n\t{\n\t\tRTLIL::SigSpec port_a = cell->getPort(ID::A);\n\n\t\tports.clear();\n\t\tbit_ports = cell->getPort(ID::B);\n\n\t\tstd::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;\n\t\tint config_cursor = 0;\n\n\t\tint config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();\n\t\tlog_assert(GetSize(config_bits) >= config_width);\n\n\t\tint num_bits = 0;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 1;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 2;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 4;\n\t\tif (config_bits[config_cursor++] == State::S1) num_bits |= 8;\n\n\t\tint port_a_cursor = 0;\n\t\twhile (port_a_cursor < GetSize(port_a))\n\t\t{\n\t\t\tlog_assert(config_cursor + 2 + 2*num_bits <= config_width);\n\n\t\t\tport_t this_port;\n\t\t\tthis_port.is_signed = config_bits[config_cursor++] == State::S1;\n\t\t\tthis_port.do_subtract = config_bits[config_cursor++] == State::S1;\n\n\t\t\tint size_a = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_a |= 1 << i;\n\n\t\t\tthis_port.in_a = port_a.extract(port_a_cursor, size_a);\n\t\t\tport_a_cursor += size_a;\n\n\t\t\tint size_b = 0;\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tif (config_bits[config_cursor++] == State::S1)\n\t\t\t\t\tsize_b |= 1 << i;\n\n\t\t\tthis_port.in_b = port_a.extract(port_a_cursor, size_b);\n\t\t\tport_a_cursor += size_b;\n\n\t\t\tif (size_a || size_b)\n\t\t\t\tports.push_back(this_port);\n\t\t}\n\n\t\tlog_assert(config_cursor == config_width);\n\t\tlog_assert(port_a_cursor == GetSize(port_a));\n\t}\n\n\tvoid to_cell(RTLIL::Cell *cell) const\n\t{\n\t\tRTLIL::SigSpec port_a;\n\t\tstd::vector<RTLIL::State> config_bits;\n\t\tint max_size = 0, num_bits = 0;\n\n\t\tfor (auto &port : ports) {\n\t\t\tmax_size = max(max_size, GetSize(port.in_a));\n\t\t\tmax_size = max(max_size, GetSize(port.in_b));\n\t\t}\n\n\t\twhile (max_size)\n\t\t\tnum_bits++, max_size /= 2;\n\n\t\tlog_assert(num_bits < 16);\n\t\tconfig_bits.push_back(num_bits & 1 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 2 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 4 ? State::S1 : State::S0);\n\t\tconfig_bits.push_back(num_bits & 8 ? State::S1 : State::S0);\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (GetSize(port.in_a) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tconfig_bits.push_back(port.is_signed ? State::S1 : State::S0);\n\t\t\tconfig_bits.push_back(port.do_subtract ? State::S1 : State::S0);\n\n\t\t\tint size_a = GetSize(port.in_a);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tint size_b = GetSize(port.in_b);\n\t\t\tfor (int i = 0; i < num_bits; i++)\n\t\t\t\tconfig_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);\n\n\t\t\tport_a.append(port.in_a);\n\t\t\tport_a.append(port.in_b);\n\t\t}\n\n\t\tcell->setPort(ID::A, port_a);\n\t\tcell->setPort(ID::B, bit_ports);\n\t\tcell->setParam(ID::CONFIG, config_bits);\n\t\tcell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));\n\t\tcell->setParam(ID::A_WIDTH, GetSize(port_a));\n\t\tcell->setParam(ID::B_WIDTH, GetSize(bit_ports));\n\t}\n\n\tbool eval(RTLIL::Const &result) const\n\t{\n\t\tfor (auto &bit : result.bits)\n\t\t\tbit = State::S0;\n\n\t\tfor (auto &port : ports)\n\t\t{\n\t\t\tif (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())\n\t\t\t\treturn false;\n\n\t\t\tRTLIL::Const summand;\n\t\t\tif (GetSize(port.in_b) == 0)\n\t\t\t\tsummand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tsummand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));\n\n\t\t\tif (port.do_subtract)\n\t\t\t\tresult = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t\telse\n\t\t\t\tresult = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));\n\t\t}\n\n\t\tfor (auto bit : bit_ports) {\n\t\t\tif (bit.wire)\n\t\t\t\treturn false;\n\t\t\tresult = const_add(result, bit.data, false, false, GetSize(result));\n\t\t}\n\n\t\treturn true;\n\t}\n\n\tMacc(RTLIL::Cell *cell = nullptr)\n\t{\n\t\tif (cell != nullptr)\n\t\t\tfrom_cell(cell);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "mem.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MEM_H\n#define MEM_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct MemRd : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity, ce_over_srst;\n\tConst arst_value, srst_value, init_value;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will bypass the written data\n\t// to this port's output (default behavior is to read old value).\n\t// Can only be set for write ports that have the same clock domain.\n\tstd::vector<bool> transparency_mask;\n\t// One bit for every write port, true iff simultanous read on this\n\t// port and write on the other port will return an all-X (don't care)\n\t// value. Mutually exclusive with transparency_mask.\n\t// Can only be set for write ports that have the same clock domain.\n\t// For optimization purposes, this will also be set if we can\n\t// determine that the two ports can never be active simultanously\n\t// (making the above vacuously true).\n\tstd::vector<bool> collision_x_mask;\n\tSigSpec clk, en, arst, srst, addr, data;\n\n\tMemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n};\n\nstruct MemWr : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tint wide_log2;\n\tbool clk_enable, clk_polarity;\n\tstd::vector<bool> priority_mask;\n\tSigSpec clk, en, addr, data;\n\n\tMemWr() : removed(false), cell(nullptr) {}\n\n\t// Returns the address of given subword index accessed by this port.\n\tSigSpec sub_addr(int sub) {\n\t\tSigSpec res = addr;\n\t\tfor (int i = 0; i < wide_log2; i++)\n\t\t\tres[i] = State(sub >> i & 1);\n\t\treturn res;\n\t}\n\n\tstd::pair<SigSpec, std::vector<int>> compress_en();\n\tSigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig);\n};\n\nstruct MemInit : RTLIL::AttrObject {\n\tbool removed;\n\tCell *cell;\n\tConst addr;\n\tConst data;\n\tConst en;\n\tMemInit() : removed(false), cell(nullptr) {}\n};\n\nstruct Mem : RTLIL::AttrObject {\n\tModule *module;\n\tIdString memid;\n\tbool packed;\n\tRTLIL::Memory *mem;\n\tCell *cell;\n\tint width, start_offset, size;\n\tstd::vector<MemInit> inits;\n\tstd::vector<MemRd> rd_ports;\n\tstd::vector<MemWr> wr_ports;\n\n\t// Removes this memory from the module. The data in helper structures\n\t// is unaffected except for the cell/mem fields.\n\tvoid remove();\n\n\t// Commits all changes in helper structures into the module — ports and\n\t// inits marked as removed are actually removed, new ports/inits create\n\t// new cells, modified port/inits are commited into their existing\n\t// cells. Note that this reindexes the ports and inits array (actually\n\t// removing the ports/inits marked as removed).\n\tvoid emit();\n\n\t// Marks all inits as removed.\n\tvoid clear_inits();\n\n\t// Coalesces inits: whenever two inits have overlapping or touching\n\t// address ranges, they are combined into one, with the higher-priority\n\t// one's data overwriting the other. Running this results in\n\t// an inits list equivalent to the original, in which all entries\n\t// cover disjoint (and non-touching) address ranges, and all enable\n\t// masks are all-1.\n\tvoid coalesce_inits();\n\n\t// Checks consistency of this memory and all its ports/inits, using\n\t// log_assert.\n\tvoid check();\n\n\t// Gathers all initialization data into a single big const covering\n\t// the whole memory. For all non-initialized bits, Sx will be returned.\n\tConst get_init_data() const;\n\n\t// Constructs and returns the helper structures for all memories\n\t// in a module.\n\tstatic std::vector<Mem> get_all_memories(Module *module);\n\n\t// Constructs and returns the helper structures for all selected\n\t// memories in a module.\n\tstatic std::vector<Mem> get_selected_memories(Module *module);\n\n\t// Converts a synchronous read port into an asynchronous one by\n\t// extracting the data (or, in some rare cases, address) register\n\t// into a separate cell, together with any soft-transparency\n\t// logic necessary to preserve its semantics. Returns the created\n\t// register cell, if any. Note that in some rare cases this function\n\t// may succeed and perform a conversion without creating a new\n\t// register — a nullptr result doesn't imply nothing was done.\n\tCell *extract_rdff(int idx, FfInitVals *initvals);\n\n\t// Splits all wide ports in this memory into equivalent narrow ones.\n\t// This function performs no modifications at all to the actual\n\t// netlist unless and until emit() is called.\n\tvoid narrow();\n\n\t// If write port idx2 currently has priority over write port idx1,\n\t// inserts extra logic on idx1's enable signal to disable writes\n\t// when idx2 is writing to the same address, then removes the priority\n\t// from the priority mask. If there is a memory port that is\n\t// transparent with idx1, but not with idx2, that port is converted\n\t// to use soft transparency logic.\n\tvoid emulate_priority(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Creates soft-transparency logic on read port ridx, bypassing the\n\t// data from write port widx. Should only be called when ridx is\n\t// transparent wrt widx in the first place. Once we're done, the\n\t// transparency_mask bit will be cleared, and the collision_x_mask\n\t// bit will be set instead (since whatever value is read will be\n\t// replaced by the soft transparency logic).\n\tvoid emulate_transparency(int widx, int ridx, FfInitVals *initvals);\n\n\t// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).\n\t// Specifically, takes care of priority masks: any priority relations\n\t// that idx2 had are replicated onto idx1, unless they conflict with\n\t// priorities already present on idx1, in which case emulate_priority\n\t// is called. Likewise, ensures transparency and undefined collision\n\t// masks of all read ports have the same values for both ports,\n\t// calling emulate_transparency if necessary.\n\tvoid prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares for merging read port idx2 into idx1.\n\t// Specifically, makes sure the transparency and undefined collision\n\t// masks of both ports are equal, by changing undefined behavior\n\t// of one port to the other's defined behavior, or by calling\n\t// emulate_transparency if necessary.\n\tvoid prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals);\n\n\t// Prepares the memory for widening a port to a given width. This\n\t// involves ensuring that start_offset and size are aligned to the\n\t// target width.\n\tvoid widen_prep(int wide_log2);\n\n\t// Widens a write port up to a given width. The newly port is\n\t// equivalent to the original, made by replicating enable/data bits\n\t// and masking enable bits with decoders on the low part of the\n\t// original address.\n\tvoid widen_wr_port(int idx, int wide_log2);\n\n\t// Emulates a sync read port's enable functionality in soft logic,\n\t// changing the actual read port's enable to be always-on.\n\tvoid emulate_rden(int idx, FfInitVals *initvals);\n\n\t// Emulates a sync read port's initial/reset value functionality in\n\t// soft logic, removing it from the actual read port.\n\tvoid emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals);\n\n\t// Given a read port with ce_over_srst set, converts it to a port\n\t// with ce_over_srst unset without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_ce_over_srst(int idx);\n\n\t// Given a read port with ce_over_srst unset, converts it to a port\n\t// with ce_over_srst set without changing its behavior by adding\n\t// emulation logic.\n\tvoid emulate_rd_srst_over_ce(int idx);\n\n\t// Returns true iff emulate_read_first makes sense to call.\n\tbool emulate_read_first_ok();\n\n\t// Emulates all read-first read-write port relationships in terms of\n\t// all-transparent ports, by delaying all write ports by one cycle.\n\t// This can only be used when all read ports and all write ports are\n\t// in the same clock domain.\n\tvoid emulate_read_first(FfInitVals *initvals);\n\n\tMem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "modtools.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef MODTOOLS_H\n#define MODTOOLS_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct ModIndex : public RTLIL::Monitor\n{\n\tstruct PortInfo {\n\t\tRTLIL::Cell* cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tPortInfo() : cell(), port(), offset() { }\n\t\tPortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }\n\n\t\tbool operator<(const PortInfo &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (offset != other.offset)\n\t\t\t\treturn offset < other.offset;\n\t\t\treturn port < other.port;\n\t\t}\n\n\t\tbool operator==(const PortInfo &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t\t}\n\t};\n\n\tstruct SigBitInfo\n\t{\n\t\tbool is_input, is_output;\n\t\tpool<PortInfo> ports;\n\n\t\tSigBitInfo() : is_input(false), is_output(false) { }\n\n\t\tbool operator==(const SigBitInfo &other) const {\n\t\t\treturn is_input == other.is_input && is_output == other.is_output && ports == other.ports;\n\t\t}\n\n\t\tvoid merge(const SigBitInfo &other)\n\t\t{\n\t\t\tis_input = is_input || other.is_input;\n\t\t\tis_output = is_output || other.is_output;\n\t\t\tports.insert(other.ports.begin(), other.ports.end());\n\t\t}\n\t};\n\n\tSigMap sigmap;\n\tRTLIL::Module *module;\n\tstd::map<RTLIL::SigBit, SigBitInfo> database;\n\tint auto_reload_counter;\n\tbool auto_reload_module;\n\n\tvoid port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.insert(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tvoid port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (int i = 0; i < GetSize(sig); i++) {\n\t\t\tRTLIL::SigBit bit = sigmap(sig[i]);\n\t\t\tif (bit.wire)\n\t\t\t\tdatabase[bit].ports.erase(PortInfo(cell, port, i));\n\t\t}\n\t}\n\n\tconst SigBitInfo &info(RTLIL::SigBit bit)\n\t{\n\t\treturn database[sigmap(bit)];\n\t}\n\n\tvoid reload_module(bool reset_sigmap = true)\n\t{\n\t\tif (reset_sigmap) {\n\t\t\tsigmap.clear();\n\t\t\tsigmap.set(module);\n\t\t}\n\n\t\tdatabase.clear();\n\t\tfor (auto wire : module->wires())\n\t\t\tif (wire->port_input || wire->port_output)\n\t\t\t\tfor (int i = 0; i < GetSize(wire); i++) {\n\t\t\t\t\tRTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));\n\t\t\t\t\tif (bit.wire && wire->port_input)\n\t\t\t\t\t\tdatabase[bit].is_input = true;\n\t\t\t\t\tif (bit.wire && wire->port_output)\n\t\t\t\t\t\tdatabase[bit].is_output = true;\n\t\t\t\t}\n\t\tfor (auto cell : module->cells())\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tport_add(cell, conn.first, conn.second);\n\n\t\tif (auto_reload_module) {\n\t\t\tif (++auto_reload_counter > 2)\n\t\t\t\tlog_warning(\"Auto-reload in ModIndex -- possible performance bug!\\n\");\n\t\t\tauto_reload_module = false;\n\t\t}\n\t}\n\n\tvoid check()\n\t{\n#ifndef NDEBUG\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (auto it : database)\n\t\t\tlog_assert(it.first == sigmap(it.first));\n\n\t\tauto database_bak = std::move(database);\n\t\treload_module(false);\n\n\t\tif (!(database == database_bak))\n\t\t{\n\t\t\tfor (auto &it : database_bak)\n\t\t\t\tif (!database.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database_bak, not database: %s\\n\", log_signal(it.first));\n\n\t\t\tfor (auto &it : database)\n\t\t\t\tif (!database_bak.count(it.first))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Only in database, not database_bak: %s\\n\", log_signal(it.first));\n\t\t\t\telse if (!(it.second == database_bak.at(it.first)))\n\t\t\t\t\tlog(\"ModuleIndex::check(): Different content for database[%s].\\n\", log_signal(it.first));\n\n\t\t\tlog_assert(database == database_bak);\n\t\t}\n#endif\n\t}\n\n\tvoid notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override\n\t{\n\t\tlog_assert(module == cell->module);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tport_del(cell, port, old_sig);\n\t\tport_add(cell, port, sig);\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override\n\t{\n\t\tlog_assert(module == mod);\n\n\t\tif (auto_reload_module)\n\t\t\treturn;\n\n\t\tfor (int i = 0; i < GetSize(sigsig.first); i++)\n\t\t{\n\t\t\tRTLIL::SigBit lhs = sigmap(sigsig.first[i]);\n\t\t\tRTLIL::SigBit rhs = sigmap(sigsig.second[i]);\n\t\t\tbool has_lhs = database.count(lhs) != 0;\n\t\t\tbool has_rhs = database.count(rhs) != 0;\n\n\t\t\tif (!has_lhs && !has_rhs) {\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t} else\n\t\t\tif (!has_rhs) {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\tlhs = sigmap(lhs);\n\t\t\t\tif (lhs.wire)\n\t\t\t\t\tdatabase[lhs] = new_info;\n\t\t\t} else\n\t\t\tif (!has_lhs) {\n\t\t\t\tSigBitInfo new_info = database.at(rhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t} else {\n\t\t\t\tSigBitInfo new_info = database.at(lhs);\n\t\t\t\tnew_info.merge(database.at(rhs));\n\t\t\t\tdatabase.erase(lhs);\n\t\t\t\tdatabase.erase(rhs);\n\t\t\t\tsigmap.add(lhs, rhs);\n\t\t\t\trhs = sigmap(rhs);\n\t\t\t\tif (rhs.wire)\n\t\t\t\t\tdatabase[rhs] = new_info;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tvoid notify_blackout(RTLIL::Module *mod) override\n\t{\n\t\tlog_assert(module == mod);\n\t\tauto_reload_module = true;\n\t}\n\n\tModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)\n\t{\n\t\tauto_reload_counter = 0;\n\t\tauto_reload_module = true;\n\t\tmodule->monitors.insert(this);\n\t}\n\n\t~ModIndex()\n\t{\n\t\tmodule->monitors.erase(this);\n\t}\n\n\tSigBitInfo *query(RTLIL::SigBit bit)\n\t{\n\t\tif (auto_reload_module)\n\t\t\treload_module();\n\n\t\tauto it = database.find(sigmap(bit));\n\t\tif (it == database.end())\n\t\t\treturn nullptr;\n\t\telse\n\t\t\treturn &it->second;\n\t}\n\n\tbool query_is_input(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_input;\n\t}\n\n\tbool query_is_output(RTLIL::SigBit bit)\n\t{\n\t\tconst SigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn false;\n\t\treturn info->is_output;\n\t}\n\n\tpool<PortInfo> &query_ports(RTLIL::SigBit bit)\n\t{\n\t\tstatic pool<PortInfo> empty_result_set;\n\t\tSigBitInfo *info = query(bit);\n\t\tif (info == nullptr)\n\t\t\treturn empty_result_set;\n\t\treturn info->ports;\n\t}\n\n\tvoid dump_db()\n\t{\n\t\tlog(\"--- ModIndex Dump ---\\n\");\n\n\t\tif (auto_reload_module) {\n\t\t\tlog(\"AUTO-RELOAD\\n\");\n\t\t\treload_module();\n\t\t}\n\n\t\tfor (auto &it : database) {\n\t\t\tlog(\"BIT %s:\\n\", log_signal(it.first));\n\t\t\tif (it.second.is_input)\n\t\t\t\tlog(\" PRIMARY INPUT\\n\");\n\t\t\tif (it.second.is_output)\n\t\t\t\tlog(\" PRIMARY OUTPUT\\n\");\n\t\t\tfor (auto &port : it.second.ports)\n\t\t\t\tlog(\" PORT: %s.%s[%d] (%s)\\n\", log_id(port.cell),\n\t\t\t\t\t\tlog_id(port.port), port.offset, log_id(port.cell->type));\n\t\t}\n\t}\n};\n\nstruct ModWalker\n{\n\tstruct PortBit\n\t{\n\t\tRTLIL::Cell *cell;\n\t\tRTLIL::IdString port;\n\t\tint offset;\n\n\t\tbool operator<(const PortBit &other) const {\n\t\t\tif (cell != other.cell)\n\t\t\t\treturn cell < other.cell;\n\t\t\tif (port != other.port)\n\t\t\t\treturn port < other.port;\n\t\t\treturn offset < other.offset;\n\t\t}\n\n\t\tbool operator==(const PortBit &other) const {\n\t\t\treturn cell == other.cell && port == other.port && offset == other.offset;\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);\n\t\t}\n\t};\n\n\tRTLIL::Design *design;\n\tRTLIL::Module *module;\n\n\tCellTypes ct;\n\tSigMap sigmap;\n\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_drivers;\n\tdict<RTLIL::SigBit, pool<PortBit>> signal_consumers;\n\tpool<RTLIL::SigBit> signal_inputs, signal_outputs;\n\n\tdict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;\n\n\tvoid add_wire(RTLIL::Wire *wire)\n\t{\n\t\tif (wire->port_input) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_inputs.insert(bit);\n\t\t}\n\n\t\tif (wire->port_output) {\n\t\t\tstd::vector<RTLIL::SigBit> bits = sigmap(wire);\n\t\t\tfor (auto bit : bits)\n\t\t\t\tif (bit.wire != NULL)\n\t\t\t\t\tsignal_outputs.insert(bit);\n\t\t}\n\t}\n\n\tvoid add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)\n\t{\n\t\tfor (int i = 0; i < int(bits.size()); i++)\n\t\t\tif (bits[i].wire != NULL) {\n\t\t\t\tPortBit pbit = { cell, port, i };\n\t\t\t\tif (is_output) {\n\t\t\t\t\tsignal_drivers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_outputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t\tif (is_input) {\n\t\t\t\t\tsignal_consumers[bits[i]].insert(pbit);\n\t\t\t\t\tcell_inputs[cell].insert(bits[i]);\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\tvoid add_cell(RTLIL::Cell *cell)\n\t{\n\t\tif (ct.cell_known(cell->type)) {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second),\n\t\t\t\t\t\tct.cell_output(cell->type, conn.first),\n\t\t\t\t\t\tct.cell_input(cell->type, conn.first));\n\t\t} else {\n\t\t\tfor (auto &conn : cell->connections())\n\t\t\t\tadd_cell_port(cell, conn.first, sigmap(conn.second), true, true);\n\t\t}\n\t}\n\n\tModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)\n\t{\n\t\tct.setup(design);\n\t\tif (module)\n\t\t\tsetup(module);\n\t}\n\n\tvoid setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)\n\t{\n\t\tthis->module = module;\n\n\t\tsigmap.set(module);\n\n\t\tsignal_drivers.clear();\n\t\tsignal_consumers.clear();\n\t\tsignal_inputs.clear();\n\t\tsignal_outputs.clear();\n\t\tcell_inputs.clear();\n\t\tcell_outputs.clear();\n\n\t\tfor (auto &it : module->wires_)\n\t\t\tadd_wire(it.second);\n\t\tfor (auto &it : module->cells_)\n\t\t\tif (filter_ct == NULL || filter_ct->cell_known(it.second->type))\n\t\t\t\tadd_cell(it.second);\n\t}\n\n\t// get_* methods -- single RTLIL::SigBit\n\n\tinline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_drivers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_consumers.count(bit)) {\n\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\tresult.insert(r.begin(), r.end());\n\t\t\tfound = true;\n\t\t}\n\t\treturn found;\n\t}\n\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_inputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const\n\t{\n\t\tbool found = false;\n\t\tif (signal_outputs.count(bit))\n\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- container of RTLIL::SigBit's (always by reference)\n\n\ttemplate<typename T>\n\tinline bool get_drivers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_drivers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_drivers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_consumers(pool<PortBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_consumers.count(bit)) {\n\t\t\t\tconst pool<PortBit> &r = signal_consumers.at(bit);\n\t\t\t\tresult.insert(r.begin(), r.end());\n\t\t\t\tfound = true;\n\t\t\t}\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_inputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\ttemplate<typename T>\n\tinline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const\n\t{\n\t\tbool found = false;\n\t\tfor (RTLIL::SigBit bit : bits)\n\t\t\tif (signal_outputs.count(bit))\n\t\t\t\tresult.insert(bit), found = true;\n\t\treturn found;\n\t}\n\n\t// get_* methods -- call by RTLIL::SigSpec (always by value)\n\n\tbool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_drivers(result, bits);\n\t}\n\n\tbool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_consumers(result, bits);\n\t}\n\n\tbool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_inputs(result, bits);\n\t}\n\n\tbool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const\n\t{\n\t\tstd::vector<RTLIL::SigBit> bits = sigmap(signal);\n\t\treturn get_outputs(result, bits);\n\t}\n\n\t// has_* methods -- call by reference\n\n\ttemplate<typename T>\n\tinline bool has_drivers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_consumers(const T &sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_inputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\ttemplate<typename T>\n\tinline bool has_outputs(const T &sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n\n\t// has_* methods -- call by value\n\n\tinline bool has_drivers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_drivers(result, sig);\n\t}\n\n\tinline bool has_consumers(RTLIL::SigSpec sig) const {\n\t\tpool<PortBit> result;\n\t\treturn get_consumers(result, sig);\n\t}\n\n\tinline bool has_inputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_inputs(result, sig);\n\t}\n\n\tinline bool has_outputs(RTLIL::SigSpec sig) const {\n\t\tpool<RTLIL::SigBit> result;\n\t\treturn get_outputs(result, sig);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "qcsat.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef QCSAT_H\n#define QCSAT_H\n\n#include \"kernel/satgen.h\"\n#include \"kernel/modtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// This is a helper class meant for easy construction of quick SAT queries\n// to a combinatorial input cone of some set of signals, meant for SAT-based\n// optimizations. Various knobs are provided to set just how much of the\n// cone should be included in the model — since this class is meant for\n// optimization, it should not be a correctness problem when some cells are\n// skipped and the solver spuriously returns SAT with a solution that\n// cannot exist in reality due to skipped constraints (ie. only UNSAT results\n// from this class should be considered binding).\nstruct QuickConeSat {\n\tModWalker &modwalker;\n\tezSatPtr ez;\n\tSatGen satgen;\n\n\t// The effort level knobs.\n\n\t// The maximum \"complexity level\" of cells that will be imported.\n\t// - 1: bitwise operations, muxes, equality comparisons, lut, sop, fa\n\t// - 2: addition, subtraction, greater/less than comparisons, lcu\n\t// - 3: shifts\n\t// - 4: multiplication, division, power\n\tint max_cell_complexity = 2;\n\t// The maximum number of cells to import, or 0 for no limit.\n\tint max_cell_count = 0;\n\t// If non-0, skip importing cells with more than this number of output bits.\n\tint max_cell_outs = 0;\n\n\t// Internal state.\n\tpool<RTLIL::Cell*> imported_cells;\n\tpool<RTLIL::Wire*> imported_onehot;\n\tpool<RTLIL::SigBit> bits_queue;\n\n\tQuickConeSat(ModWalker &modwalker) : modwalker(modwalker), ez(), satgen(ez.get(), &modwalker.sigmap) {}\n\n\t// Imports a signal into the SAT solver, queues its input cone to be\n\t// imported in the next prepare() call.\n\tstd::vector<int> importSig(SigSpec sig);\n\tint importSigBit(SigBit bit);\n\n\t// Imports the input cones of all previously importSig'd signals into\n\t// the SAT solver.\n\tvoid prepare();\n\n\t// Returns the \"complexity level\" of a given cell.\n\tstatic int cell_complexity(RTLIL::Cell *cell);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
173
- "register.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"kernel/yosys.h\"\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
174
- "rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"kernel/yosys.h\"\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct IdString\n\t{\n\t\t#undef YOSYS_XTRACE_GET_PUT\n\t\t#undef YOSYS_SORT_ID_FREE_LIST\n\t\t#undef YOSYS_USE_STICKY_IDS\n\t\t#undef YOSYS_NO_IDS_REFCNT\n\n\t\t// the global id string cache\n\n\t\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\t\tstatic struct destruct_guard_t {\n\t\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t\t} destruct_guard;\n\n\t\tstatic std::vector<char*> global_id_storage_;\n\t\tstatic dict<char*, int, hash_cstr_ops> global_id_index_;\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic std::vector<int> global_refcount_storage_;\n\t\tstatic std::vector<int> global_free_idx_list_;\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tstatic int last_created_idx_ptr_;\n\t\tstatic int last_created_idx_[8];\n\t#endif\n\n\t\tstatic inline void xtrace_db_dump()\n\t\t{\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t\t{\n\t\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\t\telse\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\t\t}\n\n\t\tstatic inline void checkpoint()\n\t\t{\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\tlast_created_idx_ptr_ = 0;\n\t\t\tfor (int i = 0; i < 8; i++) {\n\t\t\t\tif (last_created_idx_[i])\n\t\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\t\tlast_created_idx_[i] = 0;\n\t\t\t}\n\t\t#endif\n\t\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t\t#endif\n\t\t}\n\n\t\tstatic inline int get_reference(int idx)\n\t\t{\n\t\t\tif (idx) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_[idx]++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\t\t\t}\n\t\t\treturn idx;\n\t\t}\n\n\t\tstatic int get_reference(const char *p)\n\t\t{\n\t\t\tlog_assert(destruct_guard_ok);\n\n\t\t\tif (!p[0])\n\t\t\t\treturn 0;\n\n\t\t\tauto it = global_id_index_.find((char*)p);\n\t\t\tif (it != global_id_index_.end()) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t\t#endif\n\t\t\t\treturn it->second;\n\t\t\t}\n\n\t\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\t\tlog_assert(p[1] != 0);\n\t\t\tfor (const char *c = p; *c; c++)\n\t\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tif (global_free_idx_list_.empty()) {\n\t\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t\t}\n\t\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t}\n\n\t\t\tint idx = global_free_idx_list_.back();\n\t\t\tglobal_free_idx_list_.pop_back();\n\t\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\t\tglobal_refcount_storage_.at(idx)++;\n\t\t#else\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tint idx = global_id_storage_.size();\n\t\t\tglobal_id_storage_.push_back(strdup(p));\n\t\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t\t#endif\n\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\t// Avoid Create->Delete->Create pattern\n\t\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t\t#endif\n\n\t\t\treturn idx;\n\t\t}\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic inline void put_reference(int idx)\n\t\t{\n\t\t\t// put_reference() may be called from destructors after the destructor of\n\t\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\t\tif (!destruct_guard_ok || !idx)\n\t\t\t\treturn;\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\n\t\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\t\tif (--refcount > 0)\n\t\t\t\treturn;\n\n\t\t\tlog_assert(refcount == 0);\n\t\t\tfree_reference(idx);\n\t\t}\n\t\tstatic inline void free_reference(int idx)\n\t\t{\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\t\tfree(global_id_storage_.at(idx));\n\t\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\t\tglobal_free_idx_list_.push_back(idx);\n\t\t}\n\t#else\n\t\tstatic inline void put_reference(int) { }\n\t#endif\n\n\t\t// the actual IdString object is just is a single int\n\n\t\tint index_;\n\n\t\tinline IdString() : index_(0) { }\n\t\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\t\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\t\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\t\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\t\tinline ~IdString() { put_reference(index_); }\n\n\t\tinline void operator=(const IdString &rhs) {\n\t\t\tput_reference(index_);\n\t\t\tindex_ = get_reference(rhs.index_);\n\t\t}\n\n\t\tinline void operator=(const char *rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline void operator=(const std::string &rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline const char *c_str() const {\n\t\t\treturn global_id_storage_.at(index_);\n\t\t}\n\n\t\tinline std::string str() const {\n\t\t\treturn std::string(global_id_storage_.at(index_));\n\t\t}\n\n\t\tinline bool operator<(const IdString &rhs) const {\n\t\t\treturn index_ < rhs.index_;\n\t\t}\n\n\t\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\t\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\t\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\t\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\t\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\t\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\t\tchar operator[](size_t i) const {\n const char *p = c_str();\n#ifndef NDEBUG\n\t\t\tfor (; i != 0; i--, p++)\n\t\t\t\tlog_assert(*p != 0);\n\t\t\treturn *p;\n#else\n\t\t\treturn *(p + i);\n#endif\n\t\t}\n\n\t\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\t\treturn std::string(c_str() + pos);\n\t\t\telse\n\t\t\t\treturn std::string(c_str() + pos, len);\n\t\t}\n\n\t\tint compare(size_t pos, size_t len, const char* s) const {\n\t\t\treturn strncmp(c_str()+pos, s, len);\n\t\t}\n\n\t\tbool begins_with(const char* prefix) const {\n\t\t\tsize_t len = strlen(prefix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(0, len, prefix) == 0;\n\t\t}\n\n\t\tbool ends_with(const char* suffix) const {\n\t\t\tsize_t len = strlen(suffix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(size()-len, len, suffix) == 0;\n\t\t}\n\n\t\tbool contains(const char* str) const {\n\t\t\treturn strstr(c_str(), str);\n\t\t}\n\n\t\tsize_t size() const {\n\t\t\treturn strlen(c_str());\n\t\t}\n\n\t\tbool empty() const {\n\t\t\treturn c_str()[0] == 0;\n\t\t}\n\n\t\tvoid clear() {\n\t\t\t*this = IdString();\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn index_;\n\t\t}\n\n\t\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t\t// set has an influence on the algorithm.\n\n\t\ttemplate<typename T> struct compare_ptr_by_name {\n\t\t\tbool operator()(const T *a, const T *b) const {\n\t\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t\t}\n\t\t};\n\n\t\t// often one needs to check if a given IdString is part of a list (for example a list\n\t\t// of cell types). the following functions helps with that.\n\n\t\ttemplate<typename... Args>\n\t\tbool in(Args... args) const {\n\t\t\t// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html\n\t\t\tbool result = false;\n\t\t\t(void) std::initializer_list<int>{ (result = result || in(args), 0)... };\n\t\t\treturn result;\n\t\t}\n\n\t\tbool in(const IdString &rhs) const { return *this == rhs; }\n\t\tbool in(const char *rhs) const { return *this == rhs; }\n\t\tbool in(const std::string &rhs) const { return *this == rhs; }\n\t\tbool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n\n\t\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\t};\n\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tint flags;\n\tstd::vector<RTLIL::State> bits;\n\n\tConst() : flags(RTLIL::CONST_FLAG_NONE) {}\n\tConst(const std::string &str);\n\tConst(int val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &c) = default;\n\tRTLIL::Const &operator =(const RTLIL::Const &other) = default;\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tstatic Const from_string(const std::string &str);\n\n\tstd::string decode_string() const;\n\n\tinline int size() const { return bits.size(); }\n\tinline bool empty() const { return bits.empty(); }\n\tinline RTLIL::State &operator[](int index) { return bits.at(index); }\n\tinline const RTLIL::State &operator[](int index) const { return bits.at(index); }\n\tinline decltype(bits)::iterator begin() { return bits.begin(); }\n\tinline decltype(bits)::iterator end() { return bits.end(); }\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tinline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {\n\t\tRTLIL::Const ret;\n\t\tret.bits.reserve(len);\n\t\tfor (int i = offset; i < offset + len; i++)\n\t\t\tret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);\n\t\treturn ret;\n\t}\n\n\tvoid extu(int width) {\n\t\tbits.resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());\n\t}\n\n\tinline unsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto b : bits)\n\t\t\th = mkhash(h, b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\tunsigned int hash() const;\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tunsigned long hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tsize_t get_hash() const {\n\t\tif (!hash_) hash();\n\t\treturn hash_;\n\t}\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\tunsigned int hash() const { if (!hash_) updhash(); return hash_; };\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline unsigned int RTLIL::SigBit::hash() const {\n\tif (wire)\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\treturn data;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
176
+ "register.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef REGISTER_H\n#define REGISTER_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct Pass\n{\n\tstd::string pass_name, short_help;\n\tPass(std::string name, std::string short_help = \"** document me **\");\n\tvirtual ~Pass();\n\n\tvirtual void help();\n\tvirtual void clear_flags();\n\tvirtual void execute(std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tint call_counter;\n\tint64_t runtime_ns;\n\tbool experimental_flag = false;\n\n\tvoid experimental() {\n\t\texperimental_flag = true;\n\t}\n\n\tstruct pre_post_exec_state_t {\n\t\tPass *parent_pass;\n\t\tint64_t begin_ns;\n\t};\n\n\tpre_post_exec_state_t pre_execute();\n\tvoid post_execute(pre_post_exec_state_t state);\n\n\tvoid cmd_log_args(const std::vector<std::string> &args);\n\tvoid cmd_error(const std::vector<std::string> &args, size_t argidx, std::string msg);\n\tvoid extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select = true);\n\n\tstatic void call(RTLIL::Design *design, std::string command);\n\tstatic void call(RTLIL::Design *design, std::vector<std::string> args);\n\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);\n\tstatic void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);\n\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);\n\tstatic void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);\n\n\tPass *next_queued_pass;\n\tvirtual void run_register();\n\tstatic void init_register();\n\tstatic void done_register();\n\n\tvirtual void on_register();\n\tvirtual void on_shutdown();\n\tvirtual bool replace_existing_pass() const { return false; }\n};\n\nstruct ScriptPass : Pass\n{\n\tbool block_active, help_mode;\n\tRTLIL::Design *active_design;\n\tstd::string active_run_from, active_run_to;\n\n\tScriptPass(std::string name, std::string short_help = \"** document me **\") : Pass(name, short_help) { }\n\n\tvirtual void script() = 0;\n\n\tbool check_label(std::string label, std::string info = std::string());\n\tvoid run(std::string command, std::string info = std::string());\n\tvoid run_nocheck(std::string command, std::string info = std::string());\n\tvoid run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());\n\tvoid help_script();\n};\n\nstruct Frontend : Pass\n{\n\t// for reading of here documents\n\tstatic FILE *current_script_file;\n\tstatic std::string last_here_document;\n\n\tstd::string frontend_name;\n\tFrontend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Frontend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tstatic std::vector<std::string> next_args;\n\tvoid extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);\n\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);\n\tstatic void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);\n};\n\nstruct Backend : Pass\n{\n\tstd::string backend_name;\n\tBackend(std::string name, std::string short_help = \"** document me **\");\n\tvoid run_register() override;\n\t~Backend() override;\n\tvoid execute(std::vector<std::string> args, RTLIL::Design *design) override final;\n\tvirtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;\n\n\tvoid extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);\n\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);\n\tstatic void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);\n};\n\n// implemented in passes/cmds/select.cc\nextern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);\nextern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);\nextern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);\n\nextern std::map<std::string, Pass*> pass_register;\nextern std::map<std::string, Frontend*> frontend_register;\nextern std::map<std::string, Backend*> backend_register;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
177
+ "rtlil.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef RTLIL_H\n#define RTLIL_H\n\n#include \"kernel/yosys_common.h\"\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nnamespace RTLIL\n{\n\tenum State : unsigned char {\n\t\tS0 = 0,\n\t\tS1 = 1,\n\t\tSx = 2, // undefined value or conflict\n\t\tSz = 3, // high-impedance / not-connected\n\t\tSa = 4, // don't care (used only in cases)\n\t\tSm = 5 // marker (used internally by some passes)\n\t};\n\n\tenum SyncType : unsigned char {\n\t\tST0 = 0, // level sensitive: 0\n\t\tST1 = 1, // level sensitive: 1\n\t\tSTp = 2, // edge sensitive: posedge\n\t\tSTn = 3, // edge sensitive: negedge\n\t\tSTe = 4, // edge sensitive: both edges\n\t\tSTa = 5, // always active\n\t\tSTg = 6, // global clock\n\t\tSTi = 7 // init\n\t};\n\n\tenum ConstFlags : unsigned char {\n\t\tCONST_FLAG_NONE = 0,\n\t\tCONST_FLAG_STRING = 1,\n\t\tCONST_FLAG_SIGNED = 2, // only used for parameters\n\t\tCONST_FLAG_REAL = 4 // only used for parameters\n\t};\n\n\tstruct Const;\n\tstruct AttrObject;\n\tstruct Selection;\n\tstruct Monitor;\n\tstruct Design;\n\tstruct Module;\n\tstruct Wire;\n\tstruct Memory;\n\tstruct Cell;\n\tstruct SigChunk;\n\tstruct SigBit;\n\tstruct SigSpecIterator;\n\tstruct SigSpecConstIterator;\n\tstruct SigSpec;\n\tstruct CaseRule;\n\tstruct SwitchRule;\n\tstruct MemWriteAction;\n\tstruct SyncRule;\n\tstruct Process;\n\tstruct Binding;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n\tstruct IdString\n\t{\n\t\t#undef YOSYS_XTRACE_GET_PUT\n\t\t#undef YOSYS_SORT_ID_FREE_LIST\n\t\t#undef YOSYS_USE_STICKY_IDS\n\t\t#undef YOSYS_NO_IDS_REFCNT\n\n\t\t// the global id string cache\n\n\t\tstatic bool destruct_guard_ok; // POD, will be initialized to zero\n\t\tstatic struct destruct_guard_t {\n\t\t\tdestruct_guard_t() { destruct_guard_ok = true; }\n\t\t\t~destruct_guard_t() { destruct_guard_ok = false; }\n\t\t} destruct_guard;\n\n\t\tstatic std::vector<char*> global_id_storage_;\n\t\tstatic dict<char*, int, hash_cstr_ops> global_id_index_;\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic std::vector<int> global_refcount_storage_;\n\t\tstatic std::vector<int> global_free_idx_list_;\n\t#endif\n\n\t#ifdef YOSYS_USE_STICKY_IDS\n\t\tstatic int last_created_idx_ptr_;\n\t\tstatic int last_created_idx_[8];\n\t#endif\n\n\t\tstatic inline void xtrace_db_dump()\n\t\t{\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tfor (int idx = 0; idx < GetSize(global_id_storage_); idx++)\n\t\t\t{\n\t\t\t\tif (global_id_storage_.at(idx) == nullptr)\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: FREE\\n\", idx);\n\t\t\t\telse\n\t\t\t\t\tlog(\"#X# DB-DUMP index %d: '%s' (ref %d)\\n\", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\t\t}\n\n\t\tstatic inline void checkpoint()\n\t\t{\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\tlast_created_idx_ptr_ = 0;\n\t\t\tfor (int i = 0; i < 8; i++) {\n\t\t\t\tif (last_created_idx_[i])\n\t\t\t\t\tput_reference(last_created_idx_[i]);\n\t\t\t\tlast_created_idx_[i] = 0;\n\t\t\t}\n\t\t#endif\n\t\t#ifdef YOSYS_SORT_ID_FREE_LIST\n\t\t\tstd::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());\n\t\t#endif\n\t\t}\n\n\t\tstatic inline int get_reference(int idx)\n\t\t{\n\t\t\tif (idx) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_[idx]++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-INDEX '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\t\t\t}\n\t\t\treturn idx;\n\t\t}\n\n\t\tstatic int get_reference(const char *p)\n\t\t{\n\t\t\tlog_assert(destruct_guard_ok);\n\n\t\t\tif (!p[0])\n\t\t\t\treturn 0;\n\n\t\t\tauto it = global_id_index_.find((char*)p);\n\t\t\tif (it != global_id_index_.end()) {\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\t\tglobal_refcount_storage_.at(it->second)++;\n\t\t#endif\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\t\tif (yosys_xtrace)\n\t\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));\n\t\t#endif\n\t\t\t\treturn it->second;\n\t\t\t}\n\n\t\t\tlog_assert(p[0] == '$' || p[0] == '\\\\');\n\t\t\tlog_assert(p[1] != 0);\n\t\t\tfor (const char *c = p; *c; c++)\n\t\t\t\tif ((unsigned)*c <= (unsigned)' ')\n\t\t\t\t\tlog_error(\"Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\\n\", *c, p);\n\n\t\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\t\tif (global_free_idx_list_.empty()) {\n\t\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t\t}\n\t\t\t\tlog_assert(global_id_storage_.size() < 0x40000000);\n\t\t\t\tglobal_free_idx_list_.push_back(global_id_storage_.size());\n\t\t\t\tglobal_id_storage_.push_back(nullptr);\n\t\t\t\tglobal_refcount_storage_.push_back(0);\n\t\t\t}\n\n\t\t\tint idx = global_free_idx_list_.back();\n\t\t\tglobal_free_idx_list_.pop_back();\n\t\t\tglobal_id_storage_.at(idx) = strdup(p);\n\t\t\tglobal_id_index_[global_id_storage_.at(idx)] = idx;\n\t\t\tglobal_refcount_storage_.at(idx)++;\n\t\t#else\n\t\t\tif (global_id_storage_.empty()) {\n\t\t\t\tglobal_id_storage_.push_back((char*)\"\");\n\t\t\t\tglobal_id_index_[global_id_storage_.back()] = 0;\n\t\t\t}\n\t\t\tint idx = global_id_storage_.size();\n\t\t\tglobal_id_storage_.push_back(strdup(p));\n\t\t\tglobal_id_index_[global_id_storage_.back()] = idx;\n\t\t#endif\n\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# New IdString '%s' with index %d.\\n\", p, idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace)\n\t\t\t\tlog(\"#X# GET-BY-NAME '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t#endif\n\n\t\t#ifdef YOSYS_USE_STICKY_IDS\n\t\t\t// Avoid Create->Delete->Create pattern\n\t\t\tif (last_created_idx_[last_created_idx_ptr_])\n\t\t\t\tput_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_[last_created_idx_ptr_] = idx;\n\t\t\tget_reference(last_created_idx_[last_created_idx_ptr_]);\n\t\t\tlast_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;\n\t\t#endif\n\n\t\t\treturn idx;\n\t\t}\n\n\t#ifndef YOSYS_NO_IDS_REFCNT\n\t\tstatic inline void put_reference(int idx)\n\t\t{\n\t\t\t// put_reference() may be called from destructors after the destructor of\n\t\t\t// global_refcount_storage_ has been run. in this case we simply do nothing.\n\t\t\tif (!destruct_guard_ok || !idx)\n\t\t\t\treturn;\n\n\t\t#ifdef YOSYS_XTRACE_GET_PUT\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# PUT '%s' (index %d, refcount %d)\\n\", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));\n\t\t\t}\n\t\t#endif\n\n\t\t\tint &refcount = global_refcount_storage_[idx];\n\n\t\t\tif (--refcount > 0)\n\t\t\t\treturn;\n\n\t\t\tlog_assert(refcount == 0);\n\t\t\tfree_reference(idx);\n\t\t}\n\t\tstatic inline void free_reference(int idx)\n\t\t{\n\t\t\tif (yosys_xtrace) {\n\t\t\t\tlog(\"#X# Removed IdString '%s' with index %d.\\n\", global_id_storage_.at(idx), idx);\n\t\t\t\tlog_backtrace(\"-X- \", yosys_xtrace-1);\n\t\t\t}\n\n\t\t\tglobal_id_index_.erase(global_id_storage_.at(idx));\n\t\t\tfree(global_id_storage_.at(idx));\n\t\t\tglobal_id_storage_.at(idx) = nullptr;\n\t\t\tglobal_free_idx_list_.push_back(idx);\n\t\t}\n\t#else\n\t\tstatic inline void put_reference(int) { }\n\t#endif\n\n\t\t// the actual IdString object is just is a single int\n\n\t\tint index_;\n\n\t\tinline IdString() : index_(0) { }\n\t\tinline IdString(const char *str) : index_(get_reference(str)) { }\n\t\tinline IdString(const IdString &str) : index_(get_reference(str.index_)) { }\n\t\tinline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }\n\t\tinline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }\n\t\tinline ~IdString() { put_reference(index_); }\n\n\t\tinline void operator=(const IdString &rhs) {\n\t\t\tput_reference(index_);\n\t\t\tindex_ = get_reference(rhs.index_);\n\t\t}\n\n\t\tinline void operator=(const char *rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline void operator=(const std::string &rhs) {\n\t\t\tIdString id(rhs);\n\t\t\t*this = id;\n\t\t}\n\n\t\tinline const char *c_str() const {\n\t\t\treturn global_id_storage_.at(index_);\n\t\t}\n\n\t\tinline std::string str() const {\n\t\t\treturn std::string(global_id_storage_.at(index_));\n\t\t}\n\n\t\tinline bool operator<(const IdString &rhs) const {\n\t\t\treturn index_ < rhs.index_;\n\t\t}\n\n\t\tinline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }\n\t\tinline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }\n\n\t\t// The methods below are just convenience functions for better compatibility with std::string.\n\n\t\tbool operator==(const std::string &rhs) const { return c_str() == rhs; }\n\t\tbool operator!=(const std::string &rhs) const { return c_str() != rhs; }\n\n\t\tbool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }\n\t\tbool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }\n\n\t\tchar operator[](size_t i) const {\n const char *p = c_str();\n#ifndef NDEBUG\n\t\t\tfor (; i != 0; i--, p++)\n\t\t\t\tlog_assert(*p != 0);\n\t\t\treturn *p;\n#else\n\t\t\treturn *(p + i);\n#endif\n\t\t}\n\n\t\tstd::string substr(size_t pos = 0, size_t len = std::string::npos) const {\n\t\t\tif (len == std::string::npos || len >= strlen(c_str() + pos))\n\t\t\t\treturn std::string(c_str() + pos);\n\t\t\telse\n\t\t\t\treturn std::string(c_str() + pos, len);\n\t\t}\n\n\t\tint compare(size_t pos, size_t len, const char* s) const {\n\t\t\treturn strncmp(c_str()+pos, s, len);\n\t\t}\n\n\t\tbool begins_with(const char* prefix) const {\n\t\t\tsize_t len = strlen(prefix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(0, len, prefix) == 0;\n\t\t}\n\n\t\tbool ends_with(const char* suffix) const {\n\t\t\tsize_t len = strlen(suffix);\n\t\t\tif (size() < len) return false;\n\t\t\treturn compare(size()-len, len, suffix) == 0;\n\t\t}\n\n\t\tbool contains(const char* str) const {\n\t\t\treturn strstr(c_str(), str);\n\t\t}\n\n\t\tsize_t size() const {\n\t\t\treturn strlen(c_str());\n\t\t}\n\n\t\tbool empty() const {\n\t\t\treturn c_str()[0] == 0;\n\t\t}\n\n\t\tvoid clear() {\n\t\t\t*this = IdString();\n\t\t}\n\n\t\tunsigned int hash() const {\n\t\t\treturn index_;\n\t\t}\n\n\t\t// The following is a helper key_compare class. Instead of for example std::set<Cell*>\n\t\t// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the\n\t\t// set has an influence on the algorithm.\n\n\t\ttemplate<typename T> struct compare_ptr_by_name {\n\t\t\tbool operator()(const T *a, const T *b) const {\n\t\t\t\treturn (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);\n\t\t\t}\n\t\t};\n\n\t\t// often one needs to check if a given IdString is part of a list (for example a list\n\t\t// of cell types). the following functions helps with that.\n\n\t\ttemplate<typename... Args>\n\t\tbool in(Args... args) const {\n\t\t\t// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html\n\t\t\tbool result = false;\n\t\t\t(void) std::initializer_list<int>{ (result = result || in(args), 0)... };\n\t\t\treturn result;\n\t\t}\n\n\t\tbool in(const IdString &rhs) const { return *this == rhs; }\n\t\tbool in(const char *rhs) const { return *this == rhs; }\n\t\tbool in(const std::string &rhs) const { return *this == rhs; }\n\t\tbool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }\n\n\t\tbool isPublic() const { return begins_with(\"\\\\\"); }\n\t};\n\n\tnamespace ID {\n#define X(_id) extern IdString _id;\n#include \"kernel/constids.inc\"\n#undef X\n\t};\n\n\textern dict<std::string, std::string> constpad;\n\n\tconst pool<IdString> &builtin_ff_cell_types();\n\n\tstatic inline std::string escape_id(const std::string &str) {\n\t\tif (str.size() > 0 && str[0] != '\\\\' && str[0] != '$')\n\t\t\treturn \"\\\\\" + str;\n\t\treturn str;\n\t}\n\n\tstatic inline std::string unescape_id(const std::string &str) {\n\t\tif (str.size() < 2)\n\t\t\treturn str;\n\t\tif (str[0] != '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] == '$' || str[1] == '\\\\')\n\t\t\treturn str;\n\t\tif (str[1] >= '0' && str[1] <= '9')\n\t\t\treturn str;\n\t\treturn str.substr(1);\n\t}\n\n\tstatic inline std::string unescape_id(const RTLIL::IdString &str) {\n\t\treturn unescape_id(str.str());\n\t}\n\n\tstatic inline const char *id2cstr(const RTLIL::IdString &str) {\n\t\treturn log_id(str);\n\t}\n\n\ttemplate <typename T> struct sort_by_name_id {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn a->name < b->name;\n\t\t}\n\t};\n\n\ttemplate <typename T> struct sort_by_name_str {\n\t\tbool operator()(T *a, T *b) const {\n\t\t\treturn strcmp(a->name.c_str(), b->name.c_str()) < 0;\n\t\t}\n\t};\n\n\tstruct sort_by_id_str {\n\t\tbool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {\n\t\t\treturn strcmp(a.c_str(), b.c_str()) < 0;\n\t\t}\n\t};\n\n\tstatic inline std::string encode_filename(const std::string &filename)\n\t{\n\t\tstd::stringstream val;\n\t\tif (!std::any_of(filename.begin(), filename.end(), [](char c) {\n\t\t\treturn static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;\n\t\t})) return filename;\n\t\tfor (unsigned char const c : filename) {\n\t\t\tif (c < 33 || c > 126)\n\t\t\t\tval << stringf(\"$%02x\", c);\n\t\t\telse\n\t\t\t\tval << c;\n\t\t}\n\t\treturn val.str();\n\t}\n\n\t// see calc.cc for the implementation of this functions\n\tRTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\tRTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);\n\n\tRTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\tRTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\n\tRTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);\n\tRTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);\n\n\n\t// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().\n\t// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.\n\n\ttemplate<typename T>\n\tstruct ObjIterator {\n\t\tusing iterator_category = std::forward_iterator_tag;\n\t\tusing value_type = T;\n\t\tusing difference_type = ptrdiff_t;\n\t\tusing pointer = T*;\n\t\tusing reference = T&;\n\t\ttypename dict<RTLIL::IdString, T>::iterator it;\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjIterator() : list_p(nullptr), refcount_p(nullptr) {\n\t\t}\n\n\t\tObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {\n\t\t\tif (list_p->empty()) {\n\t\t\t\tthis->list_p = nullptr;\n\t\t\t\tthis->refcount_p = nullptr;\n\t\t\t} else {\n\t\t\t\tit = list_p->begin();\n\t\t\t\t(*refcount_p)++;\n\t\t\t}\n\t\t}\n\n\t\tObjIterator(const RTLIL::ObjIterator<T> &other) {\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t}\n\n\t\tObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t\tit = other.it;\n\t\t\tlist_p = other.list_p;\n\t\t\trefcount_p = other.refcount_p;\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)++;\n\t\t\treturn *this;\n\t\t}\n\n\t\t~ObjIterator() {\n\t\t\tif (refcount_p)\n\t\t\t\t(*refcount_p)--;\n\t\t}\n\n\t\tinline T operator*() const {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\treturn it->second;\n\t\t}\n\n\t\tinline bool operator!=(const RTLIL::ObjIterator<T> &other) const {\n\t\t\tif (list_p == nullptr || other.list_p == nullptr)\n\t\t\t\treturn list_p != other.list_p;\n\t\t\treturn it != other.it;\n\t\t}\n\n\n\t\tinline bool operator==(const RTLIL::ObjIterator<T> &other) const {\n\t\t\treturn !(*this != other);\n\t\t}\n\n\t\tinline ObjIterator<T>& operator++() {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tif (++it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T>& operator+=(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tit += amt;\n\t\t\tif (it == list_p->end()) {\n\t\t\t\t(*refcount_p)--;\n\t\t\t\tlist_p = nullptr;\n\t\t\t\trefcount_p = nullptr;\n\t\t\t}\n\t\t\treturn *this;\n\t\t}\n\n\t\tinline ObjIterator<T> operator+(int amt) {\n\t\t\tlog_assert(list_p != nullptr);\n\t\t\tObjIterator<T> new_obj(*this);\n\t\t\tnew_obj.it += amt;\n\t\t\tif (new_obj.it == list_p->end()) {\n\t\t\t\t(*(new_obj.refcount_p))--;\n\t\t\t\tnew_obj.list_p = nullptr;\n\t\t\t\tnew_obj.refcount_p = nullptr;\n\t\t\t}\n\t\t\treturn new_obj;\n\t\t}\n\n\t\tinline const ObjIterator<T> operator++(int) {\n\t\t\tObjIterator<T> result(*this);\n\t\t\t++(*this);\n\t\t\treturn result;\n\t\t}\n\t};\n\n\ttemplate<typename T>\n\tstruct ObjRange\n\t{\n\t\tdict<RTLIL::IdString, T> *list_p;\n\t\tint *refcount_p;\n\n\t\tObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }\n\t\tRTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }\n\t\tRTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }\n\n\t\tsize_t size() const {\n\t\t\treturn list_p->size();\n\t\t}\n\n\t\toperator pool<T>() const {\n\t\t\tpool<T> result;\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.insert(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\toperator std::vector<T>() const {\n\t\t\tstd::vector<T> result;\n\t\t\tresult.reserve(list_p->size());\n\t\t\tfor (auto &it : *list_p)\n\t\t\t\tresult.push_back(it.second);\n\t\t\treturn result;\n\t\t}\n\n\t\tpool<T> to_pool() const { return *this; }\n\t\tstd::vector<T> to_vector() const { return *this; }\n\t};\n};\n\nstruct RTLIL::Const\n{\n\tint flags;\n\tstd::vector<RTLIL::State> bits;\n\n\tConst() : flags(RTLIL::CONST_FLAG_NONE) {}\n\tConst(const std::string &str);\n\tConst(int val, int width = 32);\n\tConst(RTLIL::State bit, int width = 1);\n\tConst(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }\n\tConst(const std::vector<bool> &bits);\n\tConst(const RTLIL::Const &c) = default;\n\tRTLIL::Const &operator =(const RTLIL::Const &other) = default;\n\n\tbool operator <(const RTLIL::Const &other) const;\n\tbool operator ==(const RTLIL::Const &other) const;\n\tbool operator !=(const RTLIL::Const &other) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tstatic Const from_string(const std::string &str);\n\n\tstd::string decode_string() const;\n\n\tinline int size() const { return bits.size(); }\n\tinline bool empty() const { return bits.empty(); }\n\tinline RTLIL::State &operator[](int index) { return bits.at(index); }\n\tinline const RTLIL::State &operator[](int index) const { return bits.at(index); }\n\tinline decltype(bits)::iterator begin() { return bits.begin(); }\n\tinline decltype(bits)::iterator end() { return bits.end(); }\n\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool is_fully_undef_x_only() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tinline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {\n\t\tRTLIL::Const ret;\n\t\tret.bits.reserve(len);\n\t\tfor (int i = offset; i < offset + len; i++)\n\t\t\tret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);\n\t\treturn ret;\n\t}\n\n\tvoid extu(int width) {\n\t\tbits.resize(width, RTLIL::State::S0);\n\t}\n\n\tvoid exts(int width) {\n\t\tbits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());\n\t}\n\n\tinline unsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto b : bits)\n\t\t\th = mkhash(h, b);\n\t\treturn h;\n\t}\n};\n\nstruct RTLIL::AttrObject\n{\n\tdict<RTLIL::IdString, RTLIL::Const> attributes;\n\n\tbool has_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_bool_attribute(const RTLIL::IdString &id, bool value=true);\n\tbool get_bool_attribute(const RTLIL::IdString &id) const;\n\n\tbool get_blackbox_attribute(bool ignore_wb=false) const {\n\t\treturn get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));\n\t}\n\n\tvoid set_string_attribute(const RTLIL::IdString& id, string value);\n\tstring get_string_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tvoid add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);\n\tpool<string> get_strpool_attribute(const RTLIL::IdString &id) const;\n\n\tvoid set_src_attribute(const std::string &src) {\n\t\tset_string_attribute(ID::src, src);\n\t}\n\tstd::string get_src_attribute() const {\n\t\treturn get_string_attribute(ID::src);\n\t}\n\n\tvoid set_hdlname_attribute(const vector<string> &hierarchy);\n\tvector<string> get_hdlname_attribute() const;\n\n\tvoid set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);\n\tvector<int> get_intvec_attribute(const RTLIL::IdString &id) const;\n};\n\nstruct RTLIL::SigChunk\n{\n\tRTLIL::Wire *wire;\n\tstd::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0\n\tint width, offset;\n\n\tSigChunk() : wire(nullptr), width(0), offset(0) {}\n\tSigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}\n\tSigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}\n\tSigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}\n\tSigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}\n\tSigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}\n\tSigChunk(const RTLIL::SigBit &bit);\n\n\tRTLIL::SigChunk extract(int offset, int length) const;\n\tinline int size() const { return width; }\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigChunk &other) const;\n\tbool operator ==(const RTLIL::SigChunk &other) const;\n\tbool operator !=(const RTLIL::SigChunk &other) const;\n};\n\nstruct RTLIL::SigBit\n{\n\tRTLIL::Wire *wire;\n\tunion {\n\t\tRTLIL::State data; // used if wire == NULL\n\t\tint offset; // used if wire != NULL\n\t};\n\n\tSigBit();\n\tSigBit(RTLIL::State bit);\n\texplicit SigBit(bool bit);\n\tSigBit(RTLIL::Wire *wire);\n\tSigBit(RTLIL::Wire *wire, int offset);\n\tSigBit(const RTLIL::SigChunk &chunk);\n\tSigBit(const RTLIL::SigChunk &chunk, int index);\n\tSigBit(const RTLIL::SigSpec &sig);\n\tSigBit(const RTLIL::SigBit &sigbit) = default;\n\tRTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;\n\n\tinline bool is_wire() const { return wire != NULL; }\n\n\tbool operator <(const RTLIL::SigBit &other) const;\n\tbool operator ==(const RTLIL::SigBit &other) const;\n\tbool operator !=(const RTLIL::SigBit &other) const;\n\tunsigned int hash() const;\n};\n\nstruct RTLIL::SigSpecIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tRTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpecConstIterator\n{\n\ttypedef std::input_iterator_tag iterator_category;\n\ttypedef RTLIL::SigBit value_type;\n\ttypedef ptrdiff_t difference_type;\n\ttypedef RTLIL::SigBit* pointer;\n\ttypedef RTLIL::SigBit& reference;\n\n\tconst RTLIL::SigSpec *sig_p;\n\tint index;\n\n\tinline const RTLIL::SigBit &operator*() const;\n\tinline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }\n\tinline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }\n\tinline void operator++() { index++; }\n};\n\nstruct RTLIL::SigSpec\n{\nprivate:\n\tint width_;\n\tunsigned long hash_;\n\tstd::vector<RTLIL::SigChunk> chunks_; // LSB at index 0\n\tstd::vector<RTLIL::SigBit> bits_; // LSB at index 0\n\n\tvoid pack() const;\n\tvoid unpack() const;\n\tvoid updhash() const;\n\n\tinline bool packed() const {\n\t\treturn bits_.empty();\n\t}\n\n\tinline void inline_unpack() const {\n\t\tif (!chunks_.empty())\n\t\t\tunpack();\n\t}\n\n\t// Only used by Module::remove(const pool<Wire*> &wires)\n\t// but cannot be more specific as it isn't yet declared\n\tfriend struct RTLIL::Module;\n\npublic:\n\tSigSpec() : width_(0), hash_(0) {}\n\tSigSpec(std::initializer_list<RTLIL::SigSpec> parts);\n\n\tSigSpec(const RTLIL::Const &value);\n\tSigSpec(RTLIL::Const &&value);\n\tSigSpec(const RTLIL::SigChunk &chunk);\n\tSigSpec(RTLIL::SigChunk &&chunk);\n\tSigSpec(RTLIL::Wire *wire);\n\tSigSpec(RTLIL::Wire *wire, int offset, int width = 1);\n\tSigSpec(const std::string &str);\n\tSigSpec(int val, int width = 32);\n\tSigSpec(RTLIL::State bit, int width = 1);\n\tSigSpec(const RTLIL::SigBit &bit, int width = 1);\n\tSigSpec(const std::vector<RTLIL::SigChunk> &chunks);\n\tSigSpec(const std::vector<RTLIL::SigBit> &bits);\n\tSigSpec(const pool<RTLIL::SigBit> &bits);\n\tSigSpec(const std::set<RTLIL::SigBit> &bits);\n\texplicit SigSpec(bool bit);\n\n\tsize_t get_hash() const {\n\t\tif (!hash_) hash();\n\t\treturn hash_;\n\t}\n\n\tinline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }\n\tinline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }\n\n\tinline int size() const { return width_; }\n\tinline bool empty() const { return width_ == 0; }\n\n\tinline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }\n\tinline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }\n\n\tinline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tinline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }\n\tinline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }\n\n\tvoid sort();\n\tvoid sort_and_unify();\n\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);\n\tvoid replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);\n\tvoid replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;\n\n\tvoid replace(int offset, const RTLIL::SigSpec &with);\n\n\tvoid remove(const RTLIL::SigSpec &pattern);\n\tvoid remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(const pool<RTLIL::SigBit> &pattern);\n\tvoid remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;\n\tvoid remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);\n\tvoid remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);\n\n\tvoid remove(int offset, int length = 1);\n\tvoid remove_const();\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;\n\tRTLIL::SigSpec extract(int offset, int length = 1) const;\n\tRTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }\n\n\tRTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };\n\tRTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };\n\n\tvoid append(const RTLIL::SigSpec &signal);\n\tinline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }\n\tinline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }\n\tinline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }\n\n\tvoid append(const RTLIL::SigBit &bit);\n\tinline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }\n\tinline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }\n\n\tvoid extend_u0(int width, bool is_signed = false);\n\n\tRTLIL::SigSpec repeat(int num) const;\n\n\tvoid reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }\n\n\tbool operator <(const RTLIL::SigSpec &other) const;\n\tbool operator ==(const RTLIL::SigSpec &other) const;\n\tinline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }\n\n\tbool is_wire() const;\n\tbool is_chunk() const;\n\tinline bool is_bit() const { return width_ == 1; }\n\n\tbool is_fully_const() const;\n\tbool is_fully_zero() const;\n\tbool is_fully_ones() const;\n\tbool is_fully_def() const;\n\tbool is_fully_undef() const;\n\tbool has_const() const;\n\tbool has_marked_bits() const;\n\tbool is_onehot(int *pos = nullptr) const;\n\n\tbool as_bool() const;\n\tint as_int(bool is_signed = false) const;\n\tstd::string as_string() const;\n\tRTLIL::Const as_const() const;\n\tRTLIL::Wire *as_wire() const;\n\tRTLIL::SigChunk as_chunk() const;\n\tRTLIL::SigBit as_bit() const;\n\n\tbool match(const char* pattern) const;\n\n\tstd::set<RTLIL::SigBit> to_sigbit_set() const;\n\tpool<RTLIL::SigBit> to_sigbit_pool() const;\n\tstd::vector<RTLIL::SigBit> to_sigbit_vector() const;\n\tstd::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;\n\tdict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;\n\n\tstatic bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\tstatic bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);\n\tstatic bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);\n\n\toperator std::vector<RTLIL::SigChunk>() const { return chunks(); }\n\toperator std::vector<RTLIL::SigBit>() const { return bits(); }\n\tconst RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }\n\n\tunsigned int hash() const { if (!hash_) updhash(); return hash_; };\n\n#ifndef NDEBUG\n\tvoid check(Module *mod = nullptr) const;\n#else\n\tvoid check(Module *mod = nullptr) const { (void)mod; }\n#endif\n};\n\nstruct RTLIL::Selection\n{\n\tbool full_selection;\n\tpool<RTLIL::IdString> selected_modules;\n\tdict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;\n\n\tSelection(bool full = true) : full_selection(full) { }\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\tvoid optimize(RTLIL::Design *design);\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0) {\n\t\t\tselected_modules.insert(module->name);\n\t\t\tselected_members.erase(module->name);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (!full_selection && selected_modules.count(module->name) == 0)\n\t\t\tselected_members[module->name].insert(member->name);\n\t}\n\n\tbool empty() const {\n\t\treturn !full_selection && selected_modules.empty() && selected_members.empty();\n\t}\n};\n\nstruct RTLIL::Monitor\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMonitor() {\n\t\tstatic unsigned int hashidx_count = 123456789;\n\t\thashidx_count = mkhash_xorshift(hashidx_count);\n\t\thashidx_ = hashidx_count;\n\t}\n\n\tvirtual ~Monitor() { }\n\tvirtual void notify_module_add(RTLIL::Module*) { }\n\tvirtual void notify_module_del(RTLIL::Module*) { }\n\tvirtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }\n\tvirtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }\n\tvirtual void notify_blackout(RTLIL::Module*) { }\n};\n\n// Forward declaration; defined in preproc.h.\nstruct define_map_t;\n\nstruct RTLIL::Design\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tpool<RTLIL::Monitor*> monitors;\n\tdict<std::string, std::string> scratchpad;\n\n\tint refcount_modules_;\n\tdict<RTLIL::IdString, RTLIL::Module*> modules_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tstd::vector<AST::AstNode*> verilog_packages, verilog_globals;\n\tstd::unique_ptr<define_map_t> verilog_defines;\n\n\tstd::vector<RTLIL::Selection> selection_stack;\n\tdict<RTLIL::IdString, RTLIL::Selection> selection_vars;\n\tstd::string selected_active_module;\n\n\tDesign();\n\t~Design();\n\n\tRTLIL::ObjRange<RTLIL::Module*> modules();\n\tRTLIL::Module *module(const RTLIL::IdString &name);\n\tconst RTLIL::Module *module(const RTLIL::IdString &name) const;\n\tRTLIL::Module *top_module();\n\n\tbool has(const RTLIL::IdString &id) const {\n\t\treturn modules_.count(id) != 0;\n\t}\n\n\tvoid add(RTLIL::Module *module);\n\tvoid add(RTLIL::Binding *binding);\n\n\tRTLIL::Module *addModule(RTLIL::IdString name);\n\tvoid remove(RTLIL::Module *module);\n\tvoid rename(RTLIL::Module *module, RTLIL::IdString new_name);\n\n\tvoid scratchpad_unset(const std::string &varname);\n\n\tvoid scratchpad_set_int(const std::string &varname, int value);\n\tvoid scratchpad_set_bool(const std::string &varname, bool value);\n\tvoid scratchpad_set_string(const std::string &varname, std::string value);\n\n\tint scratchpad_get_int(const std::string &varname, int default_value = 0) const;\n\tbool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;\n\tstd::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid optimize();\n\n\tbool selected_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_whole_module(const RTLIL::IdString &mod_name) const;\n\tbool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;\n\n\tbool selected_module(RTLIL::Module *mod) const;\n\tbool selected_whole_module(RTLIL::Module *mod) const;\n\n\tRTLIL::Selection &selection() {\n\t\treturn selection_stack.back();\n\t}\n\n\tconst RTLIL::Selection &selection() const {\n\t\treturn selection_stack.back();\n\t}\n\n\tbool full_selection() const {\n\t\treturn selection_stack.back().full_selection;\n\t}\n\n\ttemplate<typename T1> bool selected(T1 *module) const {\n\t\treturn selected_module(module->name);\n\t}\n\n\ttemplate<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {\n\t\treturn selected_member(module->name, member->name);\n\t}\n\n\ttemplate<typename T1> void select(T1 *module) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module);\n\t\t}\n\t}\n\n\ttemplate<typename T1, typename T2> void select(T1 *module, T2 *member) {\n\t\tif (selection_stack.size() > 0) {\n\t\t\tRTLIL::Selection &sel = selection_stack.back();\n\t\t\tsel.select(module, member);\n\t\t}\n\t}\n\n\n\tstd::vector<RTLIL::Module*> selected_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules() const;\n\tstd::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);\n#endif\n};\n\nstruct RTLIL::Module : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\tvoid add(RTLIL::Wire *wire);\n\tvoid add(RTLIL::Cell *cell);\n\tvoid add(RTLIL::Process *process);\n\npublic:\n\tRTLIL::Design *design;\n\tpool<RTLIL::Monitor*> monitors;\n\n\tint refcount_wires_;\n\tint refcount_cells_;\n\n\tdict<RTLIL::IdString, RTLIL::Wire*> wires_;\n\tdict<RTLIL::IdString, RTLIL::Cell*> cells_;\n\n\tstd::vector<RTLIL::SigSig> connections_;\n\tstd::vector<RTLIL::Binding*> bindings_;\n\n\tRTLIL::IdString name;\n\tidict<RTLIL::IdString> avail_parameters;\n\tdict<RTLIL::IdString, RTLIL::Const> parameter_default_values;\n\tdict<RTLIL::IdString, RTLIL::Memory*> memories;\n\tdict<RTLIL::IdString, RTLIL::Process*> processes;\n\n\tModule();\n\tvirtual ~Module();\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);\n\tvirtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);\n\tvirtual size_t count_id(const RTLIL::IdString& id);\n\tvirtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);\n\tvirtual bool reprocess_if_necessary(RTLIL::Design *design);\n\n\tvirtual void sort();\n\tvirtual void check();\n\tvirtual void optimize();\n\tvirtual void makeblackbox();\n\n\tvoid connect(const RTLIL::SigSig &conn);\n\tvoid connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);\n\tvoid new_connections(const std::vector<RTLIL::SigSig> &new_conn);\n\tconst std::vector<RTLIL::SigSig> &connections() const;\n\n\tstd::vector<RTLIL::IdString> ports;\n\tvoid fixup_ports();\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tvoid cloneInto(RTLIL::Module *new_mod) const;\n\tvirtual RTLIL::Module *clone() const;\n\n\tbool has_memories() const;\n\tbool has_processes() const;\n\n\tbool has_memories_warn() const;\n\tbool has_processes_warn() const;\n\n\tstd::vector<RTLIL::Wire*> selected_wires() const;\n\tstd::vector<RTLIL::Cell*> selected_cells() const;\n\n\ttemplate<typename T> bool selected(T *member) const {\n\t\treturn design->selected_member(name, member->name);\n\t}\n\n\tRTLIL::Wire* wire(const RTLIL::IdString &id) {\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tRTLIL::Cell* cell(const RTLIL::IdString &id) {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tconst RTLIL::Wire* wire(const RTLIL::IdString &id) const{\n\t\tauto it = wires_.find(id);\n\t\treturn it == wires_.end() ? nullptr : it->second;\n\t}\n\tconst RTLIL::Cell* cell(const RTLIL::IdString &id) const {\n\t\tauto it = cells_.find(id);\n\t\treturn it == cells_.end() ? nullptr : it->second;\n\t}\n\n\tRTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }\n\tRTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }\n\n\tvoid add(RTLIL::Binding *binding);\n\n\t// Removing wires is expensive. If you have to remove wires, remove them all at once.\n\tvoid remove(const pool<RTLIL::Wire*> &wires);\n\tvoid remove(RTLIL::Cell *cell);\n\tvoid remove(RTLIL::Process *process);\n\n\tvoid rename(RTLIL::Wire *wire, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::Cell *cell, RTLIL::IdString new_name);\n\tvoid rename(RTLIL::IdString old_name, RTLIL::IdString new_name);\n\n\tvoid swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);\n\tvoid swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);\n\n\tRTLIL::IdString uniquify(RTLIL::IdString name);\n\tRTLIL::IdString uniquify(RTLIL::IdString name, int &index);\n\n\tRTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);\n\tRTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);\n\n\tRTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);\n\tRTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);\n\n\tRTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);\n\n\tRTLIL::Process *addProcess(RTLIL::IdString name);\n\tRTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);\n\n\t// The add* methods create a cell and return the created cell. All signals must exist in advance.\n\n\tRTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = \"\");\n\tRTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = \"\");\n\tRTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = \"\");\n\tRTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\tRTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = \"\");\n\n\tRTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tconst RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\tRTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tconst RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,\n\t\t\tbool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = \"\");\n\tRTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,\n\t\t\tRTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = \"\");\n\n\tRTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = \"\");\n\n\t// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.\n\n\tRTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating division\n\tRTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\t// truncating modulo\n\tRTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\tRTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\tRTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = \"\");\n\tRTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = \"\");\n\n\tRTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = \"\");\n\tRTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = \"\");\n\tRTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = \"\");\n\tRTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\tRTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = \"\");\n\n\tRTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = \"\");\n\tRTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = \"\");\n\n\tRTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = \"\");\n\tRTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = \"\");\n\tRTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = \"\");\n\tRTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = \"\");\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);\n#endif\n};\n\nstruct RTLIL::Wire : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addWire() and module->remove() to create or destroy wires\n\tfriend struct RTLIL::Module;\n\tWire();\n\t~Wire();\n\npublic:\n\t// do not simply copy wires\n\tWire(RTLIL::Wire &other) = delete;\n\tvoid operator=(RTLIL::Wire &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tint width, start_offset, port_id;\n\tbool port_input, port_output, upto, is_signed;\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);\n#endif\n};\n\ninline int GetSize(RTLIL::Wire *wire) {\n\treturn wire->width;\n}\n\nstruct RTLIL::Memory : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\n\tMemory();\n\n\tRTLIL::IdString name;\n\tint width, start_offset, size;\n#ifdef WITH_PYTHON\n\t~Memory();\n\tstatic std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);\n#endif\n};\n\nstruct RTLIL::Cell : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addCell() and module->remove() to create or destroy cells\n\tfriend struct RTLIL::Module;\n\tCell();\n\t~Cell();\n\npublic:\n\t// do not simply copy cells\n\tCell(RTLIL::Cell &other) = delete;\n\tvoid operator=(RTLIL::Cell &other) = delete;\n\n\tRTLIL::Module *module;\n\tRTLIL::IdString name;\n\tRTLIL::IdString type;\n\tdict<RTLIL::IdString, RTLIL::SigSpec> connections_;\n\tdict<RTLIL::IdString, RTLIL::Const> parameters;\n\n\t// access cell ports\n\tbool hasPort(const RTLIL::IdString &portname) const;\n\tvoid unsetPort(const RTLIL::IdString &portname);\n\tvoid setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);\n\tconst RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;\n\tconst dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;\n\n\t// information about cell ports\n\tbool known() const;\n\tbool input(const RTLIL::IdString &portname) const;\n\tbool output(const RTLIL::IdString &portname) const;\n\n\t// access cell parameters\n\tbool hasParam(const RTLIL::IdString &paramname) const;\n\tvoid unsetParam(const RTLIL::IdString &paramname);\n\tvoid setParam(const RTLIL::IdString &paramname, RTLIL::Const value);\n\tconst RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;\n\n\tvoid sort();\n\tvoid check();\n\tvoid fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);\n\n\tbool has_keep_attr() const {\n\t\treturn get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&\n\t\t\t\tmodule->design->module(type)->get_bool_attribute(ID::keep));\n\t}\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\n#ifdef WITH_PYTHON\n\tstatic std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);\n#endif\n\n\tbool has_memid() const;\n\tbool is_mem_cell() const;\n};\n\nstruct RTLIL::CaseRule : public RTLIL::AttrObject\n{\n\tstd::vector<RTLIL::SigSpec> compare;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::SwitchRule*> switches;\n\n\t~CaseRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::CaseRule *clone() const;\n};\n\nstruct RTLIL::SwitchRule : public RTLIL::AttrObject\n{\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::CaseRule*> cases;\n\n\t~SwitchRule();\n\n\tbool empty() const;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SwitchRule *clone() const;\n};\n\nstruct RTLIL::MemWriteAction : RTLIL::AttrObject\n{\n\tRTLIL::IdString memid;\n\tRTLIL::SigSpec address;\n\tRTLIL::SigSpec data;\n\tRTLIL::SigSpec enable;\n\tRTLIL::Const priority_mask;\n};\n\nstruct RTLIL::SyncRule\n{\n\tRTLIL::SyncType type;\n\tRTLIL::SigSpec signal;\n\tstd::vector<RTLIL::SigSig> actions;\n\tstd::vector<RTLIL::MemWriteAction> mem_write_actions;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::SyncRule *clone() const;\n};\n\nstruct RTLIL::Process : public RTLIL::AttrObject\n{\n\tunsigned int hashidx_;\n\tunsigned int hash() const { return hashidx_; }\n\nprotected:\n\t// use module->addProcess() and module->remove() to create or destroy processes\n\tfriend struct RTLIL::Module;\n\tProcess();\n\t~Process();\n\npublic:\n\tRTLIL::IdString name;\n\tRTLIL::Module *module;\n\tRTLIL::CaseRule root_case;\n\tstd::vector<RTLIL::SyncRule*> syncs;\n\n\ttemplate<typename T> void rewrite_sigspecs(T &functor);\n\ttemplate<typename T> void rewrite_sigspecs2(T &functor);\n\tRTLIL::Process *clone() const;\n};\n\n\ninline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }\ninline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }\ninline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }\ninline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }\n\ninline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {\n\tif (wire == other.wire)\n\t\treturn wire ? (offset < other.offset) : (data < other.data);\n\tif (wire != nullptr && other.wire != nullptr)\n\t\treturn wire->name < other.wire->name;\n\treturn (wire != nullptr) < (other.wire != nullptr);\n}\n\ninline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {\n\treturn (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));\n}\n\ninline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {\n\treturn (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));\n}\n\ninline unsigned int RTLIL::SigBit::hash() const {\n\tif (wire)\n\t\treturn mkhash_add(wire->name.hash(), offset);\n\treturn data;\n}\n\ninline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {\n\treturn (*sig_p)[index];\n}\n\ninline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {\n\tlog_assert(sig.size() == 1 && sig.chunks().size() == 1);\n\t*this = SigBit(sig.chunks().front());\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Module::rewrite_sigspecs2(T &functor)\n{\n\tfor (auto &it : cells_)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : processes)\n\t\tit.second->rewrite_sigspecs2(functor);\n\tfor (auto &it : connections_) {\n\t\tfunctor(it.first, it.second);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::Cell::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : connections_)\n\t\tfunctor(it.second);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {\n\tfor (auto &it : compare)\n\t\tfunctor(it);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto it : switches)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto it : cases)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first);\n\t\tfunctor(it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::SyncRule::rewrite_sigspecs2(T &functor)\n{\n\tfunctor(signal);\n\tfor (auto &it : actions) {\n\t\tfunctor(it.first, it.second);\n\t}\n\tfor (auto &it : mem_write_actions) {\n\t\tfunctor(it.address);\n\t\tfunctor(it.data);\n\t\tfunctor(it.enable);\n\t}\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs(T &functor)\n{\n\troot_case.rewrite_sigspecs(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs(functor);\n}\n\ntemplate<typename T>\nvoid RTLIL::Process::rewrite_sigspecs2(T &functor)\n{\n\troot_case.rewrite_sigspecs2(functor);\n\tfor (auto it : syncs)\n\t\tit->rewrite_sigspecs2(functor);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "satgen.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SATGEN_H\n#define SATGEN_H\n\n#include \"kernel/rtlil.h\"\n#include \"kernel/sigtools.h\"\n#include \"kernel/celltypes.h\"\n#include \"kernel/macc.h\"\n\n#include \"libs/ezsat/ezminisat.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// defined in kernel/register.cc\nextern struct SatSolver *yosys_satsolver_list;\nextern struct SatSolver *yosys_satsolver;\n\nstruct SatSolver\n{\n\tstring name;\n\tSatSolver *next;\n\tvirtual ezSAT *create() = 0;\n\n\tSatSolver(string name) : name(name) {\n\t\tnext = yosys_satsolver_list;\n\t\tyosys_satsolver_list = this;\n\t}\n\n\tvirtual ~SatSolver() {\n\t\tauto p = &yosys_satsolver_list;\n\t\twhile (*p) {\n\t\t\tif (*p == this)\n\t\t\t\t*p = next;\n\t\t\telse\n\t\t\t\tp = &(*p)->next;\n\t\t}\n\t\tif (yosys_satsolver == this)\n\t\t\tyosys_satsolver = yosys_satsolver_list;\n\t}\n};\n\nstruct ezSatPtr : public std::unique_ptr<ezSAT> {\n\tezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { }\n};\n\nstruct SatGen\n{\n\tezSAT *ez;\n\tSigMap *sigmap;\n\tstd::string prefix;\n\tSigPool initial_state;\n\tstd::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;\n\tstd::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;\n\tstd::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;\n\tstd::map<std::pair<std::string, int>, bool> initstates;\n\tbool ignore_div_by_zero;\n\tbool model_undef;\n\tbool def_formal = false;\n\n\tSatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :\n\t\t\tez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)\n\t{\n\t}\n\n\tvoid setContext(SigMap *sigmap, std::string prefix = std::string())\n\t{\n\t\tthis->sigmap = sigmap;\n\t\tthis->prefix = prefix;\n\t}\n\n\tstd::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef)\n\t{\n\t\tlog_assert(!undef_mode || model_undef);\n\t\tsigmap->apply(sig);\n\n\t\tstd::vector<int> vec;\n\t\tvec.reserve(GetSize(sig));\n\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire == NULL) {\n\t\t\t\tif (model_undef && dup_undef && bit == RTLIL::State::Sx)\n\t\t\t\t\tvec.push_back(ez->frozen_literal());\n\t\t\t\telse\n\t\t\t\t\tvec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);\n\t\t\t} else {\n\t\t\t\tstd::string name = pf + (bit.wire->width == 1 ? stringf(\"%s\", log_id(bit.wire)) : stringf(\"%s [%d]\", log_id(bit.wire->name), bit.offset));\n\t\t\t\tvec.push_back(ez->frozen_literal(name));\n\t\t\t\timported_signals[pf][bit] = vec.back();\n\t\t\t}\n\t\treturn vec;\n\t}\n\n\tstd::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, false);\n\t}\n\n\tstd::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, false, true);\n\t}\n\n\tstd::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(sig, pf, true, false);\n\t}\n\n\tint importSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, false).front();\n\t}\n\n\tint importDefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, false, true).front();\n\t}\n\n\tint importUndefSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = \"undef:\" + prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn importSigSpecWorker(bit, pf, true, false).front();\n\t}\n\n\tbool importedSigBit(RTLIL::SigBit bit, int timestep = -1)\n\t{\n\t\tlog_assert(timestep != 0);\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\treturn imported_signals[pf].count(bit) != 0;\n\t}\n\n\tvoid getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = asserts_a[pf];\n\t\tsig_en = asserts_en[pf];\n\t}\n\n\tvoid getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)\n\t{\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tsig_a = assumes_a[pf];\n\t\tsig_en = assumes_en[pf];\n\t}\n\n\tint importAsserts(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(asserts_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(asserts_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint importAssumes(int timestep = -1)\n\t{\n\t\tstd::vector<int> check_bits, enable_bits;\n\t\tstd::string pf = prefix + (timestep == -1 ? \"\" : stringf(\"@%d:\", timestep));\n\t\tif (model_undef) {\n\t\t\tcheck_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep));\n\t\t\tenable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep));\n\t\t} else {\n\t\t\tcheck_bits = importDefSigSpec(assumes_a[pf], timestep);\n\t\t\tenable_bits = importDefSigSpec(assumes_en[pf], timestep);\n\t\t}\n\t\treturn ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits)));\n\t}\n\n\tint signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1)\n\t{\n\t\tif (timestep_rhs < 0)\n\t\t\ttimestep_rhs = timestep_lhs;\n\n\t\tlog_assert(lhs.size() == rhs.size());\n\n\t\tstd::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);\n\n\t\tif (!model_undef)\n\t\t\treturn ez->vec_eq(vec_lhs, vec_rhs);\n\n\t\tstd::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs);\n\t\tstd::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);\n\n\t\tstd::vector<int> eq_bits;\n\t\tfor (int i = 0; i < lhs.size(); i++)\n\t\t\teq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),\n\t\t\t\t\tez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));\n\t\treturn ez->expression(ezSAT::OpAnd, eq_bits);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed;\n\t\tif (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)\n\t\t\tis_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();\n\t\twhile (vec_a.size() < vec_b.size() || vec_a.size() < y_width)\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_b.size() < vec_a.size() || vec_b.size() < y_width)\n\t\t\tvec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE);\n\t}\n\n\tvoid extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\textendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)\n\t{\n\t\tbool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());\n\t\twhile (vec_a.size() < vec_y.size())\n\t\t\tvec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);\n\t\twhile (vec_y.size() < vec_a.size())\n\t\t\tvec_y.push_back(ez->literal());\n\t}\n\n\tvoid undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)\n\t{\n\t\tlog_assert(model_undef);\n\t\tlog_assert(vec_y.size() == vec_yy.size());\n\t\tif (vec_y.size() > vec_undef.size()) {\n\t\t\tstd::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());\n\t\t\tstd::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));\n\t\t} else {\n\t\t\tlog_assert(vec_y.size() == vec_undef.size());\n\t\t\tez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));\n\t\t}\n\t}\n\n\tstd::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) {\n\t\tstd::vector<int> res;\n\t\tstd::vector<int> undef_res;\n\t\tres = ez->vec_ite(s, b, a);\n\t\tif (model_undef) {\n\t\t\tstd::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));\n\t\t\tstd::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));\n\t\t\tundef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a));\n\t\t}\n\t\treturn std::make_pair(res, undef_res);\n\t}\n\n\tvoid undefGating(int y, int yy, int undef)\n\t{\n\t\tez->assume(ez->OR(undef, ez->IFF(y, yy)));\n\t}\n\n\tvoid setInitState(int timestep)\n\t{\n\t\tauto key = make_pair(prefix, timestep);\n\t\tlog_assert(initstates.count(key) == 0 || initstates.at(key) == true);\n\t\tinitstates[key] = true;\n\t}\n\n\tbool importCell(RTLIL::Cell *cell, int timestep = -1);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "scopeinfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2024 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SCOPEINFO_H\n#define SCOPEINFO_H\n\n#include <vector>\n#include <algorithm>\n\n#include \"kernel/yosys.h\"\n#include \"kernel/celltypes.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\ntemplate<typename T>\nclass IdTree\n{\npublic:\n\tstruct Cursor;\n\nprotected:\n\tIdTree *parent = nullptr;\n\tIdString scope_name;\n\tint depth = 0;\n\n\tpool<IdString> names;\n\tdict<IdString, T> entries;\npublic: // XXX\n\tdict<IdString, std::unique_ptr<IdTree>> subtrees;\n\n\ttemplate<typename P, typename T_ref>\n\tstatic Cursor do_insert(IdTree *tree, P begin, P end, T_ref &&value)\n\t{\n\t\tlog_assert(begin != end && \"path must be non-empty\");\n\t\twhile (true) {\n\t\t\tIdString name = *begin;\n\t\t\t++begin;\n\t\t\tlog_assert(!name.empty());\n\t\t\ttree->names.insert(name);\n\t\t\tif (begin == end) {\n\t\t\t\ttree->entries.emplace(name, std::forward<T_ref>(value));\n\t\t\t\treturn Cursor(tree, name);\n\t\t\t}\n\t\t\tauto &unique = tree->subtrees[name];\n\t\t\tif (!unique) {\n\t\t\t\tunique.reset(new IdTree);\n\t\t\t\tunique->scope_name = name;\n\t\t\t\tunique->parent = tree;\n\t\t\t\tunique->depth = tree->depth + 1;\n\t\t\t}\n\t\t\ttree = unique.get();\n\t\t}\n\t}\n\npublic:\n\tIdTree() = default;\n\tIdTree(const IdTree &) = delete;\n\tIdTree(IdTree &&) = delete;\n\n\t// A cursor remains valid as long as the (sub-)IdTree it points at is alive\n\tstruct Cursor\n\t{\n\t\tfriend class IdTree;\n\tprotected:\n\tpublic:\n\t\tIdTree *target;\n\t\tIdString scope_name;\n\n\t\tCursor() : target(nullptr) {}\n\t\tCursor(IdTree *target, IdString scope_name) : target(target), scope_name(scope_name) {\n\t\t\tif (scope_name.empty())\n\t\t\t\tlog_assert(target->parent == nullptr);\n\t\t}\n\n\t\tCursor do_first_child() {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (tree->names.empty()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *tree->names.begin());\n\t\t}\n\n\t\tCursor do_next_sibling() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tauto found = target->names.find(scope_name);\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\t++found;\n\t\t\tif (found == target->names.end())\n\t\t\t\treturn Cursor();\n\t\t\treturn Cursor(target, *found);\n\t\t}\n\n\t\tCursor do_parent() {\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn Cursor();\n\t\t\tif (target->parent != nullptr)\n\t\t\t\treturn Cursor(target->parent, target->scope_name);\n\t\t\treturn Cursor(target, IdString());\n\t\t}\n\n\t\tCursor do_next_preorder() {\n\t\t\tCursor current = *this;\n\t\t\tCursor next = current.do_first_child();\n\t\t\tif (next.valid())\n\t\t\t\treturn next;\n\t\t\twhile (current.valid()) {\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tnext = current.do_next_sibling();\n\t\t\t\tif (next.valid())\n\t\t\t\t\treturn next;\n\t\t\t\tcurrent = current.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\n\t\tCursor do_child(IdString name) {\n\t\t\tIdTree *tree = nullptr;\n\t\t\tif (scope_name.empty()) {\n\t\t\t\ttree = target;\n\t\t\t} else {\n\t\t\t\tauto found = target->subtrees.find(scope_name);\n\t\t\t\tif (found != target->subtrees.end()) {\n\t\t\t\t\ttree = found->second.get();\n\t\t\t\t} else {\n\t\t\t\t\treturn Cursor();\n\t\t\t\t}\n\t\t\t}\n\t\t\tauto found = tree->names.find(name);\n\t\t\tif (found == tree->names.end()) {\n\t\t\t\treturn Cursor();\n\t\t\t}\n\t\t\treturn Cursor(tree, *found);\n\t\t}\n\n\tpublic:\n\t\tbool operator==(const Cursor &other) const {\n\t\t\treturn target == other.target && scope_name == other.scope_name;\n\t\t}\n\t\tbool operator!=(const Cursor &other) const {\n\t\t\treturn !(*this == other);\n\t\t}\n\n\t\tbool valid() const {\n\t\t\treturn target != nullptr;\n\t\t}\n\n\t\tint depth() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn target->depth + !scope_name.empty();\n\t\t}\n\n\t\tbool is_root() const {\n\t\t\treturn target != nullptr && scope_name.empty();\n\t\t}\n\n\t\tbool has_entry() const {\n\t\t\tlog_assert(valid());\n\t\t\treturn !scope_name.empty() && target->entries.count(scope_name);\n\t\t}\n\n\t\tT &entry() {\n\t\t\tlog_assert(!scope_name.empty());\n\t\t\treturn target->entries.at(scope_name);\n\t\t}\n\n\t\tvoid assign_path_to(std::vector<IdString> &out_path) {\n\t\t\tlog_assert(valid());\n\t\t\tout_path.clear();\n\t\t\tif (scope_name.empty())\n\t\t\t\treturn;\n\t\t\tout_path.push_back(scope_name);\n\t\t\tIdTree *current = target;\n\t\t\twhile (current->parent) {\n\t\t\t\tout_path.push_back(current->scope_name);\n\t\t\t\tcurrent = current->parent;\n\t\t\t}\n\t\t\tstd::reverse(out_path.begin(), out_path.end());\n\t\t}\n\n\t\tstd::vector<IdString> path() {\n\t\t\tstd::vector<IdString> result;\n\t\t\tassign_path_to(result);\n\t\t\treturn result;\n\t\t}\n\n\t\tstd::string path_str() {\n\t\t\tstd::string result;\n\t\t\tfor (const auto &item : path()) {\n\t\t\t\tif (!result.empty())\n\t\t\t\t\tresult.push_back(' ');\n\t\t\t\tresult += RTLIL::unescape_id(item);\n\t\t\t}\n\t\t\treturn result;\n\t\t}\n\n\t\tCursor first_child() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_first_child();\n\t\t}\n\n\t\tCursor next_preorder() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_next_preorder();\n\t\t}\n\n\t\tCursor parent() {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_parent();\n\t\t}\n\n\t\tCursor child(IdString name) {\n\t\t\tlog_assert(valid());\n\t\t\treturn do_child(name);\n\t\t}\n\n\t\tCursor common_ancestor(Cursor other) {\n\t\t\tCursor current = *this;\n\n\t\t\twhile (current != other) {\n\t\t\t\tif (!current.valid() || !other.valid())\n\t\t\t\t\treturn Cursor();\n\t\t\t\tint delta = current.depth() - other.depth();\n\t\t\t\tif (delta >= 0)\n\t\t\t\t\tcurrent = current.do_parent();\n\t\t\t\tif (delta <= 0)\n\t\t\t\t\tother = other.do_parent();\n\t\t\t}\n\t\t\treturn current;\n\t\t}\n\t};\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, const T &value) {\n\t\treturn do_insert(this, begin, end, value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(P begin, P end, T &&value) {\n\t\treturn do_insert(this, begin, end, std::move(value));\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, const T &value) {\n\t\treturn do_insert(this, path.begin(), path.end(), value);\n\t}\n\n\ttemplate<typename P>\n\tCursor insert(const P &path, T &&value) {\n\t\treturn do_insert(this, path.begin(), path.end(), std::move(value));\n\t}\n\n\tCursor cursor() {\n\t\treturn parent ? Cursor(this->parent, this->scope_name) : Cursor(this, IdString());\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(P begin, P end) {\n\t\tCursor current = cursor();\n\t\tfor (; begin != end; ++begin) {\n\t\t\tcurrent = current.do_child(*begin);\n\t\t\tif (!current.valid())\n\t\t\t\tbreak;\n\t\t}\n\t\treturn current;\n\t}\n\n\ttemplate<typename P>\n\tCursor cursor(const P &path) {\n\t\treturn cursor(path.begin(), path.end());\n\t}\n};\n\n\nstruct ModuleItem {\n\tenum class Type {\n\t\tWire,\n\t\tCell,\n\t};\n\tType type;\n\tvoid *ptr;\n\n\tModuleItem(Wire *wire) : type(Type::Wire), ptr(wire) {}\n\tModuleItem(Cell *cell) : type(Type::Cell), ptr(cell) {}\n\n\tbool is_wire() const { return type == Type::Wire; }\n\tbool is_cell() const { return type == Type::Cell; }\n\n\tWire *wire() const { return type == Type::Wire ? static_cast<Wire *>(ptr) : nullptr; }\n\tCell *cell() const { return type == Type::Cell ? static_cast<Cell *>(ptr) : nullptr; }\n\n\tbool operator==(const ModuleItem &other) const { return ptr == other.ptr && type == other.type; }\n\tunsigned int hash() const { return (uintptr_t)ptr; }\n};\n\nstatic inline void log_dump_val_worker(typename IdTree<ModuleItem>::Cursor cursor ) { log(\"%p %s\", cursor.target, log_id(cursor.scope_name)); }\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(const typename std::unique_ptr<T> &cursor ) { log(\"unique %p\", cursor.get()); }\n\ntemplate<typename O>\nstd::vector<IdString> parse_hdlname(const O* object)\n{\n\tstd::vector<IdString> path;\n\tif (!object->name.isPublic())\n\t\treturn path;\n\tfor (auto const &item : object->get_hdlname_attribute())\n\t\tpath.push_back(\"\\\\\" + item);\n\tif (path.empty())\n\t\tpath.push_back(object->name);\n\treturn path;\n}\n\ntemplate<typename O>\nstd::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)\n{\n\tstd::vector<IdString> path;\n\tIdString trailing = object->name;\n\tif (object->name.isPublic()) {\n\t\tfor (auto const &item : object->get_hdlname_attribute())\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (!path.empty()) {\n\t\t\ttrailing = path.back();\n\t\t\tpath.pop_back();\n\t\t}\n\t} else {\n\t\tfor (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), \" \"))\n\t\t\tpath.push_back(\"\\\\\" + item);\n\n\t}\n\treturn {path, trailing};\n}\n\nstruct ModuleHdlnameIndex {\n\ttypedef IdTree<ModuleItem>::Cursor Cursor;\n\n\tRTLIL::Module *module;\n\tIdTree<ModuleItem> tree;\n\tdict<ModuleItem, Cursor> lookup;\n\n\tModuleHdlnameIndex(RTLIL::Module *module) : module(module) {}\n\nprivate:\n\ttemplate<typename I, typename Filter>\n\tvoid index_items(I begin, I end, Filter filter);\n\npublic:\n\t// Index all wires and cells of the module\n\tvoid index();\n\n\t// Index all wires of the module\n\tvoid index_wires();\n\n\t// Index all cells of the module\n\tvoid index_cells();\n\n\t// Index only the $scopeinfo cells of the module.\n\t// This is sufficient when using `containing_scope`.\n\tvoid index_scopeinfo_cells();\n\n\n\t// Return the cursor for the containing scope of some RTLIL object (Wire/Cell/...)\n\ttemplate<typename O>\n\tstd::pair<Cursor, IdString> containing_scope(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\treturn {tree.cursor(pair.first), pair.second};\n\t}\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the scope represented by the cursor. The vector alternates module and\n\t// module item source locations, using empty strings for missing src\n\t// attributes.\n\tstd::vector<std::string> scope_sources(Cursor cursor);\n\n\t// Return a vector of source locations starting from the indexed module to\n\t// the passed RTLIL object (Wire/Cell/...). The vector alternates module\n\t// and module item source locations, using empty strings for missing src\n\t// attributes.\n\ttemplate<typename O>\n\tstd::vector<std::string> sources(O *object) {\n\t\tauto pair = parse_scopename(object);\n\t\tstd::vector<std::string> result = scope_sources(tree.cursor(pair.first));\n\t\tresult.push_back(object->get_src_attribute());\n\t\treturn result;\n\t}\n};\n\nenum class ScopeinfoAttrs {\n\tModule,\n\tCell,\n};\n\n// Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.\nbool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\nRTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);\n\n// Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.\ndict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "sigtools.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef SIGTOOLS_H\n#define SIGTOOLS_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct SigPool\n{\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tpool<bitDef_t> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.insert(bit);\n\t}\n\n\tvoid add(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.insert(bit);\n\t}\n\n\tvoid del(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits.erase(bit);\n\t}\n\n\tvoid del(const SigPool &other)\n\t{\n\t\tfor (auto &bit : other.bits)\n\t\t\tbits.erase(bit);\n\t}\n\n\tvoid expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\t\tfor (int i = 0; i < GetSize(from); i++) {\n\t\t\tbitDef_t bit_from(from[i]), bit_to(to[i]);\n\t\t\tif (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)\n\t\t\t\tbits.insert(bit_to);\n\t\t}\n\t}\n\n\tRTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tRTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::SigSpec result;\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\tresult.append(bit);\n\t\treturn result;\n\t}\n\n\tbool check(const RTLIL::SigBit &bit) const\n\t{\n\t\treturn bit.wire != NULL && bits.count(bit);\n\t}\n\n\tbool check_any(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n\n\tbool check_all(const RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit) == 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tRTLIL::SigSpec export_one() const\n\t{\n\t\tfor (auto &bit : bits)\n\t\t\treturn RTLIL::SigSpec(bit.first, bit.second);\n\t\treturn RTLIL::SigSpec();\n\t}\n\n\tRTLIL::SigSpec export_all() const\n\t{\n\t\tpool<RTLIL::SigBit> sig;\n\t\tfor (auto &bit : bits)\n\t\t\tsig.insert(RTLIL::SigBit(bit.first, bit.second));\n\t\treturn sig;\n\t}\n\n\tsize_t size() const\n\t{\n\t\treturn bits.size();\n\t}\n};\n\ntemplate <typename T, class Compare = void>\nstruct SigSet\n{\n\tstatic_assert(!std::is_same<Compare,void>::value, \"Default value for `Compare' class not found for SigSet<T>. Please specify.\");\n\n\tstruct bitDef_t : public std::pair<RTLIL::Wire*, int> {\n\t\tbitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }\n\t\tbitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }\n\t\tunsigned int hash() const { return first->name.hash() + second; }\n\t};\n\n\tdict<bitDef_t, std::set<T, Compare>> bits;\n\n\tvoid clear()\n\t{\n\t\tbits.clear();\n\t}\n\n\tvoid insert(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data);\n\t}\n\n\tvoid insert(const RTLIL::SigSpec& sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].insert(data.begin(), data.end());\n\t}\n\n\tvoid erase(const RTLIL::SigSpec& sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].clear();\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, T data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data);\n\t}\n\n\tvoid erase(const RTLIL::SigSpec &sig, const std::set<T> &data)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL)\n\t\t\t\tbits[bit].erase(data.begin(), data.end());\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, std::set<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tvoid find(const RTLIL::SigSpec &sig, pool<T> &result)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tif (bit.wire != NULL) {\n\t\t\t\tauto &data = bits[bit];\n\t\t\t\tresult.insert(data.begin(), data.end());\n\t\t\t}\n\t}\n\n\tstd::set<T> find(const RTLIL::SigSpec &sig)\n\t{\n\t\tstd::set<T> result;\n\t\tfind(sig, result);\n\t\treturn result;\n\t}\n\n\tbool has(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tif (bit.wire != NULL && bits.count(bit))\n\t\t\t\treturn true;\n\t\treturn false;\n\t}\n};\n\ntemplate<typename T>\nclass SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};\ntemplate<typename T>\nusing sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;\ntemplate<typename T>\nclass SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};\n\nstruct SigMap\n{\n\tmfp<SigBit> database;\n\n\tSigMap(RTLIL::Module *module = NULL)\n\t{\n\t\tif (module != NULL)\n\t\t\tset(module);\n\t}\n\n\tvoid swap(SigMap &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid clear()\n\t{\n\t\tdatabase.clear();\n\t}\n\n\tvoid set(RTLIL::Module *module)\n\t{\n\t\tint bitcount = 0;\n\t\tfor (auto &it : module->connections())\n\t\t\tbitcount += it.first.size();\n\n\t\tdatabase.clear();\n\t\tdatabase.reserve(bitcount);\n\n\t\tfor (auto &it : module->connections())\n\t\t\tadd(it.first, it.second);\n\t}\n\n\tvoid add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)\n\t{\n\t\tlog_assert(GetSize(from) == GetSize(to));\n\n\t\tfor (int i = 0; i < GetSize(from); i++)\n\t\t{\n\t\t\tint bfi = database.lookup(from[i]);\n\t\t\tint bti = database.lookup(to[i]);\n\n\t\t\tconst RTLIL::SigBit &bf = database[bfi];\n\t\t\tconst RTLIL::SigBit &bt = database[bti];\n\n\t\t\tif (bf.wire || bt.wire)\n\t\t\t{\n\t\t\t\tdatabase.imerge(bfi, bti);\n\n\t\t\t\tif (bf.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bfi);\n\n\t\t\t\tif (bt.wire == nullptr)\n\t\t\t\t\tdatabase.ipromote(bti);\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid add(const RTLIL::SigBit &bit)\n\t{\n\t\tconst auto &b = database.find(bit);\n\t\tif (b.wire != nullptr)\n\t\t\tdatabase.promote(bit);\n\t}\n\n\tvoid add(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (const auto &bit : sig)\n\t\t\tadd(bit);\n\t}\n\n\tinline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }\n\n\tvoid apply(RTLIL::SigBit &bit) const\n\t{\n\t\tbit = database.find(bit);\n\t}\n\n\tvoid apply(RTLIL::SigSpec &sig) const\n\t{\n\t\tfor (auto &bit : sig)\n\t\t\tapply(bit);\n\t}\n\n\tRTLIL::SigBit operator()(RTLIL::SigBit bit) const\n\t{\n\t\tapply(bit);\n\t\treturn bit;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::SigSpec sig) const\n\t{\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec operator()(RTLIL::Wire *wire) const\n\t{\n\t\tSigSpec sig(wire);\n\t\tapply(sig);\n\t\treturn sig;\n\t}\n\n\tRTLIL::SigSpec allbits() const\n\t{\n\t\tRTLIL::SigSpec sig;\n\t\tfor (const auto &bit : database)\n\t\t\tif (bit.wire != nullptr)\n\t\t\t\tsig.append(bit);\n\t\treturn sig;\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif /* SIGTOOLS_H */\n",
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  "timinginfo.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * (C) 2020 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef TIMINGINFO_H\n#define TIMINGINFO_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct TimingInfo\n{\n\tstruct NameBit\n\t{\n\t\tRTLIL::IdString name;\n\t\tint offset;\n\t\tNameBit() : offset(0) {}\n\t\tNameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}\n\t\texplicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}\n\t\tbool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }\n\t\tbool operator!=(const NameBit& nb) const { return !operator==(nb); }\n\t\tunsigned int hash() const { return mkhash_add(name.hash(), offset); }\n\t};\n\tstruct BitBit\n\t{\n\t\tNameBit first, second;\n\t\tBitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}\n\t\tBitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}\n\t\tbool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }\n\t\tunsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }\n\t};\n\n\tstruct ModuleTiming\n\t{\n\t\tdict<BitBit, int> comb;\n\t\tdict<NameBit, std::pair<int,NameBit>> arrival, required;\n\t\tbool has_inputs;\n\t};\n\n\tdict<RTLIL::IdString, ModuleTiming> data;\n\n\tTimingInfo()\n\t{\n\t}\n\n\tTimingInfo(RTLIL::Design *design)\n\t{\n\t\tsetup(design);\n\t}\n\n\tvoid setup(RTLIL::Design *design)\n\t{\n\t\tfor (auto module : design->modules()) {\n\t\t\tif (!module->get_blackbox_attribute())\n\t\t\t\tcontinue;\n\t\t\tsetup_module(module);\n\t\t}\n\t}\n\n\tconst ModuleTiming& setup_module(RTLIL::Module *module)\n\t{\n\t\tauto r = data.insert(module->name);\n\t\tlog_assert(r.second);\n\t\tauto &t = r.first->second;\n\n\t\tfor (auto cell : module->cells()) {\n\t\t\tif (cell->type == ID($specify2)) {\n\t\t\t\tauto en = cell->getPort(ID::EN);\n\t\t\t\tif (en.is_fully_const() && !en.as_bool())\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\tif (cell->getParam(ID::FULL).as_bool()) {\n\t\t\t\t\tfor (const auto &s : src)\n\t\t\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\tlog_assert(GetSize(src) == GetSize(dst));\n\t\t\t\t\tfor (auto i = 0; i < GetSize(src); i++) {\n\t\t\t\t\t\tconst auto &s = src[i];\n\t\t\t\t\t\tconst auto &d = dst[i];\n\t\t\t\t\t\tauto r = t.comb.insert(BitBit(s,d));\n\t\t\t\t\t\tif (!r.second)\n\t\t\t\t\t\t\tlog_error(\"Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\\n\", log_id(module), log_signal(s), log_signal(d));\n\t\t\t\t\t\tr.first->second = max;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specify3)) {\n\t\t\t\tauto src = cell->getPort(ID::SRC).as_bit();\n\t\t\t\tauto dst = cell->getPort(ID::DST);\n\t\t\t\tif (!src.wire || !src.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tfor (const auto &c : dst.chunks())\n\t\t\t\t\tif (!c.wire->port_output)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint rise_max = cell->getParam(ID::T_RISE_MAX).as_int();\n\t\t\t\tint fall_max = cell->getParam(ID::T_FALL_MAX).as_int();\n\t\t\t\tint max = std::max(rise_max,fall_max);\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &d : dst) {\n\t\t\t\t\tauto r = t.arrival.insert(NameBit(d));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(src);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if (cell->type == ID($specrule)) {\n\t\t\t\tIdString type = cell->getParam(ID::TYPE).decode_string();\n\t\t\t\tif (type != ID($setup) && type != ID($setuphold))\n\t\t\t\t\tcontinue;\n\t\t\t\tauto src = cell->getPort(ID::SRC);\n\t\t\t\tauto dst = cell->getPort(ID::DST).as_bit();\n\t\t\t\tfor (const auto &c : src.chunks())\n\t\t\t\t\tif (!c.wire || !c.wire->port_input)\n\t\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(src));\n\t\t\t\tif (!dst.wire || !dst.wire->port_input)\n\t\t\t\t\tlog_error(\"Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\\n\", log_id(module), log_id(cell), log_signal(dst));\n\t\t\t\tint max = cell->getParam(ID::T_LIMIT_MAX).as_int();\n\t\t\t\tif (max < 0) {\n\t\t\t\t\tlog_warning(\"Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\\n\", log_id(module), log_id(cell));\n\t\t\t\t\tmax = 0;\n\t\t\t\t}\n\t\t\t\tfor (const auto &s : src) {\n\t\t\t\t\tauto r = t.required.insert(NameBit(s));\n\t\t\t\t\tauto &v = r.first->second;\n\t\t\t\t\tif (r.second || v.first < max) {\n\t\t\t\t\t\tv.first = max;\n\t\t\t\t\t\tv.second = NameBit(dst);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfor (auto port_name : module->ports) {\n\t\t\tauto wire = module->wire(port_name);\n\t\t\tif (wire->port_input) {\n\t\t\t\tt.has_inputs = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\treturn t;\n\t}\n\n\tdecltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }\n\tdecltype(data)::const_iterator end() const { return data.end(); }\n\tint count(RTLIL::IdString module_name) const { return data.count(module_name); }\n\tconst ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "utils.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file contains various c++ utility routines and helper classes that\n// do not depend on any other components of yosys (except stuff like log_*).\n\n#include \"kernel/yosys.h\"\n\n#ifndef UTILS_H\n#define UTILS_H\n\nYOSYS_NAMESPACE_BEGIN\n\n// ------------------------------------------------\n// A map-like container, but you can save and restore the state\n// ------------------------------------------------\n\ntemplate<typename Key, typename T, typename OPS = hash_ops<Key>>\nstruct stackmap\n{\nprivate:\n\tstd::vector<dict<Key, T*, OPS>> backup_state;\n\tdict<Key, T, OPS> current_state;\n\tstatic T empty_tuple;\n\npublic:\n\tstackmap() { }\n\tstackmap(const dict<Key, T, OPS> &other) : current_state(other) { }\n\n\ttemplate<typename Other>\n\tvoid operator=(const Other &other)\n\t{\n\t\tfor (auto &it : current_state)\n\t\t\tif (!backup_state.empty() && backup_state.back().count(it.first) == 0)\n\t\t\t\tbackup_state.back()[it.first] = new T(it.second);\n\t\tcurrent_state.clear();\n\n\t\tfor (auto &it : other)\n\t\t\tset(it.first, it.second);\n\t}\n\n\tbool has(const Key &k)\n\t{\n\t\treturn current_state.count(k) != 0;\n\t}\n\n\tvoid set(const Key &k, const T &v)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state[k] = v;\n\t}\n\n\tvoid unset(const Key &k)\n\t{\n\t\tif (!backup_state.empty() && backup_state.back().count(k) == 0)\n\t\t\tbackup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr;\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst T &get(const Key &k)\n\t{\n\t\tif (current_state.count(k) == 0)\n\t\t\treturn empty_tuple;\n\t\treturn current_state.at(k);\n\t}\n\n\tvoid reset(const Key &k)\n\t{\n\t\tfor (int i = GetSize(backup_state)-1; i >= 0; i--)\n\t\t\tif (backup_state[i].count(k) != 0) {\n\t\t\t\tif (backup_state[i].at(k) == nullptr)\n\t\t\t\t\tcurrent_state.erase(k);\n\t\t\t\telse\n\t\t\t\t\tcurrent_state[k] = *backup_state[i].at(k);\n\t\t\t\treturn;\n\t\t\t}\n\t\tcurrent_state.erase(k);\n\t}\n\n\tconst dict<Key, T, OPS> &stdmap()\n\t{\n\t\treturn current_state;\n\t}\n\n\tvoid save()\n\t{\n\t\tbackup_state.resize(backup_state.size()+1);\n\t}\n\n\tvoid restore()\n\t{\n\t\tlog_assert(!backup_state.empty());\n\t\tfor (auto &it : backup_state.back())\n\t\t\tif (it.second != nullptr) {\n\t\t\t\tcurrent_state[it.first] = *it.second;\n\t\t\t\tdelete it.second;\n\t\t\t} else\n\t\t\t\tcurrent_state.erase(it.first);\n\t\tbackup_state.pop_back();\n\t}\n\n\t~stackmap()\n\t{\n\t\twhile (!backup_state.empty())\n\t\t\trestore();\n\t}\n};\n\n\n// ------------------------------------------------\n// A simple class for topological sorting\n// ------------------------------------------------\n\ntemplate <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> class TopoSort\n{\n public:\n\t// We use this ordering of the edges in the adjacency matrix for\n\t// exact compatibility with an older implementation.\n\tstruct IndirectCmp {\n IndirectCmp(const std::vector<T> &nodes) : node_cmp_(), nodes_(nodes) {}\n\t\tbool operator()(int a, int b) const\n\t\t{\n log_assert(static_cast<size_t>(a) < nodes_.size());\n\t\t\tlog_assert(static_cast<size_t>(b) < nodes_.size());\n\t\t\treturn node_cmp_(nodes_[a], nodes_[b]);\n\t\t}\n\t\tconst C node_cmp_;\n\t\tconst std::vector<T> &nodes_;\n\t};\n\n\tbool analyze_loops;\n\tstd::map<T, int, C> node_to_index;\n\tstd::vector<std::set<int, IndirectCmp>> edges;\n\tstd::vector<T> sorted;\n\tstd::set<std::vector<T>> loops;\n\n\tTopoSort() : indirect_cmp(nodes)\n\t{\n\t\tanalyze_loops = true;\n\t\tfound_loops = false;\n\t}\n\n\tint node(T n)\n\t{\n auto rv = node_to_index.emplace(n, static_cast<int>(nodes.size()));\n if (rv.second) {\n \t nodes.push_back(n);\n\t\t edges.push_back(std::set<int, IndirectCmp>(indirect_cmp));\n\t\t}\n\t\treturn rv.first->second;\n\t}\n\n\tvoid edge(int l_index, int r_index) { edges[r_index].insert(l_index); }\n\n\tvoid edge(T left, T right) { edge(node(left), node(right)); }\n\n\tbool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }\n\n\tbool sort()\n\t{\n\t\tlog_assert(GetSize(node_to_index) == GetSize(edges));\n\t\tlog_assert(GetSize(nodes) == GetSize(edges));\n\n\t\tloops.clear();\n\t\tsorted.clear();\n\t\tfound_loops = false;\n\n\t\tstd::vector<bool> marked_cells(edges.size(), false);\n\t\tstd::vector<bool> active_cells(edges.size(), false);\n\t\tstd::vector<int> active_stack;\n\t\tsorted.reserve(edges.size());\n\n\t\tfor (const auto &it : node_to_index)\n\t\t\tsort_worker(it.second, marked_cells, active_cells, active_stack);\n\n\t\tlog_assert(GetSize(sorted) == GetSize(nodes));\n\n\t\treturn !found_loops;\n\t}\n\n\t// Build the more expensive representation of edges for\n\t// a few passes that use it directly.\n\tstd::map<T, std::set<T, C>, C> get_database()\n\t{\n\t\tstd::map<T, std::set<T, C>, C> database;\n\t\tfor (size_t i = 0; i < nodes.size(); ++i) {\n\t\t\tstd::set<T, C> converted_edge_set;\n\t\t\tfor (int other_node : edges[i]) {\n\t\t\t\tconverted_edge_set.insert(nodes[other_node]);\n\t\t\t}\n\t\t\tdatabase.emplace(nodes[i], converted_edge_set);\n\t\t}\n\t\treturn database;\n\t}\n\n private:\n\tbool found_loops;\n\tstd::vector<T> nodes;\n\tconst IndirectCmp indirect_cmp;\n\n\tvoid sort_worker(const int root_index, std::vector<bool> &marked_cells, std::vector<bool> &active_cells, std::vector<int> &active_stack)\n\t{\n\t\tif (active_cells[root_index]) {\n\t\t\tfound_loops = true;\n\t\t\tif (analyze_loops) {\n\t\t\t\tstd::vector<T> loop;\n\t\t\t\tfor (int i = GetSize(active_stack) - 1; i >= 0; i--) {\n\t\t\t\t\tconst int index = active_stack[i];\n\t\t\t\t\tloop.push_back(nodes[index]);\n\t\t\t\t\tif (index == root_index)\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tloops.insert(loop);\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\n\t\tif (marked_cells[root_index])\n\t\t\treturn;\n\n\t\tif (!edges[root_index].empty()) {\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.push_back(root_index);\n\t\t\tactive_cells[root_index] = true;\n\n\t\t\tfor (int left_n : edges[root_index])\n\t\t\t\tsort_worker(left_n, marked_cells, active_cells, active_stack);\n\n\t\t\tif (analyze_loops)\n\t\t\t\tactive_stack.pop_back();\n\t\t\tactive_cells[root_index] = false;\n\t\t}\n\n\t\tmarked_cells[root_index] = true;\n\t\tsorted.push_back(nodes[root_index]);\n\t}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
180
- "yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n//\n// Find more information in the \"guidelines/GettingStarted\" file.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#ifdef YOSYS_ENABLE_TCL\n# include <tcl.h>\n# ifdef YOSYS_MXE_HACKS\nextern Tcl_Command Tcl_CreateCommand(Tcl_Interp *interp, const char *cmdName, Tcl_CmdProc *proc, ClientData clientData, Tcl_CmdDeleteProc *deleteProc);\nextern Tcl_Interp *Tcl_CreateInterp(void);\nextern void Tcl_Preserve(ClientData data);\nextern void Tcl_Release(ClientData clientData);\nextern int Tcl_InterpDeleted(Tcl_Interp *interp);\nextern void Tcl_DeleteInterp(Tcl_Interp *interp);\nextern int Tcl_Eval(Tcl_Interp *interp, const char *script);\nextern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);\nextern void Tcl_Finalize(void);\nextern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);\nextern const char *Tcl_GetStringResult(Tcl_Interp *interp);\nextern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);\nextern Tcl_Obj *Tcl_NewIntObj(int intValue);\nextern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);\nextern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);\n# endif\n# undef CONST\n# undef INLINE\n#endif\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#elif defined(__clang__)\n# define YS_FALLTHROUGH [[clang::fallthrough]];\n#elif defined(__GNUC__)\n# define YS_FALLTHROUGH [[gnu::fallthrough]];\n#else\n# define YS_FALLTHROUGH\n#endif\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# undef HASHLIB_H\n# include \"kernel/hashlib.h\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\tunsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }\n};\n\nusing hashlib::mkhash;\nusing hashlib::mkhash_init;\nusing hashlib::mkhash_add;\nusing hashlib::mkhash_xorshift;\nusing hashlib::hash_ops;\nusing hashlib::hash_cstr_ops;\nusing hashlib::hash_ptr_ops;\nusing hashlib::hash_obj_ops;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n\tenum State : unsigned char;\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n // For the common case of strings shorter than 128, save a heap\n // allocation by using a stack allocated buffer.\n const int kBufSize = 128;\n char buf[kBufSize];\n buf[0] = '\\0';\n va_list apc;\n va_copy(apc, ap);\n int n = vsnprintf(buf, kBufSize, fmt, apc);\n va_end(apc);\n if (n < kBufSize)\n return std::string(buf);\n\n std::string string;\n char *str = NULL;\n#if defined(_WIN32 )|| defined(__CYGWIN__)\n int sz = 2 * kBufSize, rc;\n while (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char*)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n if (vasprintf(&str, fmt, ap) < 0)\n str = NULL;\n if (str != NULL) {\n string = str;\n free(str);\n }\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nYOSYS_NAMESPACE_END\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::State> : hash_ops<int> {};\n}\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n// sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
183
+ "yosys.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n\n// *** NOTE TO THE READER ***\n//\n// Maybe you have just opened this file in the hope to learn more about the\n// Yosys API. Let me congratulate you on this great decision! ;)\n//\n// If you want to know how the design is represented by Yosys in the memory,\n// you should read \"kernel/rtlil.h\".\n//\n// If you want to know how to register a command with Yosys, you could read\n// \"kernel/register.h\", but it would be easier to just look at a simple\n// example instead. A simple one would be \"passes/cmds/log.cc\".\n//\n// This header is very boring. It just defines some general things that\n// belong nowhere else and includes the interesting headers.\n//\n// Find more information in the \"guidelines/GettingStarted\" file.\n\n\n#ifndef YOSYS_H\n#define YOSYS_H\n\n#include \"kernel/yosys_common.h\"\n\n#include \"kernel/log.h\"\n#include \"kernel/rtlil.h\"\n#include \"kernel/register.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nvoid yosys_setup();\n\n#ifdef WITH_PYTHON\nbool yosys_already_setup();\n#endif\n\nvoid yosys_shutdown();\n\n#ifdef YOSYS_ENABLE_TCL\nTcl_Interp *yosys_get_tcl_interp();\n#endif\n\nextern RTLIL::Design *yosys_design;\n\nRTLIL::Design *yosys_get_design();\nstd::string proc_self_dirname();\nstd::string proc_share_dirname();\nstd::string proc_program_prefix();\nconst char *create_prompt(RTLIL::Design *design, int recursion_counter);\nstd::vector<std::string> glob_filename(const std::string &filename_pattern);\nvoid rewrite_filename(std::string &filename);\n\nvoid run_pass(std::string command, RTLIL::Design *design = nullptr);\nbool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);\nvoid run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);\nvoid shell(RTLIL::Design *design);\n\n// journal of all input and output files read (for \"yosys -E\")\nextern std::set<std::string> yosys_input_files, yosys_output_files;\n\n// from kernel/version_*.o (cc source generated from Makefile)\nextern const char *yosys_version_str;\n\n// from passes/cmds/design.cc\nextern std::map<std::string, RTLIL::Design*> saved_designs;\nextern std::vector<RTLIL::Design*> pushed_designs;\n\n// from passes/cmds/pluginc.cc\nextern std::map<std::string, void*> loaded_plugins;\n#ifdef WITH_PYTHON\nextern std::map<std::string, void*> loaded_python_plugins;\n#endif\nextern std::map<std::string, std::string> loaded_plugin_aliases;\nvoid load_plugin(std::string filename, std::vector<std::string> aliases);\n\nextern std::string yosys_share_dirname;\nextern std::string yosys_abc_executable;\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
184
+ "yosys_common.h": "/* -*- c++ -*-\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YOSYS_COMMON_H\n#define YOSYS_COMMON_H\n\n#include <map>\n#include <set>\n#include <tuple>\n#include <vector>\n#include <string>\n#include <algorithm>\n#include <functional>\n#include <unordered_map>\n#include <unordered_set>\n#include <initializer_list>\n#include <stdexcept>\n#include <memory>\n#include <cmath>\n#include <cstddef>\n\n#include <sstream>\n#include <fstream>\n#include <istream>\n#include <ostream>\n#include <iostream>\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <limits.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n#ifdef WITH_PYTHON\n#include <Python.h>\n#endif\n\n#ifndef _YOSYS_\n# error It looks like you are trying to build Yosys without the config defines set. \\\n When building Yosys with a custom make system, make sure you set all the \\\n defines the Yosys Makefile would set for your build configuration.\n#endif\n\n#ifdef YOSYS_ENABLE_TCL\n# include <tcl.h>\n# ifdef YOSYS_MXE_HACKS\nextern Tcl_Command Tcl_CreateCommand(Tcl_Interp *interp, const char *cmdName, Tcl_CmdProc *proc, ClientData clientData, Tcl_CmdDeleteProc *deleteProc);\nextern Tcl_Interp *Tcl_CreateInterp(void);\nextern void Tcl_Preserve(ClientData data);\nextern void Tcl_Release(ClientData clientData);\nextern int Tcl_InterpDeleted(Tcl_Interp *interp);\nextern void Tcl_DeleteInterp(Tcl_Interp *interp);\nextern int Tcl_Eval(Tcl_Interp *interp, const char *script);\nextern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);\nextern void Tcl_Finalize(void);\nextern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);\nextern const char *Tcl_GetStringResult(Tcl_Interp *interp);\nextern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);\nextern Tcl_Obj *Tcl_NewIntObj(int intValue);\nextern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);\nextern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);\n# endif\n# undef CONST\n# undef INLINE\n#endif\n\n#ifdef _WIN32\n# undef NOMINMAX\n# define NOMINMAX 1\n# undef YY_NO_UNISTD_H\n# define YY_NO_UNISTD_H 1\n\n# include <windows.h>\n# include <io.h>\n# include <direct.h>\n\n# define strtok_r strtok_s\n# define strdup _strdup\n# define snprintf _snprintf\n# define getcwd _getcwd\n# define mkdir _mkdir\n# define popen _popen\n# define pclose _pclose\n\n# ifndef __MINGW32__\n# define PATH_MAX MAX_PATH\n# define isatty _isatty\n# define fileno _fileno\n# endif\n\n// The following defines conflict with our identifiers:\n# undef CONST\n// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc\n# undef TRANSPARENT\n#endif\n\n#ifndef PATH_MAX\n# define PATH_MAX 4096\n#endif\n\n\n#define YOSYS_NAMESPACE Yosys\n#define PRIVATE_NAMESPACE_BEGIN namespace {\n#define PRIVATE_NAMESPACE_END }\n#define YOSYS_NAMESPACE_BEGIN namespace Yosys {\n#define YOSYS_NAMESPACE_END }\n#define YOSYS_NAMESPACE_PREFIX Yosys::\n#define USING_YOSYS_NAMESPACE using namespace Yosys;\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))\n#elif defined(_MSC_VER)\n# define YS_ATTRIBUTE(...)\n#else\n# define YS_ATTRIBUTE(...)\n#endif\n\n#if defined(__GNUC__) || defined(__clang__)\n# define YS_MAYBE_UNUSED __attribute__((__unused__))\n#else\n# define YS_MAYBE_UNUSED\n#endif\n\n#if __cplusplus >= 201703L\n# define YS_FALLTHROUGH [[fallthrough]];\n#elif defined(__clang__)\n# define YS_FALLTHROUGH [[clang::fallthrough]];\n#elif defined(__GNUC__)\n# define YS_FALLTHROUGH [[gnu::fallthrough]];\n#else\n# define YS_FALLTHROUGH\n#endif\n\n\nYOSYS_NAMESPACE_BEGIN\n\n// Note: All headers included in hashlib.h must be included\n// outside of YOSYS_NAMESPACE before this or bad things will happen.\n#ifdef HASHLIB_H\n# undef HASHLIB_H\n# include \"kernel/hashlib.h\"\n#else\n# include \"kernel/hashlib.h\"\n# undef HASHLIB_H\n#endif\n\n\nusing std::vector;\nusing std::string;\nusing std::tuple;\nusing std::pair;\n\nusing std::make_tuple;\nusing std::make_pair;\nusing std::get;\nusing std::min;\nusing std::max;\n\n// A primitive shared string implementation that does not\n// move its .c_str() when the object is copied or moved.\nstruct shared_str {\n\tstd::shared_ptr<string> content;\n\tshared_str() { }\n\tshared_str(string s) { content = std::shared_ptr<string>(new string(s)); }\n\tshared_str(const char *s) { content = std::shared_ptr<string>(new string(s)); }\n\tconst char *c_str() const { return content->c_str(); }\n\tconst string &str() const { return *content; }\n\tbool operator==(const shared_str &other) const { return *content == *other.content; }\n\tunsigned int hash() const { return hashlib::hash_ops<std::string>::hash(*content); }\n};\n\nusing hashlib::mkhash;\nusing hashlib::mkhash_init;\nusing hashlib::mkhash_add;\nusing hashlib::mkhash_xorshift;\nusing hashlib::hash_ops;\nusing hashlib::hash_cstr_ops;\nusing hashlib::hash_ptr_ops;\nusing hashlib::hash_obj_ops;\nusing hashlib::dict;\nusing hashlib::idict;\nusing hashlib::pool;\nusing hashlib::mfp;\n\nnamespace RTLIL {\n\tstruct IdString;\n\tstruct Const;\n\tstruct SigBit;\n\tstruct SigSpec;\n\tstruct Wire;\n\tstruct Cell;\n\tstruct Memory;\n\tstruct Process;\n\tstruct Module;\n\tstruct Design;\n\tstruct Monitor;\n struct Selection;\n\tstruct SigChunk;\n\tenum State : unsigned char;\n\n\ttypedef std::pair<SigSpec, SigSpec> SigSig;\n\n namespace ID {}\n}\n\nnamespace AST {\n\tstruct AstNode;\n}\n\nusing RTLIL::IdString;\nusing RTLIL::Const;\nusing RTLIL::SigBit;\nusing RTLIL::SigSpec;\nusing RTLIL::Wire;\nusing RTLIL::Cell;\nusing RTLIL::Module;\nusing RTLIL::Design;\n\nusing RTLIL::State;\nusing RTLIL::SigChunk;\nusing RTLIL::SigSig;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<AST::AstNode*> : hash_obj_ops {};\n\n\ttemplate<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};\n\ttemplate<> struct hash_ops<const AST::AstNode*> : hash_obj_ops {};\n}\n\nvoid memhasher_on();\nvoid memhasher_off();\nvoid memhasher_do();\n\nextern bool memhasher_active;\ninline void memhasher() { if (memhasher_active) memhasher_do(); }\n\nvoid yosys_banner();\nint ceil_log2(int x) YS_ATTRIBUTE(const);\n\ninline std::string vstringf(const char *fmt, va_list ap)\n{\n // For the common case of strings shorter than 128, save a heap\n // allocation by using a stack allocated buffer.\n const int kBufSize = 128;\n char buf[kBufSize];\n buf[0] = '\\0';\n va_list apc;\n va_copy(apc, ap);\n int n = vsnprintf(buf, kBufSize, fmt, apc);\n va_end(apc);\n if (n < kBufSize)\n return std::string(buf);\n\n std::string string;\n char *str = NULL;\n#if defined(_WIN32 )|| defined(__CYGWIN__)\n int sz = 2 * kBufSize, rc;\n while (1) {\n\t\tva_copy(apc, ap);\n\t\tstr = (char*)realloc(str, sz);\n\t\trc = vsnprintf(str, sz, fmt, apc);\n\t\tva_end(apc);\n\t\tif (rc >= 0 && rc < sz)\n\t\t\tbreak;\n\t\tsz *= 2;\n\t}\n\tif (str != NULL) {\n\t\tstring = str;\n\t\tfree(str);\n\t}\n\treturn string;\n#else\n if (vasprintf(&str, fmt, ap) < 0)\n str = NULL;\n if (str != NULL) {\n string = str;\n free(str);\n }\n\treturn string;\n#endif\n}\n\nstd::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\ninline std::string stringf(const char *fmt, ...)\n{\n\tstd::string string;\n\tva_list ap;\n\n\tva_start(ap, fmt);\n\tstring = vstringf(fmt, ap);\n\tva_end(ap);\n\n\treturn string;\n}\n\nint readsome(std::istream &f, char *s, int n);\nstd::string next_token(std::string &text, const char *sep = \" \\t\\r\\n\", bool long_strings = false);\nstd::vector<std::string> split_tokens(const std::string &text, const char *sep = \" \\t\\r\\n\");\nbool patmatch(const char *pattern, const char *string);\n#if !defined(YOSYS_DISABLE_SPAWN)\nint run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());\n#endif\nstd::string get_base_tmpdir();\nstd::string make_temp_file(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nstd::string make_temp_dir(std::string template_str = get_base_tmpdir() + \"/yosys_XXXXXX\");\nbool check_file_exists(std::string filename, bool is_exec = false);\nbool check_directory_exists(const std::string& dirname);\nbool is_absolute_path(std::string filename);\nvoid remove_directory(std::string dirname);\nbool create_directory(const std::string& dirname);\nstd::string escape_filename_spaces(const std::string& filename);\n\ntemplate<typename T> int GetSize(const T &obj) { return obj.size(); }\ninline int GetSize(RTLIL::Wire *wire);\n\nextern int autoidx;\nextern int yosys_xtrace;\n\nRTLIL::IdString new_id(std::string file, int line, std::string func);\nRTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);\n\n#define NEW_ID \\\n\tYOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)\n#define NEW_ID_SUFFIX(suffix) \\\n\tYOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)\n\n// Create a statically allocated IdString object, using for example ID::A or ID($add).\n//\n// Recipe for Converting old code that is using conversion of strings like ID::A and\n// \"$add\" for creating IdStrings: Run below SED command on the .cc file and then use for\n// example \"meld foo.cc foo.cc.orig\" to manually compile errors, if necessary.\n//\n// sed -i.orig -r 's/\"\\\\\\\\([a-zA-Z0-9_]+)\"/ID(\\1)/g; s/\"(\\$[a-zA-Z0-9_]+)\"/ID(\\1)/g;' <filename>\n//\n#define ID(_id) ([]() { const char *p = \"\\\\\" #_id, *q = p[1] == '$' ? p+1 : p; \\\n static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })()\nnamespace ID = RTLIL::ID;\n\nnamespace hashlib {\n\ttemplate<> struct hash_ops<RTLIL::State> : hash_ops<int> {};\n}\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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  "yw.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef YW_H\n#define YW_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/mem.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct IdPath : public std::vector<RTLIL::IdString>\n{\n\ttemplate<typename... T>\n\tIdPath(T&&... args) : std::vector<RTLIL::IdString>(std::forward<T>(args)...) { }\n\tIdPath prefix() const { return {begin(), end() - !empty()}; }\n\tstd::string str() const;\n\n\tbool has_address() const { int tmp; return get_address(tmp); };\n\tbool get_address(int &addr) const;\n\n\tint hash() const { return hashlib::hash_ops<std::vector<RTLIL::IdString>>::hash(*this); }\n};\n\nstruct WitnessHierarchyItem {\n\tRTLIL::Module *module;\n\tRTLIL::Wire *wire = nullptr;\n\tRTLIL::Cell *cell = nullptr;\n\tMem *mem = nullptr;\n\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Wire *wire) : module(module), wire(wire) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) {}\n\tWitnessHierarchyItem(RTLIL::Module *module, Mem *mem) : module(module), mem(mem) {}\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback);\n\ntemplate<class T> static std::vector<std::string> witness_path(T *obj) {\n\tstd::vector<std::string> path;\n\tif (obj->name.isPublic()) {\n\t\tauto hdlname = obj->get_string_attribute(ID::hdlname);\n\t\tfor (auto token : split_tokens(hdlname))\n\t\t\tpath.push_back(\"\\\\\" + token);\n\t}\n\tif (path.empty())\n\t\tpath.push_back(obj->name.str());\n\treturn path;\n}\n\nstruct ReadWitness\n{\n\tstruct Clock {\n\t\tIdPath path;\n\t\tint offset;\n\t\tbool is_posedge = false;\n\t\tbool is_negedge = false;\n\t};\n\n\tstruct Signal {\n\t\tIdPath path;\n\t\tint offset;\n\t\tint width;\n\t\tbool init_only;\n\n\t\tint bits_offset;\n\t};\n\n\tstruct Step {\n\t\tstd::string bits;\n\t};\n\n\tstd::string filename;\n\tstd::vector<Clock> clocks;\n\tstd::vector<Signal> signals;\n\tstd::vector<Step> steps;\n\n\tReadWitness(const std::string &filename);\n\n\tRTLIL::Const get_bits(int t, int bits_offset, int width) const;\n};\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *module, D data, T &callback)\n{\n\tauto const &const_path = path;\n\tsize_t path_size = path.size();\n\tfor (auto wire : module->wires())\n\t{\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : wire->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == wire->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty())\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(wire->name);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, wire), data);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto cell : module->cells())\n\t{\n\t\tModule *child = module->design->module(cell->type);\n\t\tif (child == nullptr)\n\t\t\tcontinue;\n\n\t\tauto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, 1, child, child_data, callback);\n\t\t}\n\t\tpath.resize(path_size);\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(cell->name);\n\t\t\tD child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);\n\t\t\twitness_hierarchy_recursion<D, T>(path, hdlname.empty() ? hdlname_mode : -1, child, child_data, callback);\n\t\t\tpath.pop_back();\n\t\t}\n\t}\n\n\tfor (auto mem : Mem::get_all_memories(module)) {\n\t\tstd::vector<std::string> hdlname;\n\n\t\tif (hdlname_mode >= 0 && mem.cell != nullptr)\n\t\t\thdlname = mem.cell->get_hdlname_attribute();\n\t\tfor (auto item : hdlname)\n\t\t\tpath.push_back(\"\\\\\" + item);\n\t\tif (hdlname.size() == 1 && path.back() == mem.cell->name)\n\t\t\thdlname.clear();\n\t\tif (!hdlname.empty()) {\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t}\n\t\tpath.resize(path_size);\n\n\t\tif (hdlname.empty() || hdlname_mode <= 0) {\n\t\t\tpath.push_back(mem.memid);\n\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\tpath.pop_back();\n\n\t\t\tif (mem.cell != nullptr && mem.cell->name != mem.memid) {\n\t\t\t\tpath.push_back(mem.cell->name);\n\t\t\t\tcallback(const_path, WitnessHierarchyItem(module, &mem), data);\n\t\t\t\tpath.pop_back();\n\t\t\t}\n\t\t}\n\t}\n}\n\ntemplate<typename D, typename T>\nvoid witness_hierarchy(RTLIL::Module *module, D data, T callback)\n{\n\tIdPath path;\n\twitness_hierarchy_recursion<D, T>(path, 0, module, data, callback);\n}\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
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@@ -333,9 +337,9 @@ export const filesystem = {
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  "cells_sim.v": "// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf\n\nmodule AND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A & B;\nendmodule\n\nmodule AND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A & B & C;\nendmodule\n\nmodule AND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A & B & C & D;\nendmodule\n\nmodule CFG1 (\n\toutput Y,\n\tinput A\n);\n\tparameter [1:0] INIT = 2'h0;\n\tassign Y = INIT >> A;\nendmodule\n\nmodule CFG2 (\n\toutput Y,\n\tinput A,\n\tinput B\n);\n\tparameter [3:0] INIT = 4'h0;\n\tassign Y = INIT >> {B, A};\nendmodule\n\nmodule CFG3 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C\n);\n\tparameter [7:0] INIT = 8'h0;\n\tassign Y = INIT >> {C, B, A};\nendmodule\n\nmodule CFG4 (\n\toutput Y,\n\tinput A,\n\tinput B,\n\tinput C,\n\tinput D\n);\n\tparameter [15:0] INIT = 16'h0;\n\tassign Y = INIT >> {D, C, B, A};\nendmodule\n\nmodule BUFF (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule BUFD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule CLKINT_PRESERVE (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule GCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule RCLKINT (\n\tinput A,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A;\nendmodule\n\nmodule RGCLKINT (\n\tinput A, EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tassign Y = A & EN;\nendmodule\n\nmodule SLE (\n\toutput Q,\n\tinput ADn,\n\tinput ALn,\n\t(* clkbuf_sink *)\n\tinput CLK,\n\tinput D,\n\tinput LAT,\n\tinput SD,\n\tinput EN,\n\tinput SLn\n);\n\treg q_latch, q_ff;\n\n\talways @(posedge CLK, negedge ALn) begin\n\t\tif (!ALn) begin\n\t\t\tq_ff <= !ADn;\n\t\tend else if (EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\talways @* begin\n\t\tif (!ALn) begin\n\t\t\tq_latch <= !ADn;\n\t\tend else if (CLK && EN) begin\n\t\t\tif (!SLn)\n\t\t\t\tq_ff <= SD;\n\t\t\telse\n\t\t\t\tq_ff <= D;\n\t\tend\n\tend\n\n\tassign Q = LAT ? q_latch : q_ff;\nendmodule\n\nmodule ARI1 (\n\tinput A, B, C, D, FCI,\n\toutput Y, S, FCO\n);\n\tparameter [19:0] INIT = 20'h0;\n\twire [2:0] Fsel = {D, C, B};\n\twire F0 = INIT[Fsel];\n\twire F1 = INIT[8 + Fsel];\n\twire Yout = A ? F1 : F0;\n\tassign Y = Yout;\n\tassign S = FCI ^ Yout;\n\twire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];\n\twire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);\n\tassign FCO = P ? FCI : G;\nendmodule\n\n// module FCEND_BUFF\n// module FCINIT_BUFF\n// module FLASH_FREEZE\n// module OSCILLATOR\n// module SYSCTRL_RESET_STATUS\n// module LIVE_PROBE_FB\n\n(* blackbox *)\nmodule GCLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\tinput EN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n(* blackbox *)\nmodule GCLKBIBUF (\n\tinput D,\n\tinput E,\n\tinput EN,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\nendmodule\n\n// module DFN1\n// module DFN1C0\n// module DFN1E1\n// module DFN1E1C0\n// module DFN1E1P0\n// module DFN1P0\n// module DLN1\n// module DLN1C0\n// module DLN1P0\n\nmodule INV (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule INVD (\n\tinput A,\n\toutput Y\n);\n\tassign Y = !A;\nendmodule\n\nmodule MX2 (\n\tinput A, B, S,\n\toutput Y\n);\n\tassign Y = S ? B : A;\nendmodule\n\nmodule MX4 (\n\tinput D0, D1, D2, D3, S0, S1,\n\toutput Y\n);\n\tassign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);\nendmodule\n\nmodule NAND2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A & B);\nendmodule\n\nmodule NAND3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A & B & C);\nendmodule\n\nmodule NAND4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A & B & C & D);\nendmodule\n\nmodule NOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = !(A | B);\nendmodule\n\nmodule NOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = !(A | B | C);\nendmodule\n\nmodule NOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = !(A | B | C | D);\nendmodule\n\nmodule OR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A | B;\nendmodule\n\nmodule OR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A | B | C;\nendmodule\n\nmodule OR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A | B | C | D;\nendmodule\n\nmodule XOR2 (\n\tinput A, B,\n\toutput Y\n);\n\tassign Y = A ^ B;\nendmodule\n\nmodule XOR3 (\n\tinput A, B, C,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C;\nendmodule\n\nmodule XOR4 (\n\tinput A, B, C, D,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D;\nendmodule\n\nmodule XOR8 (\n\tinput A, B, C, D, E, F, G, H,\n\toutput Y\n);\n\tassign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;\nendmodule\n\n// module UJTAG\n\nmodule BIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule BIBUF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PADP,\n\t(* iopad_external_pin *)\n\tinout PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule CLKBIBUF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\tinout PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\n\tassign Y = PAD;\nendmodule\n\nmodule CLKBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule CLKBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\t(* clkbuf_driver *)\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule INBUF (\n\t(* iopad_external_pin *)\n\tinput PAD,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\n\tassign Y = PAD;\nendmodule\n\n(* blackbox *)\nmodule INBUF_DIFF (\n\t(* iopad_external_pin *)\n\tinput PADP,\n\t(* iopad_external_pin *)\n\tinput PADN,\n\toutput Y\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule OUTBUF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = D;\nendmodule\n\n(* blackbox *)\nmodule OUTBUF_DIFF (\n\tinput D,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\nmodule TRIBUFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PAD\n);\n\tparameter IOSTD = \"\";\n\tassign PAD = E ? D : 1'bz;\nendmodule\n\n(* blackbox *)\nmodule TRIBUFF_DIFF (\n\tinput D,\n\tinput E,\n\t(* iopad_external_pin *)\n\toutput PADP,\n\t(* iopad_external_pin *)\n\toutput PADN\n);\n\tparameter IOSTD = \"\";\nendmodule\n\n// module DDR_IN\n// module DDR_OUT\n// module RAM1K18\n// module RAM64x18\n// module MACC\n\n(* blackbox *)\nmodule SYSRESET (\n\t(* iopad_external_pin *)\n\tinput DEVRST_N,\n\toutput POWER_ON_RESET_N);\nendmodule\n\n\n(* blackbox *)\nmodule XTLOSC (\n\t(* iopad_external_pin *)\n\tinput XTL,\n\toutput CLKOUT);\n\tparameter [1:0] MODE = 2'h3;\n\tparameter real FREQUENCY = 20.0;\nendmodule\n\n(* blackbox *)\nmodule RAM1K18 (\n\tinput [13:0] A_ADDR,\n\tinput [2:0] A_BLK,\n\t(* clkbuf_sink *)\n\tinput\t A_CLK,\n\tinput [17:0] A_DIN,\n\toutput [17:0] A_DOUT,\n\tinput [1:0] A_WEN,\n\tinput [2:0] A_WIDTH,\n\tinput\t A_WMODE,\n\tinput\t A_ARST_N,\n\tinput\t A_DOUT_LAT,\n\tinput\t A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_DOUT_CLK,\n\tinput\t A_DOUT_EN,\n\tinput\t A_DOUT_SRST_N,\n\n\tinput [13:0] B_ADDR,\n\tinput [2:0] B_BLK,\n\t(* clkbuf_sink *)\n\tinput\t B_CLK,\n\tinput [17:0] B_DIN,\n\toutput [17:0] B_DOUT,\n\tinput [1:0] B_WEN,\n\tinput [2:0] B_WIDTH,\n\tinput\t B_WMODE,\n\tinput\t B_ARST_N,\n\tinput\t B_DOUT_LAT,\n\tinput\t B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_DOUT_CLK,\n\tinput\t B_DOUT_EN,\n\tinput\t B_DOUT_SRST_N,\n\n\tinput\t A_EN,\n\tinput\t B_EN,\n\tinput\t SII_LOCK,\n\toutput\t BUSY);\nendmodule\n\n(* blackbox *)\nmodule RAM64x18 (\n\tinput [9:0] A_ADDR,\n\tinput [1:0] A_BLK,\n\tinput [2:0] A_WIDTH,\n\toutput [17:0] A_DOUT,\n\tinput\t A_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_DOUT_CLK,\n\tinput\t A_DOUT_EN,\n\tinput\t A_DOUT_LAT,\n\tinput\t A_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t A_ADDR_CLK,\n\tinput\t A_ADDR_EN,\n\tinput\t A_ADDR_LAT,\n\tinput\t A_ADDR_SRST_N,\n\tinput\t A_ADDR_ARST_N,\n\n\tinput [9:0] B_ADDR,\n\tinput [1:0] B_BLK,\n\tinput [2:0] B_WIDTH,\n\toutput [17:0] B_DOUT,\n\tinput\t B_DOUT_ARST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_DOUT_CLK,\n\tinput\t B_DOUT_EN,\n\tinput\t B_DOUT_LAT,\n\tinput\t B_DOUT_SRST_N,\n\t(* clkbuf_sink *)\n\tinput\t B_ADDR_CLK,\n\tinput\t B_ADDR_EN,\n\tinput\t B_ADDR_LAT,\n\tinput\t B_ADDR_SRST_N,\n\tinput\t B_ADDR_ARST_N,\n\n\tinput [9:0] C_ADDR,\n\t(* clkbuf_sink *)\n\tinput\t C_CLK,\n\tinput [17:0] C_DIN,\n\tinput\t C_WEN,\n\tinput [1:0] C_BLK,\n\tinput [2:0] C_WIDTH,\n\n\tinput\t A_EN,\n\tinput\t B_EN,\n\tinput\t C_EN,\n\tinput\t SII_LOCK,\n\toutput\t BUSY);\nendmodule\n",
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  "simcells.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell simulation library.\n *\n * This Verilog library contains simple simulation models for the internal\n * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology\n * mapper (see \"techmap.v\" in this directory) and expected by the \"abc\" pass.\n *\n */\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_BUF_ (A, Y)\n//-\n//- A buffer. This cell type is always optimized away by the opt_clean pass.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 0\n//- 1 | 1\n//-\nmodule \\$_BUF_ (A, Y);\ninput A;\noutput Y;\nassign Y = A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOT_ (A, Y)\n//-\n//- An inverter gate.\n//-\n//- Truth table: A | Y\n//- ---+---\n//- 0 | 1\n//- 1 | 0\n//-\nmodule \\$_NOT_ (A, Y);\ninput A;\noutput Y;\nassign Y = ~A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AND_ (A, B, Y)\n//-\n//- A 2-input AND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_AND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NAND_ (A, B, Y)\n//-\n//- A 2-input NAND gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_NAND_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A & B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OR_ (A, B, Y)\n//-\n//- A 2-input OR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_OR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NOR_ (A, B, Y)\n//-\n//- A 2-input NOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 0\n//-\nmodule \\$_NOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A | B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XOR_ (A, B, Y)\n//-\n//- A 2-input XOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 1\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_XOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A ^ B;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_XNOR_ (A, B, Y)\n//-\n//- A 2-input XNOR gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 0\n//- 1 1 | 1\n//-\nmodule \\$_XNOR_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = ~(A ^ B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ANDNOT_ (A, B, Y)\n//-\n//- A 2-input AND-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 0\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 0\n//-\nmodule \\$_ANDNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A & (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ORNOT_ (A, B, Y)\n//-\n//- A 2-input OR-NOT gate.\n//-\n//- Truth table: A B | Y\n//- -----+---\n//- 0 0 | 1\n//- 0 1 | 0\n//- 1 0 | 1\n//- 1 1 | 1\n//-\nmodule \\$_ORNOT_ (A, B, Y);\ninput A, B;\noutput Y;\nassign Y = A | (~B);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX_ (A, B, S, Y)\n//-\n//- A 2-input MUX gate.\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- a - 0 | a\n//- - b 1 | b\n//-\nmodule \\$_MUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? B : A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_NMUX_ (A, B, S, Y)\n//-\n//- A 2-input inverting MUX gate.\n//-\n//- Truth table: A B S | Y\n//- -------+---\n//- 0 - 0 | 1\n//- 1 - 0 | 0\n//- - 0 1 | 1\n//- - 1 1 | 0\n//-\nmodule \\$_NMUX_ (A, B, S, Y);\ninput A, B, S;\noutput Y;\nassign Y = S ? !B : !A;\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX4_ (A, B, C, D, S, T, Y)\n//-\n//- A 4-input MUX gate.\n//-\n//- Truth table: A B C D S T | Y\n//- -------------+---\n//- a - - - 0 0 | a\n//- - b - - 1 0 | b\n//- - - c - 0 1 | c\n//- - - - d 1 1 | d\n//-\nmodule \\$_MUX4_ (A, B, C, D, S, T, Y);\ninput A, B, C, D, S, T;\noutput Y;\nassign Y = T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y)\n//-\n//- An 8-input MUX gate.\n//-\n//- Truth table: A B C D E F G H S T U | Y\n//- -----------------------+---\n//- a - - - - - - - 0 0 0 | a\n//- - b - - - - - - 1 0 0 | b\n//- - - c - - - - - 0 1 0 | c\n//- - - - d - - - - 1 1 0 | d\n//- - - - - e - - - 0 0 1 | e\n//- - - - - - f - - 1 0 1 | f\n//- - - - - - - g - 0 1 1 | g\n//- - - - - - - - h 1 1 1 | h\n//-\nmodule \\$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);\ninput A, B, C, D, E, F, G, H, S, T, U;\noutput Y;\nassign Y = U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)\n//-\n//- A 16-input MUX gate.\n//-\n//- Truth table: A B C D E F G H I J K L M N O P S T U V | Y\n//- -----------------------------------------+---\n//- a - - - - - - - - - - - - - - - 0 0 0 0 | a\n//- - b - - - - - - - - - - - - - - 1 0 0 0 | b\n//- - - c - - - - - - - - - - - - - 0 1 0 0 | c\n//- - - - d - - - - - - - - - - - - 1 1 0 0 | d\n//- - - - - e - - - - - - - - - - - 0 0 1 0 | e\n//- - - - - - f - - - - - - - - - - 1 0 1 0 | f\n//- - - - - - - g - - - - - - - - - 0 1 1 0 | g\n//- - - - - - - - h - - - - - - - - 1 1 1 0 | h\n//- - - - - - - - - i - - - - - - - 0 0 0 1 | i\n//- - - - - - - - - - j - - - - - - 1 0 0 1 | j\n//- - - - - - - - - - - k - - - - - 0 1 0 1 | k\n//- - - - - - - - - - - - l - - - - 1 1 0 1 | l\n//- - - - - - - - - - - - - m - - - 0 0 1 1 | m\n//- - - - - - - - - - - - - - n - - 1 0 1 1 | n\n//- - - - - - - - - - - - - - - o - 0 1 1 1 | o\n//- - - - - - - - - - - - - - - - p 1 1 1 1 | p\n//-\nmodule \\$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);\ninput A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;\noutput Y;\nassign Y = V ? U ? T ? (S ? P : O) :\n (S ? N : M) :\n T ? (S ? L : K) :\n (S ? J : I) :\n U ? T ? (S ? H : G) :\n (S ? F : E) :\n T ? (S ? D : C) :\n (S ? B : A);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI3_ (A, B, C, Y)\n//-\n//- A 3-input And-Or-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 0\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 0\n//- 1 1 1 | 0\n//-\nmodule \\$_AOI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A & B) | C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI3_ (A, B, C, Y)\n//-\n//- A 3-input Or-And-Invert gate.\n//-\n//- Truth table: A B C | Y\n//- -------+---\n//- 0 0 0 | 1\n//- 0 0 1 | 1\n//- 0 1 0 | 1\n//- 0 1 1 | 0\n//- 1 0 0 | 1\n//- 1 0 1 | 0\n//- 1 1 0 | 1\n//- 1 1 1 | 0\n//-\nmodule \\$_OAI3_ (A, B, C, Y);\ninput A, B, C;\noutput Y;\nassign Y = ~((A | B) & C);\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_AOI4_ (A, B, C, Y)\n//-\n//- A 4-input And-Or-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 0\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 1\n//- 0 1 1 0 | 1\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 1\n//- 1 0 1 0 | 1\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 0\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_AOI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A & B) | (C & D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_OAI4_ (A, B, C, Y)\n//-\n//- A 4-input Or-And-Invert gate.\n//-\n//- Truth table: A B C D | Y\n//- ---------+---\n//- 0 0 0 0 | 1\n//- 0 0 0 1 | 1\n//- 0 0 1 0 | 1\n//- 0 0 1 1 | 1\n//- 0 1 0 0 | 1\n//- 0 1 0 1 | 0\n//- 0 1 1 0 | 0\n//- 0 1 1 1 | 0\n//- 1 0 0 0 | 1\n//- 1 0 0 1 | 0\n//- 1 0 1 0 | 0\n//- 1 0 1 1 | 0\n//- 1 1 0 0 | 1\n//- 1 1 0 1 | 0\n//- 1 1 1 0 | 0\n//- 1 1 1 1 | 0\n//-\nmodule \\$_OAI4_ (A, B, C, D, Y);\ninput A, B, C, D;\noutput Y;\nassign Y = ~((A | B) & (C | D));\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_TBUF_ (A, E, Y)\n//-\n//- A tri-state buffer.\n//-\n//- Truth table: A E | Y\n//- -----+---\n//- a 1 | a\n//- - 0 | z\n//-\nmodule \\$_TBUF_ (A, E, Y);\ninput A, E;\noutput Y;\nassign Y = E ? A : 1'bz;\nendmodule\n\n// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually,\n// instead edit the templates in gen_ff_types.py and rerun it.\n\n// START AUTOGENERATED CELL TYPES\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NN_ (S, R, Q)\n//-\n//- A set-reset latch with negative polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_NP_ (S, R, Q)\n//-\n//- A set-reset latch with negative polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 0 - | 1\n//- - - | q\n//-\nmodule \\$_SR_NP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PN_ (S, R, Q)\n//-\n//- A set-reset latch with positive polarity SET and negative polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 0 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PN_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SR_PP_ (S, R, Q)\n//-\n//- A set-reset latch with positive polarity SET and positive polarity RESET.\n//-\n//- Truth table: S R | Q\n//- -----+---\n//- - 1 | 0\n//- 1 - | 1\n//- - - | q\n//-\nmodule \\$_SR_PP_ (S, R, Q);\ninput S, R;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\nend\nendmodule\n\n`ifdef SIMCELLS_FF\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_FF_ (D, Q)\n//-\n//- A D-type flip-flop that is clocked from the implicit global clock. (This cell\n//- type is usually only used in netlists for formal verification.)\n//-\nmodule \\$_FF_ (D, Q);\ninput D;\noutput reg Q;\nalways @($global_clock) begin\n\tQ <= D;\nend\nendmodule\n`endif\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_N_ (D, C, Q)\n//-\n//- A negative edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d \\ | d\n//- - - | q\n//-\nmodule \\$_DFF_N_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(negedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_P_ (D, C, Q)\n//-\n//- A positive edge D-type flip-flop.\n//-\n//- Truth table: D C | Q\n//- -----+---\n//- d / | d\n//- - - | q\n//-\nmodule \\$_DFF_P_ (D, C, Q);\ninput D, C;\noutput reg Q;\nalways @(posedge C) begin\n\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN_ (D, C, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP_ (D, C, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d \\ 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_NP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN_ (D, C, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 0 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PN_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (!E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP_ (D, C, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity enable.\n//-\n//- Truth table: D C E | Q\n//- -------+---\n//- d / 1 | d\n//- - - - | q\n//-\nmodule \\$_DFFE_PP_ (D, C, E, Q);\ninput D, C, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E) Q <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NN1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_NP1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_DFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PN1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFF_PP1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - - 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_DFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or negedge R) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity reset and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - - 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_DFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C or posedge R) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NN_ (D, C, L, AD, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_NP_ (D, C, L, AD, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d \\ - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_NP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PN_ (D, C, L, AD, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 0 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PN_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFF_PP_ (D, C, L, AD, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load.\n//-\n//- Truth table: D C L AD | Q\n//- ----------+---\n//- - - 1 a | a\n//- d / - - | d\n//- - - - - | q\n//-\nmodule \\$_ALDFF_PP_ (D, C, L, AD, Q);\ninput D, C, L, AD;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNN_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NNP_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPN_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_NPP_ (D, C, L, AD, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d \\ - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_NPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(negedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNN_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PNP_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 0 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PNP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or negedge L) begin\n\tif (L == 0)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPN_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and negative\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 0 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPN_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_ALDFFE_PPP_ (D, C, L, AD, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity async load and positive\n//- polarity clock enable.\n//-\n//- Truth table: D C L AD E | Q\n//- ------------+---\n//- - - 1 a - | a\n//- d / - - 1 | d\n//- - - - - - | q\n//-\nmodule \\$_ALDFFE_PPP_ (D, C, L, AD, E, Q);\ninput D, C, L, AD, E;\noutput reg Q;\nalways @(posedge C or posedge L) begin\n\tif (L == 1)\n\t\tQ <= AD;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNN_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NNP_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPN_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_NPP_ (C, S, R, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- \\ - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_NPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNN_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PNP_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PNP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPN_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPN_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSR_PPP_ (C, S, R, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: C S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- / - - d | d\n//- - - - - | q\n//-\nmodule \\$_DFFSR_PPP_ (C, S, R, D, Q);\ninput C, S, R, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNNP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NNPP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPNP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPN_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_NPPP_ (C, S, R, E, D, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- \\ - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_NPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(negedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNNP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PNPP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 0 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PNPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, negedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPNP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, negative\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 0 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPNP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, negedge R) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPN_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and negative polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 0 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPN_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DFFSRE_PPPP_ (C, S, R, E, D, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity set, positive\n//- polarity reset and positive polarity clock enable.\n//-\n//- Truth table: C S R E D | Q\n//- -----------+---\n//- - - 1 - - | 0\n//- - 1 - - - | 1\n//- / - - 1 d | d\n//- - - - - - | q\n//-\nmodule \\$_DFFSRE_PPPP_ (C, S, R, E, D, Q);\ninput C, S, R, E, D;\noutput reg Q;\nalways @(posedge C, posedge S, posedge R) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n else if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NN1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 0 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP0_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 0\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_NP1_ (D, C, R, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - \\ 1 | 1\n//- d \\ - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_NP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PN1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 0 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PN1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP0_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 0\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP0_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFF_PP1_ (D, C, R, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set.\n//-\n//- Truth table: D C R | Q\n//- -------+---\n//- - / 1 | 1\n//- d / - | d\n//- - - - | q\n//-\nmodule \\$_SDFF_PP1_ (D, C, R, Q);\ninput D, C, R;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 - | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with reset having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with set having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 - | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (R == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NN1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 0 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 0\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP0P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 0\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1N_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 0 | 1\n//- d \\ - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_NP1P_ (D, C, R, E, Q)\n//-\n//- A negative edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - \\ 1 1 | 1\n//- d \\ - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_NP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(negedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PN1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with negative polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 0 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PN1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 0)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 0\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP0P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 0\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP0P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 0;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1N_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and negative\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 0 | 1\n//- d / - 0 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1N_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 0) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_SDFFCE_PP1P_ (D, C, R, E, Q)\n//-\n//- A positive edge D-type flip-flop with positive polarity synchronous set and positive\n//- polarity clock enable (with clock enable having priority).\n//-\n//- Truth table: D C R E | Q\n//- ---------+---\n//- - / 1 1 | 1\n//- d / - 1 | d\n//- - - - - | q\n//-\nmodule \\$_SDFFCE_PP1P_ (D, C, R, E, Q);\ninput D, C, R, E;\noutput reg Q;\nalways @(posedge C) begin\n\tif (E == 1) begin\n\t\tif (R == 1)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_N_ (E, D, Q)\n//-\n//- A negative enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 0 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_N_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_P_ (E, D, Q)\n//-\n//- A positive enable D-type latch.\n//-\n//- Truth table: E D | Q\n//- -----+---\n//- 1 d | d\n//- - - | q\n//-\nmodule \\$_DLATCH_P_ (E, D, Q);\ninput E, D;\noutput reg Q;\nalways @* begin\n\tif (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN0_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NN1_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP0_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_NP1_ (E, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 0 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_NP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN0_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PN1_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 0 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PN1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP0_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity reset.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 0\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP0_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 0;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCH_PP1_ (E, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set.\n//-\n//- Truth table: E R D | Q\n//- -------+---\n//- - 1 - | 1\n//- 1 - d | d\n//- - - - | q\n//-\nmodule \\$_DLATCH_PP1_ (E, R, D, Q);\ninput E, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n Q <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNN_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NNP_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPN_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_NPP_ (E, S, R, D, Q)\n//-\n//- A negative enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 0 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_NPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 0)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNN_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PNP_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with negative polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 0 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PNP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 0)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPN_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set and negative\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 0 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPN_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 0)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $_DLATCHSR_PPP_ (E, S, R, D, Q)\n//-\n//- A positive enable D-type latch with positive polarity set and positive\n//- polarity reset.\n//-\n//- Truth table: E S R D | Q\n//- ---------+---\n//- - - 1 - | 0\n//- - 1 - - | 1\n//- 1 - - d | d\n//- - - - - | q\n//-\nmodule \\$_DLATCHSR_PPP_ (E, S, R, D, Q);\ninput E, S, R, D;\noutput reg Q;\nalways @* begin\n\tif (R == 1)\n\t\tQ <= 0;\n\telse if (S == 1)\n\t\tQ <= 1;\n\telse if (E == 1)\n\t\tQ <= D;\nend\nendmodule\n",
336
- "simlib.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The Simulation Library.\n *\n * This Verilog library contains simple simulation models for the internal\n * cells ($not, ...) generated by the frontends and used in most passes.\n *\n * This library can be used to verify the internal netlists as generated\n * by the different frontends and passes.\n *\n * Note that memory can only be simulated when all $memrd and $memwr cells\n * have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n * pass is doing).\n *\n */\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $not (A, Y)\n//-\n//- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pos (A, Y)\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $neg (A, Y)\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $and (A, B, Y)\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $or (A, B, Y)\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xor (A, B, Y)\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xnor (A, B, Y)\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_and (A, Y)\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_or (A, Y)\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xor (A, Y)\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xnor (A, Y)\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_bool (A, Y)\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P; // Propagate\ninput [WIDTH-1:0] G; // Generate\ninput CI; // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $alu (A, B, CI, BI, X, Y, CO)\n//-\n//- Arithmetic logic unit.\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex\n//- cells into this $alu cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A; // Input operand\ninput [B_WIDTH-1:0] B; // Input operand\noutput [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,\n // used in combination with\n // reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y; // Sum\n\ninput CI; // Carry-in (set for $sub)\ninput BI; // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO; // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput reg [Y_WIDTH-1:0] Y;\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $div (A, B, Y)\n//-\n//- Division with truncated result (rounded towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mod (A, B, Y)\n//-\n//- Modulo/remainder of division with truncated result (rounded towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $divfloor (A, B, Y)\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $modfloor (A, B, Y)\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <- MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
340
+ "simlib.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The Simulation Library.\n *\n * This Verilog library contains simple simulation models for the internal\n * cells ($not, ...) generated by the frontends and used in most passes.\n *\n * This library can be used to verify the internal netlists as generated\n * by the different frontends and passes.\n *\n * Note that memory can only be simulated when all $memrd and $memwr cells\n * have been merged to stand-alone $mem cells (this is what the \"memory_collect\"\n * pass is doing).\n *\n */\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $not (A, Y)\n//-\n//- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.\n//-\nmodule \\$not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~A;\n\tend\nendgenerate\n\nendmodule\n\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $pos (A, Y)\n//-\n//- A buffer. This corresponds to the Verilog unary prefix '+' operator.\n//-\nmodule \\$pos (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $neg (A, Y)\n//-\n//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.\n//-\nmodule \\$neg (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = -$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = -A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $and (A, B, Y)\n//-\n//- A bit-wise AND. This corresponds to the Verilog '&' operator.\n//-\nmodule \\$and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) & $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A & B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $or (A, B, Y)\n//-\n//- A bit-wise OR. This corresponds to the Verilog '|' operator.\n//-\nmodule \\$or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) | $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A | B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xor (A, B, Y)\n//-\n//- A bit-wise XOR. This corresponds to the Verilog '^' operator.\n//-\nmodule \\$xor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $xnor (A, B, Y)\n//-\n//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.\n//-\nmodule \\$xnor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ~^ $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A ~^ B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_and (A, Y)\n//-\n//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.\n//-\nmodule \\$reduce_and (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = &$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = &A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_or (A, Y)\n//-\n//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.\n//-\nmodule \\$reduce_or (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = |$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = |A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xor (A, Y)\n//-\n//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.\n//-\nmodule \\$reduce_xor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_xnor (A, Y)\n//-\n//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.\n//-\nmodule \\$reduce_xnor (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = ~^$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = ~^A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $reduce_bool (A, Y)\n//-\n//- An OR reduction. This cell type is used instead of $reduce_or when a signal is\n//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.\n//-\nmodule \\$reduce_bool (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !(!$signed(A));\n\tend else begin:BLOCK2\n\t\tassign Y = !(!A);\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) << B;\n\tend else begin:BLOCK2\n\t\tassign Y = A << B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sshl (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <<< B;\n\tend else begin:BLOCK2\n\t\tassign Y = A <<< B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sshr (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >>> B;\n\tend else begin:BLOCK2\n\t\tassign Y = A >>> B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shift (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tif (B_SIGNED) begin:BLOCK2\n\t\t\tassign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;\n\t\tend else begin:BLOCK3\n\t\t\tassign Y = $signed(A) >> B;\n\t\tend\n\tend else begin:BLOCK4\n\t\tif (B_SIGNED) begin:BLOCK5\n\t\t\tassign Y = $signed(B) < 0 ? A << -B : A >> B;\n\t\tend else begin:BLOCK6\n\t\t\tassign Y = A >> B;\n\t\tend\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$shiftx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (Y_WIDTH > 0)\n\t\tif (B_SIGNED) begin:BLOCK1\n\t\t\tassign Y = A[$signed(B) +: Y_WIDTH];\n\t\tend else begin:BLOCK2\n\t\t\tassign Y = A[B +: Y_WIDTH];\n\t\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fa (A, B, C, X, Y);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] A, B, C;\noutput [WIDTH-1:0] X, Y;\n\nwire [WIDTH-1:0] t1, t2, t3;\n\nassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\nassign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $lcu (P, G, CI, CO)\n//-\n//- Lookahead carry unit\n//- A building block dedicated to fast computation of carry-bits used in binary\n//- arithmetic operations. By replacing the ripple carry structure used in full-adder\n//- blocks, the more significant bits of the sum can be expected to be computed more\n//- quickly.\n//- Typically created during `techmap` of $alu cells (see the \"_90_alu\" rule in\n//- +/techmap.v).\nmodule \\$lcu (P, G, CI, CO);\n\nparameter WIDTH = 1;\n\ninput [WIDTH-1:0] P; // Propagate\ninput [WIDTH-1:0] G; // Generate\ninput CI; // Carry-in\n\noutput reg [WIDTH-1:0] CO; // Carry-out\n\ninteger i;\nalways @* begin\n\tCO = 'bx;\n\tif (^{P, G, CI} !== 1'bx) begin\n\t\tCO[0] = G[0] || (P[0] && CI);\n\t\tfor (i = 1; i < WIDTH; i = i+1)\n\t\t\tCO[i] = G[i] || (P[i] && CO[i-1]);\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $alu (A, B, CI, BI, X, Y, CO)\n//-\n//- Arithmetic logic unit.\n//- A building block supporting both binary addition/subtraction operations, and\n//- indirectly, comparison operations.\n//- Typically created by the `alumacc` pass, which transforms:\n//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex\n//- cells into this $alu cell.\n//-\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 1;\nparameter B_WIDTH = 1;\nparameter Y_WIDTH = 1;\n\ninput [A_WIDTH-1:0] A; // Input operand\ninput [B_WIDTH-1:0] B; // Input operand\noutput [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,\n // used in combination with\n // reduction-AND for $eq/$ne ops)\noutput [Y_WIDTH-1:0] Y; // Sum\n\ninput CI; // Carry-in (set for $sub)\ninput BI; // Invert-B (set for $sub)\noutput [Y_WIDTH-1:0] CO; // Carry-out\n\nwire [Y_WIDTH-1:0] AA, BB;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);\n\tend else begin:BLOCK2\n\t\tassign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);\n\tend\nendgenerate\n\n// this is 'x' if Y and CO should be all 'x', and '0' otherwise\nwire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};\n\nassign X = AA ^ BB;\n// Full adder\nassign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};\n\nfunction get_carry;\n\tinput a, b, c;\n\tget_carry = (a&b) | (a&c) | (b&c);\nendfunction\n\ngenvar i;\ngenerate\n\tassign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;\n\tfor (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3\n\t\tassign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$lt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) < $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A < B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$le (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) <= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A <= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$eq (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) == $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A == B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$ne (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) != $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A != B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$eqx (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) === $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A === B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$nex (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) !== $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A !== B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$ge (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) >= $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A >= B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$gt (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) > $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A > B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$add (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) + $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A + B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sub (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) - $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A - B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mul (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) * $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A * B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $macc (A, B, Y)\n//-\n//- Multiply and accumulate.\n//- A building block for summing any number of negated and unnegated signals\n//- and arithmetic products of pairs of signals. Cell port A concatenates pairs\n//- of signals to be multiplied together. When the second signal in a pair is zero\n//- length, a constant 1 is used instead as the second factor. Cell port B\n//- concatenates 1-bit-wide signals to also be summed, such as \"carry in\" in adders.\n//- Typically created by the `alumacc` pass, which transforms $add and $mul\n//- into $macc cells.\nmodule \\$macc (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n// CONFIG determines the layout of A, as explained below\nparameter CONFIG = 4'b0000;\nparameter CONFIG_WIDTH = 4;\n\n// In the terms used for this cell, there's mixed meanings for the term \"port\". To disambiguate:\n// A cell port is for example the A input (it is constructed in C++ as cell->setPort(ID::A, ...))\n// Multiplier ports are pairs of multiplier inputs (\"factors\").\n// If the second signal in such a pair is zero length, no multiplication is necessary, and the first signal is just added to the sum.\ninput [A_WIDTH-1:0] A; // Cell port A is the concatenation of all arithmetic ports\ninput [B_WIDTH-1:0] B; // Cell port B is the concatenation of single-bit unsigned signals to be also added to the sum\noutput reg [Y_WIDTH-1:0] Y; // Output sum\n\n// Xilinx XSIM does not like $clog2() below..\nfunction integer my_clog2;\n\tinput integer v;\n\tbegin\n\t\tif (v > 0)\n\t\t\tv = v - 1;\n\t\tmy_clog2 = 0;\n\t\twhile (v) begin\n\t\t\tv = v >> 1;\n\t\t\tmy_clog2 = my_clog2 + 1;\n\t\tend\n\tend\nendfunction\n\n// Bits that a factor's length field in CONFIG per factor in cell port A\nlocalparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;\n// Number of multiplier ports\nlocalparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);\n// Minium bit width of an induction variable to iterate over all bits of cell port A\nlocalparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;\n\n// In this pseudocode, u(foo) means an unsigned int that's foo bits long.\n// The CONFIG parameter carries the following information:\n//\tstruct CONFIG {\n//\t\tu4 num_bits;\n//\t\tstruct port_field {\n//\t\t\tbool is_signed;\n//\t\t\tbool is_subtract;\n//\t\t\tu(num_bits) factor1_len;\n//\t\t\tu(num_bits) factor2_len;\n//\t\t}[num_ports];\n//\t};\n\n// The A cell port carries the following information:\n//\tstruct A {\n//\t\tu(CONFIG.port_field[0].factor1_len) port0factor1;\n//\t\tu(CONFIG.port_field[0].factor2_len) port0factor2;\n//\t\tu(CONFIG.port_field[1].factor1_len) port1factor1;\n//\t\tu(CONFIG.port_field[1].factor2_len) port1factor2;\n//\t\t...\n//\t};\n// and log(sizeof(A)) is num_abits.\n// No factor1 may have a zero length.\n// A factor2 having a zero length implies factor2 is replaced with a constant 1.\n\n// Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.\n// Finally, we have:\n// Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...\n// * B[0] + B[1] + ...\n\nfunction [2*num_ports*num_abits-1:0] get_port_offsets;\n\tinput [CONFIG_WIDTH-1:0] cfg;\n\tinteger i, cursor;\n\tbegin\n\t\tcursor = 0;\n\t\tget_port_offsets = 0;\n\t\tfor (i = 0; i < num_ports; i = i+1) begin\n\t\t\tget_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];\n\t\t\tget_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;\n\t\t\tcursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];\n\t\tend\n\tend\nendfunction\n\nlocalparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);\n\n`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])\n`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])\n`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])\n`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])\n`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])\n`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])\n\ninteger i, j;\nreg [Y_WIDTH-1:0] tmp_a, tmp_b;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < num_ports; i = i+1)\n\tbegin\n\t\ttmp_a = 0;\n\t\ttmp_b = 0;\n\n\t\tfor (j = 0; j < `PORT_SIZE_A; j = j+1)\n\t\t\ttmp_a[j] = A[`PORT_OFFSET_A + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)\n\t\t\tfor (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_a[j] = tmp_a[`PORT_SIZE_A-1];\n\n\t\tfor (j = 0; j < `PORT_SIZE_B; j = j+1)\n\t\t\ttmp_b[j] = A[`PORT_OFFSET_B + j];\n\n\t\tif (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)\n\t\t\tfor (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)\n\t\t\t\ttmp_b[j] = tmp_b[`PORT_SIZE_B-1];\n\n\t\tif (`PORT_SIZE_B > 0)\n\t\t\ttmp_a = tmp_a * tmp_b;\n\n\t\tif (`PORT_DO_SUBTRACT)\n\t\t\tY = Y - tmp_a;\n\t\telse\n\t\t\tY = Y + tmp_a;\n\tend\n\tfor (i = 0; i < B_WIDTH; i = i+1) begin\n\t\tY = Y + B[i];\n\tend\nend\n\n`undef PORT_IS_SIGNED\n`undef PORT_DO_SUBTRACT\n`undef PORT_SIZE_A\n`undef PORT_SIZE_B\n`undef PORT_OFFSET_A\n`undef PORT_OFFSET_B\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $div (A, B, Y)\n//-\n//- Division with truncated result (rounded towards 0).\n//-\nmodule \\$div (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) / $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $mod (A, B, Y)\n//-\n//- Modulo/remainder of division with truncated result (rounded towards 0).\n//-\n//- Invariant: $div(A, B) * B + $mod(A, B) == A\n//-\nmodule \\$mod (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) % $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $divfloor (A, B, Y)\n//-\n//- Division with floored result (rounded towards negative infinity).\n//-\nmodule \\$divfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH =\n\t\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH:0] A_buf, B_buf, N_buf;\n\t\tassign A_buf = $signed(A);\n\t\tassign B_buf = $signed(B);\n\t\tassign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));\n\t\tassign Y = $signed(N_buf) / $signed(B_buf);\n\tend else begin:BLOCK2\n\t\tassign Y = A / B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\n// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|\n//-\n//- $modfloor (A, B, Y)\n//-\n//- Modulo/remainder of division with floored result (rounded towards negative infinity).\n//-\n//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A\n//-\nmodule \\$modfloor (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tlocalparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\t\twire [WIDTH-1:0] B_buf, Y_trunc;\n\t\tassign B_buf = $signed(B);\n\t\tassign Y_trunc = $signed(A) % $signed(B);\n\t\t// flooring mod is the same as truncating mod for positive division results (A and B have\n\t\t// the same sign), as well as when there's no remainder.\n\t\t// For all other cases, they behave as `floor - trunc = B`\n\t\tassign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);\n\tend else begin:BLOCK2\n\t\t// no difference between truncating and flooring for unsigned\n\t\tassign Y = A % B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOPOW\n\nmodule \\$pow (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) ** $signed(B);\n\tend else if (A_SIGNED) begin:BLOCK2\n\t\tassign Y = $signed(A) ** B;\n\tend else if (B_SIGNED) begin:BLOCK3\n\t\tassign Y = A ** $signed(B);\n\tend else begin:BLOCK4\n\t\tassign Y = A ** B;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$logic_not (A, Y);\n\nparameter A_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED) begin:BLOCK1\n\t\tassign Y = !$signed(A);\n\tend else begin:BLOCK2\n\t\tassign Y = !A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$logic_and (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) && $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A && B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$logic_or (A, B, Y);\n\nparameter A_SIGNED = 0;\nparameter B_SIGNED = 0;\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [Y_WIDTH-1:0] Y;\n\ngenerate\n\tif (A_SIGNED && B_SIGNED) begin:BLOCK1\n\t\tassign Y = $signed(A) || $signed(B);\n\tend else begin:BLOCK2\n\t\tassign Y = A || B;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$slice (A, Y);\n\nparameter OFFSET = 0;\nparameter A_WIDTH = 0;\nparameter Y_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\noutput [Y_WIDTH-1:0] Y;\n\nassign Y = A >> OFFSET;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$concat (A, B, Y);\n\nparameter A_WIDTH = 0;\nparameter B_WIDTH = 0;\n\ninput [A_WIDTH-1:0] A;\ninput [B_WIDTH-1:0] B;\noutput [A_WIDTH+B_WIDTH-1:0] Y;\n\nassign Y = {B, A};\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput S;\noutput [WIDTH-1:0] Y;\n\nassign Y = S ? B : A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bmux (A, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [(WIDTH << S_WIDTH)-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\nwire [WIDTH-1:0] bm0_out, bm1_out;\n\ngenerate\n\tif (S_WIDTH > 1) begin:muxlogic\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));\n\t\t\\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));\n\t\tassign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;\n\tend else if (S_WIDTH == 1) begin:simple\n\t\tassign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];\n\tend else begin:passthru\n\t\tassign Y = A;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$pmux (A, B, S, Y);\n\nparameter WIDTH = 0;\nparameter S_WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH*S_WIDTH-1:0] B;\ninput [S_WIDTH-1:0] S;\noutput reg [WIDTH-1:0] Y;\n\ninteger i;\nreg found_active_sel_bit;\n\nalways @* begin\n\tY = A;\n\tfound_active_sel_bit = 0;\n\tfor (i = 0; i < S_WIDTH; i = i+1)\n\t\tcase (S[i])\n\t\t\t1'b1: begin\n\t\t\t\tY = found_active_sel_bit ? 'bx : B >> (WIDTH*i);\n\t\t\t\tfound_active_sel_bit = 1;\n\t\t\tend\n\t\t\t1'b0: ;\n\t\t\t1'bx: begin\n\t\t\t\tY = 'bx;\n\t\t\t\tfound_active_sel_bit = 'bx;\n\t\t\tend\n\t\tendcase\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$demux (A, S, Y);\n\nparameter WIDTH = 1;\nparameter S_WIDTH = 1;\n\ninput [WIDTH-1:0] A;\ninput [S_WIDTH-1:0] S;\noutput [(WIDTH << S_WIDTH)-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices\n\t\tassign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOLUT\n\nmodule \\$lut (A, Y);\n\nparameter WIDTH = 0;\nparameter LUT = 0;\n\ninput [WIDTH-1:0] A;\noutput Y;\n\n\\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$sop (A, Y);\n\nparameter WIDTH = 0;\nparameter DEPTH = 0;\nparameter TABLE = 0;\n\ninput [WIDTH-1:0] A;\noutput reg Y;\n\ninteger i, j;\nreg match;\n\nalways @* begin\n\tY = 0;\n\tfor (i = 0; i < DEPTH; i=i+1) begin\n\t\tmatch = 1;\n\t\tfor (j = 0; j < WIDTH; j=j+1) begin\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;\n\t\t\tif (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;\n\t\tend\n\t\tif (match) Y = 1;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$tribuf (A, EN, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput EN;\noutput [WIDTH-1:0] Y;\n\nassign Y = EN ? A : 'bz;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify2 (EN, SRC, DST);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\tif (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specify3 (EN, SRC, DST, DAT);\n\nparameter FULL = 0;\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter EDGE_EN = 0;\nparameter EDGE_POL = 0;\n\nparameter SRC_DST_PEN = 0;\nparameter SRC_DST_POL = 0;\n\nparameter DAT_DST_PEN = 0;\nparameter DAT_DST_POL = 0;\n\nparameter T_RISE_MIN = 0;\nparameter T_RISE_TYP = 0;\nparameter T_RISE_MAX = 0;\n\nparameter T_FALL_MIN = 0;\nparameter T_FALL_TYP = 0;\nparameter T_FALL_MAX = 0;\n\ninput EN;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST, DAT;\n\nlocalparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;\nlocalparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;\nlocalparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// DD=0\n\n\tif (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=1\n\n\tif (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\t// DD=2\n\n\tif (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\n\tif (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\n\tif (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$specrule (EN_SRC, EN_DST, SRC, DST);\n\nparameter TYPE = \"\";\nparameter T_LIMIT = 0;\nparameter T_LIMIT2 = 0;\n\nparameter SRC_WIDTH = 1;\nparameter DST_WIDTH = 1;\n\nparameter SRC_PEN = 0;\nparameter SRC_POL = 0;\n\nparameter DST_PEN = 0;\nparameter DST_POL = 0;\n\ninput EN_SRC, EN_DST;\ninput [SRC_WIDTH-1:0] SRC;\ninput [DST_WIDTH-1:0] DST;\n\n`ifdef SIMLIB_SPECIFY\nspecify\n\t// TBD\nendspecify\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bweqx (A, B, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = A[i] === B[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$bwmux (A, B, S, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A, B;\ninput [WIDTH-1:0] S;\noutput [WIDTH-1:0] Y;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i + 1) begin:slices\n\t\tassign Y[i] = S[i] ? B[i] : A[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assert (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assertion %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$assume (A, EN);\n\ninput A, EN;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'b1 && EN === 1'b1) begin\n\t\t$display(\"Assumption %m failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$live (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$fair (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$cover (A, EN);\n\ninput A, EN;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$initstate (Y);\n\noutput reg Y = 1;\nreg [3:0] cnt = 1;\nreg trig = 0;\n\ninitial trig <= 1;\n\nalways @(cnt, trig) begin\n\tY <= |cnt;\n\tcnt <= cnt + |cnt;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$anyseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\nmodule \\$anyinit (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\ninitial Q <= 'bx;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n`endif\n// --------------------------------------------------------\n\nmodule \\$allconst (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$allseq (Y);\n\nparameter WIDTH = 0;\n\noutput [WIDTH-1:0] Y;\n\nassign Y = 'bx;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$equiv (A, B, Y);\n\ninput A, B;\noutput Y;\n\nassign Y = (A !== 1'bx && A !== B) ? 1'bx : A;\n\n`ifndef SIMLIB_NOCHECKS\nalways @* begin\n\tif (A !== 1'bx && A !== B) begin\n\t\t$display(\"Equivalence failed!\");\n\t\t$stop;\n\tend\nend\n`endif\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$print (EN, TRG, ARGS);\n\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$check (A, EN, TRG, ARGS);\n\nparameter FLAVOR = \"\";\nparameter PRIORITY = 0;\n\nparameter FORMAT = \"\";\nparameter ARGS_WIDTH = 0;\n\nparameter TRG_ENABLE = 1;\nparameter TRG_WIDTH = 0;\nparameter TRG_POLARITY = 0;\n\ninput A;\ninput EN;\ninput [TRG_WIDTH-1:0] TRG;\ninput [ARGS_WIDTH-1:0] ARGS;\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$sr (SET, CLR, Q);\n\nparameter WIDTH = 0;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput [WIDTH-1:0] SET, CLR;\noutput reg [WIDTH-1:0] Q;\n\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n`ifdef SIMLIB_FF\n`ifndef SIMLIB_GLOBAL_CLOCK\n`define SIMLIB_GLOBAL_CLOCK $global_clk\n`endif\n\nmodule \\$ff (D, Q);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @(`SIMLIB_GLOBAL_CLOCK) begin\n\tQ <= D;\nend\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$dff (CLK, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffe (CLK, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) Q <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dffsr (CLK, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput CLK;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dffsre (CLK, SET, CLR, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\n\ninput CLK, EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] <= 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] <= 1;\n\t\t\telse if (EN == EN_POLARITY)\n\t\t\t\tQ[i] <= D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$adff (CLK, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldff (CLK, ALOAD, AD, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD;\ninput [WIDTH-1:0] AD;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdff (CLK, SRST, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adffe (CLK, ARST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput CLK, ARST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst)\n\t\tQ <= ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$aldffe (CLK, ALOAD, AD, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter ALOAD_POLARITY = 1'b1;\n\ninput CLK, ALOAD, EN;\ninput [WIDTH-1:0] D;\ninput [WIDTH-1:0] AD;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_aload = ALOAD == ALOAD_POLARITY;\n\nalways @(posedge pos_clk, posedge pos_aload) begin\n\tif (pos_aload)\n\t\tQ <= AD;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffe (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (pos_srst)\n\t\tQ <= SRST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ <= D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$sdffce (CLK, SRST, EN, D, Q);\n\nparameter WIDTH = 0;\nparameter CLK_POLARITY = 1'b1;\nparameter EN_POLARITY = 1'b1;\nparameter SRST_POLARITY = 1'b1;\nparameter SRST_VALUE = 0;\n\ninput CLK, SRST, EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_srst = SRST == SRST_POLARITY;\n\nalways @(posedge pos_clk) begin\n\tif (EN == EN_POLARITY) begin\n\t\tif (pos_srst)\n\t\t\tQ <= SRST_VALUE;\n\t\telse\n\t\t\tQ <= D;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$dlatch (EN, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$adlatch (EN, ARST, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\nparameter ARST_VALUE = 0;\n\ninput EN, ARST;\ninput [WIDTH-1:0] D;\noutput reg [WIDTH-1:0] Q;\n\nalways @* begin\n\tif (ARST == ARST_POLARITY)\n\t\tQ = ARST_VALUE;\n\telse if (EN == EN_POLARITY)\n\t\tQ = D;\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOSR\n\nmodule \\$dlatchsr (EN, SET, CLR, D, Q);\n\nparameter WIDTH = 0;\nparameter EN_POLARITY = 1'b1;\nparameter SET_POLARITY = 1'b1;\nparameter CLR_POLARITY = 1'b1;\n\ninput EN;\ninput [WIDTH-1:0] SET, CLR, D;\noutput reg [WIDTH-1:0] Q;\n\nwire pos_en = EN == EN_POLARITY;\nwire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;\nwire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;\n\ngenvar i;\ngenerate\n\tfor (i = 0; i < WIDTH; i = i+1) begin:bitslices\n\t\talways @*\n\t\t\tif (pos_clr[i])\n\t\t\t\tQ[i] = 0;\n\t\t\telse if (pos_set[i])\n\t\t\t\tQ[i] = 1;\n\t\t\telse if (pos_en)\n\t\t\t\tQ[i] = D[i];\n\tend\nendgenerate\n\nendmodule\n\n`endif\n// --------------------------------------------------------\n\nmodule \\$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);\n\nparameter NAME = \"\";\n\nparameter CLK_POLARITY = 1'b1;\nparameter ARST_POLARITY = 1'b1;\n\nparameter CTRL_IN_WIDTH = 1;\nparameter CTRL_OUT_WIDTH = 1;\n\nparameter STATE_BITS = 1;\nparameter STATE_NUM = 1;\nparameter STATE_NUM_LOG2 = 1;\nparameter STATE_RST = 0;\nparameter STATE_TABLE = 1'b0;\n\nparameter TRANS_NUM = 1;\nparameter TRANS_TABLE = 4'b0x0x;\n\ninput CLK, ARST;\ninput [CTRL_IN_WIDTH-1:0] CTRL_IN;\noutput reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;\n\nwire pos_clk = CLK == CLK_POLARITY;\nwire pos_arst = ARST == ARST_POLARITY;\n\nreg [STATE_BITS-1:0] state;\nreg [STATE_BITS-1:0] state_tmp;\nreg [STATE_BITS-1:0] next_state;\n\nreg [STATE_BITS-1:0] tr_state_in;\nreg [STATE_BITS-1:0] tr_state_out;\nreg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;\nreg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;\n\ninteger i;\n\ntask tr_fetch;\n\tinput [31:0] tr_num;\n\treg [31:0] tr_pos;\n\treg [STATE_NUM_LOG2-1:0] state_num;\n\tbegin\n\t\ttr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;\n\t\ttr_ctrl_out = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_OUT_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_out = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\t\ttr_ctrl_in = TRANS_TABLE >> tr_pos;\n\t\ttr_pos = tr_pos + CTRL_IN_WIDTH;\n\t\tstate_num = TRANS_TABLE >> tr_pos;\n\t\ttr_state_in = STATE_TABLE >> (STATE_BITS*state_num);\n\t\ttr_pos = tr_pos + STATE_NUM_LOG2;\n\tend\nendtask\n\nalways @(posedge pos_clk, posedge pos_arst) begin\n\tif (pos_arst) begin\n\t\tstate_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend else begin\n\t\tstate_tmp = next_state;\n\t\tfor (i = 0; i < STATE_BITS; i = i+1)\n\t\t\tif (state_tmp[i] === 1'bz)\n\t\t\t\tstate_tmp[i] = 0;\n\t\tstate <= state_tmp;\n\tend\nend\n\nalways @(state, CTRL_IN) begin\n\tnext_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];\n\tCTRL_OUT <= 'bx;\n\t// $display(\"---\");\n\t// $display(\"Q: %b %b\", state, CTRL_IN);\n\tfor (i = 0; i < TRANS_NUM; i = i+1) begin\n\t\ttr_fetch(i);\n\t\t// $display(\"T: %b %b -> %b %b [%d]\", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);\n\t\tcasez ({state, CTRL_IN})\n\t\t\t{tr_state_in, tr_ctrl_in}: begin\n\t\t\t\t// $display(\"-> %b %b <- MATCH\", state, CTRL_IN);\n\t\t\t\t{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};\n\t\t\tend\n\t\tendcase\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n`ifndef SIMLIB_NOMEM\n\nmodule \\$memrd (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENT = 0;\n\ninput CLK, EN;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter TRANSPARENCY_MASK = 0;\nparameter COLLISION_X_MASK = 0;\nparameter ARST_VALUE = 0;\nparameter SRST_VALUE = 0;\nparameter INIT_VALUE = 0;\nparameter CE_OVER_SRST = 0;\n\ninput CLK, EN, ARST, SRST;\ninput [ABITS-1:0] ADDR;\noutput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memrd_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$memwr (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PRIORITY = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\nmodule \\$memwr_v2 (CLK, EN, ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\n\nparameter CLK_ENABLE = 0;\nparameter CLK_POLARITY = 0;\nparameter PORTID = 0;\nparameter PRIORITY_MASK = 0;\n\ninput CLK;\ninput [WIDTH-1:0] EN;\ninput [ABITS-1:0] ADDR;\ninput [WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $memwr_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit (ADDR, DATA);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$meminit_v2 (ADDR, DATA, EN);\n\nparameter MEMID = \"\";\nparameter ABITS = 8;\nparameter WIDTH = 8;\nparameter WORDS = 1;\n\nparameter PRIORITY = 0;\n\ninput [ABITS-1:0] ADDR;\ninput [WORDS*WIDTH-1:0] DATA;\ninput [WIDTH-1:0] EN;\n\ninitial begin\n\tif (MEMID != \"\") begin\n\t\t$display(\"ERROR: Found non-simulatable instance of $meminit_v2!\");\n\t\t$finish;\n\tend\nend\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENT = 1'b1;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\nend\n\nalways @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Transparent read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\nmodule \\$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);\n\nparameter MEMID = \"\";\nparameter signed SIZE = 4;\nparameter signed OFFSET = 0;\nparameter signed ABITS = 2;\nparameter signed WIDTH = 8;\nparameter signed INIT = 1'bx;\n\nparameter signed RD_PORTS = 1;\nparameter RD_CLK_ENABLE = 1'b1;\nparameter RD_CLK_POLARITY = 1'b1;\nparameter RD_TRANSPARENCY_MASK = 1'b0;\nparameter RD_COLLISION_X_MASK = 1'b0;\nparameter RD_WIDE_CONTINUATION = 1'b0;\nparameter RD_CE_OVER_SRST = 1'b0;\nparameter RD_ARST_VALUE = 1'b0;\nparameter RD_SRST_VALUE = 1'b0;\nparameter RD_INIT_VALUE = 1'b0;\n\nparameter signed WR_PORTS = 1;\nparameter WR_CLK_ENABLE = 1'b1;\nparameter WR_CLK_POLARITY = 1'b1;\nparameter WR_PRIORITY_MASK = 1'b0;\nparameter WR_WIDE_CONTINUATION = 1'b0;\n\ninput [RD_PORTS-1:0] RD_CLK;\ninput [RD_PORTS-1:0] RD_EN;\ninput [RD_PORTS-1:0] RD_ARST;\ninput [RD_PORTS-1:0] RD_SRST;\ninput [RD_PORTS*ABITS-1:0] RD_ADDR;\noutput reg [RD_PORTS*WIDTH-1:0] RD_DATA;\n\ninput [WR_PORTS-1:0] WR_CLK;\ninput [WR_PORTS*WIDTH-1:0] WR_EN;\ninput [WR_PORTS*ABITS-1:0] WR_ADDR;\ninput [WR_PORTS*WIDTH-1:0] WR_DATA;\n\nreg [WIDTH-1:0] memory [SIZE-1:0];\n\ninteger i, j, k;\nreg [WR_PORTS-1:0] LAST_WR_CLK;\nreg [RD_PORTS-1:0] LAST_RD_CLK;\n\nfunction port_active;\n\tinput clk_enable;\n\tinput clk_polarity;\n\tinput last_clk;\n\tinput this_clk;\n\tbegin\n\t\tcasez ({clk_enable, clk_polarity, last_clk, this_clk})\n\t\t\t4'b0???: port_active = 1;\n\t\t\t4'b1101: port_active = 1;\n\t\t\t4'b1010: port_active = 1;\n\t\t\tdefault: port_active = 0;\n\t\tendcase\n\tend\nendfunction\n\ninitial begin\n\tfor (i = 0; i < SIZE; i = i+1)\n\t\tmemory[i] = INIT >>> (i*WIDTH);\n\tRD_DATA = RD_INIT_VALUE;\nend\n\nalways @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin\n`ifdef SIMLIB_MEMDELAY\n\t#`SIMLIB_MEMDELAY;\n`endif\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin\n\t\t\t// $display(\"Read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\n\t\t\tfor (j = 0; j < WR_PORTS; j = j+1) begin\n\t\t\t\tif (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];\n\t\t\t\tif (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])\n\t\t\t\t\tfor (k = 0; k < WIDTH; k = k+1)\n\t\t\t\t\t\tif (WR_EN[j*WIDTH+k])\n\t\t\t\t\t\t\tRD_DATA[i*WIDTH+k] <= 1'bx;\n\t\t\tend\n\t\tend\n\tend\n\n\tfor (i = 0; i < WR_PORTS; i = i+1) begin\n\t\tif (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))\n\t\t\tfor (j = 0; j < WIDTH; j = j+1)\n\t\t\t\tif (WR_EN[i*WIDTH+j]) begin\n\t\t\t\t\t// $display(\"Write to %s: addr=%b data=%b\", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);\n\t\t\t\t\tmemory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];\n\t\t\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (!RD_CLK_ENABLE[i]) begin\n\t\t\t// $display(\"Combinatorial read from %s: addr=%b data=%b\", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];\n\t\tend\n\tend\n\n\tfor (i = 0; i < RD_PORTS; i = i+1) begin\n\t\tif (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];\n\t\tif (RD_ARST[i])\n\t\t\tRD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];\n\tend\n\n\tLAST_RD_CLK <= RD_CLK;\n\tLAST_WR_CLK <= WR_CLK;\nend\n\nendmodule\n\n`endif\n\n// --------------------------------------------------------\n\nmodule \\$set_tag (A, SET, CLR, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$get_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$overwrite_tag (A, SET, CLR);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\ninput [WIDTH-1:0] SET;\ninput [WIDTH-1:0] CLR;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$original_tag (A, Y);\n\nparameter TAG = \"\";\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\nmodule \\$future_ff (A, Y);\n\nparameter WIDTH = 0;\n\ninput [WIDTH-1:0] A;\noutput [WIDTH-1:0] Y;\n\nassign Y = A;\n\nendmodule\n\n// --------------------------------------------------------\n\n(* noblackbox *)\nmodule \\$scopeinfo ();\n\nparameter TYPE = \"\";\n\nendmodule\n",
337
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  "smtmap.v": "(* techmap_celltype = \"$pmux\" *)\nmodule smt_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*(S_WIDTH+1)-1:0] C;\n\n\t\tassign C[WIDTH-1:0] = A;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1)\n\t\t\tassign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i];\n\t\tassign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH];\n\tendgenerate\nendmodule\n",
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- "techmap.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell technology mapper.\n *\n * This Verilog library contains the mapping of internal cells (e.g. $not with\n * variable bit width) to the internal logic cells (such as the single bit $_NOT_\n * gate). Usually this logic network is then mapped to the actual technology\n * using e.g. the \"abc\" pass.\n *\n * Note that this library does not map $mem cells. They must be mapped to logic\n * and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n * which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
342
+ "techmap.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * ---\n *\n * The internal logic cell technology mapper.\n *\n * This Verilog library contains the mapping of internal cells (e.g. $not with\n * variable bit width) to the internal logic cells (such as the single bit $_NOT_\n * gate). Usually this logic network is then mapped to the actual technology\n * using e.g. the \"abc\" pass.\n *\n * Note that this library does not map $mem cells. They must be mapped to logic\n * and $dff cells using the \"memory_map\" pass first. (Or map it to custom cells,\n * which is of course highly recommended for larger memories.)\n *\n */\n\n`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))\n`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))\n\n\n// --------------------------------------------------------\n// Use simplemap for trivial cell types\n// --------------------------------------------------------\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$not $and $or $xor $xnor\" *)\nmodule _90_simplemap_bool_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool\" *)\nmodule _90_simplemap_reduce_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$logic_not $logic_and $logic_or\" *)\nmodule _90_simplemap_logic_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$eq $eqx $ne $nex\" *)\nmodule _90_simplemap_compare_ops;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx\" *)\nmodule _90_simplemap_various;\nendmodule\n\n(* techmap_simplemap *)\n(* techmap_celltype = \"$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr\" *)\nmodule _90_simplemap_registers;\nendmodule\n\n\n// --------------------------------------------------------\n// Shift operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$shr $shl $sshl $sshr\" *)\nmodule _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tlocalparam shift_left = _TECHMAP_CELLTYPE_ == \"$shl\" || _TECHMAP_CELLTYPE_ == \"$sshl\";\n\tlocalparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == \"$sshr\";\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);\n\tlocalparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;\n\t\tbuffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};\n\n\t\tfor (i = 0; i < BB_WIDTH; i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (shift_left)\n\t\t\t\t\tbuffer = {buffer, (2**i)'b0};\n\t\t\t\telse if (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};\n\t\t\tend\n\tend\n\n\tassign Y = buffer;\nendmodule\n\n(* techmap_celltype = \"$shift $shiftx\" *)\nmodule _90_shift_shiftx (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\tparameter _TECHMAP_CELLTYPE_ = \"\";\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;\n\tparameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;\n\n\tlocalparam extbit = _TECHMAP_CELLTYPE_ == \"$shift\" ? 1'b0 : 1'bx;\n\twire a_padding = _TECHMAP_CELLTYPE_ == \"$shiftx\" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\n\n\tlocalparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);\n\tlocalparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);\n\n\twire [1023:0] _TECHMAP_DO_00_ = \"proc;;\";\n\twire [1023:0] _TECHMAP_DO_01_ = \"CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;\";\n\n\tinteger i;\n\t(* force_downto *)\n\treg [WIDTH-1:0] buffer;\n\treg overflow;\n\n\talways @* begin\n\t\toverflow = 0;\n\t\tbuffer = {WIDTH{extbit}};\n\t\tbuffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};\n\t\tbuffer[A_WIDTH-1:0] = A;\n\n\t\tif (B_WIDTH > BB_WIDTH) begin\n\t\t\tif (B_SIGNED) begin\n\t\t\t\tfor (i = BB_WIDTH; i < B_WIDTH; i = i+1)\n\t\t\t\t\tif (B[i] != B[BB_WIDTH-1])\n\t\t\t\t\t\toverflow = 1;\n\t\t\tend else\n\t\t\t\toverflow = |B[B_WIDTH-1:BB_WIDTH];\n\t\t\tif (overflow)\n\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\tend\n\n\t\tif (B_SIGNED && B[BB_WIDTH-1])\n\t\t\tbuffer = {buffer, {2**(BB_WIDTH-1){extbit}}};\n\n\t\tfor (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)\n\t\t\tif (B[i]) begin\n\t\t\t\tif (2**i < WIDTH)\n\t\t\t\t\tbuffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};\n\t\t\t\telse\n\t\t\t\t\tbuffer = {WIDTH{extbit}};\n\t\t\tend\n\tend\n\tassign Y = buffer;\nendmodule\n\n\n// --------------------------------------------------------\n// Arithmetic operators\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$fa\" *)\nmodule _90_fa (A, B, C, X, Y);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B, C;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] X, Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] t1, t2, t3;\n\n\tassign t1 = A ^ B, t2 = A & B, t3 = C & t1;\n\tassign Y = t1 ^ C, X = t2 | t3;\nendmodule\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _90_lcu_brent_kung (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\tinteger i, j;\n\t(* force_downto *)\n\treg [WIDTH-1:0] p, g;\n\n\twire [1023:0] _TECHMAP_DO_ = \"proc; opt -fast\";\n\n\talways @* begin\n\t\tp = P;\n\t\tg = G;\n\n\t\t// in almost all cases CI will be constant zero\n\t\tg[0] = g[0] | (p[0] & CI);\n\n\t\t// [[CITE]] Brent Kung Adder\n\t\t// R. P. Brent and H. T. Kung, \"A Regular Layout for Parallel Adders\",\n\t\t// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982\n\n\t\t// Main tree\n\t\tfor (i = 1; i <= $clog2(WIDTH); i = i+1) begin\n\t\t\tfor (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\n\t\t// Inverse tree\n\t\tfor (i = $clog2(WIDTH); i > 0; i = i-1) begin\n\t\t\tfor (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin\n\t\t\t\tg[j] = g[j] | p[j] & g[j - 2**(i-1)];\n\t\t\t\tp[j] = p[j] & p[j - 2**(i-1)];\n\t\t\tend\n\t\tend\n\tend\n\n\tassign CO = g;\nendmodule\n\n(* techmap_celltype = \"$alu\" *)\nmodule _90_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t\\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));\n\n\tassign X = AA ^ BB;\n\tassign Y = X ^ {CO, CI};\nendmodule\n\n(* techmap_maccmap *)\n(* techmap_celltype = \"$macc\" *)\nmodule _90_macc;\nendmodule\n\n(* techmap_wrap = \"alumacc\" *)\n(* techmap_celltype = \"$lt $le $ge $gt $add $sub $neg $mul\" *)\nmodule _90_alumacc;\nendmodule\n\n\n// --------------------------------------------------------\n// Divide and Modulo\n// --------------------------------------------------------\n\nmodule \\$__div_mod_u (A, B, Y, R);\n\tparameter WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A, B;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH*WIDTH-1:0] chaindata;\n\tassign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];\n\n\tgenvar i;\n\tgenerate begin\n\t\tfor (i = 0; i < WIDTH; i=i+1) begin:stage\n\t\t\t(* force_downto *)\n\t\t\twire [WIDTH-1:0] stage_in;\n\n\t\t\tif (i == 0) begin:cp\n\t\t\t\tassign stage_in = A;\n\t\t\tend else begin:cp\n\t\t\t\tassign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];\n\t\t\tend\n\n\t\t\tassign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};\n\t\t\tassign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;\n\t\tend\n\tend endgenerate\nendmodule\n\n// truncating signed division/modulo\nmodule \\$__div_mod_trunc (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;\n\tassign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\nendmodule\n\n(* techmap_celltype = \"$div\" *)\nmodule _90_div (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$mod\" *)\nmodule _90_mod (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_trunc #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n// flooring signed division/modulo\nmodule \\$__div_mod_floor (A, B, Y, R);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\tlocalparam WIDTH =\n\t\t\tA_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :\n\t\t\tB_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;\n\n\tinput [A_WIDTH-1:0] A;\n\tinput [B_WIDTH-1:0] B;\n\toutput [Y_WIDTH-1:0] Y, R;\n\n\twire [WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\twire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;\n\tassign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;\n\tassign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;\n\n\t\\$__div_mod_u #(\n\t\t.WIDTH(WIDTH)\n\t) div_mod_u (\n\t\t.A(A_buf_u),\n\t\t.B(B_buf_u),\n\t\t.Y(Y_u),\n\t\t.R(R_u)\n\t);\n\n\t// For negative results, if there was a remainder, subtract one to turn\n\t// the round towards 0 into a round towards -inf\n\tassign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;\n\n\t// truncating modulo\n\tassign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;\n\t// Flooring modulo differs from truncating modulo only if it is nonzero and\n\t// A and B have different signs - then `floor - trunc = B`\n\tassign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;\nendmodule\n\n(* techmap_celltype = \"$divfloor\" *)\nmodule _90_divfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.Y(Y)\n\t);\nendmodule\n\n(* techmap_celltype = \"$modfloor\" *)\nmodule _90_modfloor (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\t\\$__div_mod_floor #(\n\t\t.A_SIGNED(A_SIGNED),\n\t\t.B_SIGNED(B_SIGNED),\n\t\t.A_WIDTH(A_WIDTH),\n\t\t.B_WIDTH(B_WIDTH),\n\t\t.Y_WIDTH(Y_WIDTH)\n\t) div_mod (\n\t\t.A(A),\n\t\t.B(B),\n\t\t.R(Y)\n\t);\nendmodule\n\n\n// --------------------------------------------------------\n// Power\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pow\" *)\nmodule _90_pow (A, B, Y);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] Y;\n\n\twire _TECHMAP_FAIL_ = 1;\nendmodule\n\n\n// --------------------------------------------------------\n// Parallel Multiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$pmux\" *)\nmodule _90_pmux (A, B, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [WIDTH*S_WIDTH-1:0] B;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [WIDTH-1:0] Y;\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] Y_B;\n\n\tgenvar i, j;\n\tgenerate\n\t\t(* force_downto *)\n\t\twire [WIDTH*S_WIDTH-1:0] B_AND_S;\n\t\tfor (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND\n\t\t\tassign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};\n\t\tend:B_AND\n\t\tfor (i = 0; i < WIDTH; i = i + 1) begin:B_OR\n\t\t\t(* force_downto *)\n\t\t\twire [S_WIDTH-1:0] B_AND_BITS;\n\t\t\tfor (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT\n\t\t\t\tassign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];\n\t\t\tend:B_AND_BITS_COLLECT\n\t\t\tassign Y_B[i] = |B_AND_BITS;\n\t\tend:B_OR\n\tendgenerate\n\n\tassign Y = |S ? Y_B : A;\nendmodule\n\n// --------------------------------------------------------\n// Demultiplexers\n// --------------------------------------------------------\n\n(* techmap_celltype = \"$demux\" *)\nmodule _90_demux (A, S, Y);\n\tparameter WIDTH = 1;\n\tparameter S_WIDTH = 1;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [S_WIDTH-1:0] S;\n\t(* force_downto *)\n\toutput [(WIDTH << S_WIDTH)-1:0] Y;\n\n\tgenerate\n\t\tif (S_WIDTH == 0) begin\n\t\t\tassign Y = A;\n\t\tend else if (S_WIDTH == 1) begin\n\t\t\tassign Y[0+:WIDTH] = S ? 0 : A;\n\t\t\tassign Y[WIDTH+:WIDTH] = S ? A : 0;\n\t\tend else begin\n\t\t\tlocalparam SPLIT = S_WIDTH / 2;\n\t\t\twire [(1 << (S_WIDTH-SPLIT))-1:0] YH;\n\t\t\twire [(1 << SPLIT)-1:0] YL;\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));\n\t\t\t$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));\n\t\t\tgenvar i;\n\t\t\tfor (i = 0; i < (1 << S_WIDTH); i = i + 1) begin\n\t\t\t\tlocalparam [S_WIDTH-1:0] IDX = i;\n\t\t\t\tassign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;\n\t\t\tend\n\t\tend\n\tendgenerate\nendmodule\n\n\n// --------------------------------------------------------\n// LUTs\n// --------------------------------------------------------\n\n`ifndef NOLUT\n(* techmap_simplemap *)\n(* techmap_celltype = \"$lut $sop\" *)\nmodule _90_lut;\nendmodule\n`endif\n\n",
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  "abc9_model.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * 2019 Eddie Hung <eddie@fpgeh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n\n// Box containing MUXF7.[AB] + MUXF8,\n// Necessary to make these an atomic unit so that\n// ABC cannot optimise just one of the MUXF7 away\n// and expect to save on its delay\n(* abc9_box, lib_whitebox *)\nmodule \\$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);\n assign O = S1 ? (S0 ? I3 : I2)\n : (S0 ? I1 : I0);\n specify\n (I0 => O) = 294;\n (I1 => O) = 297;\n (I2 => O) = 311;\n (I3 => O) = 317;\n (S0 => O) = 390;\n (S1 => O) = 273;\n endspecify\nendmodule\n",
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  "arith_map.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// ============================================================================\n// LCU\n\n(* techmap_celltype = \"$lcu\" *)\nmodule _80_xilinx_lcu (P, G, CI, CO);\n\tparameter WIDTH = 2;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] P, G;\n\tinput CI;\n\n\t(* force_downto *)\n\toutput [WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = WIDTH <= 2;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [WIDTH-1:0] S = P & ~G;\n\n\tgenerate for (i = 0; i < WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(G[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\tend endgenerate\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH = MAX_WIDTH - WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign CO = C;\n\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI (1'd0),\n\t\t\t.DI (GG[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4]),\n\t\t\t);\n\t\tend else begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI (C [i*4 - 1]),\n\t\t\t.DI (GG[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4]),\n\t\t\t);\n\t\tend\n\tend endgenerate\nend endgenerate\n\nendmodule\n\n\n// ============================================================================\n// ALU\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_xilinx_alu (A, B, CI, BI, X, Y, CO);\n\tparameter A_SIGNED = 0;\n\tparameter B_SIGNED = 0;\n\tparameter A_WIDTH = 1;\n\tparameter B_WIDTH = 1;\n\tparameter Y_WIDTH = 1;\n\tparameter _TECHMAP_CONSTVAL_CI_ = 0;\n\tparameter _TECHMAP_CONSTMSK_CI_ = 0;\n\n\t(* force_downto *)\n\tinput [A_WIDTH-1:0] A;\n\t(* force_downto *)\n\tinput [B_WIDTH-1:0] B;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] X, Y;\n\n\tinput CI, BI;\n\t(* force_downto *)\n\toutput [Y_WIDTH-1:0] CO;\n\n\twire _TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] A_buf, B_buf;\n\t\\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n\t\\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] AA = A_buf;\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;\n\n\tgenvar i;\n\ngenerate if (`LUT_SIZE == 4) begin\n\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] C = {CO, CI};\n\t(* force_downto *)\n\twire [Y_WIDTH-1:0] S = {AA ^ BB};\n\n\tgenvar i;\n\tgenerate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n\t\tMUXCY muxcy (\n\t\t\t.CI(C[i]),\n\t\t\t.DI(AA[i]),\n\t\t\t.S(S[i]),\n\t\t\t.O(CO[i])\n\t\t);\n\t\tXORCY xorcy (\n\t\t\t.CI(C[i]),\n\t\t\t.LI(S[i]),\n\t\t\t.O(Y[i])\n\t\t);\n\tend endgenerate\n\n\tassign X = S;\n\nend else begin\n\n\tlocalparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;\n\tlocalparam MAX_WIDTH = CARRY4_COUNT * 4;\n\tlocalparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};\n\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] O;\n\t(* force_downto *)\n\twire [MAX_WIDTH-1:0] C;\n\tassign Y = O, CO = C;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice\n\t\tif (i == 0) begin\n\t\t\tCARRY4 carry4\n\t\t\t(\n\t\t\t.CYINIT(CI),\n\t\t\t.CI (1'd0),\n\t\t\t.DI (DI[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.O (O [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4])\n\t\t\t);\n\t\tend else begin\n\t\t CARRY4 carry4\n\t\t (\n\t\t\t.CYINIT(1'd0),\n\t\t\t.CI (C [i*4 - 1]),\n\t\t\t.DI (DI[i*4 +: 4]),\n\t\t\t.S (S [i*4 +: 4]),\n\t\t\t.O (O [i*4 +: 4]),\n\t\t\t.CO (C [i*4 +: 4])\n\t\t );\n\t\tend\n\tend endgenerate\n\n\tassign X = S;\n\nend endgenerate\nendmodule\n\n",